From 7231a4e2102e85b66eb377d246d65c1150a6115f Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Sun, 23 Mar 2014 22:30:53 +1000 Subject: [PATCH] Compile fix. --- .../Generated_Source/PSoC5/cybootloader.c | 586 +- software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 226302 -> 226302 bytes .../ARM_GCC_473/Release/.deps/ARM_C_FILE.P | 170 - .../ARM_GCC_473/Release/.deps/C_FILE.P | 70 - .../Release/.deps/GNU_ARM_ASM_FILE.P | 10 - .../CortexM3/ARM_GCC_473/Release/BL.lst | 8147 -------- .../CortexM3/ARM_GCC_473/Release/BL.o | Bin 22004 -> 0 bytes .../CortexM3/ARM_GCC_473/Release/Cm3Start.lst | 2082 -- .../CortexM3/ARM_GCC_473/Release/Cm3Start.o | Bin 7956 -> 0 bytes .../ARM_GCC_473/Release/CyBootAsmGnu.lst | 12936 ------------- .../ARM_GCC_473/Release/CyBootAsmGnu.o | Bin 435620 -> 0 bytes .../CortexM3/ARM_GCC_473/Release/CyDmac.lst | 6089 ------ .../CortexM3/ARM_GCC_473/Release/CyDmac.o | Bin 22040 -> 0 bytes .../CortexM3/ARM_GCC_473/Release/CyFlash.lst | 4249 ---- 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100755 software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/warp_dependencies.txt diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c index 2292dca..32543d5 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c @@ -31,18 +31,18 @@ const uint8 cy_bootloader[] = { 0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u, 0x61u, 0x01u, 0x00u, 0x00u, 0x61u, 0x01u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u, - 0x02u, 0x60u, 0x00u, 0xF0u, 0x71u, 0xFCu, 0x00u, 0xF0u, + 0x02u, 0x60u, 0x00u, 0xF0u, 0x7Bu, 0xFCu, 0x00u, 0xF0u, 0xA1u, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u, 0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu, 0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u, 0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u, 0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu, - 0x00u, 0x00u, 0x00u, 0x00u, 0xF4u, 0x1Fu, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x20u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u, 0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u, 0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u, 0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u, - 0xF4u, 0x1Fu, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu, + 0x0Cu, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x36u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x22u, 0x10u, @@ -70,7 +70,7 @@ const uint8 cy_bootloader[] = { 0x03u, 0xF8u, 0x0Du, 0x0Cu, 0x13u, 0xF8u, 0x0Eu, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Eu, 0x2Cu, 0x13u, 0xF8u, 0x0Fu, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, - 0x03u, 0xF8u, 0x0Fu, 0x1Cu, 0x00u, 0xF0u, 0x94u, 0xFBu, + 0x03u, 0xF8u, 0x0Fu, 0x1Cu, 0x00u, 0xF0u, 0x9Eu, 0xFBu, 0xFEu, 0xE7u, 0x00u, 0xBFu, 0x00u, 0x50u, 0x00u, 0x40u, 0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u, 0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u, @@ -80,9 +80,9 @@ const uint8 cy_bootloader[] = { 0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu, 0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u, 0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u, - 0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0xEAu, 0xFEu, + 0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0xF6u, 0xFEu, 0xFFu, 0xF7u, 0x6Au, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu, - 0x00u, 0x00u, 0x00u, 0x00u, 0x38u, 0x22u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x22u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u, 0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u, 0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au, @@ -96,232 +96,235 @@ const uint8 cy_bootloader[] = { 0x61u, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu, 0xBCu, 0x76u, 0x00u, 0x40u, 0x04u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xC1u, 0xFFu, 0x1Fu, - 0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Au, 0x4Bu, 0x01u, 0x22u, + 0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Fu, 0x4Bu, 0x01u, 0x22u, 0xA3u, 0xF5u, 0xA0u, 0x61u, 0xA1u, 0xF5u, 0x80u, 0x75u, - 0x06u, 0x20u, 0x52u, 0x24u, 0x57u, 0x4Eu, 0x1Au, 0x70u, - 0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x56u, 0x4Bu, - 0x56u, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u, + 0x06u, 0x20u, 0x52u, 0x24u, 0x5Cu, 0x4Eu, 0x1Au, 0x70u, + 0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x5Bu, 0x4Bu, + 0x5Bu, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u, 0x51u, 0x21u, 0x17u, 0x70u, 0x19u, 0x25u, 0x18u, 0x80u, - 0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x52u, 0x4Eu, + 0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x57u, 0x4Eu, 0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u, 0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u, - 0x63u, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u, - 0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x4Bu, 0x48u, - 0x4Bu, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u, - 0x4Au, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u, + 0x6Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u, + 0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x50u, 0x48u, + 0x50u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u, + 0x4Fu, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u, 0x03u, 0x80u, 0x01u, 0x70u, 0x3Eu, 0x70u, 0xBAu, 0x70u, 0x06u, 0x70u, 0x46u, 0x71u, 0x00u, 0xF8u, 0x03u, 0x4Cu, 0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u, - 0x00u, 0xE0u, 0xFEu, 0xE7u, 0x42u, 0x4Fu, 0x06u, 0x21u, + 0x00u, 0xE0u, 0xFEu, 0xE7u, 0x47u, 0x4Fu, 0x06u, 0x21u, 0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u, - 0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0x91u, 0xFEu, + 0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0x9Du, 0xFEu, 0x08u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u, - 0x3Cu, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u, + 0x41u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u, 0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu, 0x41u, 0x04u, 0xD5u, 0xB2u, 0xAEu, 0x42u, 0x09u, 0xD0u, 0x04u, 0xEBu, 0x42u, 0x0Cu, 0x14u, 0xF8u, 0x12u, 0x50u, 0x9Cu, 0xF8u, 0x01u, 0xE0u, 0x01u, 0x32u, 0x05u, 0xF8u, 0x07u, 0xE0u, 0xF2u, 0xE7u, 0x04u, 0x33u, 0xC0u, 0xB2u, - 0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x30u, 0x4Cu, + 0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x35u, 0x4Cu, 0x22u, 0x78u, 0x42u, 0xF0u, 0x02u, 0x00u, 0x20u, 0x70u, - 0x21u, 0x7Cu, 0x2Eu, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u, - 0x2Du, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u, - 0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x2Bu, 0x4Au, - 0x43u, 0xF0u, 0x10u, 0x04u, 0x2Au, 0x4Bu, 0x04u, 0x70u, + 0x21u, 0x7Cu, 0x33u, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u, + 0x32u, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u, + 0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x30u, 0x4Au, + 0x43u, 0xF0u, 0x10u, 0x04u, 0x2Fu, 0x4Bu, 0x04u, 0x70u, 0x18u, 0x68u, 0x5Cu, 0x68u, 0x10u, 0x60u, 0x54u, 0x60u, - 0x1Au, 0x46u, 0x28u, 0x48u, 0x52u, 0xF8u, 0x08u, 0x4Fu, + 0x1Au, 0x46u, 0x2Du, 0x48u, 0x52u, 0xF8u, 0x08u, 0x4Fu, 0x04u, 0x60u, 0x54u, 0x68u, 0x12u, 0x89u, 0x44u, 0x60u, 0x02u, 0x81u, 0x1Au, 0x46u, 0x52u, 0xF8u, 0x12u, 0x4Fu, - 0x52u, 0x68u, 0x40u, 0xF8u, 0xAEu, 0x4Cu, 0x40u, 0xF8u, - 0xAAu, 0x2Cu, 0x53u, 0xF8u, 0x1Au, 0x0Fu, 0x20u, 0x4Au, - 0x5Bu, 0x68u, 0x10u, 0x60u, 0x1Fu, 0x48u, 0x53u, 0x60u, - 0x02u, 0x78u, 0x42u, 0xF0u, 0x08u, 0x03u, 0x03u, 0x70u, - 0x1Du, 0x48u, 0x1Eu, 0x4Au, 0x03u, 0x78u, 0x03u, 0xF0u, - 0x07u, 0x00u, 0x1Bu, 0x09u, 0x10u, 0x70u, 0x53u, 0x70u, - 0x1Bu, 0x4Au, 0x44u, 0x20u, 0x10u, 0x70u, 0x1Bu, 0x4Au, - 0x0Bu, 0x46u, 0x0Cu, 0x31u, 0x53u, 0xF8u, 0x04u, 0x0Bu, - 0x8Bu, 0x42u, 0x42u, 0xF8u, 0x04u, 0x0Bu, 0xF9u, 0xD1u, - 0x19u, 0x88u, 0x11u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0xBFu, - 0x00u, 0x48u, 0x00u, 0x40u, 0x0Fu, 0x01u, 0x00u, 0x49u, - 0x22u, 0x42u, 0x00u, 0x40u, 0xA1u, 0x46u, 0x00u, 0x40u, - 0x25u, 0x42u, 0x00u, 0x40u, 0x04u, 0x40u, 0x00u, 0x40u, - 0x06u, 0x40u, 0x00u, 0x40u, 0xE8u, 0x46u, 0x00u, 0x40u, - 0xF8u, 0x1Fu, 0x00u, 0x00u, 0x28u, 0x20u, 0x00u, 0x00u, - 0x03u, 0x50u, 0x01u, 0x40u, 0xC2u, 0x43u, 0x00u, 0x40u, - 0xA0u, 0x43u, 0x00u, 0x40u, 0x02u, 0x51u, 0x00u, 0x40u, - 0x84u, 0x20u, 0x00u, 0x00u, 0xF0u, 0x51u, 0x00u, 0x40u, - 0x62u, 0x51u, 0x00u, 0x40u, 0x22u, 0x43u, 0x00u, 0x40u, - 0xCFu, 0x01u, 0x00u, 0x49u, 0x6Eu, 0x58u, 0x00u, 0x40u, - 0x76u, 0x58u, 0x00u, 0x40u, 0xB0u, 0x43u, 0x00u, 0x40u, - 0x00u, 0x47u, 0x00u, 0x00u, 0x43u, 0x1Eu, 0x10u, 0xB5u, - 0x02u, 0x46u, 0x06u, 0x2Bu, 0x0Du, 0xD8u, 0xDFu, 0xE8u, - 0x03u, 0xF0u, 0x06u, 0x0Eu, 0x23u, 0x04u, 0x08u, 0x0Au, - 0x21u, 0x00u, 0x16u, 0x48u, 0x08u, 0xE0u, 0x16u, 0x4Bu, - 0x1Bu, 0xE0u, 0x16u, 0x48u, 0x04u, 0xE0u, 0x16u, 0x48u, - 0x02u, 0xE0u, 0x00u, 0x20u, 0x00u, 0xE0u, 0x15u, 0x48u, - 0x41u, 0x78u, 0x00u, 0x78u, 0x41u, 0xEAu, 0x00u, 0x20u, - 0x02u, 0x2Au, 0x04u, 0xD0u, 0x03u, 0x2Au, 0x07u, 0xD0u, - 0x01u, 0x2Au, 0x15u, 0xD1u, 0x04u, 0xE0u, 0x02u, 0x02u, - 0x42u, 0xEAu, 0x10u, 0x23u, 0x98u, 0xB2u, 0x10u, 0xBDu, - 0x00u, 0xBAu, 0x10u, 0xBDu, 0x0Cu, 0x4Bu, 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0x6Au, 0xFDu, - 0x30u, 0xB1u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0x66u, 0xFDu, - 0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0x60u, 0xBDu, - 0x08u, 0xBDu, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u, + 0x40u, 0xF8u, 0xC0u, 0x4Cu, 0x54u, 0x68u, 0x12u, 0x89u, + 0x40u, 0xF8u, 0xBCu, 0x4Cu, 0x20u, 0xF8u, 0xB8u, 0x2Cu, + 0x1Au, 0x46u, 0x52u, 0xF8u, 0x1Cu, 0x4Fu, 0x52u, 0x68u, + 0x40u, 0xF8u, 0xAEu, 0x4Cu, 0x40u, 0xF8u, 0xAAu, 0x2Cu, + 0x53u, 0xF8u, 0x24u, 0x0Fu, 0x1Fu, 0x4Au, 0x5Bu, 0x68u, + 0x10u, 0x60u, 0x1Fu, 0x48u, 0x53u, 0x60u, 0x02u, 0x78u, + 0x42u, 0xF0u, 0x08u, 0x03u, 0x03u, 0x70u, 0x1Du, 0x48u, + 0x1Du, 0x4Au, 0x03u, 0x78u, 0x03u, 0xF0u, 0x07u, 0x00u, + 0x1Bu, 0x09u, 0x10u, 0x70u, 0x53u, 0x70u, 0x1Bu, 0x4Au, + 0x44u, 0x20u, 0x10u, 0x70u, 0x1Au, 0x4Au, 0x0Bu, 0x46u, + 0x0Cu, 0x31u, 0x53u, 0xF8u, 0x04u, 0x0Bu, 0x8Bu, 0x42u, + 0x42u, 0xF8u, 0x04u, 0x0Bu, 0xF9u, 0xD1u, 0x19u, 0x88u, + 0x11u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0x48u, 0x00u, 0x40u, + 0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u, 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0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u, + 0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u, + 0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu, + 0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u, + 0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u, + 0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u, + 0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u, + 0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u, + 0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u, + 0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u, + 0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u, + 0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu, + 0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u, + 0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u, + 0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u, + 0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u, + 0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u, + 0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u, + 0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u, + 0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u, + 0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u, + 0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu, + 0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u, + 0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u, + 0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du, + 0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u, + 0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au, + 0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u, + 0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u, + 0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u, + 0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u, + 0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u, + 0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u, + 0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu, + 0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu, + 0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u, + 0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u, + 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du, + 0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u, + 0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u, + 0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u, + 0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u, + 0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u, + 0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u, + 0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u, + 0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u, + 0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u, + 0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u, + 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u, + 0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u, + 0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu, + 0xCCu, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u, + 0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u, + 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u, + 0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, + 0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u, + 0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u, + 0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u, + 0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u, + 0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u, + 0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u, + 0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u, + 0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu, + 0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u, + 0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u, + 0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu, + 0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u, + 0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u, + 0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu, + 0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu, + 0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u, + 0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u, + 0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u, + 0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u, + 0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu, + 0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u, 0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u, 0xFCu, 0xAFu, 0x70u, 0x47u, 0xEFu, 0xF3u, 0x10u, 0x80u, @@ -506,9 +509,9 @@ const uint8 cy_bootloader[] = { 0x23u, 0xBEu, 0x00u, 0xBFu, 0xA5u, 0x43u, 0x00u, 0x40u, 0x9Du, 0x60u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u, 0x12u, 0x60u, 0x00u, 0x40u, 0xF8u, 0x51u, 0x00u, 0x40u, - 0x84u, 0x60u, 0x00u, 0x40u, 0xF3u, 0x15u, 0x00u, 0x00u, - 0xF1u, 0x15u, 0x00u, 0x00u, 0x31u, 0x14u, 0x00u, 0x00u, - 0x89u, 0x15u, 0x00u, 0x00u, 0xBDu, 0x15u, 0x00u, 0x00u, + 0x84u, 0x60u, 0x00u, 0x40u, 0x0Bu, 0x16u, 0x00u, 0x00u, + 0x09u, 0x16u, 0x00u, 0x00u, 0x49u, 0x14u, 0x00u, 0x00u, + 0xA1u, 0x15u, 0x00u, 0x00u, 0xD5u, 0x15u, 0x00u, 0x00u, 0x18u, 0x4Bu, 0x01u, 0x22u, 0x10u, 0xB5u, 0x1Au, 0x70u, 0x17u, 0x4Bu, 0x4Fu, 0xF4u, 0x00u, 0x04u, 0x1Cu, 0x60u, 0x4Fu, 0xF0u, 0x80u, 0x74u, 0x1Cu, 0x60u, 0x1Au, 0x60u, @@ -822,7 +825,7 @@ const uint8 cy_bootloader[] = { 0x04u, 0x4Bu, 0x05u, 0x49u, 0x1Au, 0x78u, 0x01u, 0xEBu, 0xC2u, 0x03u, 0x5Au, 0x68u, 0x02u, 0xEBu, 0xC0u, 0x00u, 0xC0u, 0x68u, 0x70u, 0x47u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu, - 0xB0u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu, + 0xD4u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu, 0x1Au, 0x78u, 0x00u, 0x2Au, 0x74u, 0xD0u, 0x18u, 0x78u, 0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u, 0xE8u, 0xFFu, 0xC3u, 0x68u, 0x05u, 0x7Au, 0x08u, 0x33u, 0x00u, 0x20u, @@ -1009,9 +1012,9 @@ const uint8 cy_bootloader[] = { 0x08u, 0x70u, 0x32u, 0xE0u, 0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u, 0x03u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu, - 0xB0u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u, - 0x76u, 0x21u, 0x00u, 0x00u, 0xF2u, 0x21u, 0x00u, 0x00u, - 0x6Cu, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u, + 0xD4u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u, + 0x9Au, 0x21u, 0x00u, 0x00u, 0x16u, 0x22u, 0x00u, 0x00u, + 0x90u, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu, @@ -1039,92 +1042,94 @@ const uint8 cy_bootloader[] = { 0x0Eu, 0x4Bu, 0x00u, 0x24u, 0xE8u, 0x1Au, 0x85u, 0x10u, 0xACu, 0x42u, 0x05u, 0xD0u, 0x0Bu, 0x49u, 0x51u, 0xF8u, 0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, - 0x00u, 0xF0u, 0x34u, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au, + 0x00u, 0xF0u, 0x3Au, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au, 0x54u, 0x1Au, 0xA5u, 0x10u, 0x00u, 0x24u, 0xACu, 0x42u, 0x05u, 0xD0u, 0x05u, 0x4Bu, 0x53u, 0xF8u, 0x24u, 0x00u, 0x80u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, 0x38u, 0xBDu, - 0x10u, 0x22u, 0x00u, 0x00u, 0x10u, 0x22u, 0x00u, 0x00u, - 0x10u, 0x22u, 0x00u, 0x00u, 0x18u, 0x22u, 0x00u, 0x00u, + 0x34u, 0x22u, 0x00u, 0x00u, 0x34u, 0x22u, 0x00u, 0x00u, + 0x34u, 0x22u, 0x00u, 0x00u, 0x3Cu, 0x22u, 0x00u, 0x00u, 0x10u, 0xB5u, 0x00u, 0x23u, 0x93u, 0x42u, 0x03u, 0xD0u, 0xCCu, 0x5Cu, 0xC4u, 0x54u, 0x01u, 0x33u, 0xF9u, 0xE7u, 0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u, 0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u, - 0x70u, 0x47u, 0x00u, 0x00u, 0x58u, 0x22u, 0x00u, 0x00u, - 0x81u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x10u, 0x51u, 0x00u, 0x40u, 0x30u, 0x00u, 0x50u, 0x51u, + 0x70u, 0x47u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u, + 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x10u, 0x51u, 0x00u, 0x40u, 0x20u, 0x00u, 0x50u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u, 0x00u, 0x40u, 0x01u, 0x40u, 0x00u, 0x0Au, 0x00u, 0x4Cu, 0x01u, 0x40u, 0x00u, 0x02u, 0x00u, 0x50u, 0x01u, 0x40u, 0x20u, 0x00u, - 0x01u, 0x45u, 0x00u, 0x40u, 0x01u, 0x52u, 0x00u, 0x40u, + 0x01u, 0x45u, 0x00u, 0x40u, 0x02u, 0x52u, 0x00u, 0x40u, 0x01u, 0x17u, 0x01u, 0x40u, 0x01u, 0x19u, 0x01u, 0x40u, 0x03u, 0x40u, 0x01u, 0x40u, 0x02u, 0x41u, 0x01u, 0x40u, 0x02u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u, 0x03u, 0x47u, 0x01u, 0x40u, 0x03u, 0x48u, 0x01u, 0x40u, 0x02u, 0x4Cu, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u, - 0x7Eu, 0x02u, 0x7Cu, 0x40u, 0xEEu, 0x0Au, 0xEEu, 0x0Au, - 0x33u, 0x80u, 0x36u, 0x40u, 0xCCu, 0x30u, 0xA6u, 0x40u, - 0xA7u, 0x80u, 0xA6u, 0x40u, 0xA7u, 0x80u, 0xA6u, 0x40u, - 0xA7u, 0x80u, 0x08u, 0x08u, 0x0Fu, 0x40u, 0xC2u, 0x0Cu, - 0xAEu, 0x40u, 0xAFu, 0x80u, 0xEEu, 0x50u, 0xACu, 0x08u, - 0xAFu, 0x40u, 0x00u, 0x0Au, 0x00u, 0xFFu, 0xFFu, 0x00u, + 0x7Eu, 0x02u, 0x1Cu, 0x3Eu, 0x7Cu, 0x40u, 0xEEu, 0x0Au, + 0xEEu, 0x0Au, 0x33u, 0x80u, 0x36u, 0x40u, 0xCCu, 0x30u, + 0xA6u, 0x40u, 0xA7u, 0x80u, 0xA6u, 0x40u, 0xA7u, 0x80u, + 0xA6u, 0x40u, 0xA7u, 0x80u, 0x08u, 0x08u, 0x0Fu, 0x40u, + 0xC2u, 0x0Cu, 0xAEu, 0x40u, 0xAFu, 0x80u, 0xEEu, 0x50u, + 0xACu, 0x08u, 0xAFu, 0x40u, 0x00u, 0x0Au, 0x00u, 0xFFu, + 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, + 0x3Eu, 0x00u, 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x69u, 0x30u, 0x13u, 0x2Eu, + 0x00u, 0x14u, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u, + 0xDCu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x16u, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0xECu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0xEDu, 0x21u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, + 0x0Eu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x20u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x0Cu, 0x21u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, + 0x82u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x28u, 0x21u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x21u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0xFCu, - 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Fu, - 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x14u, 0x01u, 0x01u, - 0x01u, 0x00u, 0x00u, 0x00u, 0xB8u, 0x20u, 0x00u, 0x00u, - 0x01u, 0x00u, 0x00u, 0x00u, 0xF2u, 0x21u, 0x00u, 0x00u, - 0x01u, 0x00u, 0x00u, 0x00u, 0xC8u, 0x20u, 0x00u, 0x00u, - 0x01u, 0x00u, 0x00u, 0x00u, 0xC9u, 0x21u, 0x00u, 0x00u, - 0x02u, 0x00u, 0x00u, 0x00u, 0xEAu, 0x20u, 0x00u, 0x00u, - 0x01u, 0x00u, 0x00u, 0x00u, 0xFCu, 0x20u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xE8u, 0x20u, 0x00u, 0x00u, - 0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x03u, 0x40u, 0x00u, - 0x03u, 0x00u, 0x00u, 0x00u, 0x82u, 0x03u, 0x40u, 0x00u, - 0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, - 0x04u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x38u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x2Cu, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, - 0x44u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, - 0xDBu, 0x21u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u, - 0x33u, 0xC2u, 0xFFu, 0x1Fu, 0x74u, 0xC2u, 0xFFu, 0x1Fu, - 0x41u, 0x00u, 0x00u, 0x00u, 0xF2u, 0xC1u, 0xFFu, 0x1Fu, - 0xEEu, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u, - 0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0xA1u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x68u, 0x21u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x21u, 0x00u, 0x00u, + 0x41u, 0x00u, 0x00u, 0x00u, 0x33u, 0xC2u, 0xFFu, 0x1Fu, + 0x74u, 0xC2u, 0xFFu, 0x1Fu, 0x41u, 0x00u, 0x00u, 0x00u, + 0xF2u, 0xC1u, 0xFFu, 0x1Fu, 0xEEu, 0xC1u, 0xFFu, 0x1Fu, + 0x24u, 0x00u, 0x05u, 0x01u, 0x09u, 0x00u, 0xA1u, 0x00u, + 0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0x15u, 0x00u, + 0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x91u, 0x02u, 0x09u, 0x00u, 0x15u, 0x00u, 0x25u, 0xFFu, 0x75u, 0x08u, - 0x95u, 0x40u, 0x91u, 0x02u, 0x09u, 0x00u, 0x15u, 0x00u, - 0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x81u, 0x02u, - 0xC0u, 0xC0u, 0x00u, 0x00u, 0x0Au, 0x03u, 0x30u, 0x00u, - 0x30u, 0x00u, 0x30u, 0x00u, 0x31u, 0x00u, 0x04u, 0x03u, - 0x09u, 0x04u, 0x2Cu, 0x03u, 0x43u, 0x00u, 0x79u, 0x00u, - 0x70u, 0x00u, 0x72u, 0x00u, 0x65u, 0x00u, 0x73u, 0x00u, - 0x73u, 0x00u, 0x20u, 0x00u, 0x53u, 0x00u, 0x65u, 0x00u, - 0x6Du, 0x00u, 0x69u, 0x00u, 0x63u, 0x00u, 0x6Fu, 0x00u, - 0x6Eu, 0x00u, 0x64u, 0x00u, 0x75u, 0x00u, 0x63u, 0x00u, - 0x74u, 0x00u, 0x6Fu, 0x00u, 0x72u, 0x00u, 0x22u, 0x03u, - 0x50u, 0x00u, 0x53u, 0x00u, 0x6Fu, 0x00u, 0x43u, 0x00u, - 0x33u, 0x00u, 0x20u, 0x00u, 0x42u, 0x00u, 0x6Fu, 0x00u, - 0x6Fu, 0x00u, 0x74u, 0x00u, 0x6Cu, 0x00u, 0x6Fu, 0x00u, - 0x61u, 0x00u, 0x64u, 0x00u, 0x65u, 0x00u, 0x72u, 0x00u, - 0x00u, 0x09u, 0x02u, 0x29u, 0x00u, 0x01u, 0x01u, 0x00u, - 0x80u, 0x00u, 0x09u, 0x04u, 0x00u, 0x00u, 0x02u, 0x03u, - 0x00u, 0x00u, 0x02u, 0x09u, 0x21u, 0x11u, 0x01u, 0x00u, - 0x01u, 0x22u, 0x24u, 0x00u, 0x07u, 0x05u, 0x01u, 0x03u, - 0x40u, 0x00u, 0x01u, 0x07u, 0x05u, 0x82u, 0x03u, 0x40u, - 0x00u, 0x01u, 0x12u, 0x01u, 0x00u, 0x02u, 0x00u, 0x00u, - 0x00u, 0x08u, 0xB4u, 0x04u, 0x1Du, 0xB7u, 0x01u, 0x30u, - 0x01u, 0x02u, 0x80u, 0x01u, 0xF8u, 0xB5u, 0x00u, 0xBFu, - 0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u, - 0x51u, 0x00u, 0x00u, 0x00u, 0xB9u, 0x01u, 0x00u, 0x00u, + 0x95u, 0x40u, 0x81u, 0x02u, 0xC0u, 0xC0u, 0x00u, 0x00u, + 0x0Au, 0x03u, 0x30u, 0x00u, 0x30u, 0x00u, 0x30u, 0x00u, + 0x31u, 0x00u, 0x04u, 0x03u, 0x09u, 0x04u, 0x2Cu, 0x03u, + 0x43u, 0x00u, 0x79u, 0x00u, 0x70u, 0x00u, 0x72u, 0x00u, + 0x65u, 0x00u, 0x73u, 0x00u, 0x73u, 0x00u, 0x20u, 0x00u, + 0x53u, 0x00u, 0x65u, 0x00u, 0x6Du, 0x00u, 0x69u, 0x00u, + 0x63u, 0x00u, 0x6Fu, 0x00u, 0x6Eu, 0x00u, 0x64u, 0x00u, + 0x75u, 0x00u, 0x63u, 0x00u, 0x74u, 0x00u, 0x6Fu, 0x00u, + 0x72u, 0x00u, 0x22u, 0x03u, 0x50u, 0x00u, 0x53u, 0x00u, + 0x6Fu, 0x00u, 0x43u, 0x00u, 0x33u, 0x00u, 0x20u, 0x00u, + 0x42u, 0x00u, 0x6Fu, 0x00u, 0x6Fu, 0x00u, 0x74u, 0x00u, + 0x6Cu, 0x00u, 0x6Fu, 0x00u, 0x61u, 0x00u, 0x64u, 0x00u, + 0x65u, 0x00u, 0x72u, 0x00u, 0x00u, 0x09u, 0x02u, 0x29u, + 0x00u, 0x01u, 0x01u, 0x00u, 0x80u, 0x00u, 0x09u, 0x04u, + 0x00u, 0x00u, 0x02u, 0x03u, 0x00u, 0x00u, 0x02u, 0x09u, + 0x21u, 0x11u, 0x01u, 0x00u, 0x01u, 0x22u, 0x24u, 0x00u, + 0x07u, 0x05u, 0x01u, 0x03u, 0x40u, 0x00u, 0x01u, 0x07u, + 0x05u, 0x82u, 0x03u, 0x40u, 0x00u, 0x01u, 0x12u, 0x01u, + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x08u, 0xB4u, 0x04u, + 0x1Du, 0xB7u, 0x01u, 0x30u, 0x01u, 0x02u, 0x80u, 0x01u, 0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu, - 0x9Eu, 0x46u, 0x70u, 0x47u, 0x2Du, 0x00u, 0x00u, 0x00u, - 0x38u, 0x22u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu, - 0x20u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xECu, 0x1Fu, 0x00u, 0x00u, - 0xF0u, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du, + 0x9Eu, 0x46u, 0x70u, 0x47u, 0x51u, 0x00u, 0x00u, 0x00u, + 0xB9u, 0x01u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu, + 0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u, + 0x2Du, 0x00u, 0x00u, 0x00u, 0x60u, 0x22u, 0x00u, 0x00u, + 0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x20u, 0x00u, 0x00u, 0x00u, + 0x50u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x20u, 0x00u, 0x00u, + 0x08u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du, 0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, @@ -1142,11 +1147,6 @@ const uint8 cy_bootloader[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; #if defined(__GNUC__) || defined(__ARMCC_VERSION) @@ -1158,7 +1158,7 @@ __attribute__ ((__section__(".cymeta"), used)) #endif const uint8 cy_metadata[] = { 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, - 0x2Eu, 0x1Fu, 0x88u, 0x6Bu}; + 0x2Eu, 0x1Fu, 0x8Cu, 0x6Bu}; #if defined(__GNUC__) || defined(__ARMCC_VERSION) __attribute__ ((__section__(".cycustnvl"), used)) diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit index e8e530bdb2728d8c3b3ff0a8dfe636a741ec39f2..d6ca5042ce7d59f0d6b2238f54299bd1a22af9af 100755 GIT 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-W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/Cm3Start.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyFlash.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyLib.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/SD_PULLUP.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cdc.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_descr.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_hid.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_midi.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_pm.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyPm.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c : - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P deleted file mode 100755 index aa6db68..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/C_FILE.P +++ /dev/null @@ -1,70 +0,0 @@ -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/main.c - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/main.c : - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P deleted file mode 100755 index 7595633..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/.deps/GNU_ARM_ASM_FILE.P +++ /dev/null @@ -1,10 +0,0 @@ -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o : W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc : - -W:/SCSI2SD/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s : - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst deleted file mode 100755 index 5fc2a5b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/BL.lst +++ /dev/null @@ -1,8147 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "BL.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.BL_LaunchBootloadable,"ax",%progbits - 19 .align 1 - 20 .thumb - 21 .thumb_func - 22 .type BL_LaunchBootloadable, %function - 23 BL_LaunchBootloadable: - 24 .LFB62: - 25 .file 1 ".\\Generated_Source\\PSoC5\\BL.c" - 1:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/BL.c **** * File Name: BL.c - 3:.\Generated_Source\PSoC5/BL.c **** * Version 1.20 - 4:.\Generated_Source\PSoC5/BL.c **** * - 5:.\Generated_Source\PSoC5/BL.c **** * Description: - 6:.\Generated_Source\PSoC5/BL.c **** * Provides an API for the Bootloader component. The API includes functions - 7:.\Generated_Source\PSoC5/BL.c **** * for starting boot loading operations, validating the application and - 8:.\Generated_Source\PSoC5/BL.c **** * jumping to the application. - 9:.\Generated_Source\PSoC5/BL.c **** * - 10:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/BL.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/BL.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/BL.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/BL.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/BL.c **** - 17:.\Generated_Source\PSoC5/BL.c **** #include "BL_PVT.h" - 18:.\Generated_Source\PSoC5/BL.c **** - 19:.\Generated_Source\PSoC5/BL.c **** #include "project.h" - 20:.\Generated_Source\PSoC5/BL.c **** #include - 21:.\Generated_Source\PSoC5/BL.c **** - 22:.\Generated_Source\PSoC5/BL.c **** - 23:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 24:.\Generated_Source\PSoC5/BL.c **** * The Checksum and SizeBytes are forcefully set in code. We then post process - 25:.\Generated_Source\PSoC5/BL.c **** * the hex file from the linker and inject their values then. When the hex file - 26:.\Generated_Source\PSoC5/BL.c **** * is loaded onto the device these two variables should have valid values. - 27:.\Generated_Source\PSoC5/BL.c **** * Because the compiler can do optimizations remove the constant - 28:.\Generated_Source\PSoC5/BL.c **** * accesses, these should not be accessed directly. Instead, the variables - 29:.\Generated_Source\PSoC5/BL.c **** * CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the - 30:.\Generated_Source\PSoC5/BL.c **** * proper values at runtime. - 31:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 32:.\Generated_Source\PSoC5/BL.c **** #if defined(__ARMCC_VERSION) || defined (__GNUC__) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 2 - - - 33:.\Generated_Source\PSoC5/BL.c **** __attribute__((section (".bootloader"))) - 34:.\Generated_Source\PSoC5/BL.c **** #elif defined (__ICCARM__) - 35:.\Generated_Source\PSoC5/BL.c **** #pragma location=".bootloader" - 36:.\Generated_Source\PSoC5/BL.c **** #endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ - 37:.\Generated_Source\PSoC5/BL.c **** - 38:.\Generated_Source\PSoC5/BL.c **** const uint8 CYCODE BL_Checksum = 0u; - 39:.\Generated_Source\PSoC5/BL.c **** const uint8 CYCODE *BL_ChecksumAccess = (const uint8 CYCODE *)(&BL_Checksum); - 40:.\Generated_Source\PSoC5/BL.c **** - 41:.\Generated_Source\PSoC5/BL.c **** #if defined(__ARMCC_VERSION) || defined (__GNUC__) - 42:.\Generated_Source\PSoC5/BL.c **** __attribute__((section (".bootloader"))) - 43:.\Generated_Source\PSoC5/BL.c **** #elif defined (__ICCARM__) - 44:.\Generated_Source\PSoC5/BL.c **** #pragma location=".bootloader" - 45:.\Generated_Source\PSoC5/BL.c **** #endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ - 46:.\Generated_Source\PSoC5/BL.c **** - 47:.\Generated_Source\PSoC5/BL.c **** const uint32 CYCODE BL_SizeBytes = 0xFFFFFFFFu; - 48:.\Generated_Source\PSoC5/BL.c **** const uint32 CYCODE *BL_SizeBytesAccess = (const uint32 CYCODE *)(&BL_SizeBytes); - 49:.\Generated_Source\PSoC5/BL.c **** - 50:.\Generated_Source\PSoC5/BL.c **** - 51:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_DUAL_APP_BOOTLOADER) - 52:.\Generated_Source\PSoC5/BL.c **** uint8 BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; - 53:.\Generated_Source\PSoC5/BL.c **** #else - 54:.\Generated_Source\PSoC5/BL.c **** #define BL_activeApp (BL_MD_BTLDB_ACTIVE_0) - 55:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - 56:.\Generated_Source\PSoC5/BL.c **** - 57:.\Generated_Source\PSoC5/BL.c **** - 58:.\Generated_Source\PSoC5/BL.c **** /*************************************** - 59:.\Generated_Source\PSoC5/BL.c **** * Function Prototypes - 60:.\Generated_Source\PSoC5/BL.c **** ***************************************/ - 61:.\Generated_Source\PSoC5/BL.c **** static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ - 62:.\Generated_Source\PSoC5/BL.c **** ; - 63:.\Generated_Source\PSoC5/BL.c **** - 64:.\Generated_Source\PSoC5/BL.c **** static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \ - 65:.\Generated_Source\PSoC5/BL.c **** ; - 66:.\Generated_Source\PSoC5/BL.c **** - 67:.\Generated_Source\PSoC5/BL.c **** static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) CYSMALL \ - 68:.\Generated_Source\PSoC5/BL.c **** ; - 69:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 70:.\Generated_Source\PSoC5/BL.c **** static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) CYSMALL \ - 71:.\Generated_Source\PSoC5/BL.c **** ; - 72:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ - 73:.\Generated_Source\PSoC5/BL.c **** - 74:.\Generated_Source\PSoC5/BL.c **** static void BL_HostLink(uint8 timeOut) \ - 75:.\Generated_Source\PSoC5/BL.c **** ; - 76:.\Generated_Source\PSoC5/BL.c **** - 77:.\Generated_Source\PSoC5/BL.c **** static void BL_LaunchApplication(void) CYSMALL \ - 78:.\Generated_Source\PSoC5/BL.c **** ; - 79:.\Generated_Source\PSoC5/BL.c **** - 80:.\Generated_Source\PSoC5/BL.c **** static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ - 81:.\Generated_Source\PSoC5/BL.c **** ; - 82:.\Generated_Source\PSoC5/BL.c **** - 83:.\Generated_Source\PSoC5/BL.c **** static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)\ - 84:.\Generated_Source\PSoC5/BL.c **** ; - 85:.\Generated_Source\PSoC5/BL.c **** - 86:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC3) - 87:.\Generated_Source\PSoC5/BL.c **** /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ - 88:.\Generated_Source\PSoC5/BL.c **** static void BL_LaunchBootloadable(uint32 appAddr); - 89:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC3) */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 3 - - - 90:.\Generated_Source\PSoC5/BL.c **** - 91:.\Generated_Source\PSoC5/BL.c **** - 92:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 93:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_CalcPacketChecksum - 94:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 95:.\Generated_Source\PSoC5/BL.c **** * - 96:.\Generated_Source\PSoC5/BL.c **** * Summary: - 97:.\Generated_Source\PSoC5/BL.c **** * This computes the 16 bit checksum for the provided number of bytes contained - 98:.\Generated_Source\PSoC5/BL.c **** * in the provided buffer - 99:.\Generated_Source\PSoC5/BL.c **** * - 100:.\Generated_Source\PSoC5/BL.c **** * Parameters: - 101:.\Generated_Source\PSoC5/BL.c **** * buffer: - 102:.\Generated_Source\PSoC5/BL.c **** * The buffer containing the data to compute the checksum for - 103:.\Generated_Source\PSoC5/BL.c **** * size: - 104:.\Generated_Source\PSoC5/BL.c **** * The number of bytes in buffer to compute the checksum for - 105:.\Generated_Source\PSoC5/BL.c **** * - 106:.\Generated_Source\PSoC5/BL.c **** * Returns: - 107:.\Generated_Source\PSoC5/BL.c **** * 16 bit checksum for the provided data - 108:.\Generated_Source\PSoC5/BL.c **** * - 109:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 110:.\Generated_Source\PSoC5/BL.c **** static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \ - 111:.\Generated_Source\PSoC5/BL.c **** CYSMALL - 112:.\Generated_Source\PSoC5/BL.c **** { - 113:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_PACKET_CHECKSUM_CRC) - 114:.\Generated_Source\PSoC5/BL.c **** - 115:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA crc = BL_CRC_CCITT_INITIAL_VALUE; - 116:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA tmp; - 117:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA i; - 118:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA tmpIndex = size; - 119:.\Generated_Source\PSoC5/BL.c **** - 120:.\Generated_Source\PSoC5/BL.c **** if(0u == size) - 121:.\Generated_Source\PSoC5/BL.c **** { - 122:.\Generated_Source\PSoC5/BL.c **** crc = ~crc; - 123:.\Generated_Source\PSoC5/BL.c **** } - 124:.\Generated_Source\PSoC5/BL.c **** else - 125:.\Generated_Source\PSoC5/BL.c **** { - 126:.\Generated_Source\PSoC5/BL.c **** do - 127:.\Generated_Source\PSoC5/BL.c **** { - 128:.\Generated_Source\PSoC5/BL.c **** tmp = buffer[tmpIndex - size]; - 129:.\Generated_Source\PSoC5/BL.c **** - 130:.\Generated_Source\PSoC5/BL.c **** for (i = 0u; i < 8u; i++) - 131:.\Generated_Source\PSoC5/BL.c **** { - 132:.\Generated_Source\PSoC5/BL.c **** if (0u != ((crc & 0x0001u) ^ (tmp & 0x0001u))) - 133:.\Generated_Source\PSoC5/BL.c **** { - 134:.\Generated_Source\PSoC5/BL.c **** crc = (crc >> 1u) ^ BL_CRC_CCITT_POLYNOMIAL; - 135:.\Generated_Source\PSoC5/BL.c **** } - 136:.\Generated_Source\PSoC5/BL.c **** else - 137:.\Generated_Source\PSoC5/BL.c **** { - 138:.\Generated_Source\PSoC5/BL.c **** crc >>= 1u; - 139:.\Generated_Source\PSoC5/BL.c **** } - 140:.\Generated_Source\PSoC5/BL.c **** - 141:.\Generated_Source\PSoC5/BL.c **** tmp >>= 1u; - 142:.\Generated_Source\PSoC5/BL.c **** } - 143:.\Generated_Source\PSoC5/BL.c **** - 144:.\Generated_Source\PSoC5/BL.c **** size--; - 145:.\Generated_Source\PSoC5/BL.c **** } - 146:.\Generated_Source\PSoC5/BL.c **** while(0u != size); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 4 - - - 147:.\Generated_Source\PSoC5/BL.c **** - 148:.\Generated_Source\PSoC5/BL.c **** crc = ~crc; - 149:.\Generated_Source\PSoC5/BL.c **** tmp = crc; - 150:.\Generated_Source\PSoC5/BL.c **** crc = ( uint16 )(crc << 8u) | (tmp >> 8u); - 151:.\Generated_Source\PSoC5/BL.c **** } - 152:.\Generated_Source\PSoC5/BL.c **** - 153:.\Generated_Source\PSoC5/BL.c **** return(crc); - 154:.\Generated_Source\PSoC5/BL.c **** - 155:.\Generated_Source\PSoC5/BL.c **** #else - 156:.\Generated_Source\PSoC5/BL.c **** - 157:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA sum = 0u; - 158:.\Generated_Source\PSoC5/BL.c **** - 159:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 160:.\Generated_Source\PSoC5/BL.c **** { - 161:.\Generated_Source\PSoC5/BL.c **** sum += buffer[size - 1u]; - 162:.\Generated_Source\PSoC5/BL.c **** size--; - 163:.\Generated_Source\PSoC5/BL.c **** } - 164:.\Generated_Source\PSoC5/BL.c **** - 165:.\Generated_Source\PSoC5/BL.c **** return(( uint16 )1u + ( uint16 )(~sum)); - 166:.\Generated_Source\PSoC5/BL.c **** - 167:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_PACKET_CHECKSUM_CRC) */ - 168:.\Generated_Source\PSoC5/BL.c **** } - 169:.\Generated_Source\PSoC5/BL.c **** - 170:.\Generated_Source\PSoC5/BL.c **** - 171:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 172:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_Calc8BitFlashSum - 173:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 174:.\Generated_Source\PSoC5/BL.c **** * - 175:.\Generated_Source\PSoC5/BL.c **** * Summary: - 176:.\Generated_Source\PSoC5/BL.c **** * This computes the 8 bit sum for the provided number of bytes contained in - 177:.\Generated_Source\PSoC5/BL.c **** * flash. - 178:.\Generated_Source\PSoC5/BL.c **** * - 179:.\Generated_Source\PSoC5/BL.c **** * Parameters: - 180:.\Generated_Source\PSoC5/BL.c **** * start: - 181:.\Generated_Source\PSoC5/BL.c **** * The starting address to start summing data for - 182:.\Generated_Source\PSoC5/BL.c **** * size: - 183:.\Generated_Source\PSoC5/BL.c **** * The number of bytes to read and compute the sum for - 184:.\Generated_Source\PSoC5/BL.c **** * - 185:.\Generated_Source\PSoC5/BL.c **** * Returns: - 186:.\Generated_Source\PSoC5/BL.c **** * 8 bit sum for the provided data - 187:.\Generated_Source\PSoC5/BL.c **** * - 188:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 189:.\Generated_Source\PSoC5/BL.c **** static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) \ - 190:.\Generated_Source\PSoC5/BL.c **** CYSMALL - 191:.\Generated_Source\PSoC5/BL.c **** { - 192:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA sum = 0u; - 193:.\Generated_Source\PSoC5/BL.c **** - 194:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 195:.\Generated_Source\PSoC5/BL.c **** { - 196:.\Generated_Source\PSoC5/BL.c **** size--; - 197:.\Generated_Source\PSoC5/BL.c **** sum += BL_GET_CODE_BYTE(start + size); - 198:.\Generated_Source\PSoC5/BL.c **** } - 199:.\Generated_Source\PSoC5/BL.c **** - 200:.\Generated_Source\PSoC5/BL.c **** return(sum); - 201:.\Generated_Source\PSoC5/BL.c **** } - 202:.\Generated_Source\PSoC5/BL.c **** - 203:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 5 - - - 204:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 205:.\Generated_Source\PSoC5/BL.c **** - 206:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 207:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_Calc8BitEepromSum - 208:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 209:.\Generated_Source\PSoC5/BL.c **** * - 210:.\Generated_Source\PSoC5/BL.c **** * Summary: - 211:.\Generated_Source\PSoC5/BL.c **** * This computes the 8 bit sum for the provided number of bytes contained in - 212:.\Generated_Source\PSoC5/BL.c **** * EEPROM. - 213:.\Generated_Source\PSoC5/BL.c **** * - 214:.\Generated_Source\PSoC5/BL.c **** * Parameters: - 215:.\Generated_Source\PSoC5/BL.c **** * start: - 216:.\Generated_Source\PSoC5/BL.c **** * The starting address to start summing data for - 217:.\Generated_Source\PSoC5/BL.c **** * size: - 218:.\Generated_Source\PSoC5/BL.c **** * The number of bytes to read and compute the sum for - 219:.\Generated_Source\PSoC5/BL.c **** * - 220:.\Generated_Source\PSoC5/BL.c **** * Returns: - 221:.\Generated_Source\PSoC5/BL.c **** * 8 bit sum for the provided data - 222:.\Generated_Source\PSoC5/BL.c **** * - 223:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 224:.\Generated_Source\PSoC5/BL.c **** static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) \ - 225:.\Generated_Source\PSoC5/BL.c **** CYSMALL - 226:.\Generated_Source\PSoC5/BL.c **** { - 227:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA sum = 0u; - 228:.\Generated_Source\PSoC5/BL.c **** - 229:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 230:.\Generated_Source\PSoC5/BL.c **** { - 231:.\Generated_Source\PSoC5/BL.c **** size--; - 232:.\Generated_Source\PSoC5/BL.c **** sum += BL_GET_EEPROM_BYTE(start + size); - 233:.\Generated_Source\PSoC5/BL.c **** } - 234:.\Generated_Source\PSoC5/BL.c **** - 235:.\Generated_Source\PSoC5/BL.c **** return(sum); - 236:.\Generated_Source\PSoC5/BL.c **** } - 237:.\Generated_Source\PSoC5/BL.c **** - 238:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ - 239:.\Generated_Source\PSoC5/BL.c **** - 240:.\Generated_Source\PSoC5/BL.c **** - 241:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 242:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_Start - 243:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 244:.\Generated_Source\PSoC5/BL.c **** * Summary: - 245:.\Generated_Source\PSoC5/BL.c **** * This function is called in order executing following algorithm: - 246:.\Generated_Source\PSoC5/BL.c **** * - 247:.\Generated_Source\PSoC5/BL.c **** * - Identify active bootloadable application (applicable only to - 248:.\Generated_Source\PSoC5/BL.c **** * Multi-application bootloader) - 249:.\Generated_Source\PSoC5/BL.c **** * - 250:.\Generated_Source\PSoC5/BL.c **** * - Validate bootloader application (desing-time configurable, Bootloader - 251:.\Generated_Source\PSoC5/BL.c **** * application validation option of the component customizer) - 252:.\Generated_Source\PSoC5/BL.c **** * - 253:.\Generated_Source\PSoC5/BL.c **** * - Validate active bootloadable application - 254:.\Generated_Source\PSoC5/BL.c **** * - 255:.\Generated_Source\PSoC5/BL.c **** * - Run communication subroutine (desing-time configurable, Wait for command - 256:.\Generated_Source\PSoC5/BL.c **** * option of the component customizer) - 257:.\Generated_Source\PSoC5/BL.c **** * - 258:.\Generated_Source\PSoC5/BL.c **** * - Schedule bootloadable and reset device - 259:.\Generated_Source\PSoC5/BL.c **** * - 260:.\Generated_Source\PSoC5/BL.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 6 - - - 261:.\Generated_Source\PSoC5/BL.c **** * None - 262:.\Generated_Source\PSoC5/BL.c **** * - 263:.\Generated_Source\PSoC5/BL.c **** * Return: - 264:.\Generated_Source\PSoC5/BL.c **** * This method will never return. It will either load a new application and - 265:.\Generated_Source\PSoC5/BL.c **** * reset the device or it will jump directly to the existing application. - 266:.\Generated_Source\PSoC5/BL.c **** * - 267:.\Generated_Source\PSoC5/BL.c **** * Side Effects: - 268:.\Generated_Source\PSoC5/BL.c **** * If this method determines that the bootloader appliation itself is corrupt, - 269:.\Generated_Source\PSoC5/BL.c **** * this method will not return, instead it will simply hang the application. - 270:.\Generated_Source\PSoC5/BL.c **** * - 271:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 272:.\Generated_Source\PSoC5/BL.c **** void BL_Start(void) CYSMALL - 273:.\Generated_Source\PSoC5/BL.c **** { - 274:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_BOOTLOADER_APP_VALIDATION) - 275:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA calcedChecksum; - 276:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ - 277:.\Generated_Source\PSoC5/BL.c **** - 278:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 279:.\Generated_Source\PSoC5/BL.c **** uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE]; - 280:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ - 281:.\Generated_Source\PSoC5/BL.c **** - 282:.\Generated_Source\PSoC5/BL.c **** cystatus tmpStatus; - 283:.\Generated_Source\PSoC5/BL.c **** - 284:.\Generated_Source\PSoC5/BL.c **** - 285:.\Generated_Source\PSoC5/BL.c **** /* Identify active bootloadable application */ - 286:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_DUAL_APP_BOOTLOADER) - 287:.\Generated_Source\PSoC5/BL.c **** - 288:.\Generated_Source\PSoC5/BL.c **** if(BL_MD_BTLDB_ACTIVE_VALUE(0u) == BL_MD_BTLDB_IS_ACTIVE) - 289:.\Generated_Source\PSoC5/BL.c **** { - 290:.\Generated_Source\PSoC5/BL.c **** BL_activeApp = BL_MD_BTLDB_ACTIVE_0; - 291:.\Generated_Source\PSoC5/BL.c **** } - 292:.\Generated_Source\PSoC5/BL.c **** else if (BL_MD_BTLDB_ACTIVE_VALUE(1u) == BL_MD_BTLDB_IS_ACTIVE) - 293:.\Generated_Source\PSoC5/BL.c **** { - 294:.\Generated_Source\PSoC5/BL.c **** BL_activeApp = BL_MD_BTLDB_ACTIVE_1; - 295:.\Generated_Source\PSoC5/BL.c **** } - 296:.\Generated_Source\PSoC5/BL.c **** else - 297:.\Generated_Source\PSoC5/BL.c **** { - 298:.\Generated_Source\PSoC5/BL.c **** BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; - 299:.\Generated_Source\PSoC5/BL.c **** } - 300:.\Generated_Source\PSoC5/BL.c **** - 301:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - 302:.\Generated_Source\PSoC5/BL.c **** - 303:.\Generated_Source\PSoC5/BL.c **** - 304:.\Generated_Source\PSoC5/BL.c **** /* Initialize Flash subsystem for non-PSoC 4 devices */ - 305:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 306:.\Generated_Source\PSoC5/BL.c **** if (CYRET_SUCCESS != CySetTemp()) - 307:.\Generated_Source\PSoC5/BL.c **** { - 308:.\Generated_Source\PSoC5/BL.c **** CyHalt(0x00u); - 309:.\Generated_Source\PSoC5/BL.c **** } - 310:.\Generated_Source\PSoC5/BL.c **** - 311:.\Generated_Source\PSoC5/BL.c **** if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer)) - 312:.\Generated_Source\PSoC5/BL.c **** { - 313:.\Generated_Source\PSoC5/BL.c **** CyHalt(0x00u); - 314:.\Generated_Source\PSoC5/BL.c **** } - 315:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC4) */ - 316:.\Generated_Source\PSoC5/BL.c **** - 317:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 7 - - - 318:.\Generated_Source\PSoC5/BL.c **** /*********************************************************************** - 319:.\Generated_Source\PSoC5/BL.c **** * Bootloader Application Validation - 320:.\Generated_Source\PSoC5/BL.c **** * - 321:.\Generated_Source\PSoC5/BL.c **** * Halt device if: - 322:.\Generated_Source\PSoC5/BL.c **** * - Calculated checksum does not much one stored in metadata section - 323:.\Generated_Source\PSoC5/BL.c **** * - Invalid pointer to the place where bootloader application ends - 324:.\Generated_Source\PSoC5/BL.c **** * - Flash subsystem where not initialized correctly - 325:.\Generated_Source\PSoC5/BL.c **** ***********************************************************************/ - 326:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_BOOTLOADER_APP_VALIDATION) - 327:.\Generated_Source\PSoC5/BL.c **** - 328:.\Generated_Source\PSoC5/BL.c **** /* Calculate Bootloader application checksum */ - 329:.\Generated_Source\PSoC5/BL.c **** calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR, - 330:.\Generated_Source\PSoC5/BL.c **** *BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR); - 331:.\Generated_Source\PSoC5/BL.c **** - 332:.\Generated_Source\PSoC5/BL.c **** /* we actually included the checksum, so remove it */ - 333:.\Generated_Source\PSoC5/BL.c **** calcedChecksum -= *BL_ChecksumAccess; - 334:.\Generated_Source\PSoC5/BL.c **** calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); - 335:.\Generated_Source\PSoC5/BL.c **** - 336:.\Generated_Source\PSoC5/BL.c **** /* Checksum and pointer to bootloader verification */ - 337:.\Generated_Source\PSoC5/BL.c **** if((calcedChecksum != *BL_ChecksumAccess) || - 338:.\Generated_Source\PSoC5/BL.c **** (0u == *BL_SizeBytesAccess)) - 339:.\Generated_Source\PSoC5/BL.c **** { - 340:.\Generated_Source\PSoC5/BL.c **** CyHalt(0x00u); - 341:.\Generated_Source\PSoC5/BL.c **** } - 342:.\Generated_Source\PSoC5/BL.c **** - 343:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ - 344:.\Generated_Source\PSoC5/BL.c **** - 345:.\Generated_Source\PSoC5/BL.c **** - 346:.\Generated_Source\PSoC5/BL.c **** /*********************************************************************** - 347:.\Generated_Source\PSoC5/BL.c **** * Active Bootloadable Application Validation - 348:.\Generated_Source\PSoC5/BL.c **** * - 349:.\Generated_Source\PSoC5/BL.c **** * If active bootloadable application is invalid or bootloader - 350:.\Generated_Source\PSoC5/BL.c **** * application is scheduled - do the following: - 351:.\Generated_Source\PSoC5/BL.c **** * - schedule bootloader application to be run after software reset - 352:.\Generated_Source\PSoC5/BL.c **** * - Go to the communication subroutine. Will wait for commands forever - 353:.\Generated_Source\PSoC5/BL.c **** ***********************************************************************/ - 354:.\Generated_Source\PSoC5/BL.c **** tmpStatus = BL_ValidateBootloadable(BL_activeApp); - 355:.\Generated_Source\PSoC5/BL.c **** - 356:.\Generated_Source\PSoC5/BL.c **** if ((BL_GET_RUN_TYPE == BL_START_BTLDR) || - 357:.\Generated_Source\PSoC5/BL.c **** (CYRET_SUCCESS != tmpStatus)) - 358:.\Generated_Source\PSoC5/BL.c **** { - 359:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(0u); - 360:.\Generated_Source\PSoC5/BL.c **** - 361:.\Generated_Source\PSoC5/BL.c **** BL_HostLink(BL_WAIT_FOR_COMMAND_FOREVER); - 362:.\Generated_Source\PSoC5/BL.c **** } - 363:.\Generated_Source\PSoC5/BL.c **** - 364:.\Generated_Source\PSoC5/BL.c **** - 365:.\Generated_Source\PSoC5/BL.c **** /* Go to the communication subroutine. Will wait for commands specifed time */ - 366:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_WAIT_FOR_COMMAND) - 367:.\Generated_Source\PSoC5/BL.c **** - 368:.\Generated_Source\PSoC5/BL.c **** /* Timeout is in 100s of miliseconds */ - 369:.\Generated_Source\PSoC5/BL.c **** BL_HostLink(BL_WAIT_FOR_COMMAND_TIME); - 370:.\Generated_Source\PSoC5/BL.c **** - 371:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_WAIT_FOR_COMMAND) */ - 372:.\Generated_Source\PSoC5/BL.c **** - 373:.\Generated_Source\PSoC5/BL.c **** - 374:.\Generated_Source\PSoC5/BL.c **** /* Schedule bootloadable application and perform software reset */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 8 - - - 375:.\Generated_Source\PSoC5/BL.c **** BL_LaunchApplication(); - 376:.\Generated_Source\PSoC5/BL.c **** } - 377:.\Generated_Source\PSoC5/BL.c **** - 378:.\Generated_Source\PSoC5/BL.c **** - 379:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 380:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_LaunchApplication - 381:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 382:.\Generated_Source\PSoC5/BL.c **** * - 383:.\Generated_Source\PSoC5/BL.c **** * Summary: - 384:.\Generated_Source\PSoC5/BL.c **** * Jumps the PC to the start address of the user application in flash. - 385:.\Generated_Source\PSoC5/BL.c **** * - 386:.\Generated_Source\PSoC5/BL.c **** * Parameters: - 387:.\Generated_Source\PSoC5/BL.c **** * None - 388:.\Generated_Source\PSoC5/BL.c **** * - 389:.\Generated_Source\PSoC5/BL.c **** * Returns: - 390:.\Generated_Source\PSoC5/BL.c **** * This method will never return if it succesfully goes to the user application. - 391:.\Generated_Source\PSoC5/BL.c **** * - 392:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 393:.\Generated_Source\PSoC5/BL.c **** static void BL_LaunchApplication(void) CYSMALL - 394:.\Generated_Source\PSoC5/BL.c **** { - 395:.\Generated_Source\PSoC5/BL.c **** /* Schedule Bootloadable to start after reset */ - 396:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(BL_START_APP); - 397:.\Generated_Source\PSoC5/BL.c **** - 398:.\Generated_Source\PSoC5/BL.c **** CySoftwareReset(); - 399:.\Generated_Source\PSoC5/BL.c **** } - 400:.\Generated_Source\PSoC5/BL.c **** - 401:.\Generated_Source\PSoC5/BL.c **** - 402:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 403:.\Generated_Source\PSoC5/BL.c **** * Function Name: CyBtldr_CheckLaunch - 404:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 405:.\Generated_Source\PSoC5/BL.c **** * - 406:.\Generated_Source\PSoC5/BL.c **** * Summary: - 407:.\Generated_Source\PSoC5/BL.c **** * This routine checks to see if the bootloader or the bootloadable application - 408:.\Generated_Source\PSoC5/BL.c **** * should be run. If the application is to be run, it will start executing. - 409:.\Generated_Source\PSoC5/BL.c **** * If the bootloader is to be run, it will return so the bootloader can - 410:.\Generated_Source\PSoC5/BL.c **** * continue starting up. - 411:.\Generated_Source\PSoC5/BL.c **** * - 412:.\Generated_Source\PSoC5/BL.c **** * Parameters: - 413:.\Generated_Source\PSoC5/BL.c **** * None - 414:.\Generated_Source\PSoC5/BL.c **** * - 415:.\Generated_Source\PSoC5/BL.c **** * Returns: - 416:.\Generated_Source\PSoC5/BL.c **** * None - 417:.\Generated_Source\PSoC5/BL.c **** * - 418:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 419:.\Generated_Source\PSoC5/BL.c **** void CyBtldr_CheckLaunch(void) CYSMALL - 420:.\Generated_Source\PSoC5/BL.c **** { - 421:.\Generated_Source\PSoC5/BL.c **** - 422:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC4) - 423:.\Generated_Source\PSoC5/BL.c **** - 424:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 425:.\Generated_Source\PSoC5/BL.c **** * Set cyBtldrRunType to zero in case of non-software reset occured. This means - 426:.\Generated_Source\PSoC5/BL.c **** * that bootloader application is scheduled - that is initial clean state. The - 427:.\Generated_Source\PSoC5/BL.c **** * value of cyBtldrRunType is valid only in case of software reset. - 428:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 429:.\Generated_Source\PSoC5/BL.c **** if (0u == (BL_RES_CAUSE_REG & BL_RES_CAUSE_RESET_SOFT)) - 430:.\Generated_Source\PSoC5/BL.c **** { - 431:.\Generated_Source\PSoC5/BL.c **** cyBtldrRunType = 0u; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 9 - - - 432:.\Generated_Source\PSoC5/BL.c **** } - 433:.\Generated_Source\PSoC5/BL.c **** - 434:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC4) */ - 435:.\Generated_Source\PSoC5/BL.c **** - 436:.\Generated_Source\PSoC5/BL.c **** - 437:.\Generated_Source\PSoC5/BL.c **** if (BL_GET_RUN_TYPE == BL_START_APP) - 438:.\Generated_Source\PSoC5/BL.c **** { - 439:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(0u); - 440:.\Generated_Source\PSoC5/BL.c **** - 441:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 442:.\Generated_Source\PSoC5/BL.c **** * Indicates that we have told ourselves to jump to the application since we have - 443:.\Generated_Source\PSoC5/BL.c **** * already told ourselves to jump, we do not do any expensive verification of the - 444:.\Generated_Source\PSoC5/BL.c **** * application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS - 445:.\Generated_Source\PSoC5/BL.c **** * is something other than 0. - 446:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 447:.\Generated_Source\PSoC5/BL.c **** if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp)) - 448:.\Generated_Source\PSoC5/BL.c **** { - 449:.\Generated_Source\PSoC5/BL.c **** /* Never return from this method */ - 450:.\Generated_Source\PSoC5/BL.c **** BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, - 451:.\Generated_Source\PSoC5/BL.c **** BL_activeApp)); - 452:.\Generated_Source\PSoC5/BL.c **** } - 453:.\Generated_Source\PSoC5/BL.c **** } - 454:.\Generated_Source\PSoC5/BL.c **** } - 455:.\Generated_Source\PSoC5/BL.c **** - 456:.\Generated_Source\PSoC5/BL.c **** - 457:.\Generated_Source\PSoC5/BL.c **** /* Moves the arguement appAddr (RO) into PC, moving execution to the appAddr */ - 458:.\Generated_Source\PSoC5/BL.c **** #if defined (__ARMCC_VERSION) - 459:.\Generated_Source\PSoC5/BL.c **** - 460:.\Generated_Source\PSoC5/BL.c **** __asm static void BL_LaunchBootloadable(uint32 appAddr) - 461:.\Generated_Source\PSoC5/BL.c **** { - 462:.\Generated_Source\PSoC5/BL.c **** BX R0 - 463:.\Generated_Source\PSoC5/BL.c **** ALIGN - 464:.\Generated_Source\PSoC5/BL.c **** } - 465:.\Generated_Source\PSoC5/BL.c **** - 466:.\Generated_Source\PSoC5/BL.c **** #elif defined(__GNUC__) - 467:.\Generated_Source\PSoC5/BL.c **** - 468:.\Generated_Source\PSoC5/BL.c **** __attribute__((noinline)) /* Workaround for GCC toolchain bug with inlining */ - 469:.\Generated_Source\PSoC5/BL.c **** __attribute__((naked)) - 470:.\Generated_Source\PSoC5/BL.c **** static void BL_LaunchBootloadable(uint32 appAddr) - 471:.\Generated_Source\PSoC5/BL.c **** { - 26 .loc 1 471 0 - 27 .cfi_startproc - 28 @ Naked Function: prologue and epilogue provided by programmer. - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 .LVL0: - 472:.\Generated_Source\PSoC5/BL.c **** __asm volatile(" BX R0\n"); - 32 .loc 1 472 0 - 33 @ 472 ".\Generated_Source\PSoC5\BL.c" 1 - 34 0000 0047 BX R0 - 35 - 36 @ 0 "" 2 - 473:.\Generated_Source\PSoC5/BL.c **** } - 37 .loc 1 473 0 - 38 .thumb - 39 .cfi_endproc - 40 .LFE62: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 10 - - - 41 .size BL_LaunchBootloadable, .-BL_LaunchBootloadable - 42 .section .text.BL_GetMetadata.constprop.1,"ax",%progbits - 43 .align 1 - 44 .thumb - 45 .thumb_func - 46 .type BL_GetMetadata.constprop.1, %function - 47 BL_GetMetadata.constprop.1: - 48 .LFB69: - 474:.\Generated_Source\PSoC5/BL.c **** - 475:.\Generated_Source\PSoC5/BL.c **** #elif defined (__ICCARM__) - 476:.\Generated_Source\PSoC5/BL.c **** - 477:.\Generated_Source\PSoC5/BL.c **** static void BL_LaunchBootloadable(uint32 appAddr) - 478:.\Generated_Source\PSoC5/BL.c **** { - 479:.\Generated_Source\PSoC5/BL.c **** __asm volatile(" BX R0\n"); - 480:.\Generated_Source\PSoC5/BL.c **** } - 481:.\Generated_Source\PSoC5/BL.c **** - 482:.\Generated_Source\PSoC5/BL.c **** #endif /* (__ARMCC_VERSION) */ - 483:.\Generated_Source\PSoC5/BL.c **** - 484:.\Generated_Source\PSoC5/BL.c **** - 485:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 486:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_ValidateBootloadable - 487:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 488:.\Generated_Source\PSoC5/BL.c **** * Summary: - 489:.\Generated_Source\PSoC5/BL.c **** * This routine computes the checksum, zero check, 0xFF check of the - 490:.\Generated_Source\PSoC5/BL.c **** * application area to determine whether a valid application is loaded. - 491:.\Generated_Source\PSoC5/BL.c **** * - 492:.\Generated_Source\PSoC5/BL.c **** * Parameters: - 493:.\Generated_Source\PSoC5/BL.c **** * appId: - 494:.\Generated_Source\PSoC5/BL.c **** * The application number to verify - 495:.\Generated_Source\PSoC5/BL.c **** * - 496:.\Generated_Source\PSoC5/BL.c **** * Returns: - 497:.\Generated_Source\PSoC5/BL.c **** * CYRET_SUCCESS - if successful - 498:.\Generated_Source\PSoC5/BL.c **** * CYRET_BAD_DATA - if the bootloadable is corrupt - 499:.\Generated_Source\PSoC5/BL.c **** * - 500:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 501:.\Generated_Source\PSoC5/BL.c **** static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ - 502:.\Generated_Source\PSoC5/BL.c **** - 503:.\Generated_Source\PSoC5/BL.c **** { - 504:.\Generated_Source\PSoC5/BL.c **** uint32 CYDATA idx; - 505:.\Generated_Source\PSoC5/BL.c **** - 506:.\Generated_Source\PSoC5/BL.c **** uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) + - 507:.\Generated_Source\PSoC5/BL.c **** BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH, - 508:.\Generated_Source\PSoC5/BL.c **** appId); - 509:.\Generated_Source\PSoC5/BL.c **** - 510:.\Generated_Source\PSoC5/BL.c **** CYBIT valid = 0u; /* Assume bad flash image */ - 511:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA calcedChecksum = 0u; - 512:.\Generated_Source\PSoC5/BL.c **** - 513:.\Generated_Source\PSoC5/BL.c **** - 514:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_DUAL_APP_BOOTLOADER) - 515:.\Generated_Source\PSoC5/BL.c **** - 516:.\Generated_Source\PSoC5/BL.c **** if(appId > 1u) - 517:.\Generated_Source\PSoC5/BL.c **** { - 518:.\Generated_Source\PSoC5/BL.c **** return(CYRET_BAD_DATA); - 519:.\Generated_Source\PSoC5/BL.c **** } - 520:.\Generated_Source\PSoC5/BL.c **** - 521:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - 522:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 11 - - - 523:.\Generated_Source\PSoC5/BL.c **** - 524:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_FAST_APP_VALIDATION) - 525:.\Generated_Source\PSoC5/BL.c **** - 526:.\Generated_Source\PSoC5/BL.c **** if(BL_MD_BTLDB_VERIFIED_VALUE(appId) == BL_MD_BTLDB_IS_VERIFIED) - 527:.\Generated_Source\PSoC5/BL.c **** { - 528:.\Generated_Source\PSoC5/BL.c **** return(CYRET_SUCCESS); - 529:.\Generated_Source\PSoC5/BL.c **** } - 530:.\Generated_Source\PSoC5/BL.c **** - 531:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_FAST_APP_VALIDATION) */ - 532:.\Generated_Source\PSoC5/BL.c **** - 533:.\Generated_Source\PSoC5/BL.c **** - 534:.\Generated_Source\PSoC5/BL.c **** /* Calculate checksum of bootloadable image */ - 535:.\Generated_Source\PSoC5/BL.c **** for(idx = BL_FIRST_APP_BYTE(appId); idx < end; ++idx) - 536:.\Generated_Source\PSoC5/BL.c **** { - 537:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA curByte = BL_GET_CODE_BYTE(idx); - 538:.\Generated_Source\PSoC5/BL.c **** - 539:.\Generated_Source\PSoC5/BL.c **** if((curByte != 0u) && (curByte != 0xFFu)) - 540:.\Generated_Source\PSoC5/BL.c **** { - 541:.\Generated_Source\PSoC5/BL.c **** valid = 1u; - 542:.\Generated_Source\PSoC5/BL.c **** } - 543:.\Generated_Source\PSoC5/BL.c **** - 544:.\Generated_Source\PSoC5/BL.c **** calcedChecksum += curByte; - 545:.\Generated_Source\PSoC5/BL.c **** } - 546:.\Generated_Source\PSoC5/BL.c **** - 547:.\Generated_Source\PSoC5/BL.c **** - 548:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** - 549:.\Generated_Source\PSoC5/BL.c **** * We do not compute checksum over the meta data section, so no need to - 550:.\Generated_Source\PSoC5/BL.c **** * subtract off App Verified or App Active information here like we do when - 551:.\Generated_Source\PSoC5/BL.c **** * verifying a row. - 552:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ - 553:.\Generated_Source\PSoC5/BL.c **** - 554:.\Generated_Source\PSoC5/BL.c **** - 555:.\Generated_Source\PSoC5/BL.c **** #if((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) - 556:.\Generated_Source\PSoC5/BL.c **** - 557:.\Generated_Source\PSoC5/BL.c **** /* Add ECC data to checksum */ - 558:.\Generated_Source\PSoC5/BL.c **** idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u); - 559:.\Generated_Source\PSoC5/BL.c **** - 560:.\Generated_Source\PSoC5/BL.c **** /* Flash may run into meta data, ECC does not so use full row */ - 561:.\Generated_Source\PSoC5/BL.c **** end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF)) - 562:.\Generated_Source\PSoC5/BL.c **** ? (CY_FLASH_SIZE >> 3u) - 563:.\Generated_Source\PSoC5/BL.c **** : (end >> 3u); - 564:.\Generated_Source\PSoC5/BL.c **** - 565:.\Generated_Source\PSoC5/BL.c **** for (; idx < end; ++idx) - 566:.\Generated_Source\PSoC5/BL.c **** { - 567:.\Generated_Source\PSoC5/BL.c **** calcedChecksum += CY_GET_XTND_REG8((volatile uint8 *)(CYDEV_ECC_BASE + idx)); - 568:.\Generated_Source\PSoC5/BL.c **** } - 569:.\Generated_Source\PSoC5/BL.c **** - 570:.\Generated_Source\PSoC5/BL.c **** #endif /* ((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) */ - 571:.\Generated_Source\PSoC5/BL.c **** - 572:.\Generated_Source\PSoC5/BL.c **** - 573:.\Generated_Source\PSoC5/BL.c **** calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); - 574:.\Generated_Source\PSoC5/BL.c **** - 575:.\Generated_Source\PSoC5/BL.c **** if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) || - 576:.\Generated_Source\PSoC5/BL.c **** (0u == valid)) - 577:.\Generated_Source\PSoC5/BL.c **** { - 578:.\Generated_Source\PSoC5/BL.c **** return(CYRET_BAD_DATA); - 579:.\Generated_Source\PSoC5/BL.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 12 - - - 580:.\Generated_Source\PSoC5/BL.c **** - 581:.\Generated_Source\PSoC5/BL.c **** - 582:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_FAST_APP_VALIDATION) - 583:.\Generated_Source\PSoC5/BL.c **** BL_SetFlashByte((uint32) BL_MD_BTLDB_VERIFIED_OFFSET(appId), - 584:.\Generated_Source\PSoC5/BL.c **** BL_MD_BTLDB_IS_VERIFIED); - 585:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_FAST_APP_VALIDATION) */ - 586:.\Generated_Source\PSoC5/BL.c **** - 587:.\Generated_Source\PSoC5/BL.c **** - 588:.\Generated_Source\PSoC5/BL.c **** return(CYRET_SUCCESS); - 589:.\Generated_Source\PSoC5/BL.c **** } - 590:.\Generated_Source\PSoC5/BL.c **** - 591:.\Generated_Source\PSoC5/BL.c **** - 592:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* - 593:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_HostLink - 594:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** - 595:.\Generated_Source\PSoC5/BL.c **** * - 596:.\Generated_Source\PSoC5/BL.c **** * Summary: - 597:.\Generated_Source\PSoC5/BL.c **** * Causes the bootloader to attempt to read data being transmitted by the - 598:.\Generated_Source\PSoC5/BL.c **** * host application. If data is sent from the host, this establishes the - 599:.\Generated_Source\PSoC5/BL.c **** * communication interface to process all requests. - 600:.\Generated_Source\PSoC5/BL.c **** * - 601:.\Generated_Source\PSoC5/BL.c **** * Parameters: - 602:.\Generated_Source\PSoC5/BL.c **** * timeOut: - 603:.\Generated_Source\PSoC5/BL.c **** * The amount of time to listen for data before giving up. Timeout is - 604:.\Generated_Source\PSoC5/BL.c **** * measured in 10s of ms. Use 0 for infinite wait. - 605:.\Generated_Source\PSoC5/BL.c **** * - 606:.\Generated_Source\PSoC5/BL.c **** * Return: - 607:.\Generated_Source\PSoC5/BL.c **** * None - 608:.\Generated_Source\PSoC5/BL.c **** * - 609:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - 610:.\Generated_Source\PSoC5/BL.c **** static void BL_HostLink(uint8 timeOut) - 611:.\Generated_Source\PSoC5/BL.c **** { - 612:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA numberRead; - 613:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA rspSize; - 614:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA ackCode; - 615:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA pktChecksum; - 616:.\Generated_Source\PSoC5/BL.c **** cystatus CYDATA readStat; - 617:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA pktSize = 0u; - 618:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA dataOffset = 0u; - 619:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA timeOutCnt = 10u; - 620:.\Generated_Source\PSoC5/BL.c **** - 621:.\Generated_Source\PSoC5/BL.c **** #if(0u == BL_DUAL_APP_BOOTLOADER) - 622:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA clearedMetaData = 0u; - 623:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ - 624:.\Generated_Source\PSoC5/BL.c **** - 625:.\Generated_Source\PSoC5/BL.c **** CYBIT communicationState = BL_COMMUNICATION_STATE_IDLE; - 626:.\Generated_Source\PSoC5/BL.c **** - 627:.\Generated_Source\PSoC5/BL.c **** uint8 packetBuffer[BL_SIZEOF_COMMAND_BUFFER]; - 628:.\Generated_Source\PSoC5/BL.c **** uint8 dataBuffer [BL_SIZEOF_COMMAND_BUFFER]; - 629:.\Generated_Source\PSoC5/BL.c **** - 630:.\Generated_Source\PSoC5/BL.c **** - 631:.\Generated_Source\PSoC5/BL.c **** /* Initialize communications channel. */ - 632:.\Generated_Source\PSoC5/BL.c **** CyBtldrCommStart(); - 633:.\Generated_Source\PSoC5/BL.c **** - 634:.\Generated_Source\PSoC5/BL.c **** /* Enable global interrupts */ - 635:.\Generated_Source\PSoC5/BL.c **** CyGlobalIntEnable; - 636:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 13 - - - 637:.\Generated_Source\PSoC5/BL.c **** do - 638:.\Generated_Source\PSoC5/BL.c **** { - 639:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 640:.\Generated_Source\PSoC5/BL.c **** - 641:.\Generated_Source\PSoC5/BL.c **** do - 642:.\Generated_Source\PSoC5/BL.c **** { - 643:.\Generated_Source\PSoC5/BL.c **** readStat = CyBtldrCommRead(packetBuffer, - 644:.\Generated_Source\PSoC5/BL.c **** BL_SIZEOF_COMMAND_BUFFER, - 645:.\Generated_Source\PSoC5/BL.c **** &numberRead, - 646:.\Generated_Source\PSoC5/BL.c **** (0u == timeOut) ? 0xFFu : timeOut); - 647:.\Generated_Source\PSoC5/BL.c **** if (0u != timeOut) - 648:.\Generated_Source\PSoC5/BL.c **** { - 649:.\Generated_Source\PSoC5/BL.c **** timeOutCnt--; - 650:.\Generated_Source\PSoC5/BL.c **** } - 651:.\Generated_Source\PSoC5/BL.c **** - 652:.\Generated_Source\PSoC5/BL.c **** } while ( (0u != timeOutCnt) && (readStat != CYRET_SUCCESS) ); - 653:.\Generated_Source\PSoC5/BL.c **** - 654:.\Generated_Source\PSoC5/BL.c **** - 655:.\Generated_Source\PSoC5/BL.c **** if( readStat != CYRET_SUCCESS ) - 656:.\Generated_Source\PSoC5/BL.c **** { - 657:.\Generated_Source\PSoC5/BL.c **** continue; - 658:.\Generated_Source\PSoC5/BL.c **** } - 659:.\Generated_Source\PSoC5/BL.c **** - 660:.\Generated_Source\PSoC5/BL.c **** if((numberRead < BL_MIN_PKT_SIZE) || - 661:.\Generated_Source\PSoC5/BL.c **** (packetBuffer[BL_SOP_ADDR] != BL_SOP)) - 662:.\Generated_Source\PSoC5/BL.c **** { - 663:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_DATA; - 664:.\Generated_Source\PSoC5/BL.c **** } - 665:.\Generated_Source\PSoC5/BL.c **** else - 666:.\Generated_Source\PSoC5/BL.c **** { - 667:.\Generated_Source\PSoC5/BL.c **** pktSize = ((uint16)((uint16)packetBuffer[BL_SIZE_ADDR + 1u] << 8u)) | - 668:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_SIZE_ADDR]; - 669:.\Generated_Source\PSoC5/BL.c **** - 670:.\Generated_Source\PSoC5/BL.c **** pktChecksum = ((uint16)((uint16)packetBuffer[BL_CHK_ADDR(pktSize) + 1u] << 8u)) | - 671:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_CHK_ADDR(pktSize)]; - 672:.\Generated_Source\PSoC5/BL.c **** - 673:.\Generated_Source\PSoC5/BL.c **** if((pktSize + BL_MIN_PKT_SIZE) > numberRead) - 674:.\Generated_Source\PSoC5/BL.c **** { - 675:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_LENGTH; - 676:.\Generated_Source\PSoC5/BL.c **** } - 677:.\Generated_Source\PSoC5/BL.c **** else if(packetBuffer[BL_EOP_ADDR(pktSize)] != BL_EOP) - 678:.\Generated_Source\PSoC5/BL.c **** { - 679:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_DATA; - 680:.\Generated_Source\PSoC5/BL.c **** } - 681:.\Generated_Source\PSoC5/BL.c **** else if(pktChecksum != BL_CalcPacketChecksum(packetBuffer, - 682:.\Generated_Source\PSoC5/BL.c **** pktSize + BL_DATA_ADDR)) - 683:.\Generated_Source\PSoC5/BL.c **** { - 684:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_CHECKSUM; - 685:.\Generated_Source\PSoC5/BL.c **** } - 686:.\Generated_Source\PSoC5/BL.c **** else - 687:.\Generated_Source\PSoC5/BL.c **** { - 688:.\Generated_Source\PSoC5/BL.c **** /* Empty section */ - 689:.\Generated_Source\PSoC5/BL.c **** } - 690:.\Generated_Source\PSoC5/BL.c **** } - 691:.\Generated_Source\PSoC5/BL.c **** - 692:.\Generated_Source\PSoC5/BL.c **** rspSize = 0u; - 693:.\Generated_Source\PSoC5/BL.c **** if(ackCode == CYRET_SUCCESS) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 14 - - - 694:.\Generated_Source\PSoC5/BL.c **** { - 695:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA btldrData = packetBuffer[BL_DATA_ADDR]; - 696:.\Generated_Source\PSoC5/BL.c **** - 697:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_DATA; - 698:.\Generated_Source\PSoC5/BL.c **** switch(packetBuffer[BL_CMD_ADDR]) - 699:.\Generated_Source\PSoC5/BL.c **** { - 700:.\Generated_Source\PSoC5/BL.c **** - 701:.\Generated_Source\PSoC5/BL.c **** - 702:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** - 703:.\Generated_Source\PSoC5/BL.c **** * Get metadata - 704:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ - 705:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_CMD_GET_METADATA) - 706:.\Generated_Source\PSoC5/BL.c **** - 707:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_GET_METADATA: - 708:.\Generated_Source\PSoC5/BL.c **** - 709:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - 710:.\Generated_Source\PSoC5/BL.c **** { - 711:.\Generated_Source\PSoC5/BL.c **** if (btldrData >= BL_MAX_NUM_OF_BTLDB) - 712:.\Generated_Source\PSoC5/BL.c **** { - 713:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_APP; - 714:.\Generated_Source\PSoC5/BL.c **** } - 715:.\Generated_Source\PSoC5/BL.c **** else if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) - 716:.\Generated_Source\PSoC5/BL.c **** { - 717:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) - 718:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&packetBuffer[BL_DATA_ADDR], - 719:.\Generated_Source\PSoC5/BL.c **** ((uint8 CYCODE *) (BL_META_BASE(btldrData))), 56); - 720:.\Generated_Source\PSoC5/BL.c **** #else - 721:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&packetBuffer[BL_DATA_ADDR], - 722:.\Generated_Source\PSoC5/BL.c **** (uint8 *) BL_META_BASE(btldrData), 56u); - 723:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ - 724:.\Generated_Source\PSoC5/BL.c **** - 725:.\Generated_Source\PSoC5/BL.c **** rspSize = 56u; - 726:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 727:.\Generated_Source\PSoC5/BL.c **** } - 728:.\Generated_Source\PSoC5/BL.c **** else - 729:.\Generated_Source\PSoC5/BL.c **** { - 730:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_APP; - 731:.\Generated_Source\PSoC5/BL.c **** } - 732:.\Generated_Source\PSoC5/BL.c **** } - 733:.\Generated_Source\PSoC5/BL.c **** break; - 734:.\Generated_Source\PSoC5/BL.c **** - 735:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_CMD_GET_METADATA) */ - 736:.\Generated_Source\PSoC5/BL.c **** - 737:.\Generated_Source\PSoC5/BL.c **** - 738:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** - 739:.\Generated_Source\PSoC5/BL.c **** * Verify checksum - 740:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ - 741:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_CHECKSUM: - 742:.\Generated_Source\PSoC5/BL.c **** - 743:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 0u)) - 744:.\Generated_Source\PSoC5/BL.c **** { - 745:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR] = - 746:.\Generated_Source\PSoC5/BL.c **** (uint8)(BL_ValidateBootloadable(BL_activeApp) == CYRET_SUCCESS); - 747:.\Generated_Source\PSoC5/BL.c **** - 748:.\Generated_Source\PSoC5/BL.c **** rspSize = 1u; - 749:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 750:.\Generated_Source\PSoC5/BL.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 15 - - - 751:.\Generated_Source\PSoC5/BL.c **** break; - 752:.\Generated_Source\PSoC5/BL.c **** - 753:.\Generated_Source\PSoC5/BL.c **** - 754:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** - 755:.\Generated_Source\PSoC5/BL.c **** * Get flash size - 756:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ - 757:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL) - 758:.\Generated_Source\PSoC5/BL.c **** - 759:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_REPORT_SIZE: - 760:.\Generated_Source\PSoC5/BL.c **** - 761:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - 762:.\Generated_Source\PSoC5/BL.c **** { - 763:.\Generated_Source\PSoC5/BL.c **** /* btldrData holds flash array ID sent by host */ - 764:.\Generated_Source\PSoC5/BL.c **** if(btldrData < BL_NUM_OF_FLASH_ARRAYS) - 765:.\Generated_Source\PSoC5/BL.c **** { - 766:.\Generated_Source\PSoC5/BL.c **** #if (1u == BL_NUM_OF_FLASH_ARRAYS) - 767:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA startRow = (uint16)*BL_SizeBytesAccess / CYDEV_FLS_RO - 768:.\Generated_Source\PSoC5/BL.c **** #else - 769:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA startRow = 0u; - 770:.\Generated_Source\PSoC5/BL.c **** #endif /* (1u == BL_NUM_OF_FLASH_ARRAYS) */ - 771:.\Generated_Source\PSoC5/BL.c **** - 772:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR] = LO8(startRow); - 773:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow); - 774:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u); - 775:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u); - 776:.\Generated_Source\PSoC5/BL.c **** - 777:.\Generated_Source\PSoC5/BL.c **** rspSize = 4u; - 778:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 779:.\Generated_Source\PSoC5/BL.c **** } - 780:.\Generated_Source\PSoC5/BL.c **** - 781:.\Generated_Source\PSoC5/BL.c **** } - 782:.\Generated_Source\PSoC5/BL.c **** break; - 783:.\Generated_Source\PSoC5/BL.c **** - 784:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_CMD_GET_FLASH_SIZE_AVAIL) */ - 785:.\Generated_Source\PSoC5/BL.c **** - 786:.\Generated_Source\PSoC5/BL.c **** - 787:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** - 788:.\Generated_Source\PSoC5/BL.c **** * Get application status - 789:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ - 790:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_DUAL_APP_BOOTLOADER) - 791:.\Generated_Source\PSoC5/BL.c **** - 792:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_CMD_GET_APP_STATUS_AVAIL) - 793:.\Generated_Source\PSoC5/BL.c **** - 794:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_APP_STATUS: - 795:.\Generated_Source\PSoC5/BL.c **** - 796:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u) - 797:.\Generated_Source\PSoC5/BL.c **** { - 798:.\Generated_Source\PSoC5/BL.c **** - 799:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR] = - 800:.\Generated_Source\PSoC5/BL.c **** (uint8)BL_ValidateBootloadable(btldrData); - 801:.\Generated_Source\PSoC5/BL.c **** - 802:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 1u] = - 803:.\Generated_Source\PSoC5/BL.c **** (uint8)BL_MD_BTLDB_ACTIVE_VALUE(btldrData); - 804:.\Generated_Source\PSoC5/BL.c **** - 805:.\Generated_Source\PSoC5/BL.c **** rspSize = 2u; - 806:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 807:.\Generated_Source\PSoC5/BL.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 16 - - - 808:.\Generated_Source\PSoC5/BL.c **** break; - 809:.\Generated_Source\PSoC5/BL.c **** - 810:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_CMD_GET_APP_STATUS_AVAIL) */ - 811:.\Generated_Source\PSoC5/BL.c **** - 812:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - 813:.\Generated_Source\PSoC5/BL.c **** - 814:.\Generated_Source\PSoC5/BL.c **** - 815:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** - 816:.\Generated_Source\PSoC5/BL.c **** * Program / Erase row - 817:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ - 818:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_PROGRAM: - 819:.\Generated_Source\PSoC5/BL.c **** - 820:.\Generated_Source\PSoC5/BL.c **** /* The btldrData variable holds Flash Array ID */ - 821:.\Generated_Source\PSoC5/BL.c **** - 822:.\Generated_Source\PSoC5/BL.c **** #if (0u != BL_CMD_ERASE_ROW_AVAIL) - 823:.\Generated_Source\PSoC5/BL.c **** - 824:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_ERASE: - 825:.\Generated_Source\PSoC5/BL.c **** if (BL_COMMAND_ERASE == packetBuffer[BL_CMD_ADDR]) - 826:.\Generated_Source\PSoC5/BL.c **** { - 827:.\Generated_Source\PSoC5/BL.c **** if ((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) - 828:.\Generated_Source\PSoC5/BL.c **** { - 829:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 830:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 831:.\Generated_Source\PSoC5/BL.c **** (btldrData <= BL_LAST_EE_ARRAYID)) - 832:.\Generated_Source\PSoC5/BL.c **** { - 833:.\Generated_Source\PSoC5/BL.c **** /* Size of EEPROM row */ - 834:.\Generated_Source\PSoC5/BL.c **** dataOffset = CY_EEPROM_SIZEOF_ROW; - 835:.\Generated_Source\PSoC5/BL.c **** } - 836:.\Generated_Source\PSoC5/BL.c **** else - 837:.\Generated_Source\PSoC5/BL.c **** { - 838:.\Generated_Source\PSoC5/BL.c **** /* Size of FLASH row (depends on ECC configuration) */ - 839:.\Generated_Source\PSoC5/BL.c **** dataOffset = BL_FROW_SIZE; - 840:.\Generated_Source\PSoC5/BL.c **** } - 841:.\Generated_Source\PSoC5/BL.c **** #else - 842:.\Generated_Source\PSoC5/BL.c **** /* Size of FLASH row (no ECC available) */ - 843:.\Generated_Source\PSoC5/BL.c **** dataOffset = BL_FROW_SIZE; - 844:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ - 845:.\Generated_Source\PSoC5/BL.c **** - 846:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) - 847:.\Generated_Source\PSoC5/BL.c **** (void) memset(dataBuffer, (char8) 0, (int16) dataOffset); - 848:.\Generated_Source\PSoC5/BL.c **** #else - 849:.\Generated_Source\PSoC5/BL.c **** (void) memset(dataBuffer, 0, dataOffset); - 850:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ - 851:.\Generated_Source\PSoC5/BL.c **** } - 852:.\Generated_Source\PSoC5/BL.c **** else - 853:.\Generated_Source\PSoC5/BL.c **** { - 854:.\Generated_Source\PSoC5/BL.c **** break; - 855:.\Generated_Source\PSoC5/BL.c **** } - 856:.\Generated_Source\PSoC5/BL.c **** } - 857:.\Generated_Source\PSoC5/BL.c **** - 858:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_CMD_ERASE_ROW_AVAIL) */ - 859:.\Generated_Source\PSoC5/BL.c **** - 860:.\Generated_Source\PSoC5/BL.c **** - 861:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize >= 3u)) - 862:.\Generated_Source\PSoC5/BL.c **** { - 863:.\Generated_Source\PSoC5/BL.c **** - 864:.\Generated_Source\PSoC5/BL.c **** /* The command may be sent along with the last block of data, to program the ro - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 17 - - - 865:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) - 866:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&dataBuffer[dataOffset], - 867:.\Generated_Source\PSoC5/BL.c **** &packetBuffer[BL_DATA_ADDR + 3u], - 868:.\Generated_Source\PSoC5/BL.c **** ( int16 )pktSize - 3); - 869:.\Generated_Source\PSoC5/BL.c **** #else - 870:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&dataBuffer[dataOffset], - 871:.\Generated_Source\PSoC5/BL.c **** &packetBuffer[BL_DATA_ADDR + 3u], - 872:.\Generated_Source\PSoC5/BL.c **** pktSize - 3u); - 873:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ - 874:.\Generated_Source\PSoC5/BL.c **** - 875:.\Generated_Source\PSoC5/BL.c **** dataOffset += (pktSize - 3u); - 876:.\Generated_Source\PSoC5/BL.c **** - 877:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 878:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 879:.\Generated_Source\PSoC5/BL.c **** (btldrData <= BL_LAST_EE_ARRAYID)) - 880:.\Generated_Source\PSoC5/BL.c **** { - 881:.\Generated_Source\PSoC5/BL.c **** - 882:.\Generated_Source\PSoC5/BL.c **** CyEEPROM_Start(); - 883:.\Generated_Source\PSoC5/BL.c **** - 884:.\Generated_Source\PSoC5/BL.c **** /* Size of EEPROM row */ - 885:.\Generated_Source\PSoC5/BL.c **** pktSize = CY_EEPROM_SIZEOF_ROW; - 886:.\Generated_Source\PSoC5/BL.c **** } - 887:.\Generated_Source\PSoC5/BL.c **** else - 888:.\Generated_Source\PSoC5/BL.c **** { - 889:.\Generated_Source\PSoC5/BL.c **** /* Size of FLASH row (depends on ECC configuration) */ - 890:.\Generated_Source\PSoC5/BL.c **** pktSize = BL_FROW_SIZE; - 891:.\Generated_Source\PSoC5/BL.c **** } - 892:.\Generated_Source\PSoC5/BL.c **** #else - 893:.\Generated_Source\PSoC5/BL.c **** /* Size of FLASH row (no ECC available) */ - 894:.\Generated_Source\PSoC5/BL.c **** pktSize = BL_FROW_SIZE; - 895:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ - 896:.\Generated_Source\PSoC5/BL.c **** - 897:.\Generated_Source\PSoC5/BL.c **** - 898:.\Generated_Source\PSoC5/BL.c **** /* Check if we have all data to program */ - 899:.\Generated_Source\PSoC5/BL.c **** if(dataOffset == pktSize) - 900:.\Generated_Source\PSoC5/BL.c **** { - 901:.\Generated_Source\PSoC5/BL.c **** /* Get FLASH/EEPROM row number */ - 902:.\Generated_Source\PSoC5/BL.c **** dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | - 903:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 1u]; - 904:.\Generated_Source\PSoC5/BL.c **** - 905:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 906:.\Generated_Source\PSoC5/BL.c **** if(btldrData <= BL_LAST_FLASH_ARRAYID) - 907:.\Generated_Source\PSoC5/BL.c **** { - 908:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ - 909:.\Generated_Source\PSoC5/BL.c **** - 910:.\Generated_Source\PSoC5/BL.c **** #if(0u == BL_DUAL_APP_BOOTLOADER) - 911:.\Generated_Source\PSoC5/BL.c **** - 912:.\Generated_Source\PSoC5/BL.c **** if(0u == clearedMetaData) - 913:.\Generated_Source\PSoC5/BL.c **** { - 914:.\Generated_Source\PSoC5/BL.c **** /* Metadata section must be filled with zeroes */ - 915:.\Generated_Source\PSoC5/BL.c **** - 916:.\Generated_Source\PSoC5/BL.c **** uint8 erase[BL_FROW_SIZE]; - 917:.\Generated_Source\PSoC5/BL.c **** - 918:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) - 919:.\Generated_Source\PSoC5/BL.c **** (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE); - 920:.\Generated_Source\PSoC5/BL.c **** #else - 921:.\Generated_Source\PSoC5/BL.c **** (void) memset(erase, 0, BL_FROW_SIZE); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 18 - - - 922:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ - 923:.\Generated_Source\PSoC5/BL.c **** - 924:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC4) - 925:.\Generated_Source\PSoC5/BL.c **** (void) CySysFlashWriteRow(BL_MD_ROW, erase); - 926:.\Generated_Source\PSoC5/BL.c **** #else - 927:.\Generated_Source\PSoC5/BL.c **** (void) CyWriteRowFull((uint8) BL_MD_FLASH_ARRAY_NUM, - 928:.\Generated_Source\PSoC5/BL.c **** (uint16) BL_MD_ROW, - 929:.\Generated_Source\PSoC5/BL.c **** erase, - 930:.\Generated_Source\PSoC5/BL.c **** BL_FROW_SIZE); - 931:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC4) */ - 932:.\Generated_Source\PSoC5/BL.c **** - 933:.\Generated_Source\PSoC5/BL.c **** /* Set up flag that metadata was cleared */ - 934:.\Generated_Source\PSoC5/BL.c **** clearedMetaData = 1u; - 935:.\Generated_Source\PSoC5/BL.c **** } - 936:.\Generated_Source\PSoC5/BL.c **** - 937:.\Generated_Source\PSoC5/BL.c **** #else - 938:.\Generated_Source\PSoC5/BL.c **** - 939:.\Generated_Source\PSoC5/BL.c **** if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE) - 940:.\Generated_Source\PSoC5/BL.c **** { - 941:.\Generated_Source\PSoC5/BL.c **** /* First active bootloadable application row */ - 942:.\Generated_Source\PSoC5/BL.c **** uint16 firstRow = (uint16) 1u + - 943:.\Generated_Source\PSoC5/BL.c **** (uint16) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, - 944:.\Generated_Source\PSoC5/BL.c **** BL_activeApp); - 945:.\Generated_Source\PSoC5/BL.c **** - 946:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC4) - 947:.\Generated_Source\PSoC5/BL.c **** uint16 row = dataOffset; - 948:.\Generated_Source\PSoC5/BL.c **** #else - 949:.\Generated_Source\PSoC5/BL.c **** uint16 row = (uint16)(btldrData * (CYDEV_FLS_SECTOR_SIZE / CYDE - 950:.\Generated_Source\PSoC5/BL.c **** dataOffset; - 951:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC4) */ - 952:.\Generated_Source\PSoC5/BL.c **** - 953:.\Generated_Source\PSoC5/BL.c **** - 954:.\Generated_Source\PSoC5/BL.c **** /****************************************************************** - 955:.\Generated_Source\PSoC5/BL.c **** * Last row is equal to the first row plus the number of rows availa - 956:.\Generated_Source\PSoC5/BL.c **** * app. To compute this, we first subtract the number of appliaction - 957:.\Generated_Source\PSoC5/BL.c **** * the total flash rows: (CY_FLASH_NUMBER_ROWS - 2u). - 958:.\Generated_Source\PSoC5/BL.c **** * - 959:.\Generated_Source\PSoC5/BL.c **** * Then subtract off the first row: - 960:.\Generated_Source\PSoC5/BL.c **** * App Rows = (CY_FLASH_NUMBER_ROWS - 2u - firstRow) - 961:.\Generated_Source\PSoC5/BL.c **** * Then divide that number by the number of application that must fi - 962:.\Generated_Source\PSoC5/BL.c **** * space, if we are app1 then that number is 2, if app2 then 1. Our - 963:.\Generated_Source\PSoC5/BL.c **** * then: (2u - BL_activeApp). - 964:.\Generated_Source\PSoC5/BL.c **** * - 965:.\Generated_Source\PSoC5/BL.c **** * Adding this number to firstRow gives the address right beyond our - 966:.\Generated_Source\PSoC5/BL.c **** * so we subtract 1. - 967:.\Generated_Source\PSoC5/BL.c **** ******************************************************************* - 968:.\Generated_Source\PSoC5/BL.c **** uint16 lastRow = (firstRow - 1u) + - 969:.\Generated_Source\PSoC5/BL.c **** ((uint16)((CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) - 970:.\Generated_Source\PSoC5/BL.c **** ((uint16)2u - (uint16)BL_activeApp)); - 971:.\Generated_Source\PSoC5/BL.c **** - 972:.\Generated_Source\PSoC5/BL.c **** - 973:.\Generated_Source\PSoC5/BL.c **** /****************************************************************** - 974:.\Generated_Source\PSoC5/BL.c **** * Check to see if the row to program is within the range of the act - 975:.\Generated_Source\PSoC5/BL.c **** * application, or if it maches the active application's metadata ro - 976:.\Generated_Source\PSoC5/BL.c **** * refuse to program as it would corrupt the active app. - 977:.\Generated_Source\PSoC5/BL.c **** ******************************************************************* - 978:.\Generated_Source\PSoC5/BL.c **** if(((row >= firstRow) && (row <= lastRow)) || - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 19 - - - 979:.\Generated_Source\PSoC5/BL.c **** ((btldrData == BL_MD_FLASH_ARRAY_NUM) && - 980:.\Generated_Source\PSoC5/BL.c **** (dataOffset == BL_MD_ROW_NUM(BL_activeApp)))) - 981:.\Generated_Source\PSoC5/BL.c **** { - 982:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_ACTIVE; - 983:.\Generated_Source\PSoC5/BL.c **** dataOffset = 0u; - 984:.\Generated_Source\PSoC5/BL.c **** break; - 985:.\Generated_Source\PSoC5/BL.c **** } - 986:.\Generated_Source\PSoC5/BL.c **** } - 987:.\Generated_Source\PSoC5/BL.c **** - 988:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ - 989:.\Generated_Source\PSoC5/BL.c **** - 990:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) - 991:.\Generated_Source\PSoC5/BL.c **** } - 992:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ - 993:.\Generated_Source\PSoC5/BL.c **** - 994:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC4) - 995:.\Generated_Source\PSoC5/BL.c **** - 996:.\Generated_Source\PSoC5/BL.c **** ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) dataOffset, dat - 997:.\Generated_Source\PSoC5/BL.c **** ? BL_ERR_ROW \ - 998:.\Generated_Source\PSoC5/BL.c **** : CYRET_SUCCESS; - 999:.\Generated_Source\PSoC5/BL.c **** -1000:.\Generated_Source\PSoC5/BL.c **** #else -1001:.\Generated_Source\PSoC5/BL.c **** -1002:.\Generated_Source\PSoC5/BL.c **** ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataB -1003:.\Generated_Source\PSoC5/BL.c **** ? BL_ERR_ROW \ -1004:.\Generated_Source\PSoC5/BL.c **** : CYRET_SUCCESS; -1005:.\Generated_Source\PSoC5/BL.c **** -1006:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC4) */ -1007:.\Generated_Source\PSoC5/BL.c **** -1008:.\Generated_Source\PSoC5/BL.c **** } -1009:.\Generated_Source\PSoC5/BL.c **** else -1010:.\Generated_Source\PSoC5/BL.c **** { -1011:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_LENGTH; -1012:.\Generated_Source\PSoC5/BL.c **** } -1013:.\Generated_Source\PSoC5/BL.c **** -1014:.\Generated_Source\PSoC5/BL.c **** dataOffset = 0u; -1015:.\Generated_Source\PSoC5/BL.c **** } -1016:.\Generated_Source\PSoC5/BL.c **** break; -1017:.\Generated_Source\PSoC5/BL.c **** -1018:.\Generated_Source\PSoC5/BL.c **** -1019:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** -1020:.\Generated_Source\PSoC5/BL.c **** * Sync bootloader -1021:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ -1022:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) -1023:.\Generated_Source\PSoC5/BL.c **** -1024:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_SYNC: -1025:.\Generated_Source\PSoC5/BL.c **** -1026:.\Generated_Source\PSoC5/BL.c **** if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) -1027:.\Generated_Source\PSoC5/BL.c **** { -1028:.\Generated_Source\PSoC5/BL.c **** /* If something failed the host would send this command to reset the bootloader -1029:.\Generated_Source\PSoC5/BL.c **** dataOffset = 0u; -1030:.\Generated_Source\PSoC5/BL.c **** -1031:.\Generated_Source\PSoC5/BL.c **** /* Don't ack the packet, just get ready to accept the next one */ -1032:.\Generated_Source\PSoC5/BL.c **** continue; -1033:.\Generated_Source\PSoC5/BL.c **** } -1034:.\Generated_Source\PSoC5/BL.c **** break; -1035:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 20 - - -1036:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) */ -1037:.\Generated_Source\PSoC5/BL.c **** -1038:.\Generated_Source\PSoC5/BL.c **** -1039:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** -1040:.\Generated_Source\PSoC5/BL.c **** * Set active application -1041:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ -1042:.\Generated_Source\PSoC5/BL.c **** #if(0u != BL_DUAL_APP_BOOTLOADER) -1043:.\Generated_Source\PSoC5/BL.c **** -1044:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_APP_ACTIVE: -1045:.\Generated_Source\PSoC5/BL.c **** -1046:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) -1047:.\Generated_Source\PSoC5/BL.c **** { -1048:.\Generated_Source\PSoC5/BL.c **** if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) -1049:.\Generated_Source\PSoC5/BL.c **** { -1050:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA idx; -1051:.\Generated_Source\PSoC5/BL.c **** -1052:.\Generated_Source\PSoC5/BL.c **** for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++) -1053:.\Generated_Source\PSoC5/BL.c **** { -1054:.\Generated_Source\PSoC5/BL.c **** BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx), -1055:.\Generated_Source\PSoC5/BL.c **** (uint8 )(idx == btldrData)); -1056:.\Generated_Source\PSoC5/BL.c **** } -1057:.\Generated_Source\PSoC5/BL.c **** BL_activeApp = btldrData; -1058:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; -1059:.\Generated_Source\PSoC5/BL.c **** } -1060:.\Generated_Source\PSoC5/BL.c **** else -1061:.\Generated_Source\PSoC5/BL.c **** { -1062:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_APP; -1063:.\Generated_Source\PSoC5/BL.c **** } -1064:.\Generated_Source\PSoC5/BL.c **** } -1065:.\Generated_Source\PSoC5/BL.c **** break; -1066:.\Generated_Source\PSoC5/BL.c **** -1067:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ -1068:.\Generated_Source\PSoC5/BL.c **** -1069:.\Generated_Source\PSoC5/BL.c **** -1070:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** -1071:.\Generated_Source\PSoC5/BL.c **** * Send data -1072:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ -1073:.\Generated_Source\PSoC5/BL.c **** #if (0u != BL_CMD_SEND_DATA_AVAIL) -1074:.\Generated_Source\PSoC5/BL.c **** -1075:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_DATA: -1076:.\Generated_Source\PSoC5/BL.c **** -1077:.\Generated_Source\PSoC5/BL.c **** if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) -1078:.\Generated_Source\PSoC5/BL.c **** { -1079:.\Generated_Source\PSoC5/BL.c **** /* Make sure that dataOffset is valid before copying the data */ -1080:.\Generated_Source\PSoC5/BL.c **** if((dataOffset + pktSize) <= BL_SIZEOF_COMMAND_BUFFER) -1081:.\Generated_Source\PSoC5/BL.c **** { -1082:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; -1083:.\Generated_Source\PSoC5/BL.c **** -1084:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) -1085:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&dataBuffer[dataOffset], -1086:.\Generated_Source\PSoC5/BL.c **** &packetBuffer[BL_DATA_ADDR], -1087:.\Generated_Source\PSoC5/BL.c **** ( int16 )pktSize); -1088:.\Generated_Source\PSoC5/BL.c **** #else -1089:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&dataBuffer[dataOffset], -1090:.\Generated_Source\PSoC5/BL.c **** &packetBuffer[BL_DATA_ADDR], -1091:.\Generated_Source\PSoC5/BL.c **** pktSize); -1092:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 21 - - -1093:.\Generated_Source\PSoC5/BL.c **** -1094:.\Generated_Source\PSoC5/BL.c **** dataOffset += pktSize; -1095:.\Generated_Source\PSoC5/BL.c **** } -1096:.\Generated_Source\PSoC5/BL.c **** else -1097:.\Generated_Source\PSoC5/BL.c **** { -1098:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_LENGTH; -1099:.\Generated_Source\PSoC5/BL.c **** } -1100:.\Generated_Source\PSoC5/BL.c **** } -1101:.\Generated_Source\PSoC5/BL.c **** -1102:.\Generated_Source\PSoC5/BL.c **** break; -1103:.\Generated_Source\PSoC5/BL.c **** -1104:.\Generated_Source\PSoC5/BL.c **** #endif /* (0u != BL_CMD_SEND_DATA_AVAIL) */ -1105:.\Generated_Source\PSoC5/BL.c **** -1106:.\Generated_Source\PSoC5/BL.c **** -1107:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** -1108:.\Generated_Source\PSoC5/BL.c **** * Enter bootloader -1109:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ -1110:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_ENTER: -1111:.\Generated_Source\PSoC5/BL.c **** -1112:.\Generated_Source\PSoC5/BL.c **** if(pktSize == 0u) -1113:.\Generated_Source\PSoC5/BL.c **** { -1114:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) -1115:.\Generated_Source\PSoC5/BL.c **** -1116:.\Generated_Source\PSoC5/BL.c **** BL_ENTER CYDATA BtldrVersion = -1117:.\Generated_Source\PSoC5/BL.c **** {CYSWAP_ENDIAN32(CYDEV_CHIP_JTAG_ID), CYDEV_CHIP_REV_EXPECT, BL_VERSION -1118:.\Generated_Source\PSoC5/BL.c **** -1119:.\Generated_Source\PSoC5/BL.c **** #else -1120:.\Generated_Source\PSoC5/BL.c **** -1121:.\Generated_Source\PSoC5/BL.c **** BL_ENTER CYDATA BtldrVersion = -1122:.\Generated_Source\PSoC5/BL.c **** {CYDEV_CHIP_JTAG_ID, CYDEV_CHIP_REV_EXPECT, BL_VERSION}; -1123:.\Generated_Source\PSoC5/BL.c **** -1124:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ -1125:.\Generated_Source\PSoC5/BL.c **** -1126:.\Generated_Source\PSoC5/BL.c **** communicationState = BL_COMMUNICATION_STATE_ACTIVE; -1127:.\Generated_Source\PSoC5/BL.c **** -1128:.\Generated_Source\PSoC5/BL.c **** rspSize = sizeof(BL_ENTER); -1129:.\Generated_Source\PSoC5/BL.c **** -1130:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC3) -1131:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&packetBuffer[BL_DATA_ADDR], -1132:.\Generated_Source\PSoC5/BL.c **** &BtldrVersion, -1133:.\Generated_Source\PSoC5/BL.c **** ( int16 )rspSize); -1134:.\Generated_Source\PSoC5/BL.c **** #else -1135:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&packetBuffer[BL_DATA_ADDR], -1136:.\Generated_Source\PSoC5/BL.c **** &BtldrVersion, -1137:.\Generated_Source\PSoC5/BL.c **** rspSize); -1138:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC3) */ -1139:.\Generated_Source\PSoC5/BL.c **** -1140:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; -1141:.\Generated_Source\PSoC5/BL.c **** } -1142:.\Generated_Source\PSoC5/BL.c **** break; -1143:.\Generated_Source\PSoC5/BL.c **** -1144:.\Generated_Source\PSoC5/BL.c **** -1145:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** -1146:.\Generated_Source\PSoC5/BL.c **** * Verify row -1147:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ -1148:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_VERIFY: -1149:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 22 - - -1150:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) -1151:.\Generated_Source\PSoC5/BL.c **** { -1152:.\Generated_Source\PSoC5/BL.c **** /* Get FLASH/EEPROM row number */ -1153:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA rowNum = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u) -1154:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 1u]; -1155:.\Generated_Source\PSoC5/BL.c **** -1156:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) -1157:.\Generated_Source\PSoC5/BL.c **** -1158:.\Generated_Source\PSoC5/BL.c **** uint32 CYDATA rowAddr; -1159:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA checksum; -1160:.\Generated_Source\PSoC5/BL.c **** -1161:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && -1162:.\Generated_Source\PSoC5/BL.c **** (btldrData <= BL_LAST_EE_ARRAYID)) -1163:.\Generated_Source\PSoC5/BL.c **** { -1164:.\Generated_Source\PSoC5/BL.c **** /* EEPROM */ -1165:.\Generated_Source\PSoC5/BL.c **** /* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */ -1166:.\Generated_Source\PSoC5/BL.c **** rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE; -1167:.\Generated_Source\PSoC5/BL.c **** -1168:.\Generated_Source\PSoC5/BL.c **** checksum = BL_Calc8BitEepromSum(rowAddr, CYDEV_EEPROM_ROW_SIZE); -1169:.\Generated_Source\PSoC5/BL.c **** } -1170:.\Generated_Source\PSoC5/BL.c **** else -1171:.\Generated_Source\PSoC5/BL.c **** { -1172:.\Generated_Source\PSoC5/BL.c **** /* FLASH */ -1173:.\Generated_Source\PSoC5/BL.c **** rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) -1174:.\Generated_Source\PSoC5/BL.c **** + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); -1175:.\Generated_Source\PSoC5/BL.c **** -1176:.\Generated_Source\PSoC5/BL.c **** checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE); -1177:.\Generated_Source\PSoC5/BL.c **** } -1178:.\Generated_Source\PSoC5/BL.c **** -1179:.\Generated_Source\PSoC5/BL.c **** #else -1180:.\Generated_Source\PSoC5/BL.c **** -1181:.\Generated_Source\PSoC5/BL.c **** uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) -1182:.\Generated_Source\PSoC5/BL.c **** + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); -1183:.\Generated_Source\PSoC5/BL.c **** -1184:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE); -1185:.\Generated_Source\PSoC5/BL.c **** -1186:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) */ -1187:.\Generated_Source\PSoC5/BL.c **** -1188:.\Generated_Source\PSoC5/BL.c **** -1189:.\Generated_Source\PSoC5/BL.c **** /* Calculate checksum on data from ECC */ -1190:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) -1191:.\Generated_Source\PSoC5/BL.c **** -1192:.\Generated_Source\PSoC5/BL.c **** if(btldrData <= BL_LAST_FLASH_ARRAYID) -1193:.\Generated_Source\PSoC5/BL.c **** { -1194:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA tmpIndex; -1195:.\Generated_Source\PSoC5/BL.c **** -1196:.\Generated_Source\PSoC5/BL.c **** rowAddr = CYDEV_ECC_BASE + ((uint32)btldrData * (CYDEV_FLS_SECTOR_SIZE -1197:.\Generated_Source\PSoC5/BL.c **** + ((uint32)rowNum * CYDEV_ECC_ROW_SIZE); -1198:.\Generated_Source\PSoC5/BL.c **** -1199:.\Generated_Source\PSoC5/BL.c **** for(tmpIndex = 0u; tmpIndex < CYDEV_ECC_ROW_SIZE; tmpIndex++) -1200:.\Generated_Source\PSoC5/BL.c **** { -1201:.\Generated_Source\PSoC5/BL.c **** checksum += CY_GET_XTND_REG8((uint8 CYFAR *)(rowAddr + tmpIndex)); -1202:.\Generated_Source\PSoC5/BL.c **** } -1203:.\Generated_Source\PSoC5/BL.c **** } -1204:.\Generated_Source\PSoC5/BL.c **** -1205:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) */ -1206:.\Generated_Source\PSoC5/BL.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 23 - - -1207:.\Generated_Source\PSoC5/BL.c **** -1208:.\Generated_Source\PSoC5/BL.c **** /****************************************************************************** -1209:.\Generated_Source\PSoC5/BL.c **** * App Verified & App Active are information that is updated in flash at runtime -1210:.\Generated_Source\PSoC5/BL.c **** * remove these items from the checksum to allow the host to verify everything i -1211:.\Generated_Source\PSoC5/BL.c **** * correct. -1212:.\Generated_Source\PSoC5/BL.c **** ****************************************************************************** -1213:.\Generated_Source\PSoC5/BL.c **** if((BL_MD_FLASH_ARRAY_NUM == btldrData) && -1214:.\Generated_Source\PSoC5/BL.c **** (BL_CONTAIN_METADATA(rowNum))) -1215:.\Generated_Source\PSoC5/BL.c **** { -1216:.\Generated_Source\PSoC5/BL.c **** checksum -= BL_MD_BTLDB_ACTIVE_VALUE (BL_GET_APP_ID(rowNum)); -1217:.\Generated_Source\PSoC5/BL.c **** checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum)); -1218:.\Generated_Source\PSoC5/BL.c **** } -1219:.\Generated_Source\PSoC5/BL.c **** -1220:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum); -1221:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; -1222:.\Generated_Source\PSoC5/BL.c **** rspSize = 1u; -1223:.\Generated_Source\PSoC5/BL.c **** } -1224:.\Generated_Source\PSoC5/BL.c **** break; -1225:.\Generated_Source\PSoC5/BL.c **** -1226:.\Generated_Source\PSoC5/BL.c **** -1227:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** -1228:.\Generated_Source\PSoC5/BL.c **** * Exit bootloader -1229:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ -1230:.\Generated_Source\PSoC5/BL.c **** case BL_COMMAND_EXIT: -1231:.\Generated_Source\PSoC5/BL.c **** -1232:.\Generated_Source\PSoC5/BL.c **** if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp)) -1233:.\Generated_Source\PSoC5/BL.c **** { -1234:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(BL_START_APP); -1235:.\Generated_Source\PSoC5/BL.c **** } -1236:.\Generated_Source\PSoC5/BL.c **** -1237:.\Generated_Source\PSoC5/BL.c **** CySoftwareReset(); -1238:.\Generated_Source\PSoC5/BL.c **** -1239:.\Generated_Source\PSoC5/BL.c **** /* Will never get here */ -1240:.\Generated_Source\PSoC5/BL.c **** break; -1241:.\Generated_Source\PSoC5/BL.c **** -1242:.\Generated_Source\PSoC5/BL.c **** -1243:.\Generated_Source\PSoC5/BL.c **** /*************************************************************************** -1244:.\Generated_Source\PSoC5/BL.c **** * Unsupported command -1245:.\Generated_Source\PSoC5/BL.c **** ***************************************************************************/ -1246:.\Generated_Source\PSoC5/BL.c **** default: -1247:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_CMD; -1248:.\Generated_Source\PSoC5/BL.c **** break; -1249:.\Generated_Source\PSoC5/BL.c **** } -1250:.\Generated_Source\PSoC5/BL.c **** } -1251:.\Generated_Source\PSoC5/BL.c **** -1252:.\Generated_Source\PSoC5/BL.c **** /* ?CK the packet and function. */ -1253:.\Generated_Source\PSoC5/BL.c **** (void) BL_WritePacket(ackCode, packetBuffer, rspSize); -1254:.\Generated_Source\PSoC5/BL.c **** -1255:.\Generated_Source\PSoC5/BL.c **** } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState)); -1256:.\Generated_Source\PSoC5/BL.c **** } -1257:.\Generated_Source\PSoC5/BL.c **** -1258:.\Generated_Source\PSoC5/BL.c **** -1259:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* -1260:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_WritePacket -1261:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** -1262:.\Generated_Source\PSoC5/BL.c **** * -1263:.\Generated_Source\PSoC5/BL.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 24 - - -1264:.\Generated_Source\PSoC5/BL.c **** * Creates a bootloader responce packet and transmits it back to the bootloader -1265:.\Generated_Source\PSoC5/BL.c **** * host application over the already established communications protocol. -1266:.\Generated_Source\PSoC5/BL.c **** * -1267:.\Generated_Source\PSoC5/BL.c **** * Parameters: -1268:.\Generated_Source\PSoC5/BL.c **** * status: -1269:.\Generated_Source\PSoC5/BL.c **** * The status code to pass back as the second byte of the packet -1270:.\Generated_Source\PSoC5/BL.c **** * buffer: -1271:.\Generated_Source\PSoC5/BL.c **** * The buffer containing the data portion of the packet -1272:.\Generated_Source\PSoC5/BL.c **** * size: -1273:.\Generated_Source\PSoC5/BL.c **** * The number of bytes contained within the buffer to pass back -1274:.\Generated_Source\PSoC5/BL.c **** * -1275:.\Generated_Source\PSoC5/BL.c **** * Return: -1276:.\Generated_Source\PSoC5/BL.c **** * CYRET_SUCCESS if successful. -1277:.\Generated_Source\PSoC5/BL.c **** * CYRET_UNKNOWN if there was an error tranmitting the packet. -1278:.\Generated_Source\PSoC5/BL.c **** * -1279:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ -1280:.\Generated_Source\PSoC5/BL.c **** static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ -1281:.\Generated_Source\PSoC5/BL.c **** -1282:.\Generated_Source\PSoC5/BL.c **** { -1283:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA checksum; -1284:.\Generated_Source\PSoC5/BL.c **** -1285:.\Generated_Source\PSoC5/BL.c **** /* Start of the packet. */ -1286:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SOP_ADDR] = BL_SOP; -1287:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CMD_ADDR] = status; -1288:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SIZE_ADDR] = LO8(size); -1289:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SIZE_ADDR + 1u] = HI8(size); -1290:.\Generated_Source\PSoC5/BL.c **** -1291:.\Generated_Source\PSoC5/BL.c **** /* Compute the checksum. */ -1292:.\Generated_Source\PSoC5/BL.c **** checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR); -1293:.\Generated_Source\PSoC5/BL.c **** -1294:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CHK_ADDR(size)] = LO8(checksum); -1295:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum); -1296:.\Generated_Source\PSoC5/BL.c **** buffer[BL_EOP_ADDR(size)] = BL_EOP; -1297:.\Generated_Source\PSoC5/BL.c **** -1298:.\Generated_Source\PSoC5/BL.c **** /* Start the packet transmit. */ -1299:.\Generated_Source\PSoC5/BL.c **** return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u)); -1300:.\Generated_Source\PSoC5/BL.c **** } -1301:.\Generated_Source\PSoC5/BL.c **** -1302:.\Generated_Source\PSoC5/BL.c **** -1303:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* -1304:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_SetFlashByte -1305:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** -1306:.\Generated_Source\PSoC5/BL.c **** * -1307:.\Generated_Source\PSoC5/BL.c **** * Summary: -1308:.\Generated_Source\PSoC5/BL.c **** * Writes byte a flash memory location -1309:.\Generated_Source\PSoC5/BL.c **** * -1310:.\Generated_Source\PSoC5/BL.c **** * Parameters: -1311:.\Generated_Source\PSoC5/BL.c **** * address: -1312:.\Generated_Source\PSoC5/BL.c **** * Address in Flash memory where data will be written -1313:.\Generated_Source\PSoC5/BL.c **** * -1314:.\Generated_Source\PSoC5/BL.c **** * runType: -1315:.\Generated_Source\PSoC5/BL.c **** * Byte to be written -1316:.\Generated_Source\PSoC5/BL.c **** * -1317:.\Generated_Source\PSoC5/BL.c **** * Return: -1318:.\Generated_Source\PSoC5/BL.c **** * None -1319:.\Generated_Source\PSoC5/BL.c **** * -1320:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 25 - - -1321:.\Generated_Source\PSoC5/BL.c **** void BL_SetFlashByte(uint32 address, uint8 runType) -1322:.\Generated_Source\PSoC5/BL.c **** { -1323:.\Generated_Source\PSoC5/BL.c **** uint32 flsAddr = address - CYDEV_FLASH_BASE; -1324:.\Generated_Source\PSoC5/BL.c **** uint8 rowData[CYDEV_FLS_ROW_SIZE]; -1325:.\Generated_Source\PSoC5/BL.c **** -1326:.\Generated_Source\PSoC5/BL.c **** #if !(CY_PSOC4) -1327:.\Generated_Source\PSoC5/BL.c **** uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); -1328:.\Generated_Source\PSoC5/BL.c **** #endif /* !(CY_PSOC4) */ -1329:.\Generated_Source\PSoC5/BL.c **** -1330:.\Generated_Source\PSoC5/BL.c **** uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); -1331:.\Generated_Source\PSoC5/BL.c **** uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); -1332:.\Generated_Source\PSoC5/BL.c **** uint16 idx; -1333:.\Generated_Source\PSoC5/BL.c **** -1334:.\Generated_Source\PSoC5/BL.c **** for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) -1335:.\Generated_Source\PSoC5/BL.c **** { -1336:.\Generated_Source\PSoC5/BL.c **** rowData[idx] = BL_GET_CODE_BYTE(baseAddr + idx); -1337:.\Generated_Source\PSoC5/BL.c **** } -1338:.\Generated_Source\PSoC5/BL.c **** -1339:.\Generated_Source\PSoC5/BL.c **** rowData[address % CYDEV_FLS_ROW_SIZE] = runType; -1340:.\Generated_Source\PSoC5/BL.c **** -1341:.\Generated_Source\PSoC5/BL.c **** #if(CY_PSOC4) -1342:.\Generated_Source\PSoC5/BL.c **** (void) CySysFlashWriteRow((uint32) rowNum, rowData); -1343:.\Generated_Source\PSoC5/BL.c **** #else -1344:.\Generated_Source\PSoC5/BL.c **** (void) CyWriteRowData(arrayId, rowNum, rowData); -1345:.\Generated_Source\PSoC5/BL.c **** #endif /* (CY_PSOC4) */ -1346:.\Generated_Source\PSoC5/BL.c **** } -1347:.\Generated_Source\PSoC5/BL.c **** -1348:.\Generated_Source\PSoC5/BL.c **** -1349:.\Generated_Source\PSoC5/BL.c **** /******************************************************************************* -1350:.\Generated_Source\PSoC5/BL.c **** * Function Name: BL_GetMetadata -1351:.\Generated_Source\PSoC5/BL.c **** ******************************************************************************** -1352:.\Generated_Source\PSoC5/BL.c **** * -1353:.\Generated_Source\PSoC5/BL.c **** * Summary: -1354:.\Generated_Source\PSoC5/BL.c **** * Returns value of the multi-byte field. -1355:.\Generated_Source\PSoC5/BL.c **** * -1356:.\Generated_Source\PSoC5/BL.c **** * Parameters: -1357:.\Generated_Source\PSoC5/BL.c **** * fieldName: -1358:.\Generated_Source\PSoC5/BL.c **** * The field to get data from: -1359:.\Generated_Source\PSoC5/BL.c **** * BL_GET_METADATA_BTLDB_ADDR -1360:.\Generated_Source\PSoC5/BL.c **** * BL_GET_METADATA_BTLDR_LAST_ROW -1361:.\Generated_Source\PSoC5/BL.c **** * BL_GET_METADATA_BTLDB_LENGTH -1362:.\Generated_Source\PSoC5/BL.c **** * BL_GET_METADATA_BTLDR_APP_VERSION -1363:.\Generated_Source\PSoC5/BL.c **** * BL_GET_METADATA_BTLDB_APP_VERSION -1364:.\Generated_Source\PSoC5/BL.c **** * BL_GET_METADATA_BTLDB_APP_ID -1365:.\Generated_Source\PSoC5/BL.c **** * BL_GET_METADATA_BTLDB_APP_CUST_ID -1366:.\Generated_Source\PSoC5/BL.c **** * -1367:.\Generated_Source\PSoC5/BL.c **** * appId: -1368:.\Generated_Source\PSoC5/BL.c **** * Number of the bootlodable application. -1369:.\Generated_Source\PSoC5/BL.c **** * -1370:.\Generated_Source\PSoC5/BL.c **** * Return: -1371:.\Generated_Source\PSoC5/BL.c **** * None -1372:.\Generated_Source\PSoC5/BL.c **** * -1373:.\Generated_Source\PSoC5/BL.c **** *******************************************************************************/ -1374:.\Generated_Source\PSoC5/BL.c **** static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId) - 49 .loc 1 1374 0 - 50 .cfi_startproc - 51 @ args = 0, pretend = 0, frame = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 26 - - - 52 @ frame_needed = 0, uses_anonymous_args = 0 - 53 .LVL1: -1375:.\Generated_Source\PSoC5/BL.c **** { -1376:.\Generated_Source\PSoC5/BL.c **** uint32 fieldPtr; -1377:.\Generated_Source\PSoC5/BL.c **** uint8 fieldSize = 2u; -1378:.\Generated_Source\PSoC5/BL.c **** uint32 result; -1379:.\Generated_Source\PSoC5/BL.c **** -1380:.\Generated_Source\PSoC5/BL.c **** switch (fieldName) - 54 .loc 1 1380 0 - 55 0000 431E subs r3, r0, #1 -1374:.\Generated_Source\PSoC5/BL.c **** static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId) - 56 .loc 1 1374 0 - 57 0002 10B5 push {r4, lr} - 58 .LCFI0: - 59 .cfi_def_cfa_offset 8 - 60 .cfi_offset 4, -8 - 61 .cfi_offset 14, -4 -1374:.\Generated_Source\PSoC5/BL.c **** static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId) - 62 .loc 1 1374 0 - 63 0004 0246 mov r2, r0 - 64 .loc 1 1380 0 - 65 0006 062B cmp r3, #6 - 66 0008 0DD8 bhi .L3 - 67 000a DFE803F0 tbb [pc, r3] - 68 .L11: - 69 000e 06 .byte (.L4-.L11)/2 - 70 000f 0E .byte (.L16-.L11)/2 - 71 0010 23 .byte (.L17-.L11)/2 - 72 0011 04 .byte (.L7-.L11)/2 - 73 0012 08 .byte (.L8-.L11)/2 - 74 0013 0A .byte (.L9-.L11)/2 - 75 0014 21 .byte (.L10-.L11)/2 - 76 0015 00 .align 1 - 77 .L7: -1381:.\Generated_Source\PSoC5/BL.c **** { -1382:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDB_APP_CUST_ID: -1383:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId); -1384:.\Generated_Source\PSoC5/BL.c **** fieldSize = 4u; -1385:.\Generated_Source\PSoC5/BL.c **** break; -1386:.\Generated_Source\PSoC5/BL.c **** -1387:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDR_APP_VERSION: -1388:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId); - 78 .loc 1 1388 0 - 79 0016 1648 ldr r0, .L26 - 80 .LVL2: - 81 0018 08E0 b .L5 - 82 .LVL3: - 83 .L4: -1389:.\Generated_Source\PSoC5/BL.c **** break; -1390:.\Generated_Source\PSoC5/BL.c **** -1391:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDB_ADDR: -1392:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDB_ADDR_OFFSET(appId); - 84 .loc 1 1392 0 - 85 001a 164B ldr r3, .L26+4 - 86 001c 1BE0 b .L6 - 87 .L8: - 88 .LVL4: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 27 - - -1393:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC3) -1394:.\Generated_Source\PSoC5/BL.c **** fieldSize = 4u; -1395:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC3) */ -1396:.\Generated_Source\PSoC5/BL.c **** break; -1397:.\Generated_Source\PSoC5/BL.c **** -1398:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDR_LAST_ROW: -1399:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDR_LAST_ROW_OFFSET(appId); -1400:.\Generated_Source\PSoC5/BL.c **** break; -1401:.\Generated_Source\PSoC5/BL.c **** -1402:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDB_LENGTH: -1403:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDB_LENGTH_OFFSET(appId); -1404:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC3) -1405:.\Generated_Source\PSoC5/BL.c **** fieldSize = 4u; -1406:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC3) */ -1407:.\Generated_Source\PSoC5/BL.c **** break; -1408:.\Generated_Source\PSoC5/BL.c **** -1409:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDB_APP_VERSION: -1410:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDB_APP_VERSION_OFFSET(appId); - 89 .loc 1 1410 0 - 90 001e 1648 ldr r0, .L26+8 - 91 .LVL5: - 92 0020 04E0 b .L5 - 93 .LVL6: - 94 .L9: -1411:.\Generated_Source\PSoC5/BL.c **** break; -1412:.\Generated_Source\PSoC5/BL.c **** -1413:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDB_APP_ID: -1414:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDB_APP_ID_OFFSET(appId); - 95 .loc 1 1414 0 - 96 0022 1648 ldr r0, .L26+12 - 97 .LVL7: - 98 0024 02E0 b .L5 - 99 .LVL8: - 100 .L3: -1415:.\Generated_Source\PSoC5/BL.c **** break; -1416:.\Generated_Source\PSoC5/BL.c **** -1417:.\Generated_Source\PSoC5/BL.c **** default: -1418:.\Generated_Source\PSoC5/BL.c **** /* Should never be here */ -1419:.\Generated_Source\PSoC5/BL.c **** CYASSERT(0u != 0u); -1420:.\Generated_Source\PSoC5/BL.c **** fieldPtr = 0u; - 101 .loc 1 1420 0 - 102 0026 0020 movs r0, #0 - 103 .LVL9: - 104 0028 00E0 b .L5 - 105 .LVL10: - 106 .L16: -1399:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDR_LAST_ROW_OFFSET(appId); - 107 .loc 1 1399 0 - 108 002a 1548 ldr r0, .L26+16 - 109 .LVL11: - 110 .L5: -1421:.\Generated_Source\PSoC5/BL.c **** break; -1422:.\Generated_Source\PSoC5/BL.c **** } -1423:.\Generated_Source\PSoC5/BL.c **** -1424:.\Generated_Source\PSoC5/BL.c **** -1425:.\Generated_Source\PSoC5/BL.c **** /* Read all fields as big-endian */ -1426:.\Generated_Source\PSoC5/BL.c **** if (2u == fieldSize) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 28 - - -1427:.\Generated_Source\PSoC5/BL.c **** { -1428:.\Generated_Source\PSoC5/BL.c **** result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)); - 111 .loc 1 1428 0 - 112 002c 4178 ldrb r1, [r0, #1] @ zero_extendqisi2 - 113 .LVL12: -1429:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) fieldPtr ) << 8u; - 114 .loc 1 1429 0 - 115 002e 0078 ldrb r0, [r0, #0] @ zero_extendqisi2 - 116 .LVL13: - 117 0030 41EA0020 orr r0, r1, r0, lsl #8 - 118 .LVL14: - 119 .L15: -1430:.\Generated_Source\PSoC5/BL.c **** } -1431:.\Generated_Source\PSoC5/BL.c **** else -1432:.\Generated_Source\PSoC5/BL.c **** { -1433:.\Generated_Source\PSoC5/BL.c **** result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)); -1434:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u; -1435:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u; -1436:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u; -1437:.\Generated_Source\PSoC5/BL.c **** } -1438:.\Generated_Source\PSoC5/BL.c **** -1439:.\Generated_Source\PSoC5/BL.c **** /* Following fields should be little-endian */ -1440:.\Generated_Source\PSoC5/BL.c **** #if(!CY_PSOC3) -1441:.\Generated_Source\PSoC5/BL.c **** switch (fieldName) - 120 .loc 1 1441 0 - 121 0034 022A cmp r2, #2 - 122 0036 04D0 beq .L14 - 123 0038 032A cmp r2, #3 - 124 003a 07D0 beq .L13 - 125 003c 012A cmp r2, #1 - 126 003e 15D1 bne .L24 - 127 0040 04E0 b .L13 - 128 .L14: -1442:.\Generated_Source\PSoC5/BL.c **** { -1443:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDR_LAST_ROW: -1444:.\Generated_Source\PSoC5/BL.c **** result = CYSWAP_ENDIAN16(result); - 129 .loc 1 1444 0 - 130 0042 0202 lsls r2, r0, #8 - 131 0044 42EA1023 orr r3, r2, r0, lsr #8 - 132 0048 98B2 uxth r0, r3 - 133 .LVL15: - 134 004a 10BD pop {r4, pc} - 135 .L13: - 136 004c 00BA rev r0, r0 - 137 .LVL16: - 138 004e 10BD pop {r4, pc} - 139 .LVL17: - 140 .L10: -1383:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId); - 141 .loc 1 1383 0 - 142 0050 0C4B ldr r3, .L26+20 - 143 0052 00E0 b .L6 - 144 .L17: -1403:.\Generated_Source\PSoC5/BL.c **** fieldPtr = BL_MD_BTLDB_LENGTH_OFFSET(appId); - 145 .loc 1 1403 0 - 146 0054 0C4B ldr r3, .L26+24 - 147 .L6: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 29 - - - 148 .LVL18: -1433:.\Generated_Source\PSoC5/BL.c **** result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)); - 149 .loc 1 1433 0 - 150 0056 D878 ldrb r0, [r3, #3] @ zero_extendqisi2 - 151 .LVL19: -1434:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u; - 152 .loc 1 1434 0 - 153 0058 9C78 ldrb r4, [r3, #2] @ zero_extendqisi2 - 154 .LVL20: -1435:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u; - 155 .loc 1 1435 0 - 156 005a 5978 ldrb r1, [r3, #1] @ zero_extendqisi2 - 157 .LVL21: -1436:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u; - 158 .loc 1 1436 0 - 159 005c 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 160 .LVL22: -1434:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u; - 161 .loc 1 1434 0 - 162 005e 40EA0360 orr r0, r0, r3, lsl #24 - 163 .LVL23: -1435:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u; - 164 .loc 1 1435 0 - 165 0062 40EA0423 orr r3, r0, r4, lsl #8 -1436:.\Generated_Source\PSoC5/BL.c **** result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u; - 166 .loc 1 1436 0 - 167 0066 43EA0140 orr r0, r3, r1, lsl #16 - 168 .LVL24: - 169 006a E3E7 b .L15 - 170 .LVL25: - 171 .L24: -1445:.\Generated_Source\PSoC5/BL.c **** break; -1446:.\Generated_Source\PSoC5/BL.c **** -1447:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDB_ADDR: -1448:.\Generated_Source\PSoC5/BL.c **** case BL_GET_METADATA_BTLDB_LENGTH: -1449:.\Generated_Source\PSoC5/BL.c **** result = CYSWAP_ENDIAN32(result); -1450:.\Generated_Source\PSoC5/BL.c **** break; -1451:.\Generated_Source\PSoC5/BL.c **** -1452:.\Generated_Source\PSoC5/BL.c **** default: -1453:.\Generated_Source\PSoC5/BL.c **** break; -1454:.\Generated_Source\PSoC5/BL.c **** } -1455:.\Generated_Source\PSoC5/BL.c **** -1456:.\Generated_Source\PSoC5/BL.c **** #endif /* (!CY_PSOC3) */ -1457:.\Generated_Source\PSoC5/BL.c **** -1458:.\Generated_Source\PSoC5/BL.c **** return (result); -1459:.\Generated_Source\PSoC5/BL.c **** } - 172 .loc 1 1459 0 - 173 006c 10BD pop {r4, pc} - 174 .L27: - 175 006e 00BF .align 2 - 176 .L26: - 177 0070 D2FF0100 .word 131026 - 178 0074 C1FF0100 .word 131009 - 179 0078 D6FF0100 .word 131030 - 180 007c D4FF0100 .word 131028 - 181 0080 C5FF0100 .word 131013 - 182 0084 D8FF0100 .word 131032 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 30 - - - 183 0088 C9FF0100 .word 131017 - 184 .cfi_endproc - 185 .LFE69: - 186 .size BL_GetMetadata.constprop.1, .-BL_GetMetadata.constprop.1 - 187 .section .text.BL_ValidateBootloadable.constprop.0,"ax",%progbits - 188 .align 1 - 189 .thumb - 190 .thumb_func - 191 .type BL_ValidateBootloadable.constprop.0, %function - 192 BL_ValidateBootloadable.constprop.0: - 193 .LFB70: - 501:.\Generated_Source\PSoC5/BL.c **** static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ - 194 .loc 1 501 0 - 195 .cfi_startproc - 196 @ args = 0, pretend = 0, frame = 0 - 197 @ frame_needed = 0, uses_anonymous_args = 0 - 198 .LVL26: - 199 0000 70B5 push {r4, r5, r6, lr} - 200 .LCFI1: - 201 .cfi_def_cfa_offset 16 - 202 .cfi_offset 4, -16 - 203 .cfi_offset 5, -12 - 204 .cfi_offset 6, -8 - 205 .cfi_offset 14, -4 - 506:.\Generated_Source\PSoC5/BL.c **** uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) + - 206 .loc 1 506 0 - 207 0002 0220 movs r0, #2 - 208 0004 FFF7FEFF bl BL_GetMetadata.constprop.1 - 209 .LVL27: - 210 0008 0646 mov r6, r0 - 507:.\Generated_Source\PSoC5/BL.c **** BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH, - 211 .loc 1 507 0 - 212 000a 0320 movs r0, #3 - 213 000c FFF7FEFF bl BL_GetMetadata.constprop.1 - 214 .LVL28: - 506:.\Generated_Source\PSoC5/BL.c **** uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) + - 215 .loc 1 506 0 - 216 0010 711C adds r1, r6, #1 - 217 0012 00EB0126 add r6, r0, r1, lsl #8 - 218 .LVL29: - 535:.\Generated_Source\PSoC5/BL.c **** for(idx = BL_FIRST_APP_BYTE(appId); idx < end; ++idx) - 219 .loc 1 535 0 - 220 0016 0220 movs r0, #2 - 221 0018 FFF7FEFF bl BL_GetMetadata.constprop.1 - 222 .LVL30: - 511:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA calcedChecksum = 0u; - 223 .loc 1 511 0 - 224 001c 0024 movs r4, #0 - 535:.\Generated_Source\PSoC5/BL.c **** for(idx = BL_FIRST_APP_BYTE(appId); idx < end; ++idx) - 225 .loc 1 535 0 - 226 001e 0130 adds r0, r0, #1 - 227 0020 0102 lsls r1, r0, #8 - 228 .LVL31: - 510:.\Generated_Source\PSoC5/BL.c **** CYBIT valid = 0u; /* Assume bad flash image */ - 229 .loc 1 510 0 - 230 0022 2546 mov r5, r4 - 231 .LVL32: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 31 - - - 232 .L29: - 535:.\Generated_Source\PSoC5/BL.c **** for(idx = BL_FIRST_APP_BYTE(appId); idx < end; ++idx) - 233 .loc 1 535 0 - 234 0024 B142 cmp r1, r6 - 235 0026 09D2 bcs .L44 - 236 .L31: - 237 .LBB3: - 537:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA curByte = BL_GET_CODE_BYTE(idx); - 238 .loc 1 537 0 - 239 0028 11F8010B ldrb r0, [r1], #1 @ zero_extendqisi2 - 240 .LVL33: - 539:.\Generated_Source\PSoC5/BL.c **** if((curByte != 0u) && (curByte != 0xFFu)) - 241 .loc 1 539 0 - 242 002c 421E subs r2, r0, #1 - 243 002e D3B2 uxtb r3, r2 - 544:.\Generated_Source\PSoC5/BL.c **** calcedChecksum += curByte; - 244 .loc 1 544 0 - 245 0030 0419 adds r4, r0, r4 - 246 .LVL34: - 541:.\Generated_Source\PSoC5/BL.c **** valid = 1u; - 247 .loc 1 541 0 - 248 0032 FD2B cmp r3, #253 - 249 0034 98BF it ls - 250 0036 0125 movls r5, #1 - 251 .LVL35: - 544:.\Generated_Source\PSoC5/BL.c **** calcedChecksum += curByte; - 252 .loc 1 544 0 - 253 0038 E4B2 uxtb r4, r4 - 254 .LVL36: - 255 003a F3E7 b .L29 - 256 .LVL37: - 257 .L44: - 258 .LBE3: - 558:.\Generated_Source\PSoC5/BL.c **** idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u); - 259 .loc 1 558 0 - 260 003c 0220 movs r0, #2 - 261 003e FFF7FEFF bl BL_GetMetadata.constprop.1 - 262 .LVL38: - 563:.\Generated_Source\PSoC5/BL.c **** : (end >> 3u); - 263 .loc 1 563 0 - 264 0042 0F49 ldr r1, .L46 - 558:.\Generated_Source\PSoC5/BL.c **** idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u); - 265 .loc 1 558 0 - 266 0044 421C adds r2, r0, #1 - 267 0046 1302 lsls r3, r2, #8 - 268 0048 DB08 lsrs r3, r3, #3 - 269 .LVL39: - 563:.\Generated_Source\PSoC5/BL.c **** : (end >> 3u); - 270 .loc 1 563 0 - 271 004a 8E42 cmp r6, r1 - 272 004c 01D0 beq .L39 - 273 004e F608 lsrs r6, r6, #3 - 274 .LVL40: - 275 0050 01E0 b .L43 - 276 .LVL41: - 277 .L39: - 278 0052 4FF48046 mov r6, #16384 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 32 - - - 279 .LVL42: - 280 .L43: - 565:.\Generated_Source\PSoC5/BL.c **** for (; idx < end; ++idx) - 281 .loc 1 565 0 - 282 0056 B342 cmp r3, r6 - 283 0058 06D2 bcs .L45 - 284 .L34: - 501:.\Generated_Source\PSoC5/BL.c **** static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ - 285 .loc 1 501 0 - 286 005a 03F19041 add r1, r3, #1207959552 - 567:.\Generated_Source\PSoC5/BL.c **** calcedChecksum += CY_GET_XTND_REG8((volatile uint8 *)(CYDEV_ECC_BASE + idx)); - 287 .loc 1 567 0 - 288 005e 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 565:.\Generated_Source\PSoC5/BL.c **** for (; idx < end; ++idx) - 289 .loc 1 565 0 - 290 0060 0133 adds r3, r3, #1 - 291 .LVL43: - 567:.\Generated_Source\PSoC5/BL.c **** calcedChecksum += CY_GET_XTND_REG8((volatile uint8 *)(CYDEV_ECC_BASE + idx)); - 292 .loc 1 567 0 - 293 0062 0219 adds r2, r0, r4 - 294 0064 D4B2 uxtb r4, r2 - 295 .LVL44: - 296 0066 F6E7 b .L43 - 297 .LVL45: - 298 .L45: - 575:.\Generated_Source\PSoC5/BL.c **** if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) || - 299 .loc 1 575 0 - 300 0068 0548 ldr r0, .L46 - 573:.\Generated_Source\PSoC5/BL.c **** calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); - 301 .loc 1 573 0 - 302 006a 6442 negs r4, r4 - 303 .LVL46: - 575:.\Generated_Source\PSoC5/BL.c **** if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) || - 304 .loc 1 575 0 - 305 006c 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 306 006e E4B2 uxtb r4, r4 - 307 .LVL47: - 308 0070 9442 cmp r4, r2 - 309 0072 01D0 beq .L35 - 310 .L37: - 578:.\Generated_Source\PSoC5/BL.c **** return(CYRET_BAD_DATA); - 311 .loc 1 578 0 - 312 0074 0620 movs r0, #6 - 313 0076 70BD pop {r4, r5, r6, pc} - 314 .L35: - 575:.\Generated_Source\PSoC5/BL.c **** if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) || - 315 .loc 1 575 0 - 316 0078 002D cmp r5, #0 - 317 007a FBD0 beq .L37 - 588:.\Generated_Source\PSoC5/BL.c **** return(CYRET_SUCCESS); - 318 .loc 1 588 0 - 319 007c 0020 movs r0, #0 - 589:.\Generated_Source\PSoC5/BL.c **** } - 320 .loc 1 589 0 - 321 007e 70BD pop {r4, r5, r6, pc} - 322 .L47: - 323 .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 33 - - - 324 .L46: - 325 0080 C0FF0100 .word 131008 - 326 .cfi_endproc - 327 .LFE70: - 328 .size BL_ValidateBootloadable.constprop.0, .-BL_ValidateBootloadable.constprop.0 - 329 .section .text.BL_HostLink,"ax",%progbits - 330 .align 1 - 331 .thumb - 332 .thumb_func - 333 .type BL_HostLink, %function - 334 BL_HostLink: - 335 .LFB64: - 611:.\Generated_Source\PSoC5/BL.c **** { - 336 .loc 1 611 0 - 337 .cfi_startproc - 338 @ args = 0, pretend = 0, frame = 896 - 339 @ frame_needed = 0, uses_anonymous_args = 0 - 340 .LVL48: - 341 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 342 .LCFI2: - 343 .cfi_def_cfa_offset 36 - 344 .cfi_offset 4, -36 - 345 .cfi_offset 5, -32 - 346 .cfi_offset 6, -28 - 347 .cfi_offset 7, -24 - 348 .cfi_offset 8, -20 - 349 .cfi_offset 9, -16 - 350 .cfi_offset 10, -12 - 351 .cfi_offset 11, -8 - 352 .cfi_offset 14, -4 - 353 0004 ADF5617D sub sp, sp, #900 - 354 .LCFI3: - 355 .cfi_def_cfa_offset 936 - 611:.\Generated_Source\PSoC5/BL.c **** { - 356 .loc 1 611 0 - 357 0008 8046 mov r8, r0 - 632:.\Generated_Source\PSoC5/BL.c **** CyBtldrCommStart(); - 358 .loc 1 632 0 - 359 000a FFF7FEFF bl USBFS_CyBtldrCommStart - 360 .LVL49: - 635:.\Generated_Source\PSoC5/BL.c **** CyGlobalIntEnable; - 361 .loc 1 635 0 - 362 @ 635 ".\Generated_Source\PSoC5\BL.c" 1 - 363 000e 62B6 CPSIE i - 364 @ 0 "" 2 - 625:.\Generated_Source\PSoC5/BL.c **** CYBIT communicationState = BL_COMMUNICATION_STATE_IDLE; - 365 .loc 1 625 0 - 366 .thumb - 367 0010 0026 movs r6, #0 - 622:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA clearedMetaData = 0u; - 368 .loc 1 622 0 - 369 0012 B246 mov sl, r6 - 619:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA timeOutCnt = 10u; - 370 .loc 1 619 0 - 371 0014 4FF00A09 mov r9, #10 - 618:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA dataOffset = 0u; - 372 .loc 1 618 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 34 - - - 373 0018 3746 mov r7, r6 - 374 .LVL50: - 375 .L128: - 643:.\Generated_Source\PSoC5/BL.c **** readStat = CyBtldrCommRead(packetBuffer, - 376 .loc 1 643 0 - 377 001a B8F1000F cmp r8, #0 - 378 001e 01D1 bne .L86 - 379 .LVL51: - 380 .L112: - 381 0020 FF23 movs r3, #255 - 382 0022 00E0 b .L50 - 383 .LVL52: - 384 .L86: - 385 0024 4346 mov r3, r8 - 386 .LVL53: - 387 .L50: - 643:.\Generated_Source\PSoC5/BL.c **** readStat = CyBtldrCommRead(packetBuffer, - 388 .loc 1 643 0 is_stmt 0 discriminator 3 - 389 0026 4AA8 add r0, sp, #296 - 390 0028 4FF49671 mov r1, #300 - 391 002c 01AA add r2, sp, #4 - 392 002e FFF7FEFF bl USBFS_CyBtldrCommRead - 393 .LVL54: - 647:.\Generated_Source\PSoC5/BL.c **** if (0u != timeOut) - 394 .loc 1 647 0 is_stmt 1 discriminator 3 - 395 0032 B8F1000F cmp r8, #0 - 396 0036 03D0 beq .L51 - 649:.\Generated_Source\PSoC5/BL.c **** timeOutCnt--; - 397 .loc 1 649 0 - 398 0038 09F1FF39 add r9, r9, #-1 - 399 003c 5FFA89F9 uxtb r9, r9 - 400 .LVL55: - 401 .L51: - 652:.\Generated_Source\PSoC5/BL.c **** } while ( (0u != timeOutCnt) && (readStat != CYRET_SUCCESS) ); - 402 .loc 1 652 0 - 403 0040 B9F1000F cmp r9, #0 - 404 0044 02D0 beq .L52 - 652:.\Generated_Source\PSoC5/BL.c **** } while ( (0u != timeOutCnt) && (readStat != CYRET_SUCCESS) ); - 405 .loc 1 652 0 is_stmt 0 discriminator 1 - 406 0046 0028 cmp r0, #0 - 407 0048 E7D1 bne .L128 - 408 004a 01E0 b .L54 - 409 .L52: - 655:.\Generated_Source\PSoC5/BL.c **** if( readStat != CYRET_SUCCESS ) - 410 .loc 1 655 0 is_stmt 1 - 411 004c 0028 cmp r0, #0 - 412 004e 71D1 bne .L55 - 413 .L54: - 660:.\Generated_Source\PSoC5/BL.c **** if((numberRead < BL_MIN_PKT_SIZE) || - 414 .loc 1 660 0 - 415 0050 BDF80420 ldrh r2, [sp, #4] - 416 0054 062A cmp r2, #6 - 417 0056 40F27B81 bls .L90 - 660:.\Generated_Source\PSoC5/BL.c **** if((numberRead < BL_MIN_PKT_SIZE) || - 418 .loc 1 660 0 is_stmt 0 discriminator 1 - 419 005a 9DF82831 ldrb r3, [sp, #296] @ zero_extendqisi2 - 420 005e 012B cmp r3, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 35 - - - 421 0060 40F07681 bne .L90 - 667:.\Generated_Source\PSoC5/BL.c **** pktSize = ((uint16)((uint16)packetBuffer[BL_SIZE_ADDR + 1u] << 8u)) | - 422 .loc 1 667 0 is_stmt 1 - 423 0064 9DF82A01 ldrb r0, [sp, #298] @ zero_extendqisi2 - 424 .LVL56: - 425 0068 9DF82B51 ldrb r5, [sp, #299] @ zero_extendqisi2 - 670:.\Generated_Source\PSoC5/BL.c **** pktChecksum = ((uint16)((uint16)packetBuffer[BL_CHK_ADDR(pktSize) + 1u] << 8u)) | - 426 .loc 1 670 0 - 427 006c 4AA9 add r1, sp, #296 - 667:.\Generated_Source\PSoC5/BL.c **** pktSize = ((uint16)((uint16)packetBuffer[BL_SIZE_ADDR + 1u] << 8u)) | - 428 .loc 1 667 0 - 429 006e 40EA0525 orr r5, r0, r5, lsl #8 - 430 .LVL57: - 673:.\Generated_Source\PSoC5/BL.c **** if((pktSize + BL_MIN_PKT_SIZE) > numberRead) - 431 .loc 1 673 0 - 432 0072 EC1D adds r4, r5, #7 - 670:.\Generated_Source\PSoC5/BL.c **** pktChecksum = ((uint16)((uint16)packetBuffer[BL_CHK_ADDR(pktSize) + 1u] << 8u)) | - 433 .loc 1 670 0 - 434 0074 4B19 adds r3, r1, r5 - 673:.\Generated_Source\PSoC5/BL.c **** if((pktSize + BL_MIN_PKT_SIZE) > numberRead) - 435 .loc 1 673 0 - 436 0076 9442 cmp r4, r2 - 670:.\Generated_Source\PSoC5/BL.c **** pktChecksum = ((uint16)((uint16)packetBuffer[BL_CHK_ADDR(pktSize) + 1u] << 8u)) | - 437 .loc 1 670 0 - 438 0078 5879 ldrb r0, [r3, #5] @ zero_extendqisi2 - 671:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_CHK_ADDR(pktSize)]; - 439 .loc 1 671 0 - 440 007a 1979 ldrb r1, [r3, #4] @ zero_extendqisi2 - 441 .LVL58: - 673:.\Generated_Source\PSoC5/BL.c **** if((pktSize + BL_MIN_PKT_SIZE) > numberRead) - 442 .loc 1 673 0 - 443 007c 00F26681 bhi .L89 - 677:.\Generated_Source\PSoC5/BL.c **** else if(packetBuffer[BL_EOP_ADDR(pktSize)] != BL_EOP) - 444 .loc 1 677 0 - 445 0080 9A79 ldrb r2, [r3, #6] @ zero_extendqisi2 - 446 0082 172A cmp r2, #23 - 447 0084 40F06481 bne .L90 - 681:.\Generated_Source\PSoC5/BL.c **** else if(pktChecksum != BL_CalcPacketChecksum(packetBuffer, - 448 .loc 1 681 0 - 449 0088 2B1D adds r3, r5, #4 - 450 008a 9BB2 uxth r3, r3 - 451 .LVL59: - 157:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA sum = 0u; - 452 .loc 1 157 0 - 453 008c 0022 movs r2, #0 - 454 .LVL60: - 455 .L57: - 456 .LBB20: - 457 .LBB21: - 159:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 458 .loc 1 159 0 - 459 008e 3BB1 cbz r3, .L134 - 460 .L58: - 161:.\Generated_Source\PSoC5/BL.c **** sum += buffer[size - 1u]; - 461 .loc 1 161 0 - 462 0090 0DF22714 addw r4, sp, #295 - 463 0094 E45C ldrb r4, [r4, r3] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 36 - - - 162:.\Generated_Source\PSoC5/BL.c **** size--; - 464 .loc 1 162 0 - 465 0096 013B subs r3, r3, #1 - 466 .LVL61: - 161:.\Generated_Source\PSoC5/BL.c **** sum += buffer[size - 1u]; - 467 .loc 1 161 0 - 468 0098 1219 adds r2, r2, r4 - 469 .LVL62: - 470 009a 92B2 uxth r2, r2 - 471 .LVL63: - 162:.\Generated_Source\PSoC5/BL.c **** size--; - 472 .loc 1 162 0 - 473 009c 9BB2 uxth r3, r3 - 474 .LVL64: - 475 009e F6E7 b .L57 - 476 .L134: - 165:.\Generated_Source\PSoC5/BL.c **** return(( uint16 )1u + ( uint16 )(~sum)); - 477 .loc 1 165 0 - 478 00a0 5242 negs r2, r2 - 479 .LVL65: - 480 .LBE21: - 481 .LBE20: - 681:.\Generated_Source\PSoC5/BL.c **** else if(pktChecksum != BL_CalcPacketChecksum(packetBuffer, - 482 .loc 1 681 0 - 483 00a2 41EA0020 orr r0, r1, r0, lsl #8 - 484 .LVL66: - 485 00a6 91B2 uxth r1, r2 - 486 .LVL67: - 487 00a8 8842 cmp r0, r1 - 488 00aa 40F05381 bne .L91 - 489 00ae 4AE0 b .L135 - 490 .LVL68: - 491 .L62: - 492 .LBB22: - 761:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - 493 .loc 1 761 0 - 494 00b0 002E cmp r6, #0 - 495 00b2 00F04D81 beq .L90 - 761:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - 496 .loc 1 761 0 is_stmt 0 discriminator 1 - 497 00b6 012D cmp r5, #1 - 498 00b8 4FF00004 mov r4, #0 - 499 00bc 40F03C81 bne .L96 - 764:.\Generated_Source\PSoC5/BL.c **** if(btldrData < BL_NUM_OF_FLASH_ARRAYS) - 500 .loc 1 764 0 is_stmt 1 - 501 00c0 BBF1010F cmp fp, #1 - 502 00c4 00F23881 bhi .L96 - 503 .LVL69: - 504 .LBB23: - 774:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u); - 505 .loc 1 774 0 - 506 00c8 FF23 movs r3, #255 - 772:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR] = LO8(startRow); - 507 .loc 1 772 0 - 508 00ca 8DF82C41 strb r4, [sp, #300] - 773:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow); - 509 .loc 1 773 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 37 - - - 510 00ce 8DF82D41 strb r4, [sp, #301] - 778:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 511 .loc 1 778 0 - 512 00d2 2546 mov r5, r4 - 513 .LVL70: - 774:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u); - 514 .loc 1 774 0 - 515 00d4 8DF82E31 strb r3, [sp, #302] - 775:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u); - 516 .loc 1 775 0 - 517 00d8 8DF82F61 strb r6, [sp, #303] - 518 .LVL71: - 777:.\Generated_Source\PSoC5/BL.c **** rspSize = 4u; - 519 .loc 1 777 0 - 520 00dc 0424 movs r4, #4 - 521 .LVL72: - 522 .L61: - 523 .LBE23: - 524 .LBE22: - 525 .LBB32: - 526 .LBB33: -1286:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SOP_ADDR] = BL_SOP; - 527 .loc 1 1286 0 - 528 00de 0120 movs r0, #1 -1289:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SIZE_ADDR + 1u] = HI8(size); - 529 .loc 1 1289 0 - 530 00e0 0022 movs r2, #0 -1292:.\Generated_Source\PSoC5/BL.c **** checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR); - 531 .loc 1 1292 0 - 532 00e2 211D adds r1, r4, #4 - 533 00e4 ADF80640 strh r4, [sp, #6] @ movhi -1286:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SOP_ADDR] = BL_SOP; - 534 .loc 1 1286 0 - 535 00e8 8DF82801 strb r0, [sp, #296] -1287:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CMD_ADDR] = status; - 536 .loc 1 1287 0 - 537 00ec 8DF82951 strb r5, [sp, #297] -1288:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SIZE_ADDR] = LO8(size); - 538 .loc 1 1288 0 - 539 00f0 8DF82A41 strb r4, [sp, #298] -1289:.\Generated_Source\PSoC5/BL.c **** buffer[BL_SIZE_ADDR + 1u] = HI8(size); - 540 .loc 1 1289 0 - 541 00f4 8DF82B21 strb r2, [sp, #299] -1292:.\Generated_Source\PSoC5/BL.c **** checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR); - 542 .loc 1 1292 0 - 543 00f8 8BB2 uxth r3, r1 - 544 .LVL73: - 545 .L82: - 546 .LBB34: - 547 .LBB35: - 161:.\Generated_Source\PSoC5/BL.c **** sum += buffer[size - 1u]; - 548 .loc 1 161 0 - 549 00fa 0DF22710 addw r0, sp, #295 - 550 00fe C15C ldrb r1, [r0, r3] @ zero_extendqisi2 - 162:.\Generated_Source\PSoC5/BL.c **** size--; - 551 .loc 1 162 0 - 552 0100 013B subs r3, r3, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 38 - - - 161:.\Generated_Source\PSoC5/BL.c **** sum += buffer[size - 1u]; - 553 .loc 1 161 0 - 554 0102 5218 adds r2, r2, r1 - 162:.\Generated_Source\PSoC5/BL.c **** size--; - 555 .loc 1 162 0 - 556 0104 9BB2 uxth r3, r3 - 161:.\Generated_Source\PSoC5/BL.c **** sum += buffer[size - 1u]; - 557 .loc 1 161 0 - 558 0106 92B2 uxth r2, r2 - 559 .LVL74: - 159:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 560 .loc 1 159 0 - 561 0108 002B cmp r3, #0 - 562 010a F6D1 bne .L82 - 165:.\Generated_Source\PSoC5/BL.c **** return(( uint16 )1u + ( uint16 )(~sum)); - 563 .loc 1 165 0 - 564 010c 5042 negs r0, r2 - 565 010e 81B2 uxth r1, r0 - 566 .LBE35: - 567 .LBE34: -1295:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum); - 568 .loc 1 1295 0 - 569 0110 080A lsrs r0, r1, #8 -1294:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CHK_ADDR(size)] = LO8(checksum); - 570 .loc 1 1294 0 - 571 0112 4BAA add r2, sp, #300 - 572 .LVL75: -1295:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum); - 573 .loc 1 1295 0 - 574 0114 0DF22D13 addw r3, sp, #301 - 575 .LVL76: -1294:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CHK_ADDR(size)] = LO8(checksum); - 576 .loc 1 1294 0 - 577 0118 1155 strb r1, [r2, r4] -1295:.\Generated_Source\PSoC5/BL.c **** buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum); - 578 .loc 1 1295 0 - 579 011a 1855 strb r0, [r3, r4] -1296:.\Generated_Source\PSoC5/BL.c **** buffer[BL_EOP_ADDR(size)] = BL_EOP; - 580 .loc 1 1296 0 - 581 011c 1721 movs r1, #23 - 582 011e 0DF59772 add r2, sp, #302 -1299:.\Generated_Source\PSoC5/BL.c **** return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u)); - 583 .loc 1 1299 0 - 584 0122 E31D adds r3, r4, #7 -1296:.\Generated_Source\PSoC5/BL.c **** buffer[BL_EOP_ADDR(size)] = BL_EOP; - 585 .loc 1 1296 0 - 586 0124 1155 strb r1, [r2, r4] -1299:.\Generated_Source\PSoC5/BL.c **** return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u)); - 587 .loc 1 1299 0 - 588 0126 4AA8 add r0, sp, #296 - 589 .LVL77: - 590 0128 99B2 uxth r1, r3 - 591 012a 0DF10602 add r2, sp, #6 - 592 012e 9623 movs r3, #150 - 593 0130 FFF7FEFF bl USBFS_CyBtldrCommWrite - 594 .LVL78: - 595 .L55: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 39 - - - 596 .LBE33: - 597 .LBE32: -1255:.\Generated_Source\PSoC5/BL.c **** } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState)); - 598 .loc 1 1255 0 - 599 0134 B8F1000F cmp r8, #0 - 600 0138 3FF472AF beq .L112 -1255:.\Generated_Source\PSoC5/BL.c **** } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState)); - 601 .loc 1 1255 0 is_stmt 0 discriminator 1 - 602 013c 002E cmp r6, #0 - 603 013e 00F01281 beq .L136 - 604 .LVL79: - 605 .L84: -1029:.\Generated_Source\PSoC5/BL.c **** dataOffset = 0u; - 606 .loc 1 1029 0 is_stmt 1 - 607 0142 0126 movs r6, #1 - 608 0144 69E7 b .L128 - 609 .LVL80: - 610 .L135: - 611 .LBB36: - 698:.\Generated_Source\PSoC5/BL.c **** switch(packetBuffer[BL_CMD_ADDR]) - 612 .loc 1 698 0 - 613 0146 9DF82921 ldrb r2, [sp, #297] @ zero_extendqisi2 - 614 .LVL81: - 695:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA btldrData = packetBuffer[BL_DATA_ADDR]; - 615 .loc 1 695 0 - 616 014a 9DF82CB1 ldrb fp, [sp, #300] @ zero_extendqisi2 - 617 .LVL82: - 698:.\Generated_Source\PSoC5/BL.c **** switch(packetBuffer[BL_CMD_ADDR]) - 618 .loc 1 698 0 - 619 014e A2F13103 sub r3, r2, #49 - 620 .LVL83: - 621 0152 0A2B cmp r3, #10 - 622 0154 00F2F780 bhi .L110 - 623 0158 01A1 adr r1, .L85 - 624 015a 51F823F0 ldr pc, [r1, r3, lsl #2] - 625 015e 00BF .align 2 - 626 .L85: - 627 0160 8D010000 .word .L60+1 - 628 0164 B1000000 .word .L62+1 - 629 0168 47030000 .word .L110+1 - 630 016c AB010000 .word .L63+1 - 631 0170 5D020000 .word .L69+1 - 632 0174 47030000 .word .L110+1 - 633 0178 63020000 .word .L71+1 - 634 017c 81020000 .word .L72+1 - 635 0180 AB010000 .word .L63+1 - 636 0184 9B020000 .word .L73+1 - 637 0188 27030000 .word .L80+1 - 638 .L60: - 743:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 0u)) - 639 .loc 1 743 0 - 640 018c 002E cmp r6, #0 - 641 018e 00F0DF80 beq .L90 - 743:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 0u)) - 642 .loc 1 743 0 is_stmt 0 discriminator 1 - 643 0192 002D cmp r5, #0 - 644 0194 40F0DC80 bne .L90 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 40 - - - 746:.\Generated_Source\PSoC5/BL.c **** (uint8)(BL_ValidateBootloadable(BL_activeApp) == CYRET_SUCCESS); - 645 .loc 1 746 0 is_stmt 1 - 646 0198 FFF7FEFF bl BL_ValidateBootloadable.constprop.0 - 647 .LVL84: - 648 019c D0F10102 rsbs r2, r0, #1 - 649 01a0 38BF it cc - 650 01a2 0022 movcc r2, #0 - 651 01a4 8DF82C21 strb r2, [sp, #300] - 652 .LVL85: - 653 01a8 BBE0 b .L132 - 654 .LVL86: - 655 .L63: - 825:.\Generated_Source\PSoC5/BL.c **** if (BL_COMMAND_ERASE == packetBuffer[BL_CMD_ADDR]) - 656 .loc 1 825 0 - 657 01aa 342A cmp r2, #52 - 658 01ac 12D1 bne .L64 - 827:.\Generated_Source\PSoC5/BL.c **** if ((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) - 659 .loc 1 827 0 - 660 01ae 002E cmp r6, #0 - 661 01b0 00F0CE80 beq .L90 - 827:.\Generated_Source\PSoC5/BL.c **** if ((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) - 662 .loc 1 827 0 is_stmt 0 discriminator 1 - 663 01b4 032D cmp r5, #3 - 664 01b6 40F0CB80 bne .L90 - 830:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 665 .loc 1 830 0 is_stmt 1 - 666 01ba ABF14007 sub r7, fp, #64 - 834:.\Generated_Source\PSoC5/BL.c **** dataOffset = CY_EEPROM_SIZEOF_ROW; - 667 .loc 1 834 0 - 668 01be 3F2F cmp r7, #63 - 669 01c0 8CBF ite hi - 670 01c2 4FF49077 movhi r7, #288 - 671 01c6 1027 movls r7, #16 - 672 .LVL87: - 849:.\Generated_Source\PSoC5/BL.c **** (void) memset(dataBuffer, 0, dataOffset); - 673 .loc 1 849 0 - 674 01c8 95A8 add r0, sp, #596 - 675 01ca 0021 movs r1, #0 - 676 01cc 3A46 mov r2, r7 - 677 01ce FFF7FEFF bl memset - 678 .LVL88: - 679 01d2 05E0 b .L66 - 680 .LVL89: - 681 .L64: - 861:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize >= 3u)) - 682 .loc 1 861 0 - 683 01d4 002E cmp r6, #0 - 684 01d6 00F0BB80 beq .L90 - 861:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize >= 3u)) - 685 .loc 1 861 0 is_stmt 0 discriminator 1 - 686 01da 022D cmp r5, #2 - 687 01dc 40F2B880 bls .L90 - 688 .LVL90: - 689 .L66: - 870:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&dataBuffer[dataOffset], - 690 .loc 1 870 0 is_stmt 1 - 691 01e0 033D subs r5, r5, #3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 41 - - - 692 .LVL91: - 693 01e2 95AB add r3, sp, #596 - 694 01e4 2A46 mov r2, r5 - 695 01e6 D819 adds r0, r3, r7 - 696 01e8 0DF22F11 addw r1, sp, #303 - 697 01ec FFF7FEFF bl memcpy - 698 .LVL92: - 878:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 699 .loc 1 878 0 - 700 01f0 ABF14000 sub r0, fp, #64 - 875:.\Generated_Source\PSoC5/BL.c **** dataOffset += (pktSize - 3u); - 701 .loc 1 875 0 - 702 01f4 7A19 adds r2, r7, r5 - 878:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 703 .loc 1 878 0 - 704 01f6 3F28 cmp r0, #63 - 875:.\Generated_Source\PSoC5/BL.c **** dataOffset += (pktSize - 3u); - 705 .loc 1 875 0 - 706 01f8 96B2 uxth r6, r2 - 707 .LVL93: - 878:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 708 .loc 1 878 0 - 709 01fa 03D8 bhi .L102 - 882:.\Generated_Source\PSoC5/BL.c **** CyEEPROM_Start(); - 710 .loc 1 882 0 - 711 01fc FFF7FEFF bl CyEEPROM_Start - 712 .LVL94: - 885:.\Generated_Source\PSoC5/BL.c **** pktSize = CY_EEPROM_SIZEOF_ROW; - 713 .loc 1 885 0 - 714 0200 1024 movs r4, #16 - 715 0202 01E0 b .L67 - 716 .LVL95: - 717 .L102: - 890:.\Generated_Source\PSoC5/BL.c **** pktSize = BL_FROW_SIZE; - 718 .loc 1 890 0 - 719 0204 4FF49074 mov r4, #288 - 720 .LVL96: - 721 .L67: - 899:.\Generated_Source\PSoC5/BL.c **** if(dataOffset == pktSize) - 722 .loc 1 899 0 - 723 0208 A642 cmp r6, r4 - 724 020a 40F09780 bne .L103 - 902:.\Generated_Source\PSoC5/BL.c **** dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | - 725 .loc 1 902 0 - 726 020e 9DF82E11 ldrb r1, [sp, #302] @ zero_extendqisi2 - 727 0212 9DF82D71 ldrb r7, [sp, #301] @ zero_extendqisi2 - 906:.\Generated_Source\PSoC5/BL.c **** if(btldrData <= BL_LAST_FLASH_ARRAYID) - 728 .loc 1 906 0 - 729 0216 BBF13F0F cmp fp, #63 - 902:.\Generated_Source\PSoC5/BL.c **** dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | - 730 .loc 1 902 0 - 731 021a 47EA0125 orr r5, r7, r1, lsl #8 - 732 .LVL97: - 906:.\Generated_Source\PSoC5/BL.c **** if(btldrData <= BL_LAST_FLASH_ARRAYID) - 733 .loc 1 906 0 - 734 021e 11D8 bhi .L68 - 912:.\Generated_Source\PSoC5/BL.c **** if(0u == clearedMetaData) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 42 - - - 735 .loc 1 912 0 - 736 0220 BAF1000F cmp sl, #0 - 737 0224 0ED1 bne .L68 - 738 .LBB24: - 921:.\Generated_Source\PSoC5/BL.c **** (void) memset(erase, 0, BL_FROW_SIZE); - 739 .loc 1 921 0 - 740 0226 5146 mov r1, sl - 741 0228 4FF49072 mov r2, #288 - 742 022c 02A8 add r0, sp, #8 - 743 022e FFF7FEFF bl memset - 744 .LVL98: - 927:.\Generated_Source\PSoC5/BL.c **** (void) CyWriteRowFull((uint8) BL_MD_FLASH_ARRAY_NUM, - 745 .loc 1 927 0 - 746 0232 0120 movs r0, #1 - 747 0234 FF21 movs r1, #255 - 748 0236 02AA add r2, sp, #8 - 749 0238 4FF49073 mov r3, #288 - 750 023c FFF7FEFF bl CyWriteRowFull - 751 .LVL99: - 934:.\Generated_Source\PSoC5/BL.c **** clearedMetaData = 1u; - 752 .loc 1 934 0 - 753 0240 4FF0010A mov sl, #1 - 754 .LVL100: - 755 .L68: - 756 .LBE24: -1002:.\Generated_Source\PSoC5/BL.c **** ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataB - 757 .loc 1 1002 0 - 758 0244 3346 mov r3, r6 - 759 0246 5846 mov r0, fp - 760 0248 2946 mov r1, r5 - 761 024a 95AA add r2, sp, #596 - 762 024c FFF7FEFF bl CyWriteRowFull - 763 .LVL101: - 764 0250 0126 movs r6, #1 - 765 0252 0028 cmp r0, #0 - 766 0254 75D0 beq .L104 -1014:.\Generated_Source\PSoC5/BL.c **** dataOffset = 0u; - 767 .loc 1 1014 0 - 768 0256 0027 movs r7, #0 -1002:.\Generated_Source\PSoC5/BL.c **** ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataB - 769 .loc 1 1002 0 - 770 0258 0A25 movs r5, #10 - 771 .LVL102: - 772 025a 75E0 b .L131 - 773 .LVL103: - 774 .L69: -1026:.\Generated_Source\PSoC5/BL.c **** if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) - 775 .loc 1 1026 0 - 776 025c 002E cmp r6, #0 - 777 025e 77D0 beq .L90 - 778 0260 7AE0 b .L70 - 779 .L71: -1077:.\Generated_Source\PSoC5/BL.c **** if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) - 780 .loc 1 1077 0 - 781 0262 002E cmp r6, #0 - 782 0264 74D0 beq .L90 -1080:.\Generated_Source\PSoC5/BL.c **** if((dataOffset + pktSize) <= BL_SIZEOF_COMMAND_BUFFER) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 43 - - - 783 .loc 1 1080 0 - 784 0266 7C19 adds r4, r7, r5 - 785 0268 B4F5967F cmp r4, #300 - 786 026c 6ED8 bhi .L89 - 787 .LVL104: -1089:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&dataBuffer[dataOffset], - 788 .loc 1 1089 0 - 789 026e 95A9 add r1, sp, #596 - 790 0270 C819 adds r0, r1, r7 - 791 0272 2A46 mov r2, r5 - 792 0274 4BA9 add r1, sp, #300 - 793 .LVL105: - 794 0276 FFF7FEFF bl memcpy - 795 .LVL106: -1094:.\Generated_Source\PSoC5/BL.c **** dataOffset += pktSize; - 796 .loc 1 1094 0 - 797 027a A7B2 uxth r7, r4 - 798 .LVL107: - 799 .L133: -1082:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 800 .loc 1 1082 0 - 801 027c 0025 movs r5, #0 - 802 027e 63E0 b .L131 - 803 .LVL108: - 804 .L72: -1112:.\Generated_Source\PSoC5/BL.c **** if(pktSize == 0u) - 805 .loc 1 1112 0 - 806 0280 002D cmp r5, #0 - 807 0282 65D1 bne .L90 - 808 .LBB25: -1121:.\Generated_Source\PSoC5/BL.c **** BL_ENTER CYDATA BtldrVersion = - 809 .loc 1 1121 0 - 810 0284 3A48 ldr r0, .L138 - 811 0286 02AE add r6, sp, #8 -1135:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&packetBuffer[BL_DATA_ADDR], - 812 .loc 1 1135 0 - 813 0288 4BAC add r4, sp, #300 - 814 .LVL109: -1121:.\Generated_Source\PSoC5/BL.c **** BL_ENTER CYDATA BtldrVersion = - 815 .loc 1 1121 0 - 816 028a 03C8 ldmia r0, {r0, r1} - 817 028c 86E80300 stmia r6, {r0, r1} - 818 .LVL110: -1135:.\Generated_Source\PSoC5/BL.c **** (void) memcpy(&packetBuffer[BL_DATA_ADDR], - 819 .loc 1 1135 0 - 820 0290 84E80300 stmia r4, {r0, r1} - 821 .LVL111: -1126:.\Generated_Source\PSoC5/BL.c **** communicationState = BL_COMMUNICATION_STATE_ACTIVE; - 822 .loc 1 1126 0 - 823 0294 0126 movs r6, #1 -1128:.\Generated_Source\PSoC5/BL.c **** rspSize = sizeof(BL_ENTER); - 824 .loc 1 1128 0 - 825 0296 0824 movs r4, #8 - 826 .LVL112: - 827 0298 21E7 b .L61 - 828 .LVL113: - 829 .L73: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 44 - - - 830 .LBE25: -1150:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) - 831 .loc 1 1150 0 - 832 029a 002E cmp r6, #0 - 833 029c 58D0 beq .L90 -1150:.\Generated_Source\PSoC5/BL.c **** if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) - 834 .loc 1 1150 0 is_stmt 0 discriminator 1 - 835 029e 032D cmp r5, #3 - 836 02a0 56D1 bne .L90 - 837 .LBB26: -1153:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA rowNum = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u) - 838 .loc 1 1153 0 is_stmt 1 - 839 02a2 9DF82E01 ldrb r0, [sp, #302] @ zero_extendqisi2 - 840 02a6 9DF82D11 ldrb r1, [sp, #301] @ zero_extendqisi2 -1161:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 841 .loc 1 1161 0 - 842 02aa ABF14002 sub r2, fp, #64 - 843 02ae 3F2A cmp r2, #63 -1153:.\Generated_Source\PSoC5/BL.c **** uint16 CYDATA rowNum = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u) - 844 .loc 1 1153 0 - 845 02b0 41EA0025 orr r5, r1, r0, lsl #8 - 846 .LVL114: -1161:.\Generated_Source\PSoC5/BL.c **** if((btldrData >= BL_FIRST_EE_ARRAYID) && - 847 .loc 1 1161 0 - 848 02b4 0AD8 bhi .L74 -1166:.\Generated_Source\PSoC5/BL.c **** rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE; - 849 .loc 1 1166 0 - 850 02b6 2D01 lsls r5, r5, #4 - 851 .LVL115: - 227:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA sum = 0u; - 852 .loc 1 227 0 - 853 02b8 0023 movs r3, #0 -1166:.\Generated_Source\PSoC5/BL.c **** rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE; - 854 .loc 1 1166 0 - 855 02ba 1022 movs r2, #16 - 856 .LVL116: - 857 .L75: - 858 .LBB27: - 859 .LBB28: - 610:.\Generated_Source\PSoC5/BL.c **** static void BL_HostLink(uint8 timeOut) - 860 .loc 1 610 0 - 861 02bc 2D48 ldr r0, .L138+4 - 862 02be 1118 adds r1, r2, r0 - 232:.\Generated_Source\PSoC5/BL.c **** sum += BL_GET_EEPROM_BYTE(start + size); - 863 .loc 1 232 0 - 864 02c0 4C5D ldrb r4, [r1, r5] @ zero_extendqisi2 - 229:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 865 .loc 1 229 0 - 866 02c2 013A subs r2, r2, #1 - 867 .LVL117: - 232:.\Generated_Source\PSoC5/BL.c **** sum += BL_GET_EEPROM_BYTE(start + size); - 868 .loc 1 232 0 - 869 02c4 2344 add r3, r3, r4 - 870 02c6 DBB2 uxtb r3, r3 - 871 .LVL118: - 229:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 872 .loc 1 229 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 45 - - - 873 02c8 F8D1 bne .L75 - 874 02ca 26E0 b .L79 - 875 .LVL119: - 876 .L74: - 877 .LBE28: - 878 .LBE27: -1174:.\Generated_Source\PSoC5/BL.c **** + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); - 879 .loc 1 1174 0 - 880 02cc 05EB0B23 add r3, r5, fp, lsl #8 -1173:.\Generated_Source\PSoC5/BL.c **** rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) - 881 .loc 1 1173 0 - 882 02d0 1C02 lsls r4, r3, #8 - 883 .LVL120: - 884 02d2 4FF48072 mov r2, #256 - 192:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA sum = 0u; - 885 .loc 1 192 0 - 886 02d6 0023 movs r3, #0 - 887 .LVL121: - 888 .L77: - 889 .LBB29: - 890 .LBB30: - 196:.\Generated_Source\PSoC5/BL.c **** size--; - 891 .loc 1 196 0 - 892 02d8 013A subs r2, r2, #1 - 893 .LVL122: - 197:.\Generated_Source\PSoC5/BL.c **** sum += BL_GET_CODE_BYTE(start + size); - 894 .loc 1 197 0 - 895 02da 105D ldrb r0, [r2, r4] @ zero_extendqisi2 - 896 02dc 1918 adds r1, r3, r0 - 897 02de CBB2 uxtb r3, r1 - 898 .LVL123: - 194:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 899 .loc 1 194 0 - 900 02e0 002A cmp r2, #0 - 901 02e2 F9D1 bne .L77 - 902 .LVL124: - 903 .LBE30: - 904 .LBE29: -1192:.\Generated_Source\PSoC5/BL.c **** if(btldrData <= BL_LAST_FLASH_ARRAYID) - 905 .loc 1 1192 0 - 906 02e4 BBF13F0F cmp fp, #63 - 907 02e8 17D8 bhi .L79 - 908 .LBB31: -1197:.\Generated_Source\PSoC5/BL.c **** + ((uint32)rowNum * CYDEV_ECC_ROW_SIZE); - 909 .loc 1 1197 0 - 910 02ea 0BF51034 add r4, fp, #147456 - 911 .LVL125: - 912 02ee 05EB0420 add r0, r5, r4, lsl #8 -1196:.\Generated_Source\PSoC5/BL.c **** rowAddr = CYDEV_ECC_BASE + ((uint32)btldrData * (CYDEV_FLS_SECTOR_SIZE - 913 .loc 1 1196 0 - 914 02f2 4101 lsls r1, r0, #5 - 915 .LVL126: - 916 .L78: -1201:.\Generated_Source\PSoC5/BL.c **** checksum += CY_GET_XTND_REG8((uint8 CYFAR *)(rowAddr + tmpIndex)); - 917 .loc 1 1201 0 discriminator 2 - 918 02f4 545C ldrb r4, [r2, r1] @ zero_extendqisi2 - 919 02f6 0132 adds r2, r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 46 - - - 920 02f8 1B19 adds r3, r3, r4 -1199:.\Generated_Source\PSoC5/BL.c **** for(tmpIndex = 0u; tmpIndex < CYDEV_ECC_ROW_SIZE; tmpIndex++) - 921 .loc 1 1199 0 discriminator 2 - 922 02fa 202A cmp r2, #32 -1201:.\Generated_Source\PSoC5/BL.c **** checksum += CY_GET_XTND_REG8((uint8 CYFAR *)(rowAddr + tmpIndex)); - 923 .loc 1 1201 0 discriminator 2 - 924 02fc DBB2 uxtb r3, r3 - 925 .LVL127: -1199:.\Generated_Source\PSoC5/BL.c **** for(tmpIndex = 0u; tmpIndex < CYDEV_ECC_ROW_SIZE; tmpIndex++) - 926 .loc 1 1199 0 discriminator 2 - 927 02fe F9D1 bne .L78 - 928 .LBE31: -1213:.\Generated_Source\PSoC5/BL.c **** if((BL_MD_FLASH_ARRAY_NUM == btldrData) && - 929 .loc 1 1213 0 - 930 0300 BBF1010F cmp fp, #1 - 931 0304 09D1 bne .L79 -1213:.\Generated_Source\PSoC5/BL.c **** if((BL_MD_FLASH_ARRAY_NUM == btldrData) && - 932 .loc 1 1213 0 is_stmt 0 discriminator 1 - 933 0306 FF2D cmp r5, #255 - 934 0308 07D1 bne .L79 -1216:.\Generated_Source\PSoC5/BL.c **** checksum -= BL_MD_BTLDB_ACTIVE_VALUE (BL_GET_APP_ID(rowNum)); - 935 .loc 1 1216 0 is_stmt 1 - 936 030a 1B4D ldr r5, .L138+8 - 937 .LVL128: -1217:.\Generated_Source\PSoC5/BL.c **** checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum)); - 938 .loc 1 1217 0 - 939 030c 1B4C ldr r4, .L138+12 -1216:.\Generated_Source\PSoC5/BL.c **** checksum -= BL_MD_BTLDB_ACTIVE_VALUE (BL_GET_APP_ID(rowNum)); - 940 .loc 1 1216 0 - 941 030e 2878 ldrb r0, [r5, #0] @ zero_extendqisi2 - 942 0310 191A subs r1, r3, r0 - 943 .LVL129: -1217:.\Generated_Source\PSoC5/BL.c **** checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum)); - 944 .loc 1 1217 0 - 945 0312 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 946 0314 CA1A subs r2, r1, r3 - 947 0316 02F0FF03 and r3, r2, #255 - 948 .LVL130: - 949 .L79: -1220:.\Generated_Source\PSoC5/BL.c **** packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum); - 950 .loc 1 1220 0 - 951 031a 5D42 negs r5, r3 - 952 031c 8DF82C51 strb r5, [sp, #300] - 953 .LVL131: -1221:.\Generated_Source\PSoC5/BL.c **** ackCode = CYRET_SUCCESS; - 954 .loc 1 1221 0 - 955 0320 0025 movs r5, #0 - 956 .LVL132: - 957 .L132: -1222:.\Generated_Source\PSoC5/BL.c **** rspSize = 1u; - 958 .loc 1 1222 0 - 959 0322 0124 movs r4, #1 - 960 0324 DBE6 b .L61 - 961 .LVL133: - 962 .L80: - 963 .LBE26: -1232:.\Generated_Source\PSoC5/BL.c **** if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp)) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 47 - - - 964 .loc 1 1232 0 - 965 0326 FFF7FEFF bl BL_ValidateBootloadable.constprop.0 - 966 .LVL134: - 967 032a 10B9 cbnz r0, .L81 -1234:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(BL_START_APP); - 968 .loc 1 1234 0 - 969 032c 144D ldr r5, .L138+16 - 970 .LVL135: - 971 032e 8024 movs r4, #128 - 972 0330 2C70 strb r4, [r5, #0] - 973 .L81: -1237:.\Generated_Source\PSoC5/BL.c **** CySoftwareReset(); - 974 .loc 1 1237 0 - 975 0332 FFF7FEFF bl CySoftwareReset - 976 .LVL136: - 977 0336 0BE0 b .L90 - 978 .LVL137: - 979 .L96: - 697:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_DATA; - 980 .loc 1 697 0 - 981 0338 0425 movs r5, #4 - 982 .LVL138: - 983 033a D0E6 b .L61 - 984 .LVL139: - 985 .L103: - 899:.\Generated_Source\PSoC5/BL.c **** if(dataOffset == pktSize) - 986 .loc 1 899 0 - 987 033c 0126 movs r6, #1 - 988 .LVL140: -1014:.\Generated_Source\PSoC5/BL.c **** dataOffset = 0u; - 989 .loc 1 1014 0 - 990 033e 0027 movs r7, #0 - 991 .LVL141: - 992 0340 04E0 b .L89 - 993 .LVL142: - 994 .L104: - 995 0342 0746 mov r7, r0 - 996 0344 9AE7 b .L133 - 997 .LVL143: - 998 .L110: -1247:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_CMD; - 999 .loc 1 1247 0 - 1000 0346 0525 movs r5, #5 - 1001 .LVL144: - 1002 .L131: - 692:.\Generated_Source\PSoC5/BL.c **** rspSize = 0u; - 1003 .loc 1 692 0 - 1004 0348 0024 movs r4, #0 - 1005 034a C8E6 b .L61 - 1006 .L89: - 1007 .LBE36: - 675:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_LENGTH; - 1008 .loc 1 675 0 - 1009 034c 0325 movs r5, #3 - 1010 034e FBE7 b .L131 - 1011 .L90: - 663:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_DATA; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 48 - - - 1012 .loc 1 663 0 - 1013 0350 0425 movs r5, #4 - 1014 0352 F9E7 b .L131 - 1015 .LVL145: - 1016 .L91: - 684:.\Generated_Source\PSoC5/BL.c **** ackCode = BL_ERR_CHECKSUM; - 1017 .loc 1 684 0 - 1018 0354 0825 movs r5, #8 - 1019 .LVL146: - 1020 0356 F7E7 b .L131 - 1021 .LVL147: - 1022 .L70: -1255:.\Generated_Source\PSoC5/BL.c **** } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState)); - 1023 .loc 1 1255 0 - 1024 0358 B8F1000F cmp r8, #0 - 1025 035c 01D1 bne .L137 - 1026 .L111: -1029:.\Generated_Source\PSoC5/BL.c **** dataOffset = 0u; - 1027 .loc 1 1029 0 - 1028 035e 4746 mov r7, r8 - 1029 0360 5EE6 b .L112 - 1030 .L137: - 1031 0362 0027 movs r7, #0 - 1032 0364 EDE6 b .L84 - 1033 .LVL148: - 1034 .L136: -1256:.\Generated_Source\PSoC5/BL.c **** } - 1035 .loc 1 1256 0 - 1036 0366 0DF5617D add sp, sp, #900 - 1037 036a BDE8F08F pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 1038 .L139: - 1039 036e 00BF .align 2 - 1040 .L138: - 1041 0370 00000000 .word .LANCHOR0 - 1042 0374 FF7F0040 .word 1073774591 - 1043 0378 D0FF0100 .word 131024 - 1044 037c D1FF0100 .word 131025 - 1045 0380 FA460040 .word 1073759994 - 1046 .cfi_endproc - 1047 .LFE64: - 1048 .size BL_HostLink, .-BL_HostLink - 1049 .section .text.BL_Start,"ax",%progbits - 1050 .align 1 - 1051 .global BL_Start - 1052 .thumb - 1053 .thumb_func - 1054 .type BL_Start, %function - 1055 BL_Start: - 1056 .LFB59: - 273:.\Generated_Source\PSoC5/BL.c **** { - 1057 .loc 1 273 0 - 1058 .cfi_startproc - 1059 @ args = 0, pretend = 0, frame = 288 - 1060 @ frame_needed = 0, uses_anonymous_args = 0 - 1061 0000 10B5 push {r4, lr} - 1062 .LCFI4: - 1063 .cfi_def_cfa_offset 8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 49 - - - 1064 .cfi_offset 4, -8 - 1065 .cfi_offset 14, -4 - 1066 0002 C8B0 sub sp, sp, #288 - 1067 .LCFI5: - 1068 .cfi_def_cfa_offset 296 - 306:.\Generated_Source\PSoC5/BL.c **** if (CYRET_SUCCESS != CySetTemp()) - 1069 .loc 1 306 0 - 1070 0004 FFF7FEFF bl CySetTemp - 1071 .LVL149: - 1072 0008 10B1 cbz r0, .L141 - 308:.\Generated_Source\PSoC5/BL.c **** CyHalt(0x00u); - 1073 .loc 1 308 0 - 1074 000a 0020 movs r0, #0 - 1075 000c FFF7FEFF bl CyHalt - 1076 .LVL150: - 1077 .L141: - 311:.\Generated_Source\PSoC5/BL.c **** if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer)) - 1078 .loc 1 311 0 - 1079 0010 6846 mov r0, sp - 1080 0012 FFF7FEFF bl CySetFlashEEBuffer - 1081 .LVL151: - 1082 0016 10B1 cbz r0, .L142 - 313:.\Generated_Source\PSoC5/BL.c **** CyHalt(0x00u); - 1083 .loc 1 313 0 - 1084 0018 0020 movs r0, #0 - 1085 001a FFF7FEFF bl CyHalt - 1086 .LVL152: - 1087 .L142: - 329:.\Generated_Source\PSoC5/BL.c **** calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR, - 1088 .loc 1 329 0 - 1089 001e 1648 ldr r0, .L162 - 1090 0020 0368 ldr r3, [r0, #0] - 1091 0022 1968 ldr r1, [r3, #0] - 1092 .LVL153: - 192:.\Generated_Source\PSoC5/BL.c **** uint8 CYDATA sum = 0u; - 1093 .loc 1 192 0 - 1094 0024 0023 movs r3, #0 - 329:.\Generated_Source\PSoC5/BL.c **** calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR, - 1095 .loc 1 329 0 - 1096 0026 0A46 mov r2, r1 - 1097 .LVL154: - 1098 .L143: - 1099 .LBB41: - 1100 .LBB42: - 194:.\Generated_Source\PSoC5/BL.c **** while (size > 0u) - 1101 .loc 1 194 0 - 1102 0028 22B1 cbz r2, .L161 - 1103 .L144: - 197:.\Generated_Source\PSoC5/BL.c **** sum += BL_GET_CODE_BYTE(start + size); - 1104 .loc 1 197 0 - 1105 002a 12F8014D ldrb r4, [r2, #-1]! @ zero_extendqisi2 - 1106 002e E318 adds r3, r4, r3 - 1107 .LVL155: - 1108 0030 DBB2 uxtb r3, r3 - 1109 .LVL156: - 1110 0032 F9E7 b .L143 - 1111 .L161: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 50 - - - 1112 .LBE42: - 1113 .LBE41: - 333:.\Generated_Source\PSoC5/BL.c **** calcedChecksum -= *BL_ChecksumAccess; - 1114 .loc 1 333 0 - 1115 0034 4268 ldr r2, [r0, #4] - 1116 0036 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 1117 .LVL157: - 334:.\Generated_Source\PSoC5/BL.c **** calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); - 1118 .loc 1 334 0 - 1119 0038 C41A subs r4, r0, r3 - 337:.\Generated_Source\PSoC5/BL.c **** if((calcedChecksum != *BL_ChecksumAccess) || - 1120 .loc 1 337 0 - 1121 003a 04F0FF03 and r3, r4, #255 - 1122 .LVL158: - 1123 003e 8342 cmp r3, r0 - 1124 0040 00D1 bne .L145 - 337:.\Generated_Source\PSoC5/BL.c **** if((calcedChecksum != *BL_ChecksumAccess) || - 1125 .loc 1 337 0 is_stmt 0 discriminator 1 - 1126 0042 11B9 cbnz r1, .L146 - 1127 .L145: - 340:.\Generated_Source\PSoC5/BL.c **** CyHalt(0x00u); - 1128 .loc 1 340 0 is_stmt 1 - 1129 0044 0020 movs r0, #0 - 1130 0046 FFF7FEFF bl CyHalt - 1131 .LVL159: - 1132 .L146: - 356:.\Generated_Source\PSoC5/BL.c **** if ((BL_GET_RUN_TYPE == BL_START_BTLDR) || - 1133 .loc 1 356 0 - 1134 004a 0C4C ldr r4, .L162+4 - 354:.\Generated_Source\PSoC5/BL.c **** tmpStatus = BL_ValidateBootloadable(BL_activeApp); - 1135 .loc 1 354 0 - 1136 004c FFF7FEFF bl BL_ValidateBootloadable.constprop.0 - 1137 .LVL160: - 356:.\Generated_Source\PSoC5/BL.c **** if ((BL_GET_RUN_TYPE == BL_START_BTLDR) || - 1138 .loc 1 356 0 - 1139 0050 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1140 0052 01F0C002 and r2, r1, #192 - 1141 0056 402A cmp r2, #64 - 1142 0058 00D0 beq .L147 - 356:.\Generated_Source\PSoC5/BL.c **** if ((BL_GET_RUN_TYPE == BL_START_BTLDR) || - 1143 .loc 1 356 0 is_stmt 0 discriminator 1 - 1144 005a 18B1 cbz r0, .L148 - 1145 .L147: - 359:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(0u); - 1146 .loc 1 359 0 is_stmt 1 - 1147 005c 0020 movs r0, #0 - 1148 .LVL161: - 1149 005e 2070 strb r0, [r4, #0] - 361:.\Generated_Source\PSoC5/BL.c **** BL_HostLink(BL_WAIT_FOR_COMMAND_FOREVER); - 1150 .loc 1 361 0 - 1151 0060 FFF7FEFF bl BL_HostLink - 1152 .LVL162: - 1153 .L148: - 369:.\Generated_Source\PSoC5/BL.c **** BL_HostLink(BL_WAIT_FOR_COMMAND_TIME); - 1154 .loc 1 369 0 - 1155 0064 1420 movs r0, #20 - 1156 0066 FFF7FEFF bl BL_HostLink - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 51 - - - 1157 .LVL163: - 1158 .LBB43: - 1159 .LBB44: - 396:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(BL_START_APP); - 1160 .loc 1 396 0 - 1161 006a 8020 movs r0, #128 - 1162 006c 2070 strb r0, [r4, #0] - 398:.\Generated_Source\PSoC5/BL.c **** CySoftwareReset(); - 1163 .loc 1 398 0 - 1164 006e FFF7FEFF bl CySoftwareReset - 1165 .LVL164: - 1166 .LBE44: - 1167 .LBE43: - 376:.\Generated_Source\PSoC5/BL.c **** } - 1168 .loc 1 376 0 - 1169 0072 48B0 add sp, sp, #288 - 1170 0074 10BD pop {r4, pc} - 1171 .L163: - 1172 0076 00BF .align 2 - 1173 .L162: - 1174 0078 00000000 .word .LANCHOR1 - 1175 007c FA460040 .word 1073759994 - 1176 .cfi_endproc - 1177 .LFE59: - 1178 .size BL_Start, .-BL_Start - 1179 .section .text.CyBtldr_CheckLaunch,"ax",%progbits - 1180 .align 1 - 1181 .global CyBtldr_CheckLaunch - 1182 .thumb - 1183 .thumb_func - 1184 .type CyBtldr_CheckLaunch, %function - 1185 CyBtldr_CheckLaunch: - 1186 .LFB61: - 420:.\Generated_Source\PSoC5/BL.c **** { - 1187 .loc 1 420 0 - 1188 .cfi_startproc - 1189 @ args = 0, pretend = 0, frame = 0 - 1190 @ frame_needed = 0, uses_anonymous_args = 0 - 1191 0000 08B5 push {r3, lr} - 1192 .LCFI6: - 1193 .cfi_def_cfa_offset 8 - 1194 .cfi_offset 3, -8 - 1195 .cfi_offset 14, -4 - 437:.\Generated_Source\PSoC5/BL.c **** if (BL_GET_RUN_TYPE == BL_START_APP) - 1196 .loc 1 437 0 - 1197 0002 0A4B ldr r3, .L171 - 1198 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1199 0006 02F0C000 and r0, r2, #192 - 1200 000a 8028 cmp r0, #128 - 1201 000c 0CD1 bne .L164 - 439:.\Generated_Source\PSoC5/BL.c **** BL_SET_RUN_TYPE(0u); - 1202 .loc 1 439 0 - 1203 000e 0021 movs r1, #0 - 1204 0010 1970 strb r1, [r3, #0] - 447:.\Generated_Source\PSoC5/BL.c **** if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp)) - 1205 .loc 1 447 0 - 1206 0012 0120 movs r0, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 52 - - - 1207 0014 FFF7FEFF bl BL_GetMetadata.constprop.1 - 1208 .LVL165: - 1209 0018 30B1 cbz r0, .L164 - 450:.\Generated_Source\PSoC5/BL.c **** BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, - 1210 .loc 1 450 0 - 1211 001a 0120 movs r0, #1 - 1212 001c FFF7FEFF bl BL_GetMetadata.constprop.1 - 1213 .LVL166: - 454:.\Generated_Source\PSoC5/BL.c **** } - 1214 .loc 1 454 0 - 1215 0020 BDE80840 pop {r3, lr} - 450:.\Generated_Source\PSoC5/BL.c **** BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, - 1216 .loc 1 450 0 - 1217 0024 FFF7FEBF b BL_LaunchBootloadable - 1218 .LVL167: - 1219 .L164: - 1220 0028 08BD pop {r3, pc} - 1221 .L172: - 1222 002a 00BF .align 2 - 1223 .L171: - 1224 002c FA460040 .word 1073759994 - 1225 .cfi_endproc - 1226 .LFE61: - 1227 .size CyBtldr_CheckLaunch, .-CyBtldr_CheckLaunch - 1228 .section .text.BL_SetFlashByte,"ax",%progbits - 1229 .align 1 - 1230 .global BL_SetFlashByte - 1231 .thumb - 1232 .thumb_func - 1233 .type BL_SetFlashByte, %function - 1234 BL_SetFlashByte: - 1235 .LFB66: -1322:.\Generated_Source\PSoC5/BL.c **** { - 1236 .loc 1 1322 0 - 1237 .cfi_startproc - 1238 @ args = 0, pretend = 0, frame = 256 - 1239 @ frame_needed = 0, uses_anonymous_args = 0 - 1240 .LVL168: - 1241 0000 70B5 push {r4, r5, r6, lr} - 1242 .LCFI7: - 1243 .cfi_def_cfa_offset 16 - 1244 .cfi_offset 4, -16 - 1245 .cfi_offset 5, -12 - 1246 .cfi_offset 6, -8 - 1247 .cfi_offset 14, -4 -1330:.\Generated_Source\PSoC5/BL.c **** uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); - 1248 .loc 1 1330 0 - 1249 0002 C0F30722 ubfx r2, r0, #8, #8 -1322:.\Generated_Source\PSoC5/BL.c **** { - 1250 .loc 1 1322 0 - 1251 0006 C0B0 sub sp, sp, #256 - 1252 .LCFI8: - 1253 .cfi_def_cfa_offset 272 -1327:.\Generated_Source\PSoC5/BL.c **** uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); - 1254 .loc 1 1327 0 - 1255 0008 C0F30744 ubfx r4, r0, #16, #8 - 1256 .LVL169: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 53 - - -1331:.\Generated_Source\PSoC5/BL.c **** uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); - 1257 .loc 1 1331 0 - 1258 000c 20F0FF06 bic r6, r0, #255 - 1259 .LVL170: - 1260 0010 0023 movs r3, #0 - 1261 .LVL171: - 1262 .L174: -1336:.\Generated_Source\PSoC5/BL.c **** rowData[idx] = BL_GET_CODE_BYTE(baseAddr + idx); - 1263 .loc 1 1336 0 discriminator 2 - 1264 0012 9D5D ldrb r5, [r3, r6] @ zero_extendqisi2 - 1265 0014 0DF80350 strb r5, [sp, r3] - 1266 0018 0133 adds r3, r3, #1 -1334:.\Generated_Source\PSoC5/BL.c **** for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) - 1267 .loc 1 1334 0 discriminator 2 - 1268 001a B3F5807F cmp r3, #256 - 1269 001e F8D1 bne .L174 -1339:.\Generated_Source\PSoC5/BL.c **** rowData[address % CYDEV_FLS_ROW_SIZE] = runType; - 1270 .loc 1 1339 0 - 1271 0020 C0B2 uxtb r0, r0 - 1272 .LVL172: - 1273 0022 0DF80010 strb r1, [sp, r0] -1344:.\Generated_Source\PSoC5/BL.c **** (void) CyWriteRowData(arrayId, rowNum, rowData); - 1274 .loc 1 1344 0 - 1275 0026 1146 mov r1, r2 - 1276 .LVL173: - 1277 0028 2046 mov r0, r4 - 1278 .LVL174: - 1279 002a 6A46 mov r2, sp - 1280 .LVL175: - 1281 002c FFF7FEFF bl CyWriteRowData - 1282 .LVL176: -1346:.\Generated_Source\PSoC5/BL.c **** } - 1283 .loc 1 1346 0 - 1284 0030 40B0 add sp, sp, #256 - 1285 0032 70BD pop {r4, r5, r6, pc} - 1286 .cfi_endproc - 1287 .LFE66: - 1288 .size BL_SetFlashByte, .-BL_SetFlashByte - 1289 .global BL_SizeBytesAccess - 1290 .global BL_SizeBytes - 1291 .global BL_ChecksumAccess - 1292 .global BL_Checksum - 1293 .section .rodata - 1294 .align 2 - 1295 .set .LANCHOR0,. + 0 - 1296 .LC0: - 1297 0000 6930132E .word 773009513 - 1298 0004 00 .byte 0 - 1299 0005 14 .byte 20 - 1300 0006 01 .byte 1 - 1301 0007 01 .byte 1 - 1302 .section .bootloader,"a",%progbits - 1303 .align 2 - 1304 .type BL_SizeBytes, %object - 1305 .size BL_SizeBytes, 4 - 1306 BL_SizeBytes: - 1307 0000 FFFFFFFF .word -1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 54 - - - 1308 .type BL_Checksum, %object - 1309 .size BL_Checksum, 1 - 1310 BL_Checksum: - 1311 0004 00 .space 1 - 1312 0005 000000 .data - 1313 .align 2 - 1314 .set .LANCHOR1,. + 0 - 1315 .type BL_SizeBytesAccess, %object - 1316 .size BL_SizeBytesAccess, 4 - 1317 BL_SizeBytesAccess: - 1318 0000 00000000 .word BL_SizeBytes - 1319 .type BL_ChecksumAccess, %object - 1320 .size BL_ChecksumAccess, 4 - 1321 BL_ChecksumAccess: - 1322 0004 00000000 .word BL_Checksum - 1323 .text - 1324 .Letext0: - 1325 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\3.0\\psoc creator\\import\\gnu_cs\\arm\\4 - 1326 .file 3 ".\\Generated_Source\\PSoC5\\cytypes.h" - 1327 .file 4 ".\\Generated_Source\\PSoC5\\BL_PVT.h" - 1328 .file 5 "./Generated_Source/PSoC5/core_cm3.h" - 1329 .file 6 "./Generated_Source/PSoC5/CyFlash.h" - 1330 .file 7 "./Generated_Source/PSoC5/CyLib.h" - 1331 .file 8 "./Generated_Source/PSoC5/USBFS.h" - 1332 .section .debug_info,"",%progbits - 1333 .Ldebug_info0: - 1334 0000 EE0B0000 .4byte 0xbee - 1335 0004 0200 .2byte 0x2 - 1336 0006 00000000 .4byte .Ldebug_abbrev0 - 1337 000a 04 .byte 0x4 - 1338 000b 01 .uleb128 0x1 - 1339 000c 0A020000 .4byte .LASF92 - 1340 0010 01 .byte 0x1 - 1341 0011 53020000 .4byte .LASF93 - 1342 0015 13010000 .4byte .LASF94 - 1343 0019 18000000 .4byte .Ldebug_ranges0+0x18 - 1344 001d 00000000 .4byte 0 - 1345 0021 00000000 .4byte 0 - 1346 0025 00000000 .4byte .Ldebug_line0 - 1347 0029 02 .uleb128 0x2 - 1348 002a 01 .byte 0x1 - 1349 002b 06 .byte 0x6 - 1350 002c 6F010000 .4byte .LASF0 - 1351 0030 02 .uleb128 0x2 - 1352 0031 01 .byte 0x1 - 1353 0032 08 .byte 0x8 - 1354 0033 B0020000 .4byte .LASF1 - 1355 0037 02 .uleb128 0x2 - 1356 0038 02 .byte 0x2 - 1357 0039 05 .byte 0x5 - 1358 003a 5D000000 .4byte .LASF2 - 1359 003e 02 .uleb128 0x2 - 1360 003f 02 .byte 0x2 - 1361 0040 07 .byte 0x7 - 1362 0041 BA030000 .4byte .LASF3 - 1363 0045 03 .uleb128 0x3 - 1364 0046 DF020000 .4byte .LASF9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 55 - - - 1365 004a 02 .byte 0x2 - 1366 004b 4F .byte 0x4f - 1367 004c 50000000 .4byte 0x50 - 1368 0050 02 .uleb128 0x2 - 1369 0051 04 .byte 0x4 - 1370 0052 05 .byte 0x5 - 1371 0053 99030000 .4byte .LASF4 - 1372 0057 02 .uleb128 0x2 - 1373 0058 04 .byte 0x4 - 1374 0059 07 .byte 0x7 - 1375 005a 27040000 .4byte .LASF5 - 1376 005e 02 .uleb128 0x2 - 1377 005f 08 .byte 0x8 - 1378 0060 05 .byte 0x5 - 1379 0061 81010000 .4byte .LASF6 - 1380 0065 02 .uleb128 0x2 - 1381 0066 08 .byte 0x8 - 1382 0067 07 .byte 0x7 - 1383 0068 E7020000 .4byte .LASF7 - 1384 006c 04 .uleb128 0x4 - 1385 006d 04 .byte 0x4 - 1386 006e 05 .byte 0x5 - 1387 006f 696E7400 .ascii "int\000" - 1388 0073 02 .uleb128 0x2 - 1389 0074 04 .byte 0x4 - 1390 0075 07 .byte 0x7 - 1391 0076 BA040000 .4byte .LASF8 - 1392 007a 03 .uleb128 0x3 - 1393 007b 44010000 .4byte .LASF10 - 1394 007f 03 .byte 0x3 - 1395 0080 5B .byte 0x5b - 1396 0081 30000000 .4byte 0x30 - 1397 0085 03 .uleb128 0x3 - 1398 0086 EB000000 .4byte .LASF11 - 1399 008a 03 .byte 0x3 - 1400 008b 5C .byte 0x5c - 1401 008c 3E000000 .4byte 0x3e - 1402 0090 03 .uleb128 0x3 - 1403 0091 1B040000 .4byte .LASF12 - 1404 0095 03 .byte 0x3 - 1405 0096 5D .byte 0x5d - 1406 0097 57000000 .4byte 0x57 - 1407 009b 02 .uleb128 0x2 - 1408 009c 04 .byte 0x4 - 1409 009d 04 .byte 0x4 - 1410 009e 7B010000 .4byte .LASF13 - 1411 00a2 02 .uleb128 0x2 - 1412 00a3 08 .byte 0x8 - 1413 00a4 04 .byte 0x4 - 1414 00a5 41040000 .4byte .LASF14 - 1415 00a9 02 .uleb128 0x2 - 1416 00aa 01 .byte 0x1 - 1417 00ab 08 .byte 0x8 - 1418 00ac 96010000 .4byte .LASF15 - 1419 00b0 03 .uleb128 0x3 - 1420 00b1 1E030000 .4byte .LASF16 - 1421 00b5 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 56 - - - 1422 00b6 E8 .byte 0xe8 - 1423 00b7 57000000 .4byte 0x57 - 1424 00bb 03 .uleb128 0x3 - 1425 00bc 22040000 .4byte .LASF17 - 1426 00c0 03 .byte 0x3 - 1427 00c1 F0 .byte 0xf0 - 1428 00c2 C6000000 .4byte 0xc6 - 1429 00c6 05 .uleb128 0x5 - 1430 00c7 7A000000 .4byte 0x7a - 1431 00cb 06 .uleb128 0x6 - 1432 00cc 08 .byte 0x8 - 1433 00cd 04 .byte 0x4 - 1434 00ce 15 .byte 0x15 - 1435 00cf FE000000 .4byte 0xfe - 1436 00d3 07 .uleb128 0x7 - 1437 00d4 DD030000 .4byte .LASF18 - 1438 00d8 04 .byte 0x4 - 1439 00d9 17 .byte 0x17 - 1440 00da 90000000 .4byte 0x90 - 1441 00de 02 .byte 0x2 - 1442 00df 23 .byte 0x23 - 1443 00e0 00 .uleb128 0 - 1444 00e1 07 .uleb128 0x7 - 1445 00e2 A4040000 .4byte .LASF19 - 1446 00e6 04 .byte 0x4 - 1447 00e7 18 .byte 0x18 - 1448 00e8 7A000000 .4byte 0x7a - 1449 00ec 02 .byte 0x2 - 1450 00ed 23 .byte 0x23 - 1451 00ee 04 .uleb128 0x4 - 1452 00ef 07 .uleb128 0x7 - 1453 00f0 5D010000 .4byte .LASF20 - 1454 00f4 04 .byte 0x4 - 1455 00f5 19 .byte 0x19 - 1456 00f6 FE000000 .4byte 0xfe - 1457 00fa 02 .byte 0x2 - 1458 00fb 23 .byte 0x23 - 1459 00fc 05 .uleb128 0x5 - 1460 00fd 00 .byte 0 - 1461 00fe 08 .uleb128 0x8 - 1462 00ff 7A000000 .4byte 0x7a - 1463 0103 0E010000 .4byte 0x10e - 1464 0107 09 .uleb128 0x9 - 1465 0108 0E010000 .4byte 0x10e - 1466 010c 02 .byte 0x2 - 1467 010d 00 .byte 0 - 1468 010e 02 .uleb128 0x2 - 1469 010f 04 .byte 0x4 - 1470 0110 07 .byte 0x7 - 1471 0111 7E000000 .4byte .LASF21 - 1472 0115 03 .uleb128 0x3 - 1473 0116 9B040000 .4byte .LASF22 - 1474 011a 04 .byte 0x4 - 1475 011b 1B .byte 0x1b - 1476 011c CB000000 .4byte 0xcb - 1477 0120 0A .uleb128 0xa - 1478 0121 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 57 - - - 1479 0122 0B .uleb128 0xb - 1480 0123 04 .byte 0x4 - 1481 0124 28010000 .4byte 0x128 - 1482 0128 0C .uleb128 0xc - 1483 0129 0D .uleb128 0xd - 1484 012a 9B010000 .4byte .LASF25 - 1485 012e 01 .byte 0x1 - 1486 012f E0 .byte 0xe0 - 1487 0130 01 .byte 0x1 - 1488 0131 7A000000 .4byte 0x7a - 1489 0135 01 .byte 0x1 - 1490 0136 5C010000 .4byte 0x15c - 1491 013a 0E .uleb128 0xe - 1492 013b AA020000 .4byte .LASF23 - 1493 013f 01 .byte 0x1 - 1494 0140 E0 .byte 0xe0 - 1495 0141 90000000 .4byte 0x90 - 1496 0145 0E .uleb128 0xe - 1497 0146 54040000 .4byte .LASF24 - 1498 014a 01 .byte 0x1 - 1499 014b E0 .byte 0xe0 - 1500 014c 90000000 .4byte 0x90 - 1501 0150 0F .uleb128 0xf - 1502 0151 73756D00 .ascii "sum\000" - 1503 0155 01 .byte 0x1 - 1504 0156 E3 .byte 0xe3 - 1505 0157 7A000000 .4byte 0x7a - 1506 015b 00 .byte 0 - 1507 015c 10 .uleb128 0x10 - 1508 015d AB030000 .4byte .LASF26 - 1509 0161 01 .byte 0x1 - 1510 0162 5E05 .2byte 0x55e - 1511 0164 01 .byte 0x1 - 1512 0165 90000000 .4byte 0x90 - 1513 0169 01 .byte 0x1 - 1514 016a AB010000 .4byte 0x1ab - 1515 016e 11 .uleb128 0x11 - 1516 016f D6040000 .4byte .LASF27 - 1517 0173 01 .byte 0x1 - 1518 0174 5E05 .2byte 0x55e - 1519 0176 7A000000 .4byte 0x7a - 1520 017a 11 .uleb128 0x11 - 1521 017b 15000000 .4byte .LASF28 - 1522 017f 01 .byte 0x1 - 1523 0180 5E05 .2byte 0x55e - 1524 0182 7A000000 .4byte 0x7a - 1525 0186 12 .uleb128 0x12 - 1526 0187 81020000 .4byte .LASF29 - 1527 018b 01 .byte 0x1 - 1528 018c 6005 .2byte 0x560 - 1529 018e 90000000 .4byte 0x90 - 1530 0192 12 .uleb128 0x12 - 1531 0193 53030000 .4byte .LASF30 - 1532 0197 01 .byte 0x1 - 1533 0198 6105 .2byte 0x561 - 1534 019a 7A000000 .4byte 0x7a - 1535 019e 12 .uleb128 0x12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 58 - - - 1536 019f 1B000000 .4byte .LASF31 - 1537 01a3 01 .byte 0x1 - 1538 01a4 6205 .2byte 0x562 - 1539 01a6 90000000 .4byte 0x90 - 1540 01aa 00 .byte 0 - 1541 01ab 10 .uleb128 0x10 - 1542 01ac FB000000 .4byte .LASF32 - 1543 01b0 01 .byte 0x1 - 1544 01b1 F501 .2byte 0x1f5 - 1545 01b3 01 .byte 0x1 - 1546 01b4 B0000000 .4byte 0xb0 - 1547 01b8 01 .byte 0x1 - 1548 01b9 08020000 .4byte 0x208 - 1549 01bd 11 .uleb128 0x11 - 1550 01be 15000000 .4byte .LASF28 - 1551 01c2 01 .byte 0x1 - 1552 01c3 F501 .2byte 0x1f5 - 1553 01c5 7A000000 .4byte 0x7a - 1554 01c9 13 .uleb128 0x13 - 1555 01ca 69647800 .ascii "idx\000" - 1556 01ce 01 .byte 0x1 - 1557 01cf F801 .2byte 0x1f8 - 1558 01d1 90000000 .4byte 0x90 - 1559 01d5 13 .uleb128 0x13 - 1560 01d6 656E6400 .ascii "end\000" - 1561 01da 01 .byte 0x1 - 1562 01db FA01 .2byte 0x1fa - 1563 01dd 90000000 .4byte 0x90 - 1564 01e1 12 .uleb128 0x12 - 1565 01e2 00000000 .4byte .LASF33 - 1566 01e6 01 .byte 0x1 - 1567 01e7 FE01 .2byte 0x1fe - 1568 01e9 7A000000 .4byte 0x7a - 1569 01ed 12 .uleb128 0x12 - 1570 01ee DC010000 .4byte .LASF34 - 1571 01f2 01 .byte 0x1 - 1572 01f3 FF01 .2byte 0x1ff - 1573 01f5 7A000000 .4byte 0x7a - 1574 01f9 14 .uleb128 0x14 - 1575 01fa 12 .uleb128 0x12 - 1576 01fb C0010000 .4byte .LASF35 - 1577 01ff 01 .byte 0x1 - 1578 0200 1902 .2byte 0x219 - 1579 0202 7A000000 .4byte 0x7a - 1580 0206 00 .byte 0 - 1581 0207 00 .byte 0 - 1582 0208 15 .uleb128 0x15 - 1583 0209 27030000 .4byte .LASF42 - 1584 020d 01 .byte 0x1 - 1585 020e D601 .2byte 0x1d6 - 1586 0210 01 .byte 0x1 - 1587 0211 00000000 .4byte .LFB62 - 1588 0215 02000000 .4byte .LFE62 - 1589 0219 02 .byte 0x2 - 1590 021a 7D .byte 0x7d - 1591 021b 00 .sleb128 0 - 1592 021c 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 59 - - - 1593 021d 30020000 .4byte 0x230 - 1594 0221 16 .uleb128 0x16 - 1595 0222 4D000000 .4byte .LASF44 - 1596 0226 01 .byte 0x1 - 1597 0227 D601 .2byte 0x1d6 - 1598 0229 90000000 .4byte 0x90 - 1599 022d 01 .byte 0x1 - 1600 022e 50 .byte 0x50 - 1601 022f 00 .byte 0 - 1602 0230 17 .uleb128 0x17 - 1603 0231 5C010000 .4byte 0x15c - 1604 0235 00000000 .4byte .LFB69 - 1605 0239 8C000000 .4byte .LFE69 - 1606 023d 00000000 .4byte .LLST0 - 1607 0241 01 .byte 0x1 - 1608 0242 71020000 .4byte 0x271 - 1609 0246 18 .uleb128 0x18 - 1610 0247 6E010000 .4byte 0x16e - 1611 024b 20000000 .4byte .LLST1 - 1612 024f 19 .uleb128 0x19 - 1613 0250 86010000 .4byte 0x186 - 1614 0254 BE000000 .4byte .LLST2 - 1615 0258 19 .uleb128 0x19 - 1616 0259 92010000 .4byte 0x192 - 1617 025d FC000000 .4byte .LLST3 - 1618 0261 19 .uleb128 0x19 - 1619 0262 9E010000 .4byte 0x19e - 1620 0266 28010000 .4byte .LLST4 - 1621 026a 1A .uleb128 0x1a - 1622 026b 7A010000 .4byte 0x17a - 1623 026f 00 .byte 0 - 1624 0270 00 .byte 0 - 1625 0271 17 .uleb128 0x17 - 1626 0272 AB010000 .4byte 0x1ab - 1627 0276 00000000 .4byte .LFB70 - 1628 027a 84000000 .4byte .LFE70 - 1629 027e 8E010000 .4byte .LLST5 - 1630 0282 01 .byte 0x1 - 1631 0283 11030000 .4byte 0x311 - 1632 0287 19 .uleb128 0x19 - 1633 0288 C9010000 .4byte 0x1c9 - 1634 028c AE010000 .4byte .LLST6 - 1635 0290 19 .uleb128 0x19 - 1636 0291 D5010000 .4byte 0x1d5 - 1637 0295 E4010000 .4byte .LLST7 - 1638 0299 19 .uleb128 0x19 - 1639 029a E1010000 .4byte 0x1e1 - 1640 029e 02020000 .4byte .LLST8 - 1641 02a2 19 .uleb128 0x19 - 1642 02a3 ED010000 .4byte 0x1ed - 1643 02a7 21020000 .4byte .LLST9 - 1644 02ab 1A .uleb128 0x1a - 1645 02ac BD010000 .4byte 0x1bd - 1646 02b0 00 .byte 0 - 1647 02b1 1B .uleb128 0x1b - 1648 02b2 28000000 .4byte .LBB3 - 1649 02b6 3C000000 .4byte .LBE3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 60 - - - 1650 02ba C8020000 .4byte 0x2c8 - 1651 02be 19 .uleb128 0x19 - 1652 02bf FA010000 .4byte 0x1fa - 1653 02c3 73020000 .4byte .LLST10 - 1654 02c7 00 .byte 0 - 1655 02c8 1C .uleb128 0x1c - 1656 02c9 08000000 .4byte .LVL27 - 1657 02cd 30020000 .4byte 0x230 - 1658 02d1 DB020000 .4byte 0x2db - 1659 02d5 1D .uleb128 0x1d - 1660 02d6 01 .byte 0x1 - 1661 02d7 50 .byte 0x50 - 1662 02d8 01 .byte 0x1 - 1663 02d9 32 .byte 0x32 - 1664 02da 00 .byte 0 - 1665 02db 1C .uleb128 0x1c - 1666 02dc 10000000 .4byte .LVL28 - 1667 02e0 30020000 .4byte 0x230 - 1668 02e4 EE020000 .4byte 0x2ee - 1669 02e8 1D .uleb128 0x1d - 1670 02e9 01 .byte 0x1 - 1671 02ea 50 .byte 0x50 - 1672 02eb 01 .byte 0x1 - 1673 02ec 33 .byte 0x33 - 1674 02ed 00 .byte 0 - 1675 02ee 1C .uleb128 0x1c - 1676 02ef 1C000000 .4byte .LVL30 - 1677 02f3 30020000 .4byte 0x230 - 1678 02f7 01030000 .4byte 0x301 - 1679 02fb 1D .uleb128 0x1d - 1680 02fc 01 .byte 0x1 - 1681 02fd 50 .byte 0x50 - 1682 02fe 01 .byte 0x1 - 1683 02ff 32 .byte 0x32 - 1684 0300 00 .byte 0 - 1685 0301 1E .uleb128 0x1e - 1686 0302 42000000 .4byte .LVL38 - 1687 0306 30020000 .4byte 0x230 - 1688 030a 1D .uleb128 0x1d - 1689 030b 01 .byte 0x1 - 1690 030c 50 .byte 0x50 - 1691 030d 01 .byte 0x1 - 1692 030e 32 .byte 0x32 - 1693 030f 00 .byte 0 - 1694 0310 00 .byte 0 - 1695 0311 0D .uleb128 0xd - 1696 0312 3D030000 .4byte .LASF36 - 1697 0316 01 .byte 0x1 - 1698 0317 6E .byte 0x6e - 1699 0318 01 .byte 0x1 - 1700 0319 85000000 .4byte 0x85 - 1701 031d 01 .byte 0x1 - 1702 031e 44030000 .4byte 0x344 - 1703 0322 0E .uleb128 0xe - 1704 0323 FD030000 .4byte .LASF37 - 1705 0327 01 .byte 0x1 - 1706 0328 6E .byte 0x6e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 61 - - - 1707 0329 44030000 .4byte 0x344 - 1708 032d 0E .uleb128 0xe - 1709 032e 54040000 .4byte .LASF24 - 1710 0332 01 .byte 0x1 - 1711 0333 6E .byte 0x6e - 1712 0334 85000000 .4byte 0x85 - 1713 0338 0F .uleb128 0xf - 1714 0339 73756D00 .ascii "sum\000" - 1715 033d 01 .byte 0x1 - 1716 033e 9D .byte 0x9d - 1717 033f 85000000 .4byte 0x85 - 1718 0343 00 .byte 0 - 1719 0344 0B .uleb128 0xb - 1720 0345 04 .byte 0x4 - 1721 0346 4A030000 .4byte 0x34a - 1722 034a 1F .uleb128 0x1f - 1723 034b 7A000000 .4byte 0x7a - 1724 034f 0D .uleb128 0xd - 1725 0350 78030000 .4byte .LASF38 - 1726 0354 01 .byte 0x1 - 1727 0355 BD .byte 0xbd - 1728 0356 01 .byte 0x1 - 1729 0357 7A000000 .4byte 0x7a - 1730 035b 01 .byte 0x1 - 1731 035c 82030000 .4byte 0x382 - 1732 0360 0E .uleb128 0xe - 1733 0361 AA020000 .4byte .LASF23 - 1734 0365 01 .byte 0x1 - 1735 0366 BD .byte 0xbd - 1736 0367 90000000 .4byte 0x90 - 1737 036b 0E .uleb128 0xe - 1738 036c 54040000 .4byte .LASF24 - 1739 0370 01 .byte 0x1 - 1740 0371 BD .byte 0xbd - 1741 0372 90000000 .4byte 0x90 - 1742 0376 0F .uleb128 0xf - 1743 0377 73756D00 .ascii "sum\000" - 1744 037b 01 .byte 0x1 - 1745 037c C0 .byte 0xc0 - 1746 037d 7A000000 .4byte 0x7a - 1747 0381 00 .byte 0 - 1748 0382 10 .uleb128 0x10 - 1749 0383 06000000 .4byte .LASF39 - 1750 0387 01 .byte 0x1 - 1751 0388 0005 .2byte 0x500 - 1752 038a 01 .byte 0x1 - 1753 038b B0000000 .4byte 0xb0 - 1754 038f 01 .byte 0x1 - 1755 0390 C5030000 .4byte 0x3c5 - 1756 0394 11 .uleb128 0x11 - 1757 0395 5D030000 .4byte .LASF40 - 1758 0399 01 .byte 0x1 - 1759 039a 0005 .2byte 0x500 - 1760 039c 7A000000 .4byte 0x7a - 1761 03a0 11 .uleb128 0x11 - 1762 03a1 FD030000 .4byte .LASF37 - 1763 03a5 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 62 - - - 1764 03a6 0005 .2byte 0x500 - 1765 03a8 C5030000 .4byte 0x3c5 - 1766 03ac 11 .uleb128 0x11 - 1767 03ad 54040000 .4byte .LASF24 - 1768 03b1 01 .byte 0x1 - 1769 03b2 0005 .2byte 0x500 - 1770 03b4 85000000 .4byte 0x85 - 1771 03b8 12 .uleb128 0x12 - 1772 03b9 F2000000 .4byte .LASF41 - 1773 03bd 01 .byte 0x1 - 1774 03be 0305 .2byte 0x503 - 1775 03c0 85000000 .4byte 0x85 - 1776 03c4 00 .byte 0 - 1777 03c5 0B .uleb128 0xb - 1778 03c6 04 .byte 0x4 - 1779 03c7 7A000000 .4byte 0x7a - 1780 03cb 20 .uleb128 0x20 - 1781 03cc EB010000 .4byte .LASF43 - 1782 03d0 01 .byte 0x1 - 1783 03d1 6202 .2byte 0x262 - 1784 03d3 01 .byte 0x1 - 1785 03d4 00000000 .4byte .LFB64 - 1786 03d8 84030000 .4byte .LFE64 - 1787 03dc 87020000 .4byte .LLST11 - 1788 03e0 01 .byte 0x1 - 1789 03e1 F3070000 .4byte 0x7f3 - 1790 03e5 21 .uleb128 0x21 - 1791 03e6 CD030000 .4byte .LASF45 - 1792 03ea 01 .byte 0x1 - 1793 03eb 6202 .2byte 0x262 - 1794 03ed 7A000000 .4byte 0x7a - 1795 03f1 B4020000 .4byte .LLST12 - 1796 03f5 22 .uleb128 0x22 - 1797 03f6 D1010000 .4byte .LASF46 - 1798 03fa 01 .byte 0x1 - 1799 03fb 6402 .2byte 0x264 - 1800 03fd 85000000 .4byte 0x85 - 1801 0401 03 .byte 0x3 - 1802 0402 91 .byte 0x91 - 1803 0403 DC78 .sleb128 -932 - 1804 0405 23 .uleb128 0x23 - 1805 0406 D5030000 .4byte .LASF47 - 1806 040a 01 .byte 0x1 - 1807 040b 6502 .2byte 0x265 - 1808 040d 85000000 .4byte 0x85 - 1809 0411 D5020000 .4byte .LLST13 - 1810 0415 23 .uleb128 0x23 - 1811 0416 76000000 .4byte .LASF48 - 1812 041a 01 .byte 0x1 - 1813 041b 6602 .2byte 0x266 - 1814 041d 7A000000 .4byte 0x7a - 1815 0421 60030000 .4byte .LLST14 - 1816 0425 23 .uleb128 0x23 - 1817 0426 FE020000 .4byte .LASF49 - 1818 042a 01 .byte 0x1 - 1819 042b 6702 .2byte 0x267 - 1820 042d 85000000 .4byte 0x85 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 63 - - - 1821 0431 1A040000 .4byte .LLST15 - 1822 0435 23 .uleb128 0x23 - 1823 0436 A2030000 .4byte .LASF50 - 1824 043a 01 .byte 0x1 - 1825 043b 6802 .2byte 0x268 - 1826 043d B0000000 .4byte 0xb0 - 1827 0441 59070000 .4byte .LLST16 - 1828 0445 23 .uleb128 0x23 - 1829 0446 45000000 .4byte .LASF51 - 1830 044a 01 .byte 0x1 - 1831 044b 6902 .2byte 0x269 - 1832 044d 85000000 .4byte 0x85 - 1833 0451 6C070000 .4byte .LLST17 - 1834 0455 23 .uleb128 0x23 - 1835 0456 9A000000 .4byte .LASF52 - 1836 045a 01 .byte 0x1 - 1837 045b 6A02 .2byte 0x26a - 1838 045d 85000000 .4byte 0x85 - 1839 0461 6E080000 .4byte .LLST18 - 1840 0465 23 .uleb128 0x23 - 1841 0466 8A020000 .4byte .LASF53 - 1842 046a 01 .byte 0x1 - 1843 046b 6B02 .2byte 0x26b - 1844 046d 7A000000 .4byte 0x7a - 1845 0471 17090000 .4byte .LLST19 - 1846 0475 23 .uleb128 0x23 - 1847 0476 71020000 .4byte .LASF54 - 1848 047a 01 .byte 0x1 - 1849 047b 6E02 .2byte 0x26e - 1850 047d 7A000000 .4byte 0x7a - 1851 0481 4C090000 .4byte .LLST20 - 1852 0485 23 .uleb128 0x23 - 1853 0486 F7010000 .4byte .LASF55 - 1854 048a 01 .byte 0x1 - 1855 048b 7102 .2byte 0x271 - 1856 048d 7A000000 .4byte 0x7a - 1857 0491 98090000 .4byte .LLST21 - 1858 0495 22 .uleb128 0x22 - 1859 0496 6B030000 .4byte .LASF56 - 1860 049a 01 .byte 0x1 - 1861 049b 7302 .2byte 0x273 - 1862 049d F3070000 .4byte 0x7f3 - 1863 04a1 03 .byte 0x3 - 1864 04a2 91 .byte 0x91 - 1865 04a3 807B .sleb128 -640 - 1866 04a5 22 .uleb128 0x22 - 1867 04a6 BE020000 .4byte .LASF57 - 1868 04aa 01 .byte 0x1 - 1869 04ab 7402 .2byte 0x274 - 1870 04ad F3070000 .4byte 0x7f3 - 1871 04b1 03 .byte 0x3 - 1872 04b2 91 .byte 0x91 - 1873 04b3 AC7D .sleb128 -340 - 1874 04b5 24 .uleb128 0x24 - 1875 04b6 11030000 .4byte 0x311 - 1876 04ba 8E000000 .4byte .LBB20 - 1877 04be A2000000 .4byte .LBE20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 64 - - - 1878 04c2 01 .byte 0x1 - 1879 04c3 A902 .2byte 0x2a9 - 1880 04c5 EF040000 .4byte 0x4ef - 1881 04c9 18 .uleb128 0x18 - 1882 04ca 2D030000 .4byte 0x32d - 1883 04ce DA090000 .4byte .LLST22 - 1884 04d2 18 .uleb128 0x18 - 1885 04d3 22030000 .4byte 0x322 - 1886 04d7 1B0A0000 .4byte .LLST23 - 1887 04db 25 .uleb128 0x25 - 1888 04dc 8E000000 .4byte .LBB21 - 1889 04e0 A2000000 .4byte .LBE21 - 1890 04e4 19 .uleb128 0x19 - 1891 04e5 38030000 .4byte 0x338 - 1892 04e9 4D0A0000 .4byte .LLST24 - 1893 04ed 00 .byte 0 - 1894 04ee 00 .byte 0 - 1895 04ef 26 .uleb128 0x26 - 1896 04f0 00000000 .4byte .Ldebug_ranges0+0 - 1897 04f4 2B070000 .4byte 0x72b - 1898 04f8 23 .uleb128 0x23 - 1899 04f9 90000000 .4byte .LASF58 - 1900 04fd 01 .byte 0x1 - 1901 04fe B702 .2byte 0x2b7 - 1902 0500 7A000000 .4byte 0x7a - 1903 0504 A10A0000 .4byte .LLST25 - 1904 0508 1B .uleb128 0x1b - 1905 0509 C8000000 .4byte .LBB23 - 1906 050d DE000000 .4byte .LBE23 - 1907 0511 26050000 .4byte 0x526 - 1908 0515 23 .uleb128 0x23 - 1909 0516 87000000 .4byte .LASF59 - 1910 051a 01 .byte 0x1 - 1911 051b 0103 .2byte 0x301 - 1912 051d 85000000 .4byte 0x85 - 1913 0521 9D0B0000 .4byte .LLST26 - 1914 0525 00 .byte 0 - 1915 0526 1B .uleb128 0x1b - 1916 0527 26020000 .4byte .LBB24 - 1917 052b 44020000 .4byte .LBE24 - 1918 052f 89050000 .4byte 0x589 - 1919 0533 22 .uleb128 0x22 - 1920 0534 95040000 .4byte .LASF60 - 1921 0538 01 .byte 0x1 - 1922 0539 9403 .2byte 0x394 - 1923 053b 04080000 .4byte 0x804 - 1924 053f 03 .byte 0x3 - 1925 0540 91 .byte 0x91 - 1926 0541 E078 .sleb128 -928 - 1927 0543 1C .uleb128 0x1c - 1928 0544 32020000 .4byte .LVL98 - 1929 0548 BE0A0000 .4byte 0xabe - 1930 054c 65050000 .4byte 0x565 - 1931 0550 1D .uleb128 0x1d - 1932 0551 01 .byte 0x1 - 1933 0552 52 .byte 0x52 - 1934 0553 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 65 - - - 1935 0554 0A .byte 0xa - 1936 0555 2001 .2byte 0x120 - 1937 0557 1D .uleb128 0x1d - 1938 0558 01 .byte 0x1 - 1939 0559 51 .byte 0x51 - 1940 055a 02 .byte 0x2 - 1941 055b 7A .byte 0x7a - 1942 055c 00 .sleb128 0 - 1943 055d 1D .uleb128 0x1d - 1944 055e 01 .byte 0x1 - 1945 055f 50 .byte 0x50 - 1946 0560 03 .byte 0x3 - 1947 0561 91 .byte 0x91 - 1948 0562 E078 .sleb128 -928 - 1949 0564 00 .byte 0 - 1950 0565 1E .uleb128 0x1e - 1951 0566 40020000 .4byte .LVL99 - 1952 056a DF0A0000 .4byte 0xadf - 1953 056e 1D .uleb128 0x1d - 1954 056f 01 .byte 0x1 - 1955 0570 53 .byte 0x53 - 1956 0571 03 .byte 0x3 - 1957 0572 0A .byte 0xa - 1958 0573 2001 .2byte 0x120 - 1959 0575 1D .uleb128 0x1d - 1960 0576 01 .byte 0x1 - 1961 0577 52 .byte 0x52 - 1962 0578 03 .byte 0x3 - 1963 0579 91 .byte 0x91 - 1964 057a E078 .sleb128 -928 - 1965 057c 1D .uleb128 0x1d - 1966 057d 01 .byte 0x1 - 1967 057e 51 .byte 0x51 - 1968 057f 02 .byte 0x2 - 1969 0580 08 .byte 0x8 - 1970 0581 FF .byte 0xff - 1971 0582 1D .uleb128 0x1d - 1972 0583 01 .byte 0x1 - 1973 0584 50 .byte 0x50 - 1974 0585 01 .byte 0x1 - 1975 0586 31 .byte 0x31 - 1976 0587 00 .byte 0 - 1977 0588 00 .byte 0 - 1978 0589 1B .uleb128 0x1b - 1979 058a 84020000 .4byte .LBB25 - 1980 058e 9A020000 .4byte .LBE25 - 1981 0592 A7050000 .4byte 0x5a7 - 1982 0596 22 .uleb128 0x22 - 1983 0597 B8000000 .4byte .LASF61 - 1984 059b 01 .byte 0x1 - 1985 059c 6104 .2byte 0x461 - 1986 059e 15010000 .4byte 0x115 - 1987 05a2 03 .byte 0x3 - 1988 05a3 91 .byte 0x91 - 1989 05a4 E078 .sleb128 -928 - 1990 05a6 00 .byte 0 - 1991 05a7 1B .uleb128 0x1b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 66 - - - 1992 05a8 A2020000 .4byte .LBB26 - 1993 05ac 26030000 .4byte .LBE26 - 1994 05b0 6F060000 .4byte 0x66f - 1995 05b4 23 .uleb128 0x23 - 1996 05b5 64030000 .4byte .LASF62 - 1997 05b9 01 .byte 0x1 - 1998 05ba 8104 .2byte 0x481 - 1999 05bc 85000000 .4byte 0x85 - 2000 05c0 B10B0000 .4byte .LLST27 - 2001 05c4 23 .uleb128 0x23 - 2002 05c5 39040000 .4byte .LASF63 - 2003 05c9 01 .byte 0x1 - 2004 05ca 8604 .2byte 0x486 - 2005 05cc 90000000 .4byte 0x90 - 2006 05d0 1D0C0000 .4byte .LLST28 - 2007 05d4 23 .uleb128 0x23 - 2008 05d5 F2000000 .4byte .LASF41 - 2009 05d9 01 .byte 0x1 - 2010 05da 8704 .2byte 0x487 - 2011 05dc 7A000000 .4byte 0x7a - 2012 05e0 810C0000 .4byte .LLST29 - 2013 05e4 24 .uleb128 0x24 - 2014 05e5 29010000 .4byte 0x129 - 2015 05e9 BC020000 .4byte .LBB27 - 2016 05ed CC020000 .4byte .LBE27 - 2017 05f1 01 .byte 0x1 - 2018 05f2 9004 .2byte 0x490 - 2019 05f4 1E060000 .4byte 0x61e - 2020 05f8 18 .uleb128 0x18 - 2021 05f9 3A010000 .4byte 0x13a - 2022 05fd B50C0000 .4byte .LLST30 - 2023 0601 25 .uleb128 0x25 - 2024 0602 BC020000 .4byte .LBB28 - 2025 0606 CC020000 .4byte .LBE28 - 2026 060a 19 .uleb128 0x19 - 2027 060b 50010000 .4byte 0x150 - 2028 060f C80C0000 .4byte .LLST31 - 2029 0613 18 .uleb128 0x18 - 2030 0614 45010000 .4byte 0x145 - 2031 0618 E70C0000 .4byte .LLST32 - 2032 061c 00 .byte 0 - 2033 061d 00 .byte 0 - 2034 061e 24 .uleb128 0x24 - 2035 061f 4F030000 .4byte 0x34f - 2036 0623 D8020000 .4byte .LBB29 - 2037 0627 E4020000 .4byte .LBE29 - 2038 062b 01 .byte 0x1 - 2039 062c 9804 .2byte 0x498 - 2040 062e 58060000 .4byte 0x658 - 2041 0632 18 .uleb128 0x18 - 2042 0633 6B030000 .4byte 0x36b - 2043 0637 130D0000 .4byte .LLST33 - 2044 063b 18 .uleb128 0x18 - 2045 063c 60030000 .4byte 0x360 - 2046 0640 340D0000 .4byte .LLST34 - 2047 0644 25 .uleb128 0x25 - 2048 0645 D8020000 .4byte .LBB30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 67 - - - 2049 0649 E4020000 .4byte .LBE30 - 2050 064d 19 .uleb128 0x19 - 2051 064e 76030000 .4byte 0x376 - 2052 0652 800D0000 .4byte .LLST35 - 2053 0656 00 .byte 0 - 2054 0657 00 .byte 0 - 2055 0658 25 .uleb128 0x25 - 2056 0659 EA020000 .4byte .LBB31 - 2057 065d 00030000 .4byte .LBE31 - 2058 0661 12 .uleb128 0x12 - 2059 0662 C8010000 .4byte .LASF64 - 2060 0666 01 .byte 0x1 - 2061 0667 AA04 .2byte 0x4aa - 2062 0669 85000000 .4byte 0x85 - 2063 066d 00 .byte 0 - 2064 066e 00 .byte 0 - 2065 066f 27 .uleb128 0x27 - 2066 0670 9C010000 .4byte .LVL84 - 2067 0674 71020000 .4byte 0x271 - 2068 0678 1C .uleb128 0x1c - 2069 0679 D2010000 .4byte .LVL88 - 2070 067d BE0A0000 .4byte 0xabe - 2071 0681 98060000 .4byte 0x698 - 2072 0685 1D .uleb128 0x1d - 2073 0686 01 .byte 0x1 - 2074 0687 52 .byte 0x52 - 2075 0688 02 .byte 0x2 - 2076 0689 77 .byte 0x77 - 2077 068a 00 .sleb128 0 - 2078 068b 1D .uleb128 0x1d - 2079 068c 01 .byte 0x1 - 2080 068d 51 .byte 0x51 - 2081 068e 01 .byte 0x1 - 2082 068f 30 .byte 0x30 - 2083 0690 1D .uleb128 0x1d - 2084 0691 01 .byte 0x1 - 2085 0692 50 .byte 0x50 - 2086 0693 03 .byte 0x3 - 2087 0694 91 .byte 0x91 - 2088 0695 AC7D .sleb128 -340 - 2089 0697 00 .byte 0 - 2090 0698 1C .uleb128 0x1c - 2091 0699 F0010000 .4byte .LVL92 - 2092 069d 060B0000 .4byte 0xb06 - 2093 06a1 C0060000 .4byte 0x6c0 - 2094 06a5 1D .uleb128 0x1d - 2095 06a6 01 .byte 0x1 - 2096 06a7 52 .byte 0x52 - 2097 06a8 02 .byte 0x2 - 2098 06a9 75 .byte 0x75 - 2099 06aa 00 .sleb128 0 - 2100 06ab 1D .uleb128 0x1d - 2101 06ac 01 .byte 0x1 - 2102 06ad 51 .byte 0x51 - 2103 06ae 03 .byte 0x3 - 2104 06af 91 .byte 0x91 - 2105 06b0 877B .sleb128 -633 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 68 - - - 2106 06b2 1D .uleb128 0x1d - 2107 06b3 01 .byte 0x1 - 2108 06b4 50 .byte 0x50 - 2109 06b5 09 .byte 0x9 - 2110 06b6 91 .byte 0x91 - 2111 06b7 00 .sleb128 0 - 2112 06b8 77 .byte 0x77 - 2113 06b9 00 .sleb128 0 - 2114 06ba 22 .byte 0x22 - 2115 06bb 0A .byte 0xa - 2116 06bc 5401 .2byte 0x154 - 2117 06be 1C .byte 0x1c - 2118 06bf 00 .byte 0 - 2119 06c0 27 .uleb128 0x27 - 2120 06c1 00020000 .4byte .LVL94 - 2121 06c5 270B0000 .4byte 0xb27 - 2122 06c9 1C .uleb128 0x1c - 2123 06ca 50020000 .4byte .LVL101 - 2124 06ce DF0A0000 .4byte 0xadf - 2125 06d2 F0060000 .4byte 0x6f0 - 2126 06d6 1D .uleb128 0x1d - 2127 06d7 01 .byte 0x1 - 2128 06d8 53 .byte 0x53 - 2129 06d9 02 .byte 0x2 - 2130 06da 76 .byte 0x76 - 2131 06db 00 .sleb128 0 - 2132 06dc 1D .uleb128 0x1d - 2133 06dd 01 .byte 0x1 - 2134 06de 52 .byte 0x52 - 2135 06df 03 .byte 0x3 - 2136 06e0 91 .byte 0x91 - 2137 06e1 AC7D .sleb128 -340 - 2138 06e3 1D .uleb128 0x1d - 2139 06e4 01 .byte 0x1 - 2140 06e5 51 .byte 0x51 - 2141 06e6 02 .byte 0x2 - 2142 06e7 75 .byte 0x75 - 2143 06e8 00 .sleb128 0 - 2144 06e9 1D .uleb128 0x1d - 2145 06ea 01 .byte 0x1 - 2146 06eb 50 .byte 0x50 - 2147 06ec 02 .byte 0x2 - 2148 06ed 7B .byte 0x7b - 2149 06ee 00 .sleb128 0 - 2150 06ef 00 .byte 0 - 2151 06f0 1C .uleb128 0x1c - 2152 06f1 7A020000 .4byte .LVL106 - 2153 06f5 060B0000 .4byte 0xb06 - 2154 06f9 18070000 .4byte 0x718 - 2155 06fd 1D .uleb128 0x1d - 2156 06fe 01 .byte 0x1 - 2157 06ff 52 .byte 0x52 - 2158 0700 02 .byte 0x2 - 2159 0701 75 .byte 0x75 - 2160 0702 00 .sleb128 0 - 2161 0703 1D .uleb128 0x1d - 2162 0704 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 69 - - - 2163 0705 51 .byte 0x51 - 2164 0706 03 .byte 0x3 - 2165 0707 91 .byte 0x91 - 2166 0708 847B .sleb128 -636 - 2167 070a 1D .uleb128 0x1d - 2168 070b 01 .byte 0x1 - 2169 070c 50 .byte 0x50 - 2170 070d 09 .byte 0x9 - 2171 070e 91 .byte 0x91 - 2172 070f 00 .sleb128 0 - 2173 0710 77 .byte 0x77 - 2174 0711 00 .sleb128 0 - 2175 0712 22 .byte 0x22 - 2176 0713 0A .byte 0xa - 2177 0714 5401 .2byte 0x154 - 2178 0716 1C .byte 0x1c - 2179 0717 00 .byte 0 - 2180 0718 27 .uleb128 0x27 - 2181 0719 2A030000 .4byte .LVL134 - 2182 071d 71020000 .4byte 0x271 - 2183 0721 27 .uleb128 0x27 - 2184 0722 36030000 .4byte .LVL136 - 2185 0726 310B0000 .4byte 0xb31 - 2186 072a 00 .byte 0 - 2187 072b 24 .uleb128 0x24 - 2188 072c 82030000 .4byte 0x382 - 2189 0730 DE000000 .4byte .LBB32 - 2190 0734 34010000 .4byte .LBE32 - 2191 0738 01 .byte 0x1 - 2192 0739 E504 .2byte 0x4e5 - 2193 073b CA070000 .4byte 0x7ca - 2194 073f 28 .uleb128 0x28 - 2195 0740 AC030000 .4byte 0x3ac - 2196 0744 03 .byte 0x3 - 2197 0745 91 .byte 0x91 - 2198 0746 DE78 .sleb128 -930 - 2199 0748 18 .uleb128 0x18 - 2200 0749 A0030000 .4byte 0x3a0 - 2201 074d 9F0D0000 .4byte .LLST36 - 2202 0751 18 .uleb128 0x18 - 2203 0752 94030000 .4byte 0x394 - 2204 0756 CE0D0000 .4byte .LLST37 - 2205 075a 25 .uleb128 0x25 - 2206 075b DE000000 .4byte .LBB33 - 2207 075f 34010000 .4byte .LBE33 - 2208 0763 29 .uleb128 0x29 - 2209 0764 B8030000 .4byte 0x3b8 - 2210 0768 01 .byte 0x1 - 2211 0769 52 .byte 0x52 - 2212 076a 24 .uleb128 0x24 - 2213 076b 11030000 .4byte 0x311 - 2214 076f FA000000 .4byte .LBB34 - 2215 0773 10010000 .4byte .LBE34 - 2216 0777 01 .byte 0x1 - 2217 0778 0C05 .2byte 0x50c - 2218 077a A4070000 .4byte 0x7a4 - 2219 077e 18 .uleb128 0x18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 70 - - - 2220 077f 2D030000 .4byte 0x32d - 2221 0783 E10D0000 .4byte .LLST38 - 2222 0787 18 .uleb128 0x18 - 2223 0788 22030000 .4byte 0x322 - 2224 078c F40D0000 .4byte .LLST39 - 2225 0790 25 .uleb128 0x25 - 2226 0791 FA000000 .4byte .LBB35 - 2227 0795 10010000 .4byte .LBE35 - 2228 0799 19 .uleb128 0x19 - 2229 079a 38030000 .4byte 0x338 - 2230 079e 230E0000 .4byte .LLST40 - 2231 07a2 00 .byte 0 - 2232 07a3 00 .byte 0 - 2233 07a4 1E .uleb128 0x1e - 2234 07a5 34010000 .4byte .LVL78 - 2235 07a9 3B0B0000 .4byte 0xb3b - 2236 07ad 1D .uleb128 0x1d - 2237 07ae 01 .byte 0x1 - 2238 07af 53 .byte 0x53 - 2239 07b0 02 .byte 0x2 - 2240 07b1 09 .byte 0x9 - 2241 07b2 96 .byte 0x96 - 2242 07b3 1D .uleb128 0x1d - 2243 07b4 01 .byte 0x1 - 2244 07b5 52 .byte 0x52 - 2245 07b6 03 .byte 0x3 - 2246 07b7 91 .byte 0x91 - 2247 07b8 DE78 .sleb128 -930 - 2248 07ba 1D .uleb128 0x1d - 2249 07bb 01 .byte 0x1 - 2250 07bc 51 .byte 0x51 - 2251 07bd 02 .byte 0x2 - 2252 07be 74 .byte 0x74 - 2253 07bf 07 .sleb128 7 - 2254 07c0 1D .uleb128 0x1d - 2255 07c1 01 .byte 0x1 - 2256 07c2 50 .byte 0x50 - 2257 07c3 03 .byte 0x3 - 2258 07c4 91 .byte 0x91 - 2259 07c5 807B .sleb128 -640 - 2260 07c7 00 .byte 0 - 2261 07c8 00 .byte 0 - 2262 07c9 00 .byte 0 - 2263 07ca 27 .uleb128 0x27 - 2264 07cb 0E000000 .4byte .LVL49 - 2265 07cf 680B0000 .4byte 0xb68 - 2266 07d3 1E .uleb128 0x1e - 2267 07d4 32000000 .4byte .LVL54 - 2268 07d8 720B0000 .4byte 0xb72 - 2269 07dc 1D .uleb128 0x1d - 2270 07dd 01 .byte 0x1 - 2271 07de 52 .byte 0x52 - 2272 07df 03 .byte 0x3 - 2273 07e0 91 .byte 0x91 - 2274 07e1 DC78 .sleb128 -932 - 2275 07e3 1D .uleb128 0x1d - 2276 07e4 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 71 - - - 2277 07e5 51 .byte 0x51 - 2278 07e6 03 .byte 0x3 - 2279 07e7 0A .byte 0xa - 2280 07e8 2C01 .2byte 0x12c - 2281 07ea 1D .uleb128 0x1d - 2282 07eb 01 .byte 0x1 - 2283 07ec 50 .byte 0x50 - 2284 07ed 03 .byte 0x3 - 2285 07ee 91 .byte 0x91 - 2286 07ef 807B .sleb128 -640 - 2287 07f1 00 .byte 0 - 2288 07f2 00 .byte 0 - 2289 07f3 08 .uleb128 0x8 - 2290 07f4 7A000000 .4byte 0x7a - 2291 07f8 04080000 .4byte 0x804 - 2292 07fc 2A .uleb128 0x2a - 2293 07fd 0E010000 .4byte 0x10e - 2294 0801 2B01 .2byte 0x12b - 2295 0803 00 .byte 0 - 2296 0804 08 .uleb128 0x8 - 2297 0805 7A000000 .4byte 0x7a - 2298 0809 15080000 .4byte 0x815 - 2299 080d 2A .uleb128 0x2a - 2300 080e 0E010000 .4byte 0x10e - 2301 0812 1F01 .2byte 0x11f - 2302 0814 00 .byte 0 - 2303 0815 2B .uleb128 0x2b - 2304 0816 95020000 .4byte .LASF95 - 2305 081a 01 .byte 0x1 - 2306 081b 8901 .2byte 0x189 - 2307 081d 01 .byte 0x1 - 2308 081e 01 .byte 0x1 - 2309 081f 2C .uleb128 0x2c - 2310 0820 01 .byte 0x1 - 2311 0821 54010000 .4byte .LASF67 - 2312 0825 01 .byte 0x1 - 2313 0826 1001 .2byte 0x110 - 2314 0828 01 .byte 0x1 - 2315 0829 00000000 .4byte .LFB59 - 2316 082d 80000000 .4byte .LFE59 - 2317 0831 360E0000 .4byte .LLST41 - 2318 0835 01 .byte 0x1 - 2319 0836 41090000 .4byte 0x941 - 2320 083a 23 .uleb128 0x23 - 2321 083b DC010000 .4byte .LASF34 - 2322 083f 01 .byte 0x1 - 2323 0840 1301 .2byte 0x113 - 2324 0842 7A000000 .4byte 0x7a - 2325 0846 630E0000 .4byte .LLST42 - 2326 084a 22 .uleb128 0x22 - 2327 084b 67000000 .4byte .LASF65 - 2328 084f 01 .byte 0x1 - 2329 0850 1701 .2byte 0x117 - 2330 0852 04080000 .4byte 0x804 - 2331 0856 03 .byte 0x3 - 2332 0857 91 .byte 0x91 - 2333 0858 D87D .sleb128 -296 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 72 - - - 2334 085a 23 .uleb128 0x23 - 2335 085b 22000000 .4byte .LASF66 - 2336 085f 01 .byte 0x1 - 2337 0860 1A01 .2byte 0x11a - 2338 0862 B0000000 .4byte 0xb0 - 2339 0866 7C0E0000 .4byte .LLST43 - 2340 086a 24 .uleb128 0x24 - 2341 086b 4F030000 .4byte 0x34f - 2342 086f 28000000 .4byte .LBB41 - 2343 0873 34000000 .4byte .LBE41 - 2344 0877 01 .byte 0x1 - 2345 0878 4901 .2byte 0x149 - 2346 087a A1080000 .4byte 0x8a1 - 2347 087e 18 .uleb128 0x18 - 2348 087f 6B030000 .4byte 0x36b - 2349 0883 8F0E0000 .4byte .LLST44 - 2350 0887 1A .uleb128 0x1a - 2351 0888 60030000 .4byte 0x360 - 2352 088c 00 .byte 0 - 2353 088d 25 .uleb128 0x25 - 2354 088e 28000000 .4byte .LBB42 - 2355 0892 34000000 .4byte .LBE42 - 2356 0896 19 .uleb128 0x19 - 2357 0897 76030000 .4byte 0x376 - 2358 089b A20E0000 .4byte .LLST45 - 2359 089f 00 .byte 0 - 2360 08a0 00 .byte 0 - 2361 08a1 24 .uleb128 0x24 - 2362 08a2 15080000 .4byte 0x815 - 2363 08a6 6A000000 .4byte .LBB43 - 2364 08aa 72000000 .4byte .LBE43 - 2365 08ae 01 .byte 0x1 - 2366 08af 7701 .2byte 0x177 - 2367 08b1 BF080000 .4byte 0x8bf - 2368 08b5 27 .uleb128 0x27 - 2369 08b6 72000000 .4byte .LVL164 - 2370 08ba 310B0000 .4byte 0xb31 - 2371 08be 00 .byte 0 - 2372 08bf 27 .uleb128 0x27 - 2373 08c0 08000000 .4byte .LVL149 - 2374 08c4 990B0000 .4byte 0xb99 - 2375 08c8 1C .uleb128 0x1c - 2376 08c9 10000000 .4byte .LVL150 - 2377 08cd A70B0000 .4byte 0xba7 - 2378 08d1 DB080000 .4byte 0x8db - 2379 08d5 1D .uleb128 0x1d - 2380 08d6 01 .byte 0x1 - 2381 08d7 50 .byte 0x50 - 2382 08d8 01 .byte 0x1 - 2383 08d9 30 .byte 0x30 - 2384 08da 00 .byte 0 - 2385 08db 1C .uleb128 0x1c - 2386 08dc 16000000 .4byte .LVL151 - 2387 08e0 BB0B0000 .4byte 0xbbb - 2388 08e4 EF080000 .4byte 0x8ef - 2389 08e8 1D .uleb128 0x1d - 2390 08e9 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 73 - - - 2391 08ea 50 .byte 0x50 - 2392 08eb 02 .byte 0x2 - 2393 08ec 7D .byte 0x7d - 2394 08ed 00 .sleb128 0 - 2395 08ee 00 .byte 0 - 2396 08ef 1C .uleb128 0x1c - 2397 08f0 1E000000 .4byte .LVL152 - 2398 08f4 A70B0000 .4byte 0xba7 - 2399 08f8 02090000 .4byte 0x902 - 2400 08fc 1D .uleb128 0x1d - 2401 08fd 01 .byte 0x1 - 2402 08fe 50 .byte 0x50 - 2403 08ff 01 .byte 0x1 - 2404 0900 30 .byte 0x30 - 2405 0901 00 .byte 0 - 2406 0902 1C .uleb128 0x1c - 2407 0903 4A000000 .4byte .LVL159 - 2408 0907 A70B0000 .4byte 0xba7 - 2409 090b 15090000 .4byte 0x915 - 2410 090f 1D .uleb128 0x1d - 2411 0910 01 .byte 0x1 - 2412 0911 50 .byte 0x50 - 2413 0912 01 .byte 0x1 - 2414 0913 30 .byte 0x30 - 2415 0914 00 .byte 0 - 2416 0915 27 .uleb128 0x27 - 2417 0916 50000000 .4byte .LVL160 - 2418 091a 71020000 .4byte 0x271 - 2419 091e 1C .uleb128 0x1c - 2420 091f 64000000 .4byte .LVL162 - 2421 0923 CB030000 .4byte 0x3cb - 2422 0927 31090000 .4byte 0x931 - 2423 092b 1D .uleb128 0x1d - 2424 092c 01 .byte 0x1 - 2425 092d 50 .byte 0x50 - 2426 092e 01 .byte 0x1 - 2427 092f 30 .byte 0x30 - 2428 0930 00 .byte 0 - 2429 0931 1E .uleb128 0x1e - 2430 0932 6A000000 .4byte .LVL163 - 2431 0936 CB030000 .4byte 0x3cb - 2432 093a 1D .uleb128 0x1d - 2433 093b 01 .byte 0x1 - 2434 093c 50 .byte 0x50 - 2435 093d 01 .byte 0x1 - 2436 093e 44 .byte 0x44 - 2437 093f 00 .byte 0 - 2438 0940 00 .byte 0 - 2439 0941 2C .uleb128 0x2c - 2440 0942 01 .byte 0x1 - 2441 0943 0A030000 .4byte .LASF68 - 2442 0947 01 .byte 0x1 - 2443 0948 A301 .2byte 0x1a3 - 2444 094a 01 .byte 0x1 - 2445 094b 00000000 .4byte .LFB61 - 2446 094f 30000000 .4byte .LFE61 - 2447 0953 CC0E0000 .4byte .LLST46 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 74 - - - 2448 0957 01 .byte 0x1 - 2449 0958 8D090000 .4byte 0x98d - 2450 095c 1C .uleb128 0x1c - 2451 095d 18000000 .4byte .LVL165 - 2452 0961 30020000 .4byte 0x230 - 2453 0965 6F090000 .4byte 0x96f - 2454 0969 1D .uleb128 0x1d - 2455 096a 01 .byte 0x1 - 2456 096b 50 .byte 0x50 - 2457 096c 01 .byte 0x1 - 2458 096d 31 .byte 0x31 - 2459 096e 00 .byte 0 - 2460 096f 1C .uleb128 0x1c - 2461 0970 20000000 .4byte .LVL166 - 2462 0974 30020000 .4byte 0x230 - 2463 0978 82090000 .4byte 0x982 - 2464 097c 1D .uleb128 0x1d - 2465 097d 01 .byte 0x1 - 2466 097e 50 .byte 0x50 - 2467 097f 01 .byte 0x1 - 2468 0980 31 .byte 0x31 - 2469 0981 00 .byte 0 - 2470 0982 2D .uleb128 0x2d - 2471 0983 28000000 .4byte .LVL167 - 2472 0987 01 .byte 0x1 - 2473 0988 08020000 .4byte 0x208 - 2474 098c 00 .byte 0 - 2475 098d 2C .uleb128 0x2c - 2476 098e 01 .byte 0x1 - 2477 098f E0040000 .4byte .LASF69 - 2478 0993 01 .byte 0x1 - 2479 0994 2905 .2byte 0x529 - 2480 0996 01 .byte 0x1 - 2481 0997 00000000 .4byte .LFB66 - 2482 099b 34000000 .4byte .LFE66 - 2483 099f EC0E0000 .4byte .LLST47 - 2484 09a3 01 .byte 0x1 - 2485 09a4 480A0000 .4byte 0xa48 - 2486 09a8 21 .uleb128 0x21 - 2487 09a9 B8010000 .4byte .LASF70 - 2488 09ad 01 .byte 0x1 - 2489 09ae 2905 .2byte 0x529 - 2490 09b0 90000000 .4byte 0x90 - 2491 09b4 190F0000 .4byte .LLST48 - 2492 09b8 21 .uleb128 0x21 - 2493 09b9 E3000000 .4byte .LASF71 - 2494 09bd 01 .byte 0x1 - 2495 09be 2905 .2byte 0x529 - 2496 09c0 7A000000 .4byte 0x7a - 2497 09c4 3A0F0000 .4byte .LLST49 - 2498 09c8 23 .uleb128 0x23 - 2499 09c9 B0010000 .4byte .LASF72 - 2500 09cd 01 .byte 0x1 - 2501 09ce 2B05 .2byte 0x52b - 2502 09d0 90000000 .4byte 0x90 - 2503 09d4 190F0000 .4byte .LLST48 - 2504 09d8 22 .uleb128 0x22 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 75 - - - 2505 09d9 55000000 .4byte .LASF73 - 2506 09dd 01 .byte 0x1 - 2507 09de 2C05 .2byte 0x52c - 2508 09e0 480A0000 .4byte 0xa48 - 2509 09e4 03 .byte 0x3 - 2510 09e5 91 .byte 0x91 - 2511 09e6 F07D .sleb128 -272 - 2512 09e8 22 .uleb128 0x22 - 2513 09e9 8D040000 .4byte .LASF74 - 2514 09ed 01 .byte 0x1 - 2515 09ee 2F05 .2byte 0x52f - 2516 09f0 7A000000 .4byte 0x7a - 2517 09f4 01 .byte 0x1 - 2518 09f5 54 .byte 0x54 - 2519 09f6 23 .uleb128 0x23 - 2520 09f7 64030000 .4byte .LASF62 - 2521 09fb 01 .byte 0x1 - 2522 09fc 3205 .2byte 0x532 - 2523 09fe 85000000 .4byte 0x85 - 2524 0a02 6E0F0000 .4byte .LLST51 - 2525 0a06 22 .uleb128 0x22 - 2526 0a07 2C000000 .4byte .LASF75 - 2527 0a0b 01 .byte 0x1 - 2528 0a0c 3305 .2byte 0x533 - 2529 0a0e 90000000 .4byte 0x90 - 2530 0a12 01 .byte 0x1 - 2531 0a13 56 .byte 0x56 - 2532 0a14 2E .uleb128 0x2e - 2533 0a15 69647800 .ascii "idx\000" - 2534 0a19 01 .byte 0x1 - 2535 0a1a 3405 .2byte 0x534 - 2536 0a1c 85000000 .4byte 0x85 - 2537 0a20 A00F0000 .4byte .LLST52 - 2538 0a24 1E .uleb128 0x1e - 2539 0a25 30000000 .4byte .LVL176 - 2540 0a29 D30B0000 .4byte 0xbd3 - 2541 0a2d 1D .uleb128 0x1d - 2542 0a2e 01 .byte 0x1 - 2543 0a2f 52 .byte 0x52 - 2544 0a30 02 .byte 0x2 - 2545 0a31 7D .byte 0x7d - 2546 0a32 00 .sleb128 0 - 2547 0a33 1D .uleb128 0x1d - 2548 0a34 01 .byte 0x1 - 2549 0a35 51 .byte 0x51 - 2550 0a36 09 .byte 0x9 - 2551 0a37 F3 .byte 0xf3 - 2552 0a38 01 .uleb128 0x1 - 2553 0a39 50 .byte 0x50 - 2554 0a3a 09 .byte 0x9 - 2555 0a3b F4 .byte 0xf4 - 2556 0a3c 24 .byte 0x24 - 2557 0a3d 09 .byte 0x9 - 2558 0a3e FC .byte 0xfc - 2559 0a3f 25 .byte 0x25 - 2560 0a40 1D .uleb128 0x1d - 2561 0a41 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 76 - - - 2562 0a42 50 .byte 0x50 - 2563 0a43 02 .byte 0x2 - 2564 0a44 74 .byte 0x74 - 2565 0a45 00 .sleb128 0 - 2566 0a46 00 .byte 0 - 2567 0a47 00 .byte 0 - 2568 0a48 08 .uleb128 0x8 - 2569 0a49 7A000000 .4byte 0x7a - 2570 0a4d 580A0000 .4byte 0xa58 - 2571 0a51 09 .uleb128 0x9 - 2572 0a52 0E010000 .4byte 0x10e - 2573 0a56 FF .byte 0xff - 2574 0a57 00 .byte 0 - 2575 0a58 2F .uleb128 0x2f - 2576 0a59 48040000 .4byte .LASF76 - 2577 0a5d 01 .byte 0x1 - 2578 0a5e 26 .byte 0x26 - 2579 0a5f 4A030000 .4byte 0x34a - 2580 0a63 01 .byte 0x1 - 2581 0a64 05 .byte 0x5 - 2582 0a65 03 .byte 0x3 - 2583 0a66 00000000 .4byte BL_Checksum - 2584 0a6a 2F .uleb128 0x2f - 2585 0a6b 6C040000 .4byte .LASF77 - 2586 0a6f 01 .byte 0x1 - 2587 0a70 27 .byte 0x27 - 2588 0a71 44030000 .4byte 0x344 - 2589 0a75 01 .byte 0x1 - 2590 0a76 05 .byte 0x5 - 2591 0a77 03 .byte 0x3 - 2592 0a78 00000000 .4byte BL_ChecksumAccess - 2593 0a7c 2F .uleb128 0x2f - 2594 0a7d 8C030000 .4byte .LASF78 - 2595 0a81 01 .byte 0x1 - 2596 0a82 2F .byte 0x2f - 2597 0a83 8E0A0000 .4byte 0xa8e - 2598 0a87 01 .byte 0x1 - 2599 0a88 05 .byte 0x5 - 2600 0a89 03 .byte 0x3 - 2601 0a8a 00000000 .4byte BL_SizeBytes - 2602 0a8e 1F .uleb128 0x1f - 2603 0a8f 90000000 .4byte 0x90 - 2604 0a93 2F .uleb128 0x2f - 2605 0a94 A5000000 .4byte .LASF79 - 2606 0a98 01 .byte 0x1 - 2607 0a99 30 .byte 0x30 - 2608 0a9a A50A0000 .4byte 0xaa5 - 2609 0a9e 01 .byte 0x1 - 2610 0a9f 05 .byte 0x5 - 2611 0aa0 03 .byte 0x3 - 2612 0aa1 00000000 .4byte BL_SizeBytesAccess - 2613 0aa5 0B .uleb128 0xb - 2614 0aa6 04 .byte 0x4 - 2615 0aa7 8E0A0000 .4byte 0xa8e - 2616 0aab 30 .uleb128 0x30 - 2617 0aac AD040000 .4byte .LASF80 - 2618 0ab0 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 77 - - - 2619 0ab1 1606 .2byte 0x616 - 2620 0ab3 B90A0000 .4byte 0xab9 - 2621 0ab7 01 .byte 0x1 - 2622 0ab8 01 .byte 0x1 - 2623 0ab9 05 .uleb128 0x5 - 2624 0aba 45000000 .4byte 0x45 - 2625 0abe 31 .uleb128 0x31 - 2626 0abf 01 .byte 0x1 - 2627 0ac0 8F010000 .4byte .LASF81 - 2628 0ac4 01 .byte 0x1 - 2629 0ac5 20010000 .4byte 0x120 - 2630 0ac9 01 .byte 0x1 - 2631 0aca 01 .byte 0x1 - 2632 0acb DF0A0000 .4byte 0xadf - 2633 0acf 32 .uleb128 0x32 - 2634 0ad0 20010000 .4byte 0x120 - 2635 0ad4 32 .uleb128 0x32 - 2636 0ad5 6C000000 .4byte 0x6c - 2637 0ad9 32 .uleb128 0x32 - 2638 0ada 0E010000 .4byte 0x10e - 2639 0ade 00 .byte 0 - 2640 0adf 33 .uleb128 0x33 - 2641 0ae0 01 .byte 0x1 - 2642 0ae1 C7040000 .4byte .LASF85 - 2643 0ae5 06 .byte 0x6 - 2644 0ae6 42 .byte 0x42 - 2645 0ae7 01 .byte 0x1 - 2646 0ae8 B0000000 .4byte 0xb0 - 2647 0aec 01 .byte 0x1 - 2648 0aed 060B0000 .4byte 0xb06 - 2649 0af1 32 .uleb128 0x32 - 2650 0af2 7A000000 .4byte 0x7a - 2651 0af6 32 .uleb128 0x32 - 2652 0af7 85000000 .4byte 0x85 - 2653 0afb 32 .uleb128 0x32 - 2654 0afc 44030000 .4byte 0x344 - 2655 0b00 32 .uleb128 0x32 - 2656 0b01 85000000 .4byte 0x85 - 2657 0b05 00 .byte 0 - 2658 0b06 31 .uleb128 0x31 - 2659 0b07 01 .byte 0x1 - 2660 0b08 DC000000 .4byte .LASF82 - 2661 0b0c 01 .byte 0x1 - 2662 0b0d 20010000 .4byte 0x120 - 2663 0b11 01 .byte 0x1 - 2664 0b12 01 .byte 0x1 - 2665 0b13 270B0000 .4byte 0xb27 - 2666 0b17 32 .uleb128 0x32 - 2667 0b18 20010000 .4byte 0x120 - 2668 0b1c 32 .uleb128 0x32 - 2669 0b1d 22010000 .4byte 0x122 - 2670 0b21 32 .uleb128 0x32 - 2671 0b22 0E010000 .4byte 0x10e - 2672 0b26 00 .byte 0 - 2673 0b27 34 .uleb128 0x34 - 2674 0b28 01 .byte 0x1 - 2675 0b29 C9020000 .4byte .LASF83 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 78 - - - 2676 0b2d 06 .byte 0x6 - 2677 0b2e 4E .byte 0x4e - 2678 0b2f 01 .byte 0x1 - 2679 0b30 01 .byte 0x1 - 2680 0b31 34 .uleb128 0x34 - 2681 0b32 01 .byte 0x1 - 2682 0b33 35000000 .4byte .LASF84 - 2683 0b37 07 .byte 0x7 - 2684 0b38 7C .byte 0x7c - 2685 0b39 01 .byte 0x1 - 2686 0b3a 01 .byte 0x1 - 2687 0b3b 33 .uleb128 0x33 - 2688 0b3c 01 .byte 0x1 - 2689 0b3d C5000000 .4byte .LASF86 - 2690 0b41 08 .byte 0x8 - 2691 0b42 E6 .byte 0xe6 - 2692 0b43 01 .byte 0x1 - 2693 0b44 B0000000 .4byte 0xb0 - 2694 0b48 01 .byte 0x1 - 2695 0b49 620B0000 .4byte 0xb62 - 2696 0b4d 32 .uleb128 0x32 - 2697 0b4e C5030000 .4byte 0x3c5 - 2698 0b52 32 .uleb128 0x32 - 2699 0b53 85000000 .4byte 0x85 - 2700 0b57 32 .uleb128 0x32 - 2701 0b58 620B0000 .4byte 0xb62 - 2702 0b5c 32 .uleb128 0x32 - 2703 0b5d 7A000000 .4byte 0x7a - 2704 0b61 00 .byte 0 - 2705 0b62 0B .uleb128 0xb - 2706 0b63 04 .byte 0x4 - 2707 0b64 85000000 .4byte 0x85 - 2708 0b68 34 .uleb128 0x34 - 2709 0b69 01 .byte 0x1 - 2710 0b6a 04040000 .4byte .LASF87 - 2711 0b6e 08 .byte 0x8 - 2712 0b6f E3 .byte 0xe3 - 2713 0b70 01 .byte 0x1 - 2714 0b71 01 .byte 0x1 - 2715 0b72 33 .uleb128 0x33 - 2716 0b73 01 .byte 0x1 - 2717 0b74 E7030000 .4byte .LASF88 - 2718 0b78 08 .byte 0x8 - 2719 0b79 E8 .byte 0xe8 - 2720 0b7a 01 .byte 0x1 - 2721 0b7b B0000000 .4byte 0xb0 - 2722 0b7f 01 .byte 0x1 - 2723 0b80 990B0000 .4byte 0xb99 - 2724 0b84 32 .uleb128 0x32 - 2725 0b85 C5030000 .4byte 0x3c5 - 2726 0b89 32 .uleb128 0x32 - 2727 0b8a 85000000 .4byte 0x85 - 2728 0b8e 32 .uleb128 0x32 - 2729 0b8f 620B0000 .4byte 0xb62 - 2730 0b93 32 .uleb128 0x32 - 2731 0b94 7A000000 .4byte 0x7a - 2732 0b98 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 79 - - - 2733 0b99 35 .uleb128 0x35 - 2734 0b9a 01 .byte 0x1 - 2735 0b9b 4A010000 .4byte .LASF96 - 2736 0b9f 06 .byte 0x6 - 2737 0ba0 40 .byte 0x40 - 2738 0ba1 01 .byte 0x1 - 2739 0ba2 B0000000 .4byte 0xb0 - 2740 0ba6 01 .byte 0x1 - 2741 0ba7 36 .uleb128 0x36 - 2742 0ba8 01 .byte 0x1 - 2743 0ba9 D8020000 .4byte .LASF89 - 2744 0bad 07 .byte 0x7 - 2745 0bae 80 .byte 0x80 - 2746 0baf 01 .byte 0x1 - 2747 0bb0 01 .byte 0x1 - 2748 0bb1 BB0B0000 .4byte 0xbbb - 2749 0bb5 32 .uleb128 0x32 - 2750 0bb6 7A000000 .4byte 0x7a - 2751 0bba 00 .byte 0 - 2752 0bbb 33 .uleb128 0x33 - 2753 0bbc 01 .byte 0x1 - 2754 0bbd 59040000 .4byte .LASF90 - 2755 0bc1 06 .byte 0x6 - 2756 0bc2 41 .byte 0x41 - 2757 0bc3 01 .byte 0x1 - 2758 0bc4 B0000000 .4byte 0xb0 - 2759 0bc8 01 .byte 0x1 - 2760 0bc9 D30B0000 .4byte 0xbd3 - 2761 0bcd 32 .uleb128 0x32 - 2762 0bce C5030000 .4byte 0x3c5 - 2763 0bd2 00 .byte 0 - 2764 0bd3 37 .uleb128 0x37 - 2765 0bd4 01 .byte 0x1 - 2766 0bd5 7E040000 .4byte .LASF91 - 2767 0bd9 06 .byte 0x6 - 2768 0bda 44 .byte 0x44 - 2769 0bdb 01 .byte 0x1 - 2770 0bdc B0000000 .4byte 0xb0 - 2771 0be0 01 .byte 0x1 - 2772 0be1 32 .uleb128 0x32 - 2773 0be2 7A000000 .4byte 0x7a - 2774 0be6 32 .uleb128 0x32 - 2775 0be7 85000000 .4byte 0x85 - 2776 0beb 32 .uleb128 0x32 - 2777 0bec 44030000 .4byte 0x344 - 2778 0bf0 00 .byte 0 - 2779 0bf1 00 .byte 0 - 2780 .section .debug_abbrev,"",%progbits - 2781 .Ldebug_abbrev0: - 2782 0000 01 .uleb128 0x1 - 2783 0001 11 .uleb128 0x11 - 2784 0002 01 .byte 0x1 - 2785 0003 25 .uleb128 0x25 - 2786 0004 0E .uleb128 0xe - 2787 0005 13 .uleb128 0x13 - 2788 0006 0B .uleb128 0xb - 2789 0007 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 80 - - - 2790 0008 0E .uleb128 0xe - 2791 0009 1B .uleb128 0x1b - 2792 000a 0E .uleb128 0xe - 2793 000b 55 .uleb128 0x55 - 2794 000c 06 .uleb128 0x6 - 2795 000d 11 .uleb128 0x11 - 2796 000e 01 .uleb128 0x1 - 2797 000f 52 .uleb128 0x52 - 2798 0010 01 .uleb128 0x1 - 2799 0011 10 .uleb128 0x10 - 2800 0012 06 .uleb128 0x6 - 2801 0013 00 .byte 0 - 2802 0014 00 .byte 0 - 2803 0015 02 .uleb128 0x2 - 2804 0016 24 .uleb128 0x24 - 2805 0017 00 .byte 0 - 2806 0018 0B .uleb128 0xb - 2807 0019 0B .uleb128 0xb - 2808 001a 3E .uleb128 0x3e - 2809 001b 0B .uleb128 0xb - 2810 001c 03 .uleb128 0x3 - 2811 001d 0E .uleb128 0xe - 2812 001e 00 .byte 0 - 2813 001f 00 .byte 0 - 2814 0020 03 .uleb128 0x3 - 2815 0021 16 .uleb128 0x16 - 2816 0022 00 .byte 0 - 2817 0023 03 .uleb128 0x3 - 2818 0024 0E .uleb128 0xe - 2819 0025 3A .uleb128 0x3a - 2820 0026 0B .uleb128 0xb - 2821 0027 3B .uleb128 0x3b - 2822 0028 0B .uleb128 0xb - 2823 0029 49 .uleb128 0x49 - 2824 002a 13 .uleb128 0x13 - 2825 002b 00 .byte 0 - 2826 002c 00 .byte 0 - 2827 002d 04 .uleb128 0x4 - 2828 002e 24 .uleb128 0x24 - 2829 002f 00 .byte 0 - 2830 0030 0B .uleb128 0xb - 2831 0031 0B .uleb128 0xb - 2832 0032 3E .uleb128 0x3e - 2833 0033 0B .uleb128 0xb - 2834 0034 03 .uleb128 0x3 - 2835 0035 08 .uleb128 0x8 - 2836 0036 00 .byte 0 - 2837 0037 00 .byte 0 - 2838 0038 05 .uleb128 0x5 - 2839 0039 35 .uleb128 0x35 - 2840 003a 00 .byte 0 - 2841 003b 49 .uleb128 0x49 - 2842 003c 13 .uleb128 0x13 - 2843 003d 00 .byte 0 - 2844 003e 00 .byte 0 - 2845 003f 06 .uleb128 0x6 - 2846 0040 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 81 - - - 2847 0041 01 .byte 0x1 - 2848 0042 0B .uleb128 0xb - 2849 0043 0B .uleb128 0xb - 2850 0044 3A .uleb128 0x3a - 2851 0045 0B .uleb128 0xb - 2852 0046 3B .uleb128 0x3b - 2853 0047 0B .uleb128 0xb - 2854 0048 01 .uleb128 0x1 - 2855 0049 13 .uleb128 0x13 - 2856 004a 00 .byte 0 - 2857 004b 00 .byte 0 - 2858 004c 07 .uleb128 0x7 - 2859 004d 0D .uleb128 0xd - 2860 004e 00 .byte 0 - 2861 004f 03 .uleb128 0x3 - 2862 0050 0E .uleb128 0xe - 2863 0051 3A .uleb128 0x3a - 2864 0052 0B .uleb128 0xb - 2865 0053 3B .uleb128 0x3b - 2866 0054 0B .uleb128 0xb - 2867 0055 49 .uleb128 0x49 - 2868 0056 13 .uleb128 0x13 - 2869 0057 38 .uleb128 0x38 - 2870 0058 0A .uleb128 0xa - 2871 0059 00 .byte 0 - 2872 005a 00 .byte 0 - 2873 005b 08 .uleb128 0x8 - 2874 005c 01 .uleb128 0x1 - 2875 005d 01 .byte 0x1 - 2876 005e 49 .uleb128 0x49 - 2877 005f 13 .uleb128 0x13 - 2878 0060 01 .uleb128 0x1 - 2879 0061 13 .uleb128 0x13 - 2880 0062 00 .byte 0 - 2881 0063 00 .byte 0 - 2882 0064 09 .uleb128 0x9 - 2883 0065 21 .uleb128 0x21 - 2884 0066 00 .byte 0 - 2885 0067 49 .uleb128 0x49 - 2886 0068 13 .uleb128 0x13 - 2887 0069 2F .uleb128 0x2f - 2888 006a 0B .uleb128 0xb - 2889 006b 00 .byte 0 - 2890 006c 00 .byte 0 - 2891 006d 0A .uleb128 0xa - 2892 006e 0F .uleb128 0xf - 2893 006f 00 .byte 0 - 2894 0070 0B .uleb128 0xb - 2895 0071 0B .uleb128 0xb - 2896 0072 00 .byte 0 - 2897 0073 00 .byte 0 - 2898 0074 0B .uleb128 0xb - 2899 0075 0F .uleb128 0xf - 2900 0076 00 .byte 0 - 2901 0077 0B .uleb128 0xb - 2902 0078 0B .uleb128 0xb - 2903 0079 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 82 - - - 2904 007a 13 .uleb128 0x13 - 2905 007b 00 .byte 0 - 2906 007c 00 .byte 0 - 2907 007d 0C .uleb128 0xc - 2908 007e 26 .uleb128 0x26 - 2909 007f 00 .byte 0 - 2910 0080 00 .byte 0 - 2911 0081 00 .byte 0 - 2912 0082 0D .uleb128 0xd - 2913 0083 2E .uleb128 0x2e - 2914 0084 01 .byte 0x1 - 2915 0085 03 .uleb128 0x3 - 2916 0086 0E .uleb128 0xe - 2917 0087 3A .uleb128 0x3a - 2918 0088 0B .uleb128 0xb - 2919 0089 3B .uleb128 0x3b - 2920 008a 0B .uleb128 0xb - 2921 008b 27 .uleb128 0x27 - 2922 008c 0C .uleb128 0xc - 2923 008d 49 .uleb128 0x49 - 2924 008e 13 .uleb128 0x13 - 2925 008f 20 .uleb128 0x20 - 2926 0090 0B .uleb128 0xb - 2927 0091 01 .uleb128 0x1 - 2928 0092 13 .uleb128 0x13 - 2929 0093 00 .byte 0 - 2930 0094 00 .byte 0 - 2931 0095 0E .uleb128 0xe - 2932 0096 05 .uleb128 0x5 - 2933 0097 00 .byte 0 - 2934 0098 03 .uleb128 0x3 - 2935 0099 0E .uleb128 0xe - 2936 009a 3A .uleb128 0x3a - 2937 009b 0B .uleb128 0xb - 2938 009c 3B .uleb128 0x3b - 2939 009d 0B .uleb128 0xb - 2940 009e 49 .uleb128 0x49 - 2941 009f 13 .uleb128 0x13 - 2942 00a0 00 .byte 0 - 2943 00a1 00 .byte 0 - 2944 00a2 0F .uleb128 0xf - 2945 00a3 34 .uleb128 0x34 - 2946 00a4 00 .byte 0 - 2947 00a5 03 .uleb128 0x3 - 2948 00a6 08 .uleb128 0x8 - 2949 00a7 3A .uleb128 0x3a - 2950 00a8 0B .uleb128 0xb - 2951 00a9 3B .uleb128 0x3b - 2952 00aa 0B .uleb128 0xb - 2953 00ab 49 .uleb128 0x49 - 2954 00ac 13 .uleb128 0x13 - 2955 00ad 00 .byte 0 - 2956 00ae 00 .byte 0 - 2957 00af 10 .uleb128 0x10 - 2958 00b0 2E .uleb128 0x2e - 2959 00b1 01 .byte 0x1 - 2960 00b2 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 83 - - - 2961 00b3 0E .uleb128 0xe - 2962 00b4 3A .uleb128 0x3a - 2963 00b5 0B .uleb128 0xb - 2964 00b6 3B .uleb128 0x3b - 2965 00b7 05 .uleb128 0x5 - 2966 00b8 27 .uleb128 0x27 - 2967 00b9 0C .uleb128 0xc - 2968 00ba 49 .uleb128 0x49 - 2969 00bb 13 .uleb128 0x13 - 2970 00bc 20 .uleb128 0x20 - 2971 00bd 0B .uleb128 0xb - 2972 00be 01 .uleb128 0x1 - 2973 00bf 13 .uleb128 0x13 - 2974 00c0 00 .byte 0 - 2975 00c1 00 .byte 0 - 2976 00c2 11 .uleb128 0x11 - 2977 00c3 05 .uleb128 0x5 - 2978 00c4 00 .byte 0 - 2979 00c5 03 .uleb128 0x3 - 2980 00c6 0E .uleb128 0xe - 2981 00c7 3A .uleb128 0x3a - 2982 00c8 0B .uleb128 0xb - 2983 00c9 3B .uleb128 0x3b - 2984 00ca 05 .uleb128 0x5 - 2985 00cb 49 .uleb128 0x49 - 2986 00cc 13 .uleb128 0x13 - 2987 00cd 00 .byte 0 - 2988 00ce 00 .byte 0 - 2989 00cf 12 .uleb128 0x12 - 2990 00d0 34 .uleb128 0x34 - 2991 00d1 00 .byte 0 - 2992 00d2 03 .uleb128 0x3 - 2993 00d3 0E .uleb128 0xe - 2994 00d4 3A .uleb128 0x3a - 2995 00d5 0B .uleb128 0xb - 2996 00d6 3B .uleb128 0x3b - 2997 00d7 05 .uleb128 0x5 - 2998 00d8 49 .uleb128 0x49 - 2999 00d9 13 .uleb128 0x13 - 3000 00da 00 .byte 0 - 3001 00db 00 .byte 0 - 3002 00dc 13 .uleb128 0x13 - 3003 00dd 34 .uleb128 0x34 - 3004 00de 00 .byte 0 - 3005 00df 03 .uleb128 0x3 - 3006 00e0 08 .uleb128 0x8 - 3007 00e1 3A .uleb128 0x3a - 3008 00e2 0B .uleb128 0xb - 3009 00e3 3B .uleb128 0x3b - 3010 00e4 05 .uleb128 0x5 - 3011 00e5 49 .uleb128 0x49 - 3012 00e6 13 .uleb128 0x13 - 3013 00e7 00 .byte 0 - 3014 00e8 00 .byte 0 - 3015 00e9 14 .uleb128 0x14 - 3016 00ea 0B .uleb128 0xb - 3017 00eb 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 84 - - - 3018 00ec 00 .byte 0 - 3019 00ed 00 .byte 0 - 3020 00ee 15 .uleb128 0x15 - 3021 00ef 2E .uleb128 0x2e - 3022 00f0 01 .byte 0x1 - 3023 00f1 03 .uleb128 0x3 - 3024 00f2 0E .uleb128 0xe - 3025 00f3 3A .uleb128 0x3a - 3026 00f4 0B .uleb128 0xb - 3027 00f5 3B .uleb128 0x3b - 3028 00f6 05 .uleb128 0x5 - 3029 00f7 27 .uleb128 0x27 - 3030 00f8 0C .uleb128 0xc - 3031 00f9 11 .uleb128 0x11 - 3032 00fa 01 .uleb128 0x1 - 3033 00fb 12 .uleb128 0x12 - 3034 00fc 01 .uleb128 0x1 - 3035 00fd 40 .uleb128 0x40 - 3036 00fe 0A .uleb128 0xa - 3037 00ff 9742 .uleb128 0x2117 - 3038 0101 0C .uleb128 0xc - 3039 0102 01 .uleb128 0x1 - 3040 0103 13 .uleb128 0x13 - 3041 0104 00 .byte 0 - 3042 0105 00 .byte 0 - 3043 0106 16 .uleb128 0x16 - 3044 0107 05 .uleb128 0x5 - 3045 0108 00 .byte 0 - 3046 0109 03 .uleb128 0x3 - 3047 010a 0E .uleb128 0xe - 3048 010b 3A .uleb128 0x3a - 3049 010c 0B .uleb128 0xb - 3050 010d 3B .uleb128 0x3b - 3051 010e 05 .uleb128 0x5 - 3052 010f 49 .uleb128 0x49 - 3053 0110 13 .uleb128 0x13 - 3054 0111 02 .uleb128 0x2 - 3055 0112 0A .uleb128 0xa - 3056 0113 00 .byte 0 - 3057 0114 00 .byte 0 - 3058 0115 17 .uleb128 0x17 - 3059 0116 2E .uleb128 0x2e - 3060 0117 01 .byte 0x1 - 3061 0118 31 .uleb128 0x31 - 3062 0119 13 .uleb128 0x13 - 3063 011a 11 .uleb128 0x11 - 3064 011b 01 .uleb128 0x1 - 3065 011c 12 .uleb128 0x12 - 3066 011d 01 .uleb128 0x1 - 3067 011e 40 .uleb128 0x40 - 3068 011f 06 .uleb128 0x6 - 3069 0120 9742 .uleb128 0x2117 - 3070 0122 0C .uleb128 0xc - 3071 0123 01 .uleb128 0x1 - 3072 0124 13 .uleb128 0x13 - 3073 0125 00 .byte 0 - 3074 0126 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 85 - - - 3075 0127 18 .uleb128 0x18 - 3076 0128 05 .uleb128 0x5 - 3077 0129 00 .byte 0 - 3078 012a 31 .uleb128 0x31 - 3079 012b 13 .uleb128 0x13 - 3080 012c 02 .uleb128 0x2 - 3081 012d 06 .uleb128 0x6 - 3082 012e 00 .byte 0 - 3083 012f 00 .byte 0 - 3084 0130 19 .uleb128 0x19 - 3085 0131 34 .uleb128 0x34 - 3086 0132 00 .byte 0 - 3087 0133 31 .uleb128 0x31 - 3088 0134 13 .uleb128 0x13 - 3089 0135 02 .uleb128 0x2 - 3090 0136 06 .uleb128 0x6 - 3091 0137 00 .byte 0 - 3092 0138 00 .byte 0 - 3093 0139 1A .uleb128 0x1a - 3094 013a 05 .uleb128 0x5 - 3095 013b 00 .byte 0 - 3096 013c 31 .uleb128 0x31 - 3097 013d 13 .uleb128 0x13 - 3098 013e 1C .uleb128 0x1c - 3099 013f 0B .uleb128 0xb - 3100 0140 00 .byte 0 - 3101 0141 00 .byte 0 - 3102 0142 1B .uleb128 0x1b - 3103 0143 0B .uleb128 0xb - 3104 0144 01 .byte 0x1 - 3105 0145 11 .uleb128 0x11 - 3106 0146 01 .uleb128 0x1 - 3107 0147 12 .uleb128 0x12 - 3108 0148 01 .uleb128 0x1 - 3109 0149 01 .uleb128 0x1 - 3110 014a 13 .uleb128 0x13 - 3111 014b 00 .byte 0 - 3112 014c 00 .byte 0 - 3113 014d 1C .uleb128 0x1c - 3114 014e 898201 .uleb128 0x4109 - 3115 0151 01 .byte 0x1 - 3116 0152 11 .uleb128 0x11 - 3117 0153 01 .uleb128 0x1 - 3118 0154 31 .uleb128 0x31 - 3119 0155 13 .uleb128 0x13 - 3120 0156 01 .uleb128 0x1 - 3121 0157 13 .uleb128 0x13 - 3122 0158 00 .byte 0 - 3123 0159 00 .byte 0 - 3124 015a 1D .uleb128 0x1d - 3125 015b 8A8201 .uleb128 0x410a - 3126 015e 00 .byte 0 - 3127 015f 02 .uleb128 0x2 - 3128 0160 0A .uleb128 0xa - 3129 0161 9142 .uleb128 0x2111 - 3130 0163 0A .uleb128 0xa - 3131 0164 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 86 - - - 3132 0165 00 .byte 0 - 3133 0166 1E .uleb128 0x1e - 3134 0167 898201 .uleb128 0x4109 - 3135 016a 01 .byte 0x1 - 3136 016b 11 .uleb128 0x11 - 3137 016c 01 .uleb128 0x1 - 3138 016d 31 .uleb128 0x31 - 3139 016e 13 .uleb128 0x13 - 3140 016f 00 .byte 0 - 3141 0170 00 .byte 0 - 3142 0171 1F .uleb128 0x1f - 3143 0172 26 .uleb128 0x26 - 3144 0173 00 .byte 0 - 3145 0174 49 .uleb128 0x49 - 3146 0175 13 .uleb128 0x13 - 3147 0176 00 .byte 0 - 3148 0177 00 .byte 0 - 3149 0178 20 .uleb128 0x20 - 3150 0179 2E .uleb128 0x2e - 3151 017a 01 .byte 0x1 - 3152 017b 03 .uleb128 0x3 - 3153 017c 0E .uleb128 0xe - 3154 017d 3A .uleb128 0x3a - 3155 017e 0B .uleb128 0xb - 3156 017f 3B .uleb128 0x3b - 3157 0180 05 .uleb128 0x5 - 3158 0181 27 .uleb128 0x27 - 3159 0182 0C .uleb128 0xc - 3160 0183 11 .uleb128 0x11 - 3161 0184 01 .uleb128 0x1 - 3162 0185 12 .uleb128 0x12 - 3163 0186 01 .uleb128 0x1 - 3164 0187 40 .uleb128 0x40 - 3165 0188 06 .uleb128 0x6 - 3166 0189 9742 .uleb128 0x2117 - 3167 018b 0C .uleb128 0xc - 3168 018c 01 .uleb128 0x1 - 3169 018d 13 .uleb128 0x13 - 3170 018e 00 .byte 0 - 3171 018f 00 .byte 0 - 3172 0190 21 .uleb128 0x21 - 3173 0191 05 .uleb128 0x5 - 3174 0192 00 .byte 0 - 3175 0193 03 .uleb128 0x3 - 3176 0194 0E .uleb128 0xe - 3177 0195 3A .uleb128 0x3a - 3178 0196 0B .uleb128 0xb - 3179 0197 3B .uleb128 0x3b - 3180 0198 05 .uleb128 0x5 - 3181 0199 49 .uleb128 0x49 - 3182 019a 13 .uleb128 0x13 - 3183 019b 02 .uleb128 0x2 - 3184 019c 06 .uleb128 0x6 - 3185 019d 00 .byte 0 - 3186 019e 00 .byte 0 - 3187 019f 22 .uleb128 0x22 - 3188 01a0 34 .uleb128 0x34 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 87 - - - 3189 01a1 00 .byte 0 - 3190 01a2 03 .uleb128 0x3 - 3191 01a3 0E .uleb128 0xe - 3192 01a4 3A .uleb128 0x3a - 3193 01a5 0B .uleb128 0xb - 3194 01a6 3B .uleb128 0x3b - 3195 01a7 05 .uleb128 0x5 - 3196 01a8 49 .uleb128 0x49 - 3197 01a9 13 .uleb128 0x13 - 3198 01aa 02 .uleb128 0x2 - 3199 01ab 0A .uleb128 0xa - 3200 01ac 00 .byte 0 - 3201 01ad 00 .byte 0 - 3202 01ae 23 .uleb128 0x23 - 3203 01af 34 .uleb128 0x34 - 3204 01b0 00 .byte 0 - 3205 01b1 03 .uleb128 0x3 - 3206 01b2 0E .uleb128 0xe - 3207 01b3 3A .uleb128 0x3a - 3208 01b4 0B .uleb128 0xb - 3209 01b5 3B .uleb128 0x3b - 3210 01b6 05 .uleb128 0x5 - 3211 01b7 49 .uleb128 0x49 - 3212 01b8 13 .uleb128 0x13 - 3213 01b9 02 .uleb128 0x2 - 3214 01ba 06 .uleb128 0x6 - 3215 01bb 00 .byte 0 - 3216 01bc 00 .byte 0 - 3217 01bd 24 .uleb128 0x24 - 3218 01be 1D .uleb128 0x1d - 3219 01bf 01 .byte 0x1 - 3220 01c0 31 .uleb128 0x31 - 3221 01c1 13 .uleb128 0x13 - 3222 01c2 11 .uleb128 0x11 - 3223 01c3 01 .uleb128 0x1 - 3224 01c4 12 .uleb128 0x12 - 3225 01c5 01 .uleb128 0x1 - 3226 01c6 58 .uleb128 0x58 - 3227 01c7 0B .uleb128 0xb - 3228 01c8 59 .uleb128 0x59 - 3229 01c9 05 .uleb128 0x5 - 3230 01ca 01 .uleb128 0x1 - 3231 01cb 13 .uleb128 0x13 - 3232 01cc 00 .byte 0 - 3233 01cd 00 .byte 0 - 3234 01ce 25 .uleb128 0x25 - 3235 01cf 0B .uleb128 0xb - 3236 01d0 01 .byte 0x1 - 3237 01d1 11 .uleb128 0x11 - 3238 01d2 01 .uleb128 0x1 - 3239 01d3 12 .uleb128 0x12 - 3240 01d4 01 .uleb128 0x1 - 3241 01d5 00 .byte 0 - 3242 01d6 00 .byte 0 - 3243 01d7 26 .uleb128 0x26 - 3244 01d8 0B .uleb128 0xb - 3245 01d9 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 88 - - - 3246 01da 55 .uleb128 0x55 - 3247 01db 06 .uleb128 0x6 - 3248 01dc 01 .uleb128 0x1 - 3249 01dd 13 .uleb128 0x13 - 3250 01de 00 .byte 0 - 3251 01df 00 .byte 0 - 3252 01e0 27 .uleb128 0x27 - 3253 01e1 898201 .uleb128 0x4109 - 3254 01e4 00 .byte 0 - 3255 01e5 11 .uleb128 0x11 - 3256 01e6 01 .uleb128 0x1 - 3257 01e7 31 .uleb128 0x31 - 3258 01e8 13 .uleb128 0x13 - 3259 01e9 00 .byte 0 - 3260 01ea 00 .byte 0 - 3261 01eb 28 .uleb128 0x28 - 3262 01ec 05 .uleb128 0x5 - 3263 01ed 00 .byte 0 - 3264 01ee 31 .uleb128 0x31 - 3265 01ef 13 .uleb128 0x13 - 3266 01f0 02 .uleb128 0x2 - 3267 01f1 0A .uleb128 0xa - 3268 01f2 00 .byte 0 - 3269 01f3 00 .byte 0 - 3270 01f4 29 .uleb128 0x29 - 3271 01f5 34 .uleb128 0x34 - 3272 01f6 00 .byte 0 - 3273 01f7 31 .uleb128 0x31 - 3274 01f8 13 .uleb128 0x13 - 3275 01f9 02 .uleb128 0x2 - 3276 01fa 0A .uleb128 0xa - 3277 01fb 00 .byte 0 - 3278 01fc 00 .byte 0 - 3279 01fd 2A .uleb128 0x2a - 3280 01fe 21 .uleb128 0x21 - 3281 01ff 00 .byte 0 - 3282 0200 49 .uleb128 0x49 - 3283 0201 13 .uleb128 0x13 - 3284 0202 2F .uleb128 0x2f - 3285 0203 05 .uleb128 0x5 - 3286 0204 00 .byte 0 - 3287 0205 00 .byte 0 - 3288 0206 2B .uleb128 0x2b - 3289 0207 2E .uleb128 0x2e - 3290 0208 00 .byte 0 - 3291 0209 03 .uleb128 0x3 - 3292 020a 0E .uleb128 0xe - 3293 020b 3A .uleb128 0x3a - 3294 020c 0B .uleb128 0xb - 3295 020d 3B .uleb128 0x3b - 3296 020e 05 .uleb128 0x5 - 3297 020f 27 .uleb128 0x27 - 3298 0210 0C .uleb128 0xc - 3299 0211 20 .uleb128 0x20 - 3300 0212 0B .uleb128 0xb - 3301 0213 00 .byte 0 - 3302 0214 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 89 - - - 3303 0215 2C .uleb128 0x2c - 3304 0216 2E .uleb128 0x2e - 3305 0217 01 .byte 0x1 - 3306 0218 3F .uleb128 0x3f - 3307 0219 0C .uleb128 0xc - 3308 021a 03 .uleb128 0x3 - 3309 021b 0E .uleb128 0xe - 3310 021c 3A .uleb128 0x3a - 3311 021d 0B .uleb128 0xb - 3312 021e 3B .uleb128 0x3b - 3313 021f 05 .uleb128 0x5 - 3314 0220 27 .uleb128 0x27 - 3315 0221 0C .uleb128 0xc - 3316 0222 11 .uleb128 0x11 - 3317 0223 01 .uleb128 0x1 - 3318 0224 12 .uleb128 0x12 - 3319 0225 01 .uleb128 0x1 - 3320 0226 40 .uleb128 0x40 - 3321 0227 06 .uleb128 0x6 - 3322 0228 9742 .uleb128 0x2117 - 3323 022a 0C .uleb128 0xc - 3324 022b 01 .uleb128 0x1 - 3325 022c 13 .uleb128 0x13 - 3326 022d 00 .byte 0 - 3327 022e 00 .byte 0 - 3328 022f 2D .uleb128 0x2d - 3329 0230 898201 .uleb128 0x4109 - 3330 0233 00 .byte 0 - 3331 0234 11 .uleb128 0x11 - 3332 0235 01 .uleb128 0x1 - 3333 0236 9542 .uleb128 0x2115 - 3334 0238 0C .uleb128 0xc - 3335 0239 31 .uleb128 0x31 - 3336 023a 13 .uleb128 0x13 - 3337 023b 00 .byte 0 - 3338 023c 00 .byte 0 - 3339 023d 2E .uleb128 0x2e - 3340 023e 34 .uleb128 0x34 - 3341 023f 00 .byte 0 - 3342 0240 03 .uleb128 0x3 - 3343 0241 08 .uleb128 0x8 - 3344 0242 3A .uleb128 0x3a - 3345 0243 0B .uleb128 0xb - 3346 0244 3B .uleb128 0x3b - 3347 0245 05 .uleb128 0x5 - 3348 0246 49 .uleb128 0x49 - 3349 0247 13 .uleb128 0x13 - 3350 0248 02 .uleb128 0x2 - 3351 0249 06 .uleb128 0x6 - 3352 024a 00 .byte 0 - 3353 024b 00 .byte 0 - 3354 024c 2F .uleb128 0x2f - 3355 024d 34 .uleb128 0x34 - 3356 024e 00 .byte 0 - 3357 024f 03 .uleb128 0x3 - 3358 0250 0E .uleb128 0xe - 3359 0251 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 90 - - - 3360 0252 0B .uleb128 0xb - 3361 0253 3B .uleb128 0x3b - 3362 0254 0B .uleb128 0xb - 3363 0255 49 .uleb128 0x49 - 3364 0256 13 .uleb128 0x13 - 3365 0257 3F .uleb128 0x3f - 3366 0258 0C .uleb128 0xc - 3367 0259 02 .uleb128 0x2 - 3368 025a 0A .uleb128 0xa - 3369 025b 00 .byte 0 - 3370 025c 00 .byte 0 - 3371 025d 30 .uleb128 0x30 - 3372 025e 34 .uleb128 0x34 - 3373 025f 00 .byte 0 - 3374 0260 03 .uleb128 0x3 - 3375 0261 0E .uleb128 0xe - 3376 0262 3A .uleb128 0x3a - 3377 0263 0B .uleb128 0xb - 3378 0264 3B .uleb128 0x3b - 3379 0265 05 .uleb128 0x5 - 3380 0266 49 .uleb128 0x49 - 3381 0267 13 .uleb128 0x13 - 3382 0268 3F .uleb128 0x3f - 3383 0269 0C .uleb128 0xc - 3384 026a 3C .uleb128 0x3c - 3385 026b 0C .uleb128 0xc - 3386 026c 00 .byte 0 - 3387 026d 00 .byte 0 - 3388 026e 31 .uleb128 0x31 - 3389 026f 2E .uleb128 0x2e - 3390 0270 01 .byte 0x1 - 3391 0271 3F .uleb128 0x3f - 3392 0272 0C .uleb128 0xc - 3393 0273 03 .uleb128 0x3 - 3394 0274 0E .uleb128 0xe - 3395 0275 27 .uleb128 0x27 - 3396 0276 0C .uleb128 0xc - 3397 0277 49 .uleb128 0x49 - 3398 0278 13 .uleb128 0x13 - 3399 0279 34 .uleb128 0x34 - 3400 027a 0C .uleb128 0xc - 3401 027b 3C .uleb128 0x3c - 3402 027c 0C .uleb128 0xc - 3403 027d 01 .uleb128 0x1 - 3404 027e 13 .uleb128 0x13 - 3405 027f 00 .byte 0 - 3406 0280 00 .byte 0 - 3407 0281 32 .uleb128 0x32 - 3408 0282 05 .uleb128 0x5 - 3409 0283 00 .byte 0 - 3410 0284 49 .uleb128 0x49 - 3411 0285 13 .uleb128 0x13 - 3412 0286 00 .byte 0 - 3413 0287 00 .byte 0 - 3414 0288 33 .uleb128 0x33 - 3415 0289 2E .uleb128 0x2e - 3416 028a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 91 - - - 3417 028b 3F .uleb128 0x3f - 3418 028c 0C .uleb128 0xc - 3419 028d 03 .uleb128 0x3 - 3420 028e 0E .uleb128 0xe - 3421 028f 3A .uleb128 0x3a - 3422 0290 0B .uleb128 0xb - 3423 0291 3B .uleb128 0x3b - 3424 0292 0B .uleb128 0xb - 3425 0293 27 .uleb128 0x27 - 3426 0294 0C .uleb128 0xc - 3427 0295 49 .uleb128 0x49 - 3428 0296 13 .uleb128 0x13 - 3429 0297 3C .uleb128 0x3c - 3430 0298 0C .uleb128 0xc - 3431 0299 01 .uleb128 0x1 - 3432 029a 13 .uleb128 0x13 - 3433 029b 00 .byte 0 - 3434 029c 00 .byte 0 - 3435 029d 34 .uleb128 0x34 - 3436 029e 2E .uleb128 0x2e - 3437 029f 00 .byte 0 - 3438 02a0 3F .uleb128 0x3f - 3439 02a1 0C .uleb128 0xc - 3440 02a2 03 .uleb128 0x3 - 3441 02a3 0E .uleb128 0xe - 3442 02a4 3A .uleb128 0x3a - 3443 02a5 0B .uleb128 0xb - 3444 02a6 3B .uleb128 0x3b - 3445 02a7 0B .uleb128 0xb - 3446 02a8 27 .uleb128 0x27 - 3447 02a9 0C .uleb128 0xc - 3448 02aa 3C .uleb128 0x3c - 3449 02ab 0C .uleb128 0xc - 3450 02ac 00 .byte 0 - 3451 02ad 00 .byte 0 - 3452 02ae 35 .uleb128 0x35 - 3453 02af 2E .uleb128 0x2e - 3454 02b0 00 .byte 0 - 3455 02b1 3F .uleb128 0x3f - 3456 02b2 0C .uleb128 0xc - 3457 02b3 03 .uleb128 0x3 - 3458 02b4 0E .uleb128 0xe - 3459 02b5 3A .uleb128 0x3a - 3460 02b6 0B .uleb128 0xb - 3461 02b7 3B .uleb128 0x3b - 3462 02b8 0B .uleb128 0xb - 3463 02b9 27 .uleb128 0x27 - 3464 02ba 0C .uleb128 0xc - 3465 02bb 49 .uleb128 0x49 - 3466 02bc 13 .uleb128 0x13 - 3467 02bd 3C .uleb128 0x3c - 3468 02be 0C .uleb128 0xc - 3469 02bf 00 .byte 0 - 3470 02c0 00 .byte 0 - 3471 02c1 36 .uleb128 0x36 - 3472 02c2 2E .uleb128 0x2e - 3473 02c3 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 92 - - - 3474 02c4 3F .uleb128 0x3f - 3475 02c5 0C .uleb128 0xc - 3476 02c6 03 .uleb128 0x3 - 3477 02c7 0E .uleb128 0xe - 3478 02c8 3A .uleb128 0x3a - 3479 02c9 0B .uleb128 0xb - 3480 02ca 3B .uleb128 0x3b - 3481 02cb 0B .uleb128 0xb - 3482 02cc 27 .uleb128 0x27 - 3483 02cd 0C .uleb128 0xc - 3484 02ce 3C .uleb128 0x3c - 3485 02cf 0C .uleb128 0xc - 3486 02d0 01 .uleb128 0x1 - 3487 02d1 13 .uleb128 0x13 - 3488 02d2 00 .byte 0 - 3489 02d3 00 .byte 0 - 3490 02d4 37 .uleb128 0x37 - 3491 02d5 2E .uleb128 0x2e - 3492 02d6 01 .byte 0x1 - 3493 02d7 3F .uleb128 0x3f - 3494 02d8 0C .uleb128 0xc - 3495 02d9 03 .uleb128 0x3 - 3496 02da 0E .uleb128 0xe - 3497 02db 3A .uleb128 0x3a - 3498 02dc 0B .uleb128 0xb - 3499 02dd 3B .uleb128 0x3b - 3500 02de 0B .uleb128 0xb - 3501 02df 27 .uleb128 0x27 - 3502 02e0 0C .uleb128 0xc - 3503 02e1 49 .uleb128 0x49 - 3504 02e2 13 .uleb128 0x13 - 3505 02e3 3C .uleb128 0x3c - 3506 02e4 0C .uleb128 0xc - 3507 02e5 00 .byte 0 - 3508 02e6 00 .byte 0 - 3509 02e7 00 .byte 0 - 3510 .section .debug_loc,"",%progbits - 3511 .Ldebug_loc0: - 3512 .LLST0: - 3513 0000 00000000 .4byte .LFB69 - 3514 0004 04000000 .4byte .LCFI0 - 3515 0008 0200 .2byte 0x2 - 3516 000a 7D .byte 0x7d - 3517 000b 00 .sleb128 0 - 3518 000c 04000000 .4byte .LCFI0 - 3519 0010 8C000000 .4byte .LFE69 - 3520 0014 0200 .2byte 0x2 - 3521 0016 7D .byte 0x7d - 3522 0017 08 .sleb128 8 - 3523 0018 00000000 .4byte 0 - 3524 001c 00000000 .4byte 0 - 3525 .LLST1: - 3526 0020 00000000 .4byte .LVL1 - 3527 0024 18000000 .4byte .LVL2 - 3528 0028 0100 .2byte 0x1 - 3529 002a 50 .byte 0x50 - 3530 002b 18000000 .4byte .LVL2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 93 - - - 3531 002f 1A000000 .4byte .LVL3 - 3532 0033 0400 .2byte 0x4 - 3533 0035 F3 .byte 0xf3 - 3534 0036 01 .uleb128 0x1 - 3535 0037 50 .byte 0x50 - 3536 0038 9F .byte 0x9f - 3537 0039 1A000000 .4byte .LVL3 - 3538 003d 20000000 .4byte .LVL5 - 3539 0041 0100 .2byte 0x1 - 3540 0043 50 .byte 0x50 - 3541 0044 20000000 .4byte .LVL5 - 3542 0048 22000000 .4byte .LVL6 - 3543 004c 0400 .2byte 0x4 - 3544 004e F3 .byte 0xf3 - 3545 004f 01 .uleb128 0x1 - 3546 0050 50 .byte 0x50 - 3547 0051 9F .byte 0x9f - 3548 0052 22000000 .4byte .LVL6 - 3549 0056 24000000 .4byte .LVL7 - 3550 005a 0100 .2byte 0x1 - 3551 005c 50 .byte 0x50 - 3552 005d 24000000 .4byte .LVL7 - 3553 0061 26000000 .4byte .LVL8 - 3554 0065 0400 .2byte 0x4 - 3555 0067 F3 .byte 0xf3 - 3556 0068 01 .uleb128 0x1 - 3557 0069 50 .byte 0x50 - 3558 006a 9F .byte 0x9f - 3559 006b 26000000 .4byte .LVL8 - 3560 006f 28000000 .4byte .LVL9 - 3561 0073 0100 .2byte 0x1 - 3562 0075 50 .byte 0x50 - 3563 0076 28000000 .4byte .LVL9 - 3564 007a 2A000000 .4byte .LVL10 - 3565 007e 0400 .2byte 0x4 - 3566 0080 F3 .byte 0xf3 - 3567 0081 01 .uleb128 0x1 - 3568 0082 50 .byte 0x50 - 3569 0083 9F .byte 0x9f - 3570 0084 2A000000 .4byte .LVL10 - 3571 0088 2C000000 .4byte .LVL11 - 3572 008c 0100 .2byte 0x1 - 3573 008e 50 .byte 0x50 - 3574 008f 2C000000 .4byte .LVL11 - 3575 0093 50000000 .4byte .LVL17 - 3576 0097 0400 .2byte 0x4 - 3577 0099 F3 .byte 0xf3 - 3578 009a 01 .uleb128 0x1 - 3579 009b 50 .byte 0x50 - 3580 009c 9F .byte 0x9f - 3581 009d 50000000 .4byte .LVL17 - 3582 00a1 58000000 .4byte .LVL19 - 3583 00a5 0100 .2byte 0x1 - 3584 00a7 50 .byte 0x50 - 3585 00a8 58000000 .4byte .LVL19 - 3586 00ac 8C000000 .4byte .LFE69 - 3587 00b0 0400 .2byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 94 - - - 3588 00b2 F3 .byte 0xf3 - 3589 00b3 01 .uleb128 0x1 - 3590 00b4 50 .byte 0x50 - 3591 00b5 9F .byte 0x9f - 3592 00b6 00000000 .4byte 0 - 3593 00ba 00000000 .4byte 0 - 3594 .LLST2: - 3595 00be 1E000000 .4byte .LVL4 - 3596 00c2 22000000 .4byte .LVL6 - 3597 00c6 0600 .2byte 0x6 - 3598 00c8 0C .byte 0xc - 3599 00c9 D6FF0100 .4byte 0x1ffd6 - 3600 00cd 9F .byte 0x9f - 3601 00ce 22000000 .4byte .LVL6 - 3602 00d2 26000000 .4byte .LVL8 - 3603 00d6 0600 .2byte 0x6 - 3604 00d8 0C .byte 0xc - 3605 00d9 D4FF0100 .4byte 0x1ffd4 - 3606 00dd 9F .byte 0x9f - 3607 00de 2C000000 .4byte .LVL11 - 3608 00e2 30000000 .4byte .LVL13 - 3609 00e6 0100 .2byte 0x1 - 3610 00e8 50 .byte 0x50 - 3611 00e9 56000000 .4byte .LVL18 - 3612 00ed 5E000000 .4byte .LVL22 - 3613 00f1 0100 .2byte 0x1 - 3614 00f3 53 .byte 0x53 - 3615 00f4 00000000 .4byte 0 - 3616 00f8 00000000 .4byte 0 - 3617 .LLST3: - 3618 00fc 00000000 .4byte .LVL1 - 3619 0100 34000000 .4byte .LVL14 - 3620 0104 0200 .2byte 0x2 - 3621 0106 32 .byte 0x32 - 3622 0107 9F .byte 0x9f - 3623 0108 50000000 .4byte .LVL17 - 3624 010c 56000000 .4byte .LVL18 - 3625 0110 0200 .2byte 0x2 - 3626 0112 32 .byte 0x32 - 3627 0113 9F .byte 0x9f - 3628 0114 56000000 .4byte .LVL18 - 3629 0118 6C000000 .4byte .LVL25 - 3630 011c 0200 .2byte 0x2 - 3631 011e 34 .byte 0x34 - 3632 011f 9F .byte 0x9f - 3633 0120 00000000 .4byte 0 - 3634 0124 00000000 .4byte 0 - 3635 .LLST4: - 3636 0128 2E000000 .4byte .LVL12 - 3637 012c 34000000 .4byte .LVL14 - 3638 0130 0100 .2byte 0x1 - 3639 0132 51 .byte 0x51 - 3640 0133 34000000 .4byte .LVL14 - 3641 0137 50000000 .4byte .LVL17 - 3642 013b 0100 .2byte 0x1 - 3643 013d 50 .byte 0x50 - 3644 013e 58000000 .4byte .LVL19 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 95 - - - 3645 0142 5A000000 .4byte .LVL20 - 3646 0146 0100 .2byte 0x1 - 3647 0148 50 .byte 0x50 - 3648 0149 5A000000 .4byte .LVL20 - 3649 014d 5C000000 .4byte .LVL21 - 3650 0151 0B00 .2byte 0xb - 3651 0153 74 .byte 0x74 - 3652 0154 00 .sleb128 0 - 3653 0155 08 .byte 0x8 - 3654 0156 FF .byte 0xff - 3655 0157 1A .byte 0x1a - 3656 0158 38 .byte 0x38 - 3657 0159 24 .byte 0x24 - 3658 015a 70 .byte 0x70 - 3659 015b 00 .sleb128 0 - 3660 015c 21 .byte 0x21 - 3661 015d 9F .byte 0x9f - 3662 015e 5C000000 .4byte .LVL21 - 3663 0162 62000000 .4byte .LVL23 - 3664 0166 1300 .2byte 0x13 - 3665 0168 74 .byte 0x74 - 3666 0169 00 .sleb128 0 - 3667 016a 08 .byte 0x8 - 3668 016b FF .byte 0xff - 3669 016c 1A .byte 0x1a - 3670 016d 38 .byte 0x38 - 3671 016e 24 .byte 0x24 - 3672 016f 71 .byte 0x71 - 3673 0170 00 .sleb128 0 - 3674 0171 08 .byte 0x8 - 3675 0172 FF .byte 0xff - 3676 0173 1A .byte 0x1a - 3677 0174 40 .byte 0x40 - 3678 0175 24 .byte 0x24 - 3679 0176 21 .byte 0x21 - 3680 0177 70 .byte 0x70 - 3681 0178 00 .sleb128 0 - 3682 0179 21 .byte 0x21 - 3683 017a 9F .byte 0x9f - 3684 017b 6A000000 .4byte .LVL24 - 3685 017f 8C000000 .4byte .LFE69 - 3686 0183 0100 .2byte 0x1 - 3687 0185 50 .byte 0x50 - 3688 0186 00000000 .4byte 0 - 3689 018a 00000000 .4byte 0 - 3690 .LLST5: - 3691 018e 00000000 .4byte .LFB70 - 3692 0192 02000000 .4byte .LCFI1 - 3693 0196 0200 .2byte 0x2 - 3694 0198 7D .byte 0x7d - 3695 0199 00 .sleb128 0 - 3696 019a 02000000 .4byte .LCFI1 - 3697 019e 84000000 .4byte .LFE70 - 3698 01a2 0200 .2byte 0x2 - 3699 01a4 7D .byte 0x7d - 3700 01a5 10 .sleb128 16 - 3701 01a6 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 96 - - - 3702 01aa 00000000 .4byte 0 - 3703 .LLST6: - 3704 01ae 22000000 .4byte .LVL31 - 3705 01b2 24000000 .4byte .LVL32 - 3706 01b6 0100 .2byte 0x1 - 3707 01b8 51 .byte 0x51 - 3708 01b9 4A000000 .4byte .LVL39 - 3709 01bd 62000000 .4byte .LVL43 - 3710 01c1 0100 .2byte 0x1 - 3711 01c3 53 .byte 0x53 - 3712 01c4 62000000 .4byte .LVL43 - 3713 01c8 68000000 .4byte .LVL45 - 3714 01cc 0300 .2byte 0x3 - 3715 01ce 73 .byte 0x73 - 3716 01cf 7F .sleb128 -1 - 3717 01d0 9F .byte 0x9f - 3718 01d1 68000000 .4byte .LVL45 - 3719 01d5 84000000 .4byte .LFE70 - 3720 01d9 0100 .2byte 0x1 - 3721 01db 53 .byte 0x53 - 3722 01dc 00000000 .4byte 0 - 3723 01e0 00000000 .4byte 0 - 3724 .LLST7: - 3725 01e4 16000000 .4byte .LVL29 - 3726 01e8 50000000 .4byte .LVL40 - 3727 01ec 0100 .2byte 0x1 - 3728 01ee 56 .byte 0x56 - 3729 01ef 52000000 .4byte .LVL41 - 3730 01f3 56000000 .4byte .LVL42 - 3731 01f7 0100 .2byte 0x1 - 3732 01f9 56 .byte 0x56 - 3733 01fa 00000000 .4byte 0 - 3734 01fe 00000000 .4byte 0 - 3735 .LLST8: - 3736 0202 16000000 .4byte .LVL29 - 3737 0206 24000000 .4byte .LVL32 - 3738 020a 0200 .2byte 0x2 - 3739 020c 30 .byte 0x30 - 3740 020d 9F .byte 0x9f - 3741 020e 24000000 .4byte .LVL32 - 3742 0212 84000000 .4byte .LFE70 - 3743 0216 0100 .2byte 0x1 - 3744 0218 55 .byte 0x55 - 3745 0219 00000000 .4byte 0 - 3746 021d 00000000 .4byte 0 - 3747 .LLST9: - 3748 0221 16000000 .4byte .LVL29 - 3749 0225 24000000 .4byte .LVL32 - 3750 0229 0200 .2byte 0x2 - 3751 022b 30 .byte 0x30 - 3752 022c 9F .byte 0x9f - 3753 022d 24000000 .4byte .LVL32 - 3754 0231 32000000 .4byte .LVL34 - 3755 0235 0100 .2byte 0x1 - 3756 0237 54 .byte 0x54 - 3757 0238 3A000000 .4byte .LVL36 - 3758 023c 66000000 .4byte .LVL44 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 97 - - - 3759 0240 0100 .2byte 0x1 - 3760 0242 54 .byte 0x54 - 3761 0243 66000000 .4byte .LVL44 - 3762 0247 68000000 .4byte .LVL45 - 3763 024b 0100 .2byte 0x1 - 3764 024d 52 .byte 0x52 - 3765 024e 68000000 .4byte .LVL45 - 3766 0252 6C000000 .4byte .LVL46 - 3767 0256 0400 .2byte 0x4 - 3768 0258 74 .byte 0x74 - 3769 0259 00 .sleb128 0 - 3770 025a 1F .byte 0x1f - 3771 025b 9F .byte 0x9f - 3772 025c 6C000000 .4byte .LVL46 - 3773 0260 70000000 .4byte .LVL47 - 3774 0264 0500 .2byte 0x5 - 3775 0266 74 .byte 0x74 - 3776 0267 00 .sleb128 0 - 3777 0268 1F .byte 0x1f - 3778 0269 1F .byte 0x1f - 3779 026a 9F .byte 0x9f - 3780 026b 00000000 .4byte 0 - 3781 026f 00000000 .4byte 0 - 3782 .LLST10: - 3783 0273 2C000000 .4byte .LVL33 - 3784 0277 3C000000 .4byte .LVL37 - 3785 027b 0200 .2byte 0x2 - 3786 027d 71 .byte 0x71 - 3787 027e 7F .sleb128 -1 - 3788 027f 00000000 .4byte 0 - 3789 0283 00000000 .4byte 0 - 3790 .LLST11: - 3791 0287 00000000 .4byte .LFB64 - 3792 028b 04000000 .4byte .LCFI2 - 3793 028f 0200 .2byte 0x2 - 3794 0291 7D .byte 0x7d - 3795 0292 00 .sleb128 0 - 3796 0293 04000000 .4byte .LCFI2 - 3797 0297 08000000 .4byte .LCFI3 - 3798 029b 0200 .2byte 0x2 - 3799 029d 7D .byte 0x7d - 3800 029e 24 .sleb128 36 - 3801 029f 08000000 .4byte .LCFI3 - 3802 02a3 84030000 .4byte .LFE64 - 3803 02a7 0300 .2byte 0x3 - 3804 02a9 7D .byte 0x7d - 3805 02aa A807 .sleb128 936 - 3806 02ac 00000000 .4byte 0 - 3807 02b0 00000000 .4byte 0 - 3808 .LLST12: - 3809 02b4 00000000 .4byte .LVL48 - 3810 02b8 0D000000 .4byte .LVL49-1 - 3811 02bc 0100 .2byte 0x1 - 3812 02be 50 .byte 0x50 - 3813 02bf 0D000000 .4byte .LVL49-1 - 3814 02c3 84030000 .4byte .LFE64 - 3815 02c7 0400 .2byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 98 - - - 3816 02c9 F3 .byte 0xf3 - 3817 02ca 01 .uleb128 0x1 - 3818 02cb 50 .byte 0x50 - 3819 02cc 9F .byte 0x9f - 3820 02cd 00000000 .4byte 0 - 3821 02d1 00000000 .4byte 0 - 3822 .LLST13: - 3823 02d5 B0000000 .4byte .LVL68 - 3824 02d9 DC000000 .4byte .LVL71 - 3825 02dd 0200 .2byte 0x2 - 3826 02df 30 .byte 0x30 - 3827 02e0 9F .byte 0x9f - 3828 02e1 DC000000 .4byte .LVL71 - 3829 02e5 DE000000 .4byte .LVL72 - 3830 02e9 0200 .2byte 0x2 - 3831 02eb 34 .byte 0x34 - 3832 02ec 9F .byte 0x9f - 3833 02ed DE000000 .4byte .LVL72 - 3834 02f1 34010000 .4byte .LVL78 - 3835 02f5 0100 .2byte 0x1 - 3836 02f7 54 .byte 0x54 - 3837 02f8 46010000 .4byte .LVL80 - 3838 02fc A8010000 .4byte .LVL85 - 3839 0300 0200 .2byte 0x2 - 3840 0302 30 .byte 0x30 - 3841 0303 9F .byte 0x9f - 3842 0304 A8010000 .4byte .LVL85 - 3843 0308 AA010000 .4byte .LVL86 - 3844 030c 0200 .2byte 0x2 - 3845 030e 31 .byte 0x31 - 3846 030f 9F .byte 0x9f - 3847 0310 AA010000 .4byte .LVL86 - 3848 0314 90020000 .4byte .LVL110 - 3849 0318 0200 .2byte 0x2 - 3850 031a 30 .byte 0x30 - 3851 031b 9F .byte 0x9f - 3852 031c 90020000 .4byte .LVL110 - 3853 0320 9A020000 .4byte .LVL113 - 3854 0324 0200 .2byte 0x2 - 3855 0326 38 .byte 0x38 - 3856 0327 9F .byte 0x9f - 3857 0328 9A020000 .4byte .LVL113 - 3858 032c 20030000 .4byte .LVL131 - 3859 0330 0200 .2byte 0x2 - 3860 0332 30 .byte 0x30 - 3861 0333 9F .byte 0x9f - 3862 0334 20030000 .4byte .LVL131 - 3863 0338 26030000 .4byte .LVL133 - 3864 033c 0200 .2byte 0x2 - 3865 033e 31 .byte 0x31 - 3866 033f 9F .byte 0x9f - 3867 0340 26030000 .4byte .LVL133 - 3868 0344 48030000 .4byte .LVL144 - 3869 0348 0200 .2byte 0x2 - 3870 034a 30 .byte 0x30 - 3871 034b 9F .byte 0x9f - 3872 034c 56030000 .4byte .LVL146 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 99 - - - 3873 0350 66030000 .4byte .LVL148 - 3874 0354 0200 .2byte 0x2 - 3875 0356 30 .byte 0x30 - 3876 0357 9F .byte 0x9f - 3877 0358 00000000 .4byte 0 - 3878 035c 00000000 .4byte 0 - 3879 .LLST14: - 3880 0360 B0000000 .4byte .LVL68 - 3881 0364 DC000000 .4byte .LVL71 - 3882 0368 0200 .2byte 0x2 - 3883 036a 34 .byte 0x34 - 3884 036b 9F .byte 0x9f - 3885 036c DC000000 .4byte .LVL71 - 3886 0370 DE000000 .4byte .LVL72 - 3887 0374 0200 .2byte 0x2 - 3888 0376 30 .byte 0x30 - 3889 0377 9F .byte 0x9f - 3890 0378 DE000000 .4byte .LVL72 - 3891 037c 34010000 .4byte .LVL78 - 3892 0380 0100 .2byte 0x1 - 3893 0382 55 .byte 0x55 - 3894 0383 46010000 .4byte .LVL80 - 3895 0387 4E010000 .4byte .LVL82 - 3896 038b 0200 .2byte 0x2 - 3897 038d 30 .byte 0x30 - 3898 038e 9F .byte 0x9f - 3899 038f 4E010000 .4byte .LVL82 - 3900 0393 A8010000 .4byte .LVL85 - 3901 0397 0200 .2byte 0x2 - 3902 0399 34 .byte 0x34 - 3903 039a 9F .byte 0x9f - 3904 039b A8010000 .4byte .LVL85 - 3905 039f AA010000 .4byte .LVL86 - 3906 03a3 0200 .2byte 0x2 - 3907 03a5 30 .byte 0x30 - 3908 03a6 9F .byte 0x9f - 3909 03a7 AA010000 .4byte .LVL86 - 3910 03ab 6E020000 .4byte .LVL104 - 3911 03af 0200 .2byte 0x2 - 3912 03b1 34 .byte 0x34 - 3913 03b2 9F .byte 0x9f - 3914 03b3 6E020000 .4byte .LVL104 - 3915 03b7 7C020000 .4byte .LVL107 - 3916 03bb 0200 .2byte 0x2 - 3917 03bd 30 .byte 0x30 - 3918 03be 9F .byte 0x9f - 3919 03bf 80020000 .4byte .LVL108 - 3920 03c3 94020000 .4byte .LVL111 - 3921 03c7 0200 .2byte 0x2 - 3922 03c9 34 .byte 0x34 - 3923 03ca 9F .byte 0x9f - 3924 03cb 94020000 .4byte .LVL111 - 3925 03cf 9A020000 .4byte .LVL113 - 3926 03d3 0200 .2byte 0x2 - 3927 03d5 30 .byte 0x30 - 3928 03d6 9F .byte 0x9f - 3929 03d7 9A020000 .4byte .LVL113 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 100 - - - 3930 03db 20030000 .4byte .LVL131 - 3931 03df 0200 .2byte 0x2 - 3932 03e1 34 .byte 0x34 - 3933 03e2 9F .byte 0x9f - 3934 03e3 20030000 .4byte .LVL131 - 3935 03e7 26030000 .4byte .LVL133 - 3936 03eb 0200 .2byte 0x2 - 3937 03ed 30 .byte 0x30 - 3938 03ee 9F .byte 0x9f - 3939 03ef 26030000 .4byte .LVL133 - 3940 03f3 48030000 .4byte .LVL144 - 3941 03f7 0200 .2byte 0x2 - 3942 03f9 34 .byte 0x34 - 3943 03fa 9F .byte 0x9f - 3944 03fb 56030000 .4byte .LVL146 - 3945 03ff 58030000 .4byte .LVL147 - 3946 0403 0100 .2byte 0x1 - 3947 0405 55 .byte 0x55 - 3948 0406 58030000 .4byte .LVL147 - 3949 040a 66030000 .4byte .LVL148 - 3950 040e 0200 .2byte 0x2 - 3951 0410 34 .byte 0x34 - 3952 0411 9F .byte 0x9f - 3953 0412 00000000 .4byte 0 - 3954 0416 00000000 .4byte 0 - 3955 .LLST15: - 3956 041a 7C000000 .4byte .LVL58 - 3957 041e A6000000 .4byte .LVL66 - 3958 0422 0E00 .2byte 0xe - 3959 0424 70 .byte 0x70 - 3960 0425 00 .sleb128 0 - 3961 0426 08 .byte 0x8 - 3962 0427 FF .byte 0xff - 3963 0428 1A .byte 0x1a - 3964 0429 38 .byte 0x38 - 3965 042a 24 .byte 0x24 - 3966 042b 71 .byte 0x71 - 3967 042c 00 .sleb128 0 - 3968 042d 08 .byte 0x8 - 3969 042e FF .byte 0xff - 3970 042f 1A .byte 0x1a - 3971 0430 21 .byte 0x21 - 3972 0431 9F .byte 0x9f - 3973 0432 A6000000 .4byte .LVL66 - 3974 0436 A8000000 .4byte .LVL67 - 3975 043a 1700 .2byte 0x17 - 3976 043c 91 .byte 0x91 - 3977 043d 00 .sleb128 0 - 3978 043e 75 .byte 0x75 - 3979 043f 00 .sleb128 0 - 3980 0440 22 .byte 0x22 - 3981 0441 0A .byte 0xa - 3982 0442 7B02 .2byte 0x27b - 3983 0444 1C .byte 0x1c - 3984 0445 94 .byte 0x94 - 3985 0446 01 .byte 0x1 - 3986 0447 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 101 - - - 3987 0448 FF .byte 0xff - 3988 0449 1A .byte 0x1a - 3989 044a 38 .byte 0x38 - 3990 044b 24 .byte 0x24 - 3991 044c 71 .byte 0x71 - 3992 044d 00 .sleb128 0 - 3993 044e 08 .byte 0x8 - 3994 044f FF .byte 0xff - 3995 0450 1A .byte 0x1a - 3996 0451 21 .byte 0x21 - 3997 0452 9F .byte 0x9f - 3998 0453 A8000000 .4byte .LVL67 - 3999 0457 D4000000 .4byte .LVL70 - 4000 045b 2000 .2byte 0x20 - 4001 045d 91 .byte 0x91 - 4002 045e 00 .sleb128 0 - 4003 045f 75 .byte 0x75 - 4004 0460 00 .sleb128 0 - 4005 0461 22 .byte 0x22 - 4006 0462 0A .byte 0xa - 4007 0463 7B02 .2byte 0x27b - 4008 0465 1C .byte 0x1c - 4009 0466 94 .byte 0x94 - 4010 0467 01 .byte 0x1 - 4011 0468 08 .byte 0x8 - 4012 0469 FF .byte 0xff - 4013 046a 1A .byte 0x1a - 4014 046b 38 .byte 0x38 - 4015 046c 24 .byte 0x24 - 4016 046d 91 .byte 0x91 - 4017 046e 00 .sleb128 0 - 4018 046f 75 .byte 0x75 - 4019 0470 00 .sleb128 0 - 4020 0471 22 .byte 0x22 - 4021 0472 0A .byte 0xa - 4022 0473 7C02 .2byte 0x27c - 4023 0475 1C .byte 0x1c - 4024 0476 94 .byte 0x94 - 4025 0477 01 .byte 0x1 - 4026 0478 08 .byte 0x8 - 4027 0479 FF .byte 0xff - 4028 047a 1A .byte 0x1a - 4029 047b 21 .byte 0x21 - 4030 047c 9F .byte 0x9f - 4031 047d D4000000 .4byte .LVL70 - 4032 0481 DE000000 .4byte .LVL72 - 4033 0485 4200 .2byte 0x42 - 4034 0487 91 .byte 0x91 - 4035 0488 837B .sleb128 -637 - 4036 048a 94 .byte 0x94 - 4037 048b 01 .byte 0x1 - 4038 048c 08 .byte 0x8 - 4039 048d FF .byte 0xff - 4040 048e 1A .byte 0x1a - 4041 048f 38 .byte 0x38 - 4042 0490 24 .byte 0x24 - 4043 0491 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 102 - - - 4044 0492 827B .sleb128 -638 - 4045 0494 94 .byte 0x94 - 4046 0495 01 .byte 0x1 - 4047 0496 08 .byte 0x8 - 4048 0497 FF .byte 0xff - 4049 0498 1A .byte 0x1a - 4050 0499 21 .byte 0x21 - 4051 049a 91 .byte 0x91 - 4052 049b 00 .sleb128 0 - 4053 049c 22 .byte 0x22 - 4054 049d 0A .byte 0xa - 4055 049e 7B02 .2byte 0x27b - 4056 04a0 1C .byte 0x1c - 4057 04a1 94 .byte 0x94 - 4058 04a2 01 .byte 0x1 - 4059 04a3 08 .byte 0x8 - 4060 04a4 FF .byte 0xff - 4061 04a5 1A .byte 0x1a - 4062 04a6 38 .byte 0x38 - 4063 04a7 24 .byte 0x24 - 4064 04a8 91 .byte 0x91 - 4065 04a9 837B .sleb128 -637 - 4066 04ab 94 .byte 0x94 - 4067 04ac 01 .byte 0x1 - 4068 04ad 08 .byte 0x8 - 4069 04ae FF .byte 0xff - 4070 04af 1A .byte 0x1a - 4071 04b0 38 .byte 0x38 - 4072 04b1 24 .byte 0x24 - 4073 04b2 91 .byte 0x91 - 4074 04b3 827B .sleb128 -638 - 4075 04b5 94 .byte 0x94 - 4076 04b6 01 .byte 0x1 - 4077 04b7 08 .byte 0x8 - 4078 04b8 FF .byte 0xff - 4079 04b9 1A .byte 0x1a - 4080 04ba 21 .byte 0x21 - 4081 04bb 91 .byte 0x91 - 4082 04bc 00 .sleb128 0 - 4083 04bd 22 .byte 0x22 - 4084 04be 0A .byte 0xa - 4085 04bf 7C02 .2byte 0x27c - 4086 04c1 1C .byte 0x1c - 4087 04c2 94 .byte 0x94 - 4088 04c3 01 .byte 0x1 - 4089 04c4 08 .byte 0x8 - 4090 04c5 FF .byte 0xff - 4091 04c6 1A .byte 0x1a - 4092 04c7 21 .byte 0x21 - 4093 04c8 9F .byte 0x9f - 4094 04c9 46010000 .4byte .LVL80 - 4095 04cd 9B010000 .4byte .LVL84-1 - 4096 04d1 2000 .2byte 0x20 - 4097 04d3 91 .byte 0x91 - 4098 04d4 00 .sleb128 0 - 4099 04d5 75 .byte 0x75 - 4100 04d6 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 103 - - - 4101 04d7 22 .byte 0x22 - 4102 04d8 0A .byte 0xa - 4103 04d9 7B02 .2byte 0x27b - 4104 04db 1C .byte 0x1c - 4105 04dc 94 .byte 0x94 - 4106 04dd 01 .byte 0x1 - 4107 04de 08 .byte 0x8 - 4108 04df FF .byte 0xff - 4109 04e0 1A .byte 0x1a - 4110 04e1 38 .byte 0x38 - 4111 04e2 24 .byte 0x24 - 4112 04e3 91 .byte 0x91 - 4113 04e4 00 .sleb128 0 - 4114 04e5 75 .byte 0x75 - 4115 04e6 00 .sleb128 0 - 4116 04e7 22 .byte 0x22 - 4117 04e8 0A .byte 0xa - 4118 04e9 7C02 .2byte 0x27c - 4119 04eb 1C .byte 0x1c - 4120 04ec 94 .byte 0x94 - 4121 04ed 01 .byte 0x1 - 4122 04ee 08 .byte 0x8 - 4123 04ef FF .byte 0xff - 4124 04f0 1A .byte 0x1a - 4125 04f1 21 .byte 0x21 - 4126 04f2 9F .byte 0x9f - 4127 04f3 AA010000 .4byte .LVL86 - 4128 04f7 D1010000 .4byte .LVL88-1 - 4129 04fb 2000 .2byte 0x20 - 4130 04fd 91 .byte 0x91 - 4131 04fe 00 .sleb128 0 - 4132 04ff 75 .byte 0x75 - 4133 0500 00 .sleb128 0 - 4134 0501 22 .byte 0x22 - 4135 0502 0A .byte 0xa - 4136 0503 7B02 .2byte 0x27b - 4137 0505 1C .byte 0x1c - 4138 0506 94 .byte 0x94 - 4139 0507 01 .byte 0x1 - 4140 0508 08 .byte 0x8 - 4141 0509 FF .byte 0xff - 4142 050a 1A .byte 0x1a - 4143 050b 38 .byte 0x38 - 4144 050c 24 .byte 0x24 - 4145 050d 91 .byte 0x91 - 4146 050e 00 .sleb128 0 - 4147 050f 75 .byte 0x75 - 4148 0510 00 .sleb128 0 - 4149 0511 22 .byte 0x22 - 4150 0512 0A .byte 0xa - 4151 0513 7C02 .2byte 0x27c - 4152 0515 1C .byte 0x1c - 4153 0516 94 .byte 0x94 - 4154 0517 01 .byte 0x1 - 4155 0518 08 .byte 0x8 - 4156 0519 FF .byte 0xff - 4157 051a 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 104 - - - 4158 051b 21 .byte 0x21 - 4159 051c 9F .byte 0x9f - 4160 051d D4010000 .4byte .LVL89 - 4161 0521 E0010000 .4byte .LVL90 - 4162 0525 2000 .2byte 0x20 - 4163 0527 91 .byte 0x91 - 4164 0528 00 .sleb128 0 - 4165 0529 75 .byte 0x75 - 4166 052a 00 .sleb128 0 - 4167 052b 22 .byte 0x22 - 4168 052c 0A .byte 0xa - 4169 052d 7B02 .2byte 0x27b - 4170 052f 1C .byte 0x1c - 4171 0530 94 .byte 0x94 - 4172 0531 01 .byte 0x1 - 4173 0532 08 .byte 0x8 - 4174 0533 FF .byte 0xff - 4175 0534 1A .byte 0x1a - 4176 0535 38 .byte 0x38 - 4177 0536 24 .byte 0x24 - 4178 0537 91 .byte 0x91 - 4179 0538 00 .sleb128 0 - 4180 0539 75 .byte 0x75 - 4181 053a 00 .sleb128 0 - 4182 053b 22 .byte 0x22 - 4183 053c 0A .byte 0xa - 4184 053d 7C02 .2byte 0x27c - 4185 053f 1C .byte 0x1c - 4186 0540 94 .byte 0x94 - 4187 0541 01 .byte 0x1 - 4188 0542 08 .byte 0x8 - 4189 0543 FF .byte 0xff - 4190 0544 1A .byte 0x1a - 4191 0545 21 .byte 0x21 - 4192 0546 9F .byte 0x9f - 4193 0547 5C020000 .4byte .LVL103 - 4194 054b 79020000 .4byte .LVL106-1 - 4195 054f 2000 .2byte 0x20 - 4196 0551 91 .byte 0x91 - 4197 0552 00 .sleb128 0 - 4198 0553 75 .byte 0x75 - 4199 0554 00 .sleb128 0 - 4200 0555 22 .byte 0x22 - 4201 0556 0A .byte 0xa - 4202 0557 7B02 .2byte 0x27b - 4203 0559 1C .byte 0x1c - 4204 055a 94 .byte 0x94 - 4205 055b 01 .byte 0x1 - 4206 055c 08 .byte 0x8 - 4207 055d FF .byte 0xff - 4208 055e 1A .byte 0x1a - 4209 055f 38 .byte 0x38 - 4210 0560 24 .byte 0x24 - 4211 0561 91 .byte 0x91 - 4212 0562 00 .sleb128 0 - 4213 0563 75 .byte 0x75 - 4214 0564 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 105 - - - 4215 0565 22 .byte 0x22 - 4216 0566 0A .byte 0xa - 4217 0567 7C02 .2byte 0x27c - 4218 0569 1C .byte 0x1c - 4219 056a 94 .byte 0x94 - 4220 056b 01 .byte 0x1 - 4221 056c 08 .byte 0x8 - 4222 056d FF .byte 0xff - 4223 056e 1A .byte 0x1a - 4224 056f 21 .byte 0x21 - 4225 0570 9F .byte 0x9f - 4226 0571 80020000 .4byte .LVL108 - 4227 0575 B4020000 .4byte .LVL114 - 4228 0579 2000 .2byte 0x20 - 4229 057b 91 .byte 0x91 - 4230 057c 00 .sleb128 0 - 4231 057d 75 .byte 0x75 - 4232 057e 00 .sleb128 0 - 4233 057f 22 .byte 0x22 - 4234 0580 0A .byte 0xa - 4235 0581 7B02 .2byte 0x27b - 4236 0583 1C .byte 0x1c - 4237 0584 94 .byte 0x94 - 4238 0585 01 .byte 0x1 - 4239 0586 08 .byte 0x8 - 4240 0587 FF .byte 0xff - 4241 0588 1A .byte 0x1a - 4242 0589 38 .byte 0x38 - 4243 058a 24 .byte 0x24 - 4244 058b 91 .byte 0x91 - 4245 058c 00 .sleb128 0 - 4246 058d 75 .byte 0x75 - 4247 058e 00 .sleb128 0 - 4248 058f 22 .byte 0x22 - 4249 0590 0A .byte 0xa - 4250 0591 7C02 .2byte 0x27c - 4251 0593 1C .byte 0x1c - 4252 0594 94 .byte 0x94 - 4253 0595 01 .byte 0x1 - 4254 0596 08 .byte 0x8 - 4255 0597 FF .byte 0xff - 4256 0598 1A .byte 0x1a - 4257 0599 21 .byte 0x21 - 4258 059a 9F .byte 0x9f - 4259 059b B4020000 .4byte .LVL114 - 4260 059f 22030000 .4byte .LVL132 - 4261 05a3 4200 .2byte 0x42 - 4262 05a5 91 .byte 0x91 - 4263 05a6 837B .sleb128 -637 - 4264 05a8 94 .byte 0x94 - 4265 05a9 01 .byte 0x1 - 4266 05aa 08 .byte 0x8 - 4267 05ab FF .byte 0xff - 4268 05ac 1A .byte 0x1a - 4269 05ad 38 .byte 0x38 - 4270 05ae 24 .byte 0x24 - 4271 05af 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 106 - - - 4272 05b0 827B .sleb128 -638 - 4273 05b2 94 .byte 0x94 - 4274 05b3 01 .byte 0x1 - 4275 05b4 08 .byte 0x8 - 4276 05b5 FF .byte 0xff - 4277 05b6 1A .byte 0x1a - 4278 05b7 21 .byte 0x21 - 4279 05b8 91 .byte 0x91 - 4280 05b9 00 .sleb128 0 - 4281 05ba 22 .byte 0x22 - 4282 05bb 0A .byte 0xa - 4283 05bc 7B02 .2byte 0x27b - 4284 05be 1C .byte 0x1c - 4285 05bf 94 .byte 0x94 - 4286 05c0 01 .byte 0x1 - 4287 05c1 08 .byte 0x8 - 4288 05c2 FF .byte 0xff - 4289 05c3 1A .byte 0x1a - 4290 05c4 38 .byte 0x38 - 4291 05c5 24 .byte 0x24 - 4292 05c6 91 .byte 0x91 - 4293 05c7 837B .sleb128 -637 - 4294 05c9 94 .byte 0x94 - 4295 05ca 01 .byte 0x1 - 4296 05cb 08 .byte 0x8 - 4297 05cc FF .byte 0xff - 4298 05cd 1A .byte 0x1a - 4299 05ce 38 .byte 0x38 - 4300 05cf 24 .byte 0x24 - 4301 05d0 91 .byte 0x91 - 4302 05d1 827B .sleb128 -638 - 4303 05d3 94 .byte 0x94 - 4304 05d4 01 .byte 0x1 - 4305 05d5 08 .byte 0x8 - 4306 05d6 FF .byte 0xff - 4307 05d7 1A .byte 0x1a - 4308 05d8 21 .byte 0x21 - 4309 05d9 91 .byte 0x91 - 4310 05da 00 .sleb128 0 - 4311 05db 22 .byte 0x22 - 4312 05dc 0A .byte 0xa - 4313 05dd 7C02 .2byte 0x27c - 4314 05df 1C .byte 0x1c - 4315 05e0 94 .byte 0x94 - 4316 05e1 01 .byte 0x1 - 4317 05e2 08 .byte 0x8 - 4318 05e3 FF .byte 0xff - 4319 05e4 1A .byte 0x1a - 4320 05e5 21 .byte 0x21 - 4321 05e6 9F .byte 0x9f - 4322 05e7 26030000 .4byte .LVL133 - 4323 05eb 29030000 .4byte .LVL134-1 - 4324 05ef 2000 .2byte 0x20 - 4325 05f1 91 .byte 0x91 - 4326 05f2 00 .sleb128 0 - 4327 05f3 75 .byte 0x75 - 4328 05f4 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 107 - - - 4329 05f5 22 .byte 0x22 - 4330 05f6 0A .byte 0xa - 4331 05f7 7B02 .2byte 0x27b - 4332 05f9 1C .byte 0x1c - 4333 05fa 94 .byte 0x94 - 4334 05fb 01 .byte 0x1 - 4335 05fc 08 .byte 0x8 - 4336 05fd FF .byte 0xff - 4337 05fe 1A .byte 0x1a - 4338 05ff 38 .byte 0x38 - 4339 0600 24 .byte 0x24 - 4340 0601 91 .byte 0x91 - 4341 0602 00 .sleb128 0 - 4342 0603 75 .byte 0x75 - 4343 0604 00 .sleb128 0 - 4344 0605 22 .byte 0x22 - 4345 0606 0A .byte 0xa - 4346 0607 7C02 .2byte 0x27c - 4347 0609 1C .byte 0x1c - 4348 060a 94 .byte 0x94 - 4349 060b 01 .byte 0x1 - 4350 060c 08 .byte 0x8 - 4351 060d FF .byte 0xff - 4352 060e 1A .byte 0x1a - 4353 060f 21 .byte 0x21 - 4354 0610 9F .byte 0x9f - 4355 0611 38030000 .4byte .LVL137 - 4356 0615 3A030000 .4byte .LVL138 - 4357 0619 2000 .2byte 0x20 - 4358 061b 91 .byte 0x91 - 4359 061c 00 .sleb128 0 - 4360 061d 75 .byte 0x75 - 4361 061e 00 .sleb128 0 - 4362 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0xff - 4397 064c 1A .byte 0x1a - 4398 064d 38 .byte 0x38 - 4399 064e 24 .byte 0x24 - 4400 064f 91 .byte 0x91 - 4401 0650 827B .sleb128 -638 - 4402 0652 94 .byte 0x94 - 4403 0653 01 .byte 0x1 - 4404 0654 08 .byte 0x8 - 4405 0655 FF .byte 0xff - 4406 0656 1A .byte 0x1a - 4407 0657 21 .byte 0x21 - 4408 0658 91 .byte 0x91 - 4409 0659 00 .sleb128 0 - 4410 065a 22 .byte 0x22 - 4411 065b 0A .byte 0xa - 4412 065c 7B02 .2byte 0x27b - 4413 065e 1C .byte 0x1c - 4414 065f 94 .byte 0x94 - 4415 0660 01 .byte 0x1 - 4416 0661 08 .byte 0x8 - 4417 0662 FF .byte 0xff - 4418 0663 1A .byte 0x1a - 4419 0664 38 .byte 0x38 - 4420 0665 24 .byte 0x24 - 4421 0666 91 .byte 0x91 - 4422 0667 837B .sleb128 -637 - 4423 0669 94 .byte 0x94 - 4424 066a 01 .byte 0x1 - 4425 066b 08 .byte 0x8 - 4426 066c FF .byte 0xff - 4427 066d 1A .byte 0x1a - 4428 066e 38 .byte 0x38 - 4429 066f 24 .byte 0x24 - 4430 0670 91 .byte 0x91 - 4431 0671 827B .sleb128 -638 - 4432 0673 94 .byte 0x94 - 4433 0674 01 .byte 0x1 - 4434 0675 08 .byte 0x8 - 4435 0676 FF .byte 0xff - 4436 0677 1A .byte 0x1a - 4437 0678 21 .byte 0x21 - 4438 0679 91 .byte 0x91 - 4439 067a 00 .sleb128 0 - 4440 067b 22 .byte 0x22 - 4441 067c 0A .byte 0xa - 4442 067d 7C02 .2byte 0x27c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 109 - - - 4443 067f 1C .byte 0x1c - 4444 0680 94 .byte 0x94 - 4445 0681 01 .byte 0x1 - 4446 0682 08 .byte 0x8 - 4447 0683 FF .byte 0xff - 4448 0684 1A .byte 0x1a - 4449 0685 21 .byte 0x21 - 4450 0686 9F .byte 0x9f - 4451 0687 46030000 .4byte .LVL143 - 4452 068b 48030000 .4byte .LVL144 - 4453 068f 2000 .2byte 0x20 - 4454 0691 91 .byte 0x91 - 4455 0692 00 .sleb128 0 - 4456 0693 75 .byte 0x75 - 4457 0694 00 .sleb128 0 - 4458 0695 22 .byte 0x22 - 4459 0696 0A .byte 0xa - 4460 0697 7B02 .2byte 0x27b - 4461 0699 1C .byte 0x1c - 4462 069a 94 .byte 0x94 - 4463 069b 01 .byte 0x1 - 4464 069c 08 .byte 0x8 - 4465 069d FF .byte 0xff - 4466 069e 1A .byte 0x1a - 4467 069f 38 .byte 0x38 - 4468 06a0 24 .byte 0x24 - 4469 06a1 91 .byte 0x91 - 4470 06a2 00 .sleb128 0 - 4471 06a3 75 .byte 0x75 - 4472 06a4 00 .sleb128 0 - 4473 06a5 22 .byte 0x22 - 4474 06a6 0A .byte 0xa - 4475 06a7 7C02 .2byte 0x27c - 4476 06a9 1C .byte 0x1c - 4477 06aa 94 .byte 0x94 - 4478 06ab 01 .byte 0x1 - 4479 06ac 08 .byte 0x8 - 4480 06ad FF .byte 0xff - 4481 06ae 1A .byte 0x1a - 4482 06af 21 .byte 0x21 - 4483 06b0 9F .byte 0x9f - 4484 06b1 54030000 .4byte .LVL145 - 4485 06b5 56030000 .4byte .LVL146 - 4486 06b9 2000 .2byte 0x20 - 4487 06bb 91 .byte 0x91 - 4488 06bc 00 .sleb128 0 - 4489 06bd 75 .byte 0x75 - 4490 06be 00 .sleb128 0 - 4491 06bf 22 .byte 0x22 - 4492 06c0 0A .byte 0xa - 4493 06c1 7B02 .2byte 0x27b - 4494 06c3 1C .byte 0x1c - 4495 06c4 94 .byte 0x94 - 4496 06c5 01 .byte 0x1 - 4497 06c6 08 .byte 0x8 - 4498 06c7 FF .byte 0xff - 4499 06c8 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 110 - - - 4500 06c9 38 .byte 0x38 - 4501 06ca 24 .byte 0x24 - 4502 06cb 91 .byte 0x91 - 4503 06cc 00 .sleb128 0 - 4504 06cd 75 .byte 0x75 - 4505 06ce 00 .sleb128 0 - 4506 06cf 22 .byte 0x22 - 4507 06d0 0A .byte 0xa - 4508 06d1 7C02 .2byte 0x27c - 4509 06d3 1C .byte 0x1c - 4510 06d4 94 .byte 0x94 - 4511 06d5 01 .byte 0x1 - 4512 06d6 08 .byte 0x8 - 4513 06d7 FF .byte 0xff - 4514 06d8 1A .byte 0x1a - 4515 06d9 21 .byte 0x21 - 4516 06da 9F .byte 0x9f - 4517 06db 56030000 .4byte .LVL146 - 4518 06df 58030000 .4byte .LVL147 - 4519 06e3 4200 .2byte 0x42 - 4520 06e5 91 .byte 0x91 - 4521 06e6 837B .sleb128 -637 - 4522 06e8 94 .byte 0x94 - 4523 06e9 01 .byte 0x1 - 4524 06ea 08 .byte 0x8 - 4525 06eb FF .byte 0xff - 4526 06ec 1A .byte 0x1a - 4527 06ed 38 .byte 0x38 - 4528 06ee 24 .byte 0x24 - 4529 06ef 91 .byte 0x91 - 4530 06f0 827B .sleb128 -638 - 4531 06f2 94 .byte 0x94 - 4532 06f3 01 .byte 0x1 - 4533 06f4 08 .byte 0x8 - 4534 06f5 FF .byte 0xff - 4535 06f6 1A .byte 0x1a - 4536 06f7 21 .byte 0x21 - 4537 06f8 91 .byte 0x91 - 4538 06f9 00 .sleb128 0 - 4539 06fa 22 .byte 0x22 - 4540 06fb 0A .byte 0xa - 4541 06fc 7B02 .2byte 0x27b - 4542 06fe 1C .byte 0x1c - 4543 06ff 94 .byte 0x94 - 4544 0700 01 .byte 0x1 - 4545 0701 08 .byte 0x8 - 4546 0702 FF .byte 0xff - 4547 0703 1A .byte 0x1a - 4548 0704 38 .byte 0x38 - 4549 0705 24 .byte 0x24 - 4550 0706 91 .byte 0x91 - 4551 0707 837B .sleb128 -637 - 4552 0709 94 .byte 0x94 - 4553 070a 01 .byte 0x1 - 4554 070b 08 .byte 0x8 - 4555 070c FF .byte 0xff - 4556 070d 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 111 - - - 4557 070e 38 .byte 0x38 - 4558 070f 24 .byte 0x24 - 4559 0710 91 .byte 0x91 - 4560 0711 827B .sleb128 -638 - 4561 0713 94 .byte 0x94 - 4562 0714 01 .byte 0x1 - 4563 0715 08 .byte 0x8 - 4564 0716 FF .byte 0xff - 4565 0717 1A .byte 0x1a - 4566 0718 21 .byte 0x21 - 4567 0719 91 .byte 0x91 - 4568 071a 00 .sleb128 0 - 4569 071b 22 .byte 0x22 - 4570 071c 0A .byte 0xa - 4571 071d 7C02 .2byte 0x27c - 4572 071f 1C .byte 0x1c - 4573 0720 94 .byte 0x94 - 4574 0721 01 .byte 0x1 - 4575 0722 08 .byte 0x8 - 4576 0723 FF .byte 0xff - 4577 0724 1A .byte 0x1a - 4578 0725 21 .byte 0x21 - 4579 0726 9F .byte 0x9f - 4580 0727 58030000 .4byte .LVL147 - 4581 072b 66030000 .4byte .LVL148 - 4582 072f 2000 .2byte 0x20 - 4583 0731 91 .byte 0x91 - 4584 0732 00 .sleb128 0 - 4585 0733 75 .byte 0x75 - 4586 0734 00 .sleb128 0 - 4587 0735 22 .byte 0x22 - 4588 0736 0A .byte 0xa - 4589 0737 7B02 .2byte 0x27b - 4590 0739 1C .byte 0x1c - 4591 073a 94 .byte 0x94 - 4592 073b 01 .byte 0x1 - 4593 073c 08 .byte 0x8 - 4594 073d FF .byte 0xff - 4595 073e 1A .byte 0x1a - 4596 073f 38 .byte 0x38 - 4597 0740 24 .byte 0x24 - 4598 0741 91 .byte 0x91 - 4599 0742 00 .sleb128 0 - 4600 0743 75 .byte 0x75 - 4601 0744 00 .sleb128 0 - 4602 0745 22 .byte 0x22 - 4603 0746 0A .byte 0xa - 4604 0747 7C02 .2byte 0x27c - 4605 0749 1C .byte 0x1c - 4606 074a 94 .byte 0x94 - 4607 074b 01 .byte 0x1 - 4608 074c 08 .byte 0x8 - 4609 074d FF .byte 0xff - 4610 074e 1A .byte 0x1a - 4611 074f 21 .byte 0x21 - 4612 0750 9F .byte 0x9f - 4613 0751 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 112 - - - 4614 0755 00000000 .4byte 0 - 4615 .LLST16: - 4616 0759 32000000 .4byte .LVL54 - 4617 075d 68000000 .4byte .LVL56 - 4618 0761 0100 .2byte 0x1 - 4619 0763 50 .byte 0x50 - 4620 0764 00000000 .4byte 0 - 4621 0768 00000000 .4byte 0 - 4622 .LLST17: - 4623 076c 00000000 .4byte .LVL48 - 4624 0770 1A000000 .4byte .LVL50 - 4625 0774 0200 .2byte 0x2 - 4626 0776 30 .byte 0x30 - 4627 0777 9F .byte 0x9f - 4628 0778 72000000 .4byte .LVL57 - 4629 077c D4000000 .4byte .LVL70 - 4630 0780 0100 .2byte 0x1 - 4631 0782 55 .byte 0x55 - 4632 0783 D4000000 .4byte .LVL70 - 4633 0787 DE000000 .4byte .LVL72 - 4634 078b 1400 .2byte 0x14 - 4635 078d 91 .byte 0x91 - 4636 078e 837B .sleb128 -637 - 4637 0790 94 .byte 0x94 - 4638 0791 01 .byte 0x1 - 4639 0792 08 .byte 0x8 - 4640 0793 FF .byte 0xff - 4641 0794 1A .byte 0x1a - 4642 0795 38 .byte 0x38 - 4643 0796 24 .byte 0x24 - 4644 0797 91 .byte 0x91 - 4645 0798 827B .sleb128 -638 - 4646 079a 94 .byte 0x94 - 4647 079b 01 .byte 0x1 - 4648 079c 08 .byte 0x8 - 4649 079d FF .byte 0xff - 4650 079e 1A .byte 0x1a - 4651 079f 21 .byte 0x21 - 4652 07a0 9F .byte 0x9f - 4653 07a1 46010000 .4byte .LVL80 - 4654 07a5 E2010000 .4byte .LVL91 - 4655 07a9 0100 .2byte 0x1 - 4656 07ab 55 .byte 0x55 - 4657 07ac E2010000 .4byte .LVL91 - 4658 07b0 00020000 .4byte .LVL94 - 4659 07b4 0300 .2byte 0x3 - 4660 07b6 75 .byte 0x75 - 4661 07b7 03 .sleb128 3 - 4662 07b8 9F .byte 0x9f - 4663 07b9 00020000 .4byte .LVL94 - 4664 07bd 04020000 .4byte .LVL95 - 4665 07c1 0200 .2byte 0x2 - 4666 07c3 40 .byte 0x40 - 4667 07c4 9F .byte 0x9f - 4668 07c5 04020000 .4byte .LVL95 - 4669 07c9 08020000 .4byte .LVL96 - 4670 07cd 0300 .2byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 113 - - - 4671 07cf 75 .byte 0x75 - 4672 07d0 03 .sleb128 3 - 4673 07d1 9F .byte 0x9f - 4674 07d2 08020000 .4byte .LVL96 - 4675 07d6 5C020000 .4byte .LVL103 - 4676 07da 0100 .2byte 0x1 - 4677 07dc 54 .byte 0x54 - 4678 07dd 5C020000 .4byte .LVL103 - 4679 07e1 7C020000 .4byte .LVL107 - 4680 07e5 0100 .2byte 0x1 - 4681 07e7 55 .byte 0x55 - 4682 07e8 80020000 .4byte .LVL108 - 4683 07ec B4020000 .4byte .LVL114 - 4684 07f0 0100 .2byte 0x1 - 4685 07f2 55 .byte 0x55 - 4686 07f3 B4020000 .4byte .LVL114 - 4687 07f7 22030000 .4byte .LVL132 - 4688 07fb 1400 .2byte 0x14 - 4689 07fd 91 .byte 0x91 - 4690 07fe 837B .sleb128 -637 - 4691 0800 94 .byte 0x94 - 4692 0801 01 .byte 0x1 - 4693 0802 08 .byte 0x8 - 4694 0803 FF .byte 0xff - 4695 0804 1A .byte 0x1a - 4696 0805 38 .byte 0x38 - 4697 0806 24 .byte 0x24 - 4698 0807 91 .byte 0x91 - 4699 0808 827B .sleb128 -638 - 4700 080a 94 .byte 0x94 - 4701 080b 01 .byte 0x1 - 4702 080c 08 .byte 0x8 - 4703 080d FF .byte 0xff - 4704 080e 1A .byte 0x1a - 4705 080f 21 .byte 0x21 - 4706 0810 9F .byte 0x9f - 4707 0811 26030000 .4byte .LVL133 - 4708 0815 2E030000 .4byte .LVL135 - 4709 0819 0100 .2byte 0x1 - 4710 081b 55 .byte 0x55 - 4711 081c 38030000 .4byte .LVL137 - 4712 0820 3A030000 .4byte .LVL138 - 4713 0824 0100 .2byte 0x1 - 4714 0826 55 .byte 0x55 - 4715 0827 3A030000 .4byte .LVL138 - 4716 082b 3C030000 .4byte .LVL139 - 4717 082f 1400 .2byte 0x14 - 4718 0831 91 .byte 0x91 - 4719 0832 837B .sleb128 -637 - 4720 0834 94 .byte 0x94 - 4721 0835 01 .byte 0x1 - 4722 0836 08 .byte 0x8 - 4723 0837 FF .byte 0xff - 4724 0838 1A .byte 0x1a - 4725 0839 38 .byte 0x38 - 4726 083a 24 .byte 0x24 - 4727 083b 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 114 - - - 4728 083c 827B .sleb128 -638 - 4729 083e 94 .byte 0x94 - 4730 083f 01 .byte 0x1 - 4731 0840 08 .byte 0x8 - 4732 0841 FF .byte 0xff - 4733 0842 1A .byte 0x1a - 4734 0843 21 .byte 0x21 - 4735 0844 9F .byte 0x9f - 4736 0845 3C030000 .4byte .LVL139 - 4737 0849 46030000 .4byte .LVL143 - 4738 084d 0100 .2byte 0x1 - 4739 084f 54 .byte 0x54 - 4740 0850 46030000 .4byte .LVL143 - 4741 0854 48030000 .4byte .LVL144 - 4742 0858 0100 .2byte 0x1 - 4743 085a 55 .byte 0x55 - 4744 085b 54030000 .4byte .LVL145 - 4745 085f 56030000 .4byte .LVL146 - 4746 0863 0100 .2byte 0x1 - 4747 0865 55 .byte 0x55 - 4748 0866 00000000 .4byte 0 - 4749 086a 00000000 .4byte 0 - 4750 .LLST18: - 4751 086e 00000000 .4byte .LVL48 - 4752 0872 1A000000 .4byte .LVL50 - 4753 0876 0200 .2byte 0x2 - 4754 0878 30 .byte 0x30 - 4755 0879 9F .byte 0x9f - 4756 087a DE000000 .4byte .LVL72 - 4757 087e 42010000 .4byte .LVL79 - 4758 0882 0100 .2byte 0x1 - 4759 0884 57 .byte 0x57 - 4760 0885 C8010000 .4byte .LVL87 - 4761 0889 E0010000 .4byte .LVL90 - 4762 088d 0100 .2byte 0x1 - 4763 088f 57 .byte 0x57 - 4764 0890 FA010000 .4byte .LVL93 - 4765 0894 FF010000 .4byte .LVL94-1 - 4766 0898 0100 .2byte 0x1 - 4767 089a 52 .byte 0x52 - 4768 089b FF010000 .4byte .LVL94-1 - 4769 089f 04020000 .4byte .LVL95 - 4770 08a3 0100 .2byte 0x1 - 4771 08a5 56 .byte 0x56 - 4772 08a6 04020000 .4byte .LVL95 - 4773 08aa 08020000 .4byte .LVL96 - 4774 08ae 0100 .2byte 0x1 - 4775 08b0 52 .byte 0x52 - 4776 08b1 08020000 .4byte .LVL96 - 4777 08b5 1E020000 .4byte .LVL97 - 4778 08b9 0100 .2byte 0x1 - 4779 08bb 56 .byte 0x56 - 4780 08bc 1E020000 .4byte .LVL97 - 4781 08c0 5A020000 .4byte .LVL102 - 4782 08c4 0100 .2byte 0x1 - 4783 08c6 55 .byte 0x55 - 4784 08c7 7C020000 .4byte .LVL107 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 115 - - - 4785 08cb 80020000 .4byte .LVL108 - 4786 08cf 0100 .2byte 0x1 - 4787 08d1 57 .byte 0x57 - 4788 08d2 3C030000 .4byte .LVL139 - 4789 08d6 3E030000 .4byte .LVL140 - 4790 08da 0100 .2byte 0x1 - 4791 08dc 56 .byte 0x56 - 4792 08dd 3E030000 .4byte .LVL140 - 4793 08e1 40030000 .4byte .LVL141 - 4794 08e5 0600 .2byte 0x6 - 4795 08e7 77 .byte 0x77 - 4796 08e8 00 .sleb128 0 - 4797 08e9 75 .byte 0x75 - 4798 08ea 00 .sleb128 0 - 4799 08eb 22 .byte 0x22 - 4800 08ec 9F .byte 0x9f - 4801 08ed 42030000 .4byte .LVL142 - 4802 08f1 46030000 .4byte .LVL143 - 4803 08f5 0100 .2byte 0x1 - 4804 08f7 55 .byte 0x55 - 4805 08f8 58030000 .4byte .LVL147 - 4806 08fc 66030000 .4byte .LVL148 - 4807 0900 0200 .2byte 0x2 - 4808 0902 30 .byte 0x30 - 4809 0903 9F .byte 0x9f - 4810 0904 66030000 .4byte .LVL148 - 4811 0908 84030000 .4byte .LFE64 - 4812 090c 0100 .2byte 0x1 - 4813 090e 57 .byte 0x57 - 4814 090f 00000000 .4byte 0 - 4815 0913 00000000 .4byte 0 - 4816 .LLST19: - 4817 0917 00000000 .4byte .LVL48 - 4818 091b 1A000000 .4byte .LVL50 - 4819 091f 0200 .2byte 0x2 - 4820 0921 3A .byte 0x3a - 4821 0922 9F .byte 0x9f - 4822 0923 1A000000 .4byte .LVL50 - 4823 0927 20000000 .4byte .LVL51 - 4824 092b 0100 .2byte 0x1 - 4825 092d 59 .byte 0x59 - 4826 092e 24000000 .4byte .LVL52 - 4827 0932 26000000 .4byte .LVL53 - 4828 0936 0100 .2byte 0x1 - 4829 0938 59 .byte 0x59 - 4830 0939 40000000 .4byte .LVL55 - 4831 093d 84030000 .4byte .LFE64 - 4832 0941 0100 .2byte 0x1 - 4833 0943 59 .byte 0x59 - 4834 0944 00000000 .4byte 0 - 4835 0948 00000000 .4byte 0 - 4836 .LLST20: - 4837 094c 00000000 .4byte .LVL48 - 4838 0950 1A000000 .4byte .LVL50 - 4839 0954 0200 .2byte 0x2 - 4840 0956 30 .byte 0x30 - 4841 0957 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 116 - - - 4842 0958 DE000000 .4byte .LVL72 - 4843 095c 42010000 .4byte .LVL79 - 4844 0960 0100 .2byte 0x1 - 4845 0962 5A .byte 0x5a - 4846 0963 40020000 .4byte .LVL99 - 4847 0967 44020000 .4byte .LVL100 - 4848 096b 0200 .2byte 0x2 - 4849 096d 31 .byte 0x31 - 4850 096e 9F .byte 0x9f - 4851 096f 44020000 .4byte .LVL100 - 4852 0973 5C020000 .4byte .LVL103 - 4853 0977 0100 .2byte 0x1 - 4854 0979 5A .byte 0x5a - 4855 097a 42030000 .4byte .LVL142 - 4856 097e 46030000 .4byte .LVL143 - 4857 0982 0100 .2byte 0x1 - 4858 0984 5A .byte 0x5a - 4859 0985 58030000 .4byte .LVL147 - 4860 0989 84030000 .4byte .LFE64 - 4861 098d 0100 .2byte 0x1 - 4862 098f 5A .byte 0x5a - 4863 0990 00000000 .4byte 0 - 4864 0994 00000000 .4byte 0 - 4865 .LLST21: - 4866 0998 00000000 .4byte .LVL48 - 4867 099c 1A000000 .4byte .LVL50 - 4868 09a0 0200 .2byte 0x2 - 4869 09a2 30 .byte 0x30 - 4870 09a3 9F .byte 0x9f - 4871 09a4 DE000000 .4byte .LVL72 - 4872 09a8 42010000 .4byte .LVL79 - 4873 09ac 0100 .2byte 0x1 - 4874 09ae 56 .byte 0x56 - 4875 09af 90020000 .4byte .LVL110 - 4876 09b3 9A020000 .4byte .LVL113 - 4877 09b7 0200 .2byte 0x2 - 4878 09b9 31 .byte 0x31 - 4879 09ba 9F .byte 0x9f - 4880 09bb 58030000 .4byte .LVL147 - 4881 09bf 66030000 .4byte .LVL148 - 4882 09c3 0200 .2byte 0x2 - 4883 09c5 31 .byte 0x31 - 4884 09c6 9F .byte 0x9f - 4885 09c7 66030000 .4byte .LVL148 - 4886 09cb 84030000 .4byte .LFE64 - 4887 09cf 0100 .2byte 0x1 - 4888 09d1 56 .byte 0x56 - 4889 09d2 00000000 .4byte 0 - 4890 09d6 00000000 .4byte 0 - 4891 .LLST22: - 4892 09da 8C000000 .4byte .LVL59 - 4893 09de 98000000 .4byte .LVL61 - 4894 09e2 0100 .2byte 0x1 - 4895 09e4 53 .byte 0x53 - 4896 09e5 98000000 .4byte .LVL61 - 4897 09e9 9E000000 .4byte .LVL64 - 4898 09ed 0300 .2byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 117 - - - 4899 09ef 73 .byte 0x73 - 4900 09f0 01 .sleb128 1 - 4901 09f1 9F .byte 0x9f - 4902 09f2 9E000000 .4byte .LVL64 - 4903 09f6 B0000000 .4byte .LVL68 - 4904 09fa 0100 .2byte 0x1 - 4905 09fc 53 .byte 0x53 - 4906 09fd 46010000 .4byte .LVL80 - 4907 0a01 52010000 .4byte .LVL83 - 4908 0a05 0100 .2byte 0x1 - 4909 0a07 53 .byte 0x53 - 4910 0a08 54030000 .4byte .LVL145 - 4911 0a0c 58030000 .4byte .LVL147 - 4912 0a10 0100 .2byte 0x1 - 4913 0a12 53 .byte 0x53 - 4914 0a13 00000000 .4byte 0 - 4915 0a17 00000000 .4byte 0 - 4916 .LLST23: - 4917 0a1b 8C000000 .4byte .LVL59 - 4918 0a1f DE000000 .4byte .LVL72 - 4919 0a23 0400 .2byte 0x4 - 4920 0a25 91 .byte 0x91 - 4921 0a26 807B .sleb128 -640 - 4922 0a28 9F .byte 0x9f - 4923 0a29 46010000 .4byte .LVL80 - 4924 0a2d 48030000 .4byte .LVL144 - 4925 0a31 0400 .2byte 0x4 - 4926 0a33 91 .byte 0x91 - 4927 0a34 807B .sleb128 -640 - 4928 0a36 9F .byte 0x9f - 4929 0a37 54030000 .4byte .LVL145 - 4930 0a3b 66030000 .4byte .LVL148 - 4931 0a3f 0400 .2byte 0x4 - 4932 0a41 91 .byte 0x91 - 4933 0a42 807B .sleb128 -640 - 4934 0a44 9F .byte 0x9f - 4935 0a45 00000000 .4byte 0 - 4936 0a49 00000000 .4byte 0 - 4937 .LLST24: - 4938 0a4d 8C000000 .4byte .LVL59 - 4939 0a51 8E000000 .4byte .LVL60 - 4940 0a55 0200 .2byte 0x2 - 4941 0a57 30 .byte 0x30 - 4942 0a58 9F .byte 0x9f - 4943 0a59 8E000000 .4byte .LVL60 - 4944 0a5d 9A000000 .4byte .LVL62 - 4945 0a61 0100 .2byte 0x1 - 4946 0a63 52 .byte 0x52 - 4947 0a64 9C000000 .4byte .LVL63 - 4948 0a68 A2000000 .4byte .LVL65 - 4949 0a6c 0100 .2byte 0x1 - 4950 0a6e 52 .byte 0x52 - 4951 0a6f A2000000 .4byte .LVL65 - 4952 0a73 B0000000 .4byte .LVL68 - 4953 0a77 0400 .2byte 0x4 - 4954 0a79 72 .byte 0x72 - 4955 0a7a 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 118 - - - 4956 0a7b 1F .byte 0x1f - 4957 0a7c 9F .byte 0x9f - 4958 0a7d 46010000 .4byte .LVL80 - 4959 0a81 4A010000 .4byte .LVL81 - 4960 0a85 0400 .2byte 0x4 - 4961 0a87 72 .byte 0x72 - 4962 0a88 00 .sleb128 0 - 4963 0a89 1F .byte 0x1f - 4964 0a8a 9F .byte 0x9f - 4965 0a8b 54030000 .4byte .LVL145 - 4966 0a8f 58030000 .4byte .LVL147 - 4967 0a93 0400 .2byte 0x4 - 4968 0a95 72 .byte 0x72 - 4969 0a96 00 .sleb128 0 - 4970 0a97 1F .byte 0x1f - 4971 0a98 9F .byte 0x9f - 4972 0a99 00000000 .4byte 0 - 4973 0a9d 00000000 .4byte 0 - 4974 .LLST25: - 4975 0aa1 B0000000 .4byte .LVL68 - 4976 0aa5 DE000000 .4byte .LVL72 - 4977 0aa9 0300 .2byte 0x3 - 4978 0aab 91 .byte 0x91 - 4979 0aac 847B .sleb128 -636 - 4980 0aae 4E010000 .4byte .LVL82 - 4981 0ab2 9B010000 .4byte .LVL84-1 - 4982 0ab6 0300 .2byte 0x3 - 4983 0ab8 91 .byte 0x91 - 4984 0ab9 847B .sleb128 -636 - 4985 0abb 9B010000 .4byte .LVL84-1 - 4986 0abf AA010000 .4byte .LVL86 - 4987 0ac3 0100 .2byte 0x1 - 4988 0ac5 5B .byte 0x5b - 4989 0ac6 AA010000 .4byte .LVL86 - 4990 0aca D1010000 .4byte .LVL88-1 - 4991 0ace 0300 .2byte 0x3 - 4992 0ad0 91 .byte 0x91 - 4993 0ad1 847B .sleb128 -636 - 4994 0ad3 D1010000 .4byte .LVL88-1 - 4995 0ad7 D4010000 .4byte .LVL89 - 4996 0adb 0100 .2byte 0x1 - 4997 0add 5B .byte 0x5b - 4998 0ade D4010000 .4byte .LVL89 - 4999 0ae2 E0010000 .4byte .LVL90 - 5000 0ae6 0300 .2byte 0x3 - 5001 0ae8 91 .byte 0x91 - 5002 0ae9 847B .sleb128 -636 - 5003 0aeb E0010000 .4byte .LVL90 - 5004 0aef 5C020000 .4byte .LVL103 - 5005 0af3 0100 .2byte 0x1 - 5006 0af5 5B .byte 0x5b - 5007 0af6 5C020000 .4byte .LVL103 - 5008 0afa 76020000 .4byte .LVL105 - 5009 0afe 0300 .2byte 0x3 - 5010 0b00 91 .byte 0x91 - 5011 0b01 847B .sleb128 -636 - 5012 0b03 76020000 .4byte .LVL105 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 119 - - - 5013 0b07 79020000 .4byte .LVL106-1 - 5014 0b0b 0200 .2byte 0x2 - 5015 0b0d 71 .byte 0x71 - 5016 0b0e 00 .sleb128 0 - 5017 0b0f 79020000 .4byte .LVL106-1 - 5018 0b13 80020000 .4byte .LVL108 - 5019 0b17 0100 .2byte 0x1 - 5020 0b19 5B .byte 0x5b - 5021 0b1a 80020000 .4byte .LVL108 - 5022 0b1e 8A020000 .4byte .LVL109 - 5023 0b22 0300 .2byte 0x3 - 5024 0b24 91 .byte 0x91 - 5025 0b25 847B .sleb128 -636 - 5026 0b27 8A020000 .4byte .LVL109 - 5027 0b2b 98020000 .4byte .LVL112 - 5028 0b2f 0200 .2byte 0x2 - 5029 0b31 74 .byte 0x74 - 5030 0b32 00 .sleb128 0 - 5031 0b33 98020000 .4byte .LVL112 - 5032 0b37 22030000 .4byte .LVL132 - 5033 0b3b 0300 .2byte 0x3 - 5034 0b3d 91 .byte 0x91 - 5035 0b3e 847B .sleb128 -636 - 5036 0b40 22030000 .4byte .LVL132 - 5037 0b44 26030000 .4byte .LVL133 - 5038 0b48 0100 .2byte 0x1 - 5039 0b4a 5B .byte 0x5b - 5040 0b4b 26030000 .4byte .LVL133 - 5041 0b4f 29030000 .4byte .LVL134-1 - 5042 0b53 0300 .2byte 0x3 - 5043 0b55 91 .byte 0x91 - 5044 0b56 847B .sleb128 -636 - 5045 0b58 29030000 .4byte .LVL134-1 - 5046 0b5c 38030000 .4byte .LVL137 - 5047 0b60 0100 .2byte 0x1 - 5048 0b62 5B .byte 0x5b - 5049 0b63 38030000 .4byte .LVL137 - 5050 0b67 3C030000 .4byte .LVL139 - 5051 0b6b 0300 .2byte 0x3 - 5052 0b6d 91 .byte 0x91 - 5053 0b6e 847B .sleb128 -636 - 5054 0b70 3C030000 .4byte .LVL139 - 5055 0b74 46030000 .4byte .LVL143 - 5056 0b78 0100 .2byte 0x1 - 5057 0b7a 5B .byte 0x5b - 5058 0b7b 46030000 .4byte .LVL143 - 5059 0b7f 48030000 .4byte .LVL144 - 5060 0b83 0300 .2byte 0x3 - 5061 0b85 91 .byte 0x91 - 5062 0b86 847B .sleb128 -636 - 5063 0b88 58030000 .4byte .LVL147 - 5064 0b8c 66030000 .4byte .LVL148 - 5065 0b90 0300 .2byte 0x3 - 5066 0b92 91 .byte 0x91 - 5067 0b93 847B .sleb128 -636 - 5068 0b95 00000000 .4byte 0 - 5069 0b99 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 120 - - - 5070 .LLST26: - 5071 0b9d C8000000 .4byte .LVL69 - 5072 0ba1 DE000000 .4byte .LVL72 - 5073 0ba5 0200 .2byte 0x2 - 5074 0ba7 30 .byte 0x30 - 5075 0ba8 9F .byte 0x9f - 5076 0ba9 00000000 .4byte 0 - 5077 0bad 00000000 .4byte 0 - 5078 .LLST27: - 5079 0bb1 B4020000 .4byte .LVL114 - 5080 0bb5 B8020000 .4byte .LVL115 - 5081 0bb9 0100 .2byte 0x1 - 5082 0bbb 55 .byte 0x55 - 5083 0bbc B8020000 .4byte .LVL115 - 5084 0bc0 BC020000 .4byte .LVL116 - 5085 0bc4 0800 .2byte 0x8 - 5086 0bc6 70 .byte 0x70 - 5087 0bc7 00 .sleb128 0 - 5088 0bc8 38 .byte 0x38 - 5089 0bc9 24 .byte 0x24 - 5090 0bca 71 .byte 0x71 - 5091 0bcb 00 .sleb128 0 - 5092 0bcc 21 .byte 0x21 - 5093 0bcd 9F .byte 0x9f - 5094 0bce BC020000 .4byte .LVL116 - 5095 0bd2 CC020000 .4byte .LVL119 - 5096 0bd6 1400 .2byte 0x14 - 5097 0bd8 91 .byte 0x91 - 5098 0bd9 867B .sleb128 -634 - 5099 0bdb 94 .byte 0x94 - 5100 0bdc 01 .byte 0x1 - 5101 0bdd 08 .byte 0x8 - 5102 0bde FF .byte 0xff - 5103 0bdf 1A .byte 0x1a - 5104 0be0 38 .byte 0x38 - 5105 0be1 24 .byte 0x24 - 5106 0be2 91 .byte 0x91 - 5107 0be3 857B .sleb128 -635 - 5108 0be5 94 .byte 0x94 - 5109 0be6 01 .byte 0x1 - 5110 0be7 08 .byte 0x8 - 5111 0be8 FF .byte 0xff - 5112 0be9 1A .byte 0x1a - 5113 0bea 21 .byte 0x21 - 5114 0beb 9F .byte 0x9f - 5115 0bec CC020000 .4byte .LVL119 - 5116 0bf0 0C030000 .4byte .LVL128 - 5117 0bf4 0100 .2byte 0x1 - 5118 0bf6 55 .byte 0x55 - 5119 0bf7 0C030000 .4byte .LVL128 - 5120 0bfb 22030000 .4byte .LVL132 - 5121 0bff 1400 .2byte 0x14 - 5122 0c01 91 .byte 0x91 - 5123 0c02 867B .sleb128 -634 - 5124 0c04 94 .byte 0x94 - 5125 0c05 01 .byte 0x1 - 5126 0c06 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 121 - - - 5127 0c07 FF .byte 0xff - 5128 0c08 1A .byte 0x1a - 5129 0c09 38 .byte 0x38 - 5130 0c0a 24 .byte 0x24 - 5131 0c0b 91 .byte 0x91 - 5132 0c0c 857B .sleb128 -635 - 5133 0c0e 94 .byte 0x94 - 5134 0c0f 01 .byte 0x1 - 5135 0c10 08 .byte 0x8 - 5136 0c11 FF .byte 0xff - 5137 0c12 1A .byte 0x1a - 5138 0c13 21 .byte 0x21 - 5139 0c14 9F .byte 0x9f - 5140 0c15 00000000 .4byte 0 - 5141 0c19 00000000 .4byte 0 - 5142 .LLST28: - 5143 0c1d B8020000 .4byte .LVL115 - 5144 0c21 CC020000 .4byte .LVL119 - 5145 0c25 0100 .2byte 0x1 - 5146 0c27 55 .byte 0x55 - 5147 0c28 D2020000 .4byte .LVL120 - 5148 0c2c EE020000 .4byte .LVL125 - 5149 0c30 0100 .2byte 0x1 - 5150 0c32 54 .byte 0x54 - 5151 0c33 EE020000 .4byte .LVL125 - 5152 0c37 F4020000 .4byte .LVL126 - 5153 0c3b 0A00 .2byte 0xa - 5154 0c3d 7B .byte 0x7b - 5155 0c3e 00 .sleb128 0 - 5156 0c3f 38 .byte 0x38 - 5157 0c40 24 .byte 0x24 - 5158 0c41 75 .byte 0x75 - 5159 0c42 00 .sleb128 0 - 5160 0c43 22 .byte 0x22 - 5161 0c44 38 .byte 0x38 - 5162 0c45 24 .byte 0x24 - 5163 0c46 9F .byte 0x9f - 5164 0c47 F4020000 .4byte .LVL126 - 5165 0c4b 12030000 .4byte .LVL129 - 5166 0c4f 0100 .2byte 0x1 - 5167 0c51 51 .byte 0x51 - 5168 0c52 12030000 .4byte .LVL129 - 5169 0c56 1A030000 .4byte .LVL130 - 5170 0c5a 1D00 .2byte 0x1d - 5171 0c5c 91 .byte 0x91 - 5172 0c5d 867B .sleb128 -634 - 5173 0c5f 94 .byte 0x94 - 5174 0c60 01 .byte 0x1 - 5175 0c61 08 .byte 0x8 - 5176 0c62 FF .byte 0xff - 5177 0c63 1A .byte 0x1a - 5178 0c64 38 .byte 0x38 - 5179 0c65 24 .byte 0x24 - 5180 0c66 91 .byte 0x91 - 5181 0c67 857B .sleb128 -635 - 5182 0c69 94 .byte 0x94 - 5183 0c6a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 122 - - - 5184 0c6b 08 .byte 0x8 - 5185 0c6c FF .byte 0xff - 5186 0c6d 1A .byte 0x1a - 5187 0c6e 21 .byte 0x21 - 5188 0c6f 7B .byte 0x7b - 5189 0c70 808009 .sleb128 147456 - 5190 0c73 38 .byte 0x38 - 5191 0c74 24 .byte 0x24 - 5192 0c75 22 .byte 0x22 - 5193 0c76 35 .byte 0x35 - 5194 0c77 24 .byte 0x24 - 5195 0c78 9F .byte 0x9f - 5196 0c79 00000000 .4byte 0 - 5197 0c7d 00000000 .4byte 0 - 5198 .LLST29: - 5199 0c81 E4020000 .4byte .LVL124 - 5200 0c85 F4020000 .4byte .LVL126 - 5201 0c89 0100 .2byte 0x1 - 5202 0c8b 51 .byte 0x51 - 5203 0c8c FE020000 .4byte .LVL127 - 5204 0c90 12030000 .4byte .LVL129 - 5205 0c94 0100 .2byte 0x1 - 5206 0c96 53 .byte 0x53 - 5207 0c97 12030000 .4byte .LVL129 - 5208 0c9b 1A030000 .4byte .LVL130 - 5209 0c9f 0100 .2byte 0x1 - 5210 0ca1 51 .byte 0x51 - 5211 0ca2 1A030000 .4byte .LVL130 - 5212 0ca6 22030000 .4byte .LVL132 - 5213 0caa 0100 .2byte 0x1 - 5214 0cac 53 .byte 0x53 - 5215 0cad 00000000 .4byte 0 - 5216 0cb1 00000000 .4byte 0 - 5217 .LLST30: - 5218 0cb5 B8020000 .4byte .LVL115 - 5219 0cb9 CC020000 .4byte .LVL119 - 5220 0cbd 0100 .2byte 0x1 - 5221 0cbf 55 .byte 0x55 - 5222 0cc0 00000000 .4byte 0 - 5223 0cc4 00000000 .4byte 0 - 5224 .LLST31: - 5225 0cc8 B8020000 .4byte .LVL115 - 5226 0ccc BC020000 .4byte .LVL116 - 5227 0cd0 0200 .2byte 0x2 - 5228 0cd2 30 .byte 0x30 - 5229 0cd3 9F .byte 0x9f - 5230 0cd4 C8020000 .4byte .LVL118 - 5231 0cd8 CC020000 .4byte .LVL119 - 5232 0cdc 0100 .2byte 0x1 - 5233 0cde 53 .byte 0x53 - 5234 0cdf 00000000 .4byte 0 - 5235 0ce3 00000000 .4byte 0 - 5236 .LLST32: - 5237 0ce7 B8020000 .4byte .LVL115 - 5238 0ceb BC020000 .4byte .LVL116 - 5239 0cef 0200 .2byte 0x2 - 5240 0cf1 40 .byte 0x40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 123 - - - 5241 0cf2 9F .byte 0x9f - 5242 0cf3 BC020000 .4byte .LVL116 - 5243 0cf7 C4020000 .4byte .LVL117 - 5244 0cfb 0300 .2byte 0x3 - 5245 0cfd 72 .byte 0x72 - 5246 0cfe 7F .sleb128 -1 - 5247 0cff 9F .byte 0x9f - 5248 0d00 C4020000 .4byte .LVL117 - 5249 0d04 C8020000 .4byte .LVL118 - 5250 0d08 0100 .2byte 0x1 - 5251 0d0a 52 .byte 0x52 - 5252 0d0b 00000000 .4byte 0 - 5253 0d0f 00000000 .4byte 0 - 5254 .LLST33: - 5255 0d13 D2020000 .4byte .LVL120 - 5256 0d17 D8020000 .4byte .LVL121 - 5257 0d1b 0400 .2byte 0x4 - 5258 0d1d 0A .byte 0xa - 5259 0d1e 0001 .2byte 0x100 - 5260 0d20 9F .byte 0x9f - 5261 0d21 DA020000 .4byte .LVL122 - 5262 0d25 F4020000 .4byte .LVL126 - 5263 0d29 0100 .2byte 0x1 - 5264 0d2b 52 .byte 0x52 - 5265 0d2c 00000000 .4byte 0 - 5266 0d30 00000000 .4byte 0 - 5267 .LLST34: - 5268 0d34 D2020000 .4byte .LVL120 - 5269 0d38 EE020000 .4byte .LVL125 - 5270 0d3c 0100 .2byte 0x1 - 5271 0d3e 54 .byte 0x54 - 5272 0d3f EE020000 .4byte .LVL125 - 5273 0d43 0C030000 .4byte .LVL128 - 5274 0d47 0A00 .2byte 0xa - 5275 0d49 7B .byte 0x7b - 5276 0d4a 00 .sleb128 0 - 5277 0d4b 38 .byte 0x38 - 5278 0d4c 24 .byte 0x24 - 5279 0d4d 75 .byte 0x75 - 5280 0d4e 00 .sleb128 0 - 5281 0d4f 22 .byte 0x22 - 5282 0d50 38 .byte 0x38 - 5283 0d51 24 .byte 0x24 - 5284 0d52 9F .byte 0x9f - 5285 0d53 0C030000 .4byte .LVL128 - 5286 0d57 1A030000 .4byte .LVL130 - 5287 0d5b 1B00 .2byte 0x1b - 5288 0d5d 91 .byte 0x91 - 5289 0d5e 867B .sleb128 -634 - 5290 0d60 94 .byte 0x94 - 5291 0d61 01 .byte 0x1 - 5292 0d62 08 .byte 0x8 - 5293 0d63 FF .byte 0xff - 5294 0d64 1A .byte 0x1a - 5295 0d65 38 .byte 0x38 - 5296 0d66 24 .byte 0x24 - 5297 0d67 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 124 - - - 5298 0d68 857B .sleb128 -635 - 5299 0d6a 94 .byte 0x94 - 5300 0d6b 01 .byte 0x1 - 5301 0d6c 08 .byte 0x8 - 5302 0d6d FF .byte 0xff - 5303 0d6e 1A .byte 0x1a - 5304 0d6f 21 .byte 0x21 - 5305 0d70 7B .byte 0x7b - 5306 0d71 00 .sleb128 0 - 5307 0d72 38 .byte 0x38 - 5308 0d73 24 .byte 0x24 - 5309 0d74 22 .byte 0x22 - 5310 0d75 38 .byte 0x38 - 5311 0d76 24 .byte 0x24 - 5312 0d77 9F .byte 0x9f - 5313 0d78 00000000 .4byte 0 - 5314 0d7c 00000000 .4byte 0 - 5315 .LLST35: - 5316 0d80 D2020000 .4byte .LVL120 - 5317 0d84 D8020000 .4byte .LVL121 - 5318 0d88 0200 .2byte 0x2 - 5319 0d8a 30 .byte 0x30 - 5320 0d8b 9F .byte 0x9f - 5321 0d8c E0020000 .4byte .LVL123 - 5322 0d90 F4020000 .4byte .LVL126 - 5323 0d94 0100 .2byte 0x1 - 5324 0d96 51 .byte 0x51 - 5325 0d97 00000000 .4byte 0 - 5326 0d9b 00000000 .4byte 0 - 5327 .LLST36: - 5328 0d9f DE000000 .4byte .LVL72 - 5329 0da3 28010000 .4byte .LVL77 - 5330 0da7 0400 .2byte 0x4 - 5331 0da9 91 .byte 0x91 - 5332 0daa 807B .sleb128 -640 - 5333 0dac 9F .byte 0x9f - 5334 0dad 28010000 .4byte .LVL77 - 5335 0db1 33010000 .4byte .LVL78-1 - 5336 0db5 0100 .2byte 0x1 - 5337 0db7 50 .byte 0x50 - 5338 0db8 33010000 .4byte .LVL78-1 - 5339 0dbc 34010000 .4byte .LVL78 - 5340 0dc0 0400 .2byte 0x4 - 5341 0dc2 91 .byte 0x91 - 5342 0dc3 807B .sleb128 -640 - 5343 0dc5 9F .byte 0x9f - 5344 0dc6 00000000 .4byte 0 - 5345 0dca 00000000 .4byte 0 - 5346 .LLST37: - 5347 0dce DE000000 .4byte .LVL72 - 5348 0dd2 34010000 .4byte .LVL78 - 5349 0dd6 0100 .2byte 0x1 - 5350 0dd8 55 .byte 0x55 - 5351 0dd9 00000000 .4byte 0 - 5352 0ddd 00000000 .4byte 0 - 5353 .LLST38: - 5354 0de1 08010000 .4byte .LVL74 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 125 - - - 5355 0de5 18010000 .4byte .LVL76 - 5356 0de9 0100 .2byte 0x1 - 5357 0deb 53 .byte 0x53 - 5358 0dec 00000000 .4byte 0 - 5359 0df0 00000000 .4byte 0 - 5360 .LLST39: - 5361 0df4 FA000000 .4byte .LVL73 - 5362 0df8 28010000 .4byte .LVL77 - 5363 0dfc 0400 .2byte 0x4 - 5364 0dfe 91 .byte 0x91 - 5365 0dff 807B .sleb128 -640 - 5366 0e01 9F .byte 0x9f - 5367 0e02 28010000 .4byte .LVL77 - 5368 0e06 33010000 .4byte .LVL78-1 - 5369 0e0a 0100 .2byte 0x1 - 5370 0e0c 50 .byte 0x50 - 5371 0e0d 33010000 .4byte .LVL78-1 - 5372 0e11 34010000 .4byte .LVL78 - 5373 0e15 0400 .2byte 0x4 - 5374 0e17 91 .byte 0x91 - 5375 0e18 807B .sleb128 -640 - 5376 0e1a 9F .byte 0x9f - 5377 0e1b 00000000 .4byte 0 - 5378 0e1f 00000000 .4byte 0 - 5379 .LLST40: - 5380 0e23 08010000 .4byte .LVL74 - 5381 0e27 14010000 .4byte .LVL75 - 5382 0e2b 0100 .2byte 0x1 - 5383 0e2d 52 .byte 0x52 - 5384 0e2e 00000000 .4byte 0 - 5385 0e32 00000000 .4byte 0 - 5386 .LLST41: - 5387 0e36 00000000 .4byte .LFB59 - 5388 0e3a 02000000 .4byte .LCFI4 - 5389 0e3e 0200 .2byte 0x2 - 5390 0e40 7D .byte 0x7d - 5391 0e41 00 .sleb128 0 - 5392 0e42 02000000 .4byte .LCFI4 - 5393 0e46 04000000 .4byte .LCFI5 - 5394 0e4a 0200 .2byte 0x2 - 5395 0e4c 7D .byte 0x7d - 5396 0e4d 08 .sleb128 8 - 5397 0e4e 04000000 .4byte .LCFI5 - 5398 0e52 80000000 .4byte .LFE59 - 5399 0e56 0300 .2byte 0x3 - 5400 0e58 7D .byte 0x7d - 5401 0e59 A802 .sleb128 296 - 5402 0e5b 00000000 .4byte 0 - 5403 0e5f 00000000 .4byte 0 - 5404 .LLST42: - 5405 0e63 38000000 .4byte .LVL157 - 5406 0e67 3E000000 .4byte .LVL158 - 5407 0e6b 0700 .2byte 0x7 - 5408 0e6d 73 .byte 0x73 - 5409 0e6e 00 .sleb128 0 - 5410 0e6f 70 .byte 0x70 - 5411 0e70 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 126 - - - 5412 0e71 1C .byte 0x1c - 5413 0e72 1F .byte 0x1f - 5414 0e73 9F .byte 0x9f - 5415 0e74 00000000 .4byte 0 - 5416 0e78 00000000 .4byte 0 - 5417 .LLST43: - 5418 0e7c 50000000 .4byte .LVL160 - 5419 0e80 5E000000 .4byte .LVL161 - 5420 0e84 0100 .2byte 0x1 - 5421 0e86 50 .byte 0x50 - 5422 0e87 00000000 .4byte 0 - 5423 0e8b 00000000 .4byte 0 - 5424 .LLST44: - 5425 0e8f 24000000 .4byte .LVL153 - 5426 0e93 28000000 .4byte .LVL154 - 5427 0e97 0100 .2byte 0x1 - 5428 0e99 51 .byte 0x51 - 5429 0e9a 00000000 .4byte 0 - 5430 0e9e 00000000 .4byte 0 - 5431 .LLST45: - 5432 0ea2 24000000 .4byte .LVL153 - 5433 0ea6 28000000 .4byte .LVL154 - 5434 0eaa 0200 .2byte 0x2 - 5435 0eac 30 .byte 0x30 - 5436 0ead 9F .byte 0x9f - 5437 0eae 28000000 .4byte .LVL154 - 5438 0eb2 30000000 .4byte .LVL155 - 5439 0eb6 0100 .2byte 0x1 - 5440 0eb8 53 .byte 0x53 - 5441 0eb9 32000000 .4byte .LVL156 - 5442 0ebd 3E000000 .4byte .LVL158 - 5443 0ec1 0100 .2byte 0x1 - 5444 0ec3 53 .byte 0x53 - 5445 0ec4 00000000 .4byte 0 - 5446 0ec8 00000000 .4byte 0 - 5447 .LLST46: - 5448 0ecc 00000000 .4byte .LFB61 - 5449 0ed0 02000000 .4byte .LCFI6 - 5450 0ed4 0200 .2byte 0x2 - 5451 0ed6 7D .byte 0x7d - 5452 0ed7 00 .sleb128 0 - 5453 0ed8 02000000 .4byte .LCFI6 - 5454 0edc 30000000 .4byte .LFE61 - 5455 0ee0 0200 .2byte 0x2 - 5456 0ee2 7D .byte 0x7d - 5457 0ee3 08 .sleb128 8 - 5458 0ee4 00000000 .4byte 0 - 5459 0ee8 00000000 .4byte 0 - 5460 .LLST47: - 5461 0eec 00000000 .4byte .LFB66 - 5462 0ef0 02000000 .4byte .LCFI7 - 5463 0ef4 0200 .2byte 0x2 - 5464 0ef6 7D .byte 0x7d - 5465 0ef7 00 .sleb128 0 - 5466 0ef8 02000000 .4byte .LCFI7 - 5467 0efc 08000000 .4byte .LCFI8 - 5468 0f00 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 127 - - - 5469 0f02 7D .byte 0x7d - 5470 0f03 10 .sleb128 16 - 5471 0f04 08000000 .4byte .LCFI8 - 5472 0f08 34000000 .4byte .LFE66 - 5473 0f0c 0300 .2byte 0x3 - 5474 0f0e 7D .byte 0x7d - 5475 0f0f 9002 .sleb128 272 - 5476 0f11 00000000 .4byte 0 - 5477 0f15 00000000 .4byte 0 - 5478 .LLST48: - 5479 0f19 00000000 .4byte .LVL168 - 5480 0f1d 22000000 .4byte .LVL172 - 5481 0f21 0100 .2byte 0x1 - 5482 0f23 50 .byte 0x50 - 5483 0f24 22000000 .4byte .LVL172 - 5484 0f28 34000000 .4byte .LFE66 - 5485 0f2c 0400 .2byte 0x4 - 5486 0f2e F3 .byte 0xf3 - 5487 0f2f 01 .uleb128 0x1 - 5488 0f30 50 .byte 0x50 - 5489 0f31 9F .byte 0x9f - 5490 0f32 00000000 .4byte 0 - 5491 0f36 00000000 .4byte 0 - 5492 .LLST49: - 5493 0f3a 00000000 .4byte .LVL168 - 5494 0f3e 28000000 .4byte .LVL173 - 5495 0f42 0100 .2byte 0x1 - 5496 0f44 51 .byte 0x51 - 5497 0f45 28000000 .4byte .LVL173 - 5498 0f49 2A000000 .4byte .LVL174 - 5499 0f4d 0900 .2byte 0x9 - 5500 0f4f 91 .byte 0x91 - 5501 0f50 00 .sleb128 0 - 5502 0f51 70 .byte 0x70 - 5503 0f52 00 .sleb128 0 - 5504 0f53 22 .byte 0x22 - 5505 0f54 0A .byte 0xa - 5506 0f55 1001 .2byte 0x110 - 5507 0f57 1C .byte 0x1c - 5508 0f58 2A000000 .4byte .LVL174 - 5509 0f5c 34000000 .4byte .LFE66 - 5510 0f60 0400 .2byte 0x4 - 5511 0f62 F3 .byte 0xf3 - 5512 0f63 01 .uleb128 0x1 - 5513 0f64 51 .byte 0x51 - 5514 0f65 9F .byte 0x9f - 5515 0f66 00000000 .4byte 0 - 5516 0f6a 00000000 .4byte 0 - 5517 .LLST51: - 5518 0f6e 0C000000 .4byte .LVL169 - 5519 0f72 2C000000 .4byte .LVL175 - 5520 0f76 0100 .2byte 0x1 - 5521 0f78 52 .byte 0x52 - 5522 0f79 2C000000 .4byte .LVL175 - 5523 0f7d 2F000000 .4byte .LVL176-1 - 5524 0f81 0100 .2byte 0x1 - 5525 0f83 51 .byte 0x51 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 128 - - - 5526 0f84 2F000000 .4byte .LVL176-1 - 5527 0f88 34000000 .4byte .LFE66 - 5528 0f8c 0A00 .2byte 0xa - 5529 0f8e F3 .byte 0xf3 - 5530 0f8f 01 .uleb128 0x1 - 5531 0f90 50 .byte 0x50 - 5532 0f91 09 .byte 0x9 - 5533 0f92 F4 .byte 0xf4 - 5534 0f93 24 .byte 0x24 - 5535 0f94 09 .byte 0x9 - 5536 0f95 FC .byte 0xfc - 5537 0f96 25 .byte 0x25 - 5538 0f97 9F .byte 0x9f - 5539 0f98 00000000 .4byte 0 - 5540 0f9c 00000000 .4byte 0 - 5541 .LLST52: - 5542 0fa0 10000000 .4byte .LVL170 - 5543 0fa4 12000000 .4byte .LVL171 - 5544 0fa8 0200 .2byte 0x2 - 5545 0faa 30 .byte 0x30 - 5546 0fab 9F .byte 0x9f - 5547 0fac 00000000 .4byte 0 - 5548 0fb0 00000000 .4byte 0 - 5549 .section .debug_aranges,"",%progbits - 5550 0000 4C000000 .4byte 0x4c - 5551 0004 0200 .2byte 0x2 - 5552 0006 00000000 .4byte .Ldebug_info0 - 5553 000a 04 .byte 0x4 - 5554 000b 00 .byte 0 - 5555 000c 0000 .2byte 0 - 5556 000e 0000 .2byte 0 - 5557 0010 00000000 .4byte .LFB62 - 5558 0014 02000000 .4byte .LFE62-.LFB62 - 5559 0018 00000000 .4byte .LFB69 - 5560 001c 8C000000 .4byte .LFE69-.LFB69 - 5561 0020 00000000 .4byte .LFB70 - 5562 0024 84000000 .4byte .LFE70-.LFB70 - 5563 0028 00000000 .4byte .LFB64 - 5564 002c 84030000 .4byte .LFE64-.LFB64 - 5565 0030 00000000 .4byte .LFB59 - 5566 0034 80000000 .4byte .LFE59-.LFB59 - 5567 0038 00000000 .4byte .LFB61 - 5568 003c 30000000 .4byte .LFE61-.LFB61 - 5569 0040 00000000 .4byte .LFB66 - 5570 0044 34000000 .4byte .LFE66-.LFB66 - 5571 0048 00000000 .4byte 0 - 5572 004c 00000000 .4byte 0 - 5573 .section .debug_ranges,"",%progbits - 5574 .Ldebug_ranges0: - 5575 0000 B0000000 .4byte .LBB22 - 5576 0004 DE000000 .4byte .LBE22 - 5577 0008 46010000 .4byte .LBB36 - 5578 000c 4C030000 .4byte .LBE36 - 5579 0010 00000000 .4byte 0 - 5580 0014 00000000 .4byte 0 - 5581 0018 00000000 .4byte .LFB62 - 5582 001c 02000000 .4byte .LFE62 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 129 - - - 5583 0020 00000000 .4byte .LFB69 - 5584 0024 8C000000 .4byte .LFE69 - 5585 0028 00000000 .4byte .LFB70 - 5586 002c 84000000 .4byte .LFE70 - 5587 0030 00000000 .4byte .LFB64 - 5588 0034 84030000 .4byte .LFE64 - 5589 0038 00000000 .4byte .LFB59 - 5590 003c 80000000 .4byte .LFE59 - 5591 0040 00000000 .4byte .LFB61 - 5592 0044 30000000 .4byte .LFE61 - 5593 0048 00000000 .4byte .LFB66 - 5594 004c 34000000 .4byte .LFE66 - 5595 0050 00000000 .4byte 0 - 5596 0054 00000000 .4byte 0 - 5597 .section .debug_line,"",%progbits - 5598 .Ldebug_line0: - 5599 0000 D2030000 .section .debug_str,"MS",%progbits,1 - 5599 02002401 - 5599 00000201 - 5599 FB0E0D00 - 5599 01010101 - 5600 .LASF33: - 5601 0000 76616C69 .ascii "valid\000" - 5601 6400 - 5602 .LASF39: - 5603 0006 424C5F57 .ascii "BL_WritePacket\000" - 5603 72697465 - 5603 5061636B - 5603 657400 - 5604 .LASF28: - 5605 0015 61707049 .ascii "appId\000" - 5605 6400 - 5606 .LASF31: - 5607 001b 72657375 .ascii "result\000" - 5607 6C7400 - 5608 .LASF66: - 5609 0022 746D7053 .ascii "tmpStatus\000" - 5609 74617475 - 5609 7300 - 5610 .LASF75: - 5611 002c 62617365 .ascii "baseAddr\000" - 5611 41646472 - 5611 00 - 5612 .LASF84: - 5613 0035 4379536F .ascii "CySoftwareReset\000" - 5613 66747761 - 5613 72655265 - 5613 73657400 - 5614 .LASF51: - 5615 0045 706B7453 .ascii "pktSize\000" - 5615 697A6500 - 5616 .LASF44: - 5617 004d 61707041 .ascii "appAddr\000" - 5617 64647200 - 5618 .LASF73: - 5619 0055 726F7744 .ascii "rowData\000" - 5619 61746100 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 130 - - - 5620 .LASF2: - 5621 005d 73686F72 .ascii "short int\000" - 5621 7420696E - 5621 7400 - 5622 .LASF65: - 5623 0067 424C5F66 .ascii "BL_flashBuffer\000" - 5623 6C617368 - 5623 42756666 - 5623 657200 - 5624 .LASF48: - 5625 0076 61636B43 .ascii "ackCode\000" - 5625 6F646500 - 5626 .LASF21: - 5627 007e 73697A65 .ascii "sizetype\000" - 5627 74797065 - 5627 00 - 5628 .LASF59: - 5629 0087 73746172 .ascii "startRow\000" - 5629 74526F77 - 5629 00 - 5630 .LASF58: - 5631 0090 62746C64 .ascii "btldrData\000" - 5631 72446174 - 5631 6100 - 5632 .LASF52: - 5633 009a 64617461 .ascii "dataOffset\000" - 5633 4F666673 - 5633 657400 - 5634 .LASF79: - 5635 00a5 424C5F53 .ascii "BL_SizeBytesAccess\000" - 5635 697A6542 - 5635 79746573 - 5635 41636365 - 5635 737300 - 5636 .LASF61: - 5637 00b8 42746C64 .ascii "BtldrVersion\000" - 5637 72566572 - 5637 73696F6E - 5637 00 - 5638 .LASF86: - 5639 00c5 55534246 .ascii "USBFS_CyBtldrCommWrite\000" - 5639 535F4379 - 5639 42746C64 - 5639 72436F6D - 5639 6D577269 - 5640 .LASF82: - 5641 00dc 6D656D63 .ascii "memcpy\000" - 5641 707900 - 5642 .LASF71: - 5643 00e3 72756E54 .ascii "runType\000" - 5643 79706500 - 5644 .LASF11: - 5645 00eb 75696E74 .ascii "uint16\000" - 5645 313600 - 5646 .LASF41: - 5647 00f2 63686563 .ascii "checksum\000" - 5647 6B73756D - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 131 - - - 5647 00 - 5648 .LASF32: - 5649 00fb 424C5F56 .ascii "BL_ValidateBootloadable\000" - 5649 616C6964 - 5649 61746542 - 5649 6F6F746C - 5649 6F616461 - 5650 .LASF94: - 5651 0113 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 5651 43534932 - 5651 53445C73 - 5651 6F667477 - 5651 6172655C - 5652 0142 6E00 .ascii "n\000" - 5653 .LASF10: - 5654 0144 75696E74 .ascii "uint8\000" - 5654 3800 - 5655 .LASF96: - 5656 014a 43795365 .ascii "CySetTemp\000" - 5656 7454656D - 5656 7000 - 5657 .LASF67: - 5658 0154 424C5F53 .ascii "BL_Start\000" - 5658 74617274 - 5658 00 - 5659 .LASF20: - 5660 015d 426F6F74 .ascii "BootLoaderVersion\000" - 5660 4C6F6164 - 5660 65725665 - 5660 7273696F - 5660 6E00 - 5661 .LASF0: - 5662 016f 7369676E .ascii "signed char\000" - 5662 65642063 - 5662 68617200 - 5663 .LASF13: - 5664 017b 666C6F61 .ascii "float\000" - 5664 7400 - 5665 .LASF6: - 5666 0181 6C6F6E67 .ascii "long long int\000" - 5666 206C6F6E - 5666 6720696E - 5666 7400 - 5667 .LASF81: - 5668 018f 6D656D73 .ascii "memset\000" - 5668 657400 - 5669 .LASF15: - 5670 0196 63686172 .ascii "char\000" - 5670 00 - 5671 .LASF25: - 5672 019b 424C5F43 .ascii "BL_Calc8BitEepromSum\000" - 5672 616C6338 - 5672 42697445 - 5672 6570726F - 5672 6D53756D - 5673 .LASF72: - 5674 01b0 666C7341 .ascii "flsAddr\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 132 - - - 5674 64647200 - 5675 .LASF70: - 5676 01b8 61646472 .ascii "address\000" - 5676 65737300 - 5677 .LASF35: - 5678 01c0 63757242 .ascii "curByte\000" - 5678 79746500 - 5679 .LASF64: - 5680 01c8 746D7049 .ascii "tmpIndex\000" - 5680 6E646578 - 5680 00 - 5681 .LASF46: - 5682 01d1 6E756D62 .ascii "numberRead\000" - 5682 65725265 - 5682 616400 - 5683 .LASF34: - 5684 01dc 63616C63 .ascii "calcedChecksum\000" - 5684 65644368 - 5684 65636B73 - 5684 756D00 - 5685 .LASF43: - 5686 01eb 424C5F48 .ascii "BL_HostLink\000" - 5686 6F73744C - 5686 696E6B00 - 5687 .LASF55: - 5688 01f7 636F6D6D .ascii "communicationState\000" - 5688 756E6963 - 5688 6174696F - 5688 6E537461 - 5688 746500 - 5689 .LASF92: - 5690 020a 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 5690 4320342E - 5690 372E3320 - 5690 32303133 - 5690 30333132 - 5691 023d 616E6368 .ascii "anch revision 196615]\000" - 5691 20726576 - 5691 6973696F - 5691 6E203139 - 5691 36363135 - 5692 .LASF93: - 5693 0253 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\BL.c\000" - 5693 6E657261 - 5693 7465645F - 5693 536F7572 - 5693 63655C50 - 5694 .LASF54: - 5695 0271 636C6561 .ascii "clearedMetaData\000" - 5695 7265644D - 5695 65746144 - 5695 61746100 - 5696 .LASF29: - 5697 0281 6669656C .ascii "fieldPtr\000" - 5697 64507472 - 5697 00 - 5698 .LASF53: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 133 - - - 5699 028a 74696D65 .ascii "timeOutCnt\000" - 5699 4F757443 - 5699 6E7400 - 5700 .LASF95: - 5701 0295 424C5F4C .ascii "BL_LaunchApplication\000" - 5701 61756E63 - 5701 68417070 - 5701 6C696361 - 5701 74696F6E - 5702 .LASF23: - 5703 02aa 73746172 .ascii "start\000" - 5703 7400 - 5704 .LASF1: - 5705 02b0 756E7369 .ascii "unsigned char\000" - 5705 676E6564 - 5705 20636861 - 5705 7200 - 5706 .LASF57: - 5707 02be 64617461 .ascii "dataBuffer\000" - 5707 42756666 - 5707 657200 - 5708 .LASF83: - 5709 02c9 43794545 .ascii "CyEEPROM_Start\000" - 5709 50524F4D - 5709 5F537461 - 5709 727400 - 5710 .LASF89: - 5711 02d8 43794861 .ascii "CyHalt\000" - 5711 6C7400 - 5712 .LASF9: - 5713 02df 696E7433 .ascii "int32_t\000" - 5713 325F7400 - 5714 .LASF7: - 5715 02e7 6C6F6E67 .ascii "long long unsigned int\000" - 5715 206C6F6E - 5715 6720756E - 5715 7369676E - 5715 65642069 - 5716 .LASF49: - 5717 02fe 706B7443 .ascii "pktChecksum\000" - 5717 6865636B - 5717 73756D00 - 5718 .LASF68: - 5719 030a 43794274 .ascii "CyBtldr_CheckLaunch\000" - 5719 6C64725F - 5719 43686563 - 5719 6B4C6175 - 5719 6E636800 - 5720 .LASF16: - 5721 031e 63797374 .ascii "cystatus\000" - 5721 61747573 - 5721 00 - 5722 .LASF42: - 5723 0327 424C5F4C .ascii "BL_LaunchBootloadable\000" - 5723 61756E63 - 5723 68426F6F - 5723 746C6F61 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccjItj5m.s page 134 - - - 5723 6461626C - 5724 .LASF36: - 5725 033d 424C5F43 .ascii "BL_CalcPacketChecksum\000" - 5725 616C6350 - 5725 61636B65 - 5725 74436865 - 5725 636B7375 - 5726 .LASF30: - 5727 0353 6669656C .ascii "fieldSize\000" - 5727 6453697A - 5727 6500 - 5728 .LASF40: - 5729 035d 73746174 .ascii "status\000" - 5729 757300 - 5730 .LASF62: - 5731 0364 726F774E .ascii "rowNum\000" - 5731 756D00 - 5732 .LASF56: - 5733 036b 7061636B .ascii "packetBuffer\000" - 5733 65744275 - 5733 66666572 - 5733 00 - 5734 .LASF38: - 5735 0378 424C5F43 .ascii "BL_Calc8BitFlashSum\000" - 5735 616C6338 - 5735 42697446 - 5735 6C617368 - 5735 53756D00 - 5736 .LASF78: - 5737 038c 424C5F53 .ascii "BL_SizeBytes\000" - 5737 697A6542 - 5737 79746573 - 5737 00 - 5738 .LASF4: - 5739 0399 6C6F6E67 .ascii "long int\000" - 5739 20696E74 - 5739 00 - 5740 .LASF50: - 5741 03a2 72656164 .ascii "readStat\000" - 5741 53746174 - 5741 00 - 5742 .LASF26: - 5743 03ab 424C5F47 .ascii "BL_GetMetadata\000" - 5743 65744D65 - 5743 74616461 - 5743 746100 - 5744 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z!a2f4!llAh!a8B2aILUYsMoXbyIJI`gx3pq2>D7E#&e&L?@*zZ5#fiz zLE#s|uY`OD3;ksXbA{7{CBhlPdBR1)8sSReHsLkG9m1W$JB7Q2_X{5o@-;7v=P4my z@aMN{11em2)_{W3v1>(g?t$d$N_q5Nkd-@8J2Na%>S^PSgy#!ugnU~H?bizVb`;9JLcS1%@(+Z35enr8gg+Pd3!f716Y>Ql zydOR!JSKci$d`)n{&P?`B>Y6O$={M?GJwWT$|5VT_lW9rKa|edZtkZbv^KhNAkM7t`GH=Q3kyvj>jC~ zd=hai78dco3H8|bd%bcWb%2Cl{`(mH+)KjGFG-Z=^LK|w+K=)&KFB&g#OsxOT`%Ii bROBWSes2@`E)xEq5cx@x<45G9B - 16:.\Generated_Source\PSoC5/Cm3Start.c **** #include "cydevice_trm.h" - 17:.\Generated_Source\PSoC5/Cm3Start.c **** #include "cytypes.h" - 18:.\Generated_Source\PSoC5/Cm3Start.c **** #include "cyfitter_cfg.h" - 19:.\Generated_Source\PSoC5/Cm3Start.c **** #include "CyLib.h" - 20:.\Generated_Source\PSoC5/Cm3Start.c **** #include "CyDmac.h" - 21:.\Generated_Source\PSoC5/Cm3Start.c **** #include "cyfitter.h" - 22:.\Generated_Source\PSoC5/Cm3Start.c **** - 23:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NUM_INTERRUPTS (32u) - 24:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) - 25:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NUM_ROM_VECTORS (4u) - 26:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR) - 27:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL) - 28:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */ - 29:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NV - 30:.\Generated_Source\PSoC5/Cm3Start.c **** #define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must - 31:.\Generated_Source\PSoC5/Cm3Start.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 2 - - - 32:.\Generated_Source\PSoC5/Cm3Start.c **** - 33:.\Generated_Source\PSoC5/Cm3Start.c **** /* Extern functions */ - 34:.\Generated_Source\PSoC5/Cm3Start.c **** extern void CyBtldr_CheckLaunch(void); - 35:.\Generated_Source\PSoC5/Cm3Start.c **** - 36:.\Generated_Source\PSoC5/Cm3Start.c **** /* Function prototypes */ - 37:.\Generated_Source\PSoC5/Cm3Start.c **** void initialize_psoc(void); - 38:.\Generated_Source\PSoC5/Cm3Start.c **** CY_ISR(IntDefaultHandler); - 39:.\Generated_Source\PSoC5/Cm3Start.c **** void Reset(void); - 40:.\Generated_Source\PSoC5/Cm3Start.c **** CY_ISR(IntDefaultHandler); - 41:.\Generated_Source\PSoC5/Cm3Start.c **** - 42:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined(__ARMCC_VERSION) - 43:.\Generated_Source\PSoC5/Cm3Start.c **** #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) - 44:.\Generated_Source\PSoC5/Cm3Start.c **** #elif defined (__GNUC__) - 45:.\Generated_Source\PSoC5/Cm3Start.c **** #define INITIAL_STACK_POINTER (&__cy_stack) - 46:.\Generated_Source\PSoC5/Cm3Start.c **** #elif defined (__ICCARM__) - 47:.\Generated_Source\PSoC5/Cm3Start.c **** #pragma language=extended - 48:.\Generated_Source\PSoC5/Cm3Start.c **** #pragma segment="CSTACK" - 49:.\Generated_Source\PSoC5/Cm3Start.c **** #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } - 50:.\Generated_Source\PSoC5/Cm3Start.c **** - 51:.\Generated_Source\PSoC5/Cm3Start.c **** extern void __iar_program_start( void ); - 52:.\Generated_Source\PSoC5/Cm3Start.c **** extern void __iar_data_init3 (void); - 53:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (__ARMCC_VERSION) */ - 54:.\Generated_Source\PSoC5/Cm3Start.c **** - 55:.\Generated_Source\PSoC5/Cm3Start.c **** /* Global variables */ - 56:.\Generated_Source\PSoC5/Cm3Start.c **** #if !defined (__ICCARM__) - 57:.\Generated_Source\PSoC5/Cm3Start.c **** CY_NOINIT static uint32 cySysNoInitDataValid; - 58:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* !defined (__ICCARM__) */ - 59:.\Generated_Source\PSoC5/Cm3Start.c **** - 60:.\Generated_Source\PSoC5/Cm3Start.c **** - 61:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 62:.\Generated_Source\PSoC5/Cm3Start.c **** * Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. - 63:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 64:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined (__ICCARM__) - 65:.\Generated_Source\PSoC5/Cm3Start.c **** #pragma location=".ramvectors" - 66:.\Generated_Source\PSoC5/Cm3Start.c **** #pragma data_alignment=256 - 67:.\Generated_Source\PSoC5/Cm3Start.c **** #else - 68:.\Generated_Source\PSoC5/Cm3Start.c **** CY_SECTION(".ramvectors") - 69:.\Generated_Source\PSoC5/Cm3Start.c **** CY_ALIGN(256) - 70:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* defined (__ICCARM__) */ - 71:.\Generated_Source\PSoC5/Cm3Start.c **** cyisraddress CyRamVectors[CY_NUM_VECTORS]; - 72:.\Generated_Source\PSoC5/Cm3Start.c **** - 73:.\Generated_Source\PSoC5/Cm3Start.c **** - 74:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 75:.\Generated_Source\PSoC5/Cm3Start.c **** * Function Name: IntDefaultHandler - 76:.\Generated_Source\PSoC5/Cm3Start.c **** ******************************************************************************** - 77:.\Generated_Source\PSoC5/Cm3Start.c **** * - 78:.\Generated_Source\PSoC5/Cm3Start.c **** * Summary: - 79:.\Generated_Source\PSoC5/Cm3Start.c **** * This function is called for all interrupts, other than reset, that get - 80:.\Generated_Source\PSoC5/Cm3Start.c **** * called before the system is setup. - 81:.\Generated_Source\PSoC5/Cm3Start.c **** * - 82:.\Generated_Source\PSoC5/Cm3Start.c **** * Parameters: - 83:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 84:.\Generated_Source\PSoC5/Cm3Start.c **** * - 85:.\Generated_Source\PSoC5/Cm3Start.c **** * Return: - 86:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 87:.\Generated_Source\PSoC5/Cm3Start.c **** * - 88:.\Generated_Source\PSoC5/Cm3Start.c **** * Theory: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 3 - - - 89:.\Generated_Source\PSoC5/Cm3Start.c **** * Any value other than zero is acceptable. - 90:.\Generated_Source\PSoC5/Cm3Start.c **** * - 91:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 92:.\Generated_Source\PSoC5/Cm3Start.c **** CY_ISR(IntDefaultHandler) - 93:.\Generated_Source\PSoC5/Cm3Start.c **** { - 27 .loc 1 93 0 - 28 .cfi_startproc - 29 @ Volatile: function does not return. - 30 @ args = 0, pretend = 0, frame = 0 - 31 @ frame_needed = 0, uses_anonymous_args = 0 - 32 @ link register save eliminated. - 33 .L2: - 34 0000 FEE7 b .L2 - 35 .cfi_endproc - 36 .LFE0: - 37 .size IntDefaultHandler, .-IntDefaultHandler - 38 .section .text._exit,"ax",%progbits - 39 .align 1 - 40 .weak _exit - 41 .thumb - 42 .thumb_func - 43 .type _exit, %function - 44 _exit: - 45 .LFB2: - 94:.\Generated_Source\PSoC5/Cm3Start.c **** - 95:.\Generated_Source\PSoC5/Cm3Start.c **** while(1) - 96:.\Generated_Source\PSoC5/Cm3Start.c **** { - 97:.\Generated_Source\PSoC5/Cm3Start.c **** /*********************************************************************** - 98:.\Generated_Source\PSoC5/Cm3Start.c **** * We should never get here. If we do, a serious problem occured, so go - 99:.\Generated_Source\PSoC5/Cm3Start.c **** * into an infinite loop. - 100:.\Generated_Source\PSoC5/Cm3Start.c **** ***********************************************************************/ - 101:.\Generated_Source\PSoC5/Cm3Start.c **** } - 102:.\Generated_Source\PSoC5/Cm3Start.c **** } - 103:.\Generated_Source\PSoC5/Cm3Start.c **** - 104:.\Generated_Source\PSoC5/Cm3Start.c **** - 105:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined(__ARMCC_VERSION) - 106:.\Generated_Source\PSoC5/Cm3Start.c **** - 107:.\Generated_Source\PSoC5/Cm3Start.c **** /* Local function for the device reset. */ - 108:.\Generated_Source\PSoC5/Cm3Start.c **** extern void Reset(void); - 109:.\Generated_Source\PSoC5/Cm3Start.c **** - 110:.\Generated_Source\PSoC5/Cm3Start.c **** /* Application entry point. */ - 111:.\Generated_Source\PSoC5/Cm3Start.c **** extern void $Super$$main(void); - 112:.\Generated_Source\PSoC5/Cm3Start.c **** - 113:.\Generated_Source\PSoC5/Cm3Start.c **** /* Linker-generated Stack Base addresses, Two Region and One Region */ - 114:.\Generated_Source\PSoC5/Cm3Start.c **** extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; - 115:.\Generated_Source\PSoC5/Cm3Start.c **** - 116:.\Generated_Source\PSoC5/Cm3Start.c **** /* RealView C Library initialization. */ - 117:.\Generated_Source\PSoC5/Cm3Start.c **** extern int __main(void); - 118:.\Generated_Source\PSoC5/Cm3Start.c **** - 119:.\Generated_Source\PSoC5/Cm3Start.c **** - 120:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 121:.\Generated_Source\PSoC5/Cm3Start.c **** * Function Name: Reset - 122:.\Generated_Source\PSoC5/Cm3Start.c **** ******************************************************************************** - 123:.\Generated_Source\PSoC5/Cm3Start.c **** * - 124:.\Generated_Source\PSoC5/Cm3Start.c **** * Summary: - 125:.\Generated_Source\PSoC5/Cm3Start.c **** * This function handles the reset interrupt for the RVDS/MDK toolchains. - 126:.\Generated_Source\PSoC5/Cm3Start.c **** * This is the first bit of code that is executed at startup. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 4 - - - 127:.\Generated_Source\PSoC5/Cm3Start.c **** * - 128:.\Generated_Source\PSoC5/Cm3Start.c **** * Parameters: - 129:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 130:.\Generated_Source\PSoC5/Cm3Start.c **** * - 131:.\Generated_Source\PSoC5/Cm3Start.c **** * Return: - 132:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 133:.\Generated_Source\PSoC5/Cm3Start.c **** * - 134:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 135:.\Generated_Source\PSoC5/Cm3Start.c **** void Reset(void) - 136:.\Generated_Source\PSoC5/Cm3Start.c **** { - 137:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) - 138:.\Generated_Source\PSoC5/Cm3Start.c **** - 139:.\Generated_Source\PSoC5/Cm3Start.c **** /* For PSoC 5LP, debugging is enabled by default */ - 140:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_DEBUGGING_ENABLE == 0) - 141:.\Generated_Source\PSoC5/Cm3Start.c **** *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; - 142:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_DEBUGGING_ENABLE) */ - 143:.\Generated_Source\PSoC5/Cm3Start.c **** - 144:.\Generated_Source\PSoC5/Cm3Start.c **** /* Reset Status Register has Read-to-clear SW access mode. - 145:.\Generated_Source\PSoC5/Cm3Start.c **** * Preserve current RESET_SR0 state to make it available for next reading. - 146:.\Generated_Source\PSoC5/Cm3Start.c **** */ - 147:.\Generated_Source\PSoC5/Cm3Start.c **** *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - 148:.\Generated_Source\PSoC5/Cm3Start.c **** - 149:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ - 150:.\Generated_Source\PSoC5/Cm3Start.c **** - 151:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_BOOTLOADER_ENABLE) - 152:.\Generated_Source\PSoC5/Cm3Start.c **** CyBtldr_CheckLaunch(); - 153:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_BOOTLOADER_ENABLE) */ - 154:.\Generated_Source\PSoC5/Cm3Start.c **** - 155:.\Generated_Source\PSoC5/Cm3Start.c **** __main(); - 156:.\Generated_Source\PSoC5/Cm3Start.c **** } - 157:.\Generated_Source\PSoC5/Cm3Start.c **** - 158:.\Generated_Source\PSoC5/Cm3Start.c **** - 159:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 160:.\Generated_Source\PSoC5/Cm3Start.c **** * Function Name: $Sub$$main - 161:.\Generated_Source\PSoC5/Cm3Start.c **** ******************************************************************************** - 162:.\Generated_Source\PSoC5/Cm3Start.c **** * - 163:.\Generated_Source\PSoC5/Cm3Start.c **** * Summary: - 164:.\Generated_Source\PSoC5/Cm3Start.c **** * This function is called imediatly before the users main - 165:.\Generated_Source\PSoC5/Cm3Start.c **** * - 166:.\Generated_Source\PSoC5/Cm3Start.c **** * Parameters: - 167:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 168:.\Generated_Source\PSoC5/Cm3Start.c **** * - 169:.\Generated_Source\PSoC5/Cm3Start.c **** * Return: - 170:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 171:.\Generated_Source\PSoC5/Cm3Start.c **** * - 172:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 173:.\Generated_Source\PSoC5/Cm3Start.c **** void $Sub$$main(void) - 174:.\Generated_Source\PSoC5/Cm3Start.c **** { - 175:.\Generated_Source\PSoC5/Cm3Start.c **** initialize_psoc(); - 176:.\Generated_Source\PSoC5/Cm3Start.c **** - 177:.\Generated_Source\PSoC5/Cm3Start.c **** /* Call original main */ - 178:.\Generated_Source\PSoC5/Cm3Start.c **** $Super$$main(); - 179:.\Generated_Source\PSoC5/Cm3Start.c **** - 180:.\Generated_Source\PSoC5/Cm3Start.c **** while (1) - 181:.\Generated_Source\PSoC5/Cm3Start.c **** { - 182:.\Generated_Source\PSoC5/Cm3Start.c **** /* If main returns it is undefined what we should do. */ - 183:.\Generated_Source\PSoC5/Cm3Start.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 5 - - - 184:.\Generated_Source\PSoC5/Cm3Start.c **** } - 185:.\Generated_Source\PSoC5/Cm3Start.c **** - 186:.\Generated_Source\PSoC5/Cm3Start.c **** #elif defined(__GNUC__) - 187:.\Generated_Source\PSoC5/Cm3Start.c **** - 188:.\Generated_Source\PSoC5/Cm3Start.c **** void Start_c(void); - 189:.\Generated_Source\PSoC5/Cm3Start.c **** - 190:.\Generated_Source\PSoC5/Cm3Start.c **** /* Stack Base address */ - 191:.\Generated_Source\PSoC5/Cm3Start.c **** extern void __cy_stack(void); - 192:.\Generated_Source\PSoC5/Cm3Start.c **** - 193:.\Generated_Source\PSoC5/Cm3Start.c **** /* Application entry point. */ - 194:.\Generated_Source\PSoC5/Cm3Start.c **** extern int main(void); - 195:.\Generated_Source\PSoC5/Cm3Start.c **** - 196:.\Generated_Source\PSoC5/Cm3Start.c **** /* The static objects constructors initializer */ - 197:.\Generated_Source\PSoC5/Cm3Start.c **** extern void __libc_init_array(void); - 198:.\Generated_Source\PSoC5/Cm3Start.c **** - 199:.\Generated_Source\PSoC5/Cm3Start.c **** typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); - 200:.\Generated_Source\PSoC5/Cm3Start.c **** - 201:.\Generated_Source\PSoC5/Cm3Start.c **** struct __cy_region - 202:.\Generated_Source\PSoC5/Cm3Start.c **** { - 203:.\Generated_Source\PSoC5/Cm3Start.c **** __cy_byte_align8 *init; /* Initial contents of this region. */ - 204:.\Generated_Source\PSoC5/Cm3Start.c **** __cy_byte_align8 *data; /* Start address of region. */ - 205:.\Generated_Source\PSoC5/Cm3Start.c **** size_t init_size; /* Size of initial data. */ - 206:.\Generated_Source\PSoC5/Cm3Start.c **** size_t zero_size; /* Additional size to be zeroed. */ - 207:.\Generated_Source\PSoC5/Cm3Start.c **** }; - 208:.\Generated_Source\PSoC5/Cm3Start.c **** - 209:.\Generated_Source\PSoC5/Cm3Start.c **** extern const struct __cy_region __cy_regions[]; - 210:.\Generated_Source\PSoC5/Cm3Start.c **** extern const char __cy_region_num __attribute__((weak)); - 211:.\Generated_Source\PSoC5/Cm3Start.c **** #define __cy_region_num ((size_t)&__cy_region_num) - 212:.\Generated_Source\PSoC5/Cm3Start.c **** - 213:.\Generated_Source\PSoC5/Cm3Start.c **** - 214:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 215:.\Generated_Source\PSoC5/Cm3Start.c **** * Function Name: Reset - 216:.\Generated_Source\PSoC5/Cm3Start.c **** ******************************************************************************** - 217:.\Generated_Source\PSoC5/Cm3Start.c **** * - 218:.\Generated_Source\PSoC5/Cm3Start.c **** * Summary: - 219:.\Generated_Source\PSoC5/Cm3Start.c **** * This function handles the reset interrupt for the GCC toolchain. This is the - 220:.\Generated_Source\PSoC5/Cm3Start.c **** * first bit of code that is executed at startup. - 221:.\Generated_Source\PSoC5/Cm3Start.c **** * - 222:.\Generated_Source\PSoC5/Cm3Start.c **** * Parameters: - 223:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 224:.\Generated_Source\PSoC5/Cm3Start.c **** * - 225:.\Generated_Source\PSoC5/Cm3Start.c **** * Return: - 226:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 227:.\Generated_Source\PSoC5/Cm3Start.c **** * - 228:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 229:.\Generated_Source\PSoC5/Cm3Start.c **** void Reset(void) - 230:.\Generated_Source\PSoC5/Cm3Start.c **** { - 231:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) - 232:.\Generated_Source\PSoC5/Cm3Start.c **** - 233:.\Generated_Source\PSoC5/Cm3Start.c **** /* For PSoC 5LP, debugging is enabled by default */ - 234:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_DEBUGGING_ENABLE == 0) - 235:.\Generated_Source\PSoC5/Cm3Start.c **** *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; - 236:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_DEBUGGING_ENABLE) */ - 237:.\Generated_Source\PSoC5/Cm3Start.c **** - 238:.\Generated_Source\PSoC5/Cm3Start.c **** /* Reset Status Register has Read-to-clear SW access mode. - 239:.\Generated_Source\PSoC5/Cm3Start.c **** * Preserve current RESET_SR0 state to make it available for next reading. - 240:.\Generated_Source\PSoC5/Cm3Start.c **** */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 6 - - - 241:.\Generated_Source\PSoC5/Cm3Start.c **** *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - 242:.\Generated_Source\PSoC5/Cm3Start.c **** - 243:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ - 244:.\Generated_Source\PSoC5/Cm3Start.c **** - 245:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_BOOTLOADER_ENABLE) - 246:.\Generated_Source\PSoC5/Cm3Start.c **** CyBtldr_CheckLaunch(); - 247:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_BOOTLOADER_ENABLE) */ - 248:.\Generated_Source\PSoC5/Cm3Start.c **** - 249:.\Generated_Source\PSoC5/Cm3Start.c **** Start_c(); - 250:.\Generated_Source\PSoC5/Cm3Start.c **** } - 251:.\Generated_Source\PSoC5/Cm3Start.c **** - 252:.\Generated_Source\PSoC5/Cm3Start.c **** __attribute__((weak)) - 253:.\Generated_Source\PSoC5/Cm3Start.c **** void _exit(int status) - 254:.\Generated_Source\PSoC5/Cm3Start.c **** { - 46 .loc 1 254 0 - 47 .cfi_startproc - 48 @ Volatile: function does not return. - 49 @ args = 0, pretend = 0, frame = 0 - 50 @ frame_needed = 0, uses_anonymous_args = 0 - 51 @ link register save eliminated. - 52 .LVL0: - 53 .L4: - 54 0000 FEE7 b .L4 - 55 .cfi_endproc - 56 .LFE2: - 57 .size _exit, .-_exit - 58 .section .text.Start_c,"ax",%progbits - 59 .align 1 - 60 .global Start_c - 61 .thumb - 62 .thumb_func - 63 .type Start_c, %function - 64 Start_c: - 65 .LFB3: - 255:.\Generated_Source\PSoC5/Cm3Start.c **** /* Cause a divide by 0 exception */ - 256:.\Generated_Source\PSoC5/Cm3Start.c **** int x = status / INT_MAX; - 257:.\Generated_Source\PSoC5/Cm3Start.c **** x = 4 / x; - 258:.\Generated_Source\PSoC5/Cm3Start.c **** - 259:.\Generated_Source\PSoC5/Cm3Start.c **** while(1) - 260:.\Generated_Source\PSoC5/Cm3Start.c **** { - 261:.\Generated_Source\PSoC5/Cm3Start.c **** } - 262:.\Generated_Source\PSoC5/Cm3Start.c **** } - 263:.\Generated_Source\PSoC5/Cm3Start.c **** - 264:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 265:.\Generated_Source\PSoC5/Cm3Start.c **** * Function Name: Start_c - 266:.\Generated_Source\PSoC5/Cm3Start.c **** ******************************************************************************** - 267:.\Generated_Source\PSoC5/Cm3Start.c **** * - 268:.\Generated_Source\PSoC5/Cm3Start.c **** * Summary: - 269:.\Generated_Source\PSoC5/Cm3Start.c **** * This function handles initializing the .data and .bss sections in - 270:.\Generated_Source\PSoC5/Cm3Start.c **** * preperation for running standard C code. Once initialization is complete - 271:.\Generated_Source\PSoC5/Cm3Start.c **** * it will call main(). This function will never return. - 272:.\Generated_Source\PSoC5/Cm3Start.c **** * - 273:.\Generated_Source\PSoC5/Cm3Start.c **** * Parameters: - 274:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 275:.\Generated_Source\PSoC5/Cm3Start.c **** * - 276:.\Generated_Source\PSoC5/Cm3Start.c **** * Return: - 277:.\Generated_Source\PSoC5/Cm3Start.c **** * None - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 7 - - - 278:.\Generated_Source\PSoC5/Cm3Start.c **** * - 279:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 280:.\Generated_Source\PSoC5/Cm3Start.c **** void Start_c(void) __attribute__ ((noreturn)); - 281:.\Generated_Source\PSoC5/Cm3Start.c **** void Start_c(void) - 282:.\Generated_Source\PSoC5/Cm3Start.c **** { - 66 .loc 1 282 0 - 67 .cfi_startproc - 68 @ Volatile: function does not return. - 69 @ args = 0, pretend = 0, frame = 0 - 70 @ frame_needed = 0, uses_anonymous_args = 0 - 71 .LVL1: - 72 .loc 1 282 0 - 73 0000 08B5 push {r3, lr} - 74 .LCFI0: - 75 .cfi_def_cfa_offset 8 - 76 .cfi_offset 3, -8 - 77 .cfi_offset 14, -4 - 78 0002 1249 ldr r1, .L17 - 79 0004 124B ldr r3, .L17+4 - 80 .LVL2: - 81 .L6: - 283:.\Generated_Source\PSoC5/Cm3Start.c **** unsigned regions = __cy_region_num; - 284:.\Generated_Source\PSoC5/Cm3Start.c **** const struct __cy_region *rptr = __cy_regions; - 285:.\Generated_Source\PSoC5/Cm3Start.c **** - 286:.\Generated_Source\PSoC5/Cm3Start.c **** /* Initialize memory */ - 287:.\Generated_Source\PSoC5/Cm3Start.c **** for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++) - 82 .loc 1 287 0 discriminator 1 - 83 0006 4A1C adds r2, r1, #1 - 84 0008 1AD0 beq .L14 - 85 .L11: - 86 .LBB2: - 288:.\Generated_Source\PSoC5/Cm3Start.c **** { - 289:.\Generated_Source\PSoC5/Cm3Start.c **** uint32 *src = (uint32 *)rptr->init; - 87 .loc 1 289 0 - 88 000a 53F8106C ldr r6, [r3, #-16] - 89 .LVL3: - 290:.\Generated_Source\PSoC5/Cm3Start.c **** uint32 *dst = (uint32 *)rptr->data; - 90 .loc 1 290 0 - 91 000e 53F80C0C ldr r0, [r3, #-12] - 92 .LVL4: - 291:.\Generated_Source\PSoC5/Cm3Start.c **** unsigned limit = rptr->init_size; - 93 .loc 1 291 0 - 94 0012 53F8085C ldr r5, [r3, #-8] - 95 .LVL5: - 292:.\Generated_Source\PSoC5/Cm3Start.c **** unsigned count; - 293:.\Generated_Source\PSoC5/Cm3Start.c **** - 294:.\Generated_Source\PSoC5/Cm3Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) - 96 .loc 1 294 0 - 97 0016 0022 movs r2, #0 - 98 .LVL6: - 99 .L7: - 100 .loc 1 294 0 is_stmt 0 discriminator 1 - 101 0018 AA42 cmp r2, r5 - 281:.\Generated_Source\PSoC5/Cm3Start.c **** void Start_c(void) - 102 .loc 1 281 0 is_stmt 1 discriminator 1 - 103 001a 00EB0204 add r4, r0, r2 - 104 .LVL7: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 8 - - - 105 .loc 1 294 0 discriminator 1 - 106 001e 03D0 beq .L15 - 107 .L8: - 295:.\Generated_Source\PSoC5/Cm3Start.c **** { - 296:.\Generated_Source\PSoC5/Cm3Start.c **** *dst++ = *src++; - 108 .loc 1 296 0 discriminator 2 - 109 0020 B458 ldr r4, [r6, r2] - 110 0022 8450 str r4, [r0, r2] - 294:.\Generated_Source\PSoC5/Cm3Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) - 111 .loc 1 294 0 discriminator 2 - 112 0024 0432 adds r2, r2, #4 - 113 .LVL8: - 114 0026 F7E7 b .L7 - 115 .L15: - 297:.\Generated_Source\PSoC5/Cm3Start.c **** } - 298:.\Generated_Source\PSoC5/Cm3Start.c **** limit = rptr->zero_size; - 116 .loc 1 298 0 - 117 0028 53F8040C ldr r0, [r3, #-4] - 118 .LVL9: - 299:.\Generated_Source\PSoC5/Cm3Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) - 119 .loc 1 299 0 - 120 002c 0022 movs r2, #0 - 121 .LVL10: - 122 .L9: - 123 .loc 1 299 0 is_stmt 0 discriminator 1 - 124 002e 8242 cmp r2, r0 - 125 0030 03D0 beq .L16 - 126 .L10: - 300:.\Generated_Source\PSoC5/Cm3Start.c **** { - 301:.\Generated_Source\PSoC5/Cm3Start.c **** *dst++ = 0u; - 127 .loc 1 301 0 is_stmt 1 discriminator 2 - 128 0032 0025 movs r5, #0 - 129 0034 A550 str r5, [r4, r2] - 299:.\Generated_Source\PSoC5/Cm3Start.c **** for (count = 0u; count != limit; count += sizeof (uint32)) - 130 .loc 1 299 0 discriminator 2 - 131 0036 0432 adds r2, r2, #4 - 132 .LVL11: - 133 0038 F9E7 b .L9 - 134 .L16: - 135 003a 0139 subs r1, r1, #1 - 136 003c 1033 adds r3, r3, #16 - 137 003e E2E7 b .L6 - 138 .LVL12: - 139 .L14: - 140 .LBE2: - 302:.\Generated_Source\PSoC5/Cm3Start.c **** } - 303:.\Generated_Source\PSoC5/Cm3Start.c **** } - 304:.\Generated_Source\PSoC5/Cm3Start.c **** - 305:.\Generated_Source\PSoC5/Cm3Start.c **** /* Invoke static objects constructors */ - 306:.\Generated_Source\PSoC5/Cm3Start.c **** __libc_init_array(); - 141 .loc 1 306 0 - 142 0040 FFF7FEFF bl __libc_init_array - 143 .LVL13: - 307:.\Generated_Source\PSoC5/Cm3Start.c **** (void) main(); - 144 .loc 1 307 0 - 145 0044 FFF7FEFF bl main - 146 .LVL14: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 9 - - - 147 .L12: - 148 0048 FEE7 b .L12 - 149 .L18: - 150 004a 00BF .align 2 - 151 .L17: - 152 004c FFFFFFFF .word __cy_region_num-1 - 153 0050 10000000 .word __cy_regions+16 - 154 .cfi_endproc - 155 .LFE3: - 156 .size Start_c, .-Start_c - 157 .section .text.Reset,"ax",%progbits - 158 .align 1 - 159 .global Reset - 160 .thumb - 161 .thumb_func - 162 .type Reset, %function - 163 Reset: - 164 .LFB1: - 230:.\Generated_Source\PSoC5/Cm3Start.c **** { - 165 .loc 1 230 0 - 166 .cfi_startproc - 167 @ args = 0, pretend = 0, frame = 0 - 168 @ frame_needed = 0, uses_anonymous_args = 0 - 169 0000 08B5 push {r3, lr} - 170 .LCFI1: - 171 .cfi_def_cfa_offset 8 - 172 .cfi_offset 3, -8 - 173 .cfi_offset 14, -4 - 241:.\Generated_Source\PSoC5/Cm3Start.c **** *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - 174 .loc 1 241 0 - 175 0002 044B ldr r3, .L20 - 176 0004 0448 ldr r0, .L20+4 - 177 0006 1A68 ldr r2, [r3, #0] - 178 0008 0260 str r2, [r0, #0] - 246:.\Generated_Source\PSoC5/Cm3Start.c **** CyBtldr_CheckLaunch(); - 179 .loc 1 246 0 - 180 000a FFF7FEFF bl CyBtldr_CheckLaunch - 181 .LVL15: - 249:.\Generated_Source\PSoC5/Cm3Start.c **** Start_c(); - 182 .loc 1 249 0 - 183 000e FFF7FEFF bl Start_c - 184 .LVL16: - 185 .L21: - 186 0012 00BF .align 2 - 187 .L20: - 188 0014 FA460040 .word 1073759994 - 189 0018 BC760040 .word 1073772220 - 190 .cfi_endproc - 191 .LFE1: - 192 .size Reset, .-Reset - 193 .section .text.startup.initialize_psoc,"ax",%progbits - 194 .align 1 - 195 .global initialize_psoc - 196 .thumb - 197 .thumb_func - 198 .type initialize_psoc, %function - 199 initialize_psoc: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 10 - - - 200 .LFB4: - 308:.\Generated_Source\PSoC5/Cm3Start.c **** - 309:.\Generated_Source\PSoC5/Cm3Start.c **** while (1) - 310:.\Generated_Source\PSoC5/Cm3Start.c **** { - 311:.\Generated_Source\PSoC5/Cm3Start.c **** /* If main returns, make sure we don't return. */ - 312:.\Generated_Source\PSoC5/Cm3Start.c **** } - 313:.\Generated_Source\PSoC5/Cm3Start.c **** } - 314:.\Generated_Source\PSoC5/Cm3Start.c **** - 315:.\Generated_Source\PSoC5/Cm3Start.c **** - 316:.\Generated_Source\PSoC5/Cm3Start.c **** #elif defined (__ICCARM__) - 317:.\Generated_Source\PSoC5/Cm3Start.c **** - 318:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 319:.\Generated_Source\PSoC5/Cm3Start.c **** * Function Name: __low_level_init - 320:.\Generated_Source\PSoC5/Cm3Start.c **** ******************************************************************************** - 321:.\Generated_Source\PSoC5/Cm3Start.c **** * - 322:.\Generated_Source\PSoC5/Cm3Start.c **** * Summary: - 323:.\Generated_Source\PSoC5/Cm3Start.c **** * This function perform early initializations for the IAR Embedded - 324:.\Generated_Source\PSoC5/Cm3Start.c **** * Workbench IDE. It is executed in the context of reset interrupt handler - 325:.\Generated_Source\PSoC5/Cm3Start.c **** * before the data sections are initialized. - 326:.\Generated_Source\PSoC5/Cm3Start.c **** * - 327:.\Generated_Source\PSoC5/Cm3Start.c **** * Parameters: - 328:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 329:.\Generated_Source\PSoC5/Cm3Start.c **** * - 330:.\Generated_Source\PSoC5/Cm3Start.c **** * Return: - 331:.\Generated_Source\PSoC5/Cm3Start.c **** * The value that determines whether or not data sections should be initialized - 332:.\Generated_Source\PSoC5/Cm3Start.c **** * by the system startup code: - 333:.\Generated_Source\PSoC5/Cm3Start.c **** * 0 - skip data sections initialization; - 334:.\Generated_Source\PSoC5/Cm3Start.c **** * 1 - initialize data sections; - 335:.\Generated_Source\PSoC5/Cm3Start.c **** * - 336:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 337:.\Generated_Source\PSoC5/Cm3Start.c **** int __low_level_init(void) - 338:.\Generated_Source\PSoC5/Cm3Start.c **** { - 339:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) - 340:.\Generated_Source\PSoC5/Cm3Start.c **** - 341:.\Generated_Source\PSoC5/Cm3Start.c **** /* For PSoC 5LP, debugging is enabled by default */ - 342:.\Generated_Source\PSoC5/Cm3Start.c **** #if(CYDEV_DEBUGGING_ENABLE == 0) - 343:.\Generated_Source\PSoC5/Cm3Start.c **** *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; - 344:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_DEBUGGING_ENABLE) */ - 345:.\Generated_Source\PSoC5/Cm3Start.c **** - 346:.\Generated_Source\PSoC5/Cm3Start.c **** /* Reset Status Register has Read-to-clear SW access mode. - 347:.\Generated_Source\PSoC5/Cm3Start.c **** * Preserve current RESET_SR0 state to make it available for next reading. - 348:.\Generated_Source\PSoC5/Cm3Start.c **** */ - 349:.\Generated_Source\PSoC5/Cm3Start.c **** *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - 350:.\Generated_Source\PSoC5/Cm3Start.c **** - 351:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ - 352:.\Generated_Source\PSoC5/Cm3Start.c **** - 353:.\Generated_Source\PSoC5/Cm3Start.c **** #if (CYDEV_BOOTLOADER_ENABLE) - 354:.\Generated_Source\PSoC5/Cm3Start.c **** CyBtldr_CheckLaunch(); - 355:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* CYDEV_BOOTLOADER_ENABLE */ - 356:.\Generated_Source\PSoC5/Cm3Start.c **** - 357:.\Generated_Source\PSoC5/Cm3Start.c **** /* Initialize data sections */ - 358:.\Generated_Source\PSoC5/Cm3Start.c **** __iar_data_init3(); - 359:.\Generated_Source\PSoC5/Cm3Start.c **** - 360:.\Generated_Source\PSoC5/Cm3Start.c **** initialize_psoc(); - 361:.\Generated_Source\PSoC5/Cm3Start.c **** - 362:.\Generated_Source\PSoC5/Cm3Start.c **** return 0; - 363:.\Generated_Source\PSoC5/Cm3Start.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 11 - - - 364:.\Generated_Source\PSoC5/Cm3Start.c **** - 365:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* __GNUC__ */ - 366:.\Generated_Source\PSoC5/Cm3Start.c **** - 367:.\Generated_Source\PSoC5/Cm3Start.c **** - 368:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 369:.\Generated_Source\PSoC5/Cm3Start.c **** * - 370:.\Generated_Source\PSoC5/Cm3Start.c **** * Default Rom Interrupt Vector table. - 371:.\Generated_Source\PSoC5/Cm3Start.c **** * - 372:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 373:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined(__ARMCC_VERSION) - 374:.\Generated_Source\PSoC5/Cm3Start.c **** /* Suppress diagnostic message 1296-D: extended constant initialiser used */ - 375:.\Generated_Source\PSoC5/Cm3Start.c **** #pragma diag_suppress 1296 - 376:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* defined(__ARMCC_VERSION) */ - 377:.\Generated_Source\PSoC5/Cm3Start.c **** - 378:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined (__ICCARM__) - 379:.\Generated_Source\PSoC5/Cm3Start.c **** #pragma location=".romvectors" - 380:.\Generated_Source\PSoC5/Cm3Start.c **** const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = - 381:.\Generated_Source\PSoC5/Cm3Start.c **** #else - 382:.\Generated_Source\PSoC5/Cm3Start.c **** CY_SECTION(".romvectors") - 383:.\Generated_Source\PSoC5/Cm3Start.c **** const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = - 384:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* defined (__ICCARM__) */ - 385:.\Generated_Source\PSoC5/Cm3Start.c **** { - 386:.\Generated_Source\PSoC5/Cm3Start.c **** INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ - 387:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined (__ICCARM__) /* The reset handler 1 */ - 388:.\Generated_Source\PSoC5/Cm3Start.c **** __iar_program_start, - 389:.\Generated_Source\PSoC5/Cm3Start.c **** #else - 390:.\Generated_Source\PSoC5/Cm3Start.c **** (cyisraddress)&Reset, - 391:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* defined (__ICCARM__) */ - 392:.\Generated_Source\PSoC5/Cm3Start.c **** &IntDefaultHandler, /* The NMI handler 2 */ - 393:.\Generated_Source\PSoC5/Cm3Start.c **** &IntDefaultHandler, /* The hard fault handler 3 */ - 394:.\Generated_Source\PSoC5/Cm3Start.c **** }; - 395:.\Generated_Source\PSoC5/Cm3Start.c **** - 396:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined(__ARMCC_VERSION) - 397:.\Generated_Source\PSoC5/Cm3Start.c **** #pragma diag_default 1296 - 398:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* defined(__ARMCC_VERSION) */ - 399:.\Generated_Source\PSoC5/Cm3Start.c **** - 400:.\Generated_Source\PSoC5/Cm3Start.c **** - 401:.\Generated_Source\PSoC5/Cm3Start.c **** /******************************************************************************* - 402:.\Generated_Source\PSoC5/Cm3Start.c **** * Function Name: initialize_psoc - 403:.\Generated_Source\PSoC5/Cm3Start.c **** ******************************************************************************** - 404:.\Generated_Source\PSoC5/Cm3Start.c **** * - 405:.\Generated_Source\PSoC5/Cm3Start.c **** * Summary: - 406:.\Generated_Source\PSoC5/Cm3Start.c **** * This function used to initialize the PSoC chip before calling main. - 407:.\Generated_Source\PSoC5/Cm3Start.c **** * - 408:.\Generated_Source\PSoC5/Cm3Start.c **** * Parameters: - 409:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 410:.\Generated_Source\PSoC5/Cm3Start.c **** * - 411:.\Generated_Source\PSoC5/Cm3Start.c **** * Return: - 412:.\Generated_Source\PSoC5/Cm3Start.c **** * None - 413:.\Generated_Source\PSoC5/Cm3Start.c **** * - 414:.\Generated_Source\PSoC5/Cm3Start.c **** *******************************************************************************/ - 415:.\Generated_Source\PSoC5/Cm3Start.c **** #if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) - 416:.\Generated_Source\PSoC5/Cm3Start.c **** __attribute__ ((constructor(101))) - 417:.\Generated_Source\PSoC5/Cm3Start.c **** #endif - 418:.\Generated_Source\PSoC5/Cm3Start.c **** void initialize_psoc(void) - 419:.\Generated_Source\PSoC5/Cm3Start.c **** { - 201 .loc 1 419 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 12 - - - 202 .cfi_startproc - 203 @ args = 0, pretend = 0, frame = 0 - 204 @ frame_needed = 0, uses_anonymous_args = 0 - 205 0000 08B5 push {r3, lr} - 206 .LCFI2: - 207 .cfi_def_cfa_offset 8 - 208 .cfi_offset 3, -8 - 209 .cfi_offset 14, -4 - 420:.\Generated_Source\PSoC5/Cm3Start.c **** uint32 i; - 421:.\Generated_Source\PSoC5/Cm3Start.c **** - 422:.\Generated_Source\PSoC5/Cm3Start.c **** /* Set Priority group 5. */ - 423:.\Generated_Source\PSoC5/Cm3Start.c **** - 424:.\Generated_Source\PSoC5/Cm3Start.c **** /* Writes to NVIC_APINT register require the VECTKEY in the upper half */ - 425:.\Generated_Source\PSoC5/Cm3Start.c **** *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5; - 210 .loc 1 425 0 - 211 0002 104A ldr r2, .L27 - 212 0004 104B ldr r3, .L27+4 - 213 0006 1A60 str r2, [r3, #0] - 426:.\Generated_Source\PSoC5/Cm3Start.c **** *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN; - 214 .loc 1 426 0 - 215 0008 9868 ldr r0, [r3, #8] - 216 000a 40F40072 orr r2, r0, #512 - 217 000e 9A60 str r2, [r3, #8] - 218 .LVL17: - 427:.\Generated_Source\PSoC5/Cm3Start.c **** - 428:.\Generated_Source\PSoC5/Cm3Start.c **** /* Set Ram interrupt vectors to default functions. */ - 429:.\Generated_Source\PSoC5/Cm3Start.c **** for (i = 0u; i < CY_NUM_VECTORS; i++) - 219 .loc 1 429 0 - 220 0010 0023 movs r3, #0 - 221 .LVL18: - 222 .L24: - 430:.\Generated_Source\PSoC5/Cm3Start.c **** { - 431:.\Generated_Source\PSoC5/Cm3Start.c **** #if defined (__ICCARM__) - 432:.\Generated_Source\PSoC5/Cm3Start.c **** CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandl - 433:.\Generated_Source\PSoC5/Cm3Start.c **** #else - 434:.\Generated_Source\PSoC5/Cm3Start.c **** CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; - 223 .loc 1 434 0 - 224 0012 032B cmp r3, #3 - 225 0014 96BF itet ls - 226 0016 0D4A ldrls r2, .L27+8 - 227 0018 0D49 ldrhi r1, .L27+12 - 228 001a 52F82310 ldrls r1, [r2, r3, lsl #2] - 229 001e 0D4A ldr r2, .L27+16 - 230 0020 42F82310 str r1, [r2, r3, lsl #2] - 429:.\Generated_Source\PSoC5/Cm3Start.c **** for (i = 0u; i < CY_NUM_VECTORS; i++) - 231 .loc 1 429 0 - 232 0024 0133 adds r3, r3, #1 - 233 .LVL19: - 234 0026 302B cmp r3, #48 - 235 0028 F3D1 bne .L24 - 435:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* defined (__ICCARM__) */ - 436:.\Generated_Source\PSoC5/Cm3Start.c **** } - 437:.\Generated_Source\PSoC5/Cm3Start.c **** - 438:.\Generated_Source\PSoC5/Cm3Start.c **** /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ - 439:.\Generated_Source\PSoC5/Cm3Start.c **** CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); - 236 .loc 1 439 0 - 237 002a 0B49 ldr r1, .L27+20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 13 - - - 238 002c 0B4B ldr r3, .L27+24 - 239 .LVL20: - 240 002e 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 440:.\Generated_Source\PSoC5/Cm3Start.c **** - 441:.\Generated_Source\PSoC5/Cm3Start.c **** /* Point NVIC at the RAM vector table. */ - 442:.\Generated_Source\PSoC5/Cm3Start.c **** *CYINT_VECT_TABLE = CyRamVectors; - 241 .loc 1 442 0 - 242 0030 0B49 ldr r1, .L27+28 - 439:.\Generated_Source\PSoC5/Cm3Start.c **** CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); - 243 .loc 1 439 0 - 244 0032 1870 strb r0, [r3, #0] - 245 .loc 1 442 0 - 246 0034 0A60 str r2, [r1, #0] - 443:.\Generated_Source\PSoC5/Cm3Start.c **** - 444:.\Generated_Source\PSoC5/Cm3Start.c **** /* Initialize the configuration registers. */ - 445:.\Generated_Source\PSoC5/Cm3Start.c **** cyfitter_cfg(); - 247 .loc 1 445 0 - 248 0036 FFF7FEFF bl cyfitter_cfg - 249 .LVL21: - 446:.\Generated_Source\PSoC5/Cm3Start.c **** - 447:.\Generated_Source\PSoC5/Cm3Start.c **** #if(0u != DMA_CHANNELS_USED__MASK0) - 448:.\Generated_Source\PSoC5/Cm3Start.c **** - 449:.\Generated_Source\PSoC5/Cm3Start.c **** /* Setup DMA - only necessary if the design contains a DMA component. */ - 450:.\Generated_Source\PSoC5/Cm3Start.c **** CyDmacConfigure(); - 451:.\Generated_Source\PSoC5/Cm3Start.c **** - 452:.\Generated_Source\PSoC5/Cm3Start.c **** #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ - 453:.\Generated_Source\PSoC5/Cm3Start.c **** - 454:.\Generated_Source\PSoC5/Cm3Start.c **** #if !defined (__ICCARM__) - 455:.\Generated_Source\PSoC5/Cm3Start.c **** /* Actually, no need to clean this variable, just to make compiler happy. */ - 456:.\Generated_Source\PSoC5/Cm3Start.c **** cySysNoInitDataValid = 0u; - 250 .loc 1 456 0 - 251 003a 0A48 ldr r0, .L27+32 - 252 003c 0022 movs r2, #0 - 253 003e 0260 str r2, [r0, #0] - 254 0040 08BD pop {r3, pc} - 255 .L28: - 256 0042 00BF .align 2 - 257 .L27: - 258 0044 0004FA05 .word 100271104 - 259 0048 0CED00E0 .word -536810228 - 260 004c 00000000 .word .LANCHOR0 - 261 0050 00000000 .word IntDefaultHandler - 262 0054 00000000 .word .LANCHOR1 - 263 0058 BC760040 .word 1073772220 - 264 005c 00000000 .word CyResetStatus - 265 0060 08ED00E0 .word -536810232 - 266 0064 00000000 .word .LANCHOR2 - 267 .cfi_endproc - 268 .LFE4: - 269 .size initialize_psoc, .-initialize_psoc - 270 .section .init_array,"aw",%init_array - 271 .align 2 - 272 0000 00000000 .word initialize_psoc(target1) - 273 .global RomVectors - 274 .global CyRamVectors - 275 .section .romvectors,"a",%progbits - 276 .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 14 - - - 277 .set .LANCHOR0,. + 0 - 278 .type RomVectors, %object - 279 .size RomVectors, 16 - 280 RomVectors: - 281 0000 00000000 .word __cy_stack - 282 0004 00000000 .word Reset - 283 0008 00000000 .word IntDefaultHandler - 284 000c 00000000 .word IntDefaultHandler - 285 .section .noinit,"aw",%progbits - 286 .align 2 - 287 .set .LANCHOR2,. + 0 - 288 .type cySysNoInitDataValid, %object - 289 .size cySysNoInitDataValid, 4 - 290 cySysNoInitDataValid: - 291 0000 00000000 .space 4 - 292 .section .ramvectors,"aw",%progbits - 293 .align 8 - 294 .set .LANCHOR1,. + 0 - 295 .type CyRamVectors, %object - 296 .size CyRamVectors, 192 - 297 CyRamVectors: - 298 0000 00000000 .space 192 - 298 00000000 - 298 00000000 - 298 00000000 - 298 00000000 - 299 .weak __cy_region_num - 300 00c0 00000000 .text - 300 00000000 - 300 00000000 - 300 00000000 - 300 00000000 - 301 .Letext0: - 302 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 303 .file 3 "c:\\program files (x86)\\cypress\\psoc creator\\3.0\\psoc creator\\import\\gnu_cs\\arm\\4 - 304 .file 4 ".\\Generated_Source\\PSoC5\\CyLib.h" - 305 .file 5 ".\\Generated_Source\\PSoC5\\cyfitter_cfg.h" - 306 .section .debug_info,"",%progbits - 307 .Ldebug_info0: - 308 0000 41030000 .4byte 0x341 - 309 0004 0200 .2byte 0x2 - 310 0006 00000000 .4byte .Ldebug_abbrev0 - 311 000a 04 .byte 0x4 - 312 000b 01 .uleb128 0x1 - 313 000c E4010000 .4byte .LASF41 - 314 0010 01 .byte 0x1 - 315 0011 00000000 .4byte .LASF42 - 316 0015 BB000000 .4byte .LASF43 - 317 0019 00000000 .4byte .Ldebug_ranges0+0 - 318 001d 00000000 .4byte 0 - 319 0021 00000000 .4byte 0 - 320 0025 00000000 .4byte .Ldebug_line0 - 321 0029 02 .uleb128 0x2 - 322 002a 01 .byte 0x1 - 323 002b 06 .byte 0x6 - 324 002c 56020000 .4byte .LASF0 - 325 0030 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 15 - - - 326 0031 01 .byte 0x1 - 327 0032 08 .byte 0x8 - 328 0033 90000000 .4byte .LASF1 - 329 0037 02 .uleb128 0x2 - 330 0038 02 .byte 0x2 - 331 0039 05 .byte 0x5 - 332 003a C5010000 .4byte .LASF2 - 333 003e 02 .uleb128 0x2 - 334 003f 02 .byte 0x2 - 335 0040 07 .byte 0x7 - 336 0041 4C000000 .4byte .LASF3 - 337 0045 02 .uleb128 0x2 - 338 0046 04 .byte 0x4 - 339 0047 05 .byte 0x5 - 340 0048 3F020000 .4byte .LASF4 - 341 004c 02 .uleb128 0x2 - 342 004d 04 .byte 0x4 - 343 004e 07 .byte 0x7 - 344 004f A9000000 .4byte .LASF5 - 345 0053 02 .uleb128 0x2 - 346 0054 08 .byte 0x8 - 347 0055 05 .byte 0x5 - 348 0056 9E010000 .4byte .LASF6 - 349 005a 02 .uleb128 0x2 - 350 005b 08 .byte 0x8 - 351 005c 07 .byte 0x7 - 352 005d 4B010000 .4byte .LASF7 - 353 0061 03 .uleb128 0x3 - 354 0062 04 .byte 0x4 - 355 0063 05 .byte 0x5 - 356 0064 696E7400 .ascii "int\000" - 357 0068 02 .uleb128 0x2 - 358 0069 04 .byte 0x4 - 359 006a 07 .byte 0x7 - 360 006b 31010000 .4byte .LASF8 - 361 006f 04 .uleb128 0x4 - 362 0070 EC000000 .4byte .LASF9 - 363 0074 02 .byte 0x2 - 364 0075 5B .byte 0x5b - 365 0076 30000000 .4byte 0x30 - 366 007a 04 .uleb128 0x4 - 367 007b 2A010000 .4byte .LASF10 - 368 007f 02 .byte 0x2 - 369 0080 5D .byte 0x5d - 370 0081 4C000000 .4byte 0x4c - 371 0085 02 .uleb128 0x2 - 372 0086 04 .byte 0x4 - 373 0087 04 .byte 0x4 - 374 0088 85000000 .4byte .LASF11 - 375 008c 02 .uleb128 0x2 - 376 008d 08 .byte 0x8 - 377 008e 04 .byte 0x4 - 378 008f 62020000 .4byte .LASF12 - 379 0093 02 .uleb128 0x2 - 380 0094 01 .byte 0x1 - 381 0095 08 .byte 0x8 - 382 0096 AC010000 .4byte .LASF13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 16 - - - 383 009a 04 .uleb128 0x4 - 384 009b 90010000 .4byte .LASF14 - 385 009f 02 .byte 0x2 - 386 00a0 F0 .byte 0xf0 - 387 00a1 A5000000 .4byte 0xa5 - 388 00a5 05 .uleb128 0x5 - 389 00a6 6F000000 .4byte 0x6f - 390 00aa 04 .uleb128 0x4 - 391 00ab 24000000 .4byte .LASF15 - 392 00af 02 .byte 0x2 - 393 00b0 F2 .byte 0xf2 - 394 00b1 B5000000 .4byte 0xb5 - 395 00b5 05 .uleb128 0x5 - 396 00b6 7A000000 .4byte 0x7a - 397 00ba 06 .uleb128 0x6 - 398 00bb 68010000 .4byte .LASF16 - 399 00bf 02 .byte 0x2 - 400 00c0 0201 .2byte 0x102 - 401 00c2 C6000000 .4byte 0xc6 - 402 00c6 07 .uleb128 0x7 - 403 00c7 04 .byte 0x4 - 404 00c8 CC000000 .4byte 0xcc - 405 00cc 08 .uleb128 0x8 - 406 00cd 01 .byte 0x1 - 407 00ce 02 .uleb128 0x2 - 408 00cf 04 .byte 0x4 - 409 00d0 07 .byte 0x7 - 410 00d1 95010000 .4byte .LASF17 - 411 00d5 09 .uleb128 0x9 - 412 00d6 93000000 .4byte 0x93 - 413 00da 04 .uleb128 0x4 - 414 00db 2A000000 .4byte .LASF18 - 415 00df 03 .byte 0x3 - 416 00e0 D5 .byte 0xd5 - 417 00e1 68000000 .4byte 0x68 - 418 00e5 04 .uleb128 0x4 - 419 00e6 7F010000 .4byte .LASF19 - 420 00ea 01 .byte 0x1 - 421 00eb C7 .byte 0xc7 - 422 00ec 30000000 .4byte 0x30 - 423 00f0 0A .uleb128 0xa - 424 00f1 7E020000 .4byte .LASF44 - 425 00f5 10 .byte 0x10 - 426 00f6 01 .byte 0x1 - 427 00f7 C9 .byte 0xc9 - 428 00f8 35010000 .4byte 0x135 - 429 00fc 0B .uleb128 0xb - 430 00fd 6F000000 .4byte .LASF20 - 431 0101 01 .byte 0x1 - 432 0102 CB .byte 0xcb - 433 0103 35010000 .4byte 0x135 - 434 0107 02 .byte 0x2 - 435 0108 23 .byte 0x23 - 436 0109 00 .uleb128 0 - 437 010a 0B .uleb128 0xb - 438 010b 8B000000 .4byte .LASF21 - 439 010f 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 17 - - - 440 0110 CC .byte 0xcc - 441 0111 35010000 .4byte 0x135 - 442 0115 02 .byte 0x2 - 443 0116 23 .byte 0x23 - 444 0117 04 .uleb128 0x4 - 445 0118 0B .uleb128 0xb - 446 0119 75010000 .4byte .LASF22 - 447 011d 01 .byte 0x1 - 448 011e CD .byte 0xcd - 449 011f DA000000 .4byte 0xda - 450 0123 02 .byte 0x2 - 451 0124 23 .byte 0x23 - 452 0125 08 .uleb128 0x8 - 453 0126 0B .uleb128 0xb - 454 0127 7B000000 .4byte .LASF23 - 455 012b 01 .byte 0x1 - 456 012c CE .byte 0xce - 457 012d DA000000 .4byte 0xda - 458 0131 02 .byte 0x2 - 459 0132 23 .byte 0x23 - 460 0133 0C .uleb128 0xc - 461 0134 00 .byte 0 - 462 0135 07 .uleb128 0x7 - 463 0136 04 .byte 0x4 - 464 0137 E5000000 .4byte 0xe5 - 465 013b 0C .uleb128 0xc - 466 013c 01 .byte 0x1 - 467 013d FE000000 .4byte .LASF45 - 468 0141 01 .byte 0x1 - 469 0142 5C .byte 0x5c - 470 0143 01 .byte 0x1 - 471 0144 00000000 .4byte .LFB0 - 472 0148 02000000 .4byte .LFE0 - 473 014c 02 .byte 0x2 - 474 014d 7D .byte 0x7d - 475 014e 00 .sleb128 0 - 476 014f 01 .byte 0x1 - 477 0150 0D .uleb128 0xd - 478 0151 01 .byte 0x1 - 479 0152 F8000000 .4byte .LASF24 - 480 0156 01 .byte 0x1 - 481 0157 FD .byte 0xfd - 482 0158 01 .byte 0x1 - 483 0159 00000000 .4byte .LFB2 - 484 015d 02000000 .4byte .LFE2 - 485 0161 02 .byte 0x2 - 486 0162 7D .byte 0x7d - 487 0163 00 .sleb128 0 - 488 0164 01 .byte 0x1 - 489 0165 81010000 .4byte 0x181 - 490 0169 0E .uleb128 0xe - 491 016a 74000000 .4byte .LASF46 - 492 016e 01 .byte 0x1 - 493 016f FD .byte 0xfd - 494 0170 61000000 .4byte 0x61 - 495 0174 01 .byte 0x1 - 496 0175 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 18 - - - 497 0176 0F .uleb128 0xf - 498 0177 7800 .ascii "x\000" - 499 0179 01 .byte 0x1 - 500 017a 0001 .2byte 0x100 - 501 017c 61000000 .4byte 0x61 - 502 0180 00 .byte 0 - 503 0181 10 .uleb128 0x10 - 504 0182 01 .byte 0x1 - 505 0183 3E000000 .4byte .LASF25 - 506 0187 01 .byte 0x1 - 507 0188 1901 .2byte 0x119 - 508 018a 01 .byte 0x1 - 509 018b 00000000 .4byte .LFB3 - 510 018f 54000000 .4byte .LFE3 - 511 0193 00000000 .4byte .LLST0 - 512 0197 01 .byte 0x1 - 513 0198 15020000 .4byte 0x215 - 514 019c 11 .uleb128 0x11 - 515 019d 76020000 .4byte .LASF26 - 516 01a1 01 .byte 0x1 - 517 01a2 1B01 .2byte 0x11b - 518 01a4 68000000 .4byte 0x68 - 519 01a8 11 .uleb128 0x11 - 520 01a9 10010000 .4byte .LASF27 - 521 01ad 01 .byte 0x1 - 522 01ae 1C01 .2byte 0x11c - 523 01b0 15020000 .4byte 0x215 - 524 01b4 12 .uleb128 0x12 - 525 01b5 0A000000 .4byte .LBB2 - 526 01b9 40000000 .4byte .LBE2 - 527 01bd 02020000 .4byte 0x202 - 528 01c1 13 .uleb128 0x13 - 529 01c2 73726300 .ascii "src\000" - 530 01c6 01 .byte 0x1 - 531 01c7 2101 .2byte 0x121 - 532 01c9 20020000 .4byte 0x220 - 533 01cd 20000000 .4byte .LLST1 - 534 01d1 13 .uleb128 0x13 - 535 01d2 64737400 .ascii "dst\000" - 536 01d6 01 .byte 0x1 - 537 01d7 2201 .2byte 0x122 - 538 01d9 20020000 .4byte 0x220 - 539 01dd 33000000 .4byte .LLST2 - 540 01e1 14 .uleb128 0x14 - 541 01e2 62010000 .4byte .LASF28 - 542 01e6 01 .byte 0x1 - 543 01e7 2301 .2byte 0x123 - 544 01e9 68000000 .4byte 0x68 - 545 01ed 46000000 .4byte .LLST3 - 546 01f1 14 .uleb128 0x14 - 547 01f2 46000000 .4byte .LASF29 - 548 01f6 01 .byte 0x1 - 549 01f7 2401 .2byte 0x124 - 550 01f9 68000000 .4byte 0x68 - 551 01fd 64000000 .4byte .LLST4 - 552 0201 00 .byte 0 - 553 0202 15 .uleb128 0x15 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 19 - - - 554 0203 44000000 .4byte .LVL13 - 555 0207 18030000 .4byte 0x318 - 556 020b 15 .uleb128 0x15 - 557 020c 48000000 .4byte .LVL14 - 558 0210 22030000 .4byte 0x322 - 559 0214 00 .byte 0 - 560 0215 07 .uleb128 0x7 - 561 0216 04 .byte 0x4 - 562 0217 1B020000 .4byte 0x21b - 563 021b 09 .uleb128 0x9 - 564 021c F0000000 .4byte 0xf0 - 565 0220 07 .uleb128 0x7 - 566 0221 04 .byte 0x4 - 567 0222 7A000000 .4byte 0x7a - 568 0226 16 .uleb128 0x16 - 569 0227 01 .byte 0x1 - 570 0228 F2000000 .4byte .LASF30 - 571 022c 01 .byte 0x1 - 572 022d E5 .byte 0xe5 - 573 022e 01 .byte 0x1 - 574 022f 00000000 .4byte .LFB1 - 575 0233 1C000000 .4byte .LFE1 - 576 0237 9A000000 .4byte .LLST5 - 577 023b 01 .byte 0x1 - 578 023c 53020000 .4byte 0x253 - 579 0240 15 .uleb128 0x15 - 580 0241 0E000000 .4byte .LVL15 - 581 0245 30030000 .4byte 0x330 - 582 0249 15 .uleb128 0x15 - 583 024a 12000000 .4byte .LVL16 - 584 024e 81010000 .4byte 0x181 - 585 0252 00 .byte 0 - 586 0253 10 .uleb128 0x10 - 587 0254 01 .byte 0x1 - 588 0255 1A010000 .4byte .LASF31 - 589 0259 01 .byte 0x1 - 590 025a A201 .2byte 0x1a2 - 591 025c 01 .byte 0x1 - 592 025d 00000000 .4byte .LFB4 - 593 0261 68000000 .4byte .LFE4 - 594 0265 BA000000 .4byte .LLST6 - 595 0269 01 .byte 0x1 - 596 026a 86020000 .4byte 0x286 - 597 026e 13 .uleb128 0x13 - 598 026f 6900 .ascii "i\000" - 599 0271 01 .byte 0x1 - 600 0272 A401 .2byte 0x1a4 - 601 0274 7A000000 .4byte 0x7a - 602 0278 DA000000 .4byte .LLST7 - 603 027c 15 .uleb128 0x15 - 604 027d 3A000000 .4byte .LVL21 - 605 0281 3A030000 .4byte 0x33a - 606 0285 00 .byte 0 - 607 0286 17 .uleb128 0x17 - 608 0287 CF010000 .4byte .LASF32 - 609 028b 01 .byte 0x1 - 610 028c 39 .byte 0x39 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 20 - - - 611 028d 7A000000 .4byte 0x7a - 612 0291 05 .byte 0x5 - 613 0292 03 .byte 0x3 - 614 0293 00000000 .4byte cySysNoInitDataValid - 615 0297 18 .uleb128 0x18 - 616 0298 48020000 .4byte .LASF33 - 617 029c 04 .byte 0x4 - 618 029d 2D .byte 0x2d - 619 029e 6F000000 .4byte 0x6f - 620 02a2 01 .byte 0x1 - 621 02a3 01 .byte 0x1 - 622 02a4 19 .uleb128 0x19 - 623 02a5 BA000000 .4byte 0xba - 624 02a9 B4020000 .4byte 0x2b4 - 625 02ad 1A .uleb128 0x1a - 626 02ae CE000000 .4byte 0xce - 627 02b2 2F .byte 0x2f - 628 02b3 00 .byte 0 - 629 02b4 1B .uleb128 0x1b - 630 02b5 31000000 .4byte .LASF34 - 631 02b9 01 .byte 0x1 - 632 02ba 47 .byte 0x47 - 633 02bb A4020000 .4byte 0x2a4 - 634 02bf 01 .byte 0x1 - 635 02c0 05 .byte 0x5 - 636 02c1 03 .byte 0x3 - 637 02c2 00000000 .4byte CyRamVectors - 638 02c6 19 .uleb128 0x19 - 639 02c7 F0000000 .4byte 0xf0 - 640 02cb D1020000 .4byte 0x2d1 - 641 02cf 1C .uleb128 0x1c - 642 02d0 00 .byte 0 - 643 02d1 18 .uleb128 0x18 - 644 02d2 69020000 .4byte .LASF35 - 645 02d6 01 .byte 0x1 - 646 02d7 D1 .byte 0xd1 - 647 02d8 DE020000 .4byte 0x2de - 648 02dc 01 .byte 0x1 - 649 02dd 01 .byte 0x1 - 650 02de 09 .uleb128 0x9 - 651 02df C6020000 .4byte 0x2c6 - 652 02e3 18 .uleb128 0x18 - 653 02e4 5F000000 .4byte .LASF36 - 654 02e8 01 .byte 0x1 - 655 02e9 D2 .byte 0xd2 - 656 02ea D5000000 .4byte 0xd5 - 657 02ee 01 .byte 0x1 - 658 02ef 01 .byte 0x1 - 659 02f0 19 .uleb128 0x19 - 660 02f1 BA000000 .4byte 0xba - 661 02f5 00030000 .4byte 0x300 - 662 02f9 1A .uleb128 0x1a - 663 02fa CE000000 .4byte 0xce - 664 02fe 03 .byte 0x3 - 665 02ff 00 .byte 0 - 666 0300 1D .uleb128 0x1d - 667 0301 9E000000 .4byte .LASF37 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 21 - - - 668 0305 01 .byte 0x1 - 669 0306 7F01 .2byte 0x17f - 670 0308 13030000 .4byte 0x313 - 671 030c 01 .byte 0x1 - 672 030d 05 .byte 0x5 - 673 030e 03 .byte 0x3 - 674 030f 00000000 .4byte RomVectors - 675 0313 09 .uleb128 0x9 - 676 0314 F0020000 .4byte 0x2f0 - 677 0318 1E .uleb128 0x1e - 678 0319 01 .byte 0x1 - 679 031a 2D020000 .4byte .LASF38 - 680 031e 01 .byte 0x1 - 681 031f C5 .byte 0xc5 - 682 0320 01 .byte 0x1 - 683 0321 01 .byte 0x1 - 684 0322 1F .uleb128 0x1f - 685 0323 01 .byte 0x1 - 686 0324 15010000 .4byte .LASF47 - 687 0328 01 .byte 0x1 - 688 0329 C2 .byte 0xc2 - 689 032a 01 .byte 0x1 - 690 032b 61000000 .4byte 0x61 - 691 032f 01 .byte 0x1 - 692 0330 1E .uleb128 0x1e - 693 0331 01 .byte 0x1 - 694 0332 B1010000 .4byte .LASF39 - 695 0336 01 .byte 0x1 - 696 0337 22 .byte 0x22 - 697 0338 01 .byte 0x1 - 698 0339 01 .byte 0x1 - 699 033a 1E .uleb128 0x1e - 700 033b 01 .byte 0x1 - 701 033c 3E010000 .4byte .LASF40 - 702 0340 05 .byte 0x5 - 703 0341 14 .byte 0x14 - 704 0342 01 .byte 0x1 - 705 0343 01 .byte 0x1 - 706 0344 00 .byte 0 - 707 .section .debug_abbrev,"",%progbits - 708 .Ldebug_abbrev0: - 709 0000 01 .uleb128 0x1 - 710 0001 11 .uleb128 0x11 - 711 0002 01 .byte 0x1 - 712 0003 25 .uleb128 0x25 - 713 0004 0E .uleb128 0xe - 714 0005 13 .uleb128 0x13 - 715 0006 0B .uleb128 0xb - 716 0007 03 .uleb128 0x3 - 717 0008 0E .uleb128 0xe - 718 0009 1B .uleb128 0x1b - 719 000a 0E .uleb128 0xe - 720 000b 55 .uleb128 0x55 - 721 000c 06 .uleb128 0x6 - 722 000d 11 .uleb128 0x11 - 723 000e 01 .uleb128 0x1 - 724 000f 52 .uleb128 0x52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 22 - - - 725 0010 01 .uleb128 0x1 - 726 0011 10 .uleb128 0x10 - 727 0012 06 .uleb128 0x6 - 728 0013 00 .byte 0 - 729 0014 00 .byte 0 - 730 0015 02 .uleb128 0x2 - 731 0016 24 .uleb128 0x24 - 732 0017 00 .byte 0 - 733 0018 0B .uleb128 0xb - 734 0019 0B .uleb128 0xb - 735 001a 3E .uleb128 0x3e - 736 001b 0B .uleb128 0xb - 737 001c 03 .uleb128 0x3 - 738 001d 0E .uleb128 0xe - 739 001e 00 .byte 0 - 740 001f 00 .byte 0 - 741 0020 03 .uleb128 0x3 - 742 0021 24 .uleb128 0x24 - 743 0022 00 .byte 0 - 744 0023 0B .uleb128 0xb - 745 0024 0B .uleb128 0xb - 746 0025 3E .uleb128 0x3e - 747 0026 0B .uleb128 0xb - 748 0027 03 .uleb128 0x3 - 749 0028 08 .uleb128 0x8 - 750 0029 00 .byte 0 - 751 002a 00 .byte 0 - 752 002b 04 .uleb128 0x4 - 753 002c 16 .uleb128 0x16 - 754 002d 00 .byte 0 - 755 002e 03 .uleb128 0x3 - 756 002f 0E .uleb128 0xe - 757 0030 3A .uleb128 0x3a - 758 0031 0B .uleb128 0xb - 759 0032 3B .uleb128 0x3b - 760 0033 0B .uleb128 0xb - 761 0034 49 .uleb128 0x49 - 762 0035 13 .uleb128 0x13 - 763 0036 00 .byte 0 - 764 0037 00 .byte 0 - 765 0038 05 .uleb128 0x5 - 766 0039 35 .uleb128 0x35 - 767 003a 00 .byte 0 - 768 003b 49 .uleb128 0x49 - 769 003c 13 .uleb128 0x13 - 770 003d 00 .byte 0 - 771 003e 00 .byte 0 - 772 003f 06 .uleb128 0x6 - 773 0040 16 .uleb128 0x16 - 774 0041 00 .byte 0 - 775 0042 03 .uleb128 0x3 - 776 0043 0E .uleb128 0xe - 777 0044 3A .uleb128 0x3a - 778 0045 0B .uleb128 0xb - 779 0046 3B .uleb128 0x3b - 780 0047 05 .uleb128 0x5 - 781 0048 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 23 - - - 782 0049 13 .uleb128 0x13 - 783 004a 00 .byte 0 - 784 004b 00 .byte 0 - 785 004c 07 .uleb128 0x7 - 786 004d 0F .uleb128 0xf - 787 004e 00 .byte 0 - 788 004f 0B .uleb128 0xb - 789 0050 0B .uleb128 0xb - 790 0051 49 .uleb128 0x49 - 791 0052 13 .uleb128 0x13 - 792 0053 00 .byte 0 - 793 0054 00 .byte 0 - 794 0055 08 .uleb128 0x8 - 795 0056 15 .uleb128 0x15 - 796 0057 00 .byte 0 - 797 0058 27 .uleb128 0x27 - 798 0059 0C .uleb128 0xc - 799 005a 00 .byte 0 - 800 005b 00 .byte 0 - 801 005c 09 .uleb128 0x9 - 802 005d 26 .uleb128 0x26 - 803 005e 00 .byte 0 - 804 005f 49 .uleb128 0x49 - 805 0060 13 .uleb128 0x13 - 806 0061 00 .byte 0 - 807 0062 00 .byte 0 - 808 0063 0A .uleb128 0xa - 809 0064 13 .uleb128 0x13 - 810 0065 01 .byte 0x1 - 811 0066 03 .uleb128 0x3 - 812 0067 0E .uleb128 0xe - 813 0068 0B .uleb128 0xb - 814 0069 0B .uleb128 0xb - 815 006a 3A .uleb128 0x3a - 816 006b 0B .uleb128 0xb - 817 006c 3B .uleb128 0x3b - 818 006d 0B .uleb128 0xb - 819 006e 01 .uleb128 0x1 - 820 006f 13 .uleb128 0x13 - 821 0070 00 .byte 0 - 822 0071 00 .byte 0 - 823 0072 0B .uleb128 0xb - 824 0073 0D .uleb128 0xd - 825 0074 00 .byte 0 - 826 0075 03 .uleb128 0x3 - 827 0076 0E .uleb128 0xe - 828 0077 3A .uleb128 0x3a - 829 0078 0B .uleb128 0xb - 830 0079 3B .uleb128 0x3b - 831 007a 0B .uleb128 0xb - 832 007b 49 .uleb128 0x49 - 833 007c 13 .uleb128 0x13 - 834 007d 38 .uleb128 0x38 - 835 007e 0A .uleb128 0xa - 836 007f 00 .byte 0 - 837 0080 00 .byte 0 - 838 0081 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 24 - - - 839 0082 2E .uleb128 0x2e - 840 0083 00 .byte 0 - 841 0084 3F .uleb128 0x3f - 842 0085 0C .uleb128 0xc - 843 0086 03 .uleb128 0x3 - 844 0087 0E .uleb128 0xe - 845 0088 3A .uleb128 0x3a - 846 0089 0B .uleb128 0xb - 847 008a 3B .uleb128 0x3b - 848 008b 0B .uleb128 0xb - 849 008c 27 .uleb128 0x27 - 850 008d 0C .uleb128 0xc - 851 008e 11 .uleb128 0x11 - 852 008f 01 .uleb128 0x1 - 853 0090 12 .uleb128 0x12 - 854 0091 01 .uleb128 0x1 - 855 0092 40 .uleb128 0x40 - 856 0093 0A .uleb128 0xa - 857 0094 9742 .uleb128 0x2117 - 858 0096 0C .uleb128 0xc - 859 0097 00 .byte 0 - 860 0098 00 .byte 0 - 861 0099 0D .uleb128 0xd - 862 009a 2E .uleb128 0x2e - 863 009b 01 .byte 0x1 - 864 009c 3F .uleb128 0x3f - 865 009d 0C .uleb128 0xc - 866 009e 03 .uleb128 0x3 - 867 009f 0E .uleb128 0xe - 868 00a0 3A .uleb128 0x3a - 869 00a1 0B .uleb128 0xb - 870 00a2 3B .uleb128 0x3b - 871 00a3 0B .uleb128 0xb - 872 00a4 27 .uleb128 0x27 - 873 00a5 0C .uleb128 0xc - 874 00a6 11 .uleb128 0x11 - 875 00a7 01 .uleb128 0x1 - 876 00a8 12 .uleb128 0x12 - 877 00a9 01 .uleb128 0x1 - 878 00aa 40 .uleb128 0x40 - 879 00ab 0A .uleb128 0xa - 880 00ac 9742 .uleb128 0x2117 - 881 00ae 0C .uleb128 0xc - 882 00af 01 .uleb128 0x1 - 883 00b0 13 .uleb128 0x13 - 884 00b1 00 .byte 0 - 885 00b2 00 .byte 0 - 886 00b3 0E .uleb128 0xe - 887 00b4 05 .uleb128 0x5 - 888 00b5 00 .byte 0 - 889 00b6 03 .uleb128 0x3 - 890 00b7 0E .uleb128 0xe - 891 00b8 3A .uleb128 0x3a - 892 00b9 0B .uleb128 0xb - 893 00ba 3B .uleb128 0x3b - 894 00bb 0B .uleb128 0xb - 895 00bc 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 25 - - - 896 00bd 13 .uleb128 0x13 - 897 00be 02 .uleb128 0x2 - 898 00bf 0A .uleb128 0xa - 899 00c0 00 .byte 0 - 900 00c1 00 .byte 0 - 901 00c2 0F .uleb128 0xf - 902 00c3 34 .uleb128 0x34 - 903 00c4 00 .byte 0 - 904 00c5 03 .uleb128 0x3 - 905 00c6 08 .uleb128 0x8 - 906 00c7 3A .uleb128 0x3a - 907 00c8 0B .uleb128 0xb - 908 00c9 3B .uleb128 0x3b - 909 00ca 05 .uleb128 0x5 - 910 00cb 49 .uleb128 0x49 - 911 00cc 13 .uleb128 0x13 - 912 00cd 00 .byte 0 - 913 00ce 00 .byte 0 - 914 00cf 10 .uleb128 0x10 - 915 00d0 2E .uleb128 0x2e - 916 00d1 01 .byte 0x1 - 917 00d2 3F .uleb128 0x3f - 918 00d3 0C .uleb128 0xc - 919 00d4 03 .uleb128 0x3 - 920 00d5 0E .uleb128 0xe - 921 00d6 3A .uleb128 0x3a - 922 00d7 0B .uleb128 0xb - 923 00d8 3B .uleb128 0x3b - 924 00d9 05 .uleb128 0x5 - 925 00da 27 .uleb128 0x27 - 926 00db 0C .uleb128 0xc - 927 00dc 11 .uleb128 0x11 - 928 00dd 01 .uleb128 0x1 - 929 00de 12 .uleb128 0x12 - 930 00df 01 .uleb128 0x1 - 931 00e0 40 .uleb128 0x40 - 932 00e1 06 .uleb128 0x6 - 933 00e2 9742 .uleb128 0x2117 - 934 00e4 0C .uleb128 0xc - 935 00e5 01 .uleb128 0x1 - 936 00e6 13 .uleb128 0x13 - 937 00e7 00 .byte 0 - 938 00e8 00 .byte 0 - 939 00e9 11 .uleb128 0x11 - 940 00ea 34 .uleb128 0x34 - 941 00eb 00 .byte 0 - 942 00ec 03 .uleb128 0x3 - 943 00ed 0E .uleb128 0xe - 944 00ee 3A .uleb128 0x3a - 945 00ef 0B .uleb128 0xb - 946 00f0 3B .uleb128 0x3b - 947 00f1 05 .uleb128 0x5 - 948 00f2 49 .uleb128 0x49 - 949 00f3 13 .uleb128 0x13 - 950 00f4 00 .byte 0 - 951 00f5 00 .byte 0 - 952 00f6 12 .uleb128 0x12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 26 - - - 953 00f7 0B .uleb128 0xb - 954 00f8 01 .byte 0x1 - 955 00f9 11 .uleb128 0x11 - 956 00fa 01 .uleb128 0x1 - 957 00fb 12 .uleb128 0x12 - 958 00fc 01 .uleb128 0x1 - 959 00fd 01 .uleb128 0x1 - 960 00fe 13 .uleb128 0x13 - 961 00ff 00 .byte 0 - 962 0100 00 .byte 0 - 963 0101 13 .uleb128 0x13 - 964 0102 34 .uleb128 0x34 - 965 0103 00 .byte 0 - 966 0104 03 .uleb128 0x3 - 967 0105 08 .uleb128 0x8 - 968 0106 3A .uleb128 0x3a - 969 0107 0B .uleb128 0xb - 970 0108 3B .uleb128 0x3b - 971 0109 05 .uleb128 0x5 - 972 010a 49 .uleb128 0x49 - 973 010b 13 .uleb128 0x13 - 974 010c 02 .uleb128 0x2 - 975 010d 06 .uleb128 0x6 - 976 010e 00 .byte 0 - 977 010f 00 .byte 0 - 978 0110 14 .uleb128 0x14 - 979 0111 34 .uleb128 0x34 - 980 0112 00 .byte 0 - 981 0113 03 .uleb128 0x3 - 982 0114 0E .uleb128 0xe - 983 0115 3A .uleb128 0x3a - 984 0116 0B .uleb128 0xb - 985 0117 3B .uleb128 0x3b - 986 0118 05 .uleb128 0x5 - 987 0119 49 .uleb128 0x49 - 988 011a 13 .uleb128 0x13 - 989 011b 02 .uleb128 0x2 - 990 011c 06 .uleb128 0x6 - 991 011d 00 .byte 0 - 992 011e 00 .byte 0 - 993 011f 15 .uleb128 0x15 - 994 0120 898201 .uleb128 0x4109 - 995 0123 00 .byte 0 - 996 0124 11 .uleb128 0x11 - 997 0125 01 .uleb128 0x1 - 998 0126 31 .uleb128 0x31 - 999 0127 13 .uleb128 0x13 - 1000 0128 00 .byte 0 - 1001 0129 00 .byte 0 - 1002 012a 16 .uleb128 0x16 - 1003 012b 2E .uleb128 0x2e - 1004 012c 01 .byte 0x1 - 1005 012d 3F .uleb128 0x3f - 1006 012e 0C .uleb128 0xc - 1007 012f 03 .uleb128 0x3 - 1008 0130 0E .uleb128 0xe - 1009 0131 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 27 - - - 1010 0132 0B .uleb128 0xb - 1011 0133 3B .uleb128 0x3b - 1012 0134 0B .uleb128 0xb - 1013 0135 27 .uleb128 0x27 - 1014 0136 0C .uleb128 0xc - 1015 0137 11 .uleb128 0x11 - 1016 0138 01 .uleb128 0x1 - 1017 0139 12 .uleb128 0x12 - 1018 013a 01 .uleb128 0x1 - 1019 013b 40 .uleb128 0x40 - 1020 013c 06 .uleb128 0x6 - 1021 013d 9742 .uleb128 0x2117 - 1022 013f 0C .uleb128 0xc - 1023 0140 01 .uleb128 0x1 - 1024 0141 13 .uleb128 0x13 - 1025 0142 00 .byte 0 - 1026 0143 00 .byte 0 - 1027 0144 17 .uleb128 0x17 - 1028 0145 34 .uleb128 0x34 - 1029 0146 00 .byte 0 - 1030 0147 03 .uleb128 0x3 - 1031 0148 0E .uleb128 0xe - 1032 0149 3A .uleb128 0x3a - 1033 014a 0B .uleb128 0xb - 1034 014b 3B .uleb128 0x3b - 1035 014c 0B .uleb128 0xb - 1036 014d 49 .uleb128 0x49 - 1037 014e 13 .uleb128 0x13 - 1038 014f 02 .uleb128 0x2 - 1039 0150 0A .uleb128 0xa - 1040 0151 00 .byte 0 - 1041 0152 00 .byte 0 - 1042 0153 18 .uleb128 0x18 - 1043 0154 34 .uleb128 0x34 - 1044 0155 00 .byte 0 - 1045 0156 03 .uleb128 0x3 - 1046 0157 0E .uleb128 0xe - 1047 0158 3A .uleb128 0x3a - 1048 0159 0B .uleb128 0xb - 1049 015a 3B .uleb128 0x3b - 1050 015b 0B .uleb128 0xb - 1051 015c 49 .uleb128 0x49 - 1052 015d 13 .uleb128 0x13 - 1053 015e 3F .uleb128 0x3f - 1054 015f 0C .uleb128 0xc - 1055 0160 3C .uleb128 0x3c - 1056 0161 0C .uleb128 0xc - 1057 0162 00 .byte 0 - 1058 0163 00 .byte 0 - 1059 0164 19 .uleb128 0x19 - 1060 0165 01 .uleb128 0x1 - 1061 0166 01 .byte 0x1 - 1062 0167 49 .uleb128 0x49 - 1063 0168 13 .uleb128 0x13 - 1064 0169 01 .uleb128 0x1 - 1065 016a 13 .uleb128 0x13 - 1066 016b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 28 - - - 1067 016c 00 .byte 0 - 1068 016d 1A .uleb128 0x1a - 1069 016e 21 .uleb128 0x21 - 1070 016f 00 .byte 0 - 1071 0170 49 .uleb128 0x49 - 1072 0171 13 .uleb128 0x13 - 1073 0172 2F .uleb128 0x2f - 1074 0173 0B .uleb128 0xb - 1075 0174 00 .byte 0 - 1076 0175 00 .byte 0 - 1077 0176 1B .uleb128 0x1b - 1078 0177 34 .uleb128 0x34 - 1079 0178 00 .byte 0 - 1080 0179 03 .uleb128 0x3 - 1081 017a 0E .uleb128 0xe - 1082 017b 3A .uleb128 0x3a - 1083 017c 0B .uleb128 0xb - 1084 017d 3B .uleb128 0x3b - 1085 017e 0B .uleb128 0xb - 1086 017f 49 .uleb128 0x49 - 1087 0180 13 .uleb128 0x13 - 1088 0181 3F .uleb128 0x3f - 1089 0182 0C .uleb128 0xc - 1090 0183 02 .uleb128 0x2 - 1091 0184 0A .uleb128 0xa - 1092 0185 00 .byte 0 - 1093 0186 00 .byte 0 - 1094 0187 1C .uleb128 0x1c - 1095 0188 21 .uleb128 0x21 - 1096 0189 00 .byte 0 - 1097 018a 00 .byte 0 - 1098 018b 00 .byte 0 - 1099 018c 1D .uleb128 0x1d - 1100 018d 34 .uleb128 0x34 - 1101 018e 00 .byte 0 - 1102 018f 03 .uleb128 0x3 - 1103 0190 0E .uleb128 0xe - 1104 0191 3A .uleb128 0x3a - 1105 0192 0B .uleb128 0xb - 1106 0193 3B .uleb128 0x3b - 1107 0194 05 .uleb128 0x5 - 1108 0195 49 .uleb128 0x49 - 1109 0196 13 .uleb128 0x13 - 1110 0197 3F .uleb128 0x3f - 1111 0198 0C .uleb128 0xc - 1112 0199 02 .uleb128 0x2 - 1113 019a 0A .uleb128 0xa - 1114 019b 00 .byte 0 - 1115 019c 00 .byte 0 - 1116 019d 1E .uleb128 0x1e - 1117 019e 2E .uleb128 0x2e - 1118 019f 00 .byte 0 - 1119 01a0 3F .uleb128 0x3f - 1120 01a1 0C .uleb128 0xc - 1121 01a2 03 .uleb128 0x3 - 1122 01a3 0E .uleb128 0xe - 1123 01a4 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 29 - - - 1124 01a5 0B .uleb128 0xb - 1125 01a6 3B .uleb128 0x3b - 1126 01a7 0B .uleb128 0xb - 1127 01a8 27 .uleb128 0x27 - 1128 01a9 0C .uleb128 0xc - 1129 01aa 3C .uleb128 0x3c - 1130 01ab 0C .uleb128 0xc - 1131 01ac 00 .byte 0 - 1132 01ad 00 .byte 0 - 1133 01ae 1F .uleb128 0x1f - 1134 01af 2E .uleb128 0x2e - 1135 01b0 00 .byte 0 - 1136 01b1 3F .uleb128 0x3f - 1137 01b2 0C .uleb128 0xc - 1138 01b3 03 .uleb128 0x3 - 1139 01b4 0E .uleb128 0xe - 1140 01b5 3A .uleb128 0x3a - 1141 01b6 0B .uleb128 0xb - 1142 01b7 3B .uleb128 0x3b - 1143 01b8 0B .uleb128 0xb - 1144 01b9 27 .uleb128 0x27 - 1145 01ba 0C .uleb128 0xc - 1146 01bb 49 .uleb128 0x49 - 1147 01bc 13 .uleb128 0x13 - 1148 01bd 3C .uleb128 0x3c - 1149 01be 0C .uleb128 0xc - 1150 01bf 00 .byte 0 - 1151 01c0 00 .byte 0 - 1152 01c1 00 .byte 0 - 1153 .section .debug_loc,"",%progbits - 1154 .Ldebug_loc0: - 1155 .LLST0: - 1156 0000 00000000 .4byte .LFB3 - 1157 0004 02000000 .4byte .LCFI0 - 1158 0008 0200 .2byte 0x2 - 1159 000a 7D .byte 0x7d - 1160 000b 00 .sleb128 0 - 1161 000c 02000000 .4byte .LCFI0 - 1162 0010 54000000 .4byte .LFE3 - 1163 0014 0200 .2byte 0x2 - 1164 0016 7D .byte 0x7d - 1165 0017 08 .sleb128 8 - 1166 0018 00000000 .4byte 0 - 1167 001c 00000000 .4byte 0 - 1168 .LLST1: - 1169 0020 0E000000 .4byte .LVL3 - 1170 0024 18000000 .4byte .LVL6 - 1171 0028 0100 .2byte 0x1 - 1172 002a 56 .byte 0x56 - 1173 002b 00000000 .4byte 0 - 1174 002f 00000000 .4byte 0 - 1175 .LLST2: - 1176 0033 12000000 .4byte .LVL4 - 1177 0037 18000000 .4byte .LVL6 - 1178 003b 0100 .2byte 0x1 - 1179 003d 50 .byte 0x50 - 1180 003e 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 30 - - - 1181 0042 00000000 .4byte 0 - 1182 .LLST3: - 1183 0046 16000000 .4byte .LVL5 - 1184 004a 2C000000 .4byte .LVL9 - 1185 004e 0100 .2byte 0x1 - 1186 0050 55 .byte 0x55 - 1187 0051 2C000000 .4byte .LVL9 - 1188 0055 40000000 .4byte .LVL12 - 1189 0059 0100 .2byte 0x1 - 1190 005b 50 .byte 0x50 - 1191 005c 00000000 .4byte 0 - 1192 0060 00000000 .4byte 0 - 1193 .LLST4: - 1194 0064 16000000 .4byte .LVL5 - 1195 0068 18000000 .4byte .LVL6 - 1196 006c 0200 .2byte 0x2 - 1197 006e 30 .byte 0x30 - 1198 006f 9F .byte 0x9f - 1199 0070 1E000000 .4byte .LVL7 - 1200 0074 2C000000 .4byte .LVL9 - 1201 0078 0100 .2byte 0x1 - 1202 007a 52 .byte 0x52 - 1203 007b 2C000000 .4byte .LVL9 - 1204 007f 2E000000 .4byte .LVL10 - 1205 0083 0200 .2byte 0x2 - 1206 0085 30 .byte 0x30 - 1207 0086 9F .byte 0x9f - 1208 0087 2E000000 .4byte .LVL10 - 1209 008b 40000000 .4byte .LVL12 - 1210 008f 0100 .2byte 0x1 - 1211 0091 52 .byte 0x52 - 1212 0092 00000000 .4byte 0 - 1213 0096 00000000 .4byte 0 - 1214 .LLST5: - 1215 009a 00000000 .4byte .LFB1 - 1216 009e 02000000 .4byte .LCFI1 - 1217 00a2 0200 .2byte 0x2 - 1218 00a4 7D .byte 0x7d - 1219 00a5 00 .sleb128 0 - 1220 00a6 02000000 .4byte .LCFI1 - 1221 00aa 1C000000 .4byte .LFE1 - 1222 00ae 0200 .2byte 0x2 - 1223 00b0 7D .byte 0x7d - 1224 00b1 08 .sleb128 8 - 1225 00b2 00000000 .4byte 0 - 1226 00b6 00000000 .4byte 0 - 1227 .LLST6: - 1228 00ba 00000000 .4byte .LFB4 - 1229 00be 02000000 .4byte .LCFI2 - 1230 00c2 0200 .2byte 0x2 - 1231 00c4 7D .byte 0x7d - 1232 00c5 00 .sleb128 0 - 1233 00c6 02000000 .4byte .LCFI2 - 1234 00ca 68000000 .4byte .LFE4 - 1235 00ce 0200 .2byte 0x2 - 1236 00d0 7D .byte 0x7d - 1237 00d1 08 .sleb128 8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 31 - - - 1238 00d2 00000000 .4byte 0 - 1239 00d6 00000000 .4byte 0 - 1240 .LLST7: - 1241 00da 10000000 .4byte .LVL17 - 1242 00de 12000000 .4byte .LVL18 - 1243 00e2 0200 .2byte 0x2 - 1244 00e4 30 .byte 0x30 - 1245 00e5 9F .byte 0x9f - 1246 00e6 26000000 .4byte .LVL19 - 1247 00ea 2E000000 .4byte .LVL20 - 1248 00ee 0100 .2byte 0x1 - 1249 00f0 53 .byte 0x53 - 1250 00f1 00000000 .4byte 0 - 1251 00f5 00000000 .4byte 0 - 1252 .section .debug_aranges,"",%progbits - 1253 0000 3C000000 .4byte 0x3c - 1254 0004 0200 .2byte 0x2 - 1255 0006 00000000 .4byte .Ldebug_info0 - 1256 000a 04 .byte 0x4 - 1257 000b 00 .byte 0 - 1258 000c 0000 .2byte 0 - 1259 000e 0000 .2byte 0 - 1260 0010 00000000 .4byte .LFB0 - 1261 0014 02000000 .4byte .LFE0-.LFB0 - 1262 0018 00000000 .4byte .LFB2 - 1263 001c 02000000 .4byte .LFE2-.LFB2 - 1264 0020 00000000 .4byte .LFB3 - 1265 0024 54000000 .4byte .LFE3-.LFB3 - 1266 0028 00000000 .4byte .LFB1 - 1267 002c 1C000000 .4byte .LFE1-.LFB1 - 1268 0030 00000000 .4byte .LFB4 - 1269 0034 68000000 .4byte .LFE4-.LFB4 - 1270 0038 00000000 .4byte 0 - 1271 003c 00000000 .4byte 0 - 1272 .section .debug_ranges,"",%progbits - 1273 .Ldebug_ranges0: - 1274 0000 00000000 .4byte .LFB0 - 1275 0004 02000000 .4byte .LFE0 - 1276 0008 00000000 .4byte .LFB2 - 1277 000c 02000000 .4byte .LFE2 - 1278 0010 00000000 .4byte .LFB3 - 1279 0014 54000000 .4byte .LFE3 - 1280 0018 00000000 .4byte .LFB1 - 1281 001c 1C000000 .4byte .LFE1 - 1282 0020 00000000 .4byte .LFB4 - 1283 0024 68000000 .4byte .LFE4 - 1284 0028 00000000 .4byte 0 - 1285 002c 00000000 .4byte 0 - 1286 .section .debug_line,"",%progbits - 1287 .Ldebug_line0: - 1288 0000 98010000 .section .debug_str,"MS",%progbits,1 - 1288 0200F000 - 1288 00000201 - 1288 FB0E0D00 - 1288 01010101 - 1289 .LASF42: - 1290 0000 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\Cm3Start.c\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 32 - - - 1290 6E657261 - 1290 7465645F - 1290 536F7572 - 1290 63655C50 - 1291 .LASF15: - 1292 0024 72656733 .ascii "reg32\000" - 1292 3200 - 1293 .LASF18: - 1294 002a 73697A65 .ascii "size_t\000" - 1294 5F7400 - 1295 .LASF34: - 1296 0031 43795261 .ascii "CyRamVectors\000" - 1296 6D566563 - 1296 746F7273 - 1296 00 - 1297 .LASF25: - 1298 003e 53746172 .ascii "Start_c\000" - 1298 745F6300 - 1299 .LASF29: - 1300 0046 636F756E .ascii "count\000" - 1300 7400 - 1301 .LASF3: - 1302 004c 73686F72 .ascii "short unsigned int\000" - 1302 7420756E - 1302 7369676E - 1302 65642069 - 1302 6E7400 - 1303 .LASF36: - 1304 005f 5F5F6379 .ascii "__cy_region_num\000" - 1304 5F726567 - 1304 696F6E5F - 1304 6E756D00 - 1305 .LASF20: - 1306 006f 696E6974 .ascii "init\000" - 1306 00 - 1307 .LASF46: - 1308 0074 73746174 .ascii "status\000" - 1308 757300 - 1309 .LASF23: - 1310 007b 7A65726F .ascii "zero_size\000" - 1310 5F73697A - 1310 6500 - 1311 .LASF11: - 1312 0085 666C6F61 .ascii "float\000" - 1312 7400 - 1313 .LASF21: - 1314 008b 64617461 .ascii "data\000" - 1314 00 - 1315 .LASF1: - 1316 0090 756E7369 .ascii "unsigned char\000" - 1316 676E6564 - 1316 20636861 - 1316 7200 - 1317 .LASF37: - 1318 009e 526F6D56 .ascii "RomVectors\000" - 1318 6563746F - 1318 727300 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 33 - - - 1319 .LASF5: - 1320 00a9 6C6F6E67 .ascii "long unsigned int\000" - 1320 20756E73 - 1320 69676E65 - 1320 6420696E - 1320 7400 - 1321 .LASF43: - 1322 00bb 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 1322 43534932 - 1322 53445C73 - 1322 6F667477 - 1322 6172655C - 1323 00ea 6E00 .ascii "n\000" - 1324 .LASF9: - 1325 00ec 75696E74 .ascii "uint8\000" - 1325 3800 - 1326 .LASF30: - 1327 00f2 52657365 .ascii "Reset\000" - 1327 7400 - 1328 .LASF24: - 1329 00f8 5F657869 .ascii "_exit\000" - 1329 7400 - 1330 .LASF45: - 1331 00fe 496E7444 .ascii "IntDefaultHandler\000" - 1331 65666175 - 1331 6C744861 - 1331 6E646C65 - 1331 7200 - 1332 .LASF27: - 1333 0110 72707472 .ascii "rptr\000" - 1333 00 - 1334 .LASF47: - 1335 0115 6D61696E .ascii "main\000" - 1335 00 - 1336 .LASF31: - 1337 011a 696E6974 .ascii "initialize_psoc\000" - 1337 69616C69 - 1337 7A655F70 - 1337 736F6300 - 1338 .LASF10: - 1339 012a 75696E74 .ascii "uint32\000" - 1339 333200 - 1340 .LASF8: - 1341 0131 756E7369 .ascii "unsigned int\000" - 1341 676E6564 - 1341 20696E74 - 1341 00 - 1342 .LASF40: - 1343 013e 63796669 .ascii "cyfitter_cfg\000" - 1343 74746572 - 1343 5F636667 - 1343 00 - 1344 .LASF7: - 1345 014b 6C6F6E67 .ascii "long long unsigned int\000" - 1345 206C6F6E - 1345 6720756E - 1345 7369676E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 34 - - - 1345 65642069 - 1346 .LASF28: - 1347 0162 6C696D69 .ascii "limit\000" - 1347 7400 - 1348 .LASF16: - 1349 0168 63796973 .ascii "cyisraddress\000" - 1349 72616464 - 1349 72657373 - 1349 00 - 1350 .LASF22: - 1351 0175 696E6974 .ascii "init_size\000" - 1351 5F73697A - 1351 6500 - 1352 .LASF19: - 1353 017f 5F5F6379 .ascii "__cy_byte_align8\000" - 1353 5F627974 - 1353 655F616C - 1353 69676E38 - 1353 00 - 1354 .LASF14: - 1355 0190 72656738 .ascii "reg8\000" - 1355 00 - 1356 .LASF17: - 1357 0195 73697A65 .ascii "sizetype\000" - 1357 74797065 - 1357 00 - 1358 .LASF6: - 1359 019e 6C6F6E67 .ascii "long long int\000" - 1359 206C6F6E - 1359 6720696E - 1359 7400 - 1360 .LASF13: - 1361 01ac 63686172 .ascii "char\000" - 1361 00 - 1362 .LASF39: - 1363 01b1 43794274 .ascii "CyBtldr_CheckLaunch\000" - 1363 6C64725F - 1363 43686563 - 1363 6B4C6175 - 1363 6E636800 - 1364 .LASF2: - 1365 01c5 73686F72 .ascii "short int\000" - 1365 7420696E - 1365 7400 - 1366 .LASF32: - 1367 01cf 63795379 .ascii "cySysNoInitDataValid\000" - 1367 734E6F49 - 1367 6E697444 - 1367 61746156 - 1367 616C6964 - 1368 .LASF41: - 1369 01e4 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 1369 4320342E - 1369 372E3320 - 1369 32303133 - 1369 30333132 - 1370 0217 616E6368 .ascii "anch revision 196615]\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccFLxuTR.s page 35 - - - 1370 20726576 - 1370 6973696F - 1370 6E203139 - 1370 36363135 - 1371 .LASF38: - 1372 022d 5F5F6C69 .ascii "__libc_init_array\000" - 1372 62635F69 - 1372 6E69745F - 1372 61727261 - 1372 7900 - 1373 .LASF4: - 1374 023f 6C6F6E67 .ascii "long int\000" - 1374 20696E74 - 1374 00 - 1375 .LASF33: - 1376 0248 43795265 .ascii "CyResetStatus\000" - 1376 73657453 - 1376 74617475 - 1376 7300 - 1377 .LASF0: - 1378 0256 7369676E .ascii "signed char\000" - 1378 65642063 - 1378 68617200 - 1379 .LASF12: - 1380 0262 646F7562 .ascii "double\000" - 1380 6C6500 - 1381 .LASF35: - 1382 0269 5F5F6379 .ascii "__cy_regions\000" - 1382 5F726567 - 1382 696F6E73 - 1382 00 - 1383 .LASF26: - 1384 0276 72656769 .ascii "regions\000" - 1384 6F6E7300 - 1385 .LASF44: - 1386 027e 5F5F6379 .ascii "__cy_region\000" - 1386 5F726567 - 1386 696F6E00 - 1387 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/Cm3Start.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/Cm3Start.o deleted file mode 100755 index 75da190c6c97a4ae3a9756af88a70248fbf7b84a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 7956 zcmeHMdvIJ;9X{vYO|s2y(ma|rO<&t2^Z|5}G<{oX+7#Nf1!B@x8MZF_xJgzvyYcQ# zZ4g8rii#u5Ac%-K!xTr*e{|>{0$PR zgxuWJ|LTb|@0~uw=ky72{0thq2_FmX4ejoju&y#%ar}cz#K2>R#X$I2)1Ici9ar5w zG4MCx-gA}cvM;#nc*CBCp^=kaO$~c?;4S-mFZk;Vk)g=m@R7(+`&7M(Q@>kuT33aC zB94pD2Q|^R#2?g9^oy}chG)sO`v34hJ_FlrAuKhq5`q9hT_jPDtn60WNetUiM29 zB(H~1{+zwme-1q~$zQIAB*L)rX_8i#h}=r<8J`P9rs?wR%aB=J;mBvHd(P*g==VKQB$kE*0bw@_fl|#b-f^ zww-vjqYT=1gXjc-@hw8MId3bHb3I?ai?@6op@dkB=N_`7FluWA)l2Ud5F98*)WI(A z_eaF!AHgHP21;s|^1v23yAK8mlGtq|#8 zbKZv2Qn`i^o|JN#Y-4gysO6GNCSps+osj%4T_9V{622T-11=wpotIrdlDa zZV`!G1R<(WlVOZ$zOWm&L_QK3YK8N9L8#TT8Zvcr;YK3dCRRqV3M-UNeXFz^BN2K^ zC?gH!Fq=>f(YV+a_2aILHp><{Q2&h`aBhgpbI2K>v8EirLV&sJgdIk3l|ob5t42qw zMKpRf!;IN0vz7?P-6AP(t+-nl`n-x6*|sm=C`GgEgW>#g=*X$^M;?7LE*Q_*1f)|E2|<6_VR~ zdwTjv)W+1?E-ADd;$W>#zAjwbQ#P<_dzC2JV}%3JUzgI3#4hi%>H@<1ZMov3m!5a4 zUB7kPlCCa061NsW{b37`2#nu##{1WbQtlcj>0!VlsmX&*1`}TrYKD>-ktt5&_r5fN zS&vN@O1bfZla28TkW6M~lJL(J3(3Otq{tO=u=7&hbV*#}xWy!+im`k#<%w*{ONp{~ zW+LT^kz%>4e6cWI9sA>35~G8oLu*HOCQ8LI?=vaaDGLsa?nv$^7Ci*cI&M5OlPwj* zG&0&GMx2s^#GE6@WT@cnbjDKCd2e^Bkj*=;aHl+1Or~-Lm1-`P=crk2${W*APLRV3 zF1b({o}FesH;JAyGr5wR%4S);DzraxH9zSY&q<=E@xms7x!Rw@IIN@Zj-j|v#WG3{)`w5NClrAd{VVZYhIu9ahR_wa$Kx{Ck>N~c!x39mqzi(}9 zmFwi4RLNN#yK?);r9IAM+Cf!k*Q`r!T$6TF2pe;q!?_YxF4nhs!-l@~hp?L1I+-LF zF`07R)Qq1XJ4RV>UQrNST3rEZ4YS4RblwS8LW!e9+)_{|#IC`?EwNQhc7L&$FU7`+ zZVai#F4n2VhTUQY(}%)a{ofeP_O&>XQr!DOt^!#zi1Kxgthuyb)YjKsI>%}W&BHxl zf!&UqT8CU3>crlU!jRu?*sj+$MjI3lk!sxQ)SE`0hrek&Q@1yU2X3+kzJ^d$I-av1 zrsLTg)QNa$X3|Tgfu8H*grP71PsG($ila7;u@j)-T9lamfAHIAB!r##QirKi2>C}T(tNB_Uu7Qv9~ zi0h7O>ogirXFr(bcxb0?xxm?W)UmC^6UOte?EFhab-$)B#xXQ6`N8})1av_=)@9Ic z6L`u@Gq(iZYUUUraB+taF<=)S&H?S1{}`TNysv^c_Xv>XTSppnFy204=H<@JGe5IT42aA0*Fgv4U5j|ki}AS6 zO@7RW`I&j22ZrM?&BQ(mK``FUf%#)TCf>uK8PDX`{UP~1Hp@;WKu6Ow{S5e^n1L@g z!2`NqfDYz&6!{&&pg3M$Cry683HX2%7i00C2y|e`H)q+^Ve;OmgKoy|4e-H!7cYST zO7`1^$Mj2I;{#GT4Jg8Y8QtG~RavtbH*Zr13m`S|qHr)iG#)?_v@^}0T2Ac827qaxmV#h__0|va{f5ytWJh2}d(*bU?qy8G+vA9r40K>fVqkdUPgwk6ICew60uSRg;bEV_c$=^Ye}v356VLDlgYuAg=ZujP z?Wz%z4`xC>*dzH+)o*=eR{W^8sF|g&33dnn+FANqF&7s5%2wD^fo9|6;h9ruVP!wB zEWqXpG#e*gwSB#^-&wZdiCAeitl591ReRewF{|}Fu`12R%2ex{)R{pGuA8hn5jlU& zv+P+Vm1dW{eVHvPBc;SvCqvMlJG;_swKIb}cUGn0uRyAQ)|202hEQmW**uCn&}^|x z{a%}zZNVrvLvQ#_tp7I6?+3PEy>|ut+3yvz_)iA-80bQPr@i`vB#^(QEvSbZX6f$) z&;BQrzFs^qOaG%;{NtKu>}IU*)0(He8UJ|Bo2KR|@J-n5iS8`EYR>VwarR}?zh;`t z<=I~m>U(SUr(%FF>5sN^ef!M5h*o`)RezNPz9y@_VpUJL*k-QAZvX~dzgh_Hllt@h z{b*g_pZC^<{ym~T?%yBkacJ{SRo|=aP@==&EgV){a|`EEf{4FeW{Lb;5!#9#AFXx% z-mupA_X_%P*AcnqZ(h(_*;!{XnaTGDUA{7$6u&%rN)nH+)2cd zxmzQDlbFvH#5y4kY5bIy-=y(YB7Pul(|89F_la+7{ev2hY5k8iK1+n%?=`+kTrR|0 zntxaGr!;Tl=Yjo1HLfDUzK4iK>({uEh`8G|zenQ%BJ2+lad4(IIz-s>-bK7l%WomV z{thDQ=x)s))A$4ti~pkLU(+b@vqitTM11geXuezHT8&#ZVtLfKcxJ2dY2^MVAJf>a zQPmsd8#RB4#yuK8rtyGAwGUv=Gm7z4y#YPVtGWY!z2?-{JWcJipV7!i44%d7r-iST2iotiITm^|#& zz6F|j!_lDpRXiwphI1S-BI2m|1fC*~I1LgA|0P89do>aEpC`gj#p}}f!Cv`;SNXvY ZM+^UhOKc*-e^~STiHMWeyqbT+`zKHeqwD|x diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst deleted file mode 100755 index 190593b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.lst +++ /dev/null @@ -1,12936 +0,0 @@ -ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 1 - - - 1 /******************************************************************************* - 2 * File Name: CyBootAsmGnu.s - 3 * Version 4.0 - 4 * - 5 * Description: - 6 * Assembly routines for GNU as. - 7 * - 8 ******************************************************************************** - 9 * Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. - 10 * You may use this file only in accordance with the license, terms, conditions, - 11 * disclaimers, and limitations in the end user license agreement accompanying - 12 * the software package with which this file was provided. - 13 *******************************************************************************/ - 14 - 15 .include "cyfittergnu.inc" - 1 .ifndef INCLUDED_CYFITTERGNU_INC - 2 .set INCLUDED_CYFITTERGNU_INC, 1 - 3 .include "cydevicegnu.inc" - 1 /******************************************************************************* - 2 * FILENAME: cydevicegnu.inc - 3 * OBSOLETE: Do not use this file. Use the _trm version instead. - 4 * PSoC Creator 3.0 Component Pack 7 - 5 * - 6 * DESCRIPTION: - 7 * This file provides all of the address values for the entire PSoC device. - 8 * This file is automatically generated by PSoC Creator. - 9 * - 10 ******************************************************************************** - 11 * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12 * You may use this file only in accordance with the license, terms, conditions, - 13 * disclaimers, and limitations in the end user license agreement accompanying - 14 * the software package with which this file was provided. - 15 ********************************************************************************/ - 16 - 17 .set CYDEV_FLASH_BASE, 0x00000000 - 18 .set CYDEV_FLASH_SIZE, 0x00020000 - 19 .set CYDEV_FLASH_DATA_MBASE, 0x00000000 - 20 .set CYDEV_FLASH_DATA_MSIZE, 0x00020000 - 21 .set CYDEV_SRAM_BASE, 0x1fffc000 - 22 .set CYDEV_SRAM_SIZE, 0x00008000 - 23 .set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000 - 24 .set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000 - 25 .set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000 - 26 .set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000 - 27 .set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000 - 28 .set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000 - 29 .set CYDEV_SRAM_CODE_MBASE, 0x1fffc000 - 30 .set CYDEV_SRAM_CODE_MSIZE, 0x00004000 - 31 .set CYDEV_SRAM_DATA_MBASE, 0x20000000 - 32 .set CYDEV_SRAM_DATA_MSIZE, 0x00004000 - 33 .set CYDEV_SRAM_DATA16K_MBASE, 0x20001000 - 34 .set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000 - 35 .set CYDEV_SRAM_DATA32K_MBASE, 0x20002000 - 36 .set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000 - 37 .set CYDEV_SRAM_DATA64K_MBASE, 0x20004000 - 38 .set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000 - 39 .set CYDEV_DMA_BASE, 0x20008000 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 2 - - - 40 .set CYDEV_DMA_SIZE, 0x00008000 - 41 .set CYDEV_DMA_SRAM64K_MBASE, 0x20008000 - 42 .set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000 - 43 .set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000 - 44 .set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000 - 45 .set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000 - 46 .set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000 - 47 .set CYDEV_DMA_SRAM_MBASE, 0x2000f000 - 48 .set CYDEV_DMA_SRAM_MSIZE, 0x00001000 - 49 .set CYDEV_CLKDIST_BASE, 0x40004000 - 50 .set CYDEV_CLKDIST_SIZE, 0x00000110 - 51 .set CYDEV_CLKDIST_CR, 0x40004000 - 52 .set CYDEV_CLKDIST_LD, 0x40004001 - 53 .set CYDEV_CLKDIST_WRK0, 0x40004002 - 54 .set CYDEV_CLKDIST_WRK1, 0x40004003 - 55 .set CYDEV_CLKDIST_MSTR0, 0x40004004 - 56 .set CYDEV_CLKDIST_MSTR1, 0x40004005 - 57 .set CYDEV_CLKDIST_BCFG0, 0x40004006 - 58 .set CYDEV_CLKDIST_BCFG1, 0x40004007 - 59 .set CYDEV_CLKDIST_BCFG2, 0x40004008 - 60 .set CYDEV_CLKDIST_UCFG, 0x40004009 - 61 .set CYDEV_CLKDIST_DLY0, 0x4000400a - 62 .set CYDEV_CLKDIST_DLY1, 0x4000400b - 63 .set CYDEV_CLKDIST_DMASK, 0x40004010 - 64 .set CYDEV_CLKDIST_AMASK, 0x40004014 - 65 .set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 - 66 .set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 - 67 .set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080 - 68 .set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081 - 69 .set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082 - 70 .set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 - 71 .set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 - 72 .set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084 - 73 .set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085 - 74 .set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086 - 75 .set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 - 76 .set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 - 77 .set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088 - 78 .set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089 - 79 .set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a - 80 .set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c - 81 .set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 - 82 .set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c - 83 .set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d - 84 .set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e - 85 .set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 - 86 .set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 - 87 .set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090 - 88 .set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091 - 89 .set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092 - 90 .set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 - 91 .set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 - 92 .set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094 - 93 .set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095 - 94 .set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096 - 95 .set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 - 96 .set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 3 - - - 97 .set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098 - 98 .set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099 - 99 .set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a - 100 .set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c - 101 .set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 - 102 .set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c - 103 .set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d - 104 .set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e - 105 .set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 - 106 .set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 - 107 .set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100 - 108 .set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101 - 109 .set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102 - 110 .set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103 - 111 .set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 - 112 .set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 - 113 .set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104 - 114 .set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105 - 115 .set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106 - 116 .set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107 - 117 .set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 - 118 .set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 - 119 .set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108 - 120 .set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109 - 121 .set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a - 122 .set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b - 123 .set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c - 124 .set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 - 125 .set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c - 126 .set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d - 127 .set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e - 128 .set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f - 129 .set CYDEV_FASTCLK_BASE, 0x40004200 - 130 .set CYDEV_FASTCLK_SIZE, 0x00000026 - 131 .set CYDEV_FASTCLK_IMO_BASE, 0x40004200 - 132 .set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 - 133 .set CYDEV_FASTCLK_IMO_CR, 0x40004200 - 134 .set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 - 135 .set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 - 136 .set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210 - 137 .set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212 - 138 .set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213 - 139 .set CYDEV_FASTCLK_PLL_BASE, 0x40004220 - 140 .set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 - 141 .set CYDEV_FASTCLK_PLL_CFG0, 0x40004220 - 142 .set CYDEV_FASTCLK_PLL_CFG1, 0x40004221 - 143 .set CYDEV_FASTCLK_PLL_P, 0x40004222 - 144 .set CYDEV_FASTCLK_PLL_Q, 0x40004223 - 145 .set CYDEV_FASTCLK_PLL_SR, 0x40004225 - 146 .set CYDEV_SLOWCLK_BASE, 0x40004300 - 147 .set CYDEV_SLOWCLK_SIZE, 0x0000000b - 148 .set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 - 149 .set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 - 150 .set CYDEV_SLOWCLK_ILO_CR0, 0x40004300 - 151 .set CYDEV_SLOWCLK_ILO_CR1, 0x40004301 - 152 .set CYDEV_SLOWCLK_X32_BASE, 0x40004308 - 153 .set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 4 - - - 154 .set CYDEV_SLOWCLK_X32_CR, 0x40004308 - 155 .set CYDEV_SLOWCLK_X32_CFG, 0x40004309 - 156 .set CYDEV_SLOWCLK_X32_TST, 0x4000430a - 157 .set CYDEV_BOOST_BASE, 0x40004320 - 158 .set CYDEV_BOOST_SIZE, 0x00000007 - 159 .set CYDEV_BOOST_CR0, 0x40004320 - 160 .set CYDEV_BOOST_CR1, 0x40004321 - 161 .set CYDEV_BOOST_CR2, 0x40004322 - 162 .set CYDEV_BOOST_CR3, 0x40004323 - 163 .set CYDEV_BOOST_SR, 0x40004324 - 164 .set CYDEV_BOOST_CR4, 0x40004325 - 165 .set CYDEV_BOOST_SR2, 0x40004326 - 166 .set CYDEV_PWRSYS_BASE, 0x40004330 - 167 .set CYDEV_PWRSYS_SIZE, 0x00000002 - 168 .set CYDEV_PWRSYS_CR0, 0x40004330 - 169 .set CYDEV_PWRSYS_CR1, 0x40004331 - 170 .set CYDEV_PM_BASE, 0x40004380 - 171 .set CYDEV_PM_SIZE, 0x00000057 - 172 .set CYDEV_PM_TW_CFG0, 0x40004380 - 173 .set CYDEV_PM_TW_CFG1, 0x40004381 - 174 .set CYDEV_PM_TW_CFG2, 0x40004382 - 175 .set CYDEV_PM_WDT_CFG, 0x40004383 - 176 .set CYDEV_PM_WDT_CR, 0x40004384 - 177 .set CYDEV_PM_INT_SR, 0x40004390 - 178 .set CYDEV_PM_MODE_CFG0, 0x40004391 - 179 .set CYDEV_PM_MODE_CFG1, 0x40004392 - 180 .set CYDEV_PM_MODE_CSR, 0x40004393 - 181 .set CYDEV_PM_USB_CR0, 0x40004394 - 182 .set CYDEV_PM_WAKEUP_CFG0, 0x40004398 - 183 .set CYDEV_PM_WAKEUP_CFG1, 0x40004399 - 184 .set CYDEV_PM_WAKEUP_CFG2, 0x4000439a - 185 .set CYDEV_PM_ACT_BASE, 0x400043a0 - 186 .set CYDEV_PM_ACT_SIZE, 0x0000000e - 187 .set CYDEV_PM_ACT_CFG0, 0x400043a0 - 188 .set CYDEV_PM_ACT_CFG1, 0x400043a1 - 189 .set CYDEV_PM_ACT_CFG2, 0x400043a2 - 190 .set CYDEV_PM_ACT_CFG3, 0x400043a3 - 191 .set CYDEV_PM_ACT_CFG4, 0x400043a4 - 192 .set CYDEV_PM_ACT_CFG5, 0x400043a5 - 193 .set CYDEV_PM_ACT_CFG6, 0x400043a6 - 194 .set CYDEV_PM_ACT_CFG7, 0x400043a7 - 195 .set CYDEV_PM_ACT_CFG8, 0x400043a8 - 196 .set CYDEV_PM_ACT_CFG9, 0x400043a9 - 197 .set CYDEV_PM_ACT_CFG10, 0x400043aa - 198 .set CYDEV_PM_ACT_CFG11, 0x400043ab - 199 .set CYDEV_PM_ACT_CFG12, 0x400043ac - 200 .set CYDEV_PM_ACT_CFG13, 0x400043ad - 201 .set CYDEV_PM_STBY_BASE, 0x400043b0 - 202 .set CYDEV_PM_STBY_SIZE, 0x0000000e - 203 .set CYDEV_PM_STBY_CFG0, 0x400043b0 - 204 .set CYDEV_PM_STBY_CFG1, 0x400043b1 - 205 .set CYDEV_PM_STBY_CFG2, 0x400043b2 - 206 .set CYDEV_PM_STBY_CFG3, 0x400043b3 - 207 .set CYDEV_PM_STBY_CFG4, 0x400043b4 - 208 .set CYDEV_PM_STBY_CFG5, 0x400043b5 - 209 .set CYDEV_PM_STBY_CFG6, 0x400043b6 - 210 .set CYDEV_PM_STBY_CFG7, 0x400043b7 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 5 - - - 211 .set CYDEV_PM_STBY_CFG8, 0x400043b8 - 212 .set CYDEV_PM_STBY_CFG9, 0x400043b9 - 213 .set CYDEV_PM_STBY_CFG10, 0x400043ba - 214 .set CYDEV_PM_STBY_CFG11, 0x400043bb - 215 .set CYDEV_PM_STBY_CFG12, 0x400043bc - 216 .set CYDEV_PM_STBY_CFG13, 0x400043bd - 217 .set CYDEV_PM_AVAIL_BASE, 0x400043c0 - 218 .set CYDEV_PM_AVAIL_SIZE, 0x00000017 - 219 .set CYDEV_PM_AVAIL_CR0, 0x400043c0 - 220 .set CYDEV_PM_AVAIL_CR1, 0x400043c1 - 221 .set CYDEV_PM_AVAIL_CR2, 0x400043c2 - 222 .set CYDEV_PM_AVAIL_CR3, 0x400043c3 - 223 .set CYDEV_PM_AVAIL_CR4, 0x400043c4 - 224 .set CYDEV_PM_AVAIL_CR5, 0x400043c5 - 225 .set CYDEV_PM_AVAIL_CR6, 0x400043c6 - 226 .set CYDEV_PM_AVAIL_SR0, 0x400043d0 - 227 .set CYDEV_PM_AVAIL_SR1, 0x400043d1 - 228 .set CYDEV_PM_AVAIL_SR2, 0x400043d2 - 229 .set CYDEV_PM_AVAIL_SR3, 0x400043d3 - 230 .set CYDEV_PM_AVAIL_SR4, 0x400043d4 - 231 .set CYDEV_PM_AVAIL_SR5, 0x400043d5 - 232 .set CYDEV_PM_AVAIL_SR6, 0x400043d6 - 233 .set CYDEV_PICU_BASE, 0x40004500 - 234 .set CYDEV_PICU_SIZE, 0x000000b0 - 235 .set CYDEV_PICU_INTTYPE_BASE, 0x40004500 - 236 .set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 - 237 .set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 - 238 .set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 - 239 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500 - 240 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501 - 241 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502 - 242 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503 - 243 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504 - 244 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505 - 245 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506 - 246 .set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507 - 247 .set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 - 248 .set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 - 249 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508 - 250 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509 - 251 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a - 252 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b - 253 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c - 254 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d - 255 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e - 256 .set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f - 257 .set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 - 258 .set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 - 259 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510 - 260 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511 - 261 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512 - 262 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513 - 263 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514 - 264 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515 - 265 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516 - 266 .set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517 - 267 .set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 6 - - - 268 .set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 - 269 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518 - 270 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519 - 271 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a - 272 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b - 273 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c - 274 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d - 275 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e - 276 .set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f - 277 .set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 - 278 .set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 - 279 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520 - 280 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521 - 281 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522 - 282 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523 - 283 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524 - 284 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525 - 285 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526 - 286 .set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527 - 287 .set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 - 288 .set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 - 289 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528 - 290 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529 - 291 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a - 292 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b - 293 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c - 294 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d - 295 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e - 296 .set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f - 297 .set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 - 298 .set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 - 299 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530 - 300 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531 - 301 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532 - 302 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533 - 303 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534 - 304 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535 - 305 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536 - 306 .set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537 - 307 .set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 - 308 .set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 - 309 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560 - 310 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561 - 311 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562 - 312 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563 - 313 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564 - 314 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565 - 315 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566 - 316 .set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567 - 317 .set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 - 318 .set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 - 319 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578 - 320 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579 - 321 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a - 322 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b - 323 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c - 324 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 7 - - - 325 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e - 326 .set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f - 327 .set CYDEV_PICU_STAT_BASE, 0x40004580 - 328 .set CYDEV_PICU_STAT_SIZE, 0x00000010 - 329 .set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 - 330 .set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 - 331 .set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580 - 332 .set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 - 333 .set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 - 334 .set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581 - 335 .set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 - 336 .set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 - 337 .set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582 - 338 .set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 - 339 .set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 - 340 .set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583 - 341 .set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 - 342 .set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 - 343 .set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584 - 344 .set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 - 345 .set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 - 346 .set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585 - 347 .set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 - 348 .set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 - 349 .set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586 - 350 .set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c - 351 .set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 - 352 .set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c - 353 .set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f - 354 .set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 - 355 .set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f - 356 .set CYDEV_PICU_SNAP_BASE, 0x40004590 - 357 .set CYDEV_PICU_SNAP_SIZE, 0x00000010 - 358 .set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 - 359 .set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 - 360 .set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590 - 361 .set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 - 362 .set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 - 363 .set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591 - 364 .set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 - 365 .set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 - 366 .set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592 - 367 .set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 - 368 .set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 - 369 .set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593 - 370 .set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 - 371 .set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 - 372 .set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594 - 373 .set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 - 374 .set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 - 375 .set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595 - 376 .set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 - 377 .set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 - 378 .set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596 - 379 .set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c - 380 .set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 - 381 .set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 8 - - - 382 .set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f - 383 .set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 - 384 .set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f - 385 .set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 - 386 .set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 - 387 .set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 - 388 .set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 - 389 .set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0 - 390 .set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 - 391 .set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 - 392 .set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1 - 393 .set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 - 394 .set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 - 395 .set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2 - 396 .set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 - 397 .set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 - 398 .set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3 - 399 .set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 - 400 .set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 - 401 .set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4 - 402 .set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 - 403 .set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 - 404 .set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5 - 405 .set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 - 406 .set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 - 407 .set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6 - 408 .set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac - 409 .set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 - 410 .set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac - 411 .set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af - 412 .set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 - 413 .set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af - 414 .set CYDEV_MFGCFG_BASE, 0x40004600 - 415 .set CYDEV_MFGCFG_SIZE, 0x000000ed - 416 .set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 - 417 .set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 - 418 .set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 - 419 .set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 - 420 .set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608 - 421 .set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 - 422 .set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 - 423 .set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609 - 424 .set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a - 425 .set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 - 426 .set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a - 427 .set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b - 428 .set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 - 429 .set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b - 430 .set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 - 431 .set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 - 432 .set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610 - 433 .set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 - 434 .set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 - 435 .set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611 - 436 .set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 - 437 .set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 - 438 .set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 9 - - - 439 .set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 - 440 .set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 - 441 .set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614 - 442 .set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 - 443 .set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 - 444 .set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616 - 445 .set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 - 446 .set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 - 447 .set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620 - 448 .set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621 - 449 .set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 - 450 .set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 - 451 .set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622 - 452 .set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623 - 453 .set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 - 454 .set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 - 455 .set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624 - 456 .set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625 - 457 .set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 - 458 .set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 - 459 .set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626 - 460 .set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627 - 461 .set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 - 462 .set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 - 463 .set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630 - 464 .set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631 - 465 .set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 - 466 .set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 - 467 .set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632 - 468 .set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633 - 469 .set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 - 470 .set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 - 471 .set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634 - 472 .set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635 - 473 .set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 - 474 .set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 - 475 .set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636 - 476 .set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637 - 477 .set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 - 478 .set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b - 479 .set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680 - 480 .set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681 - 481 .set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682 - 482 .set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683 - 483 .set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684 - 484 .set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685 - 485 .set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686 - 486 .set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687 - 487 .set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688 - 488 .set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689 - 489 .set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a - 490 .set CYDEV_MFGCFG_ILO_BASE, 0x40004690 - 491 .set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 - 492 .set CYDEV_MFGCFG_ILO_TR0, 0x40004690 - 493 .set CYDEV_MFGCFG_ILO_TR1, 0x40004691 - 494 .set CYDEV_MFGCFG_X32_BASE, 0x40004698 - 495 .set CYDEV_MFGCFG_X32_SIZE, 0x00000001 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 10 - - - 496 .set CYDEV_MFGCFG_X32_TR, 0x40004698 - 497 .set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 - 498 .set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 - 499 .set CYDEV_MFGCFG_IMO_TR0, 0x400046a0 - 500 .set CYDEV_MFGCFG_IMO_TR1, 0x400046a1 - 501 .set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2 - 502 .set CYDEV_MFGCFG_IMO_C36M, 0x400046a3 - 503 .set CYDEV_MFGCFG_IMO_TR2, 0x400046a4 - 504 .set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 - 505 .set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 - 506 .set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8 - 507 .set CYDEV_MFGCFG_DLY, 0x400046c0 - 508 .set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 - 509 .set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d - 510 .set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2 - 511 .set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 - 512 .set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 - 513 .set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4 - 514 .set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5 - 515 .set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8 - 516 .set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea - 517 .set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 - 518 .set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea - 519 .set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec - 520 .set CYDEV_RESET_BASE, 0x400046f0 - 521 .set CYDEV_RESET_SIZE, 0x0000000f - 522 .set CYDEV_RESET_IPOR_CR0, 0x400046f0 - 523 .set CYDEV_RESET_IPOR_CR1, 0x400046f1 - 524 .set CYDEV_RESET_IPOR_CR2, 0x400046f2 - 525 .set CYDEV_RESET_IPOR_CR3, 0x400046f3 - 526 .set CYDEV_RESET_CR0, 0x400046f4 - 527 .set CYDEV_RESET_CR1, 0x400046f5 - 528 .set CYDEV_RESET_CR2, 0x400046f6 - 529 .set CYDEV_RESET_CR3, 0x400046f7 - 530 .set CYDEV_RESET_CR4, 0x400046f8 - 531 .set CYDEV_RESET_CR5, 0x400046f9 - 532 .set CYDEV_RESET_SR0, 0x400046fa - 533 .set CYDEV_RESET_SR1, 0x400046fb - 534 .set CYDEV_RESET_SR2, 0x400046fc - 535 .set CYDEV_RESET_SR3, 0x400046fd - 536 .set CYDEV_RESET_TR, 0x400046fe - 537 .set CYDEV_SPC_BASE, 0x40004700 - 538 .set CYDEV_SPC_SIZE, 0x00000100 - 539 .set CYDEV_SPC_FM_EE_CR, 0x40004700 - 540 .set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701 - 541 .set CYDEV_SPC_EE_SCR, 0x40004702 - 542 .set CYDEV_SPC_EE_ERR, 0x40004703 - 543 .set CYDEV_SPC_CPU_DATA, 0x40004720 - 544 .set CYDEV_SPC_DMA_DATA, 0x40004721 - 545 .set CYDEV_SPC_SR, 0x40004722 - 546 .set CYDEV_SPC_CR, 0x40004723 - 547 .set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 - 548 .set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 - 549 .set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 - 550 .set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 - 551 .set CYDEV_CACHE_BASE, 0x40004800 - 552 .set CYDEV_CACHE_SIZE, 0x0000009c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 11 - - - 553 .set CYDEV_CACHE_CC_CTL, 0x40004800 - 554 .set CYDEV_CACHE_ECC_CORR, 0x40004880 - 555 .set CYDEV_CACHE_ECC_ERR, 0x40004888 - 556 .set CYDEV_CACHE_FLASH_ERR, 0x40004890 - 557 .set CYDEV_CACHE_HITMISS, 0x40004898 - 558 .set CYDEV_I2C_BASE, 0x40004900 - 559 .set CYDEV_I2C_SIZE, 0x000000e1 - 560 .set CYDEV_I2C_XCFG, 0x400049c8 - 561 .set CYDEV_I2C_ADR, 0x400049ca - 562 .set CYDEV_I2C_CFG, 0x400049d6 - 563 .set CYDEV_I2C_CSR, 0x400049d7 - 564 .set CYDEV_I2C_D, 0x400049d8 - 565 .set CYDEV_I2C_MCSR, 0x400049d9 - 566 .set CYDEV_I2C_CLK_DIV1, 0x400049db - 567 .set CYDEV_I2C_CLK_DIV2, 0x400049dc - 568 .set CYDEV_I2C_TMOUT_CSR, 0x400049dd - 569 .set CYDEV_I2C_TMOUT_SR, 0x400049de - 570 .set CYDEV_I2C_TMOUT_CFG0, 0x400049df - 571 .set CYDEV_I2C_TMOUT_CFG1, 0x400049e0 - 572 .set CYDEV_DEC_BASE, 0x40004e00 - 573 .set CYDEV_DEC_SIZE, 0x00000015 - 574 .set CYDEV_DEC_CR, 0x40004e00 - 575 .set CYDEV_DEC_SR, 0x40004e01 - 576 .set CYDEV_DEC_SHIFT1, 0x40004e02 - 577 .set CYDEV_DEC_SHIFT2, 0x40004e03 - 578 .set CYDEV_DEC_DR2, 0x40004e04 - 579 .set CYDEV_DEC_DR2H, 0x40004e05 - 580 .set CYDEV_DEC_DR1, 0x40004e06 - 581 .set CYDEV_DEC_OCOR, 0x40004e08 - 582 .set CYDEV_DEC_OCORM, 0x40004e09 - 583 .set CYDEV_DEC_OCORH, 0x40004e0a - 584 .set CYDEV_DEC_GCOR, 0x40004e0c - 585 .set CYDEV_DEC_GCORH, 0x40004e0d - 586 .set CYDEV_DEC_GVAL, 0x40004e0e - 587 .set CYDEV_DEC_OUTSAMP, 0x40004e10 - 588 .set CYDEV_DEC_OUTSAMPM, 0x40004e11 - 589 .set CYDEV_DEC_OUTSAMPH, 0x40004e12 - 590 .set CYDEV_DEC_OUTSAMPS, 0x40004e13 - 591 .set CYDEV_DEC_COHER, 0x40004e14 - 592 .set CYDEV_TMR0_BASE, 0x40004f00 - 593 .set CYDEV_TMR0_SIZE, 0x0000000c - 594 .set CYDEV_TMR0_CFG0, 0x40004f00 - 595 .set CYDEV_TMR0_CFG1, 0x40004f01 - 596 .set CYDEV_TMR0_CFG2, 0x40004f02 - 597 .set CYDEV_TMR0_SR0, 0x40004f03 - 598 .set CYDEV_TMR0_PER0, 0x40004f04 - 599 .set CYDEV_TMR0_PER1, 0x40004f05 - 600 .set CYDEV_TMR0_CNT_CMP0, 0x40004f06 - 601 .set CYDEV_TMR0_CNT_CMP1, 0x40004f07 - 602 .set CYDEV_TMR0_CAP0, 0x40004f08 - 603 .set CYDEV_TMR0_CAP1, 0x40004f09 - 604 .set CYDEV_TMR0_RT0, 0x40004f0a - 605 .set CYDEV_TMR0_RT1, 0x40004f0b - 606 .set CYDEV_TMR1_BASE, 0x40004f0c - 607 .set CYDEV_TMR1_SIZE, 0x0000000c - 608 .set CYDEV_TMR1_CFG0, 0x40004f0c - 609 .set CYDEV_TMR1_CFG1, 0x40004f0d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 12 - - - 610 .set CYDEV_TMR1_CFG2, 0x40004f0e - 611 .set CYDEV_TMR1_SR0, 0x40004f0f - 612 .set CYDEV_TMR1_PER0, 0x40004f10 - 613 .set CYDEV_TMR1_PER1, 0x40004f11 - 614 .set CYDEV_TMR1_CNT_CMP0, 0x40004f12 - 615 .set CYDEV_TMR1_CNT_CMP1, 0x40004f13 - 616 .set CYDEV_TMR1_CAP0, 0x40004f14 - 617 .set CYDEV_TMR1_CAP1, 0x40004f15 - 618 .set CYDEV_TMR1_RT0, 0x40004f16 - 619 .set CYDEV_TMR1_RT1, 0x40004f17 - 620 .set CYDEV_TMR2_BASE, 0x40004f18 - 621 .set CYDEV_TMR2_SIZE, 0x0000000c - 622 .set CYDEV_TMR2_CFG0, 0x40004f18 - 623 .set CYDEV_TMR2_CFG1, 0x40004f19 - 624 .set CYDEV_TMR2_CFG2, 0x40004f1a - 625 .set CYDEV_TMR2_SR0, 0x40004f1b - 626 .set CYDEV_TMR2_PER0, 0x40004f1c - 627 .set CYDEV_TMR2_PER1, 0x40004f1d - 628 .set CYDEV_TMR2_CNT_CMP0, 0x40004f1e - 629 .set CYDEV_TMR2_CNT_CMP1, 0x40004f1f - 630 .set CYDEV_TMR2_CAP0, 0x40004f20 - 631 .set CYDEV_TMR2_CAP1, 0x40004f21 - 632 .set CYDEV_TMR2_RT0, 0x40004f22 - 633 .set CYDEV_TMR2_RT1, 0x40004f23 - 634 .set CYDEV_TMR3_BASE, 0x40004f24 - 635 .set CYDEV_TMR3_SIZE, 0x0000000c - 636 .set CYDEV_TMR3_CFG0, 0x40004f24 - 637 .set CYDEV_TMR3_CFG1, 0x40004f25 - 638 .set CYDEV_TMR3_CFG2, 0x40004f26 - 639 .set CYDEV_TMR3_SR0, 0x40004f27 - 640 .set CYDEV_TMR3_PER0, 0x40004f28 - 641 .set CYDEV_TMR3_PER1, 0x40004f29 - 642 .set CYDEV_TMR3_CNT_CMP0, 0x40004f2a - 643 .set CYDEV_TMR3_CNT_CMP1, 0x40004f2b - 644 .set CYDEV_TMR3_CAP0, 0x40004f2c - 645 .set CYDEV_TMR3_CAP1, 0x40004f2d - 646 .set CYDEV_TMR3_RT0, 0x40004f2e - 647 .set CYDEV_TMR3_RT1, 0x40004f2f - 648 .set CYDEV_IO_BASE, 0x40005000 - 649 .set CYDEV_IO_SIZE, 0x00000200 - 650 .set CYDEV_IO_PC_BASE, 0x40005000 - 651 .set CYDEV_IO_PC_SIZE, 0x00000080 - 652 .set CYDEV_IO_PC_PRT0_BASE, 0x40005000 - 653 .set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 - 654 .set CYDEV_IO_PC_PRT0_PC0, 0x40005000 - 655 .set CYDEV_IO_PC_PRT0_PC1, 0x40005001 - 656 .set CYDEV_IO_PC_PRT0_PC2, 0x40005002 - 657 .set CYDEV_IO_PC_PRT0_PC3, 0x40005003 - 658 .set CYDEV_IO_PC_PRT0_PC4, 0x40005004 - 659 .set CYDEV_IO_PC_PRT0_PC5, 0x40005005 - 660 .set CYDEV_IO_PC_PRT0_PC6, 0x40005006 - 661 .set CYDEV_IO_PC_PRT0_PC7, 0x40005007 - 662 .set CYDEV_IO_PC_PRT1_BASE, 0x40005008 - 663 .set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 - 664 .set CYDEV_IO_PC_PRT1_PC0, 0x40005008 - 665 .set CYDEV_IO_PC_PRT1_PC1, 0x40005009 - 666 .set CYDEV_IO_PC_PRT1_PC2, 0x4000500a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 13 - - - 667 .set CYDEV_IO_PC_PRT1_PC3, 0x4000500b - 668 .set CYDEV_IO_PC_PRT1_PC4, 0x4000500c - 669 .set CYDEV_IO_PC_PRT1_PC5, 0x4000500d - 670 .set CYDEV_IO_PC_PRT1_PC6, 0x4000500e - 671 .set CYDEV_IO_PC_PRT1_PC7, 0x4000500f - 672 .set CYDEV_IO_PC_PRT2_BASE, 0x40005010 - 673 .set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 - 674 .set CYDEV_IO_PC_PRT2_PC0, 0x40005010 - 675 .set CYDEV_IO_PC_PRT2_PC1, 0x40005011 - 676 .set CYDEV_IO_PC_PRT2_PC2, 0x40005012 - 677 .set CYDEV_IO_PC_PRT2_PC3, 0x40005013 - 678 .set CYDEV_IO_PC_PRT2_PC4, 0x40005014 - 679 .set CYDEV_IO_PC_PRT2_PC5, 0x40005015 - 680 .set CYDEV_IO_PC_PRT2_PC6, 0x40005016 - 681 .set CYDEV_IO_PC_PRT2_PC7, 0x40005017 - 682 .set CYDEV_IO_PC_PRT3_BASE, 0x40005018 - 683 .set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 - 684 .set CYDEV_IO_PC_PRT3_PC0, 0x40005018 - 685 .set CYDEV_IO_PC_PRT3_PC1, 0x40005019 - 686 .set CYDEV_IO_PC_PRT3_PC2, 0x4000501a - 687 .set CYDEV_IO_PC_PRT3_PC3, 0x4000501b - 688 .set CYDEV_IO_PC_PRT3_PC4, 0x4000501c - 689 .set CYDEV_IO_PC_PRT3_PC5, 0x4000501d - 690 .set CYDEV_IO_PC_PRT3_PC6, 0x4000501e - 691 .set CYDEV_IO_PC_PRT3_PC7, 0x4000501f - 692 .set CYDEV_IO_PC_PRT4_BASE, 0x40005020 - 693 .set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 - 694 .set CYDEV_IO_PC_PRT4_PC0, 0x40005020 - 695 .set CYDEV_IO_PC_PRT4_PC1, 0x40005021 - 696 .set CYDEV_IO_PC_PRT4_PC2, 0x40005022 - 697 .set CYDEV_IO_PC_PRT4_PC3, 0x40005023 - 698 .set CYDEV_IO_PC_PRT4_PC4, 0x40005024 - 699 .set CYDEV_IO_PC_PRT4_PC5, 0x40005025 - 700 .set CYDEV_IO_PC_PRT4_PC6, 0x40005026 - 701 .set CYDEV_IO_PC_PRT4_PC7, 0x40005027 - 702 .set CYDEV_IO_PC_PRT5_BASE, 0x40005028 - 703 .set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 - 704 .set CYDEV_IO_PC_PRT5_PC0, 0x40005028 - 705 .set CYDEV_IO_PC_PRT5_PC1, 0x40005029 - 706 .set CYDEV_IO_PC_PRT5_PC2, 0x4000502a - 707 .set CYDEV_IO_PC_PRT5_PC3, 0x4000502b - 708 .set CYDEV_IO_PC_PRT5_PC4, 0x4000502c - 709 .set CYDEV_IO_PC_PRT5_PC5, 0x4000502d - 710 .set CYDEV_IO_PC_PRT5_PC6, 0x4000502e - 711 .set CYDEV_IO_PC_PRT5_PC7, 0x4000502f - 712 .set CYDEV_IO_PC_PRT6_BASE, 0x40005030 - 713 .set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 - 714 .set CYDEV_IO_PC_PRT6_PC0, 0x40005030 - 715 .set CYDEV_IO_PC_PRT6_PC1, 0x40005031 - 716 .set CYDEV_IO_PC_PRT6_PC2, 0x40005032 - 717 .set CYDEV_IO_PC_PRT6_PC3, 0x40005033 - 718 .set CYDEV_IO_PC_PRT6_PC4, 0x40005034 - 719 .set CYDEV_IO_PC_PRT6_PC5, 0x40005035 - 720 .set CYDEV_IO_PC_PRT6_PC6, 0x40005036 - 721 .set CYDEV_IO_PC_PRT6_PC7, 0x40005037 - 722 .set CYDEV_IO_PC_PRT12_BASE, 0x40005060 - 723 .set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 14 - - - 724 .set CYDEV_IO_PC_PRT12_PC0, 0x40005060 - 725 .set CYDEV_IO_PC_PRT12_PC1, 0x40005061 - 726 .set CYDEV_IO_PC_PRT12_PC2, 0x40005062 - 727 .set CYDEV_IO_PC_PRT12_PC3, 0x40005063 - 728 .set CYDEV_IO_PC_PRT12_PC4, 0x40005064 - 729 .set CYDEV_IO_PC_PRT12_PC5, 0x40005065 - 730 .set CYDEV_IO_PC_PRT12_PC6, 0x40005066 - 731 .set CYDEV_IO_PC_PRT12_PC7, 0x40005067 - 732 .set CYDEV_IO_PC_PRT15_BASE, 0x40005078 - 733 .set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 - 734 .set CYDEV_IO_PC_PRT15_PC0, 0x40005078 - 735 .set CYDEV_IO_PC_PRT15_PC1, 0x40005079 - 736 .set CYDEV_IO_PC_PRT15_PC2, 0x4000507a - 737 .set CYDEV_IO_PC_PRT15_PC3, 0x4000507b - 738 .set CYDEV_IO_PC_PRT15_PC4, 0x4000507c - 739 .set CYDEV_IO_PC_PRT15_PC5, 0x4000507d - 740 .set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e - 741 .set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 - 742 .set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e - 743 .set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f - 744 .set CYDEV_IO_DR_BASE, 0x40005080 - 745 .set CYDEV_IO_DR_SIZE, 0x00000010 - 746 .set CYDEV_IO_DR_PRT0_BASE, 0x40005080 - 747 .set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 - 748 .set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080 - 749 .set CYDEV_IO_DR_PRT1_BASE, 0x40005081 - 750 .set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 - 751 .set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081 - 752 .set CYDEV_IO_DR_PRT2_BASE, 0x40005082 - 753 .set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 - 754 .set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082 - 755 .set CYDEV_IO_DR_PRT3_BASE, 0x40005083 - 756 .set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 - 757 .set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083 - 758 .set CYDEV_IO_DR_PRT4_BASE, 0x40005084 - 759 .set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 - 760 .set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084 - 761 .set CYDEV_IO_DR_PRT5_BASE, 0x40005085 - 762 .set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 - 763 .set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085 - 764 .set CYDEV_IO_DR_PRT6_BASE, 0x40005086 - 765 .set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 - 766 .set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086 - 767 .set CYDEV_IO_DR_PRT12_BASE, 0x4000508c - 768 .set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 - 769 .set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c - 770 .set CYDEV_IO_DR_PRT15_BASE, 0x4000508f - 771 .set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 - 772 .set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f - 773 .set CYDEV_IO_PS_BASE, 0x40005090 - 774 .set CYDEV_IO_PS_SIZE, 0x00000010 - 775 .set CYDEV_IO_PS_PRT0_BASE, 0x40005090 - 776 .set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 - 777 .set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090 - 778 .set CYDEV_IO_PS_PRT1_BASE, 0x40005091 - 779 .set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 - 780 .set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 15 - - - 781 .set CYDEV_IO_PS_PRT2_BASE, 0x40005092 - 782 .set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 - 783 .set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092 - 784 .set CYDEV_IO_PS_PRT3_BASE, 0x40005093 - 785 .set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 - 786 .set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093 - 787 .set CYDEV_IO_PS_PRT4_BASE, 0x40005094 - 788 .set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 - 789 .set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094 - 790 .set CYDEV_IO_PS_PRT5_BASE, 0x40005095 - 791 .set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 - 792 .set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095 - 793 .set CYDEV_IO_PS_PRT6_BASE, 0x40005096 - 794 .set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 - 795 .set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096 - 796 .set CYDEV_IO_PS_PRT12_BASE, 0x4000509c - 797 .set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 - 798 .set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c - 799 .set CYDEV_IO_PS_PRT15_BASE, 0x4000509f - 800 .set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 - 801 .set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f - 802 .set CYDEV_IO_PRT_BASE, 0x40005100 - 803 .set CYDEV_IO_PRT_SIZE, 0x00000100 - 804 .set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 - 805 .set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 - 806 .set CYDEV_IO_PRT_PRT0_DR, 0x40005100 - 807 .set CYDEV_IO_PRT_PRT0_PS, 0x40005101 - 808 .set CYDEV_IO_PRT_PRT0_DM0, 0x40005102 - 809 .set CYDEV_IO_PRT_PRT0_DM1, 0x40005103 - 810 .set CYDEV_IO_PRT_PRT0_DM2, 0x40005104 - 811 .set CYDEV_IO_PRT_PRT0_SLW, 0x40005105 - 812 .set CYDEV_IO_PRT_PRT0_BYP, 0x40005106 - 813 .set CYDEV_IO_PRT_PRT0_BIE, 0x40005107 - 814 .set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108 - 815 .set CYDEV_IO_PRT_PRT0_CTL, 0x40005109 - 816 .set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a - 817 .set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b - 818 .set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c - 819 .set CYDEV_IO_PRT_PRT0_AG, 0x4000510d - 820 .set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e - 821 .set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f - 822 .set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 - 823 .set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 - 824 .set CYDEV_IO_PRT_PRT1_DR, 0x40005110 - 825 .set CYDEV_IO_PRT_PRT1_PS, 0x40005111 - 826 .set CYDEV_IO_PRT_PRT1_DM0, 0x40005112 - 827 .set CYDEV_IO_PRT_PRT1_DM1, 0x40005113 - 828 .set CYDEV_IO_PRT_PRT1_DM2, 0x40005114 - 829 .set CYDEV_IO_PRT_PRT1_SLW, 0x40005115 - 830 .set CYDEV_IO_PRT_PRT1_BYP, 0x40005116 - 831 .set CYDEV_IO_PRT_PRT1_BIE, 0x40005117 - 832 .set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118 - 833 .set CYDEV_IO_PRT_PRT1_CTL, 0x40005119 - 834 .set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a - 835 .set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b - 836 .set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c - 837 .set CYDEV_IO_PRT_PRT1_AG, 0x4000511d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 16 - - - 838 .set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e - 839 .set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f - 840 .set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 - 841 .set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 - 842 .set CYDEV_IO_PRT_PRT2_DR, 0x40005120 - 843 .set CYDEV_IO_PRT_PRT2_PS, 0x40005121 - 844 .set CYDEV_IO_PRT_PRT2_DM0, 0x40005122 - 845 .set CYDEV_IO_PRT_PRT2_DM1, 0x40005123 - 846 .set CYDEV_IO_PRT_PRT2_DM2, 0x40005124 - 847 .set CYDEV_IO_PRT_PRT2_SLW, 0x40005125 - 848 .set CYDEV_IO_PRT_PRT2_BYP, 0x40005126 - 849 .set CYDEV_IO_PRT_PRT2_BIE, 0x40005127 - 850 .set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128 - 851 .set CYDEV_IO_PRT_PRT2_CTL, 0x40005129 - 852 .set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a - 853 .set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b - 854 .set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c - 855 .set CYDEV_IO_PRT_PRT2_AG, 0x4000512d - 856 .set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e - 857 .set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f - 858 .set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 - 859 .set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 - 860 .set CYDEV_IO_PRT_PRT3_DR, 0x40005130 - 861 .set CYDEV_IO_PRT_PRT3_PS, 0x40005131 - 862 .set CYDEV_IO_PRT_PRT3_DM0, 0x40005132 - 863 .set CYDEV_IO_PRT_PRT3_DM1, 0x40005133 - 864 .set CYDEV_IO_PRT_PRT3_DM2, 0x40005134 - 865 .set CYDEV_IO_PRT_PRT3_SLW, 0x40005135 - 866 .set CYDEV_IO_PRT_PRT3_BYP, 0x40005136 - 867 .set CYDEV_IO_PRT_PRT3_BIE, 0x40005137 - 868 .set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138 - 869 .set CYDEV_IO_PRT_PRT3_CTL, 0x40005139 - 870 .set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a - 871 .set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b - 872 .set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c - 873 .set CYDEV_IO_PRT_PRT3_AG, 0x4000513d - 874 .set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e - 875 .set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f - 876 .set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 - 877 .set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 - 878 .set CYDEV_IO_PRT_PRT4_DR, 0x40005140 - 879 .set CYDEV_IO_PRT_PRT4_PS, 0x40005141 - 880 .set CYDEV_IO_PRT_PRT4_DM0, 0x40005142 - 881 .set CYDEV_IO_PRT_PRT4_DM1, 0x40005143 - 882 .set CYDEV_IO_PRT_PRT4_DM2, 0x40005144 - 883 .set CYDEV_IO_PRT_PRT4_SLW, 0x40005145 - 884 .set CYDEV_IO_PRT_PRT4_BYP, 0x40005146 - 885 .set CYDEV_IO_PRT_PRT4_BIE, 0x40005147 - 886 .set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148 - 887 .set CYDEV_IO_PRT_PRT4_CTL, 0x40005149 - 888 .set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a - 889 .set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b - 890 .set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c - 891 .set CYDEV_IO_PRT_PRT4_AG, 0x4000514d - 892 .set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e - 893 .set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f - 894 .set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 17 - - - 895 .set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 - 896 .set CYDEV_IO_PRT_PRT5_DR, 0x40005150 - 897 .set CYDEV_IO_PRT_PRT5_PS, 0x40005151 - 898 .set CYDEV_IO_PRT_PRT5_DM0, 0x40005152 - 899 .set CYDEV_IO_PRT_PRT5_DM1, 0x40005153 - 900 .set CYDEV_IO_PRT_PRT5_DM2, 0x40005154 - 901 .set CYDEV_IO_PRT_PRT5_SLW, 0x40005155 - 902 .set CYDEV_IO_PRT_PRT5_BYP, 0x40005156 - 903 .set CYDEV_IO_PRT_PRT5_BIE, 0x40005157 - 904 .set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158 - 905 .set CYDEV_IO_PRT_PRT5_CTL, 0x40005159 - 906 .set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a - 907 .set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b - 908 .set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c - 909 .set CYDEV_IO_PRT_PRT5_AG, 0x4000515d - 910 .set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e - 911 .set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f - 912 .set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 - 913 .set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 - 914 .set CYDEV_IO_PRT_PRT6_DR, 0x40005160 - 915 .set CYDEV_IO_PRT_PRT6_PS, 0x40005161 - 916 .set CYDEV_IO_PRT_PRT6_DM0, 0x40005162 - 917 .set CYDEV_IO_PRT_PRT6_DM1, 0x40005163 - 918 .set CYDEV_IO_PRT_PRT6_DM2, 0x40005164 - 919 .set CYDEV_IO_PRT_PRT6_SLW, 0x40005165 - 920 .set CYDEV_IO_PRT_PRT6_BYP, 0x40005166 - 921 .set CYDEV_IO_PRT_PRT6_BIE, 0x40005167 - 922 .set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168 - 923 .set CYDEV_IO_PRT_PRT6_CTL, 0x40005169 - 924 .set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a - 925 .set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b - 926 .set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c - 927 .set CYDEV_IO_PRT_PRT6_AG, 0x4000516d - 928 .set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e - 929 .set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f - 930 .set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 - 931 .set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 - 932 .set CYDEV_IO_PRT_PRT12_DR, 0x400051c0 - 933 .set CYDEV_IO_PRT_PRT12_PS, 0x400051c1 - 934 .set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2 - 935 .set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3 - 936 .set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4 - 937 .set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5 - 938 .set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6 - 939 .set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7 - 940 .set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8 - 941 .set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9 - 942 .set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca - 943 .set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb - 944 .set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc - 945 .set CYDEV_IO_PRT_PRT12_AG, 0x400051cd - 946 .set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce - 947 .set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf - 948 .set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 - 949 .set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 - 950 .set CYDEV_IO_PRT_PRT15_DR, 0x400051f0 - 951 .set CYDEV_IO_PRT_PRT15_PS, 0x400051f1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 18 - - - 952 .set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2 - 953 .set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3 - 954 .set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4 - 955 .set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5 - 956 .set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6 - 957 .set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7 - 958 .set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8 - 959 .set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9 - 960 .set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa - 961 .set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb - 962 .set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc - 963 .set CYDEV_IO_PRT_PRT15_AG, 0x400051fd - 964 .set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe - 965 .set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff - 966 .set CYDEV_PRTDSI_BASE, 0x40005200 - 967 .set CYDEV_PRTDSI_SIZE, 0x0000007f - 968 .set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 - 969 .set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 - 970 .set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200 - 971 .set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201 - 972 .set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202 - 973 .set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203 - 974 .set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204 - 975 .set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205 - 976 .set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206 - 977 .set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 - 978 .set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 - 979 .set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208 - 980 .set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209 - 981 .set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a - 982 .set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b - 983 .set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c - 984 .set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d - 985 .set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e - 986 .set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 - 987 .set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 - 988 .set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210 - 989 .set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211 - 990 .set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212 - 991 .set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213 - 992 .set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214 - 993 .set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215 - 994 .set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216 - 995 .set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 - 996 .set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 - 997 .set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218 - 998 .set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219 - 999 .set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a - 1000 .set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b - 1001 .set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c - 1002 .set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d - 1003 .set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e - 1004 .set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 - 1005 .set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 - 1006 .set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220 - 1007 .set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221 - 1008 .set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 19 - - - 1009 .set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223 - 1010 .set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224 - 1011 .set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225 - 1012 .set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226 - 1013 .set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 - 1014 .set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 - 1015 .set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228 - 1016 .set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229 - 1017 .set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a - 1018 .set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b - 1019 .set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c - 1020 .set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d - 1021 .set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e - 1022 .set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 - 1023 .set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 - 1024 .set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230 - 1025 .set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231 - 1026 .set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232 - 1027 .set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233 - 1028 .set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234 - 1029 .set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235 - 1030 .set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236 - 1031 .set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 - 1032 .set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 - 1033 .set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260 - 1034 .set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261 - 1035 .set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262 - 1036 .set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263 - 1037 .set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264 - 1038 .set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265 - 1039 .set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 - 1040 .set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 - 1041 .set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278 - 1042 .set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279 - 1043 .set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a - 1044 .set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b - 1045 .set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c - 1046 .set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d - 1047 .set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e - 1048 .set CYDEV_EMIF_BASE, 0x40005400 - 1049 .set CYDEV_EMIF_SIZE, 0x00000007 - 1050 .set CYDEV_EMIF_NO_UDB, 0x40005400 - 1051 .set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401 - 1052 .set CYDEV_EMIF_MEM_DWN, 0x40005402 - 1053 .set CYDEV_EMIF_MEMCLK_DIV, 0x40005403 - 1054 .set CYDEV_EMIF_CLOCK_EN, 0x40005404 - 1055 .set CYDEV_EMIF_EM_TYPE, 0x40005405 - 1056 .set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406 - 1057 .set CYDEV_ANAIF_BASE, 0x40005800 - 1058 .set CYDEV_ANAIF_SIZE, 0x000003a9 - 1059 .set CYDEV_ANAIF_CFG_BASE, 0x40005800 - 1060 .set CYDEV_ANAIF_CFG_SIZE, 0x0000010f - 1061 .set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 - 1062 .set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 - 1063 .set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800 - 1064 .set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801 - 1065 .set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 20 - - - 1066 .set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 - 1067 .set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 - 1068 .set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804 - 1069 .set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805 - 1070 .set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806 - 1071 .set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 - 1072 .set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 - 1073 .set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808 - 1074 .set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809 - 1075 .set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a - 1076 .set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c - 1077 .set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 - 1078 .set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c - 1079 .set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d - 1080 .set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e - 1081 .set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 - 1082 .set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 - 1083 .set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820 - 1084 .set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821 - 1085 .set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822 - 1086 .set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 - 1087 .set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 - 1088 .set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824 - 1089 .set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825 - 1090 .set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826 - 1091 .set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 - 1092 .set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 - 1093 .set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828 - 1094 .set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829 - 1095 .set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a - 1096 .set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c - 1097 .set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 - 1098 .set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c - 1099 .set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d - 1100 .set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e - 1101 .set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 - 1102 .set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 - 1103 .set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840 - 1104 .set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 - 1105 .set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 - 1106 .set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841 - 1107 .set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 - 1108 .set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 - 1109 .set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842 - 1110 .set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 - 1111 .set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 - 1112 .set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843 - 1113 .set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 - 1114 .set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 - 1115 .set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848 - 1116 .set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849 - 1117 .set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a - 1118 .set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 - 1119 .set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a - 1120 .set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b - 1121 .set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c - 1122 .set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 21 - - - 1123 .set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c - 1124 .set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d - 1125 .set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e - 1126 .set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 - 1127 .set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e - 1128 .set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f - 1129 .set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 - 1130 .set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 - 1131 .set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858 - 1132 .set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859 - 1133 .set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a - 1134 .set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 - 1135 .set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a - 1136 .set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b - 1137 .set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c - 1138 .set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 - 1139 .set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c - 1140 .set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d - 1141 .set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e - 1142 .set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 - 1143 .set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e - 1144 .set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f - 1145 .set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 - 1146 .set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 - 1147 .set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868 - 1148 .set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869 - 1149 .set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a - 1150 .set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 - 1151 .set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a - 1152 .set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b - 1153 .set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 - 1154 .set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b - 1155 .set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c - 1156 .set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 - 1157 .set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c - 1158 .set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d - 1159 .set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e - 1160 .set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f - 1161 .set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 - 1162 .set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 - 1163 .set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870 - 1164 .set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871 - 1165 .set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 - 1166 .set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 - 1167 .set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872 - 1168 .set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873 - 1169 .set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 - 1170 .set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 - 1171 .set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876 - 1172 .set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877 - 1173 .set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 - 1174 .set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 - 1175 .set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878 - 1176 .set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879 - 1177 .set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a - 1178 .set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 - 1179 .set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 22 - - - 1180 .set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b - 1181 .set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c - 1182 .set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 - 1183 .set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c - 1184 .set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 - 1185 .set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 - 1186 .set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880 - 1187 .set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881 - 1188 .set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882 - 1189 .set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883 - 1190 .set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884 - 1191 .set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885 - 1192 .set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886 - 1193 .set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887 - 1194 .set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888 - 1195 .set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889 - 1196 .set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a - 1197 .set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b - 1198 .set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c - 1199 .set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d - 1200 .set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e - 1201 .set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f - 1202 .set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890 - 1203 .set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891 - 1204 .set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892 - 1205 .set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893 - 1206 .set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894 - 1207 .set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895 - 1208 .set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896 - 1209 .set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897 - 1210 .set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898 - 1211 .set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899 - 1212 .set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a - 1213 .set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b - 1214 .set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c - 1215 .set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d - 1216 .set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e - 1217 .set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f - 1218 .set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 - 1219 .set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 - 1220 .set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900 - 1221 .set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901 - 1222 .set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902 - 1223 .set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903 - 1224 .set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904 - 1225 .set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905 - 1226 .set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906 - 1227 .set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 - 1228 .set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 - 1229 .set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908 - 1230 .set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909 - 1231 .set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a - 1232 .set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b - 1233 .set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c - 1234 .set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d - 1235 .set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e - 1236 .set CYDEV_ANAIF_RT_BASE, 0x40005a00 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 23 - - - 1237 .set CYDEV_ANAIF_RT_SIZE, 0x00000162 - 1238 .set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 - 1239 .set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d - 1240 .set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00 - 1241 .set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02 - 1242 .set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03 - 1243 .set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04 - 1244 .set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06 - 1245 .set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07 - 1246 .set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08 - 1247 .set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a - 1248 .set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b - 1249 .set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c - 1250 .set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 - 1251 .set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d - 1252 .set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10 - 1253 .set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12 - 1254 .set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13 - 1255 .set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14 - 1256 .set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16 - 1257 .set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17 - 1258 .set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18 - 1259 .set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a - 1260 .set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b - 1261 .set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c - 1262 .set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 - 1263 .set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d - 1264 .set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20 - 1265 .set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22 - 1266 .set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23 - 1267 .set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24 - 1268 .set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26 - 1269 .set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27 - 1270 .set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28 - 1271 .set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a - 1272 .set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b - 1273 .set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c - 1274 .set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 - 1275 .set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d - 1276 .set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30 - 1277 .set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32 - 1278 .set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33 - 1279 .set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34 - 1280 .set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36 - 1281 .set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37 - 1282 .set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38 - 1283 .set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a - 1284 .set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b - 1285 .set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c - 1286 .set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 - 1287 .set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 - 1288 .set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80 - 1289 .set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82 - 1290 .set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83 - 1291 .set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84 - 1292 .set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87 - 1293 .set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 24 - - - 1294 .set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 - 1295 .set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88 - 1296 .set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a - 1297 .set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b - 1298 .set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c - 1299 .set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f - 1300 .set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 - 1301 .set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 - 1302 .set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90 - 1303 .set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92 - 1304 .set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93 - 1305 .set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94 - 1306 .set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97 - 1307 .set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 - 1308 .set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 - 1309 .set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98 - 1310 .set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a - 1311 .set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b - 1312 .set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c - 1313 .set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f - 1314 .set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 - 1315 .set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 - 1316 .set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0 - 1317 .set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2 - 1318 .set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3 - 1319 .set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4 - 1320 .set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6 - 1321 .set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7 - 1322 .set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 - 1323 .set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 - 1324 .set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8 - 1325 .set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca - 1326 .set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb - 1327 .set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc - 1328 .set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace - 1329 .set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf - 1330 .set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 - 1331 .set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 - 1332 .set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0 - 1333 .set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2 - 1334 .set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3 - 1335 .set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4 - 1336 .set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6 - 1337 .set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7 - 1338 .set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 - 1339 .set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 - 1340 .set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8 - 1341 .set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada - 1342 .set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb - 1343 .set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc - 1344 .set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade - 1345 .set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf - 1346 .set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 - 1347 .set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 - 1348 .set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00 - 1349 .set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02 - 1350 .set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 25 - - - 1351 .set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04 - 1352 .set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06 - 1353 .set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07 - 1354 .set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 - 1355 .set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 - 1356 .set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20 - 1357 .set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22 - 1358 .set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23 - 1359 .set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24 - 1360 .set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26 - 1361 .set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27 - 1362 .set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 - 1363 .set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 - 1364 .set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28 - 1365 .set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a - 1366 .set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b - 1367 .set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c - 1368 .set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e - 1369 .set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f - 1370 .set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 - 1371 .set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 - 1372 .set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40 - 1373 .set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41 - 1374 .set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 - 1375 .set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 - 1376 .set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42 - 1377 .set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43 - 1378 .set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 - 1379 .set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 - 1380 .set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44 - 1381 .set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45 - 1382 .set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 - 1383 .set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 - 1384 .set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46 - 1385 .set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47 - 1386 .set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 - 1387 .set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 - 1388 .set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50 - 1389 .set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51 - 1390 .set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52 - 1391 .set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53 - 1392 .set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54 - 1393 .set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 - 1394 .set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 - 1395 .set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56 - 1396 .set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 - 1397 .set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 - 1398 .set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58 - 1399 .set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a - 1400 .set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b - 1401 .set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c - 1402 .set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 - 1403 .set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c - 1404 .set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d - 1405 .set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e - 1406 .set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f - 1407 .set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 26 - - - 1408 .set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61 - 1409 .set CYDEV_ANAIF_WRK_BASE, 0x40005b80 - 1410 .set CYDEV_ANAIF_WRK_SIZE, 0x00000029 - 1411 .set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 - 1412 .set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 - 1413 .set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80 - 1414 .set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 - 1415 .set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 - 1416 .set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81 - 1417 .set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 - 1418 .set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 - 1419 .set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82 - 1420 .set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 - 1421 .set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 - 1422 .set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83 - 1423 .set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 - 1424 .set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 - 1425 .set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88 - 1426 .set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89 - 1427 .set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 - 1428 .set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 - 1429 .set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90 - 1430 .set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91 - 1431 .set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92 - 1432 .set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93 - 1433 .set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94 - 1434 .set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 - 1435 .set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 - 1436 .set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96 - 1437 .set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97 - 1438 .set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 - 1439 .set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 - 1440 .set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98 - 1441 .set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99 - 1442 .set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a - 1443 .set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b - 1444 .set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c - 1445 .set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 - 1446 .set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 - 1447 .set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0 - 1448 .set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1 - 1449 .set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 - 1450 .set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 - 1451 .set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2 - 1452 .set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3 - 1453 .set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 - 1454 .set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 - 1455 .set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8 - 1456 .set CYDEV_USB_BASE, 0x40006000 - 1457 .set CYDEV_USB_SIZE, 0x00000300 - 1458 .set CYDEV_USB_EP0_DR0, 0x40006000 - 1459 .set CYDEV_USB_EP0_DR1, 0x40006001 - 1460 .set CYDEV_USB_EP0_DR2, 0x40006002 - 1461 .set CYDEV_USB_EP0_DR3, 0x40006003 - 1462 .set CYDEV_USB_EP0_DR4, 0x40006004 - 1463 .set CYDEV_USB_EP0_DR5, 0x40006005 - 1464 .set CYDEV_USB_EP0_DR6, 0x40006006 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 27 - - - 1465 .set CYDEV_USB_EP0_DR7, 0x40006007 - 1466 .set CYDEV_USB_CR0, 0x40006008 - 1467 .set CYDEV_USB_CR1, 0x40006009 - 1468 .set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a - 1469 .set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b - 1470 .set CYDEV_USB_SIE_EP1_BASE, 0x4000600c - 1471 .set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 - 1472 .set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c - 1473 .set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d - 1474 .set CYDEV_USB_SIE_EP1_CR0, 0x4000600e - 1475 .set CYDEV_USB_USBIO_CR0, 0x40006010 - 1476 .set CYDEV_USB_USBIO_CR1, 0x40006012 - 1477 .set CYDEV_USB_DYN_RECONFIG, 0x40006014 - 1478 .set CYDEV_USB_SOF0, 0x40006018 - 1479 .set CYDEV_USB_SOF1, 0x40006019 - 1480 .set CYDEV_USB_SIE_EP2_BASE, 0x4000601c - 1481 .set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 - 1482 .set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c - 1483 .set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d - 1484 .set CYDEV_USB_SIE_EP2_CR0, 0x4000601e - 1485 .set CYDEV_USB_EP0_CR, 0x40006028 - 1486 .set CYDEV_USB_EP0_CNT, 0x40006029 - 1487 .set CYDEV_USB_SIE_EP3_BASE, 0x4000602c - 1488 .set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 - 1489 .set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c - 1490 .set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d - 1491 .set CYDEV_USB_SIE_EP3_CR0, 0x4000602e - 1492 .set CYDEV_USB_SIE_EP4_BASE, 0x4000603c - 1493 .set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 - 1494 .set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c - 1495 .set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d - 1496 .set CYDEV_USB_SIE_EP4_CR0, 0x4000603e - 1497 .set CYDEV_USB_SIE_EP5_BASE, 0x4000604c - 1498 .set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 - 1499 .set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c - 1500 .set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d - 1501 .set CYDEV_USB_SIE_EP5_CR0, 0x4000604e - 1502 .set CYDEV_USB_SIE_EP6_BASE, 0x4000605c - 1503 .set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 - 1504 .set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c - 1505 .set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d - 1506 .set CYDEV_USB_SIE_EP6_CR0, 0x4000605e - 1507 .set CYDEV_USB_SIE_EP7_BASE, 0x4000606c - 1508 .set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 - 1509 .set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c - 1510 .set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d - 1511 .set CYDEV_USB_SIE_EP7_CR0, 0x4000606e - 1512 .set CYDEV_USB_SIE_EP8_BASE, 0x4000607c - 1513 .set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 - 1514 .set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c - 1515 .set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d - 1516 .set CYDEV_USB_SIE_EP8_CR0, 0x4000607e - 1517 .set CYDEV_USB_ARB_EP1_BASE, 0x40006080 - 1518 .set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 - 1519 .set CYDEV_USB_ARB_EP1_CFG, 0x40006080 - 1520 .set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081 - 1521 .set CYDEV_USB_ARB_EP1_SR, 0x40006082 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 28 - - - 1522 .set CYDEV_USB_ARB_RW1_BASE, 0x40006084 - 1523 .set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 - 1524 .set CYDEV_USB_ARB_RW1_WA, 0x40006084 - 1525 .set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085 - 1526 .set CYDEV_USB_ARB_RW1_RA, 0x40006086 - 1527 .set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087 - 1528 .set CYDEV_USB_ARB_RW1_DR, 0x40006088 - 1529 .set CYDEV_USB_BUF_SIZE, 0x4000608c - 1530 .set CYDEV_USB_EP_ACTIVE, 0x4000608e - 1531 .set CYDEV_USB_EP_TYPE, 0x4000608f - 1532 .set CYDEV_USB_ARB_EP2_BASE, 0x40006090 - 1533 .set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 - 1534 .set CYDEV_USB_ARB_EP2_CFG, 0x40006090 - 1535 .set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091 - 1536 .set CYDEV_USB_ARB_EP2_SR, 0x40006092 - 1537 .set CYDEV_USB_ARB_RW2_BASE, 0x40006094 - 1538 .set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 - 1539 .set CYDEV_USB_ARB_RW2_WA, 0x40006094 - 1540 .set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095 - 1541 .set CYDEV_USB_ARB_RW2_RA, 0x40006096 - 1542 .set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097 - 1543 .set CYDEV_USB_ARB_RW2_DR, 0x40006098 - 1544 .set CYDEV_USB_ARB_CFG, 0x4000609c - 1545 .set CYDEV_USB_USB_CLK_EN, 0x4000609d - 1546 .set CYDEV_USB_ARB_INT_EN, 0x4000609e - 1547 .set CYDEV_USB_ARB_INT_SR, 0x4000609f - 1548 .set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 - 1549 .set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 - 1550 .set CYDEV_USB_ARB_EP3_CFG, 0x400060a0 - 1551 .set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1 - 1552 .set CYDEV_USB_ARB_EP3_SR, 0x400060a2 - 1553 .set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 - 1554 .set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 - 1555 .set CYDEV_USB_ARB_RW3_WA, 0x400060a4 - 1556 .set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5 - 1557 .set CYDEV_USB_ARB_RW3_RA, 0x400060a6 - 1558 .set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7 - 1559 .set CYDEV_USB_ARB_RW3_DR, 0x400060a8 - 1560 .set CYDEV_USB_CWA, 0x400060ac - 1561 .set CYDEV_USB_CWA_MSB, 0x400060ad - 1562 .set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 - 1563 .set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 - 1564 .set CYDEV_USB_ARB_EP4_CFG, 0x400060b0 - 1565 .set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1 - 1566 .set CYDEV_USB_ARB_EP4_SR, 0x400060b2 - 1567 .set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 - 1568 .set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 - 1569 .set CYDEV_USB_ARB_RW4_WA, 0x400060b4 - 1570 .set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5 - 1571 .set CYDEV_USB_ARB_RW4_RA, 0x400060b6 - 1572 .set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7 - 1573 .set CYDEV_USB_ARB_RW4_DR, 0x400060b8 - 1574 .set CYDEV_USB_DMA_THRES, 0x400060bc - 1575 .set CYDEV_USB_DMA_THRES_MSB, 0x400060bd - 1576 .set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 - 1577 .set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 - 1578 .set CYDEV_USB_ARB_EP5_CFG, 0x400060c0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 29 - - - 1579 .set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1 - 1580 .set CYDEV_USB_ARB_EP5_SR, 0x400060c2 - 1581 .set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 - 1582 .set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 - 1583 .set CYDEV_USB_ARB_RW5_WA, 0x400060c4 - 1584 .set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5 - 1585 .set CYDEV_USB_ARB_RW5_RA, 0x400060c6 - 1586 .set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7 - 1587 .set CYDEV_USB_ARB_RW5_DR, 0x400060c8 - 1588 .set CYDEV_USB_BUS_RST_CNT, 0x400060cc - 1589 .set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 - 1590 .set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 - 1591 .set CYDEV_USB_ARB_EP6_CFG, 0x400060d0 - 1592 .set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1 - 1593 .set CYDEV_USB_ARB_EP6_SR, 0x400060d2 - 1594 .set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 - 1595 .set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 - 1596 .set CYDEV_USB_ARB_RW6_WA, 0x400060d4 - 1597 .set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5 - 1598 .set CYDEV_USB_ARB_RW6_RA, 0x400060d6 - 1599 .set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7 - 1600 .set CYDEV_USB_ARB_RW6_DR, 0x400060d8 - 1601 .set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 - 1602 .set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 - 1603 .set CYDEV_USB_ARB_EP7_CFG, 0x400060e0 - 1604 .set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1 - 1605 .set CYDEV_USB_ARB_EP7_SR, 0x400060e2 - 1606 .set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 - 1607 .set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 - 1608 .set CYDEV_USB_ARB_RW7_WA, 0x400060e4 - 1609 .set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5 - 1610 .set CYDEV_USB_ARB_RW7_RA, 0x400060e6 - 1611 .set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7 - 1612 .set CYDEV_USB_ARB_RW7_DR, 0x400060e8 - 1613 .set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 - 1614 .set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 - 1615 .set CYDEV_USB_ARB_EP8_CFG, 0x400060f0 - 1616 .set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1 - 1617 .set CYDEV_USB_ARB_EP8_SR, 0x400060f2 - 1618 .set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 - 1619 .set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 - 1620 .set CYDEV_USB_ARB_RW8_WA, 0x400060f4 - 1621 .set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5 - 1622 .set CYDEV_USB_ARB_RW8_RA, 0x400060f6 - 1623 .set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7 - 1624 .set CYDEV_USB_ARB_RW8_DR, 0x400060f8 - 1625 .set CYDEV_USB_MEM_BASE, 0x40006100 - 1626 .set CYDEV_USB_MEM_SIZE, 0x00000200 - 1627 .set CYDEV_USB_MEM_DATA_MBASE, 0x40006100 - 1628 .set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200 - 1629 .set CYDEV_UWRK_BASE, 0x40006400 - 1630 .set CYDEV_UWRK_SIZE, 0x00000b60 - 1631 .set CYDEV_UWRK_UWRK8_BASE, 0x40006400 - 1632 .set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 - 1633 .set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 - 1634 .set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 - 1635 .set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 30 - - - 1636 .set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401 - 1637 .set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402 - 1638 .set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403 - 1639 .set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404 - 1640 .set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405 - 1641 .set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406 - 1642 .set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407 - 1643 .set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408 - 1644 .set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409 - 1645 .set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a - 1646 .set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b - 1647 .set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c - 1648 .set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d - 1649 .set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e - 1650 .set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f - 1651 .set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410 - 1652 .set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411 - 1653 .set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412 - 1654 .set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413 - 1655 .set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414 - 1656 .set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415 - 1657 .set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416 - 1658 .set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417 - 1659 .set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418 - 1660 .set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419 - 1661 .set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a - 1662 .set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b - 1663 .set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c - 1664 .set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d - 1665 .set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e - 1666 .set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f - 1667 .set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420 - 1668 .set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421 - 1669 .set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422 - 1670 .set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423 - 1671 .set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424 - 1672 .set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425 - 1673 .set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426 - 1674 .set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427 - 1675 .set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428 - 1676 .set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429 - 1677 .set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a - 1678 .set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b - 1679 .set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c - 1680 .set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d - 1681 .set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e - 1682 .set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f - 1683 .set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430 - 1684 .set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431 - 1685 .set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432 - 1686 .set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433 - 1687 .set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434 - 1688 .set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435 - 1689 .set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436 - 1690 .set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437 - 1691 .set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438 - 1692 .set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 31 - - - 1693 .set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a - 1694 .set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b - 1695 .set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c - 1696 .set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d - 1697 .set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e - 1698 .set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f - 1699 .set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440 - 1700 .set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441 - 1701 .set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442 - 1702 .set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443 - 1703 .set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444 - 1704 .set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445 - 1705 .set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446 - 1706 .set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447 - 1707 .set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448 - 1708 .set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449 - 1709 .set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a - 1710 .set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b - 1711 .set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c - 1712 .set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d - 1713 .set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e - 1714 .set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f - 1715 .set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450 - 1716 .set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451 - 1717 .set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452 - 1718 .set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453 - 1719 .set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454 - 1720 .set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455 - 1721 .set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456 - 1722 .set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457 - 1723 .set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458 - 1724 .set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459 - 1725 .set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a - 1726 .set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b - 1727 .set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c - 1728 .set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d - 1729 .set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e - 1730 .set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f - 1731 .set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460 - 1732 .set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461 - 1733 .set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462 - 1734 .set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463 - 1735 .set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464 - 1736 .set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465 - 1737 .set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466 - 1738 .set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467 - 1739 .set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468 - 1740 .set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469 - 1741 .set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a - 1742 .set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b - 1743 .set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c - 1744 .set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d - 1745 .set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e - 1746 .set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f - 1747 .set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470 - 1748 .set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471 - 1749 .set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 32 - - - 1750 .set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473 - 1751 .set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474 - 1752 .set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475 - 1753 .set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476 - 1754 .set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477 - 1755 .set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478 - 1756 .set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479 - 1757 .set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a - 1758 .set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b - 1759 .set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c - 1760 .set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d - 1761 .set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e - 1762 .set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f - 1763 .set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480 - 1764 .set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481 - 1765 .set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482 - 1766 .set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483 - 1767 .set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484 - 1768 .set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485 - 1769 .set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486 - 1770 .set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487 - 1771 .set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488 - 1772 .set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489 - 1773 .set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a - 1774 .set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b - 1775 .set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c - 1776 .set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d - 1777 .set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e - 1778 .set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f - 1779 .set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490 - 1780 .set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491 - 1781 .set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492 - 1782 .set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493 - 1783 .set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494 - 1784 .set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495 - 1785 .set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496 - 1786 .set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497 - 1787 .set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498 - 1788 .set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499 - 1789 .set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a - 1790 .set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b - 1791 .set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c - 1792 .set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d - 1793 .set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e - 1794 .set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f - 1795 .set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0 - 1796 .set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1 - 1797 .set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2 - 1798 .set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3 - 1799 .set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4 - 1800 .set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5 - 1801 .set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6 - 1802 .set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7 - 1803 .set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8 - 1804 .set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9 - 1805 .set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa - 1806 .set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 33 - - - 1807 .set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac - 1808 .set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad - 1809 .set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae - 1810 .set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af - 1811 .set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 - 1812 .set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 - 1813 .set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504 - 1814 .set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505 - 1815 .set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506 - 1816 .set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507 - 1817 .set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508 - 1818 .set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509 - 1819 .set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a - 1820 .set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b - 1821 .set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514 - 1822 .set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515 - 1823 .set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516 - 1824 .set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517 - 1825 .set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518 - 1826 .set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519 - 1827 .set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a - 1828 .set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b - 1829 .set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524 - 1830 .set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525 - 1831 .set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526 - 1832 .set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527 - 1833 .set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528 - 1834 .set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529 - 1835 .set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a - 1836 .set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b - 1837 .set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534 - 1838 .set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535 - 1839 .set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536 - 1840 .set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537 - 1841 .set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538 - 1842 .set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539 - 1843 .set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a - 1844 .set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b - 1845 .set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544 - 1846 .set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545 - 1847 .set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546 - 1848 .set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547 - 1849 .set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548 - 1850 .set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549 - 1851 .set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a - 1852 .set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b - 1853 .set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554 - 1854 .set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555 - 1855 .set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556 - 1856 .set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557 - 1857 .set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558 - 1858 .set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559 - 1859 .set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a - 1860 .set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b - 1861 .set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564 - 1862 .set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565 - 1863 .set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 34 - - - 1864 .set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567 - 1865 .set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568 - 1866 .set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569 - 1867 .set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a - 1868 .set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b - 1869 .set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574 - 1870 .set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575 - 1871 .set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576 - 1872 .set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577 - 1873 .set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578 - 1874 .set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579 - 1875 .set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a - 1876 .set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b - 1877 .set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584 - 1878 .set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585 - 1879 .set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586 - 1880 .set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587 - 1881 .set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588 - 1882 .set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589 - 1883 .set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a - 1884 .set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b - 1885 .set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594 - 1886 .set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595 - 1887 .set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596 - 1888 .set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597 - 1889 .set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598 - 1890 .set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599 - 1891 .set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a - 1892 .set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b - 1893 .set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4 - 1894 .set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5 - 1895 .set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6 - 1896 .set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7 - 1897 .set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8 - 1898 .set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9 - 1899 .set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa - 1900 .set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab - 1901 .set CYDEV_UWRK_UWRK16_BASE, 0x40006800 - 1902 .set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 - 1903 .set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 - 1904 .set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 - 1905 .set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 - 1906 .set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 - 1907 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800 - 1908 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802 - 1909 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804 - 1910 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806 - 1911 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808 - 1912 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a - 1913 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c - 1914 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e - 1915 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810 - 1916 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812 - 1917 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814 - 1918 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816 - 1919 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818 - 1920 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 35 - - - 1921 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c - 1922 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e - 1923 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840 - 1924 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842 - 1925 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844 - 1926 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846 - 1927 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848 - 1928 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a - 1929 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c - 1930 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e - 1931 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850 - 1932 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852 - 1933 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854 - 1934 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856 - 1935 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858 - 1936 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a - 1937 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c - 1938 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e - 1939 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880 - 1940 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882 - 1941 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884 - 1942 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886 - 1943 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888 - 1944 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a - 1945 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c - 1946 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e - 1947 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890 - 1948 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892 - 1949 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894 - 1950 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896 - 1951 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898 - 1952 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a - 1953 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c - 1954 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e - 1955 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0 - 1956 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2 - 1957 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4 - 1958 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6 - 1959 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8 - 1960 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca - 1961 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc - 1962 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce - 1963 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0 - 1964 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2 - 1965 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4 - 1966 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6 - 1967 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8 - 1968 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da - 1969 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc - 1970 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de - 1971 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900 - 1972 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902 - 1973 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904 - 1974 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906 - 1975 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908 - 1976 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a - 1977 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 36 - - - 1978 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e - 1979 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910 - 1980 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912 - 1981 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914 - 1982 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916 - 1983 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918 - 1984 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a - 1985 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c - 1986 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e - 1987 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940 - 1988 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942 - 1989 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944 - 1990 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946 - 1991 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948 - 1992 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a - 1993 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c - 1994 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e - 1995 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950 - 1996 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952 - 1997 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954 - 1998 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956 - 1999 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958 - 2000 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a - 2001 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c - 2002 .set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e - 2003 .set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 - 2004 .set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 - 2005 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08 - 2006 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a - 2007 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c - 2008 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e - 2009 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10 - 2010 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12 - 2011 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14 - 2012 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16 - 2013 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48 - 2014 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a - 2015 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c - 2016 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e - 2017 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50 - 2018 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52 - 2019 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54 - 2020 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56 - 2021 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88 - 2022 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a - 2023 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c - 2024 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e - 2025 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90 - 2026 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92 - 2027 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94 - 2028 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96 - 2029 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8 - 2030 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca - 2031 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc - 2032 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace - 2033 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0 - 2034 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 37 - - - 2035 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4 - 2036 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6 - 2037 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08 - 2038 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a - 2039 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c - 2040 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e - 2041 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10 - 2042 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12 - 2043 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14 - 2044 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16 - 2045 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48 - 2046 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a - 2047 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c - 2048 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e - 2049 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50 - 2050 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52 - 2051 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54 - 2052 .set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56 - 2053 .set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 - 2054 .set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e - 2055 .set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 - 2056 .set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e - 2057 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800 - 2058 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802 - 2059 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804 - 2060 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806 - 2061 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808 - 2062 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a - 2063 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c - 2064 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e - 2065 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810 - 2066 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812 - 2067 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814 - 2068 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816 - 2069 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818 - 2070 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a - 2071 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c - 2072 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820 - 2073 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822 - 2074 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824 - 2075 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826 - 2076 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828 - 2077 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a - 2078 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c - 2079 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e - 2080 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830 - 2081 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832 - 2082 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834 - 2083 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836 - 2084 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838 - 2085 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a - 2086 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c - 2087 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840 - 2088 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842 - 2089 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844 - 2090 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846 - 2091 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 38 - - - 2092 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a - 2093 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c - 2094 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e - 2095 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850 - 2096 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852 - 2097 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854 - 2098 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856 - 2099 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858 - 2100 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a - 2101 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c - 2102 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860 - 2103 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862 - 2104 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864 - 2105 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866 - 2106 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868 - 2107 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a - 2108 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c - 2109 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e - 2110 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870 - 2111 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872 - 2112 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874 - 2113 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876 - 2114 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878 - 2115 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a - 2116 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c - 2117 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880 - 2118 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882 - 2119 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884 - 2120 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886 - 2121 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888 - 2122 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a - 2123 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c - 2124 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e - 2125 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890 - 2126 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892 - 2127 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894 - 2128 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896 - 2129 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898 - 2130 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a - 2131 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c - 2132 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0 - 2133 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2 - 2134 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4 - 2135 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6 - 2136 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8 - 2137 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa - 2138 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac - 2139 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae - 2140 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0 - 2141 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2 - 2142 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4 - 2143 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6 - 2144 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8 - 2145 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba - 2146 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc - 2147 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0 - 2148 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 39 - - - 2149 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4 - 2150 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6 - 2151 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8 - 2152 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca - 2153 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc - 2154 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce - 2155 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0 - 2156 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2 - 2157 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4 - 2158 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6 - 2159 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8 - 2160 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da - 2161 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc - 2162 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0 - 2163 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2 - 2164 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4 - 2165 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6 - 2166 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8 - 2167 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea - 2168 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec - 2169 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee - 2170 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0 - 2171 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2 - 2172 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4 - 2173 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6 - 2174 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8 - 2175 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa - 2176 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc - 2177 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900 - 2178 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902 - 2179 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904 - 2180 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906 - 2181 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908 - 2182 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a - 2183 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c - 2184 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e - 2185 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910 - 2186 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912 - 2187 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914 - 2188 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916 - 2189 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918 - 2190 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a - 2191 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c - 2192 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920 - 2193 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922 - 2194 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924 - 2195 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926 - 2196 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928 - 2197 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a - 2198 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c - 2199 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e - 2200 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930 - 2201 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932 - 2202 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934 - 2203 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936 - 2204 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938 - 2205 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 40 - - - 2206 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c - 2207 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940 - 2208 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942 - 2209 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944 - 2210 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946 - 2211 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948 - 2212 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a - 2213 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c - 2214 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e - 2215 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950 - 2216 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952 - 2217 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954 - 2218 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956 - 2219 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958 - 2220 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a - 2221 .set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c - 2222 .set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 - 2223 .set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e - 2224 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08 - 2225 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a - 2226 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c - 2227 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e - 2228 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10 - 2229 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12 - 2230 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14 - 2231 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16 - 2232 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28 - 2233 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a - 2234 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c - 2235 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e - 2236 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30 - 2237 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32 - 2238 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34 - 2239 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36 - 2240 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48 - 2241 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a - 2242 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c - 2243 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e - 2244 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50 - 2245 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52 - 2246 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54 - 2247 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56 - 2248 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68 - 2249 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a - 2250 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c - 2251 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e - 2252 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70 - 2253 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72 - 2254 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74 - 2255 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76 - 2256 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88 - 2257 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a - 2258 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c - 2259 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e - 2260 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90 - 2261 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92 - 2262 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 41 - - - 2263 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96 - 2264 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8 - 2265 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa - 2266 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac - 2267 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae - 2268 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0 - 2269 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2 - 2270 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4 - 2271 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6 - 2272 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8 - 2273 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca - 2274 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc - 2275 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace - 2276 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0 - 2277 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2 - 2278 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4 - 2279 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6 - 2280 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8 - 2281 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea - 2282 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec - 2283 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee - 2284 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0 - 2285 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2 - 2286 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4 - 2287 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6 - 2288 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08 - 2289 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a - 2290 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c - 2291 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e - 2292 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10 - 2293 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12 - 2294 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14 - 2295 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16 - 2296 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28 - 2297 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a - 2298 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c - 2299 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e - 2300 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30 - 2301 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32 - 2302 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34 - 2303 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36 - 2304 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48 - 2305 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a - 2306 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c - 2307 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e - 2308 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50 - 2309 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52 - 2310 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54 - 2311 .set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56 - 2312 .set CYDEV_PHUB_BASE, 0x40007000 - 2313 .set CYDEV_PHUB_SIZE, 0x00000c00 - 2314 .set CYDEV_PHUB_CFG, 0x40007000 - 2315 .set CYDEV_PHUB_ERR, 0x40007004 - 2316 .set CYDEV_PHUB_ERR_ADR, 0x40007008 - 2317 .set CYDEV_PHUB_CH0_BASE, 0x40007010 - 2318 .set CYDEV_PHUB_CH0_SIZE, 0x0000000c - 2319 .set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 42 - - - 2320 .set CYDEV_PHUB_CH0_ACTION, 0x40007014 - 2321 .set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018 - 2322 .set CYDEV_PHUB_CH1_BASE, 0x40007020 - 2323 .set CYDEV_PHUB_CH1_SIZE, 0x0000000c - 2324 .set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020 - 2325 .set CYDEV_PHUB_CH1_ACTION, 0x40007024 - 2326 .set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028 - 2327 .set CYDEV_PHUB_CH2_BASE, 0x40007030 - 2328 .set CYDEV_PHUB_CH2_SIZE, 0x0000000c - 2329 .set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030 - 2330 .set CYDEV_PHUB_CH2_ACTION, 0x40007034 - 2331 .set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038 - 2332 .set CYDEV_PHUB_CH3_BASE, 0x40007040 - 2333 .set CYDEV_PHUB_CH3_SIZE, 0x0000000c - 2334 .set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040 - 2335 .set CYDEV_PHUB_CH3_ACTION, 0x40007044 - 2336 .set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048 - 2337 .set CYDEV_PHUB_CH4_BASE, 0x40007050 - 2338 .set CYDEV_PHUB_CH4_SIZE, 0x0000000c - 2339 .set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050 - 2340 .set CYDEV_PHUB_CH4_ACTION, 0x40007054 - 2341 .set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058 - 2342 .set CYDEV_PHUB_CH5_BASE, 0x40007060 - 2343 .set CYDEV_PHUB_CH5_SIZE, 0x0000000c - 2344 .set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060 - 2345 .set CYDEV_PHUB_CH5_ACTION, 0x40007064 - 2346 .set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068 - 2347 .set CYDEV_PHUB_CH6_BASE, 0x40007070 - 2348 .set CYDEV_PHUB_CH6_SIZE, 0x0000000c - 2349 .set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070 - 2350 .set CYDEV_PHUB_CH6_ACTION, 0x40007074 - 2351 .set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078 - 2352 .set CYDEV_PHUB_CH7_BASE, 0x40007080 - 2353 .set CYDEV_PHUB_CH7_SIZE, 0x0000000c - 2354 .set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080 - 2355 .set CYDEV_PHUB_CH7_ACTION, 0x40007084 - 2356 .set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088 - 2357 .set CYDEV_PHUB_CH8_BASE, 0x40007090 - 2358 .set CYDEV_PHUB_CH8_SIZE, 0x0000000c - 2359 .set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090 - 2360 .set CYDEV_PHUB_CH8_ACTION, 0x40007094 - 2361 .set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098 - 2362 .set CYDEV_PHUB_CH9_BASE, 0x400070a0 - 2363 .set CYDEV_PHUB_CH9_SIZE, 0x0000000c - 2364 .set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0 - 2365 .set CYDEV_PHUB_CH9_ACTION, 0x400070a4 - 2366 .set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8 - 2367 .set CYDEV_PHUB_CH10_BASE, 0x400070b0 - 2368 .set CYDEV_PHUB_CH10_SIZE, 0x0000000c - 2369 .set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0 - 2370 .set CYDEV_PHUB_CH10_ACTION, 0x400070b4 - 2371 .set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8 - 2372 .set CYDEV_PHUB_CH11_BASE, 0x400070c0 - 2373 .set CYDEV_PHUB_CH11_SIZE, 0x0000000c - 2374 .set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0 - 2375 .set CYDEV_PHUB_CH11_ACTION, 0x400070c4 - 2376 .set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 43 - - - 2377 .set CYDEV_PHUB_CH12_BASE, 0x400070d0 - 2378 .set CYDEV_PHUB_CH12_SIZE, 0x0000000c - 2379 .set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0 - 2380 .set CYDEV_PHUB_CH12_ACTION, 0x400070d4 - 2381 .set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8 - 2382 .set CYDEV_PHUB_CH13_BASE, 0x400070e0 - 2383 .set CYDEV_PHUB_CH13_SIZE, 0x0000000c - 2384 .set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0 - 2385 .set CYDEV_PHUB_CH13_ACTION, 0x400070e4 - 2386 .set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8 - 2387 .set CYDEV_PHUB_CH14_BASE, 0x400070f0 - 2388 .set CYDEV_PHUB_CH14_SIZE, 0x0000000c - 2389 .set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0 - 2390 .set CYDEV_PHUB_CH14_ACTION, 0x400070f4 - 2391 .set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8 - 2392 .set CYDEV_PHUB_CH15_BASE, 0x40007100 - 2393 .set CYDEV_PHUB_CH15_SIZE, 0x0000000c - 2394 .set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100 - 2395 .set CYDEV_PHUB_CH15_ACTION, 0x40007104 - 2396 .set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108 - 2397 .set CYDEV_PHUB_CH16_BASE, 0x40007110 - 2398 .set CYDEV_PHUB_CH16_SIZE, 0x0000000c - 2399 .set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110 - 2400 .set CYDEV_PHUB_CH16_ACTION, 0x40007114 - 2401 .set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118 - 2402 .set CYDEV_PHUB_CH17_BASE, 0x40007120 - 2403 .set CYDEV_PHUB_CH17_SIZE, 0x0000000c - 2404 .set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120 - 2405 .set CYDEV_PHUB_CH17_ACTION, 0x40007124 - 2406 .set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128 - 2407 .set CYDEV_PHUB_CH18_BASE, 0x40007130 - 2408 .set CYDEV_PHUB_CH18_SIZE, 0x0000000c - 2409 .set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130 - 2410 .set CYDEV_PHUB_CH18_ACTION, 0x40007134 - 2411 .set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138 - 2412 .set CYDEV_PHUB_CH19_BASE, 0x40007140 - 2413 .set CYDEV_PHUB_CH19_SIZE, 0x0000000c - 2414 .set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140 - 2415 .set CYDEV_PHUB_CH19_ACTION, 0x40007144 - 2416 .set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148 - 2417 .set CYDEV_PHUB_CH20_BASE, 0x40007150 - 2418 .set CYDEV_PHUB_CH20_SIZE, 0x0000000c - 2419 .set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150 - 2420 .set CYDEV_PHUB_CH20_ACTION, 0x40007154 - 2421 .set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158 - 2422 .set CYDEV_PHUB_CH21_BASE, 0x40007160 - 2423 .set CYDEV_PHUB_CH21_SIZE, 0x0000000c - 2424 .set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160 - 2425 .set CYDEV_PHUB_CH21_ACTION, 0x40007164 - 2426 .set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168 - 2427 .set CYDEV_PHUB_CH22_BASE, 0x40007170 - 2428 .set CYDEV_PHUB_CH22_SIZE, 0x0000000c - 2429 .set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170 - 2430 .set CYDEV_PHUB_CH22_ACTION, 0x40007174 - 2431 .set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178 - 2432 .set CYDEV_PHUB_CH23_BASE, 0x40007180 - 2433 .set CYDEV_PHUB_CH23_SIZE, 0x0000000c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 44 - - - 2434 .set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180 - 2435 .set CYDEV_PHUB_CH23_ACTION, 0x40007184 - 2436 .set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188 - 2437 .set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 - 2438 .set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 - 2439 .set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600 - 2440 .set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604 - 2441 .set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 - 2442 .set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 - 2443 .set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608 - 2444 .set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c - 2445 .set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 - 2446 .set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 - 2447 .set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610 - 2448 .set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614 - 2449 .set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 - 2450 .set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 - 2451 .set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618 - 2452 .set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c - 2453 .set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 - 2454 .set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 - 2455 .set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620 - 2456 .set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624 - 2457 .set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 - 2458 .set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 - 2459 .set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628 - 2460 .set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c - 2461 .set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 - 2462 .set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 - 2463 .set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630 - 2464 .set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634 - 2465 .set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 - 2466 .set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 - 2467 .set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638 - 2468 .set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c - 2469 .set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 - 2470 .set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 - 2471 .set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640 - 2472 .set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644 - 2473 .set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 - 2474 .set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 - 2475 .set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648 - 2476 .set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c - 2477 .set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 - 2478 .set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 - 2479 .set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650 - 2480 .set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654 - 2481 .set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 - 2482 .set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 - 2483 .set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658 - 2484 .set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c - 2485 .set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 - 2486 .set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 - 2487 .set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660 - 2488 .set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664 - 2489 .set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 - 2490 .set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 45 - - - 2491 .set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668 - 2492 .set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c - 2493 .set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 - 2494 .set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 - 2495 .set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670 - 2496 .set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674 - 2497 .set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 - 2498 .set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 - 2499 .set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678 - 2500 .set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c - 2501 .set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 - 2502 .set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 - 2503 .set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680 - 2504 .set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684 - 2505 .set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 - 2506 .set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 - 2507 .set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688 - 2508 .set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c - 2509 .set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 - 2510 .set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 - 2511 .set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690 - 2512 .set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694 - 2513 .set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 - 2514 .set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 - 2515 .set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698 - 2516 .set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c - 2517 .set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 - 2518 .set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 - 2519 .set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0 - 2520 .set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4 - 2521 .set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 - 2522 .set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 - 2523 .set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8 - 2524 .set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac - 2525 .set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 - 2526 .set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 - 2527 .set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0 - 2528 .set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4 - 2529 .set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 - 2530 .set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 - 2531 .set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8 - 2532 .set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc - 2533 .set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 - 2534 .set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 - 2535 .set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800 - 2536 .set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804 - 2537 .set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 - 2538 .set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 - 2539 .set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808 - 2540 .set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c - 2541 .set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 - 2542 .set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 - 2543 .set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810 - 2544 .set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814 - 2545 .set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 - 2546 .set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 - 2547 .set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 46 - - - 2548 .set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c - 2549 .set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 - 2550 .set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 - 2551 .set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820 - 2552 .set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824 - 2553 .set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 - 2554 .set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 - 2555 .set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828 - 2556 .set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c - 2557 .set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 - 2558 .set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 - 2559 .set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830 - 2560 .set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834 - 2561 .set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 - 2562 .set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 - 2563 .set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838 - 2564 .set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c - 2565 .set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 - 2566 .set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 - 2567 .set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840 - 2568 .set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844 - 2569 .set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 - 2570 .set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 - 2571 .set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848 - 2572 .set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c - 2573 .set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 - 2574 .set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 - 2575 .set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850 - 2576 .set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854 - 2577 .set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 - 2578 .set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 - 2579 .set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858 - 2580 .set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c - 2581 .set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 - 2582 .set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 - 2583 .set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860 - 2584 .set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864 - 2585 .set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 - 2586 .set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 - 2587 .set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868 - 2588 .set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c - 2589 .set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 - 2590 .set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 - 2591 .set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870 - 2592 .set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874 - 2593 .set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 - 2594 .set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 - 2595 .set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878 - 2596 .set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c - 2597 .set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 - 2598 .set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 - 2599 .set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880 - 2600 .set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884 - 2601 .set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 - 2602 .set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 - 2603 .set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888 - 2604 .set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 47 - - - 2605 .set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 - 2606 .set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 - 2607 .set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890 - 2608 .set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894 - 2609 .set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 - 2610 .set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 - 2611 .set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898 - 2612 .set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c - 2613 .set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 - 2614 .set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 - 2615 .set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 - 2616 .set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 - 2617 .set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 - 2618 .set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 - 2619 .set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 - 2620 .set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac - 2621 .set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 - 2622 .set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 - 2623 .set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 - 2624 .set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 - 2625 .set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 - 2626 .set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 - 2627 .set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 - 2628 .set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc - 2629 .set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 - 2630 .set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 - 2631 .set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 - 2632 .set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 - 2633 .set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 - 2634 .set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 - 2635 .set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 - 2636 .set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc - 2637 .set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 - 2638 .set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 - 2639 .set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 - 2640 .set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 - 2641 .set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 - 2642 .set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 - 2643 .set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 - 2644 .set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc - 2645 .set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 - 2646 .set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 - 2647 .set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 - 2648 .set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 - 2649 .set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 - 2650 .set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 - 2651 .set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 - 2652 .set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec - 2653 .set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 - 2654 .set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 - 2655 .set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 - 2656 .set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 - 2657 .set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 - 2658 .set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 - 2659 .set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 - 2660 .set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc - 2661 .set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 48 - - - 2662 .set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 - 2663 .set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900 - 2664 .set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904 - 2665 .set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 - 2666 .set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 - 2667 .set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908 - 2668 .set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c - 2669 .set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 - 2670 .set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 - 2671 .set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910 - 2672 .set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914 - 2673 .set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 - 2674 .set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 - 2675 .set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918 - 2676 .set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c - 2677 .set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 - 2678 .set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 - 2679 .set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920 - 2680 .set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924 - 2681 .set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 - 2682 .set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 - 2683 .set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928 - 2684 .set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c - 2685 .set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 - 2686 .set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 - 2687 .set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930 - 2688 .set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934 - 2689 .set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 - 2690 .set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 - 2691 .set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938 - 2692 .set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c - 2693 .set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 - 2694 .set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 - 2695 .set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940 - 2696 .set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944 - 2697 .set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 - 2698 .set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 - 2699 .set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948 - 2700 .set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c - 2701 .set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 - 2702 .set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 - 2703 .set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950 - 2704 .set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954 - 2705 .set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 - 2706 .set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 - 2707 .set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958 - 2708 .set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c - 2709 .set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 - 2710 .set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 - 2711 .set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960 - 2712 .set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964 - 2713 .set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 - 2714 .set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 - 2715 .set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968 - 2716 .set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c - 2717 .set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 - 2718 .set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 49 - - - 2719 .set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970 - 2720 .set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974 - 2721 .set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 - 2722 .set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 - 2723 .set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978 - 2724 .set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c - 2725 .set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 - 2726 .set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 - 2727 .set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980 - 2728 .set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984 - 2729 .set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 - 2730 .set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 - 2731 .set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988 - 2732 .set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c - 2733 .set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 - 2734 .set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 - 2735 .set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990 - 2736 .set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994 - 2737 .set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 - 2738 .set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 - 2739 .set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998 - 2740 .set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c - 2741 .set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 - 2742 .set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 - 2743 .set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 - 2744 .set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 - 2745 .set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 - 2746 .set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 - 2747 .set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 - 2748 .set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac - 2749 .set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 - 2750 .set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 - 2751 .set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 - 2752 .set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 - 2753 .set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 - 2754 .set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 - 2755 .set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 - 2756 .set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc - 2757 .set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 - 2758 .set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 - 2759 .set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 - 2760 .set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 - 2761 .set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 - 2762 .set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 - 2763 .set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 - 2764 .set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc - 2765 .set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 - 2766 .set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 - 2767 .set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 - 2768 .set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 - 2769 .set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 - 2770 .set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 - 2771 .set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 - 2772 .set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc - 2773 .set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 - 2774 .set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 - 2775 .set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 50 - - - 2776 .set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 - 2777 .set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 - 2778 .set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 - 2779 .set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 - 2780 .set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec - 2781 .set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 - 2782 .set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 - 2783 .set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 - 2784 .set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 - 2785 .set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 - 2786 .set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 - 2787 .set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 - 2788 .set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc - 2789 .set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 - 2790 .set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 - 2791 .set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 - 2792 .set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 - 2793 .set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 - 2794 .set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 - 2795 .set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 - 2796 .set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c - 2797 .set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 - 2798 .set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 - 2799 .set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 - 2800 .set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 - 2801 .set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 - 2802 .set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 - 2803 .set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 - 2804 .set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c - 2805 .set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 - 2806 .set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 - 2807 .set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 - 2808 .set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 - 2809 .set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 - 2810 .set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 - 2811 .set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 - 2812 .set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c - 2813 .set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 - 2814 .set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 - 2815 .set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 - 2816 .set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 - 2817 .set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 - 2818 .set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 - 2819 .set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 - 2820 .set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c - 2821 .set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 - 2822 .set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 - 2823 .set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 - 2824 .set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 - 2825 .set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 - 2826 .set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 - 2827 .set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 - 2828 .set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c - 2829 .set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 - 2830 .set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 - 2831 .set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 - 2832 .set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 51 - - - 2833 .set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 - 2834 .set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 - 2835 .set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 - 2836 .set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c - 2837 .set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 - 2838 .set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 - 2839 .set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 - 2840 .set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 - 2841 .set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 - 2842 .set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 - 2843 .set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 - 2844 .set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c - 2845 .set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 - 2846 .set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 - 2847 .set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 - 2848 .set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 - 2849 .set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 - 2850 .set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 - 2851 .set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 - 2852 .set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c - 2853 .set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 - 2854 .set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 - 2855 .set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 - 2856 .set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 - 2857 .set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 - 2858 .set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 - 2859 .set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 - 2860 .set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c - 2861 .set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 - 2862 .set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 - 2863 .set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 - 2864 .set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 - 2865 .set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 - 2866 .set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 - 2867 .set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 - 2868 .set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c - 2869 .set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 - 2870 .set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 - 2871 .set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 - 2872 .set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 - 2873 .set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 - 2874 .set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 - 2875 .set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 - 2876 .set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac - 2877 .set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 - 2878 .set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 - 2879 .set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 - 2880 .set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 - 2881 .set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 - 2882 .set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 - 2883 .set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 - 2884 .set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc - 2885 .set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 - 2886 .set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 - 2887 .set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 - 2888 .set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 - 2889 .set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 52 - - - 2890 .set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 - 2891 .set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 - 2892 .set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc - 2893 .set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 - 2894 .set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 - 2895 .set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 - 2896 .set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 - 2897 .set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 - 2898 .set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 - 2899 .set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 - 2900 .set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc - 2901 .set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 - 2902 .set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 - 2903 .set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 - 2904 .set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 - 2905 .set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 - 2906 .set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 - 2907 .set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 - 2908 .set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec - 2909 .set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 - 2910 .set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 - 2911 .set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 - 2912 .set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 - 2913 .set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 - 2914 .set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 - 2915 .set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 - 2916 .set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc - 2917 .set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 - 2918 .set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 - 2919 .set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 - 2920 .set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 - 2921 .set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 - 2922 .set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 - 2923 .set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 - 2924 .set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c - 2925 .set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 - 2926 .set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 - 2927 .set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 - 2928 .set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 - 2929 .set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 - 2930 .set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 - 2931 .set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 - 2932 .set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c - 2933 .set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 - 2934 .set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 - 2935 .set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 - 2936 .set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 - 2937 .set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 - 2938 .set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 - 2939 .set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 - 2940 .set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c - 2941 .set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 - 2942 .set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 - 2943 .set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 - 2944 .set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 - 2945 .set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 - 2946 .set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 53 - - - 2947 .set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 - 2948 .set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c - 2949 .set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 - 2950 .set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 - 2951 .set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 - 2952 .set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 - 2953 .set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 - 2954 .set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 - 2955 .set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 - 2956 .set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c - 2957 .set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 - 2958 .set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 - 2959 .set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 - 2960 .set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 - 2961 .set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 - 2962 .set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 - 2963 .set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 - 2964 .set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c - 2965 .set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 - 2966 .set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 - 2967 .set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 - 2968 .set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 - 2969 .set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 - 2970 .set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 - 2971 .set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 - 2972 .set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c - 2973 .set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 - 2974 .set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 - 2975 .set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 - 2976 .set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 - 2977 .set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 - 2978 .set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 - 2979 .set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 - 2980 .set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c - 2981 .set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 - 2982 .set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 - 2983 .set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 - 2984 .set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 - 2985 .set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 - 2986 .set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 - 2987 .set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 - 2988 .set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c - 2989 .set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 - 2990 .set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 - 2991 .set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 - 2992 .set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 - 2993 .set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 - 2994 .set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 - 2995 .set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 - 2996 .set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c - 2997 .set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 - 2998 .set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 - 2999 .set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 - 3000 .set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 - 3001 .set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 - 3002 .set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 - 3003 .set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 54 - - - 3004 .set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac - 3005 .set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 - 3006 .set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 - 3007 .set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 - 3008 .set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 - 3009 .set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 - 3010 .set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 - 3011 .set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 - 3012 .set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc - 3013 .set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 - 3014 .set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 - 3015 .set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 - 3016 .set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 - 3017 .set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 - 3018 .set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 - 3019 .set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 - 3020 .set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc - 3021 .set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 - 3022 .set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 - 3023 .set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 - 3024 .set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 - 3025 .set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 - 3026 .set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 - 3027 .set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 - 3028 .set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc - 3029 .set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 - 3030 .set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 - 3031 .set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 - 3032 .set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 - 3033 .set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 - 3034 .set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 - 3035 .set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 - 3036 .set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec - 3037 .set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 - 3038 .set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 - 3039 .set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 - 3040 .set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 - 3041 .set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 - 3042 .set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 - 3043 .set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 - 3044 .set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc - 3045 .set CYDEV_EE_BASE, 0x40008000 - 3046 .set CYDEV_EE_SIZE, 0x00000800 - 3047 .set CYDEV_EE_DATA_MBASE, 0x40008000 - 3048 .set CYDEV_EE_DATA_MSIZE, 0x00000800 - 3049 .set CYDEV_CAN0_BASE, 0x4000a000 - 3050 .set CYDEV_CAN0_SIZE, 0x000002a0 - 3051 .set CYDEV_CAN0_CSR_BASE, 0x4000a000 - 3052 .set CYDEV_CAN0_CSR_SIZE, 0x00000018 - 3053 .set CYDEV_CAN0_CSR_INT_SR, 0x4000a000 - 3054 .set CYDEV_CAN0_CSR_INT_EN, 0x4000a004 - 3055 .set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008 - 3056 .set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c - 3057 .set CYDEV_CAN0_CSR_CMD, 0x4000a010 - 3058 .set CYDEV_CAN0_CSR_CFG, 0x4000a014 - 3059 .set CYDEV_CAN0_TX0_BASE, 0x4000a020 - 3060 .set CYDEV_CAN0_TX0_SIZE, 0x00000010 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 55 - - - 3061 .set CYDEV_CAN0_TX0_CMD, 0x4000a020 - 3062 .set CYDEV_CAN0_TX0_ID, 0x4000a024 - 3063 .set CYDEV_CAN0_TX0_DH, 0x4000a028 - 3064 .set CYDEV_CAN0_TX0_DL, 0x4000a02c - 3065 .set CYDEV_CAN0_TX1_BASE, 0x4000a030 - 3066 .set CYDEV_CAN0_TX1_SIZE, 0x00000010 - 3067 .set CYDEV_CAN0_TX1_CMD, 0x4000a030 - 3068 .set CYDEV_CAN0_TX1_ID, 0x4000a034 - 3069 .set CYDEV_CAN0_TX1_DH, 0x4000a038 - 3070 .set CYDEV_CAN0_TX1_DL, 0x4000a03c - 3071 .set CYDEV_CAN0_TX2_BASE, 0x4000a040 - 3072 .set CYDEV_CAN0_TX2_SIZE, 0x00000010 - 3073 .set CYDEV_CAN0_TX2_CMD, 0x4000a040 - 3074 .set CYDEV_CAN0_TX2_ID, 0x4000a044 - 3075 .set CYDEV_CAN0_TX2_DH, 0x4000a048 - 3076 .set CYDEV_CAN0_TX2_DL, 0x4000a04c - 3077 .set CYDEV_CAN0_TX3_BASE, 0x4000a050 - 3078 .set CYDEV_CAN0_TX3_SIZE, 0x00000010 - 3079 .set CYDEV_CAN0_TX3_CMD, 0x4000a050 - 3080 .set CYDEV_CAN0_TX3_ID, 0x4000a054 - 3081 .set CYDEV_CAN0_TX3_DH, 0x4000a058 - 3082 .set CYDEV_CAN0_TX3_DL, 0x4000a05c - 3083 .set CYDEV_CAN0_TX4_BASE, 0x4000a060 - 3084 .set CYDEV_CAN0_TX4_SIZE, 0x00000010 - 3085 .set CYDEV_CAN0_TX4_CMD, 0x4000a060 - 3086 .set CYDEV_CAN0_TX4_ID, 0x4000a064 - 3087 .set CYDEV_CAN0_TX4_DH, 0x4000a068 - 3088 .set CYDEV_CAN0_TX4_DL, 0x4000a06c - 3089 .set CYDEV_CAN0_TX5_BASE, 0x4000a070 - 3090 .set CYDEV_CAN0_TX5_SIZE, 0x00000010 - 3091 .set CYDEV_CAN0_TX5_CMD, 0x4000a070 - 3092 .set CYDEV_CAN0_TX5_ID, 0x4000a074 - 3093 .set CYDEV_CAN0_TX5_DH, 0x4000a078 - 3094 .set CYDEV_CAN0_TX5_DL, 0x4000a07c - 3095 .set CYDEV_CAN0_TX6_BASE, 0x4000a080 - 3096 .set CYDEV_CAN0_TX6_SIZE, 0x00000010 - 3097 .set CYDEV_CAN0_TX6_CMD, 0x4000a080 - 3098 .set CYDEV_CAN0_TX6_ID, 0x4000a084 - 3099 .set CYDEV_CAN0_TX6_DH, 0x4000a088 - 3100 .set CYDEV_CAN0_TX6_DL, 0x4000a08c - 3101 .set CYDEV_CAN0_TX7_BASE, 0x4000a090 - 3102 .set CYDEV_CAN0_TX7_SIZE, 0x00000010 - 3103 .set CYDEV_CAN0_TX7_CMD, 0x4000a090 - 3104 .set CYDEV_CAN0_TX7_ID, 0x4000a094 - 3105 .set CYDEV_CAN0_TX7_DH, 0x4000a098 - 3106 .set CYDEV_CAN0_TX7_DL, 0x4000a09c - 3107 .set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 - 3108 .set CYDEV_CAN0_RX0_SIZE, 0x00000020 - 3109 .set CYDEV_CAN0_RX0_CMD, 0x4000a0a0 - 3110 .set CYDEV_CAN0_RX0_ID, 0x4000a0a4 - 3111 .set CYDEV_CAN0_RX0_DH, 0x4000a0a8 - 3112 .set CYDEV_CAN0_RX0_DL, 0x4000a0ac - 3113 .set CYDEV_CAN0_RX0_AMR, 0x4000a0b0 - 3114 .set CYDEV_CAN0_RX0_ACR, 0x4000a0b4 - 3115 .set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8 - 3116 .set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc - 3117 .set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 56 - - - 3118 .set CYDEV_CAN0_RX1_SIZE, 0x00000020 - 3119 .set CYDEV_CAN0_RX1_CMD, 0x4000a0c0 - 3120 .set CYDEV_CAN0_RX1_ID, 0x4000a0c4 - 3121 .set CYDEV_CAN0_RX1_DH, 0x4000a0c8 - 3122 .set CYDEV_CAN0_RX1_DL, 0x4000a0cc - 3123 .set CYDEV_CAN0_RX1_AMR, 0x4000a0d0 - 3124 .set CYDEV_CAN0_RX1_ACR, 0x4000a0d4 - 3125 .set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8 - 3126 .set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc - 3127 .set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 - 3128 .set CYDEV_CAN0_RX2_SIZE, 0x00000020 - 3129 .set CYDEV_CAN0_RX2_CMD, 0x4000a0e0 - 3130 .set CYDEV_CAN0_RX2_ID, 0x4000a0e4 - 3131 .set CYDEV_CAN0_RX2_DH, 0x4000a0e8 - 3132 .set CYDEV_CAN0_RX2_DL, 0x4000a0ec - 3133 .set CYDEV_CAN0_RX2_AMR, 0x4000a0f0 - 3134 .set CYDEV_CAN0_RX2_ACR, 0x4000a0f4 - 3135 .set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8 - 3136 .set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc - 3137 .set CYDEV_CAN0_RX3_BASE, 0x4000a100 - 3138 .set CYDEV_CAN0_RX3_SIZE, 0x00000020 - 3139 .set CYDEV_CAN0_RX3_CMD, 0x4000a100 - 3140 .set CYDEV_CAN0_RX3_ID, 0x4000a104 - 3141 .set CYDEV_CAN0_RX3_DH, 0x4000a108 - 3142 .set CYDEV_CAN0_RX3_DL, 0x4000a10c - 3143 .set CYDEV_CAN0_RX3_AMR, 0x4000a110 - 3144 .set CYDEV_CAN0_RX3_ACR, 0x4000a114 - 3145 .set CYDEV_CAN0_RX3_AMRD, 0x4000a118 - 3146 .set CYDEV_CAN0_RX3_ACRD, 0x4000a11c - 3147 .set CYDEV_CAN0_RX4_BASE, 0x4000a120 - 3148 .set CYDEV_CAN0_RX4_SIZE, 0x00000020 - 3149 .set CYDEV_CAN0_RX4_CMD, 0x4000a120 - 3150 .set CYDEV_CAN0_RX4_ID, 0x4000a124 - 3151 .set CYDEV_CAN0_RX4_DH, 0x4000a128 - 3152 .set CYDEV_CAN0_RX4_DL, 0x4000a12c - 3153 .set CYDEV_CAN0_RX4_AMR, 0x4000a130 - 3154 .set CYDEV_CAN0_RX4_ACR, 0x4000a134 - 3155 .set CYDEV_CAN0_RX4_AMRD, 0x4000a138 - 3156 .set CYDEV_CAN0_RX4_ACRD, 0x4000a13c - 3157 .set CYDEV_CAN0_RX5_BASE, 0x4000a140 - 3158 .set CYDEV_CAN0_RX5_SIZE, 0x00000020 - 3159 .set CYDEV_CAN0_RX5_CMD, 0x4000a140 - 3160 .set CYDEV_CAN0_RX5_ID, 0x4000a144 - 3161 .set CYDEV_CAN0_RX5_DH, 0x4000a148 - 3162 .set CYDEV_CAN0_RX5_DL, 0x4000a14c - 3163 .set CYDEV_CAN0_RX5_AMR, 0x4000a150 - 3164 .set CYDEV_CAN0_RX5_ACR, 0x4000a154 - 3165 .set CYDEV_CAN0_RX5_AMRD, 0x4000a158 - 3166 .set CYDEV_CAN0_RX5_ACRD, 0x4000a15c - 3167 .set CYDEV_CAN0_RX6_BASE, 0x4000a160 - 3168 .set CYDEV_CAN0_RX6_SIZE, 0x00000020 - 3169 .set CYDEV_CAN0_RX6_CMD, 0x4000a160 - 3170 .set CYDEV_CAN0_RX6_ID, 0x4000a164 - 3171 .set CYDEV_CAN0_RX6_DH, 0x4000a168 - 3172 .set CYDEV_CAN0_RX6_DL, 0x4000a16c - 3173 .set CYDEV_CAN0_RX6_AMR, 0x4000a170 - 3174 .set CYDEV_CAN0_RX6_ACR, 0x4000a174 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 57 - - - 3175 .set CYDEV_CAN0_RX6_AMRD, 0x4000a178 - 3176 .set CYDEV_CAN0_RX6_ACRD, 0x4000a17c - 3177 .set CYDEV_CAN0_RX7_BASE, 0x4000a180 - 3178 .set CYDEV_CAN0_RX7_SIZE, 0x00000020 - 3179 .set CYDEV_CAN0_RX7_CMD, 0x4000a180 - 3180 .set CYDEV_CAN0_RX7_ID, 0x4000a184 - 3181 .set CYDEV_CAN0_RX7_DH, 0x4000a188 - 3182 .set CYDEV_CAN0_RX7_DL, 0x4000a18c - 3183 .set CYDEV_CAN0_RX7_AMR, 0x4000a190 - 3184 .set CYDEV_CAN0_RX7_ACR, 0x4000a194 - 3185 .set CYDEV_CAN0_RX7_AMRD, 0x4000a198 - 3186 .set CYDEV_CAN0_RX7_ACRD, 0x4000a19c - 3187 .set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 - 3188 .set CYDEV_CAN0_RX8_SIZE, 0x00000020 - 3189 .set CYDEV_CAN0_RX8_CMD, 0x4000a1a0 - 3190 .set CYDEV_CAN0_RX8_ID, 0x4000a1a4 - 3191 .set CYDEV_CAN0_RX8_DH, 0x4000a1a8 - 3192 .set CYDEV_CAN0_RX8_DL, 0x4000a1ac - 3193 .set CYDEV_CAN0_RX8_AMR, 0x4000a1b0 - 3194 .set CYDEV_CAN0_RX8_ACR, 0x4000a1b4 - 3195 .set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8 - 3196 .set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc - 3197 .set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 - 3198 .set CYDEV_CAN0_RX9_SIZE, 0x00000020 - 3199 .set CYDEV_CAN0_RX9_CMD, 0x4000a1c0 - 3200 .set CYDEV_CAN0_RX9_ID, 0x4000a1c4 - 3201 .set CYDEV_CAN0_RX9_DH, 0x4000a1c8 - 3202 .set CYDEV_CAN0_RX9_DL, 0x4000a1cc - 3203 .set CYDEV_CAN0_RX9_AMR, 0x4000a1d0 - 3204 .set CYDEV_CAN0_RX9_ACR, 0x4000a1d4 - 3205 .set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8 - 3206 .set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc - 3207 .set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 - 3208 .set CYDEV_CAN0_RX10_SIZE, 0x00000020 - 3209 .set CYDEV_CAN0_RX10_CMD, 0x4000a1e0 - 3210 .set CYDEV_CAN0_RX10_ID, 0x4000a1e4 - 3211 .set CYDEV_CAN0_RX10_DH, 0x4000a1e8 - 3212 .set CYDEV_CAN0_RX10_DL, 0x4000a1ec - 3213 .set CYDEV_CAN0_RX10_AMR, 0x4000a1f0 - 3214 .set CYDEV_CAN0_RX10_ACR, 0x4000a1f4 - 3215 .set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8 - 3216 .set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc - 3217 .set CYDEV_CAN0_RX11_BASE, 0x4000a200 - 3218 .set CYDEV_CAN0_RX11_SIZE, 0x00000020 - 3219 .set CYDEV_CAN0_RX11_CMD, 0x4000a200 - 3220 .set CYDEV_CAN0_RX11_ID, 0x4000a204 - 3221 .set CYDEV_CAN0_RX11_DH, 0x4000a208 - 3222 .set CYDEV_CAN0_RX11_DL, 0x4000a20c - 3223 .set CYDEV_CAN0_RX11_AMR, 0x4000a210 - 3224 .set CYDEV_CAN0_RX11_ACR, 0x4000a214 - 3225 .set CYDEV_CAN0_RX11_AMRD, 0x4000a218 - 3226 .set CYDEV_CAN0_RX11_ACRD, 0x4000a21c - 3227 .set CYDEV_CAN0_RX12_BASE, 0x4000a220 - 3228 .set CYDEV_CAN0_RX12_SIZE, 0x00000020 - 3229 .set CYDEV_CAN0_RX12_CMD, 0x4000a220 - 3230 .set CYDEV_CAN0_RX12_ID, 0x4000a224 - 3231 .set CYDEV_CAN0_RX12_DH, 0x4000a228 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 58 - - - 3232 .set CYDEV_CAN0_RX12_DL, 0x4000a22c - 3233 .set CYDEV_CAN0_RX12_AMR, 0x4000a230 - 3234 .set CYDEV_CAN0_RX12_ACR, 0x4000a234 - 3235 .set CYDEV_CAN0_RX12_AMRD, 0x4000a238 - 3236 .set CYDEV_CAN0_RX12_ACRD, 0x4000a23c - 3237 .set CYDEV_CAN0_RX13_BASE, 0x4000a240 - 3238 .set CYDEV_CAN0_RX13_SIZE, 0x00000020 - 3239 .set CYDEV_CAN0_RX13_CMD, 0x4000a240 - 3240 .set CYDEV_CAN0_RX13_ID, 0x4000a244 - 3241 .set CYDEV_CAN0_RX13_DH, 0x4000a248 - 3242 .set CYDEV_CAN0_RX13_DL, 0x4000a24c - 3243 .set CYDEV_CAN0_RX13_AMR, 0x4000a250 - 3244 .set CYDEV_CAN0_RX13_ACR, 0x4000a254 - 3245 .set CYDEV_CAN0_RX13_AMRD, 0x4000a258 - 3246 .set CYDEV_CAN0_RX13_ACRD, 0x4000a25c - 3247 .set CYDEV_CAN0_RX14_BASE, 0x4000a260 - 3248 .set CYDEV_CAN0_RX14_SIZE, 0x00000020 - 3249 .set CYDEV_CAN0_RX14_CMD, 0x4000a260 - 3250 .set CYDEV_CAN0_RX14_ID, 0x4000a264 - 3251 .set CYDEV_CAN0_RX14_DH, 0x4000a268 - 3252 .set CYDEV_CAN0_RX14_DL, 0x4000a26c - 3253 .set CYDEV_CAN0_RX14_AMR, 0x4000a270 - 3254 .set CYDEV_CAN0_RX14_ACR, 0x4000a274 - 3255 .set CYDEV_CAN0_RX14_AMRD, 0x4000a278 - 3256 .set CYDEV_CAN0_RX14_ACRD, 0x4000a27c - 3257 .set CYDEV_CAN0_RX15_BASE, 0x4000a280 - 3258 .set CYDEV_CAN0_RX15_SIZE, 0x00000020 - 3259 .set CYDEV_CAN0_RX15_CMD, 0x4000a280 - 3260 .set CYDEV_CAN0_RX15_ID, 0x4000a284 - 3261 .set CYDEV_CAN0_RX15_DH, 0x4000a288 - 3262 .set CYDEV_CAN0_RX15_DL, 0x4000a28c - 3263 .set CYDEV_CAN0_RX15_AMR, 0x4000a290 - 3264 .set CYDEV_CAN0_RX15_ACR, 0x4000a294 - 3265 .set CYDEV_CAN0_RX15_AMRD, 0x4000a298 - 3266 .set CYDEV_CAN0_RX15_ACRD, 0x4000a29c - 3267 .set CYDEV_DFB0_BASE, 0x4000c000 - 3268 .set CYDEV_DFB0_SIZE, 0x000007b5 - 3269 .set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 - 3270 .set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 - 3271 .set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 - 3272 .set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 - 3273 .set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 - 3274 .set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 - 3275 .set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 - 3276 .set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 - 3277 .set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 - 3278 .set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 - 3279 .set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 - 3280 .set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 - 3281 .set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 - 3282 .set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 - 3283 .set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 - 3284 .set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 - 3285 .set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 - 3286 .set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 - 3287 .set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 - 3288 .set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 59 - - - 3289 .set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 - 3290 .set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 - 3291 .set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 - 3292 .set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 - 3293 .set CYDEV_DFB0_CR, 0x4000c780 - 3294 .set CYDEV_DFB0_SR, 0x4000c784 - 3295 .set CYDEV_DFB0_RAM_EN, 0x4000c788 - 3296 .set CYDEV_DFB0_RAM_DIR, 0x4000c78c - 3297 .set CYDEV_DFB0_SEMA, 0x4000c790 - 3298 .set CYDEV_DFB0_DSI_CTRL, 0x4000c794 - 3299 .set CYDEV_DFB0_INT_CTRL, 0x4000c798 - 3300 .set CYDEV_DFB0_DMA_CTRL, 0x4000c79c - 3301 .set CYDEV_DFB0_STAGEA, 0x4000c7a0 - 3302 .set CYDEV_DFB0_STAGEAM, 0x4000c7a1 - 3303 .set CYDEV_DFB0_STAGEAH, 0x4000c7a2 - 3304 .set CYDEV_DFB0_STAGEB, 0x4000c7a4 - 3305 .set CYDEV_DFB0_STAGEBM, 0x4000c7a5 - 3306 .set CYDEV_DFB0_STAGEBH, 0x4000c7a6 - 3307 .set CYDEV_DFB0_HOLDA, 0x4000c7a8 - 3308 .set CYDEV_DFB0_HOLDAM, 0x4000c7a9 - 3309 .set CYDEV_DFB0_HOLDAH, 0x4000c7aa - 3310 .set CYDEV_DFB0_HOLDAS, 0x4000c7ab - 3311 .set CYDEV_DFB0_HOLDB, 0x4000c7ac - 3312 .set CYDEV_DFB0_HOLDBM, 0x4000c7ad - 3313 .set CYDEV_DFB0_HOLDBH, 0x4000c7ae - 3314 .set CYDEV_DFB0_HOLDBS, 0x4000c7af - 3315 .set CYDEV_DFB0_COHER, 0x4000c7b0 - 3316 .set CYDEV_DFB0_DALIGN, 0x4000c7b4 - 3317 .set CYDEV_UCFG_BASE, 0x40010000 - 3318 .set CYDEV_UCFG_SIZE, 0x00005040 - 3319 .set CYDEV_UCFG_B0_BASE, 0x40010000 - 3320 .set CYDEV_UCFG_B0_SIZE, 0x00000fef - 3321 .set CYDEV_UCFG_B0_P0_BASE, 0x40010000 - 3322 .set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef - 3323 .set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 - 3324 .set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 - 3325 .set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000 - 3326 .set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004 - 3327 .set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008 - 3328 .set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c - 3329 .set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010 - 3330 .set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014 - 3331 .set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018 - 3332 .set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c - 3333 .set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020 - 3334 .set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024 - 3335 .set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028 - 3336 .set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c - 3337 .set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030 - 3338 .set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032 - 3339 .set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034 - 3340 .set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036 - 3341 .set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 - 3342 .set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a - 3343 .set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c - 3344 .set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e - 3345 .set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 60 - - - 3346 .set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041 - 3347 .set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042 - 3348 .set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043 - 3349 .set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044 - 3350 .set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045 - 3351 .set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046 - 3352 .set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047 - 3353 .set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048 - 3354 .set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049 - 3355 .set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a - 3356 .set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b - 3357 .set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c - 3358 .set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d - 3359 .set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e - 3360 .set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f - 3361 .set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050 - 3362 .set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051 - 3363 .set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052 - 3364 .set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053 - 3365 .set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054 - 3366 .set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055 - 3367 .set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056 - 3368 .set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057 - 3369 .set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058 - 3370 .set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059 - 3371 .set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a - 3372 .set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b - 3373 .set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c - 3374 .set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d - 3375 .set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e - 3376 .set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f - 3377 .set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060 - 3378 .set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062 - 3379 .set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064 - 3380 .set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066 - 3381 .set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068 - 3382 .set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a - 3383 .set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c - 3384 .set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e - 3385 .set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 - 3386 .set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 - 3387 .set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080 - 3388 .set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084 - 3389 .set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088 - 3390 .set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c - 3391 .set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090 - 3392 .set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094 - 3393 .set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098 - 3394 .set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c - 3395 .set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0 - 3396 .set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4 - 3397 .set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8 - 3398 .set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac - 3399 .set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0 - 3400 .set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2 - 3401 .set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4 - 3402 .set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 61 - - - 3403 .set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 - 3404 .set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba - 3405 .set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc - 3406 .set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be - 3407 .set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0 - 3408 .set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1 - 3409 .set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2 - 3410 .set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3 - 3411 .set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4 - 3412 .set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5 - 3413 .set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6 - 3414 .set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7 - 3415 .set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8 - 3416 .set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9 - 3417 .set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca - 3418 .set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb - 3419 .set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc - 3420 .set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd - 3421 .set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce - 3422 .set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf - 3423 .set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0 - 3424 .set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1 - 3425 .set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2 - 3426 .set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3 - 3427 .set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4 - 3428 .set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5 - 3429 .set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6 - 3430 .set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7 - 3431 .set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8 - 3432 .set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9 - 3433 .set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da - 3434 .set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db - 3435 .set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc - 3436 .set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd - 3437 .set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de - 3438 .set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df - 3439 .set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0 - 3440 .set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2 - 3441 .set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4 - 3442 .set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6 - 3443 .set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8 - 3444 .set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea - 3445 .set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec - 3446 .set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee - 3447 .set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 - 3448 .set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef - 3449 .set CYDEV_UCFG_B0_P1_BASE, 0x40010200 - 3450 .set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef - 3451 .set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 - 3452 .set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 - 3453 .set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200 - 3454 .set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204 - 3455 .set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208 - 3456 .set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c - 3457 .set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210 - 3458 .set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214 - 3459 .set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 62 - - - 3460 .set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c - 3461 .set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220 - 3462 .set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224 - 3463 .set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228 - 3464 .set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c - 3465 .set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230 - 3466 .set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232 - 3467 .set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234 - 3468 .set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236 - 3469 .set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 - 3470 .set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a - 3471 .set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c - 3472 .set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e - 3473 .set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240 - 3474 .set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241 - 3475 .set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242 - 3476 .set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243 - 3477 .set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244 - 3478 .set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245 - 3479 .set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246 - 3480 .set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247 - 3481 .set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248 - 3482 .set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249 - 3483 .set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a - 3484 .set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b - 3485 .set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c - 3486 .set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d - 3487 .set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e - 3488 .set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f - 3489 .set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250 - 3490 .set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251 - 3491 .set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252 - 3492 .set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253 - 3493 .set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254 - 3494 .set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255 - 3495 .set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256 - 3496 .set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257 - 3497 .set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258 - 3498 .set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259 - 3499 .set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a - 3500 .set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b - 3501 .set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c - 3502 .set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d - 3503 .set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e - 3504 .set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f - 3505 .set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260 - 3506 .set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262 - 3507 .set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264 - 3508 .set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266 - 3509 .set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268 - 3510 .set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a - 3511 .set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c - 3512 .set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e - 3513 .set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 - 3514 .set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 - 3515 .set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280 - 3516 .set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 63 - - - 3517 .set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288 - 3518 .set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c - 3519 .set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290 - 3520 .set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294 - 3521 .set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298 - 3522 .set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c - 3523 .set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0 - 3524 .set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4 - 3525 .set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8 - 3526 .set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac - 3527 .set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0 - 3528 .set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2 - 3529 .set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4 - 3530 .set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6 - 3531 .set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 - 3532 .set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba - 3533 .set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc - 3534 .set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be - 3535 .set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0 - 3536 .set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1 - 3537 .set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2 - 3538 .set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3 - 3539 .set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4 - 3540 .set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5 - 3541 .set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6 - 3542 .set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7 - 3543 .set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8 - 3544 .set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9 - 3545 .set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca - 3546 .set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb - 3547 .set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc - 3548 .set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd - 3549 .set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce - 3550 .set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf - 3551 .set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0 - 3552 .set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1 - 3553 .set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2 - 3554 .set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3 - 3555 .set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4 - 3556 .set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5 - 3557 .set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6 - 3558 .set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7 - 3559 .set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8 - 3560 .set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9 - 3561 .set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da - 3562 .set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db - 3563 .set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc - 3564 .set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd - 3565 .set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de - 3566 .set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df - 3567 .set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0 - 3568 .set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2 - 3569 .set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4 - 3570 .set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6 - 3571 .set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8 - 3572 .set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea - 3573 .set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 64 - - - 3574 .set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee - 3575 .set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 - 3576 .set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef - 3577 .set CYDEV_UCFG_B0_P2_BASE, 0x40010400 - 3578 .set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef - 3579 .set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 - 3580 .set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 - 3581 .set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400 - 3582 .set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404 - 3583 .set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408 - 3584 .set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c - 3585 .set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410 - 3586 .set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414 - 3587 .set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418 - 3588 .set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c - 3589 .set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420 - 3590 .set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424 - 3591 .set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428 - 3592 .set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c - 3593 .set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430 - 3594 .set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432 - 3595 .set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434 - 3596 .set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436 - 3597 .set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 - 3598 .set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a - 3599 .set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c - 3600 .set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e - 3601 .set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440 - 3602 .set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441 - 3603 .set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442 - 3604 .set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443 - 3605 .set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444 - 3606 .set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445 - 3607 .set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446 - 3608 .set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447 - 3609 .set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448 - 3610 .set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449 - 3611 .set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a - 3612 .set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b - 3613 .set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c - 3614 .set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d - 3615 .set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e - 3616 .set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f - 3617 .set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450 - 3618 .set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451 - 3619 .set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452 - 3620 .set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453 - 3621 .set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454 - 3622 .set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455 - 3623 .set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456 - 3624 .set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457 - 3625 .set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458 - 3626 .set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459 - 3627 .set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a - 3628 .set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b - 3629 .set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c - 3630 .set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 65 - - - 3631 .set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e - 3632 .set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f - 3633 .set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460 - 3634 .set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462 - 3635 .set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464 - 3636 .set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466 - 3637 .set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468 - 3638 .set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a - 3639 .set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c - 3640 .set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e - 3641 .set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 - 3642 .set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 - 3643 .set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480 - 3644 .set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484 - 3645 .set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488 - 3646 .set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c - 3647 .set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490 - 3648 .set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494 - 3649 .set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498 - 3650 .set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c - 3651 .set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0 - 3652 .set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4 - 3653 .set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8 - 3654 .set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac - 3655 .set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0 - 3656 .set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2 - 3657 .set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4 - 3658 .set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6 - 3659 .set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 - 3660 .set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba - 3661 .set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc - 3662 .set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be - 3663 .set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0 - 3664 .set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1 - 3665 .set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2 - 3666 .set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3 - 3667 .set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4 - 3668 .set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5 - 3669 .set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6 - 3670 .set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7 - 3671 .set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8 - 3672 .set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9 - 3673 .set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca - 3674 .set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb - 3675 .set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc - 3676 .set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd - 3677 .set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce - 3678 .set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf - 3679 .set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0 - 3680 .set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1 - 3681 .set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2 - 3682 .set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3 - 3683 .set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4 - 3684 .set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5 - 3685 .set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6 - 3686 .set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7 - 3687 .set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 66 - - - 3688 .set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9 - 3689 .set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da - 3690 .set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db - 3691 .set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc - 3692 .set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd - 3693 .set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de - 3694 .set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df - 3695 .set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0 - 3696 .set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2 - 3697 .set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4 - 3698 .set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6 - 3699 .set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8 - 3700 .set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea - 3701 .set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec - 3702 .set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee - 3703 .set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 - 3704 .set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef - 3705 .set CYDEV_UCFG_B0_P3_BASE, 0x40010600 - 3706 .set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef - 3707 .set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 - 3708 .set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 - 3709 .set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600 - 3710 .set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604 - 3711 .set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608 - 3712 .set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c - 3713 .set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610 - 3714 .set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614 - 3715 .set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618 - 3716 .set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c - 3717 .set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620 - 3718 .set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624 - 3719 .set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628 - 3720 .set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c - 3721 .set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630 - 3722 .set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632 - 3723 .set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634 - 3724 .set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636 - 3725 .set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 - 3726 .set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a - 3727 .set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c - 3728 .set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e - 3729 .set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640 - 3730 .set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641 - 3731 .set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642 - 3732 .set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643 - 3733 .set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644 - 3734 .set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645 - 3735 .set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646 - 3736 .set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647 - 3737 .set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648 - 3738 .set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649 - 3739 .set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a - 3740 .set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b - 3741 .set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c - 3742 .set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d - 3743 .set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e - 3744 .set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 67 - - - 3745 .set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650 - 3746 .set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651 - 3747 .set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652 - 3748 .set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653 - 3749 .set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654 - 3750 .set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655 - 3751 .set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656 - 3752 .set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657 - 3753 .set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658 - 3754 .set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659 - 3755 .set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a - 3756 .set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b - 3757 .set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c - 3758 .set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d - 3759 .set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e - 3760 .set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f - 3761 .set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660 - 3762 .set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662 - 3763 .set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664 - 3764 .set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666 - 3765 .set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668 - 3766 .set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a - 3767 .set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c - 3768 .set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e - 3769 .set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 - 3770 .set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 - 3771 .set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680 - 3772 .set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684 - 3773 .set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688 - 3774 .set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c - 3775 .set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690 - 3776 .set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694 - 3777 .set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698 - 3778 .set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c - 3779 .set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0 - 3780 .set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4 - 3781 .set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8 - 3782 .set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac - 3783 .set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0 - 3784 .set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2 - 3785 .set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4 - 3786 .set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6 - 3787 .set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 - 3788 .set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba - 3789 .set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc - 3790 .set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be - 3791 .set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0 - 3792 .set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1 - 3793 .set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2 - 3794 .set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3 - 3795 .set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4 - 3796 .set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5 - 3797 .set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6 - 3798 .set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7 - 3799 .set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8 - 3800 .set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9 - 3801 .set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 68 - - - 3802 .set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb - 3803 .set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc - 3804 .set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd - 3805 .set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce - 3806 .set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf - 3807 .set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0 - 3808 .set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1 - 3809 .set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2 - 3810 .set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3 - 3811 .set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4 - 3812 .set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5 - 3813 .set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6 - 3814 .set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7 - 3815 .set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8 - 3816 .set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9 - 3817 .set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da - 3818 .set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db - 3819 .set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc - 3820 .set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd - 3821 .set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de - 3822 .set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df - 3823 .set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0 - 3824 .set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2 - 3825 .set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4 - 3826 .set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6 - 3827 .set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8 - 3828 .set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea - 3829 .set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec - 3830 .set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee - 3831 .set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 - 3832 .set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef - 3833 .set CYDEV_UCFG_B0_P4_BASE, 0x40010800 - 3834 .set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef - 3835 .set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 - 3836 .set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 - 3837 .set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800 - 3838 .set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804 - 3839 .set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808 - 3840 .set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c - 3841 .set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810 - 3842 .set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814 - 3843 .set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818 - 3844 .set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c - 3845 .set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820 - 3846 .set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824 - 3847 .set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828 - 3848 .set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c - 3849 .set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830 - 3850 .set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832 - 3851 .set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834 - 3852 .set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836 - 3853 .set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 - 3854 .set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a - 3855 .set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c - 3856 .set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e - 3857 .set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840 - 3858 .set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 69 - - - 3859 .set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842 - 3860 .set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843 - 3861 .set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844 - 3862 .set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845 - 3863 .set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846 - 3864 .set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847 - 3865 .set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848 - 3866 .set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849 - 3867 .set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a - 3868 .set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b - 3869 .set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c - 3870 .set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d - 3871 .set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e - 3872 .set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f - 3873 .set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850 - 3874 .set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851 - 3875 .set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852 - 3876 .set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853 - 3877 .set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854 - 3878 .set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855 - 3879 .set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856 - 3880 .set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857 - 3881 .set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858 - 3882 .set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859 - 3883 .set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a - 3884 .set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b - 3885 .set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c - 3886 .set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d - 3887 .set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e - 3888 .set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f - 3889 .set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860 - 3890 .set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862 - 3891 .set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864 - 3892 .set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866 - 3893 .set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868 - 3894 .set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a - 3895 .set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c - 3896 .set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e - 3897 .set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 - 3898 .set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 - 3899 .set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880 - 3900 .set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884 - 3901 .set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888 - 3902 .set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c - 3903 .set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890 - 3904 .set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894 - 3905 .set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898 - 3906 .set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c - 3907 .set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0 - 3908 .set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4 - 3909 .set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8 - 3910 .set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac - 3911 .set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0 - 3912 .set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2 - 3913 .set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4 - 3914 .set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6 - 3915 .set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 70 - - - 3916 .set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba - 3917 .set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc - 3918 .set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be - 3919 .set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0 - 3920 .set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1 - 3921 .set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2 - 3922 .set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3 - 3923 .set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4 - 3924 .set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5 - 3925 .set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6 - 3926 .set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7 - 3927 .set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8 - 3928 .set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9 - 3929 .set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca - 3930 .set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb - 3931 .set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc - 3932 .set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd - 3933 .set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce - 3934 .set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf - 3935 .set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0 - 3936 .set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1 - 3937 .set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2 - 3938 .set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3 - 3939 .set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4 - 3940 .set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5 - 3941 .set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6 - 3942 .set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7 - 3943 .set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8 - 3944 .set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9 - 3945 .set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da - 3946 .set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db - 3947 .set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc - 3948 .set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd - 3949 .set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de - 3950 .set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df - 3951 .set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0 - 3952 .set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2 - 3953 .set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4 - 3954 .set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6 - 3955 .set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8 - 3956 .set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea - 3957 .set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec - 3958 .set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee - 3959 .set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 - 3960 .set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef - 3961 .set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 - 3962 .set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef - 3963 .set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 - 3964 .set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 - 3965 .set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00 - 3966 .set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04 - 3967 .set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08 - 3968 .set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c - 3969 .set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10 - 3970 .set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14 - 3971 .set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18 - 3972 .set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 71 - - - 3973 .set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20 - 3974 .set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24 - 3975 .set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28 - 3976 .set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c - 3977 .set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30 - 3978 .set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32 - 3979 .set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34 - 3980 .set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36 - 3981 .set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 - 3982 .set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a - 3983 .set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c - 3984 .set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e - 3985 .set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40 - 3986 .set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41 - 3987 .set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42 - 3988 .set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43 - 3989 .set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44 - 3990 .set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45 - 3991 .set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46 - 3992 .set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47 - 3993 .set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48 - 3994 .set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49 - 3995 .set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a - 3996 .set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b - 3997 .set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c - 3998 .set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d - 3999 .set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e - 4000 .set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f - 4001 .set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50 - 4002 .set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51 - 4003 .set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52 - 4004 .set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53 - 4005 .set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54 - 4006 .set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55 - 4007 .set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56 - 4008 .set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57 - 4009 .set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58 - 4010 .set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59 - 4011 .set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a - 4012 .set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b - 4013 .set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c - 4014 .set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d - 4015 .set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e - 4016 .set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f - 4017 .set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60 - 4018 .set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62 - 4019 .set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64 - 4020 .set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66 - 4021 .set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68 - 4022 .set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a - 4023 .set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c - 4024 .set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e - 4025 .set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 - 4026 .set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 - 4027 .set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80 - 4028 .set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84 - 4029 .set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 72 - - - 4030 .set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c - 4031 .set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90 - 4032 .set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94 - 4033 .set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98 - 4034 .set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c - 4035 .set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0 - 4036 .set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4 - 4037 .set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8 - 4038 .set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac - 4039 .set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0 - 4040 .set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2 - 4041 .set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4 - 4042 .set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6 - 4043 .set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 - 4044 .set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba - 4045 .set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc - 4046 .set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe - 4047 .set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0 - 4048 .set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1 - 4049 .set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2 - 4050 .set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3 - 4051 .set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4 - 4052 .set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5 - 4053 .set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6 - 4054 .set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7 - 4055 .set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8 - 4056 .set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9 - 4057 .set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca - 4058 .set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb - 4059 .set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc - 4060 .set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd - 4061 .set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace - 4062 .set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf - 4063 .set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0 - 4064 .set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1 - 4065 .set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2 - 4066 .set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3 - 4067 .set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4 - 4068 .set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5 - 4069 .set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6 - 4070 .set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7 - 4071 .set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8 - 4072 .set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9 - 4073 .set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada - 4074 .set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb - 4075 .set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc - 4076 .set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add - 4077 .set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade - 4078 .set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf - 4079 .set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0 - 4080 .set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2 - 4081 .set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4 - 4082 .set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6 - 4083 .set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8 - 4084 .set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea - 4085 .set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec - 4086 .set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 73 - - - 4087 .set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 - 4088 .set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef - 4089 .set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 - 4090 .set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef - 4091 .set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 - 4092 .set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 - 4093 .set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00 - 4094 .set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04 - 4095 .set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08 - 4096 .set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c - 4097 .set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10 - 4098 .set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14 - 4099 .set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18 - 4100 .set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c - 4101 .set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20 - 4102 .set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24 - 4103 .set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28 - 4104 .set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c - 4105 .set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30 - 4106 .set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32 - 4107 .set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34 - 4108 .set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36 - 4109 .set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 - 4110 .set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a - 4111 .set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c - 4112 .set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e - 4113 .set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40 - 4114 .set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41 - 4115 .set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42 - 4116 .set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43 - 4117 .set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44 - 4118 .set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45 - 4119 .set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46 - 4120 .set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47 - 4121 .set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48 - 4122 .set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49 - 4123 .set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a - 4124 .set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b - 4125 .set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c - 4126 .set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d - 4127 .set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e - 4128 .set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f - 4129 .set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50 - 4130 .set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51 - 4131 .set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52 - 4132 .set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53 - 4133 .set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54 - 4134 .set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55 - 4135 .set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56 - 4136 .set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57 - 4137 .set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58 - 4138 .set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59 - 4139 .set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a - 4140 .set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b - 4141 .set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c - 4142 .set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d - 4143 .set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 74 - - - 4144 .set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f - 4145 .set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60 - 4146 .set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62 - 4147 .set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64 - 4148 .set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66 - 4149 .set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68 - 4150 .set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a - 4151 .set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c - 4152 .set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e - 4153 .set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 - 4154 .set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 - 4155 .set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80 - 4156 .set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84 - 4157 .set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88 - 4158 .set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c - 4159 .set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90 - 4160 .set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94 - 4161 .set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98 - 4162 .set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c - 4163 .set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0 - 4164 .set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4 - 4165 .set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8 - 4166 .set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac - 4167 .set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0 - 4168 .set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2 - 4169 .set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4 - 4170 .set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6 - 4171 .set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 - 4172 .set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba - 4173 .set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc - 4174 .set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe - 4175 .set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0 - 4176 .set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1 - 4177 .set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2 - 4178 .set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3 - 4179 .set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4 - 4180 .set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5 - 4181 .set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6 - 4182 .set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7 - 4183 .set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8 - 4184 .set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9 - 4185 .set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca - 4186 .set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb - 4187 .set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc - 4188 .set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd - 4189 .set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce - 4190 .set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf - 4191 .set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0 - 4192 .set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1 - 4193 .set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2 - 4194 .set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3 - 4195 .set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4 - 4196 .set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5 - 4197 .set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6 - 4198 .set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7 - 4199 .set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8 - 4200 .set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 75 - - - 4201 .set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda - 4202 .set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb - 4203 .set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc - 4204 .set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd - 4205 .set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde - 4206 .set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf - 4207 .set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0 - 4208 .set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2 - 4209 .set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4 - 4210 .set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6 - 4211 .set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8 - 4212 .set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea - 4213 .set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec - 4214 .set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee - 4215 .set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 - 4216 .set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef - 4217 .set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 - 4218 .set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef - 4219 .set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 - 4220 .set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 - 4221 .set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00 - 4222 .set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04 - 4223 .set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08 - 4224 .set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c - 4225 .set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10 - 4226 .set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14 - 4227 .set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18 - 4228 .set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c - 4229 .set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20 - 4230 .set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24 - 4231 .set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28 - 4232 .set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c - 4233 .set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30 - 4234 .set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32 - 4235 .set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34 - 4236 .set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36 - 4237 .set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 - 4238 .set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a - 4239 .set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c - 4240 .set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e - 4241 .set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40 - 4242 .set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41 - 4243 .set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42 - 4244 .set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43 - 4245 .set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44 - 4246 .set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45 - 4247 .set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46 - 4248 .set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47 - 4249 .set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48 - 4250 .set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49 - 4251 .set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a - 4252 .set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b - 4253 .set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c - 4254 .set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d - 4255 .set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e - 4256 .set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f - 4257 .set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 76 - - - 4258 .set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51 - 4259 .set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52 - 4260 .set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53 - 4261 .set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54 - 4262 .set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55 - 4263 .set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56 - 4264 .set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57 - 4265 .set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58 - 4266 .set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59 - 4267 .set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a - 4268 .set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b - 4269 .set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c - 4270 .set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d - 4271 .set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e - 4272 .set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f - 4273 .set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60 - 4274 .set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62 - 4275 .set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64 - 4276 .set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66 - 4277 .set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68 - 4278 .set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a - 4279 .set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c - 4280 .set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e - 4281 .set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 - 4282 .set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 - 4283 .set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80 - 4284 .set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84 - 4285 .set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88 - 4286 .set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c - 4287 .set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90 - 4288 .set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94 - 4289 .set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98 - 4290 .set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c - 4291 .set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0 - 4292 .set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4 - 4293 .set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8 - 4294 .set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac - 4295 .set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0 - 4296 .set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2 - 4297 .set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4 - 4298 .set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6 - 4299 .set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 - 4300 .set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba - 4301 .set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc - 4302 .set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe - 4303 .set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0 - 4304 .set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1 - 4305 .set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2 - 4306 .set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3 - 4307 .set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4 - 4308 .set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5 - 4309 .set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6 - 4310 .set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7 - 4311 .set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8 - 4312 .set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9 - 4313 .set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca - 4314 .set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 77 - - - 4315 .set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc - 4316 .set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd - 4317 .set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece - 4318 .set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf - 4319 .set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0 - 4320 .set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1 - 4321 .set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2 - 4322 .set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3 - 4323 .set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4 - 4324 .set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5 - 4325 .set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6 - 4326 .set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7 - 4327 .set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8 - 4328 .set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9 - 4329 .set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda - 4330 .set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb - 4331 .set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc - 4332 .set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd - 4333 .set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede - 4334 .set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf - 4335 .set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0 - 4336 .set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2 - 4337 .set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4 - 4338 .set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6 - 4339 .set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8 - 4340 .set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea - 4341 .set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec - 4342 .set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee - 4343 .set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 - 4344 .set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef - 4345 .set CYDEV_UCFG_B1_BASE, 0x40011000 - 4346 .set CYDEV_UCFG_B1_SIZE, 0x00000fef - 4347 .set CYDEV_UCFG_B1_P2_BASE, 0x40011400 - 4348 .set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef - 4349 .set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 - 4350 .set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 - 4351 .set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400 - 4352 .set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404 - 4353 .set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408 - 4354 .set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c - 4355 .set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410 - 4356 .set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414 - 4357 .set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418 - 4358 .set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c - 4359 .set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420 - 4360 .set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424 - 4361 .set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428 - 4362 .set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c - 4363 .set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430 - 4364 .set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432 - 4365 .set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434 - 4366 .set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436 - 4367 .set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 - 4368 .set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a - 4369 .set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c - 4370 .set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e - 4371 .set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 78 - - - 4372 .set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441 - 4373 .set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442 - 4374 .set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443 - 4375 .set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444 - 4376 .set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445 - 4377 .set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446 - 4378 .set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447 - 4379 .set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448 - 4380 .set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449 - 4381 .set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a - 4382 .set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b - 4383 .set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c - 4384 .set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d - 4385 .set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e - 4386 .set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f - 4387 .set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450 - 4388 .set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451 - 4389 .set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452 - 4390 .set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453 - 4391 .set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454 - 4392 .set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455 - 4393 .set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456 - 4394 .set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457 - 4395 .set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458 - 4396 .set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459 - 4397 .set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a - 4398 .set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b - 4399 .set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c - 4400 .set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d - 4401 .set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e - 4402 .set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f - 4403 .set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460 - 4404 .set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462 - 4405 .set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464 - 4406 .set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466 - 4407 .set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468 - 4408 .set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a - 4409 .set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c - 4410 .set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e - 4411 .set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 - 4412 .set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 - 4413 .set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480 - 4414 .set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484 - 4415 .set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488 - 4416 .set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c - 4417 .set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490 - 4418 .set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494 - 4419 .set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498 - 4420 .set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c - 4421 .set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0 - 4422 .set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4 - 4423 .set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8 - 4424 .set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac - 4425 .set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0 - 4426 .set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2 - 4427 .set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4 - 4428 .set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 79 - - - 4429 .set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 - 4430 .set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba - 4431 .set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc - 4432 .set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be - 4433 .set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0 - 4434 .set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1 - 4435 .set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2 - 4436 .set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3 - 4437 .set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4 - 4438 .set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5 - 4439 .set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6 - 4440 .set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7 - 4441 .set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8 - 4442 .set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9 - 4443 .set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca - 4444 .set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb - 4445 .set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc - 4446 .set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd - 4447 .set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce - 4448 .set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf - 4449 .set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0 - 4450 .set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1 - 4451 .set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2 - 4452 .set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3 - 4453 .set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4 - 4454 .set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5 - 4455 .set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6 - 4456 .set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7 - 4457 .set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8 - 4458 .set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9 - 4459 .set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da - 4460 .set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db - 4461 .set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc - 4462 .set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd - 4463 .set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de - 4464 .set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df - 4465 .set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0 - 4466 .set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2 - 4467 .set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4 - 4468 .set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6 - 4469 .set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8 - 4470 .set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea - 4471 .set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec - 4472 .set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee - 4473 .set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 - 4474 .set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef - 4475 .set CYDEV_UCFG_B1_P3_BASE, 0x40011600 - 4476 .set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef - 4477 .set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 - 4478 .set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 - 4479 .set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600 - 4480 .set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604 - 4481 .set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608 - 4482 .set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c - 4483 .set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610 - 4484 .set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614 - 4485 .set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 80 - - - 4486 .set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c - 4487 .set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620 - 4488 .set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624 - 4489 .set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628 - 4490 .set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c - 4491 .set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630 - 4492 .set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632 - 4493 .set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634 - 4494 .set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636 - 4495 .set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 - 4496 .set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a - 4497 .set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c - 4498 .set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e - 4499 .set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640 - 4500 .set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641 - 4501 .set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642 - 4502 .set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643 - 4503 .set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644 - 4504 .set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645 - 4505 .set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646 - 4506 .set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647 - 4507 .set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648 - 4508 .set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649 - 4509 .set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a - 4510 .set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b - 4511 .set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c - 4512 .set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d - 4513 .set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e - 4514 .set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f - 4515 .set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650 - 4516 .set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651 - 4517 .set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652 - 4518 .set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653 - 4519 .set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654 - 4520 .set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655 - 4521 .set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656 - 4522 .set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657 - 4523 .set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658 - 4524 .set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659 - 4525 .set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a - 4526 .set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b - 4527 .set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c - 4528 .set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d - 4529 .set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e - 4530 .set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f - 4531 .set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660 - 4532 .set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662 - 4533 .set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664 - 4534 .set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666 - 4535 .set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668 - 4536 .set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a - 4537 .set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c - 4538 .set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e - 4539 .set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 - 4540 .set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 - 4541 .set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680 - 4542 .set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 81 - - - 4543 .set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688 - 4544 .set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c - 4545 .set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690 - 4546 .set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694 - 4547 .set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698 - 4548 .set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c - 4549 .set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0 - 4550 .set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4 - 4551 .set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8 - 4552 .set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac - 4553 .set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0 - 4554 .set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2 - 4555 .set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4 - 4556 .set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6 - 4557 .set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 - 4558 .set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba - 4559 .set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc - 4560 .set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be - 4561 .set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0 - 4562 .set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1 - 4563 .set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2 - 4564 .set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3 - 4565 .set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4 - 4566 .set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5 - 4567 .set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6 - 4568 .set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7 - 4569 .set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8 - 4570 .set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9 - 4571 .set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca - 4572 .set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb - 4573 .set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc - 4574 .set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd - 4575 .set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce - 4576 .set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf - 4577 .set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0 - 4578 .set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1 - 4579 .set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2 - 4580 .set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3 - 4581 .set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4 - 4582 .set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5 - 4583 .set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6 - 4584 .set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7 - 4585 .set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8 - 4586 .set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9 - 4587 .set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da - 4588 .set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db - 4589 .set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc - 4590 .set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd - 4591 .set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de - 4592 .set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df - 4593 .set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0 - 4594 .set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2 - 4595 .set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4 - 4596 .set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6 - 4597 .set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8 - 4598 .set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea - 4599 .set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 82 - - - 4600 .set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee - 4601 .set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 - 4602 .set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef - 4603 .set CYDEV_UCFG_B1_P4_BASE, 0x40011800 - 4604 .set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef - 4605 .set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 - 4606 .set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 - 4607 .set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800 - 4608 .set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804 - 4609 .set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808 - 4610 .set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c - 4611 .set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810 - 4612 .set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814 - 4613 .set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818 - 4614 .set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c - 4615 .set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820 - 4616 .set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824 - 4617 .set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828 - 4618 .set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c - 4619 .set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830 - 4620 .set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832 - 4621 .set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834 - 4622 .set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836 - 4623 .set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 - 4624 .set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a - 4625 .set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c - 4626 .set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e - 4627 .set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840 - 4628 .set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841 - 4629 .set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842 - 4630 .set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843 - 4631 .set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844 - 4632 .set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845 - 4633 .set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846 - 4634 .set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847 - 4635 .set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848 - 4636 .set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849 - 4637 .set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a - 4638 .set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b - 4639 .set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c - 4640 .set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d - 4641 .set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e - 4642 .set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f - 4643 .set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850 - 4644 .set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851 - 4645 .set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852 - 4646 .set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853 - 4647 .set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854 - 4648 .set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855 - 4649 .set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856 - 4650 .set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857 - 4651 .set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858 - 4652 .set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859 - 4653 .set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a - 4654 .set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b - 4655 .set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c - 4656 .set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 83 - - - 4657 .set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e - 4658 .set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f - 4659 .set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860 - 4660 .set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862 - 4661 .set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864 - 4662 .set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866 - 4663 .set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868 - 4664 .set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a - 4665 .set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c - 4666 .set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e - 4667 .set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 - 4668 .set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 - 4669 .set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880 - 4670 .set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884 - 4671 .set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888 - 4672 .set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c - 4673 .set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890 - 4674 .set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894 - 4675 .set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898 - 4676 .set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c - 4677 .set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0 - 4678 .set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4 - 4679 .set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8 - 4680 .set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac - 4681 .set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0 - 4682 .set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2 - 4683 .set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4 - 4684 .set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6 - 4685 .set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 - 4686 .set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba - 4687 .set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc - 4688 .set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be - 4689 .set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0 - 4690 .set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1 - 4691 .set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2 - 4692 .set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3 - 4693 .set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4 - 4694 .set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5 - 4695 .set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6 - 4696 .set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7 - 4697 .set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8 - 4698 .set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9 - 4699 .set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca - 4700 .set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb - 4701 .set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc - 4702 .set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd - 4703 .set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce - 4704 .set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf - 4705 .set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0 - 4706 .set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1 - 4707 .set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2 - 4708 .set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3 - 4709 .set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4 - 4710 .set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5 - 4711 .set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6 - 4712 .set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7 - 4713 .set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 84 - - - 4714 .set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9 - 4715 .set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da - 4716 .set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db - 4717 .set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc - 4718 .set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd - 4719 .set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de - 4720 .set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df - 4721 .set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0 - 4722 .set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2 - 4723 .set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4 - 4724 .set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6 - 4725 .set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8 - 4726 .set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea - 4727 .set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec - 4728 .set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee - 4729 .set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 - 4730 .set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef - 4731 .set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 - 4732 .set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef - 4733 .set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 - 4734 .set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 - 4735 .set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00 - 4736 .set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04 - 4737 .set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08 - 4738 .set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c - 4739 .set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10 - 4740 .set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14 - 4741 .set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18 - 4742 .set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c - 4743 .set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20 - 4744 .set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24 - 4745 .set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28 - 4746 .set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c - 4747 .set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30 - 4748 .set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32 - 4749 .set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34 - 4750 .set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36 - 4751 .set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 - 4752 .set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a - 4753 .set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c - 4754 .set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e - 4755 .set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40 - 4756 .set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41 - 4757 .set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42 - 4758 .set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43 - 4759 .set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44 - 4760 .set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45 - 4761 .set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46 - 4762 .set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47 - 4763 .set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48 - 4764 .set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49 - 4765 .set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a - 4766 .set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b - 4767 .set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c - 4768 .set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d - 4769 .set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e - 4770 .set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 85 - - - 4771 .set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50 - 4772 .set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51 - 4773 .set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52 - 4774 .set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53 - 4775 .set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54 - 4776 .set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55 - 4777 .set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56 - 4778 .set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57 - 4779 .set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58 - 4780 .set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59 - 4781 .set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a - 4782 .set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b - 4783 .set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c - 4784 .set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d - 4785 .set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e - 4786 .set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f - 4787 .set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60 - 4788 .set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62 - 4789 .set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64 - 4790 .set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66 - 4791 .set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68 - 4792 .set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a - 4793 .set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c - 4794 .set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e - 4795 .set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 - 4796 .set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 - 4797 .set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80 - 4798 .set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84 - 4799 .set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88 - 4800 .set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c - 4801 .set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90 - 4802 .set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94 - 4803 .set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98 - 4804 .set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c - 4805 .set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0 - 4806 .set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4 - 4807 .set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8 - 4808 .set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac - 4809 .set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0 - 4810 .set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2 - 4811 .set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4 - 4812 .set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6 - 4813 .set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 - 4814 .set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba - 4815 .set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc - 4816 .set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe - 4817 .set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0 - 4818 .set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1 - 4819 .set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2 - 4820 .set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3 - 4821 .set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4 - 4822 .set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5 - 4823 .set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6 - 4824 .set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7 - 4825 .set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8 - 4826 .set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9 - 4827 .set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 86 - - - 4828 .set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb - 4829 .set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc - 4830 .set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd - 4831 .set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace - 4832 .set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf - 4833 .set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0 - 4834 .set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1 - 4835 .set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2 - 4836 .set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3 - 4837 .set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4 - 4838 .set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5 - 4839 .set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6 - 4840 .set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7 - 4841 .set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8 - 4842 .set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9 - 4843 .set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada - 4844 .set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb - 4845 .set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc - 4846 .set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add - 4847 .set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade - 4848 .set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf - 4849 .set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0 - 4850 .set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2 - 4851 .set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4 - 4852 .set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6 - 4853 .set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8 - 4854 .set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea - 4855 .set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec - 4856 .set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee - 4857 .set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 - 4858 .set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef - 4859 .set CYDEV_UCFG_DSI0_BASE, 0x40014000 - 4860 .set CYDEV_UCFG_DSI0_SIZE, 0x000000ef - 4861 .set CYDEV_UCFG_DSI1_BASE, 0x40014100 - 4862 .set CYDEV_UCFG_DSI1_SIZE, 0x000000ef - 4863 .set CYDEV_UCFG_DSI2_BASE, 0x40014200 - 4864 .set CYDEV_UCFG_DSI2_SIZE, 0x000000ef - 4865 .set CYDEV_UCFG_DSI3_BASE, 0x40014300 - 4866 .set CYDEV_UCFG_DSI3_SIZE, 0x000000ef - 4867 .set CYDEV_UCFG_DSI4_BASE, 0x40014400 - 4868 .set CYDEV_UCFG_DSI4_SIZE, 0x000000ef - 4869 .set CYDEV_UCFG_DSI5_BASE, 0x40014500 - 4870 .set CYDEV_UCFG_DSI5_SIZE, 0x000000ef - 4871 .set CYDEV_UCFG_DSI6_BASE, 0x40014600 - 4872 .set CYDEV_UCFG_DSI6_SIZE, 0x000000ef - 4873 .set CYDEV_UCFG_DSI7_BASE, 0x40014700 - 4874 .set CYDEV_UCFG_DSI7_SIZE, 0x000000ef - 4875 .set CYDEV_UCFG_DSI8_BASE, 0x40014800 - 4876 .set CYDEV_UCFG_DSI8_SIZE, 0x000000ef - 4877 .set CYDEV_UCFG_DSI9_BASE, 0x40014900 - 4878 .set CYDEV_UCFG_DSI9_SIZE, 0x000000ef - 4879 .set CYDEV_UCFG_DSI12_BASE, 0x40014c00 - 4880 .set CYDEV_UCFG_DSI12_SIZE, 0x000000ef - 4881 .set CYDEV_UCFG_DSI13_BASE, 0x40014d00 - 4882 .set CYDEV_UCFG_DSI13_SIZE, 0x000000ef - 4883 .set CYDEV_UCFG_BCTL0_BASE, 0x40015000 - 4884 .set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 87 - - - 4885 .set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000 - 4886 .set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001 - 4887 .set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002 - 4888 .set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003 - 4889 .set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007 - 4890 .set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008 - 4891 .set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009 - 4892 .set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a - 4893 .set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b - 4894 .set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c - 4895 .set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d - 4896 .set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e - 4897 .set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f - 4898 .set CYDEV_UCFG_BCTL1_BASE, 0x40015010 - 4899 .set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 - 4900 .set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010 - 4901 .set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011 - 4902 .set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012 - 4903 .set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013 - 4904 .set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017 - 4905 .set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018 - 4906 .set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019 - 4907 .set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a - 4908 .set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b - 4909 .set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c - 4910 .set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d - 4911 .set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e - 4912 .set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f - 4913 .set CYDEV_IDMUX_BASE, 0x40015100 - 4914 .set CYDEV_IDMUX_SIZE, 0x00000016 - 4915 .set CYDEV_IDMUX_IRQ_CTL0, 0x40015100 - 4916 .set CYDEV_IDMUX_IRQ_CTL1, 0x40015101 - 4917 .set CYDEV_IDMUX_IRQ_CTL2, 0x40015102 - 4918 .set CYDEV_IDMUX_IRQ_CTL3, 0x40015103 - 4919 .set CYDEV_IDMUX_IRQ_CTL4, 0x40015104 - 4920 .set CYDEV_IDMUX_IRQ_CTL5, 0x40015105 - 4921 .set CYDEV_IDMUX_IRQ_CTL6, 0x40015106 - 4922 .set CYDEV_IDMUX_IRQ_CTL7, 0x40015107 - 4923 .set CYDEV_IDMUX_DRQ_CTL0, 0x40015110 - 4924 .set CYDEV_IDMUX_DRQ_CTL1, 0x40015111 - 4925 .set CYDEV_IDMUX_DRQ_CTL2, 0x40015112 - 4926 .set CYDEV_IDMUX_DRQ_CTL3, 0x40015113 - 4927 .set CYDEV_IDMUX_DRQ_CTL4, 0x40015114 - 4928 .set CYDEV_IDMUX_DRQ_CTL5, 0x40015115 - 4929 .set CYDEV_CACHERAM_BASE, 0x40030000 - 4930 .set CYDEV_CACHERAM_SIZE, 0x00000400 - 4931 .set CYDEV_CACHERAM_DATA_MBASE, 0x40030000 - 4932 .set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400 - 4933 .set CYDEV_SFR_BASE, 0x40050100 - 4934 .set CYDEV_SFR_SIZE, 0x000000fb - 4935 .set CYDEV_SFR_GPIO0, 0x40050180 - 4936 .set CYDEV_SFR_GPIRD0, 0x40050189 - 4937 .set CYDEV_SFR_GPIO0_SEL, 0x4005018a - 4938 .set CYDEV_SFR_GPIO1, 0x40050190 - 4939 .set CYDEV_SFR_GPIRD1, 0x40050191 - 4940 .set CYDEV_SFR_GPIO2, 0x40050198 - 4941 .set CYDEV_SFR_GPIRD2, 0x40050199 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 88 - - - 4942 .set CYDEV_SFR_GPIO2_SEL, 0x4005019a - 4943 .set CYDEV_SFR_GPIO1_SEL, 0x400501a2 - 4944 .set CYDEV_SFR_GPIO3, 0x400501b0 - 4945 .set CYDEV_SFR_GPIRD3, 0x400501b1 - 4946 .set CYDEV_SFR_GPIO3_SEL, 0x400501b2 - 4947 .set CYDEV_SFR_GPIO4, 0x400501c0 - 4948 .set CYDEV_SFR_GPIRD4, 0x400501c1 - 4949 .set CYDEV_SFR_GPIO4_SEL, 0x400501c2 - 4950 .set CYDEV_SFR_GPIO5, 0x400501c8 - 4951 .set CYDEV_SFR_GPIRD5, 0x400501c9 - 4952 .set CYDEV_SFR_GPIO5_SEL, 0x400501ca - 4953 .set CYDEV_SFR_GPIO6, 0x400501d8 - 4954 .set CYDEV_SFR_GPIRD6, 0x400501d9 - 4955 .set CYDEV_SFR_GPIO6_SEL, 0x400501da - 4956 .set CYDEV_SFR_GPIO12, 0x400501e8 - 4957 .set CYDEV_SFR_GPIRD12, 0x400501e9 - 4958 .set CYDEV_SFR_GPIO12_SEL, 0x400501f2 - 4959 .set CYDEV_SFR_GPIO15, 0x400501f8 - 4960 .set CYDEV_SFR_GPIRD15, 0x400501f9 - 4961 .set CYDEV_SFR_GPIO15_SEL, 0x400501fa - 4962 .set CYDEV_P3BA_BASE, 0x40050300 - 4963 .set CYDEV_P3BA_SIZE, 0x0000002b - 4964 .set CYDEV_P3BA_Y_START, 0x40050300 - 4965 .set CYDEV_P3BA_YROLL, 0x40050301 - 4966 .set CYDEV_P3BA_YCFG, 0x40050302 - 4967 .set CYDEV_P3BA_X_START1, 0x40050303 - 4968 .set CYDEV_P3BA_X_START2, 0x40050304 - 4969 .set CYDEV_P3BA_XROLL1, 0x40050305 - 4970 .set CYDEV_P3BA_XROLL2, 0x40050306 - 4971 .set CYDEV_P3BA_XINC, 0x40050307 - 4972 .set CYDEV_P3BA_XCFG, 0x40050308 - 4973 .set CYDEV_P3BA_OFFSETADDR1, 0x40050309 - 4974 .set CYDEV_P3BA_OFFSETADDR2, 0x4005030a - 4975 .set CYDEV_P3BA_OFFSETADDR3, 0x4005030b - 4976 .set CYDEV_P3BA_ABSADDR1, 0x4005030c - 4977 .set CYDEV_P3BA_ABSADDR2, 0x4005030d - 4978 .set CYDEV_P3BA_ABSADDR3, 0x4005030e - 4979 .set CYDEV_P3BA_ABSADDR4, 0x4005030f - 4980 .set CYDEV_P3BA_DATCFG1, 0x40050310 - 4981 .set CYDEV_P3BA_DATCFG2, 0x40050311 - 4982 .set CYDEV_P3BA_CMP_RSLT1, 0x40050314 - 4983 .set CYDEV_P3BA_CMP_RSLT2, 0x40050315 - 4984 .set CYDEV_P3BA_CMP_RSLT3, 0x40050316 - 4985 .set CYDEV_P3BA_CMP_RSLT4, 0x40050317 - 4986 .set CYDEV_P3BA_DATA_REG1, 0x40050318 - 4987 .set CYDEV_P3BA_DATA_REG2, 0x40050319 - 4988 .set CYDEV_P3BA_DATA_REG3, 0x4005031a - 4989 .set CYDEV_P3BA_DATA_REG4, 0x4005031b - 4990 .set CYDEV_P3BA_EXP_DATA1, 0x4005031c - 4991 .set CYDEV_P3BA_EXP_DATA2, 0x4005031d - 4992 .set CYDEV_P3BA_EXP_DATA3, 0x4005031e - 4993 .set CYDEV_P3BA_EXP_DATA4, 0x4005031f - 4994 .set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320 - 4995 .set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321 - 4996 .set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322 - 4997 .set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323 - 4998 .set CYDEV_P3BA_BIST_EN, 0x40050324 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 89 - - - 4999 .set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325 - 5000 .set CYDEV_P3BA_SEQCFG1, 0x40050326 - 5001 .set CYDEV_P3BA_SEQCFG2, 0x40050327 - 5002 .set CYDEV_P3BA_Y_CURR, 0x40050328 - 5003 .set CYDEV_P3BA_X_CURR1, 0x40050329 - 5004 .set CYDEV_P3BA_X_CURR2, 0x4005032a - 5005 .set CYDEV_PANTHER_BASE, 0x40080000 - 5006 .set CYDEV_PANTHER_SIZE, 0x00000020 - 5007 .set CYDEV_PANTHER_STCALIB_CFG, 0x40080000 - 5008 .set CYDEV_PANTHER_WAITPIPE, 0x40080004 - 5009 .set CYDEV_PANTHER_TRACE_CFG, 0x40080008 - 5010 .set CYDEV_PANTHER_DBG_CFG, 0x4008000c - 5011 .set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018 - 5012 .set CYDEV_PANTHER_DEVICE_ID, 0x4008001c - 5013 .set CYDEV_FLSECC_BASE, 0x48000000 - 5014 .set CYDEV_FLSECC_SIZE, 0x00008000 - 5015 .set CYDEV_FLSECC_DATA_MBASE, 0x48000000 - 5016 .set CYDEV_FLSECC_DATA_MSIZE, 0x00008000 - 5017 .set CYDEV_FLSHID_BASE, 0x49000000 - 5018 .set CYDEV_FLSHID_SIZE, 0x00000200 - 5019 .set CYDEV_FLSHID_RSVD_MBASE, 0x49000000 - 5020 .set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080 - 5021 .set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080 - 5022 .set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080 - 5023 .set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 - 5024 .set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 - 5025 .set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 - 5026 .set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101 - 5027 .set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 - 5028 .set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 - 5029 .set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 - 5030 .set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 - 5031 .set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 - 5032 .set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107 - 5033 .set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 - 5034 .set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 - 5035 .set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a - 5036 .set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b - 5037 .set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c - 5038 .set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d - 5039 .set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e - 5040 .set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f - 5041 .set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 - 5042 .set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 - 5043 .set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 - 5044 .set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 - 5045 .set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 - 5046 .set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 - 5047 .set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 - 5048 .set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 - 5049 .set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 - 5050 .set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 - 5051 .set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a - 5052 .set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b - 5053 .set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c - 5054 .set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d - 5055 .set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 90 - - - 5056 .set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f - 5057 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 - 5058 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 - 5059 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 - 5060 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 - 5061 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 - 5062 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 - 5063 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 - 5064 .set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 - 5065 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 - 5066 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 - 5067 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a - 5068 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b - 5069 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c - 5070 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d - 5071 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e - 5072 .set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f - 5073 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 - 5074 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 - 5075 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 - 5076 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 - 5077 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 - 5078 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 - 5079 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 - 5080 .set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 - 5081 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 - 5082 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 - 5083 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a - 5084 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b - 5085 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c - 5086 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d - 5087 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e - 5088 .set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f - 5089 .set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 - 5090 .set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 - 5091 .set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 - 5092 .set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac - 5093 .set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae - 5094 .set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 - 5095 .set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 - 5096 .set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 - 5097 .set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 - 5098 .set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 - 5099 .set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba - 5100 .set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce - 5101 .set CYDEV_EXTMEM_BASE, 0x60000000 - 5102 .set CYDEV_EXTMEM_SIZE, 0x00800000 - 5103 .set CYDEV_EXTMEM_DATA_MBASE, 0x60000000 - 5104 .set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000 - 5105 .set CYDEV_ITM_BASE, 0xe0000000 - 5106 .set CYDEV_ITM_SIZE, 0x00001000 - 5107 .set CYDEV_ITM_TRACE_EN, 0xe0000e00 - 5108 .set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40 - 5109 .set CYDEV_ITM_TRACE_CTRL, 0xe0000e80 - 5110 .set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0 - 5111 .set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4 - 5112 .set CYDEV_ITM_PID4, 0xe0000fd0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 91 - - - 5113 .set CYDEV_ITM_PID5, 0xe0000fd4 - 5114 .set CYDEV_ITM_PID6, 0xe0000fd8 - 5115 .set CYDEV_ITM_PID7, 0xe0000fdc - 5116 .set CYDEV_ITM_PID0, 0xe0000fe0 - 5117 .set CYDEV_ITM_PID1, 0xe0000fe4 - 5118 .set CYDEV_ITM_PID2, 0xe0000fe8 - 5119 .set CYDEV_ITM_PID3, 0xe0000fec - 5120 .set CYDEV_ITM_CID0, 0xe0000ff0 - 5121 .set CYDEV_ITM_CID1, 0xe0000ff4 - 5122 .set CYDEV_ITM_CID2, 0xe0000ff8 - 5123 .set CYDEV_ITM_CID3, 0xe0000ffc - 5124 .set CYDEV_DWT_BASE, 0xe0001000 - 5125 .set CYDEV_DWT_SIZE, 0x0000005c - 5126 .set CYDEV_DWT_CTRL, 0xe0001000 - 5127 .set CYDEV_DWT_CYCLE_COUNT, 0xe0001004 - 5128 .set CYDEV_DWT_CPI_COUNT, 0xe0001008 - 5129 .set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c - 5130 .set CYDEV_DWT_SLEEP_COUNT, 0xe0001010 - 5131 .set CYDEV_DWT_LSU_COUNT, 0xe0001014 - 5132 .set CYDEV_DWT_FOLD_COUNT, 0xe0001018 - 5133 .set CYDEV_DWT_PC_SAMPLE, 0xe000101c - 5134 .set CYDEV_DWT_COMP_0, 0xe0001020 - 5135 .set CYDEV_DWT_MASK_0, 0xe0001024 - 5136 .set CYDEV_DWT_FUNCTION_0, 0xe0001028 - 5137 .set CYDEV_DWT_COMP_1, 0xe0001030 - 5138 .set CYDEV_DWT_MASK_1, 0xe0001034 - 5139 .set CYDEV_DWT_FUNCTION_1, 0xe0001038 - 5140 .set CYDEV_DWT_COMP_2, 0xe0001040 - 5141 .set CYDEV_DWT_MASK_2, 0xe0001044 - 5142 .set CYDEV_DWT_FUNCTION_2, 0xe0001048 - 5143 .set CYDEV_DWT_COMP_3, 0xe0001050 - 5144 .set CYDEV_DWT_MASK_3, 0xe0001054 - 5145 .set CYDEV_DWT_FUNCTION_3, 0xe0001058 - 5146 .set CYDEV_FPB_BASE, 0xe0002000 - 5147 .set CYDEV_FPB_SIZE, 0x00001000 - 5148 .set CYDEV_FPB_CTRL, 0xe0002000 - 5149 .set CYDEV_FPB_REMAP, 0xe0002004 - 5150 .set CYDEV_FPB_FP_COMP_0, 0xe0002008 - 5151 .set CYDEV_FPB_FP_COMP_1, 0xe000200c - 5152 .set CYDEV_FPB_FP_COMP_2, 0xe0002010 - 5153 .set CYDEV_FPB_FP_COMP_3, 0xe0002014 - 5154 .set CYDEV_FPB_FP_COMP_4, 0xe0002018 - 5155 .set CYDEV_FPB_FP_COMP_5, 0xe000201c - 5156 .set CYDEV_FPB_FP_COMP_6, 0xe0002020 - 5157 .set CYDEV_FPB_FP_COMP_7, 0xe0002024 - 5158 .set CYDEV_FPB_PID4, 0xe0002fd0 - 5159 .set CYDEV_FPB_PID5, 0xe0002fd4 - 5160 .set CYDEV_FPB_PID6, 0xe0002fd8 - 5161 .set CYDEV_FPB_PID7, 0xe0002fdc - 5162 .set CYDEV_FPB_PID0, 0xe0002fe0 - 5163 .set CYDEV_FPB_PID1, 0xe0002fe4 - 5164 .set CYDEV_FPB_PID2, 0xe0002fe8 - 5165 .set CYDEV_FPB_PID3, 0xe0002fec - 5166 .set CYDEV_FPB_CID0, 0xe0002ff0 - 5167 .set CYDEV_FPB_CID1, 0xe0002ff4 - 5168 .set CYDEV_FPB_CID2, 0xe0002ff8 - 5169 .set CYDEV_FPB_CID3, 0xe0002ffc - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 92 - - - 5170 .set CYDEV_NVIC_BASE, 0xe000e000 - 5171 .set CYDEV_NVIC_SIZE, 0x00000d3c - 5172 .set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004 - 5173 .set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010 - 5174 .set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014 - 5175 .set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018 - 5176 .set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c - 5177 .set CYDEV_NVIC_SETENA0, 0xe000e100 - 5178 .set CYDEV_NVIC_CLRENA0, 0xe000e180 - 5179 .set CYDEV_NVIC_SETPEND0, 0xe000e200 - 5180 .set CYDEV_NVIC_CLRPEND0, 0xe000e280 - 5181 .set CYDEV_NVIC_ACTIVE0, 0xe000e300 - 5182 .set CYDEV_NVIC_PRI_0, 0xe000e400 - 5183 .set CYDEV_NVIC_PRI_1, 0xe000e401 - 5184 .set CYDEV_NVIC_PRI_2, 0xe000e402 - 5185 .set CYDEV_NVIC_PRI_3, 0xe000e403 - 5186 .set CYDEV_NVIC_PRI_4, 0xe000e404 - 5187 .set CYDEV_NVIC_PRI_5, 0xe000e405 - 5188 .set CYDEV_NVIC_PRI_6, 0xe000e406 - 5189 .set CYDEV_NVIC_PRI_7, 0xe000e407 - 5190 .set CYDEV_NVIC_PRI_8, 0xe000e408 - 5191 .set CYDEV_NVIC_PRI_9, 0xe000e409 - 5192 .set CYDEV_NVIC_PRI_10, 0xe000e40a - 5193 .set CYDEV_NVIC_PRI_11, 0xe000e40b - 5194 .set CYDEV_NVIC_PRI_12, 0xe000e40c - 5195 .set CYDEV_NVIC_PRI_13, 0xe000e40d - 5196 .set CYDEV_NVIC_PRI_14, 0xe000e40e - 5197 .set CYDEV_NVIC_PRI_15, 0xe000e40f - 5198 .set CYDEV_NVIC_PRI_16, 0xe000e410 - 5199 .set CYDEV_NVIC_PRI_17, 0xe000e411 - 5200 .set CYDEV_NVIC_PRI_18, 0xe000e412 - 5201 .set CYDEV_NVIC_PRI_19, 0xe000e413 - 5202 .set CYDEV_NVIC_PRI_20, 0xe000e414 - 5203 .set CYDEV_NVIC_PRI_21, 0xe000e415 - 5204 .set CYDEV_NVIC_PRI_22, 0xe000e416 - 5205 .set CYDEV_NVIC_PRI_23, 0xe000e417 - 5206 .set CYDEV_NVIC_PRI_24, 0xe000e418 - 5207 .set CYDEV_NVIC_PRI_25, 0xe000e419 - 5208 .set CYDEV_NVIC_PRI_26, 0xe000e41a - 5209 .set CYDEV_NVIC_PRI_27, 0xe000e41b - 5210 .set CYDEV_NVIC_PRI_28, 0xe000e41c - 5211 .set CYDEV_NVIC_PRI_29, 0xe000e41d - 5212 .set CYDEV_NVIC_PRI_30, 0xe000e41e - 5213 .set CYDEV_NVIC_PRI_31, 0xe000e41f - 5214 .set CYDEV_NVIC_CPUID_BASE, 0xe000ed00 - 5215 .set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04 - 5216 .set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08 - 5217 .set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c - 5218 .set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10 - 5219 .set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14 - 5220 .set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 - 5221 .set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c - 5222 .set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 - 5223 .set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24 - 5224 .set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 - 5225 .set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29 - 5226 .set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 93 - - - 5227 .set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c - 5228 .set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 - 5229 .set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 - 5230 .set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38 - 5231 .set CYDEV_CORE_DBG_BASE, 0xe000edf0 - 5232 .set CYDEV_CORE_DBG_SIZE, 0x00000010 - 5233 .set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0 - 5234 .set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4 - 5235 .set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8 - 5236 .set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc - 5237 .set CYDEV_TPIU_BASE, 0xe0040000 - 5238 .set CYDEV_TPIU_SIZE, 0x00001000 - 5239 .set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 - 5240 .set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 - 5241 .set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 - 5242 .set CYDEV_TPIU_PROTOCOL, 0xe00400f0 - 5243 .set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300 - 5244 .set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304 - 5245 .set CYDEV_TPIU_TRIGGER, 0xe0040ee8 - 5246 .set CYDEV_TPIU_ITETMDATA, 0xe0040eec - 5247 .set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0 - 5248 .set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8 - 5249 .set CYDEV_TPIU_ITITMDATA, 0xe0040efc - 5250 .set CYDEV_TPIU_ITCTRL, 0xe0040f00 - 5251 .set CYDEV_TPIU_DEVID, 0xe0040fc8 - 5252 .set CYDEV_TPIU_DEVTYPE, 0xe0040fcc - 5253 .set CYDEV_TPIU_PID4, 0xe0040fd0 - 5254 .set CYDEV_TPIU_PID5, 0xe0040fd4 - 5255 .set CYDEV_TPIU_PID6, 0xe0040fd8 - 5256 .set CYDEV_TPIU_PID7, 0xe0040fdc - 5257 .set CYDEV_TPIU_PID0, 0xe0040fe0 - 5258 .set CYDEV_TPIU_PID1, 0xe0040fe4 - 5259 .set CYDEV_TPIU_PID2, 0xe0040fe8 - 5260 .set CYDEV_TPIU_PID3, 0xe0040fec - 5261 .set CYDEV_TPIU_CID0, 0xe0040ff0 - 5262 .set CYDEV_TPIU_CID1, 0xe0040ff4 - 5263 .set CYDEV_TPIU_CID2, 0xe0040ff8 - 5264 .set CYDEV_TPIU_CID3, 0xe0040ffc - 5265 .set CYDEV_ETM_BASE, 0xe0041000 - 5266 .set CYDEV_ETM_SIZE, 0x00001000 - 5267 .set CYDEV_ETM_CTL, 0xe0041000 - 5268 .set CYDEV_ETM_CFG_CODE, 0xe0041004 - 5269 .set CYDEV_ETM_TRIG_EVENT, 0xe0041008 - 5270 .set CYDEV_ETM_STATUS, 0xe0041010 - 5271 .set CYDEV_ETM_SYS_CFG, 0xe0041014 - 5272 .set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020 - 5273 .set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024 - 5274 .set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c - 5275 .set CYDEV_ETM_SYNC_FREQ, 0xe00411e0 - 5276 .set CYDEV_ETM_ETM_ID, 0xe00411e4 - 5277 .set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8 - 5278 .set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 - 5279 .set CYDEV_ETM_CS_TRACE_ID, 0xe0041200 - 5280 .set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300 - 5281 .set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304 - 5282 .set CYDEV_ETM_PDSR, 0xe0041314 - 5283 .set CYDEV_ETM_ITMISCIN, 0xe0041ee0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 94 - - - 5284 .set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8 - 5285 .set CYDEV_ETM_ITATBCTR2, 0xe0041ef0 - 5286 .set CYDEV_ETM_ITATBCTR0, 0xe0041ef8 - 5287 .set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00 - 5288 .set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0 - 5289 .set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4 - 5290 .set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0 - 5291 .set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4 - 5292 .set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8 - 5293 .set CYDEV_ETM_DEV_TYPE, 0xe0041fcc - 5294 .set CYDEV_ETM_PID4, 0xe0041fd0 - 5295 .set CYDEV_ETM_PID5, 0xe0041fd4 - 5296 .set CYDEV_ETM_PID6, 0xe0041fd8 - 5297 .set CYDEV_ETM_PID7, 0xe0041fdc - 5298 .set CYDEV_ETM_PID0, 0xe0041fe0 - 5299 .set CYDEV_ETM_PID1, 0xe0041fe4 - 5300 .set CYDEV_ETM_PID2, 0xe0041fe8 - 5301 .set CYDEV_ETM_PID3, 0xe0041fec - 5302 .set CYDEV_ETM_CID0, 0xe0041ff0 - 5303 .set CYDEV_ETM_CID1, 0xe0041ff4 - 5304 .set CYDEV_ETM_CID2, 0xe0041ff8 - 5305 .set CYDEV_ETM_CID3, 0xe0041ffc - 5306 .set CYDEV_ROM_TABLE_BASE, 0xe00ff000 - 5307 .set CYDEV_ROM_TABLE_SIZE, 0x00001000 - 5308 .set CYDEV_ROM_TABLE_NVIC, 0xe00ff000 - 5309 .set CYDEV_ROM_TABLE_DWT, 0xe00ff004 - 5310 .set CYDEV_ROM_TABLE_FPB, 0xe00ff008 - 5311 .set CYDEV_ROM_TABLE_ITM, 0xe00ff00c - 5312 .set CYDEV_ROM_TABLE_TPIU, 0xe00ff010 - 5313 .set CYDEV_ROM_TABLE_ETM, 0xe00ff014 - 5314 .set CYDEV_ROM_TABLE_END, 0xe00ff018 - 5315 .set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc - 5316 .set CYDEV_ROM_TABLE_PID4, 0xe00fffd0 - 5317 .set CYDEV_ROM_TABLE_PID5, 0xe00fffd4 - 5318 .set CYDEV_ROM_TABLE_PID6, 0xe00fffd8 - 5319 .set CYDEV_ROM_TABLE_PID7, 0xe00fffdc - 5320 .set CYDEV_ROM_TABLE_PID0, 0xe00fffe0 - 5321 .set CYDEV_ROM_TABLE_PID1, 0xe00fffe4 - 5322 .set CYDEV_ROM_TABLE_PID2, 0xe00fffe8 - 5323 .set CYDEV_ROM_TABLE_PID3, 0xe00fffec - 5324 .set CYDEV_ROM_TABLE_CID0, 0xe00ffff0 - 5325 .set CYDEV_ROM_TABLE_CID1, 0xe00ffff4 - 5326 .set CYDEV_ROM_TABLE_CID2, 0xe00ffff8 - 5327 .set CYDEV_ROM_TABLE_CID3, 0xe00ffffc - 5328 .set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE - 5329 .set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE - 5330 .set CYDEV_FLS_SECTOR_SIZE, 0x00010000 - 5331 .set CYDEV_FLS_ROW_SIZE, 0x00000100 - 5332 .set CYDEV_ECC_SECTOR_SIZE, 0x00002000 - 5333 .set CYDEV_ECC_ROW_SIZE, 0x00000020 - 5334 .set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 - 5335 .set CYDEV_EEPROM_ROW_SIZE, 0x00000010 - 5336 .set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE - 5337 .set CYCLK_LD_DISABLE, 0x00000004 - 5338 .set CYCLK_LD_SYNC_EN, 0x00000002 - 5339 .set CYCLK_LD_LOAD, 0x00000001 - 5340 .set CYCLK_PIPE, 0x00000080 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 95 - - - 5341 .set CYCLK_SSS, 0x00000040 - 5342 .set CYCLK_EARLY, 0x00000020 - 5343 .set CYCLK_DUTY, 0x00000010 - 5344 .set CYCLK_SYNC, 0x00000008 - 5345 .set CYCLK_SRC_SEL_CLK_SYNC_D, 0 - 5346 .set CYCLK_SRC_SEL_SYNC_DIG, 0 - 5347 .set CYCLK_SRC_SEL_IMO, 1 - 5348 .set CYCLK_SRC_SEL_XTAL_MHZ, 2 - 5349 .set CYCLK_SRC_SEL_XTALM, 2 - 5350 .set CYCLK_SRC_SEL_ILO, 3 - 5351 .set CYCLK_SRC_SEL_PLL, 4 - 5352 .set CYCLK_SRC_SEL_XTAL_KHZ, 5 - 5353 .set CYCLK_SRC_SEL_XTALK, 5 - 5354 .set CYCLK_SRC_SEL_DSI_G, 6 - 5355 .set CYCLK_SRC_SEL_DSI_D, 7 - 5356 .set CYCLK_SRC_SEL_CLK_SYNC_A, 0 - 5357 .set CYCLK_SRC_SEL_DSI_A, 7 - 4 .include "cydevicegnu_trm.inc" - 1 /******************************************************************************* - 2 * FILENAME: cydevicegnu_trm.inc - 3 * - 4 * PSoC Creator 3.0 Component Pack 7 - 5 * - 6 * DESCRIPTION: - 7 * This file provides all of the address values for the entire PSoC device. - 8 * This file is automatically generated by PSoC Creator. - 9 * - 10 ******************************************************************************** - 11 * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12 * You may use this file only in accordance with the license, terms, conditions, - 13 * disclaimers, and limitations in the end user license agreement accompanying - 14 * the software package with which this file was provided. - 15 ********************************************************************************/ - 16 - 17 .set CYDEV_FLASH_BASE, 0x00000000 - 18 .set CYDEV_FLASH_SIZE, 0x00020000 - 19 .set CYREG_FLASH_DATA_MBASE, 0x00000000 - 20 .set CYREG_FLASH_DATA_MSIZE, 0x00020000 - 21 .set CYDEV_SRAM_BASE, 0x1fffc000 - 22 .set CYDEV_SRAM_SIZE, 0x00008000 - 23 .set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000 - 24 .set CYREG_SRAM_CODE64K_MSIZE, 0x00004000 - 25 .set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000 - 26 .set CYREG_SRAM_CODE32K_MSIZE, 0x00002000 - 27 .set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000 - 28 .set CYREG_SRAM_CODE16K_MSIZE, 0x00001000 - 29 .set CYREG_SRAM_CODE_MBASE, 0x1fffc000 - 30 .set CYREG_SRAM_CODE_MSIZE, 0x00004000 - 31 .set CYREG_SRAM_DATA_MBASE, 0x20000000 - 32 .set CYREG_SRAM_DATA_MSIZE, 0x00004000 - 33 .set CYREG_SRAM_DATA16K_MBASE, 0x20001000 - 34 .set CYREG_SRAM_DATA16K_MSIZE, 0x00001000 - 35 .set CYREG_SRAM_DATA32K_MBASE, 0x20002000 - 36 .set CYREG_SRAM_DATA32K_MSIZE, 0x00002000 - 37 .set CYREG_SRAM_DATA64K_MBASE, 0x20004000 - 38 .set CYREG_SRAM_DATA64K_MSIZE, 0x00004000 - 39 .set CYDEV_DMA_BASE, 0x20008000 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 96 - - - 40 .set CYDEV_DMA_SIZE, 0x00008000 - 41 .set CYREG_DMA_SRAM64K_MBASE, 0x20008000 - 42 .set CYREG_DMA_SRAM64K_MSIZE, 0x00004000 - 43 .set CYREG_DMA_SRAM32K_MBASE, 0x2000c000 - 44 .set CYREG_DMA_SRAM32K_MSIZE, 0x00002000 - 45 .set CYREG_DMA_SRAM16K_MBASE, 0x2000e000 - 46 .set CYREG_DMA_SRAM16K_MSIZE, 0x00001000 - 47 .set CYREG_DMA_SRAM_MBASE, 0x2000f000 - 48 .set CYREG_DMA_SRAM_MSIZE, 0x00001000 - 49 .set CYDEV_CLKDIST_BASE, 0x40004000 - 50 .set CYDEV_CLKDIST_SIZE, 0x00000110 - 51 .set CYREG_CLKDIST_CR, 0x40004000 - 52 .set CYREG_CLKDIST_LD, 0x40004001 - 53 .set CYREG_CLKDIST_WRK0, 0x40004002 - 54 .set CYREG_CLKDIST_WRK1, 0x40004003 - 55 .set CYREG_CLKDIST_MSTR0, 0x40004004 - 56 .set CYREG_CLKDIST_MSTR1, 0x40004005 - 57 .set CYREG_CLKDIST_BCFG0, 0x40004006 - 58 .set CYREG_CLKDIST_BCFG1, 0x40004007 - 59 .set CYREG_CLKDIST_BCFG2, 0x40004008 - 60 .set CYREG_CLKDIST_UCFG, 0x40004009 - 61 .set CYREG_CLKDIST_DLY0, 0x4000400a - 62 .set CYREG_CLKDIST_DLY1, 0x4000400b - 63 .set CYREG_CLKDIST_DMASK, 0x40004010 - 64 .set CYREG_CLKDIST_AMASK, 0x40004014 - 65 .set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 - 66 .set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 - 67 .set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080 - 68 .set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081 - 69 .set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082 - 70 .set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 - 71 .set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 - 72 .set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084 - 73 .set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085 - 74 .set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086 - 75 .set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 - 76 .set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 - 77 .set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088 - 78 .set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089 - 79 .set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a - 80 .set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c - 81 .set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 - 82 .set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c - 83 .set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d - 84 .set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e - 85 .set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 - 86 .set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 - 87 .set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090 - 88 .set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091 - 89 .set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092 - 90 .set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 - 91 .set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 - 92 .set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094 - 93 .set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095 - 94 .set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096 - 95 .set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 - 96 .set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 97 - - - 97 .set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098 - 98 .set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099 - 99 .set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a - 100 .set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c - 101 .set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 - 102 .set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c - 103 .set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d - 104 .set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e - 105 .set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 - 106 .set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 - 107 .set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100 - 108 .set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101 - 109 .set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102 - 110 .set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103 - 111 .set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 - 112 .set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 - 113 .set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104 - 114 .set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105 - 115 .set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106 - 116 .set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107 - 117 .set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 - 118 .set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 - 119 .set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108 - 120 .set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109 - 121 .set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a - 122 .set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b - 123 .set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c - 124 .set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 - 125 .set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c - 126 .set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d - 127 .set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e - 128 .set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f - 129 .set CYDEV_FASTCLK_BASE, 0x40004200 - 130 .set CYDEV_FASTCLK_SIZE, 0x00000026 - 131 .set CYDEV_FASTCLK_IMO_BASE, 0x40004200 - 132 .set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 - 133 .set CYREG_FASTCLK_IMO_CR, 0x40004200 - 134 .set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 - 135 .set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 - 136 .set CYREG_FASTCLK_XMHZ_CSR, 0x40004210 - 137 .set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212 - 138 .set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213 - 139 .set CYDEV_FASTCLK_PLL_BASE, 0x40004220 - 140 .set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 - 141 .set CYREG_FASTCLK_PLL_CFG0, 0x40004220 - 142 .set CYREG_FASTCLK_PLL_CFG1, 0x40004221 - 143 .set CYREG_FASTCLK_PLL_P, 0x40004222 - 144 .set CYREG_FASTCLK_PLL_Q, 0x40004223 - 145 .set CYREG_FASTCLK_PLL_SR, 0x40004225 - 146 .set CYDEV_SLOWCLK_BASE, 0x40004300 - 147 .set CYDEV_SLOWCLK_SIZE, 0x0000000b - 148 .set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 - 149 .set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 - 150 .set CYREG_SLOWCLK_ILO_CR0, 0x40004300 - 151 .set CYREG_SLOWCLK_ILO_CR1, 0x40004301 - 152 .set CYDEV_SLOWCLK_X32_BASE, 0x40004308 - 153 .set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 98 - - - 154 .set CYREG_SLOWCLK_X32_CR, 0x40004308 - 155 .set CYREG_SLOWCLK_X32_CFG, 0x40004309 - 156 .set CYREG_SLOWCLK_X32_TST, 0x4000430a - 157 .set CYDEV_BOOST_BASE, 0x40004320 - 158 .set CYDEV_BOOST_SIZE, 0x00000007 - 159 .set CYREG_BOOST_CR0, 0x40004320 - 160 .set CYREG_BOOST_CR1, 0x40004321 - 161 .set CYREG_BOOST_CR2, 0x40004322 - 162 .set CYREG_BOOST_CR3, 0x40004323 - 163 .set CYREG_BOOST_SR, 0x40004324 - 164 .set CYREG_BOOST_CR4, 0x40004325 - 165 .set CYREG_BOOST_SR2, 0x40004326 - 166 .set CYDEV_PWRSYS_BASE, 0x40004330 - 167 .set CYDEV_PWRSYS_SIZE, 0x00000002 - 168 .set CYREG_PWRSYS_CR0, 0x40004330 - 169 .set CYREG_PWRSYS_CR1, 0x40004331 - 170 .set CYDEV_PM_BASE, 0x40004380 - 171 .set CYDEV_PM_SIZE, 0x00000057 - 172 .set CYREG_PM_TW_CFG0, 0x40004380 - 173 .set CYREG_PM_TW_CFG1, 0x40004381 - 174 .set CYREG_PM_TW_CFG2, 0x40004382 - 175 .set CYREG_PM_WDT_CFG, 0x40004383 - 176 .set CYREG_PM_WDT_CR, 0x40004384 - 177 .set CYREG_PM_INT_SR, 0x40004390 - 178 .set CYREG_PM_MODE_CFG0, 0x40004391 - 179 .set CYREG_PM_MODE_CFG1, 0x40004392 - 180 .set CYREG_PM_MODE_CSR, 0x40004393 - 181 .set CYREG_PM_USB_CR0, 0x40004394 - 182 .set CYREG_PM_WAKEUP_CFG0, 0x40004398 - 183 .set CYREG_PM_WAKEUP_CFG1, 0x40004399 - 184 .set CYREG_PM_WAKEUP_CFG2, 0x4000439a - 185 .set CYDEV_PM_ACT_BASE, 0x400043a0 - 186 .set CYDEV_PM_ACT_SIZE, 0x0000000e - 187 .set CYREG_PM_ACT_CFG0, 0x400043a0 - 188 .set CYREG_PM_ACT_CFG1, 0x400043a1 - 189 .set CYREG_PM_ACT_CFG2, 0x400043a2 - 190 .set CYREG_PM_ACT_CFG3, 0x400043a3 - 191 .set CYREG_PM_ACT_CFG4, 0x400043a4 - 192 .set CYREG_PM_ACT_CFG5, 0x400043a5 - 193 .set CYREG_PM_ACT_CFG6, 0x400043a6 - 194 .set CYREG_PM_ACT_CFG7, 0x400043a7 - 195 .set CYREG_PM_ACT_CFG8, 0x400043a8 - 196 .set CYREG_PM_ACT_CFG9, 0x400043a9 - 197 .set CYREG_PM_ACT_CFG10, 0x400043aa - 198 .set CYREG_PM_ACT_CFG11, 0x400043ab - 199 .set CYREG_PM_ACT_CFG12, 0x400043ac - 200 .set CYREG_PM_ACT_CFG13, 0x400043ad - 201 .set CYDEV_PM_STBY_BASE, 0x400043b0 - 202 .set CYDEV_PM_STBY_SIZE, 0x0000000e - 203 .set CYREG_PM_STBY_CFG0, 0x400043b0 - 204 .set CYREG_PM_STBY_CFG1, 0x400043b1 - 205 .set CYREG_PM_STBY_CFG2, 0x400043b2 - 206 .set CYREG_PM_STBY_CFG3, 0x400043b3 - 207 .set CYREG_PM_STBY_CFG4, 0x400043b4 - 208 .set CYREG_PM_STBY_CFG5, 0x400043b5 - 209 .set CYREG_PM_STBY_CFG6, 0x400043b6 - 210 .set CYREG_PM_STBY_CFG7, 0x400043b7 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 99 - - - 211 .set CYREG_PM_STBY_CFG8, 0x400043b8 - 212 .set CYREG_PM_STBY_CFG9, 0x400043b9 - 213 .set CYREG_PM_STBY_CFG10, 0x400043ba - 214 .set CYREG_PM_STBY_CFG11, 0x400043bb - 215 .set CYREG_PM_STBY_CFG12, 0x400043bc - 216 .set CYREG_PM_STBY_CFG13, 0x400043bd - 217 .set CYDEV_PM_AVAIL_BASE, 0x400043c0 - 218 .set CYDEV_PM_AVAIL_SIZE, 0x00000017 - 219 .set CYREG_PM_AVAIL_CR0, 0x400043c0 - 220 .set CYREG_PM_AVAIL_CR1, 0x400043c1 - 221 .set CYREG_PM_AVAIL_CR2, 0x400043c2 - 222 .set CYREG_PM_AVAIL_CR3, 0x400043c3 - 223 .set CYREG_PM_AVAIL_CR4, 0x400043c4 - 224 .set CYREG_PM_AVAIL_CR5, 0x400043c5 - 225 .set CYREG_PM_AVAIL_CR6, 0x400043c6 - 226 .set CYREG_PM_AVAIL_SR0, 0x400043d0 - 227 .set CYREG_PM_AVAIL_SR1, 0x400043d1 - 228 .set CYREG_PM_AVAIL_SR2, 0x400043d2 - 229 .set CYREG_PM_AVAIL_SR3, 0x400043d3 - 230 .set CYREG_PM_AVAIL_SR4, 0x400043d4 - 231 .set CYREG_PM_AVAIL_SR5, 0x400043d5 - 232 .set CYREG_PM_AVAIL_SR6, 0x400043d6 - 233 .set CYDEV_PICU_BASE, 0x40004500 - 234 .set CYDEV_PICU_SIZE, 0x000000b0 - 235 .set CYDEV_PICU_INTTYPE_BASE, 0x40004500 - 236 .set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 - 237 .set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 - 238 .set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 - 239 .set CYREG_PICU0_INTTYPE0, 0x40004500 - 240 .set CYREG_PICU0_INTTYPE1, 0x40004501 - 241 .set CYREG_PICU0_INTTYPE2, 0x40004502 - 242 .set CYREG_PICU0_INTTYPE3, 0x40004503 - 243 .set CYREG_PICU0_INTTYPE4, 0x40004504 - 244 .set CYREG_PICU0_INTTYPE5, 0x40004505 - 245 .set CYREG_PICU0_INTTYPE6, 0x40004506 - 246 .set CYREG_PICU0_INTTYPE7, 0x40004507 - 247 .set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 - 248 .set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 - 249 .set CYREG_PICU1_INTTYPE0, 0x40004508 - 250 .set CYREG_PICU1_INTTYPE1, 0x40004509 - 251 .set CYREG_PICU1_INTTYPE2, 0x4000450a - 252 .set CYREG_PICU1_INTTYPE3, 0x4000450b - 253 .set CYREG_PICU1_INTTYPE4, 0x4000450c - 254 .set CYREG_PICU1_INTTYPE5, 0x4000450d - 255 .set CYREG_PICU1_INTTYPE6, 0x4000450e - 256 .set CYREG_PICU1_INTTYPE7, 0x4000450f - 257 .set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 - 258 .set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 - 259 .set CYREG_PICU2_INTTYPE0, 0x40004510 - 260 .set CYREG_PICU2_INTTYPE1, 0x40004511 - 261 .set CYREG_PICU2_INTTYPE2, 0x40004512 - 262 .set CYREG_PICU2_INTTYPE3, 0x40004513 - 263 .set CYREG_PICU2_INTTYPE4, 0x40004514 - 264 .set CYREG_PICU2_INTTYPE5, 0x40004515 - 265 .set CYREG_PICU2_INTTYPE6, 0x40004516 - 266 .set CYREG_PICU2_INTTYPE7, 0x40004517 - 267 .set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 100 - - - 268 .set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 - 269 .set CYREG_PICU3_INTTYPE0, 0x40004518 - 270 .set CYREG_PICU3_INTTYPE1, 0x40004519 - 271 .set CYREG_PICU3_INTTYPE2, 0x4000451a - 272 .set CYREG_PICU3_INTTYPE3, 0x4000451b - 273 .set CYREG_PICU3_INTTYPE4, 0x4000451c - 274 .set CYREG_PICU3_INTTYPE5, 0x4000451d - 275 .set CYREG_PICU3_INTTYPE6, 0x4000451e - 276 .set CYREG_PICU3_INTTYPE7, 0x4000451f - 277 .set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 - 278 .set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 - 279 .set CYREG_PICU4_INTTYPE0, 0x40004520 - 280 .set CYREG_PICU4_INTTYPE1, 0x40004521 - 281 .set CYREG_PICU4_INTTYPE2, 0x40004522 - 282 .set CYREG_PICU4_INTTYPE3, 0x40004523 - 283 .set CYREG_PICU4_INTTYPE4, 0x40004524 - 284 .set CYREG_PICU4_INTTYPE5, 0x40004525 - 285 .set CYREG_PICU4_INTTYPE6, 0x40004526 - 286 .set CYREG_PICU4_INTTYPE7, 0x40004527 - 287 .set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 - 288 .set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 - 289 .set CYREG_PICU5_INTTYPE0, 0x40004528 - 290 .set CYREG_PICU5_INTTYPE1, 0x40004529 - 291 .set CYREG_PICU5_INTTYPE2, 0x4000452a - 292 .set CYREG_PICU5_INTTYPE3, 0x4000452b - 293 .set CYREG_PICU5_INTTYPE4, 0x4000452c - 294 .set CYREG_PICU5_INTTYPE5, 0x4000452d - 295 .set CYREG_PICU5_INTTYPE6, 0x4000452e - 296 .set CYREG_PICU5_INTTYPE7, 0x4000452f - 297 .set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 - 298 .set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 - 299 .set CYREG_PICU6_INTTYPE0, 0x40004530 - 300 .set CYREG_PICU6_INTTYPE1, 0x40004531 - 301 .set CYREG_PICU6_INTTYPE2, 0x40004532 - 302 .set CYREG_PICU6_INTTYPE3, 0x40004533 - 303 .set CYREG_PICU6_INTTYPE4, 0x40004534 - 304 .set CYREG_PICU6_INTTYPE5, 0x40004535 - 305 .set CYREG_PICU6_INTTYPE6, 0x40004536 - 306 .set CYREG_PICU6_INTTYPE7, 0x40004537 - 307 .set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 - 308 .set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 - 309 .set CYREG_PICU12_INTTYPE0, 0x40004560 - 310 .set CYREG_PICU12_INTTYPE1, 0x40004561 - 311 .set CYREG_PICU12_INTTYPE2, 0x40004562 - 312 .set CYREG_PICU12_INTTYPE3, 0x40004563 - 313 .set CYREG_PICU12_INTTYPE4, 0x40004564 - 314 .set CYREG_PICU12_INTTYPE5, 0x40004565 - 315 .set CYREG_PICU12_INTTYPE6, 0x40004566 - 316 .set CYREG_PICU12_INTTYPE7, 0x40004567 - 317 .set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 - 318 .set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 - 319 .set CYREG_PICU15_INTTYPE0, 0x40004578 - 320 .set CYREG_PICU15_INTTYPE1, 0x40004579 - 321 .set CYREG_PICU15_INTTYPE2, 0x4000457a - 322 .set CYREG_PICU15_INTTYPE3, 0x4000457b - 323 .set CYREG_PICU15_INTTYPE4, 0x4000457c - 324 .set CYREG_PICU15_INTTYPE5, 0x4000457d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 101 - - - 325 .set CYREG_PICU15_INTTYPE6, 0x4000457e - 326 .set CYREG_PICU15_INTTYPE7, 0x4000457f - 327 .set CYDEV_PICU_STAT_BASE, 0x40004580 - 328 .set CYDEV_PICU_STAT_SIZE, 0x00000010 - 329 .set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 - 330 .set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 - 331 .set CYREG_PICU0_INTSTAT, 0x40004580 - 332 .set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 - 333 .set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 - 334 .set CYREG_PICU1_INTSTAT, 0x40004581 - 335 .set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 - 336 .set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 - 337 .set CYREG_PICU2_INTSTAT, 0x40004582 - 338 .set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 - 339 .set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 - 340 .set CYREG_PICU3_INTSTAT, 0x40004583 - 341 .set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 - 342 .set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 - 343 .set CYREG_PICU4_INTSTAT, 0x40004584 - 344 .set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 - 345 .set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 - 346 .set CYREG_PICU5_INTSTAT, 0x40004585 - 347 .set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 - 348 .set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 - 349 .set CYREG_PICU6_INTSTAT, 0x40004586 - 350 .set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c - 351 .set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 - 352 .set CYREG_PICU12_INTSTAT, 0x4000458c - 353 .set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f - 354 .set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 - 355 .set CYREG_PICU15_INTSTAT, 0x4000458f - 356 .set CYDEV_PICU_SNAP_BASE, 0x40004590 - 357 .set CYDEV_PICU_SNAP_SIZE, 0x00000010 - 358 .set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 - 359 .set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 - 360 .set CYREG_PICU0_SNAP, 0x40004590 - 361 .set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 - 362 .set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 - 363 .set CYREG_PICU1_SNAP, 0x40004591 - 364 .set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 - 365 .set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 - 366 .set CYREG_PICU2_SNAP, 0x40004592 - 367 .set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 - 368 .set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 - 369 .set CYREG_PICU3_SNAP, 0x40004593 - 370 .set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 - 371 .set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 - 372 .set CYREG_PICU4_SNAP, 0x40004594 - 373 .set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 - 374 .set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 - 375 .set CYREG_PICU5_SNAP, 0x40004595 - 376 .set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 - 377 .set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 - 378 .set CYREG_PICU6_SNAP, 0x40004596 - 379 .set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c - 380 .set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 - 381 .set CYREG_PICU12_SNAP, 0x4000459c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 102 - - - 382 .set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f - 383 .set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 - 384 .set CYREG_PICU_15_SNAP_15, 0x4000459f - 385 .set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 - 386 .set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 - 387 .set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 - 388 .set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 - 389 .set CYREG_PICU0_DISABLE_COR, 0x400045a0 - 390 .set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 - 391 .set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 - 392 .set CYREG_PICU1_DISABLE_COR, 0x400045a1 - 393 .set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 - 394 .set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 - 395 .set CYREG_PICU2_DISABLE_COR, 0x400045a2 - 396 .set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 - 397 .set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 - 398 .set CYREG_PICU3_DISABLE_COR, 0x400045a3 - 399 .set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 - 400 .set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 - 401 .set CYREG_PICU4_DISABLE_COR, 0x400045a4 - 402 .set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 - 403 .set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 - 404 .set CYREG_PICU5_DISABLE_COR, 0x400045a5 - 405 .set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 - 406 .set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 - 407 .set CYREG_PICU6_DISABLE_COR, 0x400045a6 - 408 .set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac - 409 .set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 - 410 .set CYREG_PICU12_DISABLE_COR, 0x400045ac - 411 .set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af - 412 .set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 - 413 .set CYREG_PICU15_DISABLE_COR, 0x400045af - 414 .set CYDEV_MFGCFG_BASE, 0x40004600 - 415 .set CYDEV_MFGCFG_SIZE, 0x000000ed - 416 .set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 - 417 .set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 - 418 .set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 - 419 .set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 - 420 .set CYREG_DAC0_TR, 0x40004608 - 421 .set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 - 422 .set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 - 423 .set CYREG_DAC1_TR, 0x40004609 - 424 .set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a - 425 .set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 - 426 .set CYREG_DAC2_TR, 0x4000460a - 427 .set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b - 428 .set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 - 429 .set CYREG_DAC3_TR, 0x4000460b - 430 .set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 - 431 .set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 - 432 .set CYREG_NPUMP_DSM_TR0, 0x40004610 - 433 .set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 - 434 .set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 - 435 .set CYREG_NPUMP_SC_TR0, 0x40004611 - 436 .set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 - 437 .set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 - 438 .set CYREG_NPUMP_OPAMP_TR0, 0x40004612 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 103 - - - 439 .set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 - 440 .set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 - 441 .set CYREG_SAR0_TR0, 0x40004614 - 442 .set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 - 443 .set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 - 444 .set CYREG_SAR1_TR0, 0x40004616 - 445 .set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 - 446 .set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 - 447 .set CYREG_OPAMP0_TR0, 0x40004620 - 448 .set CYREG_OPAMP0_TR1, 0x40004621 - 449 .set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 - 450 .set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 - 451 .set CYREG_OPAMP1_TR0, 0x40004622 - 452 .set CYREG_OPAMP1_TR1, 0x40004623 - 453 .set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 - 454 .set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 - 455 .set CYREG_OPAMP2_TR0, 0x40004624 - 456 .set CYREG_OPAMP2_TR1, 0x40004625 - 457 .set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 - 458 .set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 - 459 .set CYREG_OPAMP3_TR0, 0x40004626 - 460 .set CYREG_OPAMP3_TR1, 0x40004627 - 461 .set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 - 462 .set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 - 463 .set CYREG_CMP0_TR0, 0x40004630 - 464 .set CYREG_CMP0_TR1, 0x40004631 - 465 .set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 - 466 .set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 - 467 .set CYREG_CMP1_TR0, 0x40004632 - 468 .set CYREG_CMP1_TR1, 0x40004633 - 469 .set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 - 470 .set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 - 471 .set CYREG_CMP2_TR0, 0x40004634 - 472 .set CYREG_CMP2_TR1, 0x40004635 - 473 .set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 - 474 .set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 - 475 .set CYREG_CMP3_TR0, 0x40004636 - 476 .set CYREG_CMP3_TR1, 0x40004637 - 477 .set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 - 478 .set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b - 479 .set CYREG_PWRSYS_HIB_TR0, 0x40004680 - 480 .set CYREG_PWRSYS_HIB_TR1, 0x40004681 - 481 .set CYREG_PWRSYS_I2C_TR, 0x40004682 - 482 .set CYREG_PWRSYS_SLP_TR, 0x40004683 - 483 .set CYREG_PWRSYS_BUZZ_TR, 0x40004684 - 484 .set CYREG_PWRSYS_WAKE_TR0, 0x40004685 - 485 .set CYREG_PWRSYS_WAKE_TR1, 0x40004686 - 486 .set CYREG_PWRSYS_BREF_TR, 0x40004687 - 487 .set CYREG_PWRSYS_BG_TR, 0x40004688 - 488 .set CYREG_PWRSYS_WAKE_TR2, 0x40004689 - 489 .set CYREG_PWRSYS_WAKE_TR3, 0x4000468a - 490 .set CYDEV_MFGCFG_ILO_BASE, 0x40004690 - 491 .set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 - 492 .set CYREG_ILO_TR0, 0x40004690 - 493 .set CYREG_ILO_TR1, 0x40004691 - 494 .set CYDEV_MFGCFG_X32_BASE, 0x40004698 - 495 .set CYDEV_MFGCFG_X32_SIZE, 0x00000001 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 104 - - - 496 .set CYREG_X32_TR, 0x40004698 - 497 .set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 - 498 .set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 - 499 .set CYREG_IMO_TR0, 0x400046a0 - 500 .set CYREG_IMO_TR1, 0x400046a1 - 501 .set CYREG_IMO_GAIN, 0x400046a2 - 502 .set CYREG_IMO_C36M, 0x400046a3 - 503 .set CYREG_IMO_TR2, 0x400046a4 - 504 .set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 - 505 .set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 - 506 .set CYREG_XMHZ_TR, 0x400046a8 - 507 .set CYREG_MFGCFG_DLY, 0x400046c0 - 508 .set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 - 509 .set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d - 510 .set CYREG_MLOGIC_DMPSTR, 0x400046e2 - 511 .set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 - 512 .set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 - 513 .set CYREG_MLOGIC_SEG_CR, 0x400046e4 - 514 .set CYREG_MLOGIC_SEG_CFG0, 0x400046e5 - 515 .set CYREG_MLOGIC_DEBUG, 0x400046e8 - 516 .set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea - 517 .set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 - 518 .set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea - 519 .set CYREG_MLOGIC_REV_ID, 0x400046ec - 520 .set CYDEV_RESET_BASE, 0x400046f0 - 521 .set CYDEV_RESET_SIZE, 0x0000000f - 522 .set CYREG_RESET_IPOR_CR0, 0x400046f0 - 523 .set CYREG_RESET_IPOR_CR1, 0x400046f1 - 524 .set CYREG_RESET_IPOR_CR2, 0x400046f2 - 525 .set CYREG_RESET_IPOR_CR3, 0x400046f3 - 526 .set CYREG_RESET_CR0, 0x400046f4 - 527 .set CYREG_RESET_CR1, 0x400046f5 - 528 .set CYREG_RESET_CR2, 0x400046f6 - 529 .set CYREG_RESET_CR3, 0x400046f7 - 530 .set CYREG_RESET_CR4, 0x400046f8 - 531 .set CYREG_RESET_CR5, 0x400046f9 - 532 .set CYREG_RESET_SR0, 0x400046fa - 533 .set CYREG_RESET_SR1, 0x400046fb - 534 .set CYREG_RESET_SR2, 0x400046fc - 535 .set CYREG_RESET_SR3, 0x400046fd - 536 .set CYREG_RESET_TR, 0x400046fe - 537 .set CYDEV_SPC_BASE, 0x40004700 - 538 .set CYDEV_SPC_SIZE, 0x00000100 - 539 .set CYREG_SPC_FM_EE_CR, 0x40004700 - 540 .set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701 - 541 .set CYREG_SPC_EE_SCR, 0x40004702 - 542 .set CYREG_SPC_EE_ERR, 0x40004703 - 543 .set CYREG_SPC_CPU_DATA, 0x40004720 - 544 .set CYREG_SPC_DMA_DATA, 0x40004721 - 545 .set CYREG_SPC_SR, 0x40004722 - 546 .set CYREG_SPC_CR, 0x40004723 - 547 .set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 - 548 .set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 - 549 .set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 - 550 .set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 - 551 .set CYDEV_CACHE_BASE, 0x40004800 - 552 .set CYDEV_CACHE_SIZE, 0x0000009c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 105 - - - 553 .set CYREG_CACHE_CC_CTL, 0x40004800 - 554 .set CYREG_CACHE_ECC_CORR, 0x40004880 - 555 .set CYREG_CACHE_ECC_ERR, 0x40004888 - 556 .set CYREG_CACHE_FLASH_ERR, 0x40004890 - 557 .set CYREG_CACHE_HITMISS, 0x40004898 - 558 .set CYDEV_I2C_BASE, 0x40004900 - 559 .set CYDEV_I2C_SIZE, 0x000000e1 - 560 .set CYREG_I2C_XCFG, 0x400049c8 - 561 .set CYREG_I2C_ADR, 0x400049ca - 562 .set CYREG_I2C_CFG, 0x400049d6 - 563 .set CYREG_I2C_CSR, 0x400049d7 - 564 .set CYREG_I2C_D, 0x400049d8 - 565 .set CYREG_I2C_MCSR, 0x400049d9 - 566 .set CYREG_I2C_CLK_DIV1, 0x400049db - 567 .set CYREG_I2C_CLK_DIV2, 0x400049dc - 568 .set CYREG_I2C_TMOUT_CSR, 0x400049dd - 569 .set CYREG_I2C_TMOUT_SR, 0x400049de - 570 .set CYREG_I2C_TMOUT_CFG0, 0x400049df - 571 .set CYREG_I2C_TMOUT_CFG1, 0x400049e0 - 572 .set CYDEV_DEC_BASE, 0x40004e00 - 573 .set CYDEV_DEC_SIZE, 0x00000015 - 574 .set CYREG_DEC_CR, 0x40004e00 - 575 .set CYREG_DEC_SR, 0x40004e01 - 576 .set CYREG_DEC_SHIFT1, 0x40004e02 - 577 .set CYREG_DEC_SHIFT2, 0x40004e03 - 578 .set CYREG_DEC_DR2, 0x40004e04 - 579 .set CYREG_DEC_DR2H, 0x40004e05 - 580 .set CYREG_DEC_DR1, 0x40004e06 - 581 .set CYREG_DEC_OCOR, 0x40004e08 - 582 .set CYREG_DEC_OCORM, 0x40004e09 - 583 .set CYREG_DEC_OCORH, 0x40004e0a - 584 .set CYREG_DEC_GCOR, 0x40004e0c - 585 .set CYREG_DEC_GCORH, 0x40004e0d - 586 .set CYREG_DEC_GVAL, 0x40004e0e - 587 .set CYREG_DEC_OUTSAMP, 0x40004e10 - 588 .set CYREG_DEC_OUTSAMPM, 0x40004e11 - 589 .set CYREG_DEC_OUTSAMPH, 0x40004e12 - 590 .set CYREG_DEC_OUTSAMPS, 0x40004e13 - 591 .set CYREG_DEC_COHER, 0x40004e14 - 592 .set CYDEV_TMR0_BASE, 0x40004f00 - 593 .set CYDEV_TMR0_SIZE, 0x0000000c - 594 .set CYREG_TMR0_CFG0, 0x40004f00 - 595 .set CYREG_TMR0_CFG1, 0x40004f01 - 596 .set CYREG_TMR0_CFG2, 0x40004f02 - 597 .set CYREG_TMR0_SR0, 0x40004f03 - 598 .set CYREG_TMR0_PER0, 0x40004f04 - 599 .set CYREG_TMR0_PER1, 0x40004f05 - 600 .set CYREG_TMR0_CNT_CMP0, 0x40004f06 - 601 .set CYREG_TMR0_CNT_CMP1, 0x40004f07 - 602 .set CYREG_TMR0_CAP0, 0x40004f08 - 603 .set CYREG_TMR0_CAP1, 0x40004f09 - 604 .set CYREG_TMR0_RT0, 0x40004f0a - 605 .set CYREG_TMR0_RT1, 0x40004f0b - 606 .set CYDEV_TMR1_BASE, 0x40004f0c - 607 .set CYDEV_TMR1_SIZE, 0x0000000c - 608 .set CYREG_TMR1_CFG0, 0x40004f0c - 609 .set CYREG_TMR1_CFG1, 0x40004f0d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 106 - - - 610 .set CYREG_TMR1_CFG2, 0x40004f0e - 611 .set CYREG_TMR1_SR0, 0x40004f0f - 612 .set CYREG_TMR1_PER0, 0x40004f10 - 613 .set CYREG_TMR1_PER1, 0x40004f11 - 614 .set CYREG_TMR1_CNT_CMP0, 0x40004f12 - 615 .set CYREG_TMR1_CNT_CMP1, 0x40004f13 - 616 .set CYREG_TMR1_CAP0, 0x40004f14 - 617 .set CYREG_TMR1_CAP1, 0x40004f15 - 618 .set CYREG_TMR1_RT0, 0x40004f16 - 619 .set CYREG_TMR1_RT1, 0x40004f17 - 620 .set CYDEV_TMR2_BASE, 0x40004f18 - 621 .set CYDEV_TMR2_SIZE, 0x0000000c - 622 .set CYREG_TMR2_CFG0, 0x40004f18 - 623 .set CYREG_TMR2_CFG1, 0x40004f19 - 624 .set CYREG_TMR2_CFG2, 0x40004f1a - 625 .set CYREG_TMR2_SR0, 0x40004f1b - 626 .set CYREG_TMR2_PER0, 0x40004f1c - 627 .set CYREG_TMR2_PER1, 0x40004f1d - 628 .set CYREG_TMR2_CNT_CMP0, 0x40004f1e - 629 .set CYREG_TMR2_CNT_CMP1, 0x40004f1f - 630 .set CYREG_TMR2_CAP0, 0x40004f20 - 631 .set CYREG_TMR2_CAP1, 0x40004f21 - 632 .set CYREG_TMR2_RT0, 0x40004f22 - 633 .set CYREG_TMR2_RT1, 0x40004f23 - 634 .set CYDEV_TMR3_BASE, 0x40004f24 - 635 .set CYDEV_TMR3_SIZE, 0x0000000c - 636 .set CYREG_TMR3_CFG0, 0x40004f24 - 637 .set CYREG_TMR3_CFG1, 0x40004f25 - 638 .set CYREG_TMR3_CFG2, 0x40004f26 - 639 .set CYREG_TMR3_SR0, 0x40004f27 - 640 .set CYREG_TMR3_PER0, 0x40004f28 - 641 .set CYREG_TMR3_PER1, 0x40004f29 - 642 .set CYREG_TMR3_CNT_CMP0, 0x40004f2a - 643 .set CYREG_TMR3_CNT_CMP1, 0x40004f2b - 644 .set CYREG_TMR3_CAP0, 0x40004f2c - 645 .set CYREG_TMR3_CAP1, 0x40004f2d - 646 .set CYREG_TMR3_RT0, 0x40004f2e - 647 .set CYREG_TMR3_RT1, 0x40004f2f - 648 .set CYDEV_IO_BASE, 0x40005000 - 649 .set CYDEV_IO_SIZE, 0x00000200 - 650 .set CYDEV_IO_PC_BASE, 0x40005000 - 651 .set CYDEV_IO_PC_SIZE, 0x00000080 - 652 .set CYDEV_IO_PC_PRT0_BASE, 0x40005000 - 653 .set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 - 654 .set CYREG_PRT0_PC0, 0x40005000 - 655 .set CYREG_PRT0_PC1, 0x40005001 - 656 .set CYREG_PRT0_PC2, 0x40005002 - 657 .set CYREG_PRT0_PC3, 0x40005003 - 658 .set CYREG_PRT0_PC4, 0x40005004 - 659 .set CYREG_PRT0_PC5, 0x40005005 - 660 .set CYREG_PRT0_PC6, 0x40005006 - 661 .set CYREG_PRT0_PC7, 0x40005007 - 662 .set CYDEV_IO_PC_PRT1_BASE, 0x40005008 - 663 .set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 - 664 .set CYREG_PRT1_PC0, 0x40005008 - 665 .set CYREG_PRT1_PC1, 0x40005009 - 666 .set CYREG_PRT1_PC2, 0x4000500a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 107 - - - 667 .set CYREG_PRT1_PC3, 0x4000500b - 668 .set CYREG_PRT1_PC4, 0x4000500c - 669 .set CYREG_PRT1_PC5, 0x4000500d - 670 .set CYREG_PRT1_PC6, 0x4000500e - 671 .set CYREG_PRT1_PC7, 0x4000500f - 672 .set CYDEV_IO_PC_PRT2_BASE, 0x40005010 - 673 .set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 - 674 .set CYREG_PRT2_PC0, 0x40005010 - 675 .set CYREG_PRT2_PC1, 0x40005011 - 676 .set CYREG_PRT2_PC2, 0x40005012 - 677 .set CYREG_PRT2_PC3, 0x40005013 - 678 .set CYREG_PRT2_PC4, 0x40005014 - 679 .set CYREG_PRT2_PC5, 0x40005015 - 680 .set CYREG_PRT2_PC6, 0x40005016 - 681 .set CYREG_PRT2_PC7, 0x40005017 - 682 .set CYDEV_IO_PC_PRT3_BASE, 0x40005018 - 683 .set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 - 684 .set CYREG_PRT3_PC0, 0x40005018 - 685 .set CYREG_PRT3_PC1, 0x40005019 - 686 .set CYREG_PRT3_PC2, 0x4000501a - 687 .set CYREG_PRT3_PC3, 0x4000501b - 688 .set CYREG_PRT3_PC4, 0x4000501c - 689 .set CYREG_PRT3_PC5, 0x4000501d - 690 .set CYREG_PRT3_PC6, 0x4000501e - 691 .set CYREG_PRT3_PC7, 0x4000501f - 692 .set CYDEV_IO_PC_PRT4_BASE, 0x40005020 - 693 .set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 - 694 .set CYREG_PRT4_PC0, 0x40005020 - 695 .set CYREG_PRT4_PC1, 0x40005021 - 696 .set CYREG_PRT4_PC2, 0x40005022 - 697 .set CYREG_PRT4_PC3, 0x40005023 - 698 .set CYREG_PRT4_PC4, 0x40005024 - 699 .set CYREG_PRT4_PC5, 0x40005025 - 700 .set CYREG_PRT4_PC6, 0x40005026 - 701 .set CYREG_PRT4_PC7, 0x40005027 - 702 .set CYDEV_IO_PC_PRT5_BASE, 0x40005028 - 703 .set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 - 704 .set CYREG_PRT5_PC0, 0x40005028 - 705 .set CYREG_PRT5_PC1, 0x40005029 - 706 .set CYREG_PRT5_PC2, 0x4000502a - 707 .set CYREG_PRT5_PC3, 0x4000502b - 708 .set CYREG_PRT5_PC4, 0x4000502c - 709 .set CYREG_PRT5_PC5, 0x4000502d - 710 .set CYREG_PRT5_PC6, 0x4000502e - 711 .set CYREG_PRT5_PC7, 0x4000502f - 712 .set CYDEV_IO_PC_PRT6_BASE, 0x40005030 - 713 .set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 - 714 .set CYREG_PRT6_PC0, 0x40005030 - 715 .set CYREG_PRT6_PC1, 0x40005031 - 716 .set CYREG_PRT6_PC2, 0x40005032 - 717 .set CYREG_PRT6_PC3, 0x40005033 - 718 .set CYREG_PRT6_PC4, 0x40005034 - 719 .set CYREG_PRT6_PC5, 0x40005035 - 720 .set CYREG_PRT6_PC6, 0x40005036 - 721 .set CYREG_PRT6_PC7, 0x40005037 - 722 .set CYDEV_IO_PC_PRT12_BASE, 0x40005060 - 723 .set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 108 - - - 724 .set CYREG_PRT12_PC0, 0x40005060 - 725 .set CYREG_PRT12_PC1, 0x40005061 - 726 .set CYREG_PRT12_PC2, 0x40005062 - 727 .set CYREG_PRT12_PC3, 0x40005063 - 728 .set CYREG_PRT12_PC4, 0x40005064 - 729 .set CYREG_PRT12_PC5, 0x40005065 - 730 .set CYREG_PRT12_PC6, 0x40005066 - 731 .set CYREG_PRT12_PC7, 0x40005067 - 732 .set CYDEV_IO_PC_PRT15_BASE, 0x40005078 - 733 .set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 - 734 .set CYREG_IO_PC_PRT15_PC0, 0x40005078 - 735 .set CYREG_IO_PC_PRT15_PC1, 0x40005079 - 736 .set CYREG_IO_PC_PRT15_PC2, 0x4000507a - 737 .set CYREG_IO_PC_PRT15_PC3, 0x4000507b - 738 .set CYREG_IO_PC_PRT15_PC4, 0x4000507c - 739 .set CYREG_IO_PC_PRT15_PC5, 0x4000507d - 740 .set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e - 741 .set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 - 742 .set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e - 743 .set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f - 744 .set CYDEV_IO_DR_BASE, 0x40005080 - 745 .set CYDEV_IO_DR_SIZE, 0x00000010 - 746 .set CYDEV_IO_DR_PRT0_BASE, 0x40005080 - 747 .set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 - 748 .set CYREG_PRT0_DR_ALIAS, 0x40005080 - 749 .set CYDEV_IO_DR_PRT1_BASE, 0x40005081 - 750 .set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 - 751 .set CYREG_PRT1_DR_ALIAS, 0x40005081 - 752 .set CYDEV_IO_DR_PRT2_BASE, 0x40005082 - 753 .set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 - 754 .set CYREG_PRT2_DR_ALIAS, 0x40005082 - 755 .set CYDEV_IO_DR_PRT3_BASE, 0x40005083 - 756 .set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 - 757 .set CYREG_PRT3_DR_ALIAS, 0x40005083 - 758 .set CYDEV_IO_DR_PRT4_BASE, 0x40005084 - 759 .set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 - 760 .set CYREG_PRT4_DR_ALIAS, 0x40005084 - 761 .set CYDEV_IO_DR_PRT5_BASE, 0x40005085 - 762 .set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 - 763 .set CYREG_PRT5_DR_ALIAS, 0x40005085 - 764 .set CYDEV_IO_DR_PRT6_BASE, 0x40005086 - 765 .set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 - 766 .set CYREG_PRT6_DR_ALIAS, 0x40005086 - 767 .set CYDEV_IO_DR_PRT12_BASE, 0x4000508c - 768 .set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 - 769 .set CYREG_PRT12_DR_ALIAS, 0x4000508c - 770 .set CYDEV_IO_DR_PRT15_BASE, 0x4000508f - 771 .set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 - 772 .set CYREG_PRT15_DR_15_ALIAS, 0x4000508f - 773 .set CYDEV_IO_PS_BASE, 0x40005090 - 774 .set CYDEV_IO_PS_SIZE, 0x00000010 - 775 .set CYDEV_IO_PS_PRT0_BASE, 0x40005090 - 776 .set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 - 777 .set CYREG_PRT0_PS_ALIAS, 0x40005090 - 778 .set CYDEV_IO_PS_PRT1_BASE, 0x40005091 - 779 .set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 - 780 .set CYREG_PRT1_PS_ALIAS, 0x40005091 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 109 - - - 781 .set CYDEV_IO_PS_PRT2_BASE, 0x40005092 - 782 .set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 - 783 .set CYREG_PRT2_PS_ALIAS, 0x40005092 - 784 .set CYDEV_IO_PS_PRT3_BASE, 0x40005093 - 785 .set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 - 786 .set CYREG_PRT3_PS_ALIAS, 0x40005093 - 787 .set CYDEV_IO_PS_PRT4_BASE, 0x40005094 - 788 .set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 - 789 .set CYREG_PRT4_PS_ALIAS, 0x40005094 - 790 .set CYDEV_IO_PS_PRT5_BASE, 0x40005095 - 791 .set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 - 792 .set CYREG_PRT5_PS_ALIAS, 0x40005095 - 793 .set CYDEV_IO_PS_PRT6_BASE, 0x40005096 - 794 .set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 - 795 .set CYREG_PRT6_PS_ALIAS, 0x40005096 - 796 .set CYDEV_IO_PS_PRT12_BASE, 0x4000509c - 797 .set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 - 798 .set CYREG_PRT12_PS_ALIAS, 0x4000509c - 799 .set CYDEV_IO_PS_PRT15_BASE, 0x4000509f - 800 .set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 - 801 .set CYREG_PRT15_PS15_ALIAS, 0x4000509f - 802 .set CYDEV_IO_PRT_BASE, 0x40005100 - 803 .set CYDEV_IO_PRT_SIZE, 0x00000100 - 804 .set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 - 805 .set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 - 806 .set CYREG_PRT0_DR, 0x40005100 - 807 .set CYREG_PRT0_PS, 0x40005101 - 808 .set CYREG_PRT0_DM0, 0x40005102 - 809 .set CYREG_PRT0_DM1, 0x40005103 - 810 .set CYREG_PRT0_DM2, 0x40005104 - 811 .set CYREG_PRT0_SLW, 0x40005105 - 812 .set CYREG_PRT0_BYP, 0x40005106 - 813 .set CYREG_PRT0_BIE, 0x40005107 - 814 .set CYREG_PRT0_INP_DIS, 0x40005108 - 815 .set CYREG_PRT0_CTL, 0x40005109 - 816 .set CYREG_PRT0_PRT, 0x4000510a - 817 .set CYREG_PRT0_BIT_MASK, 0x4000510b - 818 .set CYREG_PRT0_AMUX, 0x4000510c - 819 .set CYREG_PRT0_AG, 0x4000510d - 820 .set CYREG_PRT0_LCD_COM_SEG, 0x4000510e - 821 .set CYREG_PRT0_LCD_EN, 0x4000510f - 822 .set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 - 823 .set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 - 824 .set CYREG_PRT1_DR, 0x40005110 - 825 .set CYREG_PRT1_PS, 0x40005111 - 826 .set CYREG_PRT1_DM0, 0x40005112 - 827 .set CYREG_PRT1_DM1, 0x40005113 - 828 .set CYREG_PRT1_DM2, 0x40005114 - 829 .set CYREG_PRT1_SLW, 0x40005115 - 830 .set CYREG_PRT1_BYP, 0x40005116 - 831 .set CYREG_PRT1_BIE, 0x40005117 - 832 .set CYREG_PRT1_INP_DIS, 0x40005118 - 833 .set CYREG_PRT1_CTL, 0x40005119 - 834 .set CYREG_PRT1_PRT, 0x4000511a - 835 .set CYREG_PRT1_BIT_MASK, 0x4000511b - 836 .set CYREG_PRT1_AMUX, 0x4000511c - 837 .set CYREG_PRT1_AG, 0x4000511d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 110 - - - 838 .set CYREG_PRT1_LCD_COM_SEG, 0x4000511e - 839 .set CYREG_PRT1_LCD_EN, 0x4000511f - 840 .set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 - 841 .set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 - 842 .set CYREG_PRT2_DR, 0x40005120 - 843 .set CYREG_PRT2_PS, 0x40005121 - 844 .set CYREG_PRT2_DM0, 0x40005122 - 845 .set CYREG_PRT2_DM1, 0x40005123 - 846 .set CYREG_PRT2_DM2, 0x40005124 - 847 .set CYREG_PRT2_SLW, 0x40005125 - 848 .set CYREG_PRT2_BYP, 0x40005126 - 849 .set CYREG_PRT2_BIE, 0x40005127 - 850 .set CYREG_PRT2_INP_DIS, 0x40005128 - 851 .set CYREG_PRT2_CTL, 0x40005129 - 852 .set CYREG_PRT2_PRT, 0x4000512a - 853 .set CYREG_PRT2_BIT_MASK, 0x4000512b - 854 .set CYREG_PRT2_AMUX, 0x4000512c - 855 .set CYREG_PRT2_AG, 0x4000512d - 856 .set CYREG_PRT2_LCD_COM_SEG, 0x4000512e - 857 .set CYREG_PRT2_LCD_EN, 0x4000512f - 858 .set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 - 859 .set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 - 860 .set CYREG_PRT3_DR, 0x40005130 - 861 .set CYREG_PRT3_PS, 0x40005131 - 862 .set CYREG_PRT3_DM0, 0x40005132 - 863 .set CYREG_PRT3_DM1, 0x40005133 - 864 .set CYREG_PRT3_DM2, 0x40005134 - 865 .set CYREG_PRT3_SLW, 0x40005135 - 866 .set CYREG_PRT3_BYP, 0x40005136 - 867 .set CYREG_PRT3_BIE, 0x40005137 - 868 .set CYREG_PRT3_INP_DIS, 0x40005138 - 869 .set CYREG_PRT3_CTL, 0x40005139 - 870 .set CYREG_PRT3_PRT, 0x4000513a - 871 .set CYREG_PRT3_BIT_MASK, 0x4000513b - 872 .set CYREG_PRT3_AMUX, 0x4000513c - 873 .set CYREG_PRT3_AG, 0x4000513d - 874 .set CYREG_PRT3_LCD_COM_SEG, 0x4000513e - 875 .set CYREG_PRT3_LCD_EN, 0x4000513f - 876 .set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 - 877 .set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 - 878 .set CYREG_PRT4_DR, 0x40005140 - 879 .set CYREG_PRT4_PS, 0x40005141 - 880 .set CYREG_PRT4_DM0, 0x40005142 - 881 .set CYREG_PRT4_DM1, 0x40005143 - 882 .set CYREG_PRT4_DM2, 0x40005144 - 883 .set CYREG_PRT4_SLW, 0x40005145 - 884 .set CYREG_PRT4_BYP, 0x40005146 - 885 .set CYREG_PRT4_BIE, 0x40005147 - 886 .set CYREG_PRT4_INP_DIS, 0x40005148 - 887 .set CYREG_PRT4_CTL, 0x40005149 - 888 .set CYREG_PRT4_PRT, 0x4000514a - 889 .set CYREG_PRT4_BIT_MASK, 0x4000514b - 890 .set CYREG_PRT4_AMUX, 0x4000514c - 891 .set CYREG_PRT4_AG, 0x4000514d - 892 .set CYREG_PRT4_LCD_COM_SEG, 0x4000514e - 893 .set CYREG_PRT4_LCD_EN, 0x4000514f - 894 .set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 111 - - - 895 .set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 - 896 .set CYREG_PRT5_DR, 0x40005150 - 897 .set CYREG_PRT5_PS, 0x40005151 - 898 .set CYREG_PRT5_DM0, 0x40005152 - 899 .set CYREG_PRT5_DM1, 0x40005153 - 900 .set CYREG_PRT5_DM2, 0x40005154 - 901 .set CYREG_PRT5_SLW, 0x40005155 - 902 .set CYREG_PRT5_BYP, 0x40005156 - 903 .set CYREG_PRT5_BIE, 0x40005157 - 904 .set CYREG_PRT5_INP_DIS, 0x40005158 - 905 .set CYREG_PRT5_CTL, 0x40005159 - 906 .set CYREG_PRT5_PRT, 0x4000515a - 907 .set CYREG_PRT5_BIT_MASK, 0x4000515b - 908 .set CYREG_PRT5_AMUX, 0x4000515c - 909 .set CYREG_PRT5_AG, 0x4000515d - 910 .set CYREG_PRT5_LCD_COM_SEG, 0x4000515e - 911 .set CYREG_PRT5_LCD_EN, 0x4000515f - 912 .set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 - 913 .set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 - 914 .set CYREG_PRT6_DR, 0x40005160 - 915 .set CYREG_PRT6_PS, 0x40005161 - 916 .set CYREG_PRT6_DM0, 0x40005162 - 917 .set CYREG_PRT6_DM1, 0x40005163 - 918 .set CYREG_PRT6_DM2, 0x40005164 - 919 .set CYREG_PRT6_SLW, 0x40005165 - 920 .set CYREG_PRT6_BYP, 0x40005166 - 921 .set CYREG_PRT6_BIE, 0x40005167 - 922 .set CYREG_PRT6_INP_DIS, 0x40005168 - 923 .set CYREG_PRT6_CTL, 0x40005169 - 924 .set CYREG_PRT6_PRT, 0x4000516a - 925 .set CYREG_PRT6_BIT_MASK, 0x4000516b - 926 .set CYREG_PRT6_AMUX, 0x4000516c - 927 .set CYREG_PRT6_AG, 0x4000516d - 928 .set CYREG_PRT6_LCD_COM_SEG, 0x4000516e - 929 .set CYREG_PRT6_LCD_EN, 0x4000516f - 930 .set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 - 931 .set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 - 932 .set CYREG_PRT12_DR, 0x400051c0 - 933 .set CYREG_PRT12_PS, 0x400051c1 - 934 .set CYREG_PRT12_DM0, 0x400051c2 - 935 .set CYREG_PRT12_DM1, 0x400051c3 - 936 .set CYREG_PRT12_DM2, 0x400051c4 - 937 .set CYREG_PRT12_SLW, 0x400051c5 - 938 .set CYREG_PRT12_BYP, 0x400051c6 - 939 .set CYREG_PRT12_BIE, 0x400051c7 - 940 .set CYREG_PRT12_INP_DIS, 0x400051c8 - 941 .set CYREG_PRT12_SIO_HYST_EN, 0x400051c9 - 942 .set CYREG_PRT12_PRT, 0x400051ca - 943 .set CYREG_PRT12_BIT_MASK, 0x400051cb - 944 .set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc - 945 .set CYREG_PRT12_AG, 0x400051cd - 946 .set CYREG_PRT12_SIO_CFG, 0x400051ce - 947 .set CYREG_PRT12_SIO_DIFF, 0x400051cf - 948 .set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 - 949 .set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 - 950 .set CYREG_PRT15_DR, 0x400051f0 - 951 .set CYREG_PRT15_PS, 0x400051f1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 112 - - - 952 .set CYREG_PRT15_DM0, 0x400051f2 - 953 .set CYREG_PRT15_DM1, 0x400051f3 - 954 .set CYREG_PRT15_DM2, 0x400051f4 - 955 .set CYREG_PRT15_SLW, 0x400051f5 - 956 .set CYREG_PRT15_BYP, 0x400051f6 - 957 .set CYREG_PRT15_BIE, 0x400051f7 - 958 .set CYREG_PRT15_INP_DIS, 0x400051f8 - 959 .set CYREG_PRT15_CTL, 0x400051f9 - 960 .set CYREG_PRT15_PRT, 0x400051fa - 961 .set CYREG_PRT15_BIT_MASK, 0x400051fb - 962 .set CYREG_PRT15_AMUX, 0x400051fc - 963 .set CYREG_PRT15_AG, 0x400051fd - 964 .set CYREG_PRT15_LCD_COM_SEG, 0x400051fe - 965 .set CYREG_PRT15_LCD_EN, 0x400051ff - 966 .set CYDEV_PRTDSI_BASE, 0x40005200 - 967 .set CYDEV_PRTDSI_SIZE, 0x0000007f - 968 .set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 - 969 .set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 - 970 .set CYREG_PRT0_OUT_SEL0, 0x40005200 - 971 .set CYREG_PRT0_OUT_SEL1, 0x40005201 - 972 .set CYREG_PRT0_OE_SEL0, 0x40005202 - 973 .set CYREG_PRT0_OE_SEL1, 0x40005203 - 974 .set CYREG_PRT0_DBL_SYNC_IN, 0x40005204 - 975 .set CYREG_PRT0_SYNC_OUT, 0x40005205 - 976 .set CYREG_PRT0_CAPS_SEL, 0x40005206 - 977 .set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 - 978 .set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 - 979 .set CYREG_PRT1_OUT_SEL0, 0x40005208 - 980 .set CYREG_PRT1_OUT_SEL1, 0x40005209 - 981 .set CYREG_PRT1_OE_SEL0, 0x4000520a - 982 .set CYREG_PRT1_OE_SEL1, 0x4000520b - 983 .set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c - 984 .set CYREG_PRT1_SYNC_OUT, 0x4000520d - 985 .set CYREG_PRT1_CAPS_SEL, 0x4000520e - 986 .set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 - 987 .set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 - 988 .set CYREG_PRT2_OUT_SEL0, 0x40005210 - 989 .set CYREG_PRT2_OUT_SEL1, 0x40005211 - 990 .set CYREG_PRT2_OE_SEL0, 0x40005212 - 991 .set CYREG_PRT2_OE_SEL1, 0x40005213 - 992 .set CYREG_PRT2_DBL_SYNC_IN, 0x40005214 - 993 .set CYREG_PRT2_SYNC_OUT, 0x40005215 - 994 .set CYREG_PRT2_CAPS_SEL, 0x40005216 - 995 .set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 - 996 .set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 - 997 .set CYREG_PRT3_OUT_SEL0, 0x40005218 - 998 .set CYREG_PRT3_OUT_SEL1, 0x40005219 - 999 .set CYREG_PRT3_OE_SEL0, 0x4000521a - 1000 .set CYREG_PRT3_OE_SEL1, 0x4000521b - 1001 .set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c - 1002 .set CYREG_PRT3_SYNC_OUT, 0x4000521d - 1003 .set CYREG_PRT3_CAPS_SEL, 0x4000521e - 1004 .set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 - 1005 .set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 - 1006 .set CYREG_PRT4_OUT_SEL0, 0x40005220 - 1007 .set CYREG_PRT4_OUT_SEL1, 0x40005221 - 1008 .set CYREG_PRT4_OE_SEL0, 0x40005222 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 113 - - - 1009 .set CYREG_PRT4_OE_SEL1, 0x40005223 - 1010 .set CYREG_PRT4_DBL_SYNC_IN, 0x40005224 - 1011 .set CYREG_PRT4_SYNC_OUT, 0x40005225 - 1012 .set CYREG_PRT4_CAPS_SEL, 0x40005226 - 1013 .set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 - 1014 .set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 - 1015 .set CYREG_PRT5_OUT_SEL0, 0x40005228 - 1016 .set CYREG_PRT5_OUT_SEL1, 0x40005229 - 1017 .set CYREG_PRT5_OE_SEL0, 0x4000522a - 1018 .set CYREG_PRT5_OE_SEL1, 0x4000522b - 1019 .set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c - 1020 .set CYREG_PRT5_SYNC_OUT, 0x4000522d - 1021 .set CYREG_PRT5_CAPS_SEL, 0x4000522e - 1022 .set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 - 1023 .set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 - 1024 .set CYREG_PRT6_OUT_SEL0, 0x40005230 - 1025 .set CYREG_PRT6_OUT_SEL1, 0x40005231 - 1026 .set CYREG_PRT6_OE_SEL0, 0x40005232 - 1027 .set CYREG_PRT6_OE_SEL1, 0x40005233 - 1028 .set CYREG_PRT6_DBL_SYNC_IN, 0x40005234 - 1029 .set CYREG_PRT6_SYNC_OUT, 0x40005235 - 1030 .set CYREG_PRT6_CAPS_SEL, 0x40005236 - 1031 .set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 - 1032 .set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 - 1033 .set CYREG_PRT12_OUT_SEL0, 0x40005260 - 1034 .set CYREG_PRT12_OUT_SEL1, 0x40005261 - 1035 .set CYREG_PRT12_OE_SEL0, 0x40005262 - 1036 .set CYREG_PRT12_OE_SEL1, 0x40005263 - 1037 .set CYREG_PRT12_DBL_SYNC_IN, 0x40005264 - 1038 .set CYREG_PRT12_SYNC_OUT, 0x40005265 - 1039 .set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 - 1040 .set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 - 1041 .set CYREG_PRT15_OUT_SEL0, 0x40005278 - 1042 .set CYREG_PRT15_OUT_SEL1, 0x40005279 - 1043 .set CYREG_PRT15_OE_SEL0, 0x4000527a - 1044 .set CYREG_PRT15_OE_SEL1, 0x4000527b - 1045 .set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c - 1046 .set CYREG_PRT15_SYNC_OUT, 0x4000527d - 1047 .set CYREG_PRT15_CAPS_SEL, 0x4000527e - 1048 .set CYDEV_EMIF_BASE, 0x40005400 - 1049 .set CYDEV_EMIF_SIZE, 0x00000007 - 1050 .set CYREG_EMIF_NO_UDB, 0x40005400 - 1051 .set CYREG_EMIF_RP_WAIT_STATES, 0x40005401 - 1052 .set CYREG_EMIF_MEM_DWN, 0x40005402 - 1053 .set CYREG_EMIF_MEMCLK_DIV, 0x40005403 - 1054 .set CYREG_EMIF_CLOCK_EN, 0x40005404 - 1055 .set CYREG_EMIF_EM_TYPE, 0x40005405 - 1056 .set CYREG_EMIF_WP_WAIT_STATES, 0x40005406 - 1057 .set CYDEV_ANAIF_BASE, 0x40005800 - 1058 .set CYDEV_ANAIF_SIZE, 0x000003a9 - 1059 .set CYDEV_ANAIF_CFG_BASE, 0x40005800 - 1060 .set CYDEV_ANAIF_CFG_SIZE, 0x0000010f - 1061 .set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 - 1062 .set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 - 1063 .set CYREG_SC0_CR0, 0x40005800 - 1064 .set CYREG_SC0_CR1, 0x40005801 - 1065 .set CYREG_SC0_CR2, 0x40005802 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 114 - - - 1066 .set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 - 1067 .set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 - 1068 .set CYREG_SC1_CR0, 0x40005804 - 1069 .set CYREG_SC1_CR1, 0x40005805 - 1070 .set CYREG_SC1_CR2, 0x40005806 - 1071 .set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 - 1072 .set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 - 1073 .set CYREG_SC2_CR0, 0x40005808 - 1074 .set CYREG_SC2_CR1, 0x40005809 - 1075 .set CYREG_SC2_CR2, 0x4000580a - 1076 .set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c - 1077 .set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 - 1078 .set CYREG_SC3_CR0, 0x4000580c - 1079 .set CYREG_SC3_CR1, 0x4000580d - 1080 .set CYREG_SC3_CR2, 0x4000580e - 1081 .set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 - 1082 .set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 - 1083 .set CYREG_DAC0_CR0, 0x40005820 - 1084 .set CYREG_DAC0_CR1, 0x40005821 - 1085 .set CYREG_DAC0_TST, 0x40005822 - 1086 .set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 - 1087 .set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 - 1088 .set CYREG_DAC1_CR0, 0x40005824 - 1089 .set CYREG_DAC1_CR1, 0x40005825 - 1090 .set CYREG_DAC1_TST, 0x40005826 - 1091 .set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 - 1092 .set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 - 1093 .set CYREG_DAC2_CR0, 0x40005828 - 1094 .set CYREG_DAC2_CR1, 0x40005829 - 1095 .set CYREG_DAC2_TST, 0x4000582a - 1096 .set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c - 1097 .set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 - 1098 .set CYREG_DAC3_CR0, 0x4000582c - 1099 .set CYREG_DAC3_CR1, 0x4000582d - 1100 .set CYREG_DAC3_TST, 0x4000582e - 1101 .set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 - 1102 .set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 - 1103 .set CYREG_CMP0_CR, 0x40005840 - 1104 .set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 - 1105 .set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 - 1106 .set CYREG_CMP1_CR, 0x40005841 - 1107 .set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 - 1108 .set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 - 1109 .set CYREG_CMP2_CR, 0x40005842 - 1110 .set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 - 1111 .set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 - 1112 .set CYREG_CMP3_CR, 0x40005843 - 1113 .set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 - 1114 .set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 - 1115 .set CYREG_LUT0_CR, 0x40005848 - 1116 .set CYREG_LUT0_MX, 0x40005849 - 1117 .set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a - 1118 .set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 - 1119 .set CYREG_LUT1_CR, 0x4000584a - 1120 .set CYREG_LUT1_MX, 0x4000584b - 1121 .set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c - 1122 .set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 115 - - - 1123 .set CYREG_LUT2_CR, 0x4000584c - 1124 .set CYREG_LUT2_MX, 0x4000584d - 1125 .set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e - 1126 .set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 - 1127 .set CYREG_LUT3_CR, 0x4000584e - 1128 .set CYREG_LUT3_MX, 0x4000584f - 1129 .set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 - 1130 .set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 - 1131 .set CYREG_OPAMP0_CR, 0x40005858 - 1132 .set CYREG_OPAMP0_RSVD, 0x40005859 - 1133 .set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a - 1134 .set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 - 1135 .set CYREG_OPAMP1_CR, 0x4000585a - 1136 .set CYREG_OPAMP1_RSVD, 0x4000585b - 1137 .set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c - 1138 .set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 - 1139 .set CYREG_OPAMP2_CR, 0x4000585c - 1140 .set CYREG_OPAMP2_RSVD, 0x4000585d - 1141 .set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e - 1142 .set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 - 1143 .set CYREG_OPAMP3_CR, 0x4000585e - 1144 .set CYREG_OPAMP3_RSVD, 0x4000585f - 1145 .set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 - 1146 .set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 - 1147 .set CYREG_LCDDAC_CR0, 0x40005868 - 1148 .set CYREG_LCDDAC_CR1, 0x40005869 - 1149 .set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a - 1150 .set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 - 1151 .set CYREG_LCDDRV_CR, 0x4000586a - 1152 .set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b - 1153 .set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 - 1154 .set CYREG_LCDTMR_CFG, 0x4000586b - 1155 .set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c - 1156 .set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 - 1157 .set CYREG_BG_CR0, 0x4000586c - 1158 .set CYREG_BG_RSVD, 0x4000586d - 1159 .set CYREG_BG_DFT0, 0x4000586e - 1160 .set CYREG_BG_DFT1, 0x4000586f - 1161 .set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 - 1162 .set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 - 1163 .set CYREG_CAPSL_CFG0, 0x40005870 - 1164 .set CYREG_CAPSL_CFG1, 0x40005871 - 1165 .set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 - 1166 .set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 - 1167 .set CYREG_CAPSR_CFG0, 0x40005872 - 1168 .set CYREG_CAPSR_CFG1, 0x40005873 - 1169 .set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 - 1170 .set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 - 1171 .set CYREG_PUMP_CR0, 0x40005876 - 1172 .set CYREG_PUMP_CR1, 0x40005877 - 1173 .set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 - 1174 .set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 - 1175 .set CYREG_LPF0_CR0, 0x40005878 - 1176 .set CYREG_LPF0_RSVD, 0x40005879 - 1177 .set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a - 1178 .set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 - 1179 .set CYREG_LPF1_CR0, 0x4000587a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 116 - - - 1180 .set CYREG_LPF1_RSVD, 0x4000587b - 1181 .set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c - 1182 .set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 - 1183 .set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c - 1184 .set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 - 1185 .set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 - 1186 .set CYREG_DSM0_CR0, 0x40005880 - 1187 .set CYREG_DSM0_CR1, 0x40005881 - 1188 .set CYREG_DSM0_CR2, 0x40005882 - 1189 .set CYREG_DSM0_CR3, 0x40005883 - 1190 .set CYREG_DSM0_CR4, 0x40005884 - 1191 .set CYREG_DSM0_CR5, 0x40005885 - 1192 .set CYREG_DSM0_CR6, 0x40005886 - 1193 .set CYREG_DSM0_CR7, 0x40005887 - 1194 .set CYREG_DSM0_CR8, 0x40005888 - 1195 .set CYREG_DSM0_CR9, 0x40005889 - 1196 .set CYREG_DSM0_CR10, 0x4000588a - 1197 .set CYREG_DSM0_CR11, 0x4000588b - 1198 .set CYREG_DSM0_CR12, 0x4000588c - 1199 .set CYREG_DSM0_CR13, 0x4000588d - 1200 .set CYREG_DSM0_CR14, 0x4000588e - 1201 .set CYREG_DSM0_CR15, 0x4000588f - 1202 .set CYREG_DSM0_CR16, 0x40005890 - 1203 .set CYREG_DSM0_CR17, 0x40005891 - 1204 .set CYREG_DSM0_REF0, 0x40005892 - 1205 .set CYREG_DSM0_REF1, 0x40005893 - 1206 .set CYREG_DSM0_REF2, 0x40005894 - 1207 .set CYREG_DSM0_REF3, 0x40005895 - 1208 .set CYREG_DSM0_DEM0, 0x40005896 - 1209 .set CYREG_DSM0_DEM1, 0x40005897 - 1210 .set CYREG_DSM0_TST0, 0x40005898 - 1211 .set CYREG_DSM0_TST1, 0x40005899 - 1212 .set CYREG_DSM0_BUF0, 0x4000589a - 1213 .set CYREG_DSM0_BUF1, 0x4000589b - 1214 .set CYREG_DSM0_BUF2, 0x4000589c - 1215 .set CYREG_DSM0_BUF3, 0x4000589d - 1216 .set CYREG_DSM0_MISC, 0x4000589e - 1217 .set CYREG_DSM0_RSVD1, 0x4000589f - 1218 .set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 - 1219 .set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 - 1220 .set CYREG_SAR0_CSR0, 0x40005900 - 1221 .set CYREG_SAR0_CSR1, 0x40005901 - 1222 .set CYREG_SAR0_CSR2, 0x40005902 - 1223 .set CYREG_SAR0_CSR3, 0x40005903 - 1224 .set CYREG_SAR0_CSR4, 0x40005904 - 1225 .set CYREG_SAR0_CSR5, 0x40005905 - 1226 .set CYREG_SAR0_CSR6, 0x40005906 - 1227 .set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 - 1228 .set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 - 1229 .set CYREG_SAR1_CSR0, 0x40005908 - 1230 .set CYREG_SAR1_CSR1, 0x40005909 - 1231 .set CYREG_SAR1_CSR2, 0x4000590a - 1232 .set CYREG_SAR1_CSR3, 0x4000590b - 1233 .set CYREG_SAR1_CSR4, 0x4000590c - 1234 .set CYREG_SAR1_CSR5, 0x4000590d - 1235 .set CYREG_SAR1_CSR6, 0x4000590e - 1236 .set CYDEV_ANAIF_RT_BASE, 0x40005a00 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 117 - - - 1237 .set CYDEV_ANAIF_RT_SIZE, 0x00000162 - 1238 .set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 - 1239 .set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d - 1240 .set CYREG_SC0_SW0, 0x40005a00 - 1241 .set CYREG_SC0_SW2, 0x40005a02 - 1242 .set CYREG_SC0_SW3, 0x40005a03 - 1243 .set CYREG_SC0_SW4, 0x40005a04 - 1244 .set CYREG_SC0_SW6, 0x40005a06 - 1245 .set CYREG_SC0_SW7, 0x40005a07 - 1246 .set CYREG_SC0_SW8, 0x40005a08 - 1247 .set CYREG_SC0_SW10, 0x40005a0a - 1248 .set CYREG_SC0_CLK, 0x40005a0b - 1249 .set CYREG_SC0_BST, 0x40005a0c - 1250 .set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 - 1251 .set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d - 1252 .set CYREG_SC1_SW0, 0x40005a10 - 1253 .set CYREG_SC1_SW2, 0x40005a12 - 1254 .set CYREG_SC1_SW3, 0x40005a13 - 1255 .set CYREG_SC1_SW4, 0x40005a14 - 1256 .set CYREG_SC1_SW6, 0x40005a16 - 1257 .set CYREG_SC1_SW7, 0x40005a17 - 1258 .set CYREG_SC1_SW8, 0x40005a18 - 1259 .set CYREG_SC1_SW10, 0x40005a1a - 1260 .set CYREG_SC1_CLK, 0x40005a1b - 1261 .set CYREG_SC1_BST, 0x40005a1c - 1262 .set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 - 1263 .set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d - 1264 .set CYREG_SC2_SW0, 0x40005a20 - 1265 .set CYREG_SC2_SW2, 0x40005a22 - 1266 .set CYREG_SC2_SW3, 0x40005a23 - 1267 .set CYREG_SC2_SW4, 0x40005a24 - 1268 .set CYREG_SC2_SW6, 0x40005a26 - 1269 .set CYREG_SC2_SW7, 0x40005a27 - 1270 .set CYREG_SC2_SW8, 0x40005a28 - 1271 .set CYREG_SC2_SW10, 0x40005a2a - 1272 .set CYREG_SC2_CLK, 0x40005a2b - 1273 .set CYREG_SC2_BST, 0x40005a2c - 1274 .set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 - 1275 .set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d - 1276 .set CYREG_SC3_SW0, 0x40005a30 - 1277 .set CYREG_SC3_SW2, 0x40005a32 - 1278 .set CYREG_SC3_SW3, 0x40005a33 - 1279 .set CYREG_SC3_SW4, 0x40005a34 - 1280 .set CYREG_SC3_SW6, 0x40005a36 - 1281 .set CYREG_SC3_SW7, 0x40005a37 - 1282 .set CYREG_SC3_SW8, 0x40005a38 - 1283 .set CYREG_SC3_SW10, 0x40005a3a - 1284 .set CYREG_SC3_CLK, 0x40005a3b - 1285 .set CYREG_SC3_BST, 0x40005a3c - 1286 .set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 - 1287 .set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 - 1288 .set CYREG_DAC0_SW0, 0x40005a80 - 1289 .set CYREG_DAC0_SW2, 0x40005a82 - 1290 .set CYREG_DAC0_SW3, 0x40005a83 - 1291 .set CYREG_DAC0_SW4, 0x40005a84 - 1292 .set CYREG_DAC0_STROBE, 0x40005a87 - 1293 .set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 118 - - - 1294 .set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 - 1295 .set CYREG_DAC1_SW0, 0x40005a88 - 1296 .set CYREG_DAC1_SW2, 0x40005a8a - 1297 .set CYREG_DAC1_SW3, 0x40005a8b - 1298 .set CYREG_DAC1_SW4, 0x40005a8c - 1299 .set CYREG_DAC1_STROBE, 0x40005a8f - 1300 .set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 - 1301 .set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 - 1302 .set CYREG_DAC2_SW0, 0x40005a90 - 1303 .set CYREG_DAC2_SW2, 0x40005a92 - 1304 .set CYREG_DAC2_SW3, 0x40005a93 - 1305 .set CYREG_DAC2_SW4, 0x40005a94 - 1306 .set CYREG_DAC2_STROBE, 0x40005a97 - 1307 .set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 - 1308 .set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 - 1309 .set CYREG_DAC3_SW0, 0x40005a98 - 1310 .set CYREG_DAC3_SW2, 0x40005a9a - 1311 .set CYREG_DAC3_SW3, 0x40005a9b - 1312 .set CYREG_DAC3_SW4, 0x40005a9c - 1313 .set CYREG_DAC3_STROBE, 0x40005a9f - 1314 .set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 - 1315 .set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 - 1316 .set CYREG_CMP0_SW0, 0x40005ac0 - 1317 .set CYREG_CMP0_SW2, 0x40005ac2 - 1318 .set CYREG_CMP0_SW3, 0x40005ac3 - 1319 .set CYREG_CMP0_SW4, 0x40005ac4 - 1320 .set CYREG_CMP0_SW6, 0x40005ac6 - 1321 .set CYREG_CMP0_CLK, 0x40005ac7 - 1322 .set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 - 1323 .set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 - 1324 .set CYREG_CMP1_SW0, 0x40005ac8 - 1325 .set CYREG_CMP1_SW2, 0x40005aca - 1326 .set CYREG_CMP1_SW3, 0x40005acb - 1327 .set CYREG_CMP1_SW4, 0x40005acc - 1328 .set CYREG_CMP1_SW6, 0x40005ace - 1329 .set CYREG_CMP1_CLK, 0x40005acf - 1330 .set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 - 1331 .set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 - 1332 .set CYREG_CMP2_SW0, 0x40005ad0 - 1333 .set CYREG_CMP2_SW2, 0x40005ad2 - 1334 .set CYREG_CMP2_SW3, 0x40005ad3 - 1335 .set CYREG_CMP2_SW4, 0x40005ad4 - 1336 .set CYREG_CMP2_SW6, 0x40005ad6 - 1337 .set CYREG_CMP2_CLK, 0x40005ad7 - 1338 .set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 - 1339 .set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 - 1340 .set CYREG_CMP3_SW0, 0x40005ad8 - 1341 .set CYREG_CMP3_SW2, 0x40005ada - 1342 .set CYREG_CMP3_SW3, 0x40005adb - 1343 .set CYREG_CMP3_SW4, 0x40005adc - 1344 .set CYREG_CMP3_SW6, 0x40005ade - 1345 .set CYREG_CMP3_CLK, 0x40005adf - 1346 .set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 - 1347 .set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 - 1348 .set CYREG_DSM0_SW0, 0x40005b00 - 1349 .set CYREG_DSM0_SW2, 0x40005b02 - 1350 .set CYREG_DSM0_SW3, 0x40005b03 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 119 - - - 1351 .set CYREG_DSM0_SW4, 0x40005b04 - 1352 .set CYREG_DSM0_SW6, 0x40005b06 - 1353 .set CYREG_DSM0_CLK, 0x40005b07 - 1354 .set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 - 1355 .set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 - 1356 .set CYREG_SAR0_SW0, 0x40005b20 - 1357 .set CYREG_SAR0_SW2, 0x40005b22 - 1358 .set CYREG_SAR0_SW3, 0x40005b23 - 1359 .set CYREG_SAR0_SW4, 0x40005b24 - 1360 .set CYREG_SAR0_SW6, 0x40005b26 - 1361 .set CYREG_SAR0_CLK, 0x40005b27 - 1362 .set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 - 1363 .set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 - 1364 .set CYREG_SAR1_SW0, 0x40005b28 - 1365 .set CYREG_SAR1_SW2, 0x40005b2a - 1366 .set CYREG_SAR1_SW3, 0x40005b2b - 1367 .set CYREG_SAR1_SW4, 0x40005b2c - 1368 .set CYREG_SAR1_SW6, 0x40005b2e - 1369 .set CYREG_SAR1_CLK, 0x40005b2f - 1370 .set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 - 1371 .set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 - 1372 .set CYREG_OPAMP0_MX, 0x40005b40 - 1373 .set CYREG_OPAMP0_SW, 0x40005b41 - 1374 .set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 - 1375 .set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 - 1376 .set CYREG_OPAMP1_MX, 0x40005b42 - 1377 .set CYREG_OPAMP1_SW, 0x40005b43 - 1378 .set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 - 1379 .set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 - 1380 .set CYREG_OPAMP2_MX, 0x40005b44 - 1381 .set CYREG_OPAMP2_SW, 0x40005b45 - 1382 .set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 - 1383 .set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 - 1384 .set CYREG_OPAMP3_MX, 0x40005b46 - 1385 .set CYREG_OPAMP3_SW, 0x40005b47 - 1386 .set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 - 1387 .set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 - 1388 .set CYREG_LCDDAC_SW0, 0x40005b50 - 1389 .set CYREG_LCDDAC_SW1, 0x40005b51 - 1390 .set CYREG_LCDDAC_SW2, 0x40005b52 - 1391 .set CYREG_LCDDAC_SW3, 0x40005b53 - 1392 .set CYREG_LCDDAC_SW4, 0x40005b54 - 1393 .set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 - 1394 .set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 - 1395 .set CYREG_SC_MISC, 0x40005b56 - 1396 .set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 - 1397 .set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 - 1398 .set CYREG_BUS_SW0, 0x40005b58 - 1399 .set CYREG_BUS_SW2, 0x40005b5a - 1400 .set CYREG_BUS_SW3, 0x40005b5b - 1401 .set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c - 1402 .set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 - 1403 .set CYREG_DFT_CR0, 0x40005b5c - 1404 .set CYREG_DFT_CR1, 0x40005b5d - 1405 .set CYREG_DFT_CR2, 0x40005b5e - 1406 .set CYREG_DFT_CR3, 0x40005b5f - 1407 .set CYREG_DFT_CR4, 0x40005b60 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 120 - - - 1408 .set CYREG_DFT_CR5, 0x40005b61 - 1409 .set CYDEV_ANAIF_WRK_BASE, 0x40005b80 - 1410 .set CYDEV_ANAIF_WRK_SIZE, 0x00000029 - 1411 .set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 - 1412 .set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 - 1413 .set CYREG_DAC0_D, 0x40005b80 - 1414 .set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 - 1415 .set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 - 1416 .set CYREG_DAC1_D, 0x40005b81 - 1417 .set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 - 1418 .set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 - 1419 .set CYREG_DAC2_D, 0x40005b82 - 1420 .set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 - 1421 .set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 - 1422 .set CYREG_DAC3_D, 0x40005b83 - 1423 .set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 - 1424 .set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 - 1425 .set CYREG_DSM0_OUT0, 0x40005b88 - 1426 .set CYREG_DSM0_OUT1, 0x40005b89 - 1427 .set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 - 1428 .set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 - 1429 .set CYREG_LUT_SR, 0x40005b90 - 1430 .set CYREG_LUT_WRK1, 0x40005b91 - 1431 .set CYREG_LUT_MSK, 0x40005b92 - 1432 .set CYREG_LUT_CLK, 0x40005b93 - 1433 .set CYREG_LUT_CPTR, 0x40005b94 - 1434 .set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 - 1435 .set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 - 1436 .set CYREG_CMP_WRK, 0x40005b96 - 1437 .set CYREG_CMP_TST, 0x40005b97 - 1438 .set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 - 1439 .set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 - 1440 .set CYREG_SC_SR, 0x40005b98 - 1441 .set CYREG_SC_WRK1, 0x40005b99 - 1442 .set CYREG_SC_MSK, 0x40005b9a - 1443 .set CYREG_SC_CMPINV, 0x40005b9b - 1444 .set CYREG_SC_CPTR, 0x40005b9c - 1445 .set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 - 1446 .set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 - 1447 .set CYREG_SAR0_WRK0, 0x40005ba0 - 1448 .set CYREG_SAR0_WRK1, 0x40005ba1 - 1449 .set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 - 1450 .set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 - 1451 .set CYREG_SAR1_WRK0, 0x40005ba2 - 1452 .set CYREG_SAR1_WRK1, 0x40005ba3 - 1453 .set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 - 1454 .set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 - 1455 .set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8 - 1456 .set CYDEV_USB_BASE, 0x40006000 - 1457 .set CYDEV_USB_SIZE, 0x00000300 - 1458 .set CYREG_USB_EP0_DR0, 0x40006000 - 1459 .set CYREG_USB_EP0_DR1, 0x40006001 - 1460 .set CYREG_USB_EP0_DR2, 0x40006002 - 1461 .set CYREG_USB_EP0_DR3, 0x40006003 - 1462 .set CYREG_USB_EP0_DR4, 0x40006004 - 1463 .set CYREG_USB_EP0_DR5, 0x40006005 - 1464 .set CYREG_USB_EP0_DR6, 0x40006006 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 121 - - - 1465 .set CYREG_USB_EP0_DR7, 0x40006007 - 1466 .set CYREG_USB_CR0, 0x40006008 - 1467 .set CYREG_USB_CR1, 0x40006009 - 1468 .set CYREG_USB_SIE_EP_INT_EN, 0x4000600a - 1469 .set CYREG_USB_SIE_EP_INT_SR, 0x4000600b - 1470 .set CYDEV_USB_SIE_EP1_BASE, 0x4000600c - 1471 .set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 - 1472 .set CYREG_USB_SIE_EP1_CNT0, 0x4000600c - 1473 .set CYREG_USB_SIE_EP1_CNT1, 0x4000600d - 1474 .set CYREG_USB_SIE_EP1_CR0, 0x4000600e - 1475 .set CYREG_USB_USBIO_CR0, 0x40006010 - 1476 .set CYREG_USB_USBIO_CR1, 0x40006012 - 1477 .set CYREG_USB_DYN_RECONFIG, 0x40006014 - 1478 .set CYREG_USB_SOF0, 0x40006018 - 1479 .set CYREG_USB_SOF1, 0x40006019 - 1480 .set CYDEV_USB_SIE_EP2_BASE, 0x4000601c - 1481 .set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 - 1482 .set CYREG_USB_SIE_EP2_CNT0, 0x4000601c - 1483 .set CYREG_USB_SIE_EP2_CNT1, 0x4000601d - 1484 .set CYREG_USB_SIE_EP2_CR0, 0x4000601e - 1485 .set CYREG_USB_EP0_CR, 0x40006028 - 1486 .set CYREG_USB_EP0_CNT, 0x40006029 - 1487 .set CYDEV_USB_SIE_EP3_BASE, 0x4000602c - 1488 .set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 - 1489 .set CYREG_USB_SIE_EP3_CNT0, 0x4000602c - 1490 .set CYREG_USB_SIE_EP3_CNT1, 0x4000602d - 1491 .set CYREG_USB_SIE_EP3_CR0, 0x4000602e - 1492 .set CYDEV_USB_SIE_EP4_BASE, 0x4000603c - 1493 .set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 - 1494 .set CYREG_USB_SIE_EP4_CNT0, 0x4000603c - 1495 .set CYREG_USB_SIE_EP4_CNT1, 0x4000603d - 1496 .set CYREG_USB_SIE_EP4_CR0, 0x4000603e - 1497 .set CYDEV_USB_SIE_EP5_BASE, 0x4000604c - 1498 .set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 - 1499 .set CYREG_USB_SIE_EP5_CNT0, 0x4000604c - 1500 .set CYREG_USB_SIE_EP5_CNT1, 0x4000604d - 1501 .set CYREG_USB_SIE_EP5_CR0, 0x4000604e - 1502 .set CYDEV_USB_SIE_EP6_BASE, 0x4000605c - 1503 .set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 - 1504 .set CYREG_USB_SIE_EP6_CNT0, 0x4000605c - 1505 .set CYREG_USB_SIE_EP6_CNT1, 0x4000605d - 1506 .set CYREG_USB_SIE_EP6_CR0, 0x4000605e - 1507 .set CYDEV_USB_SIE_EP7_BASE, 0x4000606c - 1508 .set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 - 1509 .set CYREG_USB_SIE_EP7_CNT0, 0x4000606c - 1510 .set CYREG_USB_SIE_EP7_CNT1, 0x4000606d - 1511 .set CYREG_USB_SIE_EP7_CR0, 0x4000606e - 1512 .set CYDEV_USB_SIE_EP8_BASE, 0x4000607c - 1513 .set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 - 1514 .set CYREG_USB_SIE_EP8_CNT0, 0x4000607c - 1515 .set CYREG_USB_SIE_EP8_CNT1, 0x4000607d - 1516 .set CYREG_USB_SIE_EP8_CR0, 0x4000607e - 1517 .set CYDEV_USB_ARB_EP1_BASE, 0x40006080 - 1518 .set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 - 1519 .set CYREG_USB_ARB_EP1_CFG, 0x40006080 - 1520 .set CYREG_USB_ARB_EP1_INT_EN, 0x40006081 - 1521 .set CYREG_USB_ARB_EP1_SR, 0x40006082 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 122 - - - 1522 .set CYDEV_USB_ARB_RW1_BASE, 0x40006084 - 1523 .set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 - 1524 .set CYREG_USB_ARB_RW1_WA, 0x40006084 - 1525 .set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085 - 1526 .set CYREG_USB_ARB_RW1_RA, 0x40006086 - 1527 .set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087 - 1528 .set CYREG_USB_ARB_RW1_DR, 0x40006088 - 1529 .set CYREG_USB_BUF_SIZE, 0x4000608c - 1530 .set CYREG_USB_EP_ACTIVE, 0x4000608e - 1531 .set CYREG_USB_EP_TYPE, 0x4000608f - 1532 .set CYDEV_USB_ARB_EP2_BASE, 0x40006090 - 1533 .set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 - 1534 .set CYREG_USB_ARB_EP2_CFG, 0x40006090 - 1535 .set CYREG_USB_ARB_EP2_INT_EN, 0x40006091 - 1536 .set CYREG_USB_ARB_EP2_SR, 0x40006092 - 1537 .set CYDEV_USB_ARB_RW2_BASE, 0x40006094 - 1538 .set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 - 1539 .set CYREG_USB_ARB_RW2_WA, 0x40006094 - 1540 .set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095 - 1541 .set CYREG_USB_ARB_RW2_RA, 0x40006096 - 1542 .set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097 - 1543 .set CYREG_USB_ARB_RW2_DR, 0x40006098 - 1544 .set CYREG_USB_ARB_CFG, 0x4000609c - 1545 .set CYREG_USB_USB_CLK_EN, 0x4000609d - 1546 .set CYREG_USB_ARB_INT_EN, 0x4000609e - 1547 .set CYREG_USB_ARB_INT_SR, 0x4000609f - 1548 .set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 - 1549 .set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 - 1550 .set CYREG_USB_ARB_EP3_CFG, 0x400060a0 - 1551 .set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1 - 1552 .set CYREG_USB_ARB_EP3_SR, 0x400060a2 - 1553 .set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 - 1554 .set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 - 1555 .set CYREG_USB_ARB_RW3_WA, 0x400060a4 - 1556 .set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5 - 1557 .set CYREG_USB_ARB_RW3_RA, 0x400060a6 - 1558 .set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7 - 1559 .set CYREG_USB_ARB_RW3_DR, 0x400060a8 - 1560 .set CYREG_USB_CWA, 0x400060ac - 1561 .set CYREG_USB_CWA_MSB, 0x400060ad - 1562 .set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 - 1563 .set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 - 1564 .set CYREG_USB_ARB_EP4_CFG, 0x400060b0 - 1565 .set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1 - 1566 .set CYREG_USB_ARB_EP4_SR, 0x400060b2 - 1567 .set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 - 1568 .set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 - 1569 .set CYREG_USB_ARB_RW4_WA, 0x400060b4 - 1570 .set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5 - 1571 .set CYREG_USB_ARB_RW4_RA, 0x400060b6 - 1572 .set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7 - 1573 .set CYREG_USB_ARB_RW4_DR, 0x400060b8 - 1574 .set CYREG_USB_DMA_THRES, 0x400060bc - 1575 .set CYREG_USB_DMA_THRES_MSB, 0x400060bd - 1576 .set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 - 1577 .set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 - 1578 .set CYREG_USB_ARB_EP5_CFG, 0x400060c0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 123 - - - 1579 .set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1 - 1580 .set CYREG_USB_ARB_EP5_SR, 0x400060c2 - 1581 .set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 - 1582 .set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 - 1583 .set CYREG_USB_ARB_RW5_WA, 0x400060c4 - 1584 .set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5 - 1585 .set CYREG_USB_ARB_RW5_RA, 0x400060c6 - 1586 .set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7 - 1587 .set CYREG_USB_ARB_RW5_DR, 0x400060c8 - 1588 .set CYREG_USB_BUS_RST_CNT, 0x400060cc - 1589 .set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 - 1590 .set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 - 1591 .set CYREG_USB_ARB_EP6_CFG, 0x400060d0 - 1592 .set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1 - 1593 .set CYREG_USB_ARB_EP6_SR, 0x400060d2 - 1594 .set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 - 1595 .set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 - 1596 .set CYREG_USB_ARB_RW6_WA, 0x400060d4 - 1597 .set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5 - 1598 .set CYREG_USB_ARB_RW6_RA, 0x400060d6 - 1599 .set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7 - 1600 .set CYREG_USB_ARB_RW6_DR, 0x400060d8 - 1601 .set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 - 1602 .set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 - 1603 .set CYREG_USB_ARB_EP7_CFG, 0x400060e0 - 1604 .set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1 - 1605 .set CYREG_USB_ARB_EP7_SR, 0x400060e2 - 1606 .set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 - 1607 .set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 - 1608 .set CYREG_USB_ARB_RW7_WA, 0x400060e4 - 1609 .set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5 - 1610 .set CYREG_USB_ARB_RW7_RA, 0x400060e6 - 1611 .set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7 - 1612 .set CYREG_USB_ARB_RW7_DR, 0x400060e8 - 1613 .set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 - 1614 .set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 - 1615 .set CYREG_USB_ARB_EP8_CFG, 0x400060f0 - 1616 .set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1 - 1617 .set CYREG_USB_ARB_EP8_SR, 0x400060f2 - 1618 .set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 - 1619 .set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 - 1620 .set CYREG_USB_ARB_RW8_WA, 0x400060f4 - 1621 .set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5 - 1622 .set CYREG_USB_ARB_RW8_RA, 0x400060f6 - 1623 .set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7 - 1624 .set CYREG_USB_ARB_RW8_DR, 0x400060f8 - 1625 .set CYDEV_USB_MEM_BASE, 0x40006100 - 1626 .set CYDEV_USB_MEM_SIZE, 0x00000200 - 1627 .set CYREG_USB_MEM_DATA_MBASE, 0x40006100 - 1628 .set CYREG_USB_MEM_DATA_MSIZE, 0x00000200 - 1629 .set CYDEV_UWRK_BASE, 0x40006400 - 1630 .set CYDEV_UWRK_SIZE, 0x00000b60 - 1631 .set CYDEV_UWRK_UWRK8_BASE, 0x40006400 - 1632 .set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 - 1633 .set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 - 1634 .set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 - 1635 .set CYREG_B0_UDB00_A0, 0x40006400 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 124 - - - 1636 .set CYREG_B0_UDB01_A0, 0x40006401 - 1637 .set CYREG_B0_UDB02_A0, 0x40006402 - 1638 .set CYREG_B0_UDB03_A0, 0x40006403 - 1639 .set CYREG_B0_UDB04_A0, 0x40006404 - 1640 .set CYREG_B0_UDB05_A0, 0x40006405 - 1641 .set CYREG_B0_UDB06_A0, 0x40006406 - 1642 .set CYREG_B0_UDB07_A0, 0x40006407 - 1643 .set CYREG_B0_UDB08_A0, 0x40006408 - 1644 .set CYREG_B0_UDB09_A0, 0x40006409 - 1645 .set CYREG_B0_UDB10_A0, 0x4000640a - 1646 .set CYREG_B0_UDB11_A0, 0x4000640b - 1647 .set CYREG_B0_UDB12_A0, 0x4000640c - 1648 .set CYREG_B0_UDB13_A0, 0x4000640d - 1649 .set CYREG_B0_UDB14_A0, 0x4000640e - 1650 .set CYREG_B0_UDB15_A0, 0x4000640f - 1651 .set CYREG_B0_UDB00_A1, 0x40006410 - 1652 .set CYREG_B0_UDB01_A1, 0x40006411 - 1653 .set CYREG_B0_UDB02_A1, 0x40006412 - 1654 .set CYREG_B0_UDB03_A1, 0x40006413 - 1655 .set CYREG_B0_UDB04_A1, 0x40006414 - 1656 .set CYREG_B0_UDB05_A1, 0x40006415 - 1657 .set CYREG_B0_UDB06_A1, 0x40006416 - 1658 .set CYREG_B0_UDB07_A1, 0x40006417 - 1659 .set CYREG_B0_UDB08_A1, 0x40006418 - 1660 .set CYREG_B0_UDB09_A1, 0x40006419 - 1661 .set CYREG_B0_UDB10_A1, 0x4000641a - 1662 .set CYREG_B0_UDB11_A1, 0x4000641b - 1663 .set CYREG_B0_UDB12_A1, 0x4000641c - 1664 .set CYREG_B0_UDB13_A1, 0x4000641d - 1665 .set CYREG_B0_UDB14_A1, 0x4000641e - 1666 .set CYREG_B0_UDB15_A1, 0x4000641f - 1667 .set CYREG_B0_UDB00_D0, 0x40006420 - 1668 .set CYREG_B0_UDB01_D0, 0x40006421 - 1669 .set CYREG_B0_UDB02_D0, 0x40006422 - 1670 .set CYREG_B0_UDB03_D0, 0x40006423 - 1671 .set CYREG_B0_UDB04_D0, 0x40006424 - 1672 .set CYREG_B0_UDB05_D0, 0x40006425 - 1673 .set CYREG_B0_UDB06_D0, 0x40006426 - 1674 .set CYREG_B0_UDB07_D0, 0x40006427 - 1675 .set CYREG_B0_UDB08_D0, 0x40006428 - 1676 .set CYREG_B0_UDB09_D0, 0x40006429 - 1677 .set CYREG_B0_UDB10_D0, 0x4000642a - 1678 .set CYREG_B0_UDB11_D0, 0x4000642b - 1679 .set CYREG_B0_UDB12_D0, 0x4000642c - 1680 .set CYREG_B0_UDB13_D0, 0x4000642d - 1681 .set CYREG_B0_UDB14_D0, 0x4000642e - 1682 .set CYREG_B0_UDB15_D0, 0x4000642f - 1683 .set CYREG_B0_UDB00_D1, 0x40006430 - 1684 .set CYREG_B0_UDB01_D1, 0x40006431 - 1685 .set CYREG_B0_UDB02_D1, 0x40006432 - 1686 .set CYREG_B0_UDB03_D1, 0x40006433 - 1687 .set CYREG_B0_UDB04_D1, 0x40006434 - 1688 .set CYREG_B0_UDB05_D1, 0x40006435 - 1689 .set CYREG_B0_UDB06_D1, 0x40006436 - 1690 .set CYREG_B0_UDB07_D1, 0x40006437 - 1691 .set CYREG_B0_UDB08_D1, 0x40006438 - 1692 .set CYREG_B0_UDB09_D1, 0x40006439 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 125 - - - 1693 .set CYREG_B0_UDB10_D1, 0x4000643a - 1694 .set CYREG_B0_UDB11_D1, 0x4000643b - 1695 .set CYREG_B0_UDB12_D1, 0x4000643c - 1696 .set CYREG_B0_UDB13_D1, 0x4000643d - 1697 .set CYREG_B0_UDB14_D1, 0x4000643e - 1698 .set CYREG_B0_UDB15_D1, 0x4000643f - 1699 .set CYREG_B0_UDB00_F0, 0x40006440 - 1700 .set CYREG_B0_UDB01_F0, 0x40006441 - 1701 .set CYREG_B0_UDB02_F0, 0x40006442 - 1702 .set CYREG_B0_UDB03_F0, 0x40006443 - 1703 .set CYREG_B0_UDB04_F0, 0x40006444 - 1704 .set CYREG_B0_UDB05_F0, 0x40006445 - 1705 .set CYREG_B0_UDB06_F0, 0x40006446 - 1706 .set CYREG_B0_UDB07_F0, 0x40006447 - 1707 .set CYREG_B0_UDB08_F0, 0x40006448 - 1708 .set CYREG_B0_UDB09_F0, 0x40006449 - 1709 .set CYREG_B0_UDB10_F0, 0x4000644a - 1710 .set CYREG_B0_UDB11_F0, 0x4000644b - 1711 .set CYREG_B0_UDB12_F0, 0x4000644c - 1712 .set CYREG_B0_UDB13_F0, 0x4000644d - 1713 .set CYREG_B0_UDB14_F0, 0x4000644e - 1714 .set CYREG_B0_UDB15_F0, 0x4000644f - 1715 .set CYREG_B0_UDB00_F1, 0x40006450 - 1716 .set CYREG_B0_UDB01_F1, 0x40006451 - 1717 .set CYREG_B0_UDB02_F1, 0x40006452 - 1718 .set CYREG_B0_UDB03_F1, 0x40006453 - 1719 .set CYREG_B0_UDB04_F1, 0x40006454 - 1720 .set CYREG_B0_UDB05_F1, 0x40006455 - 1721 .set CYREG_B0_UDB06_F1, 0x40006456 - 1722 .set CYREG_B0_UDB07_F1, 0x40006457 - 1723 .set CYREG_B0_UDB08_F1, 0x40006458 - 1724 .set CYREG_B0_UDB09_F1, 0x40006459 - 1725 .set CYREG_B0_UDB10_F1, 0x4000645a - 1726 .set CYREG_B0_UDB11_F1, 0x4000645b - 1727 .set CYREG_B0_UDB12_F1, 0x4000645c - 1728 .set CYREG_B0_UDB13_F1, 0x4000645d - 1729 .set CYREG_B0_UDB14_F1, 0x4000645e - 1730 .set CYREG_B0_UDB15_F1, 0x4000645f - 1731 .set CYREG_B0_UDB00_ST, 0x40006460 - 1732 .set CYREG_B0_UDB01_ST, 0x40006461 - 1733 .set CYREG_B0_UDB02_ST, 0x40006462 - 1734 .set CYREG_B0_UDB03_ST, 0x40006463 - 1735 .set CYREG_B0_UDB04_ST, 0x40006464 - 1736 .set CYREG_B0_UDB05_ST, 0x40006465 - 1737 .set CYREG_B0_UDB06_ST, 0x40006466 - 1738 .set CYREG_B0_UDB07_ST, 0x40006467 - 1739 .set CYREG_B0_UDB08_ST, 0x40006468 - 1740 .set CYREG_B0_UDB09_ST, 0x40006469 - 1741 .set CYREG_B0_UDB10_ST, 0x4000646a - 1742 .set CYREG_B0_UDB11_ST, 0x4000646b - 1743 .set CYREG_B0_UDB12_ST, 0x4000646c - 1744 .set CYREG_B0_UDB13_ST, 0x4000646d - 1745 .set CYREG_B0_UDB14_ST, 0x4000646e - 1746 .set CYREG_B0_UDB15_ST, 0x4000646f - 1747 .set CYREG_B0_UDB00_CTL, 0x40006470 - 1748 .set CYREG_B0_UDB01_CTL, 0x40006471 - 1749 .set CYREG_B0_UDB02_CTL, 0x40006472 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 126 - - - 1750 .set CYREG_B0_UDB03_CTL, 0x40006473 - 1751 .set CYREG_B0_UDB04_CTL, 0x40006474 - 1752 .set CYREG_B0_UDB05_CTL, 0x40006475 - 1753 .set CYREG_B0_UDB06_CTL, 0x40006476 - 1754 .set CYREG_B0_UDB07_CTL, 0x40006477 - 1755 .set CYREG_B0_UDB08_CTL, 0x40006478 - 1756 .set CYREG_B0_UDB09_CTL, 0x40006479 - 1757 .set CYREG_B0_UDB10_CTL, 0x4000647a - 1758 .set CYREG_B0_UDB11_CTL, 0x4000647b - 1759 .set CYREG_B0_UDB12_CTL, 0x4000647c - 1760 .set CYREG_B0_UDB13_CTL, 0x4000647d - 1761 .set CYREG_B0_UDB14_CTL, 0x4000647e - 1762 .set CYREG_B0_UDB15_CTL, 0x4000647f - 1763 .set CYREG_B0_UDB00_MSK, 0x40006480 - 1764 .set CYREG_B0_UDB01_MSK, 0x40006481 - 1765 .set CYREG_B0_UDB02_MSK, 0x40006482 - 1766 .set CYREG_B0_UDB03_MSK, 0x40006483 - 1767 .set CYREG_B0_UDB04_MSK, 0x40006484 - 1768 .set CYREG_B0_UDB05_MSK, 0x40006485 - 1769 .set CYREG_B0_UDB06_MSK, 0x40006486 - 1770 .set CYREG_B0_UDB07_MSK, 0x40006487 - 1771 .set CYREG_B0_UDB08_MSK, 0x40006488 - 1772 .set CYREG_B0_UDB09_MSK, 0x40006489 - 1773 .set CYREG_B0_UDB10_MSK, 0x4000648a - 1774 .set CYREG_B0_UDB11_MSK, 0x4000648b - 1775 .set CYREG_B0_UDB12_MSK, 0x4000648c - 1776 .set CYREG_B0_UDB13_MSK, 0x4000648d - 1777 .set CYREG_B0_UDB14_MSK, 0x4000648e - 1778 .set CYREG_B0_UDB15_MSK, 0x4000648f - 1779 .set CYREG_B0_UDB00_ACTL, 0x40006490 - 1780 .set CYREG_B0_UDB01_ACTL, 0x40006491 - 1781 .set CYREG_B0_UDB02_ACTL, 0x40006492 - 1782 .set CYREG_B0_UDB03_ACTL, 0x40006493 - 1783 .set CYREG_B0_UDB04_ACTL, 0x40006494 - 1784 .set CYREG_B0_UDB05_ACTL, 0x40006495 - 1785 .set CYREG_B0_UDB06_ACTL, 0x40006496 - 1786 .set CYREG_B0_UDB07_ACTL, 0x40006497 - 1787 .set CYREG_B0_UDB08_ACTL, 0x40006498 - 1788 .set CYREG_B0_UDB09_ACTL, 0x40006499 - 1789 .set CYREG_B0_UDB10_ACTL, 0x4000649a - 1790 .set CYREG_B0_UDB11_ACTL, 0x4000649b - 1791 .set CYREG_B0_UDB12_ACTL, 0x4000649c - 1792 .set CYREG_B0_UDB13_ACTL, 0x4000649d - 1793 .set CYREG_B0_UDB14_ACTL, 0x4000649e - 1794 .set CYREG_B0_UDB15_ACTL, 0x4000649f - 1795 .set CYREG_B0_UDB00_MC, 0x400064a0 - 1796 .set CYREG_B0_UDB01_MC, 0x400064a1 - 1797 .set CYREG_B0_UDB02_MC, 0x400064a2 - 1798 .set CYREG_B0_UDB03_MC, 0x400064a3 - 1799 .set CYREG_B0_UDB04_MC, 0x400064a4 - 1800 .set CYREG_B0_UDB05_MC, 0x400064a5 - 1801 .set CYREG_B0_UDB06_MC, 0x400064a6 - 1802 .set CYREG_B0_UDB07_MC, 0x400064a7 - 1803 .set CYREG_B0_UDB08_MC, 0x400064a8 - 1804 .set CYREG_B0_UDB09_MC, 0x400064a9 - 1805 .set CYREG_B0_UDB10_MC, 0x400064aa - 1806 .set CYREG_B0_UDB11_MC, 0x400064ab - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 127 - - - 1807 .set CYREG_B0_UDB12_MC, 0x400064ac - 1808 .set CYREG_B0_UDB13_MC, 0x400064ad - 1809 .set CYREG_B0_UDB14_MC, 0x400064ae - 1810 .set CYREG_B0_UDB15_MC, 0x400064af - 1811 .set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 - 1812 .set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 - 1813 .set CYREG_B1_UDB04_A0, 0x40006504 - 1814 .set CYREG_B1_UDB05_A0, 0x40006505 - 1815 .set CYREG_B1_UDB06_A0, 0x40006506 - 1816 .set CYREG_B1_UDB07_A0, 0x40006507 - 1817 .set CYREG_B1_UDB08_A0, 0x40006508 - 1818 .set CYREG_B1_UDB09_A0, 0x40006509 - 1819 .set CYREG_B1_UDB10_A0, 0x4000650a - 1820 .set CYREG_B1_UDB11_A0, 0x4000650b - 1821 .set CYREG_B1_UDB04_A1, 0x40006514 - 1822 .set CYREG_B1_UDB05_A1, 0x40006515 - 1823 .set CYREG_B1_UDB06_A1, 0x40006516 - 1824 .set CYREG_B1_UDB07_A1, 0x40006517 - 1825 .set CYREG_B1_UDB08_A1, 0x40006518 - 1826 .set CYREG_B1_UDB09_A1, 0x40006519 - 1827 .set CYREG_B1_UDB10_A1, 0x4000651a - 1828 .set CYREG_B1_UDB11_A1, 0x4000651b - 1829 .set CYREG_B1_UDB04_D0, 0x40006524 - 1830 .set CYREG_B1_UDB05_D0, 0x40006525 - 1831 .set CYREG_B1_UDB06_D0, 0x40006526 - 1832 .set CYREG_B1_UDB07_D0, 0x40006527 - 1833 .set CYREG_B1_UDB08_D0, 0x40006528 - 1834 .set CYREG_B1_UDB09_D0, 0x40006529 - 1835 .set CYREG_B1_UDB10_D0, 0x4000652a - 1836 .set CYREG_B1_UDB11_D0, 0x4000652b - 1837 .set CYREG_B1_UDB04_D1, 0x40006534 - 1838 .set CYREG_B1_UDB05_D1, 0x40006535 - 1839 .set CYREG_B1_UDB06_D1, 0x40006536 - 1840 .set CYREG_B1_UDB07_D1, 0x40006537 - 1841 .set CYREG_B1_UDB08_D1, 0x40006538 - 1842 .set CYREG_B1_UDB09_D1, 0x40006539 - 1843 .set CYREG_B1_UDB10_D1, 0x4000653a - 1844 .set CYREG_B1_UDB11_D1, 0x4000653b - 1845 .set CYREG_B1_UDB04_F0, 0x40006544 - 1846 .set CYREG_B1_UDB05_F0, 0x40006545 - 1847 .set CYREG_B1_UDB06_F0, 0x40006546 - 1848 .set CYREG_B1_UDB07_F0, 0x40006547 - 1849 .set CYREG_B1_UDB08_F0, 0x40006548 - 1850 .set CYREG_B1_UDB09_F0, 0x40006549 - 1851 .set CYREG_B1_UDB10_F0, 0x4000654a - 1852 .set CYREG_B1_UDB11_F0, 0x4000654b - 1853 .set CYREG_B1_UDB04_F1, 0x40006554 - 1854 .set CYREG_B1_UDB05_F1, 0x40006555 - 1855 .set CYREG_B1_UDB06_F1, 0x40006556 - 1856 .set CYREG_B1_UDB07_F1, 0x40006557 - 1857 .set CYREG_B1_UDB08_F1, 0x40006558 - 1858 .set CYREG_B1_UDB09_F1, 0x40006559 - 1859 .set CYREG_B1_UDB10_F1, 0x4000655a - 1860 .set CYREG_B1_UDB11_F1, 0x4000655b - 1861 .set CYREG_B1_UDB04_ST, 0x40006564 - 1862 .set CYREG_B1_UDB05_ST, 0x40006565 - 1863 .set CYREG_B1_UDB06_ST, 0x40006566 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 128 - - - 1864 .set CYREG_B1_UDB07_ST, 0x40006567 - 1865 .set CYREG_B1_UDB08_ST, 0x40006568 - 1866 .set CYREG_B1_UDB09_ST, 0x40006569 - 1867 .set CYREG_B1_UDB10_ST, 0x4000656a - 1868 .set CYREG_B1_UDB11_ST, 0x4000656b - 1869 .set CYREG_B1_UDB04_CTL, 0x40006574 - 1870 .set CYREG_B1_UDB05_CTL, 0x40006575 - 1871 .set CYREG_B1_UDB06_CTL, 0x40006576 - 1872 .set CYREG_B1_UDB07_CTL, 0x40006577 - 1873 .set CYREG_B1_UDB08_CTL, 0x40006578 - 1874 .set CYREG_B1_UDB09_CTL, 0x40006579 - 1875 .set CYREG_B1_UDB10_CTL, 0x4000657a - 1876 .set CYREG_B1_UDB11_CTL, 0x4000657b - 1877 .set CYREG_B1_UDB04_MSK, 0x40006584 - 1878 .set CYREG_B1_UDB05_MSK, 0x40006585 - 1879 .set CYREG_B1_UDB06_MSK, 0x40006586 - 1880 .set CYREG_B1_UDB07_MSK, 0x40006587 - 1881 .set CYREG_B1_UDB08_MSK, 0x40006588 - 1882 .set CYREG_B1_UDB09_MSK, 0x40006589 - 1883 .set CYREG_B1_UDB10_MSK, 0x4000658a - 1884 .set CYREG_B1_UDB11_MSK, 0x4000658b - 1885 .set CYREG_B1_UDB04_ACTL, 0x40006594 - 1886 .set CYREG_B1_UDB05_ACTL, 0x40006595 - 1887 .set CYREG_B1_UDB06_ACTL, 0x40006596 - 1888 .set CYREG_B1_UDB07_ACTL, 0x40006597 - 1889 .set CYREG_B1_UDB08_ACTL, 0x40006598 - 1890 .set CYREG_B1_UDB09_ACTL, 0x40006599 - 1891 .set CYREG_B1_UDB10_ACTL, 0x4000659a - 1892 .set CYREG_B1_UDB11_ACTL, 0x4000659b - 1893 .set CYREG_B1_UDB04_MC, 0x400065a4 - 1894 .set CYREG_B1_UDB05_MC, 0x400065a5 - 1895 .set CYREG_B1_UDB06_MC, 0x400065a6 - 1896 .set CYREG_B1_UDB07_MC, 0x400065a7 - 1897 .set CYREG_B1_UDB08_MC, 0x400065a8 - 1898 .set CYREG_B1_UDB09_MC, 0x400065a9 - 1899 .set CYREG_B1_UDB10_MC, 0x400065aa - 1900 .set CYREG_B1_UDB11_MC, 0x400065ab - 1901 .set CYDEV_UWRK_UWRK16_BASE, 0x40006800 - 1902 .set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 - 1903 .set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 - 1904 .set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 - 1905 .set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 - 1906 .set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 - 1907 .set CYREG_B0_UDB00_A0_A1, 0x40006800 - 1908 .set CYREG_B0_UDB01_A0_A1, 0x40006802 - 1909 .set CYREG_B0_UDB02_A0_A1, 0x40006804 - 1910 .set CYREG_B0_UDB03_A0_A1, 0x40006806 - 1911 .set CYREG_B0_UDB04_A0_A1, 0x40006808 - 1912 .set CYREG_B0_UDB05_A0_A1, 0x4000680a - 1913 .set CYREG_B0_UDB06_A0_A1, 0x4000680c - 1914 .set CYREG_B0_UDB07_A0_A1, 0x4000680e - 1915 .set CYREG_B0_UDB08_A0_A1, 0x40006810 - 1916 .set CYREG_B0_UDB09_A0_A1, 0x40006812 - 1917 .set CYREG_B0_UDB10_A0_A1, 0x40006814 - 1918 .set CYREG_B0_UDB11_A0_A1, 0x40006816 - 1919 .set CYREG_B0_UDB12_A0_A1, 0x40006818 - 1920 .set CYREG_B0_UDB13_A0_A1, 0x4000681a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 129 - - - 1921 .set CYREG_B0_UDB14_A0_A1, 0x4000681c - 1922 .set CYREG_B0_UDB15_A0_A1, 0x4000681e - 1923 .set CYREG_B0_UDB00_D0_D1, 0x40006840 - 1924 .set CYREG_B0_UDB01_D0_D1, 0x40006842 - 1925 .set CYREG_B0_UDB02_D0_D1, 0x40006844 - 1926 .set CYREG_B0_UDB03_D0_D1, 0x40006846 - 1927 .set CYREG_B0_UDB04_D0_D1, 0x40006848 - 1928 .set CYREG_B0_UDB05_D0_D1, 0x4000684a - 1929 .set CYREG_B0_UDB06_D0_D1, 0x4000684c - 1930 .set CYREG_B0_UDB07_D0_D1, 0x4000684e - 1931 .set CYREG_B0_UDB08_D0_D1, 0x40006850 - 1932 .set CYREG_B0_UDB09_D0_D1, 0x40006852 - 1933 .set CYREG_B0_UDB10_D0_D1, 0x40006854 - 1934 .set CYREG_B0_UDB11_D0_D1, 0x40006856 - 1935 .set CYREG_B0_UDB12_D0_D1, 0x40006858 - 1936 .set CYREG_B0_UDB13_D0_D1, 0x4000685a - 1937 .set CYREG_B0_UDB14_D0_D1, 0x4000685c - 1938 .set CYREG_B0_UDB15_D0_D1, 0x4000685e - 1939 .set CYREG_B0_UDB00_F0_F1, 0x40006880 - 1940 .set CYREG_B0_UDB01_F0_F1, 0x40006882 - 1941 .set CYREG_B0_UDB02_F0_F1, 0x40006884 - 1942 .set CYREG_B0_UDB03_F0_F1, 0x40006886 - 1943 .set CYREG_B0_UDB04_F0_F1, 0x40006888 - 1944 .set CYREG_B0_UDB05_F0_F1, 0x4000688a - 1945 .set CYREG_B0_UDB06_F0_F1, 0x4000688c - 1946 .set CYREG_B0_UDB07_F0_F1, 0x4000688e - 1947 .set CYREG_B0_UDB08_F0_F1, 0x40006890 - 1948 .set CYREG_B0_UDB09_F0_F1, 0x40006892 - 1949 .set CYREG_B0_UDB10_F0_F1, 0x40006894 - 1950 .set CYREG_B0_UDB11_F0_F1, 0x40006896 - 1951 .set CYREG_B0_UDB12_F0_F1, 0x40006898 - 1952 .set CYREG_B0_UDB13_F0_F1, 0x4000689a - 1953 .set CYREG_B0_UDB14_F0_F1, 0x4000689c - 1954 .set CYREG_B0_UDB15_F0_F1, 0x4000689e - 1955 .set CYREG_B0_UDB00_ST_CTL, 0x400068c0 - 1956 .set CYREG_B0_UDB01_ST_CTL, 0x400068c2 - 1957 .set CYREG_B0_UDB02_ST_CTL, 0x400068c4 - 1958 .set CYREG_B0_UDB03_ST_CTL, 0x400068c6 - 1959 .set CYREG_B0_UDB04_ST_CTL, 0x400068c8 - 1960 .set CYREG_B0_UDB05_ST_CTL, 0x400068ca - 1961 .set CYREG_B0_UDB06_ST_CTL, 0x400068cc - 1962 .set CYREG_B0_UDB07_ST_CTL, 0x400068ce - 1963 .set CYREG_B0_UDB08_ST_CTL, 0x400068d0 - 1964 .set CYREG_B0_UDB09_ST_CTL, 0x400068d2 - 1965 .set CYREG_B0_UDB10_ST_CTL, 0x400068d4 - 1966 .set CYREG_B0_UDB11_ST_CTL, 0x400068d6 - 1967 .set CYREG_B0_UDB12_ST_CTL, 0x400068d8 - 1968 .set CYREG_B0_UDB13_ST_CTL, 0x400068da - 1969 .set CYREG_B0_UDB14_ST_CTL, 0x400068dc - 1970 .set CYREG_B0_UDB15_ST_CTL, 0x400068de - 1971 .set CYREG_B0_UDB00_MSK_ACTL, 0x40006900 - 1972 .set CYREG_B0_UDB01_MSK_ACTL, 0x40006902 - 1973 .set CYREG_B0_UDB02_MSK_ACTL, 0x40006904 - 1974 .set CYREG_B0_UDB03_MSK_ACTL, 0x40006906 - 1975 .set CYREG_B0_UDB04_MSK_ACTL, 0x40006908 - 1976 .set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a - 1977 .set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 130 - - - 1978 .set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e - 1979 .set CYREG_B0_UDB08_MSK_ACTL, 0x40006910 - 1980 .set CYREG_B0_UDB09_MSK_ACTL, 0x40006912 - 1981 .set CYREG_B0_UDB10_MSK_ACTL, 0x40006914 - 1982 .set CYREG_B0_UDB11_MSK_ACTL, 0x40006916 - 1983 .set CYREG_B0_UDB12_MSK_ACTL, 0x40006918 - 1984 .set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a - 1985 .set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c - 1986 .set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e - 1987 .set CYREG_B0_UDB00_MC_00, 0x40006940 - 1988 .set CYREG_B0_UDB01_MC_00, 0x40006942 - 1989 .set CYREG_B0_UDB02_MC_00, 0x40006944 - 1990 .set CYREG_B0_UDB03_MC_00, 0x40006946 - 1991 .set CYREG_B0_UDB04_MC_00, 0x40006948 - 1992 .set CYREG_B0_UDB05_MC_00, 0x4000694a - 1993 .set CYREG_B0_UDB06_MC_00, 0x4000694c - 1994 .set CYREG_B0_UDB07_MC_00, 0x4000694e - 1995 .set CYREG_B0_UDB08_MC_00, 0x40006950 - 1996 .set CYREG_B0_UDB09_MC_00, 0x40006952 - 1997 .set CYREG_B0_UDB10_MC_00, 0x40006954 - 1998 .set CYREG_B0_UDB11_MC_00, 0x40006956 - 1999 .set CYREG_B0_UDB12_MC_00, 0x40006958 - 2000 .set CYREG_B0_UDB13_MC_00, 0x4000695a - 2001 .set CYREG_B0_UDB14_MC_00, 0x4000695c - 2002 .set CYREG_B0_UDB15_MC_00, 0x4000695e - 2003 .set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 - 2004 .set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 - 2005 .set CYREG_B1_UDB04_A0_A1, 0x40006a08 - 2006 .set CYREG_B1_UDB05_A0_A1, 0x40006a0a - 2007 .set CYREG_B1_UDB06_A0_A1, 0x40006a0c - 2008 .set CYREG_B1_UDB07_A0_A1, 0x40006a0e - 2009 .set CYREG_B1_UDB08_A0_A1, 0x40006a10 - 2010 .set CYREG_B1_UDB09_A0_A1, 0x40006a12 - 2011 .set CYREG_B1_UDB10_A0_A1, 0x40006a14 - 2012 .set CYREG_B1_UDB11_A0_A1, 0x40006a16 - 2013 .set CYREG_B1_UDB04_D0_D1, 0x40006a48 - 2014 .set CYREG_B1_UDB05_D0_D1, 0x40006a4a - 2015 .set CYREG_B1_UDB06_D0_D1, 0x40006a4c - 2016 .set CYREG_B1_UDB07_D0_D1, 0x40006a4e - 2017 .set CYREG_B1_UDB08_D0_D1, 0x40006a50 - 2018 .set CYREG_B1_UDB09_D0_D1, 0x40006a52 - 2019 .set CYREG_B1_UDB10_D0_D1, 0x40006a54 - 2020 .set CYREG_B1_UDB11_D0_D1, 0x40006a56 - 2021 .set CYREG_B1_UDB04_F0_F1, 0x40006a88 - 2022 .set CYREG_B1_UDB05_F0_F1, 0x40006a8a - 2023 .set CYREG_B1_UDB06_F0_F1, 0x40006a8c - 2024 .set CYREG_B1_UDB07_F0_F1, 0x40006a8e - 2025 .set CYREG_B1_UDB08_F0_F1, 0x40006a90 - 2026 .set CYREG_B1_UDB09_F0_F1, 0x40006a92 - 2027 .set CYREG_B1_UDB10_F0_F1, 0x40006a94 - 2028 .set CYREG_B1_UDB11_F0_F1, 0x40006a96 - 2029 .set CYREG_B1_UDB04_ST_CTL, 0x40006ac8 - 2030 .set CYREG_B1_UDB05_ST_CTL, 0x40006aca - 2031 .set CYREG_B1_UDB06_ST_CTL, 0x40006acc - 2032 .set CYREG_B1_UDB07_ST_CTL, 0x40006ace - 2033 .set CYREG_B1_UDB08_ST_CTL, 0x40006ad0 - 2034 .set CYREG_B1_UDB09_ST_CTL, 0x40006ad2 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 131 - - - 2035 .set CYREG_B1_UDB10_ST_CTL, 0x40006ad4 - 2036 .set CYREG_B1_UDB11_ST_CTL, 0x40006ad6 - 2037 .set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08 - 2038 .set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a - 2039 .set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c - 2040 .set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e - 2041 .set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10 - 2042 .set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12 - 2043 .set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14 - 2044 .set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16 - 2045 .set CYREG_B1_UDB04_MC_00, 0x40006b48 - 2046 .set CYREG_B1_UDB05_MC_00, 0x40006b4a - 2047 .set CYREG_B1_UDB06_MC_00, 0x40006b4c - 2048 .set CYREG_B1_UDB07_MC_00, 0x40006b4e - 2049 .set CYREG_B1_UDB08_MC_00, 0x40006b50 - 2050 .set CYREG_B1_UDB09_MC_00, 0x40006b52 - 2051 .set CYREG_B1_UDB10_MC_00, 0x40006b54 - 2052 .set CYREG_B1_UDB11_MC_00, 0x40006b56 - 2053 .set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 - 2054 .set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e - 2055 .set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 - 2056 .set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e - 2057 .set CYREG_B0_UDB00_01_A0, 0x40006800 - 2058 .set CYREG_B0_UDB01_02_A0, 0x40006802 - 2059 .set CYREG_B0_UDB02_03_A0, 0x40006804 - 2060 .set CYREG_B0_UDB03_04_A0, 0x40006806 - 2061 .set CYREG_B0_UDB04_05_A0, 0x40006808 - 2062 .set CYREG_B0_UDB05_06_A0, 0x4000680a - 2063 .set CYREG_B0_UDB06_07_A0, 0x4000680c - 2064 .set CYREG_B0_UDB07_08_A0, 0x4000680e - 2065 .set CYREG_B0_UDB08_09_A0, 0x40006810 - 2066 .set CYREG_B0_UDB09_10_A0, 0x40006812 - 2067 .set CYREG_B0_UDB10_11_A0, 0x40006814 - 2068 .set CYREG_B0_UDB11_12_A0, 0x40006816 - 2069 .set CYREG_B0_UDB12_13_A0, 0x40006818 - 2070 .set CYREG_B0_UDB13_14_A0, 0x4000681a - 2071 .set CYREG_B0_UDB14_15_A0, 0x4000681c - 2072 .set CYREG_B0_UDB00_01_A1, 0x40006820 - 2073 .set CYREG_B0_UDB01_02_A1, 0x40006822 - 2074 .set CYREG_B0_UDB02_03_A1, 0x40006824 - 2075 .set CYREG_B0_UDB03_04_A1, 0x40006826 - 2076 .set CYREG_B0_UDB04_05_A1, 0x40006828 - 2077 .set CYREG_B0_UDB05_06_A1, 0x4000682a - 2078 .set CYREG_B0_UDB06_07_A1, 0x4000682c - 2079 .set CYREG_B0_UDB07_08_A1, 0x4000682e - 2080 .set CYREG_B0_UDB08_09_A1, 0x40006830 - 2081 .set CYREG_B0_UDB09_10_A1, 0x40006832 - 2082 .set CYREG_B0_UDB10_11_A1, 0x40006834 - 2083 .set CYREG_B0_UDB11_12_A1, 0x40006836 - 2084 .set CYREG_B0_UDB12_13_A1, 0x40006838 - 2085 .set CYREG_B0_UDB13_14_A1, 0x4000683a - 2086 .set CYREG_B0_UDB14_15_A1, 0x4000683c - 2087 .set CYREG_B0_UDB00_01_D0, 0x40006840 - 2088 .set CYREG_B0_UDB01_02_D0, 0x40006842 - 2089 .set CYREG_B0_UDB02_03_D0, 0x40006844 - 2090 .set CYREG_B0_UDB03_04_D0, 0x40006846 - 2091 .set CYREG_B0_UDB04_05_D0, 0x40006848 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 132 - - - 2092 .set CYREG_B0_UDB05_06_D0, 0x4000684a - 2093 .set CYREG_B0_UDB06_07_D0, 0x4000684c - 2094 .set CYREG_B0_UDB07_08_D0, 0x4000684e - 2095 .set CYREG_B0_UDB08_09_D0, 0x40006850 - 2096 .set CYREG_B0_UDB09_10_D0, 0x40006852 - 2097 .set CYREG_B0_UDB10_11_D0, 0x40006854 - 2098 .set CYREG_B0_UDB11_12_D0, 0x40006856 - 2099 .set CYREG_B0_UDB12_13_D0, 0x40006858 - 2100 .set CYREG_B0_UDB13_14_D0, 0x4000685a - 2101 .set CYREG_B0_UDB14_15_D0, 0x4000685c - 2102 .set CYREG_B0_UDB00_01_D1, 0x40006860 - 2103 .set CYREG_B0_UDB01_02_D1, 0x40006862 - 2104 .set CYREG_B0_UDB02_03_D1, 0x40006864 - 2105 .set CYREG_B0_UDB03_04_D1, 0x40006866 - 2106 .set CYREG_B0_UDB04_05_D1, 0x40006868 - 2107 .set CYREG_B0_UDB05_06_D1, 0x4000686a - 2108 .set CYREG_B0_UDB06_07_D1, 0x4000686c - 2109 .set CYREG_B0_UDB07_08_D1, 0x4000686e - 2110 .set CYREG_B0_UDB08_09_D1, 0x40006870 - 2111 .set CYREG_B0_UDB09_10_D1, 0x40006872 - 2112 .set CYREG_B0_UDB10_11_D1, 0x40006874 - 2113 .set CYREG_B0_UDB11_12_D1, 0x40006876 - 2114 .set CYREG_B0_UDB12_13_D1, 0x40006878 - 2115 .set CYREG_B0_UDB13_14_D1, 0x4000687a - 2116 .set CYREG_B0_UDB14_15_D1, 0x4000687c - 2117 .set CYREG_B0_UDB00_01_F0, 0x40006880 - 2118 .set CYREG_B0_UDB01_02_F0, 0x40006882 - 2119 .set CYREG_B0_UDB02_03_F0, 0x40006884 - 2120 .set CYREG_B0_UDB03_04_F0, 0x40006886 - 2121 .set CYREG_B0_UDB04_05_F0, 0x40006888 - 2122 .set CYREG_B0_UDB05_06_F0, 0x4000688a - 2123 .set CYREG_B0_UDB06_07_F0, 0x4000688c - 2124 .set CYREG_B0_UDB07_08_F0, 0x4000688e - 2125 .set CYREG_B0_UDB08_09_F0, 0x40006890 - 2126 .set CYREG_B0_UDB09_10_F0, 0x40006892 - 2127 .set CYREG_B0_UDB10_11_F0, 0x40006894 - 2128 .set CYREG_B0_UDB11_12_F0, 0x40006896 - 2129 .set CYREG_B0_UDB12_13_F0, 0x40006898 - 2130 .set CYREG_B0_UDB13_14_F0, 0x4000689a - 2131 .set CYREG_B0_UDB14_15_F0, 0x4000689c - 2132 .set CYREG_B0_UDB00_01_F1, 0x400068a0 - 2133 .set CYREG_B0_UDB01_02_F1, 0x400068a2 - 2134 .set CYREG_B0_UDB02_03_F1, 0x400068a4 - 2135 .set CYREG_B0_UDB03_04_F1, 0x400068a6 - 2136 .set CYREG_B0_UDB04_05_F1, 0x400068a8 - 2137 .set CYREG_B0_UDB05_06_F1, 0x400068aa - 2138 .set CYREG_B0_UDB06_07_F1, 0x400068ac - 2139 .set CYREG_B0_UDB07_08_F1, 0x400068ae - 2140 .set CYREG_B0_UDB08_09_F1, 0x400068b0 - 2141 .set CYREG_B0_UDB09_10_F1, 0x400068b2 - 2142 .set CYREG_B0_UDB10_11_F1, 0x400068b4 - 2143 .set CYREG_B0_UDB11_12_F1, 0x400068b6 - 2144 .set CYREG_B0_UDB12_13_F1, 0x400068b8 - 2145 .set CYREG_B0_UDB13_14_F1, 0x400068ba - 2146 .set CYREG_B0_UDB14_15_F1, 0x400068bc - 2147 .set CYREG_B0_UDB00_01_ST, 0x400068c0 - 2148 .set CYREG_B0_UDB01_02_ST, 0x400068c2 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 133 - - - 2149 .set CYREG_B0_UDB02_03_ST, 0x400068c4 - 2150 .set CYREG_B0_UDB03_04_ST, 0x400068c6 - 2151 .set CYREG_B0_UDB04_05_ST, 0x400068c8 - 2152 .set CYREG_B0_UDB05_06_ST, 0x400068ca - 2153 .set CYREG_B0_UDB06_07_ST, 0x400068cc - 2154 .set CYREG_B0_UDB07_08_ST, 0x400068ce - 2155 .set CYREG_B0_UDB08_09_ST, 0x400068d0 - 2156 .set CYREG_B0_UDB09_10_ST, 0x400068d2 - 2157 .set CYREG_B0_UDB10_11_ST, 0x400068d4 - 2158 .set CYREG_B0_UDB11_12_ST, 0x400068d6 - 2159 .set CYREG_B0_UDB12_13_ST, 0x400068d8 - 2160 .set CYREG_B0_UDB13_14_ST, 0x400068da - 2161 .set CYREG_B0_UDB14_15_ST, 0x400068dc - 2162 .set CYREG_B0_UDB00_01_CTL, 0x400068e0 - 2163 .set CYREG_B0_UDB01_02_CTL, 0x400068e2 - 2164 .set CYREG_B0_UDB02_03_CTL, 0x400068e4 - 2165 .set CYREG_B0_UDB03_04_CTL, 0x400068e6 - 2166 .set CYREG_B0_UDB04_05_CTL, 0x400068e8 - 2167 .set CYREG_B0_UDB05_06_CTL, 0x400068ea - 2168 .set CYREG_B0_UDB06_07_CTL, 0x400068ec - 2169 .set CYREG_B0_UDB07_08_CTL, 0x400068ee - 2170 .set CYREG_B0_UDB08_09_CTL, 0x400068f0 - 2171 .set CYREG_B0_UDB09_10_CTL, 0x400068f2 - 2172 .set CYREG_B0_UDB10_11_CTL, 0x400068f4 - 2173 .set CYREG_B0_UDB11_12_CTL, 0x400068f6 - 2174 .set CYREG_B0_UDB12_13_CTL, 0x400068f8 - 2175 .set CYREG_B0_UDB13_14_CTL, 0x400068fa - 2176 .set CYREG_B0_UDB14_15_CTL, 0x400068fc - 2177 .set CYREG_B0_UDB00_01_MSK, 0x40006900 - 2178 .set CYREG_B0_UDB01_02_MSK, 0x40006902 - 2179 .set CYREG_B0_UDB02_03_MSK, 0x40006904 - 2180 .set CYREG_B0_UDB03_04_MSK, 0x40006906 - 2181 .set CYREG_B0_UDB04_05_MSK, 0x40006908 - 2182 .set CYREG_B0_UDB05_06_MSK, 0x4000690a - 2183 .set CYREG_B0_UDB06_07_MSK, 0x4000690c - 2184 .set CYREG_B0_UDB07_08_MSK, 0x4000690e - 2185 .set CYREG_B0_UDB08_09_MSK, 0x40006910 - 2186 .set CYREG_B0_UDB09_10_MSK, 0x40006912 - 2187 .set CYREG_B0_UDB10_11_MSK, 0x40006914 - 2188 .set CYREG_B0_UDB11_12_MSK, 0x40006916 - 2189 .set CYREG_B0_UDB12_13_MSK, 0x40006918 - 2190 .set CYREG_B0_UDB13_14_MSK, 0x4000691a - 2191 .set CYREG_B0_UDB14_15_MSK, 0x4000691c - 2192 .set CYREG_B0_UDB00_01_ACTL, 0x40006920 - 2193 .set CYREG_B0_UDB01_02_ACTL, 0x40006922 - 2194 .set CYREG_B0_UDB02_03_ACTL, 0x40006924 - 2195 .set CYREG_B0_UDB03_04_ACTL, 0x40006926 - 2196 .set CYREG_B0_UDB04_05_ACTL, 0x40006928 - 2197 .set CYREG_B0_UDB05_06_ACTL, 0x4000692a - 2198 .set CYREG_B0_UDB06_07_ACTL, 0x4000692c - 2199 .set CYREG_B0_UDB07_08_ACTL, 0x4000692e - 2200 .set CYREG_B0_UDB08_09_ACTL, 0x40006930 - 2201 .set CYREG_B0_UDB09_10_ACTL, 0x40006932 - 2202 .set CYREG_B0_UDB10_11_ACTL, 0x40006934 - 2203 .set CYREG_B0_UDB11_12_ACTL, 0x40006936 - 2204 .set CYREG_B0_UDB12_13_ACTL, 0x40006938 - 2205 .set CYREG_B0_UDB13_14_ACTL, 0x4000693a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 134 - - - 2206 .set CYREG_B0_UDB14_15_ACTL, 0x4000693c - 2207 .set CYREG_B0_UDB00_01_MC, 0x40006940 - 2208 .set CYREG_B0_UDB01_02_MC, 0x40006942 - 2209 .set CYREG_B0_UDB02_03_MC, 0x40006944 - 2210 .set CYREG_B0_UDB03_04_MC, 0x40006946 - 2211 .set CYREG_B0_UDB04_05_MC, 0x40006948 - 2212 .set CYREG_B0_UDB05_06_MC, 0x4000694a - 2213 .set CYREG_B0_UDB06_07_MC, 0x4000694c - 2214 .set CYREG_B0_UDB07_08_MC, 0x4000694e - 2215 .set CYREG_B0_UDB08_09_MC, 0x40006950 - 2216 .set CYREG_B0_UDB09_10_MC, 0x40006952 - 2217 .set CYREG_B0_UDB10_11_MC, 0x40006954 - 2218 .set CYREG_B0_UDB11_12_MC, 0x40006956 - 2219 .set CYREG_B0_UDB12_13_MC, 0x40006958 - 2220 .set CYREG_B0_UDB13_14_MC, 0x4000695a - 2221 .set CYREG_B0_UDB14_15_MC, 0x4000695c - 2222 .set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 - 2223 .set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e - 2224 .set CYREG_B1_UDB04_05_A0, 0x40006a08 - 2225 .set CYREG_B1_UDB05_06_A0, 0x40006a0a - 2226 .set CYREG_B1_UDB06_07_A0, 0x40006a0c - 2227 .set CYREG_B1_UDB07_08_A0, 0x40006a0e - 2228 .set CYREG_B1_UDB08_09_A0, 0x40006a10 - 2229 .set CYREG_B1_UDB09_10_A0, 0x40006a12 - 2230 .set CYREG_B1_UDB10_11_A0, 0x40006a14 - 2231 .set CYREG_B1_UDB11_12_A0, 0x40006a16 - 2232 .set CYREG_B1_UDB04_05_A1, 0x40006a28 - 2233 .set CYREG_B1_UDB05_06_A1, 0x40006a2a - 2234 .set CYREG_B1_UDB06_07_A1, 0x40006a2c - 2235 .set CYREG_B1_UDB07_08_A1, 0x40006a2e - 2236 .set CYREG_B1_UDB08_09_A1, 0x40006a30 - 2237 .set CYREG_B1_UDB09_10_A1, 0x40006a32 - 2238 .set CYREG_B1_UDB10_11_A1, 0x40006a34 - 2239 .set CYREG_B1_UDB11_12_A1, 0x40006a36 - 2240 .set CYREG_B1_UDB04_05_D0, 0x40006a48 - 2241 .set CYREG_B1_UDB05_06_D0, 0x40006a4a - 2242 .set CYREG_B1_UDB06_07_D0, 0x40006a4c - 2243 .set CYREG_B1_UDB07_08_D0, 0x40006a4e - 2244 .set CYREG_B1_UDB08_09_D0, 0x40006a50 - 2245 .set CYREG_B1_UDB09_10_D0, 0x40006a52 - 2246 .set CYREG_B1_UDB10_11_D0, 0x40006a54 - 2247 .set CYREG_B1_UDB11_12_D0, 0x40006a56 - 2248 .set CYREG_B1_UDB04_05_D1, 0x40006a68 - 2249 .set CYREG_B1_UDB05_06_D1, 0x40006a6a - 2250 .set CYREG_B1_UDB06_07_D1, 0x40006a6c - 2251 .set CYREG_B1_UDB07_08_D1, 0x40006a6e - 2252 .set CYREG_B1_UDB08_09_D1, 0x40006a70 - 2253 .set CYREG_B1_UDB09_10_D1, 0x40006a72 - 2254 .set CYREG_B1_UDB10_11_D1, 0x40006a74 - 2255 .set CYREG_B1_UDB11_12_D1, 0x40006a76 - 2256 .set CYREG_B1_UDB04_05_F0, 0x40006a88 - 2257 .set CYREG_B1_UDB05_06_F0, 0x40006a8a - 2258 .set CYREG_B1_UDB06_07_F0, 0x40006a8c - 2259 .set CYREG_B1_UDB07_08_F0, 0x40006a8e - 2260 .set CYREG_B1_UDB08_09_F0, 0x40006a90 - 2261 .set CYREG_B1_UDB09_10_F0, 0x40006a92 - 2262 .set CYREG_B1_UDB10_11_F0, 0x40006a94 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 135 - - - 2263 .set CYREG_B1_UDB11_12_F0, 0x40006a96 - 2264 .set CYREG_B1_UDB04_05_F1, 0x40006aa8 - 2265 .set CYREG_B1_UDB05_06_F1, 0x40006aaa - 2266 .set CYREG_B1_UDB06_07_F1, 0x40006aac - 2267 .set CYREG_B1_UDB07_08_F1, 0x40006aae - 2268 .set CYREG_B1_UDB08_09_F1, 0x40006ab0 - 2269 .set CYREG_B1_UDB09_10_F1, 0x40006ab2 - 2270 .set CYREG_B1_UDB10_11_F1, 0x40006ab4 - 2271 .set CYREG_B1_UDB11_12_F1, 0x40006ab6 - 2272 .set CYREG_B1_UDB04_05_ST, 0x40006ac8 - 2273 .set CYREG_B1_UDB05_06_ST, 0x40006aca - 2274 .set CYREG_B1_UDB06_07_ST, 0x40006acc - 2275 .set CYREG_B1_UDB07_08_ST, 0x40006ace - 2276 .set CYREG_B1_UDB08_09_ST, 0x40006ad0 - 2277 .set CYREG_B1_UDB09_10_ST, 0x40006ad2 - 2278 .set CYREG_B1_UDB10_11_ST, 0x40006ad4 - 2279 .set CYREG_B1_UDB11_12_ST, 0x40006ad6 - 2280 .set CYREG_B1_UDB04_05_CTL, 0x40006ae8 - 2281 .set CYREG_B1_UDB05_06_CTL, 0x40006aea - 2282 .set CYREG_B1_UDB06_07_CTL, 0x40006aec - 2283 .set CYREG_B1_UDB07_08_CTL, 0x40006aee - 2284 .set CYREG_B1_UDB08_09_CTL, 0x40006af0 - 2285 .set CYREG_B1_UDB09_10_CTL, 0x40006af2 - 2286 .set CYREG_B1_UDB10_11_CTL, 0x40006af4 - 2287 .set CYREG_B1_UDB11_12_CTL, 0x40006af6 - 2288 .set CYREG_B1_UDB04_05_MSK, 0x40006b08 - 2289 .set CYREG_B1_UDB05_06_MSK, 0x40006b0a - 2290 .set CYREG_B1_UDB06_07_MSK, 0x40006b0c - 2291 .set CYREG_B1_UDB07_08_MSK, 0x40006b0e - 2292 .set CYREG_B1_UDB08_09_MSK, 0x40006b10 - 2293 .set CYREG_B1_UDB09_10_MSK, 0x40006b12 - 2294 .set CYREG_B1_UDB10_11_MSK, 0x40006b14 - 2295 .set CYREG_B1_UDB11_12_MSK, 0x40006b16 - 2296 .set CYREG_B1_UDB04_05_ACTL, 0x40006b28 - 2297 .set CYREG_B1_UDB05_06_ACTL, 0x40006b2a - 2298 .set CYREG_B1_UDB06_07_ACTL, 0x40006b2c - 2299 .set CYREG_B1_UDB07_08_ACTL, 0x40006b2e - 2300 .set CYREG_B1_UDB08_09_ACTL, 0x40006b30 - 2301 .set CYREG_B1_UDB09_10_ACTL, 0x40006b32 - 2302 .set CYREG_B1_UDB10_11_ACTL, 0x40006b34 - 2303 .set CYREG_B1_UDB11_12_ACTL, 0x40006b36 - 2304 .set CYREG_B1_UDB04_05_MC, 0x40006b48 - 2305 .set CYREG_B1_UDB05_06_MC, 0x40006b4a - 2306 .set CYREG_B1_UDB06_07_MC, 0x40006b4c - 2307 .set CYREG_B1_UDB07_08_MC, 0x40006b4e - 2308 .set CYREG_B1_UDB08_09_MC, 0x40006b50 - 2309 .set CYREG_B1_UDB09_10_MC, 0x40006b52 - 2310 .set CYREG_B1_UDB10_11_MC, 0x40006b54 - 2311 .set CYREG_B1_UDB11_12_MC, 0x40006b56 - 2312 .set CYDEV_PHUB_BASE, 0x40007000 - 2313 .set CYDEV_PHUB_SIZE, 0x00000c00 - 2314 .set CYREG_PHUB_CFG, 0x40007000 - 2315 .set CYREG_PHUB_ERR, 0x40007004 - 2316 .set CYREG_PHUB_ERR_ADR, 0x40007008 - 2317 .set CYDEV_PHUB_CH0_BASE, 0x40007010 - 2318 .set CYDEV_PHUB_CH0_SIZE, 0x0000000c - 2319 .set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 136 - - - 2320 .set CYREG_PHUB_CH0_ACTION, 0x40007014 - 2321 .set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018 - 2322 .set CYDEV_PHUB_CH1_BASE, 0x40007020 - 2323 .set CYDEV_PHUB_CH1_SIZE, 0x0000000c - 2324 .set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020 - 2325 .set CYREG_PHUB_CH1_ACTION, 0x40007024 - 2326 .set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028 - 2327 .set CYDEV_PHUB_CH2_BASE, 0x40007030 - 2328 .set CYDEV_PHUB_CH2_SIZE, 0x0000000c - 2329 .set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030 - 2330 .set CYREG_PHUB_CH2_ACTION, 0x40007034 - 2331 .set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038 - 2332 .set CYDEV_PHUB_CH3_BASE, 0x40007040 - 2333 .set CYDEV_PHUB_CH3_SIZE, 0x0000000c - 2334 .set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040 - 2335 .set CYREG_PHUB_CH3_ACTION, 0x40007044 - 2336 .set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048 - 2337 .set CYDEV_PHUB_CH4_BASE, 0x40007050 - 2338 .set CYDEV_PHUB_CH4_SIZE, 0x0000000c - 2339 .set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050 - 2340 .set CYREG_PHUB_CH4_ACTION, 0x40007054 - 2341 .set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058 - 2342 .set CYDEV_PHUB_CH5_BASE, 0x40007060 - 2343 .set CYDEV_PHUB_CH5_SIZE, 0x0000000c - 2344 .set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060 - 2345 .set CYREG_PHUB_CH5_ACTION, 0x40007064 - 2346 .set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068 - 2347 .set CYDEV_PHUB_CH6_BASE, 0x40007070 - 2348 .set CYDEV_PHUB_CH6_SIZE, 0x0000000c - 2349 .set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070 - 2350 .set CYREG_PHUB_CH6_ACTION, 0x40007074 - 2351 .set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078 - 2352 .set CYDEV_PHUB_CH7_BASE, 0x40007080 - 2353 .set CYDEV_PHUB_CH7_SIZE, 0x0000000c - 2354 .set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080 - 2355 .set CYREG_PHUB_CH7_ACTION, 0x40007084 - 2356 .set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088 - 2357 .set CYDEV_PHUB_CH8_BASE, 0x40007090 - 2358 .set CYDEV_PHUB_CH8_SIZE, 0x0000000c - 2359 .set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090 - 2360 .set CYREG_PHUB_CH8_ACTION, 0x40007094 - 2361 .set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098 - 2362 .set CYDEV_PHUB_CH9_BASE, 0x400070a0 - 2363 .set CYDEV_PHUB_CH9_SIZE, 0x0000000c - 2364 .set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0 - 2365 .set CYREG_PHUB_CH9_ACTION, 0x400070a4 - 2366 .set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8 - 2367 .set CYDEV_PHUB_CH10_BASE, 0x400070b0 - 2368 .set CYDEV_PHUB_CH10_SIZE, 0x0000000c - 2369 .set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0 - 2370 .set CYREG_PHUB_CH10_ACTION, 0x400070b4 - 2371 .set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8 - 2372 .set CYDEV_PHUB_CH11_BASE, 0x400070c0 - 2373 .set CYDEV_PHUB_CH11_SIZE, 0x0000000c - 2374 .set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0 - 2375 .set CYREG_PHUB_CH11_ACTION, 0x400070c4 - 2376 .set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 137 - - - 2377 .set CYDEV_PHUB_CH12_BASE, 0x400070d0 - 2378 .set CYDEV_PHUB_CH12_SIZE, 0x0000000c - 2379 .set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0 - 2380 .set CYREG_PHUB_CH12_ACTION, 0x400070d4 - 2381 .set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8 - 2382 .set CYDEV_PHUB_CH13_BASE, 0x400070e0 - 2383 .set CYDEV_PHUB_CH13_SIZE, 0x0000000c - 2384 .set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0 - 2385 .set CYREG_PHUB_CH13_ACTION, 0x400070e4 - 2386 .set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8 - 2387 .set CYDEV_PHUB_CH14_BASE, 0x400070f0 - 2388 .set CYDEV_PHUB_CH14_SIZE, 0x0000000c - 2389 .set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0 - 2390 .set CYREG_PHUB_CH14_ACTION, 0x400070f4 - 2391 .set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8 - 2392 .set CYDEV_PHUB_CH15_BASE, 0x40007100 - 2393 .set CYDEV_PHUB_CH15_SIZE, 0x0000000c - 2394 .set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100 - 2395 .set CYREG_PHUB_CH15_ACTION, 0x40007104 - 2396 .set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108 - 2397 .set CYDEV_PHUB_CH16_BASE, 0x40007110 - 2398 .set CYDEV_PHUB_CH16_SIZE, 0x0000000c - 2399 .set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110 - 2400 .set CYREG_PHUB_CH16_ACTION, 0x40007114 - 2401 .set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118 - 2402 .set CYDEV_PHUB_CH17_BASE, 0x40007120 - 2403 .set CYDEV_PHUB_CH17_SIZE, 0x0000000c - 2404 .set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120 - 2405 .set CYREG_PHUB_CH17_ACTION, 0x40007124 - 2406 .set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128 - 2407 .set CYDEV_PHUB_CH18_BASE, 0x40007130 - 2408 .set CYDEV_PHUB_CH18_SIZE, 0x0000000c - 2409 .set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130 - 2410 .set CYREG_PHUB_CH18_ACTION, 0x40007134 - 2411 .set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138 - 2412 .set CYDEV_PHUB_CH19_BASE, 0x40007140 - 2413 .set CYDEV_PHUB_CH19_SIZE, 0x0000000c - 2414 .set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140 - 2415 .set CYREG_PHUB_CH19_ACTION, 0x40007144 - 2416 .set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148 - 2417 .set CYDEV_PHUB_CH20_BASE, 0x40007150 - 2418 .set CYDEV_PHUB_CH20_SIZE, 0x0000000c - 2419 .set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150 - 2420 .set CYREG_PHUB_CH20_ACTION, 0x40007154 - 2421 .set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158 - 2422 .set CYDEV_PHUB_CH21_BASE, 0x40007160 - 2423 .set CYDEV_PHUB_CH21_SIZE, 0x0000000c - 2424 .set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160 - 2425 .set CYREG_PHUB_CH21_ACTION, 0x40007164 - 2426 .set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168 - 2427 .set CYDEV_PHUB_CH22_BASE, 0x40007170 - 2428 .set CYDEV_PHUB_CH22_SIZE, 0x0000000c - 2429 .set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170 - 2430 .set CYREG_PHUB_CH22_ACTION, 0x40007174 - 2431 .set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178 - 2432 .set CYDEV_PHUB_CH23_BASE, 0x40007180 - 2433 .set CYDEV_PHUB_CH23_SIZE, 0x0000000c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 138 - - - 2434 .set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180 - 2435 .set CYREG_PHUB_CH23_ACTION, 0x40007184 - 2436 .set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188 - 2437 .set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 - 2438 .set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 - 2439 .set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600 - 2440 .set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604 - 2441 .set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 - 2442 .set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 - 2443 .set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608 - 2444 .set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c - 2445 .set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 - 2446 .set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 - 2447 .set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610 - 2448 .set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614 - 2449 .set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 - 2450 .set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 - 2451 .set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618 - 2452 .set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c - 2453 .set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 - 2454 .set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 - 2455 .set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620 - 2456 .set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624 - 2457 .set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 - 2458 .set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 - 2459 .set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628 - 2460 .set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c - 2461 .set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 - 2462 .set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 - 2463 .set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630 - 2464 .set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634 - 2465 .set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 - 2466 .set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 - 2467 .set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638 - 2468 .set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c - 2469 .set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 - 2470 .set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 - 2471 .set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640 - 2472 .set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644 - 2473 .set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 - 2474 .set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 - 2475 .set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648 - 2476 .set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c - 2477 .set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 - 2478 .set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 - 2479 .set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650 - 2480 .set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654 - 2481 .set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 - 2482 .set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 - 2483 .set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658 - 2484 .set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c - 2485 .set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 - 2486 .set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 - 2487 .set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660 - 2488 .set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664 - 2489 .set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 - 2490 .set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 139 - - - 2491 .set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668 - 2492 .set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c - 2493 .set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 - 2494 .set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 - 2495 .set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670 - 2496 .set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674 - 2497 .set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 - 2498 .set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 - 2499 .set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678 - 2500 .set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c - 2501 .set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 - 2502 .set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 - 2503 .set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680 - 2504 .set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684 - 2505 .set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 - 2506 .set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 - 2507 .set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688 - 2508 .set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c - 2509 .set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 - 2510 .set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 - 2511 .set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690 - 2512 .set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694 - 2513 .set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 - 2514 .set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 - 2515 .set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698 - 2516 .set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c - 2517 .set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 - 2518 .set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 - 2519 .set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0 - 2520 .set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4 - 2521 .set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 - 2522 .set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 - 2523 .set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8 - 2524 .set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac - 2525 .set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 - 2526 .set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 - 2527 .set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0 - 2528 .set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4 - 2529 .set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 - 2530 .set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 - 2531 .set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8 - 2532 .set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc - 2533 .set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 - 2534 .set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 - 2535 .set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800 - 2536 .set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804 - 2537 .set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 - 2538 .set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 - 2539 .set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808 - 2540 .set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c - 2541 .set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 - 2542 .set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 - 2543 .set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810 - 2544 .set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814 - 2545 .set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 - 2546 .set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 - 2547 .set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 140 - - - 2548 .set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c - 2549 .set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 - 2550 .set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 - 2551 .set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820 - 2552 .set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824 - 2553 .set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 - 2554 .set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 - 2555 .set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828 - 2556 .set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c - 2557 .set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 - 2558 .set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 - 2559 .set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830 - 2560 .set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834 - 2561 .set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 - 2562 .set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 - 2563 .set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838 - 2564 .set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c - 2565 .set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 - 2566 .set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 - 2567 .set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840 - 2568 .set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844 - 2569 .set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 - 2570 .set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 - 2571 .set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848 - 2572 .set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c - 2573 .set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 - 2574 .set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 - 2575 .set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850 - 2576 .set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854 - 2577 .set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 - 2578 .set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 - 2579 .set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858 - 2580 .set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c - 2581 .set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 - 2582 .set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 - 2583 .set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860 - 2584 .set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864 - 2585 .set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 - 2586 .set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 - 2587 .set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868 - 2588 .set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c - 2589 .set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 - 2590 .set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 - 2591 .set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870 - 2592 .set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874 - 2593 .set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 - 2594 .set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 - 2595 .set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878 - 2596 .set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c - 2597 .set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 - 2598 .set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 - 2599 .set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880 - 2600 .set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884 - 2601 .set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 - 2602 .set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 - 2603 .set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888 - 2604 .set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 141 - - - 2605 .set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 - 2606 .set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 - 2607 .set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890 - 2608 .set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894 - 2609 .set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 - 2610 .set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 - 2611 .set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898 - 2612 .set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c - 2613 .set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 - 2614 .set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 - 2615 .set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 - 2616 .set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 - 2617 .set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 - 2618 .set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 - 2619 .set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 - 2620 .set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac - 2621 .set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 - 2622 .set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 - 2623 .set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 - 2624 .set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 - 2625 .set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 - 2626 .set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 - 2627 .set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 - 2628 .set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc - 2629 .set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 - 2630 .set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 - 2631 .set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 - 2632 .set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 - 2633 .set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 - 2634 .set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 - 2635 .set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 - 2636 .set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc - 2637 .set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 - 2638 .set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 - 2639 .set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 - 2640 .set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 - 2641 .set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 - 2642 .set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 - 2643 .set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 - 2644 .set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc - 2645 .set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 - 2646 .set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 - 2647 .set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 - 2648 .set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 - 2649 .set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 - 2650 .set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 - 2651 .set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 - 2652 .set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec - 2653 .set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 - 2654 .set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 - 2655 .set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 - 2656 .set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 - 2657 .set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 - 2658 .set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 - 2659 .set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 - 2660 .set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc - 2661 .set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 142 - - - 2662 .set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 - 2663 .set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900 - 2664 .set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904 - 2665 .set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 - 2666 .set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 - 2667 .set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908 - 2668 .set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c - 2669 .set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 - 2670 .set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 - 2671 .set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910 - 2672 .set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914 - 2673 .set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 - 2674 .set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 - 2675 .set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918 - 2676 .set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c - 2677 .set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 - 2678 .set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 - 2679 .set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920 - 2680 .set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924 - 2681 .set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 - 2682 .set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 - 2683 .set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928 - 2684 .set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c - 2685 .set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 - 2686 .set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 - 2687 .set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930 - 2688 .set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934 - 2689 .set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 - 2690 .set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 - 2691 .set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938 - 2692 .set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c - 2693 .set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 - 2694 .set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 - 2695 .set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940 - 2696 .set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944 - 2697 .set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 - 2698 .set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 - 2699 .set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948 - 2700 .set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c - 2701 .set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 - 2702 .set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 - 2703 .set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950 - 2704 .set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954 - 2705 .set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 - 2706 .set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 - 2707 .set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958 - 2708 .set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c - 2709 .set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 - 2710 .set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 - 2711 .set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960 - 2712 .set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964 - 2713 .set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 - 2714 .set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 - 2715 .set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968 - 2716 .set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c - 2717 .set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 - 2718 .set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 143 - - - 2719 .set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970 - 2720 .set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974 - 2721 .set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 - 2722 .set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 - 2723 .set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978 - 2724 .set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c - 2725 .set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 - 2726 .set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 - 2727 .set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980 - 2728 .set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984 - 2729 .set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 - 2730 .set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 - 2731 .set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988 - 2732 .set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c - 2733 .set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 - 2734 .set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 - 2735 .set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990 - 2736 .set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994 - 2737 .set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 - 2738 .set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 - 2739 .set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998 - 2740 .set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c - 2741 .set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 - 2742 .set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 - 2743 .set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 - 2744 .set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 - 2745 .set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 - 2746 .set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 - 2747 .set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 - 2748 .set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac - 2749 .set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 - 2750 .set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 - 2751 .set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 - 2752 .set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 - 2753 .set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 - 2754 .set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 - 2755 .set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 - 2756 .set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc - 2757 .set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 - 2758 .set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 - 2759 .set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 - 2760 .set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 - 2761 .set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 - 2762 .set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 - 2763 .set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 - 2764 .set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc - 2765 .set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 - 2766 .set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 - 2767 .set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 - 2768 .set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 - 2769 .set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 - 2770 .set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 - 2771 .set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 - 2772 .set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc - 2773 .set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 - 2774 .set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 - 2775 .set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 144 - - - 2776 .set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 - 2777 .set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 - 2778 .set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 - 2779 .set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 - 2780 .set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec - 2781 .set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 - 2782 .set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 - 2783 .set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 - 2784 .set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 - 2785 .set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 - 2786 .set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 - 2787 .set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 - 2788 .set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc - 2789 .set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 - 2790 .set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 - 2791 .set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 - 2792 .set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 - 2793 .set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 - 2794 .set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 - 2795 .set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 - 2796 .set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c - 2797 .set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 - 2798 .set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 - 2799 .set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 - 2800 .set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 - 2801 .set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 - 2802 .set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 - 2803 .set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 - 2804 .set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c - 2805 .set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 - 2806 .set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 - 2807 .set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 - 2808 .set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 - 2809 .set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 - 2810 .set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 - 2811 .set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 - 2812 .set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c - 2813 .set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 - 2814 .set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 - 2815 .set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 - 2816 .set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 - 2817 .set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 - 2818 .set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 - 2819 .set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 - 2820 .set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c - 2821 .set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 - 2822 .set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 - 2823 .set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 - 2824 .set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 - 2825 .set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 - 2826 .set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 - 2827 .set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 - 2828 .set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c - 2829 .set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 - 2830 .set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 - 2831 .set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 - 2832 .set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 145 - - - 2833 .set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 - 2834 .set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 - 2835 .set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 - 2836 .set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c - 2837 .set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 - 2838 .set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 - 2839 .set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 - 2840 .set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 - 2841 .set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 - 2842 .set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 - 2843 .set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 - 2844 .set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c - 2845 .set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 - 2846 .set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 - 2847 .set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 - 2848 .set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 - 2849 .set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 - 2850 .set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 - 2851 .set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 - 2852 .set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c - 2853 .set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 - 2854 .set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 - 2855 .set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 - 2856 .set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 - 2857 .set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 - 2858 .set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 - 2859 .set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 - 2860 .set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c - 2861 .set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 - 2862 .set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 - 2863 .set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 - 2864 .set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 - 2865 .set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 - 2866 .set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 - 2867 .set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 - 2868 .set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c - 2869 .set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 - 2870 .set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 - 2871 .set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 - 2872 .set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 - 2873 .set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 - 2874 .set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 - 2875 .set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 - 2876 .set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac - 2877 .set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 - 2878 .set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 - 2879 .set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 - 2880 .set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 - 2881 .set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 - 2882 .set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 - 2883 .set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 - 2884 .set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc - 2885 .set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 - 2886 .set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 - 2887 .set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 - 2888 .set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 - 2889 .set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 146 - - - 2890 .set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 - 2891 .set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 - 2892 .set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc - 2893 .set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 - 2894 .set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 - 2895 .set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 - 2896 .set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 - 2897 .set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 - 2898 .set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 - 2899 .set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 - 2900 .set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc - 2901 .set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 - 2902 .set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 - 2903 .set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 - 2904 .set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 - 2905 .set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 - 2906 .set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 - 2907 .set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 - 2908 .set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec - 2909 .set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 - 2910 .set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 - 2911 .set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 - 2912 .set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 - 2913 .set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 - 2914 .set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 - 2915 .set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 - 2916 .set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc - 2917 .set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 - 2918 .set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 - 2919 .set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 - 2920 .set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 - 2921 .set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 - 2922 .set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 - 2923 .set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 - 2924 .set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c - 2925 .set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 - 2926 .set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 - 2927 .set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 - 2928 .set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 - 2929 .set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 - 2930 .set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 - 2931 .set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 - 2932 .set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c - 2933 .set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 - 2934 .set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 - 2935 .set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 - 2936 .set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 - 2937 .set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 - 2938 .set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 - 2939 .set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 - 2940 .set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c - 2941 .set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 - 2942 .set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 - 2943 .set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 - 2944 .set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 - 2945 .set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 - 2946 .set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 147 - - - 2947 .set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 - 2948 .set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c - 2949 .set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 - 2950 .set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 - 2951 .set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 - 2952 .set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 - 2953 .set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 - 2954 .set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 - 2955 .set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 - 2956 .set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c - 2957 .set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 - 2958 .set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 - 2959 .set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 - 2960 .set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 - 2961 .set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 - 2962 .set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 - 2963 .set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 - 2964 .set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c - 2965 .set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 - 2966 .set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 - 2967 .set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 - 2968 .set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 - 2969 .set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 - 2970 .set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 - 2971 .set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 - 2972 .set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c - 2973 .set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 - 2974 .set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 - 2975 .set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 - 2976 .set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 - 2977 .set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 - 2978 .set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 - 2979 .set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 - 2980 .set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c - 2981 .set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 - 2982 .set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 - 2983 .set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 - 2984 .set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 - 2985 .set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 - 2986 .set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 - 2987 .set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 - 2988 .set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c - 2989 .set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 - 2990 .set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 - 2991 .set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 - 2992 .set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 - 2993 .set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 - 2994 .set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 - 2995 .set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 - 2996 .set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c - 2997 .set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 - 2998 .set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 - 2999 .set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 - 3000 .set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 - 3001 .set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 - 3002 .set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 - 3003 .set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 148 - - - 3004 .set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac - 3005 .set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 - 3006 .set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 - 3007 .set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 - 3008 .set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 - 3009 .set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 - 3010 .set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 - 3011 .set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 - 3012 .set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc - 3013 .set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 - 3014 .set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 - 3015 .set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 - 3016 .set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 - 3017 .set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 - 3018 .set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 - 3019 .set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 - 3020 .set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc - 3021 .set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 - 3022 .set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 - 3023 .set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 - 3024 .set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 - 3025 .set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 - 3026 .set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 - 3027 .set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 - 3028 .set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc - 3029 .set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 - 3030 .set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 - 3031 .set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 - 3032 .set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 - 3033 .set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 - 3034 .set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 - 3035 .set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 - 3036 .set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec - 3037 .set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 - 3038 .set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 - 3039 .set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 - 3040 .set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 - 3041 .set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 - 3042 .set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 - 3043 .set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 - 3044 .set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc - 3045 .set CYDEV_EE_BASE, 0x40008000 - 3046 .set CYDEV_EE_SIZE, 0x00000800 - 3047 .set CYREG_EE_DATA_MBASE, 0x40008000 - 3048 .set CYREG_EE_DATA_MSIZE, 0x00000800 - 3049 .set CYDEV_CAN0_BASE, 0x4000a000 - 3050 .set CYDEV_CAN0_SIZE, 0x000002a0 - 3051 .set CYDEV_CAN0_CSR_BASE, 0x4000a000 - 3052 .set CYDEV_CAN0_CSR_SIZE, 0x00000018 - 3053 .set CYREG_CAN0_CSR_INT_SR, 0x4000a000 - 3054 .set CYREG_CAN0_CSR_INT_EN, 0x4000a004 - 3055 .set CYREG_CAN0_CSR_BUF_SR, 0x4000a008 - 3056 .set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c - 3057 .set CYREG_CAN0_CSR_CMD, 0x4000a010 - 3058 .set CYREG_CAN0_CSR_CFG, 0x4000a014 - 3059 .set CYDEV_CAN0_TX0_BASE, 0x4000a020 - 3060 .set CYDEV_CAN0_TX0_SIZE, 0x00000010 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 149 - - - 3061 .set CYREG_CAN0_TX0_CMD, 0x4000a020 - 3062 .set CYREG_CAN0_TX0_ID, 0x4000a024 - 3063 .set CYREG_CAN0_TX0_DH, 0x4000a028 - 3064 .set CYREG_CAN0_TX0_DL, 0x4000a02c - 3065 .set CYDEV_CAN0_TX1_BASE, 0x4000a030 - 3066 .set CYDEV_CAN0_TX1_SIZE, 0x00000010 - 3067 .set CYREG_CAN0_TX1_CMD, 0x4000a030 - 3068 .set CYREG_CAN0_TX1_ID, 0x4000a034 - 3069 .set CYREG_CAN0_TX1_DH, 0x4000a038 - 3070 .set CYREG_CAN0_TX1_DL, 0x4000a03c - 3071 .set CYDEV_CAN0_TX2_BASE, 0x4000a040 - 3072 .set CYDEV_CAN0_TX2_SIZE, 0x00000010 - 3073 .set CYREG_CAN0_TX2_CMD, 0x4000a040 - 3074 .set CYREG_CAN0_TX2_ID, 0x4000a044 - 3075 .set CYREG_CAN0_TX2_DH, 0x4000a048 - 3076 .set CYREG_CAN0_TX2_DL, 0x4000a04c - 3077 .set CYDEV_CAN0_TX3_BASE, 0x4000a050 - 3078 .set CYDEV_CAN0_TX3_SIZE, 0x00000010 - 3079 .set CYREG_CAN0_TX3_CMD, 0x4000a050 - 3080 .set CYREG_CAN0_TX3_ID, 0x4000a054 - 3081 .set CYREG_CAN0_TX3_DH, 0x4000a058 - 3082 .set CYREG_CAN0_TX3_DL, 0x4000a05c - 3083 .set CYDEV_CAN0_TX4_BASE, 0x4000a060 - 3084 .set CYDEV_CAN0_TX4_SIZE, 0x00000010 - 3085 .set CYREG_CAN0_TX4_CMD, 0x4000a060 - 3086 .set CYREG_CAN0_TX4_ID, 0x4000a064 - 3087 .set CYREG_CAN0_TX4_DH, 0x4000a068 - 3088 .set CYREG_CAN0_TX4_DL, 0x4000a06c - 3089 .set CYDEV_CAN0_TX5_BASE, 0x4000a070 - 3090 .set CYDEV_CAN0_TX5_SIZE, 0x00000010 - 3091 .set CYREG_CAN0_TX5_CMD, 0x4000a070 - 3092 .set CYREG_CAN0_TX5_ID, 0x4000a074 - 3093 .set CYREG_CAN0_TX5_DH, 0x4000a078 - 3094 .set CYREG_CAN0_TX5_DL, 0x4000a07c - 3095 .set CYDEV_CAN0_TX6_BASE, 0x4000a080 - 3096 .set CYDEV_CAN0_TX6_SIZE, 0x00000010 - 3097 .set CYREG_CAN0_TX6_CMD, 0x4000a080 - 3098 .set CYREG_CAN0_TX6_ID, 0x4000a084 - 3099 .set CYREG_CAN0_TX6_DH, 0x4000a088 - 3100 .set CYREG_CAN0_TX6_DL, 0x4000a08c - 3101 .set CYDEV_CAN0_TX7_BASE, 0x4000a090 - 3102 .set CYDEV_CAN0_TX7_SIZE, 0x00000010 - 3103 .set CYREG_CAN0_TX7_CMD, 0x4000a090 - 3104 .set CYREG_CAN0_TX7_ID, 0x4000a094 - 3105 .set CYREG_CAN0_TX7_DH, 0x4000a098 - 3106 .set CYREG_CAN0_TX7_DL, 0x4000a09c - 3107 .set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 - 3108 .set CYDEV_CAN0_RX0_SIZE, 0x00000020 - 3109 .set CYREG_CAN0_RX0_CMD, 0x4000a0a0 - 3110 .set CYREG_CAN0_RX0_ID, 0x4000a0a4 - 3111 .set CYREG_CAN0_RX0_DH, 0x4000a0a8 - 3112 .set CYREG_CAN0_RX0_DL, 0x4000a0ac - 3113 .set CYREG_CAN0_RX0_AMR, 0x4000a0b0 - 3114 .set CYREG_CAN0_RX0_ACR, 0x4000a0b4 - 3115 .set CYREG_CAN0_RX0_AMRD, 0x4000a0b8 - 3116 .set CYREG_CAN0_RX0_ACRD, 0x4000a0bc - 3117 .set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 150 - - - 3118 .set CYDEV_CAN0_RX1_SIZE, 0x00000020 - 3119 .set CYREG_CAN0_RX1_CMD, 0x4000a0c0 - 3120 .set CYREG_CAN0_RX1_ID, 0x4000a0c4 - 3121 .set CYREG_CAN0_RX1_DH, 0x4000a0c8 - 3122 .set CYREG_CAN0_RX1_DL, 0x4000a0cc - 3123 .set CYREG_CAN0_RX1_AMR, 0x4000a0d0 - 3124 .set CYREG_CAN0_RX1_ACR, 0x4000a0d4 - 3125 .set CYREG_CAN0_RX1_AMRD, 0x4000a0d8 - 3126 .set CYREG_CAN0_RX1_ACRD, 0x4000a0dc - 3127 .set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 - 3128 .set CYDEV_CAN0_RX2_SIZE, 0x00000020 - 3129 .set CYREG_CAN0_RX2_CMD, 0x4000a0e0 - 3130 .set CYREG_CAN0_RX2_ID, 0x4000a0e4 - 3131 .set CYREG_CAN0_RX2_DH, 0x4000a0e8 - 3132 .set CYREG_CAN0_RX2_DL, 0x4000a0ec - 3133 .set CYREG_CAN0_RX2_AMR, 0x4000a0f0 - 3134 .set CYREG_CAN0_RX2_ACR, 0x4000a0f4 - 3135 .set CYREG_CAN0_RX2_AMRD, 0x4000a0f8 - 3136 .set CYREG_CAN0_RX2_ACRD, 0x4000a0fc - 3137 .set CYDEV_CAN0_RX3_BASE, 0x4000a100 - 3138 .set CYDEV_CAN0_RX3_SIZE, 0x00000020 - 3139 .set CYREG_CAN0_RX3_CMD, 0x4000a100 - 3140 .set CYREG_CAN0_RX3_ID, 0x4000a104 - 3141 .set CYREG_CAN0_RX3_DH, 0x4000a108 - 3142 .set CYREG_CAN0_RX3_DL, 0x4000a10c - 3143 .set CYREG_CAN0_RX3_AMR, 0x4000a110 - 3144 .set CYREG_CAN0_RX3_ACR, 0x4000a114 - 3145 .set CYREG_CAN0_RX3_AMRD, 0x4000a118 - 3146 .set CYREG_CAN0_RX3_ACRD, 0x4000a11c - 3147 .set CYDEV_CAN0_RX4_BASE, 0x4000a120 - 3148 .set CYDEV_CAN0_RX4_SIZE, 0x00000020 - 3149 .set CYREG_CAN0_RX4_CMD, 0x4000a120 - 3150 .set CYREG_CAN0_RX4_ID, 0x4000a124 - 3151 .set CYREG_CAN0_RX4_DH, 0x4000a128 - 3152 .set CYREG_CAN0_RX4_DL, 0x4000a12c - 3153 .set CYREG_CAN0_RX4_AMR, 0x4000a130 - 3154 .set CYREG_CAN0_RX4_ACR, 0x4000a134 - 3155 .set CYREG_CAN0_RX4_AMRD, 0x4000a138 - 3156 .set CYREG_CAN0_RX4_ACRD, 0x4000a13c - 3157 .set CYDEV_CAN0_RX5_BASE, 0x4000a140 - 3158 .set CYDEV_CAN0_RX5_SIZE, 0x00000020 - 3159 .set CYREG_CAN0_RX5_CMD, 0x4000a140 - 3160 .set CYREG_CAN0_RX5_ID, 0x4000a144 - 3161 .set CYREG_CAN0_RX5_DH, 0x4000a148 - 3162 .set CYREG_CAN0_RX5_DL, 0x4000a14c - 3163 .set CYREG_CAN0_RX5_AMR, 0x4000a150 - 3164 .set CYREG_CAN0_RX5_ACR, 0x4000a154 - 3165 .set CYREG_CAN0_RX5_AMRD, 0x4000a158 - 3166 .set CYREG_CAN0_RX5_ACRD, 0x4000a15c - 3167 .set CYDEV_CAN0_RX6_BASE, 0x4000a160 - 3168 .set CYDEV_CAN0_RX6_SIZE, 0x00000020 - 3169 .set CYREG_CAN0_RX6_CMD, 0x4000a160 - 3170 .set CYREG_CAN0_RX6_ID, 0x4000a164 - 3171 .set CYREG_CAN0_RX6_DH, 0x4000a168 - 3172 .set CYREG_CAN0_RX6_DL, 0x4000a16c - 3173 .set CYREG_CAN0_RX6_AMR, 0x4000a170 - 3174 .set CYREG_CAN0_RX6_ACR, 0x4000a174 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 151 - - - 3175 .set CYREG_CAN0_RX6_AMRD, 0x4000a178 - 3176 .set CYREG_CAN0_RX6_ACRD, 0x4000a17c - 3177 .set CYDEV_CAN0_RX7_BASE, 0x4000a180 - 3178 .set CYDEV_CAN0_RX7_SIZE, 0x00000020 - 3179 .set CYREG_CAN0_RX7_CMD, 0x4000a180 - 3180 .set CYREG_CAN0_RX7_ID, 0x4000a184 - 3181 .set CYREG_CAN0_RX7_DH, 0x4000a188 - 3182 .set CYREG_CAN0_RX7_DL, 0x4000a18c - 3183 .set CYREG_CAN0_RX7_AMR, 0x4000a190 - 3184 .set CYREG_CAN0_RX7_ACR, 0x4000a194 - 3185 .set CYREG_CAN0_RX7_AMRD, 0x4000a198 - 3186 .set CYREG_CAN0_RX7_ACRD, 0x4000a19c - 3187 .set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 - 3188 .set CYDEV_CAN0_RX8_SIZE, 0x00000020 - 3189 .set CYREG_CAN0_RX8_CMD, 0x4000a1a0 - 3190 .set CYREG_CAN0_RX8_ID, 0x4000a1a4 - 3191 .set CYREG_CAN0_RX8_DH, 0x4000a1a8 - 3192 .set CYREG_CAN0_RX8_DL, 0x4000a1ac - 3193 .set CYREG_CAN0_RX8_AMR, 0x4000a1b0 - 3194 .set CYREG_CAN0_RX8_ACR, 0x4000a1b4 - 3195 .set CYREG_CAN0_RX8_AMRD, 0x4000a1b8 - 3196 .set CYREG_CAN0_RX8_ACRD, 0x4000a1bc - 3197 .set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 - 3198 .set CYDEV_CAN0_RX9_SIZE, 0x00000020 - 3199 .set CYREG_CAN0_RX9_CMD, 0x4000a1c0 - 3200 .set CYREG_CAN0_RX9_ID, 0x4000a1c4 - 3201 .set CYREG_CAN0_RX9_DH, 0x4000a1c8 - 3202 .set CYREG_CAN0_RX9_DL, 0x4000a1cc - 3203 .set CYREG_CAN0_RX9_AMR, 0x4000a1d0 - 3204 .set CYREG_CAN0_RX9_ACR, 0x4000a1d4 - 3205 .set CYREG_CAN0_RX9_AMRD, 0x4000a1d8 - 3206 .set CYREG_CAN0_RX9_ACRD, 0x4000a1dc - 3207 .set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 - 3208 .set CYDEV_CAN0_RX10_SIZE, 0x00000020 - 3209 .set CYREG_CAN0_RX10_CMD, 0x4000a1e0 - 3210 .set CYREG_CAN0_RX10_ID, 0x4000a1e4 - 3211 .set CYREG_CAN0_RX10_DH, 0x4000a1e8 - 3212 .set CYREG_CAN0_RX10_DL, 0x4000a1ec - 3213 .set CYREG_CAN0_RX10_AMR, 0x4000a1f0 - 3214 .set CYREG_CAN0_RX10_ACR, 0x4000a1f4 - 3215 .set CYREG_CAN0_RX10_AMRD, 0x4000a1f8 - 3216 .set CYREG_CAN0_RX10_ACRD, 0x4000a1fc - 3217 .set CYDEV_CAN0_RX11_BASE, 0x4000a200 - 3218 .set CYDEV_CAN0_RX11_SIZE, 0x00000020 - 3219 .set CYREG_CAN0_RX11_CMD, 0x4000a200 - 3220 .set CYREG_CAN0_RX11_ID, 0x4000a204 - 3221 .set CYREG_CAN0_RX11_DH, 0x4000a208 - 3222 .set CYREG_CAN0_RX11_DL, 0x4000a20c - 3223 .set CYREG_CAN0_RX11_AMR, 0x4000a210 - 3224 .set CYREG_CAN0_RX11_ACR, 0x4000a214 - 3225 .set CYREG_CAN0_RX11_AMRD, 0x4000a218 - 3226 .set CYREG_CAN0_RX11_ACRD, 0x4000a21c - 3227 .set CYDEV_CAN0_RX12_BASE, 0x4000a220 - 3228 .set CYDEV_CAN0_RX12_SIZE, 0x00000020 - 3229 .set CYREG_CAN0_RX12_CMD, 0x4000a220 - 3230 .set CYREG_CAN0_RX12_ID, 0x4000a224 - 3231 .set CYREG_CAN0_RX12_DH, 0x4000a228 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 152 - - - 3232 .set CYREG_CAN0_RX12_DL, 0x4000a22c - 3233 .set CYREG_CAN0_RX12_AMR, 0x4000a230 - 3234 .set CYREG_CAN0_RX12_ACR, 0x4000a234 - 3235 .set CYREG_CAN0_RX12_AMRD, 0x4000a238 - 3236 .set CYREG_CAN0_RX12_ACRD, 0x4000a23c - 3237 .set CYDEV_CAN0_RX13_BASE, 0x4000a240 - 3238 .set CYDEV_CAN0_RX13_SIZE, 0x00000020 - 3239 .set CYREG_CAN0_RX13_CMD, 0x4000a240 - 3240 .set CYREG_CAN0_RX13_ID, 0x4000a244 - 3241 .set CYREG_CAN0_RX13_DH, 0x4000a248 - 3242 .set CYREG_CAN0_RX13_DL, 0x4000a24c - 3243 .set CYREG_CAN0_RX13_AMR, 0x4000a250 - 3244 .set CYREG_CAN0_RX13_ACR, 0x4000a254 - 3245 .set CYREG_CAN0_RX13_AMRD, 0x4000a258 - 3246 .set CYREG_CAN0_RX13_ACRD, 0x4000a25c - 3247 .set CYDEV_CAN0_RX14_BASE, 0x4000a260 - 3248 .set CYDEV_CAN0_RX14_SIZE, 0x00000020 - 3249 .set CYREG_CAN0_RX14_CMD, 0x4000a260 - 3250 .set CYREG_CAN0_RX14_ID, 0x4000a264 - 3251 .set CYREG_CAN0_RX14_DH, 0x4000a268 - 3252 .set CYREG_CAN0_RX14_DL, 0x4000a26c - 3253 .set CYREG_CAN0_RX14_AMR, 0x4000a270 - 3254 .set CYREG_CAN0_RX14_ACR, 0x4000a274 - 3255 .set CYREG_CAN0_RX14_AMRD, 0x4000a278 - 3256 .set CYREG_CAN0_RX14_ACRD, 0x4000a27c - 3257 .set CYDEV_CAN0_RX15_BASE, 0x4000a280 - 3258 .set CYDEV_CAN0_RX15_SIZE, 0x00000020 - 3259 .set CYREG_CAN0_RX15_CMD, 0x4000a280 - 3260 .set CYREG_CAN0_RX15_ID, 0x4000a284 - 3261 .set CYREG_CAN0_RX15_DH, 0x4000a288 - 3262 .set CYREG_CAN0_RX15_DL, 0x4000a28c - 3263 .set CYREG_CAN0_RX15_AMR, 0x4000a290 - 3264 .set CYREG_CAN0_RX15_ACR, 0x4000a294 - 3265 .set CYREG_CAN0_RX15_AMRD, 0x4000a298 - 3266 .set CYREG_CAN0_RX15_ACRD, 0x4000a29c - 3267 .set CYDEV_DFB0_BASE, 0x4000c000 - 3268 .set CYDEV_DFB0_SIZE, 0x000007b5 - 3269 .set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 - 3270 .set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 - 3271 .set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 - 3272 .set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 - 3273 .set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 - 3274 .set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 - 3275 .set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 - 3276 .set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 - 3277 .set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 - 3278 .set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 - 3279 .set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 - 3280 .set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 - 3281 .set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 - 3282 .set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 - 3283 .set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 - 3284 .set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 - 3285 .set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 - 3286 .set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 - 3287 .set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 - 3288 .set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 153 - - - 3289 .set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 - 3290 .set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 - 3291 .set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 - 3292 .set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 - 3293 .set CYREG_DFB0_CR, 0x4000c780 - 3294 .set CYREG_DFB0_SR, 0x4000c784 - 3295 .set CYREG_DFB0_RAM_EN, 0x4000c788 - 3296 .set CYREG_DFB0_RAM_DIR, 0x4000c78c - 3297 .set CYREG_DFB0_SEMA, 0x4000c790 - 3298 .set CYREG_DFB0_DSI_CTRL, 0x4000c794 - 3299 .set CYREG_DFB0_INT_CTRL, 0x4000c798 - 3300 .set CYREG_DFB0_DMA_CTRL, 0x4000c79c - 3301 .set CYREG_DFB0_STAGEA, 0x4000c7a0 - 3302 .set CYREG_DFB0_STAGEAM, 0x4000c7a1 - 3303 .set CYREG_DFB0_STAGEAH, 0x4000c7a2 - 3304 .set CYREG_DFB0_STAGEB, 0x4000c7a4 - 3305 .set CYREG_DFB0_STAGEBM, 0x4000c7a5 - 3306 .set CYREG_DFB0_STAGEBH, 0x4000c7a6 - 3307 .set CYREG_DFB0_HOLDA, 0x4000c7a8 - 3308 .set CYREG_DFB0_HOLDAM, 0x4000c7a9 - 3309 .set CYREG_DFB0_HOLDAH, 0x4000c7aa - 3310 .set CYREG_DFB0_HOLDAS, 0x4000c7ab - 3311 .set CYREG_DFB0_HOLDB, 0x4000c7ac - 3312 .set CYREG_DFB0_HOLDBM, 0x4000c7ad - 3313 .set CYREG_DFB0_HOLDBH, 0x4000c7ae - 3314 .set CYREG_DFB0_HOLDBS, 0x4000c7af - 3315 .set CYREG_DFB0_COHER, 0x4000c7b0 - 3316 .set CYREG_DFB0_DALIGN, 0x4000c7b4 - 3317 .set CYDEV_UCFG_BASE, 0x40010000 - 3318 .set CYDEV_UCFG_SIZE, 0x00005040 - 3319 .set CYDEV_UCFG_B0_BASE, 0x40010000 - 3320 .set CYDEV_UCFG_B0_SIZE, 0x00000fef - 3321 .set CYDEV_UCFG_B0_P0_BASE, 0x40010000 - 3322 .set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef - 3323 .set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 - 3324 .set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 - 3325 .set CYREG_B0_P0_U0_PLD_IT0, 0x40010000 - 3326 .set CYREG_B0_P0_U0_PLD_IT1, 0x40010004 - 3327 .set CYREG_B0_P0_U0_PLD_IT2, 0x40010008 - 3328 .set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c - 3329 .set CYREG_B0_P0_U0_PLD_IT4, 0x40010010 - 3330 .set CYREG_B0_P0_U0_PLD_IT5, 0x40010014 - 3331 .set CYREG_B0_P0_U0_PLD_IT6, 0x40010018 - 3332 .set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c - 3333 .set CYREG_B0_P0_U0_PLD_IT8, 0x40010020 - 3334 .set CYREG_B0_P0_U0_PLD_IT9, 0x40010024 - 3335 .set CYREG_B0_P0_U0_PLD_IT10, 0x40010028 - 3336 .set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c - 3337 .set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030 - 3338 .set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032 - 3339 .set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034 - 3340 .set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036 - 3341 .set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 - 3342 .set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a - 3343 .set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c - 3344 .set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e - 3345 .set CYREG_B0_P0_U0_CFG0, 0x40010040 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 154 - - - 3346 .set CYREG_B0_P0_U0_CFG1, 0x40010041 - 3347 .set CYREG_B0_P0_U0_CFG2, 0x40010042 - 3348 .set CYREG_B0_P0_U0_CFG3, 0x40010043 - 3349 .set CYREG_B0_P0_U0_CFG4, 0x40010044 - 3350 .set CYREG_B0_P0_U0_CFG5, 0x40010045 - 3351 .set CYREG_B0_P0_U0_CFG6, 0x40010046 - 3352 .set CYREG_B0_P0_U0_CFG7, 0x40010047 - 3353 .set CYREG_B0_P0_U0_CFG8, 0x40010048 - 3354 .set CYREG_B0_P0_U0_CFG9, 0x40010049 - 3355 .set CYREG_B0_P0_U0_CFG10, 0x4001004a - 3356 .set CYREG_B0_P0_U0_CFG11, 0x4001004b - 3357 .set CYREG_B0_P0_U0_CFG12, 0x4001004c - 3358 .set CYREG_B0_P0_U0_CFG13, 0x4001004d - 3359 .set CYREG_B0_P0_U0_CFG14, 0x4001004e - 3360 .set CYREG_B0_P0_U0_CFG15, 0x4001004f - 3361 .set CYREG_B0_P0_U0_CFG16, 0x40010050 - 3362 .set CYREG_B0_P0_U0_CFG17, 0x40010051 - 3363 .set CYREG_B0_P0_U0_CFG18, 0x40010052 - 3364 .set CYREG_B0_P0_U0_CFG19, 0x40010053 - 3365 .set CYREG_B0_P0_U0_CFG20, 0x40010054 - 3366 .set CYREG_B0_P0_U0_CFG21, 0x40010055 - 3367 .set CYREG_B0_P0_U0_CFG22, 0x40010056 - 3368 .set CYREG_B0_P0_U0_CFG23, 0x40010057 - 3369 .set CYREG_B0_P0_U0_CFG24, 0x40010058 - 3370 .set CYREG_B0_P0_U0_CFG25, 0x40010059 - 3371 .set CYREG_B0_P0_U0_CFG26, 0x4001005a - 3372 .set CYREG_B0_P0_U0_CFG27, 0x4001005b - 3373 .set CYREG_B0_P0_U0_CFG28, 0x4001005c - 3374 .set CYREG_B0_P0_U0_CFG29, 0x4001005d - 3375 .set CYREG_B0_P0_U0_CFG30, 0x4001005e - 3376 .set CYREG_B0_P0_U0_CFG31, 0x4001005f - 3377 .set CYREG_B0_P0_U0_DCFG0, 0x40010060 - 3378 .set CYREG_B0_P0_U0_DCFG1, 0x40010062 - 3379 .set CYREG_B0_P0_U0_DCFG2, 0x40010064 - 3380 .set CYREG_B0_P0_U0_DCFG3, 0x40010066 - 3381 .set CYREG_B0_P0_U0_DCFG4, 0x40010068 - 3382 .set CYREG_B0_P0_U0_DCFG5, 0x4001006a - 3383 .set CYREG_B0_P0_U0_DCFG6, 0x4001006c - 3384 .set CYREG_B0_P0_U0_DCFG7, 0x4001006e - 3385 .set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 - 3386 .set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 - 3387 .set CYREG_B0_P0_U1_PLD_IT0, 0x40010080 - 3388 .set CYREG_B0_P0_U1_PLD_IT1, 0x40010084 - 3389 .set CYREG_B0_P0_U1_PLD_IT2, 0x40010088 - 3390 .set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c - 3391 .set CYREG_B0_P0_U1_PLD_IT4, 0x40010090 - 3392 .set CYREG_B0_P0_U1_PLD_IT5, 0x40010094 - 3393 .set CYREG_B0_P0_U1_PLD_IT6, 0x40010098 - 3394 .set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c - 3395 .set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0 - 3396 .set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4 - 3397 .set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8 - 3398 .set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac - 3399 .set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0 - 3400 .set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2 - 3401 .set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4 - 3402 .set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 155 - - - 3403 .set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 - 3404 .set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba - 3405 .set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc - 3406 .set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be - 3407 .set CYREG_B0_P0_U1_CFG0, 0x400100c0 - 3408 .set CYREG_B0_P0_U1_CFG1, 0x400100c1 - 3409 .set CYREG_B0_P0_U1_CFG2, 0x400100c2 - 3410 .set CYREG_B0_P0_U1_CFG3, 0x400100c3 - 3411 .set CYREG_B0_P0_U1_CFG4, 0x400100c4 - 3412 .set CYREG_B0_P0_U1_CFG5, 0x400100c5 - 3413 .set CYREG_B0_P0_U1_CFG6, 0x400100c6 - 3414 .set CYREG_B0_P0_U1_CFG7, 0x400100c7 - 3415 .set CYREG_B0_P0_U1_CFG8, 0x400100c8 - 3416 .set CYREG_B0_P0_U1_CFG9, 0x400100c9 - 3417 .set CYREG_B0_P0_U1_CFG10, 0x400100ca - 3418 .set CYREG_B0_P0_U1_CFG11, 0x400100cb - 3419 .set CYREG_B0_P0_U1_CFG12, 0x400100cc - 3420 .set CYREG_B0_P0_U1_CFG13, 0x400100cd - 3421 .set CYREG_B0_P0_U1_CFG14, 0x400100ce - 3422 .set CYREG_B0_P0_U1_CFG15, 0x400100cf - 3423 .set CYREG_B0_P0_U1_CFG16, 0x400100d0 - 3424 .set CYREG_B0_P0_U1_CFG17, 0x400100d1 - 3425 .set CYREG_B0_P0_U1_CFG18, 0x400100d2 - 3426 .set CYREG_B0_P0_U1_CFG19, 0x400100d3 - 3427 .set CYREG_B0_P0_U1_CFG20, 0x400100d4 - 3428 .set CYREG_B0_P0_U1_CFG21, 0x400100d5 - 3429 .set CYREG_B0_P0_U1_CFG22, 0x400100d6 - 3430 .set CYREG_B0_P0_U1_CFG23, 0x400100d7 - 3431 .set CYREG_B0_P0_U1_CFG24, 0x400100d8 - 3432 .set CYREG_B0_P0_U1_CFG25, 0x400100d9 - 3433 .set CYREG_B0_P0_U1_CFG26, 0x400100da - 3434 .set CYREG_B0_P0_U1_CFG27, 0x400100db - 3435 .set CYREG_B0_P0_U1_CFG28, 0x400100dc - 3436 .set CYREG_B0_P0_U1_CFG29, 0x400100dd - 3437 .set CYREG_B0_P0_U1_CFG30, 0x400100de - 3438 .set CYREG_B0_P0_U1_CFG31, 0x400100df - 3439 .set CYREG_B0_P0_U1_DCFG0, 0x400100e0 - 3440 .set CYREG_B0_P0_U1_DCFG1, 0x400100e2 - 3441 .set CYREG_B0_P0_U1_DCFG2, 0x400100e4 - 3442 .set CYREG_B0_P0_U1_DCFG3, 0x400100e6 - 3443 .set CYREG_B0_P0_U1_DCFG4, 0x400100e8 - 3444 .set CYREG_B0_P0_U1_DCFG5, 0x400100ea - 3445 .set CYREG_B0_P0_U1_DCFG6, 0x400100ec - 3446 .set CYREG_B0_P0_U1_DCFG7, 0x400100ee - 3447 .set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 - 3448 .set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef - 3449 .set CYDEV_UCFG_B0_P1_BASE, 0x40010200 - 3450 .set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef - 3451 .set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 - 3452 .set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 - 3453 .set CYREG_B0_P1_U0_PLD_IT0, 0x40010200 - 3454 .set CYREG_B0_P1_U0_PLD_IT1, 0x40010204 - 3455 .set CYREG_B0_P1_U0_PLD_IT2, 0x40010208 - 3456 .set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c - 3457 .set CYREG_B0_P1_U0_PLD_IT4, 0x40010210 - 3458 .set CYREG_B0_P1_U0_PLD_IT5, 0x40010214 - 3459 .set CYREG_B0_P1_U0_PLD_IT6, 0x40010218 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 156 - - - 3460 .set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c - 3461 .set CYREG_B0_P1_U0_PLD_IT8, 0x40010220 - 3462 .set CYREG_B0_P1_U0_PLD_IT9, 0x40010224 - 3463 .set CYREG_B0_P1_U0_PLD_IT10, 0x40010228 - 3464 .set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c - 3465 .set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230 - 3466 .set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232 - 3467 .set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234 - 3468 .set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236 - 3469 .set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 - 3470 .set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a - 3471 .set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c - 3472 .set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e - 3473 .set CYREG_B0_P1_U0_CFG0, 0x40010240 - 3474 .set CYREG_B0_P1_U0_CFG1, 0x40010241 - 3475 .set CYREG_B0_P1_U0_CFG2, 0x40010242 - 3476 .set CYREG_B0_P1_U0_CFG3, 0x40010243 - 3477 .set CYREG_B0_P1_U0_CFG4, 0x40010244 - 3478 .set CYREG_B0_P1_U0_CFG5, 0x40010245 - 3479 .set CYREG_B0_P1_U0_CFG6, 0x40010246 - 3480 .set CYREG_B0_P1_U0_CFG7, 0x40010247 - 3481 .set CYREG_B0_P1_U0_CFG8, 0x40010248 - 3482 .set CYREG_B0_P1_U0_CFG9, 0x40010249 - 3483 .set CYREG_B0_P1_U0_CFG10, 0x4001024a - 3484 .set CYREG_B0_P1_U0_CFG11, 0x4001024b - 3485 .set CYREG_B0_P1_U0_CFG12, 0x4001024c - 3486 .set CYREG_B0_P1_U0_CFG13, 0x4001024d - 3487 .set CYREG_B0_P1_U0_CFG14, 0x4001024e - 3488 .set CYREG_B0_P1_U0_CFG15, 0x4001024f - 3489 .set CYREG_B0_P1_U0_CFG16, 0x40010250 - 3490 .set CYREG_B0_P1_U0_CFG17, 0x40010251 - 3491 .set CYREG_B0_P1_U0_CFG18, 0x40010252 - 3492 .set CYREG_B0_P1_U0_CFG19, 0x40010253 - 3493 .set CYREG_B0_P1_U0_CFG20, 0x40010254 - 3494 .set CYREG_B0_P1_U0_CFG21, 0x40010255 - 3495 .set CYREG_B0_P1_U0_CFG22, 0x40010256 - 3496 .set CYREG_B0_P1_U0_CFG23, 0x40010257 - 3497 .set CYREG_B0_P1_U0_CFG24, 0x40010258 - 3498 .set CYREG_B0_P1_U0_CFG25, 0x40010259 - 3499 .set CYREG_B0_P1_U0_CFG26, 0x4001025a - 3500 .set CYREG_B0_P1_U0_CFG27, 0x4001025b - 3501 .set CYREG_B0_P1_U0_CFG28, 0x4001025c - 3502 .set CYREG_B0_P1_U0_CFG29, 0x4001025d - 3503 .set CYREG_B0_P1_U0_CFG30, 0x4001025e - 3504 .set CYREG_B0_P1_U0_CFG31, 0x4001025f - 3505 .set CYREG_B0_P1_U0_DCFG0, 0x40010260 - 3506 .set CYREG_B0_P1_U0_DCFG1, 0x40010262 - 3507 .set CYREG_B0_P1_U0_DCFG2, 0x40010264 - 3508 .set CYREG_B0_P1_U0_DCFG3, 0x40010266 - 3509 .set CYREG_B0_P1_U0_DCFG4, 0x40010268 - 3510 .set CYREG_B0_P1_U0_DCFG5, 0x4001026a - 3511 .set CYREG_B0_P1_U0_DCFG6, 0x4001026c - 3512 .set CYREG_B0_P1_U0_DCFG7, 0x4001026e - 3513 .set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 - 3514 .set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 - 3515 .set CYREG_B0_P1_U1_PLD_IT0, 0x40010280 - 3516 .set CYREG_B0_P1_U1_PLD_IT1, 0x40010284 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 157 - - - 3517 .set CYREG_B0_P1_U1_PLD_IT2, 0x40010288 - 3518 .set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c - 3519 .set CYREG_B0_P1_U1_PLD_IT4, 0x40010290 - 3520 .set CYREG_B0_P1_U1_PLD_IT5, 0x40010294 - 3521 .set CYREG_B0_P1_U1_PLD_IT6, 0x40010298 - 3522 .set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c - 3523 .set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0 - 3524 .set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4 - 3525 .set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8 - 3526 .set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac - 3527 .set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0 - 3528 .set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2 - 3529 .set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4 - 3530 .set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6 - 3531 .set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 - 3532 .set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba - 3533 .set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc - 3534 .set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be - 3535 .set CYREG_B0_P1_U1_CFG0, 0x400102c0 - 3536 .set CYREG_B0_P1_U1_CFG1, 0x400102c1 - 3537 .set CYREG_B0_P1_U1_CFG2, 0x400102c2 - 3538 .set CYREG_B0_P1_U1_CFG3, 0x400102c3 - 3539 .set CYREG_B0_P1_U1_CFG4, 0x400102c4 - 3540 .set CYREG_B0_P1_U1_CFG5, 0x400102c5 - 3541 .set CYREG_B0_P1_U1_CFG6, 0x400102c6 - 3542 .set CYREG_B0_P1_U1_CFG7, 0x400102c7 - 3543 .set CYREG_B0_P1_U1_CFG8, 0x400102c8 - 3544 .set CYREG_B0_P1_U1_CFG9, 0x400102c9 - 3545 .set CYREG_B0_P1_U1_CFG10, 0x400102ca - 3546 .set CYREG_B0_P1_U1_CFG11, 0x400102cb - 3547 .set CYREG_B0_P1_U1_CFG12, 0x400102cc - 3548 .set CYREG_B0_P1_U1_CFG13, 0x400102cd - 3549 .set CYREG_B0_P1_U1_CFG14, 0x400102ce - 3550 .set CYREG_B0_P1_U1_CFG15, 0x400102cf - 3551 .set CYREG_B0_P1_U1_CFG16, 0x400102d0 - 3552 .set CYREG_B0_P1_U1_CFG17, 0x400102d1 - 3553 .set CYREG_B0_P1_U1_CFG18, 0x400102d2 - 3554 .set CYREG_B0_P1_U1_CFG19, 0x400102d3 - 3555 .set CYREG_B0_P1_U1_CFG20, 0x400102d4 - 3556 .set CYREG_B0_P1_U1_CFG21, 0x400102d5 - 3557 .set CYREG_B0_P1_U1_CFG22, 0x400102d6 - 3558 .set CYREG_B0_P1_U1_CFG23, 0x400102d7 - 3559 .set CYREG_B0_P1_U1_CFG24, 0x400102d8 - 3560 .set CYREG_B0_P1_U1_CFG25, 0x400102d9 - 3561 .set CYREG_B0_P1_U1_CFG26, 0x400102da - 3562 .set CYREG_B0_P1_U1_CFG27, 0x400102db - 3563 .set CYREG_B0_P1_U1_CFG28, 0x400102dc - 3564 .set CYREG_B0_P1_U1_CFG29, 0x400102dd - 3565 .set CYREG_B0_P1_U1_CFG30, 0x400102de - 3566 .set CYREG_B0_P1_U1_CFG31, 0x400102df - 3567 .set CYREG_B0_P1_U1_DCFG0, 0x400102e0 - 3568 .set CYREG_B0_P1_U1_DCFG1, 0x400102e2 - 3569 .set CYREG_B0_P1_U1_DCFG2, 0x400102e4 - 3570 .set CYREG_B0_P1_U1_DCFG3, 0x400102e6 - 3571 .set CYREG_B0_P1_U1_DCFG4, 0x400102e8 - 3572 .set CYREG_B0_P1_U1_DCFG5, 0x400102ea - 3573 .set CYREG_B0_P1_U1_DCFG6, 0x400102ec - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 158 - - - 3574 .set CYREG_B0_P1_U1_DCFG7, 0x400102ee - 3575 .set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 - 3576 .set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef - 3577 .set CYDEV_UCFG_B0_P2_BASE, 0x40010400 - 3578 .set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef - 3579 .set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 - 3580 .set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 - 3581 .set CYREG_B0_P2_U0_PLD_IT0, 0x40010400 - 3582 .set CYREG_B0_P2_U0_PLD_IT1, 0x40010404 - 3583 .set CYREG_B0_P2_U0_PLD_IT2, 0x40010408 - 3584 .set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c - 3585 .set CYREG_B0_P2_U0_PLD_IT4, 0x40010410 - 3586 .set CYREG_B0_P2_U0_PLD_IT5, 0x40010414 - 3587 .set CYREG_B0_P2_U0_PLD_IT6, 0x40010418 - 3588 .set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c - 3589 .set CYREG_B0_P2_U0_PLD_IT8, 0x40010420 - 3590 .set CYREG_B0_P2_U0_PLD_IT9, 0x40010424 - 3591 .set CYREG_B0_P2_U0_PLD_IT10, 0x40010428 - 3592 .set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c - 3593 .set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430 - 3594 .set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432 - 3595 .set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434 - 3596 .set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436 - 3597 .set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 - 3598 .set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a - 3599 .set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c - 3600 .set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e - 3601 .set CYREG_B0_P2_U0_CFG0, 0x40010440 - 3602 .set CYREG_B0_P2_U0_CFG1, 0x40010441 - 3603 .set CYREG_B0_P2_U0_CFG2, 0x40010442 - 3604 .set CYREG_B0_P2_U0_CFG3, 0x40010443 - 3605 .set CYREG_B0_P2_U0_CFG4, 0x40010444 - 3606 .set CYREG_B0_P2_U0_CFG5, 0x40010445 - 3607 .set CYREG_B0_P2_U0_CFG6, 0x40010446 - 3608 .set CYREG_B0_P2_U0_CFG7, 0x40010447 - 3609 .set CYREG_B0_P2_U0_CFG8, 0x40010448 - 3610 .set CYREG_B0_P2_U0_CFG9, 0x40010449 - 3611 .set CYREG_B0_P2_U0_CFG10, 0x4001044a - 3612 .set CYREG_B0_P2_U0_CFG11, 0x4001044b - 3613 .set CYREG_B0_P2_U0_CFG12, 0x4001044c - 3614 .set CYREG_B0_P2_U0_CFG13, 0x4001044d - 3615 .set CYREG_B0_P2_U0_CFG14, 0x4001044e - 3616 .set CYREG_B0_P2_U0_CFG15, 0x4001044f - 3617 .set CYREG_B0_P2_U0_CFG16, 0x40010450 - 3618 .set CYREG_B0_P2_U0_CFG17, 0x40010451 - 3619 .set CYREG_B0_P2_U0_CFG18, 0x40010452 - 3620 .set CYREG_B0_P2_U0_CFG19, 0x40010453 - 3621 .set CYREG_B0_P2_U0_CFG20, 0x40010454 - 3622 .set CYREG_B0_P2_U0_CFG21, 0x40010455 - 3623 .set CYREG_B0_P2_U0_CFG22, 0x40010456 - 3624 .set CYREG_B0_P2_U0_CFG23, 0x40010457 - 3625 .set CYREG_B0_P2_U0_CFG24, 0x40010458 - 3626 .set CYREG_B0_P2_U0_CFG25, 0x40010459 - 3627 .set CYREG_B0_P2_U0_CFG26, 0x4001045a - 3628 .set CYREG_B0_P2_U0_CFG27, 0x4001045b - 3629 .set CYREG_B0_P2_U0_CFG28, 0x4001045c - 3630 .set CYREG_B0_P2_U0_CFG29, 0x4001045d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 159 - - - 3631 .set CYREG_B0_P2_U0_CFG30, 0x4001045e - 3632 .set CYREG_B0_P2_U0_CFG31, 0x4001045f - 3633 .set CYREG_B0_P2_U0_DCFG0, 0x40010460 - 3634 .set CYREG_B0_P2_U0_DCFG1, 0x40010462 - 3635 .set CYREG_B0_P2_U0_DCFG2, 0x40010464 - 3636 .set CYREG_B0_P2_U0_DCFG3, 0x40010466 - 3637 .set CYREG_B0_P2_U0_DCFG4, 0x40010468 - 3638 .set CYREG_B0_P2_U0_DCFG5, 0x4001046a - 3639 .set CYREG_B0_P2_U0_DCFG6, 0x4001046c - 3640 .set CYREG_B0_P2_U0_DCFG7, 0x4001046e - 3641 .set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 - 3642 .set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 - 3643 .set CYREG_B0_P2_U1_PLD_IT0, 0x40010480 - 3644 .set CYREG_B0_P2_U1_PLD_IT1, 0x40010484 - 3645 .set CYREG_B0_P2_U1_PLD_IT2, 0x40010488 - 3646 .set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c - 3647 .set CYREG_B0_P2_U1_PLD_IT4, 0x40010490 - 3648 .set CYREG_B0_P2_U1_PLD_IT5, 0x40010494 - 3649 .set CYREG_B0_P2_U1_PLD_IT6, 0x40010498 - 3650 .set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c - 3651 .set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0 - 3652 .set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4 - 3653 .set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8 - 3654 .set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac - 3655 .set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0 - 3656 .set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2 - 3657 .set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4 - 3658 .set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6 - 3659 .set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 - 3660 .set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba - 3661 .set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc - 3662 .set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be - 3663 .set CYREG_B0_P2_U1_CFG0, 0x400104c0 - 3664 .set CYREG_B0_P2_U1_CFG1, 0x400104c1 - 3665 .set CYREG_B0_P2_U1_CFG2, 0x400104c2 - 3666 .set CYREG_B0_P2_U1_CFG3, 0x400104c3 - 3667 .set CYREG_B0_P2_U1_CFG4, 0x400104c4 - 3668 .set CYREG_B0_P2_U1_CFG5, 0x400104c5 - 3669 .set CYREG_B0_P2_U1_CFG6, 0x400104c6 - 3670 .set CYREG_B0_P2_U1_CFG7, 0x400104c7 - 3671 .set CYREG_B0_P2_U1_CFG8, 0x400104c8 - 3672 .set CYREG_B0_P2_U1_CFG9, 0x400104c9 - 3673 .set CYREG_B0_P2_U1_CFG10, 0x400104ca - 3674 .set CYREG_B0_P2_U1_CFG11, 0x400104cb - 3675 .set CYREG_B0_P2_U1_CFG12, 0x400104cc - 3676 .set CYREG_B0_P2_U1_CFG13, 0x400104cd - 3677 .set CYREG_B0_P2_U1_CFG14, 0x400104ce - 3678 .set CYREG_B0_P2_U1_CFG15, 0x400104cf - 3679 .set CYREG_B0_P2_U1_CFG16, 0x400104d0 - 3680 .set CYREG_B0_P2_U1_CFG17, 0x400104d1 - 3681 .set CYREG_B0_P2_U1_CFG18, 0x400104d2 - 3682 .set CYREG_B0_P2_U1_CFG19, 0x400104d3 - 3683 .set CYREG_B0_P2_U1_CFG20, 0x400104d4 - 3684 .set CYREG_B0_P2_U1_CFG21, 0x400104d5 - 3685 .set CYREG_B0_P2_U1_CFG22, 0x400104d6 - 3686 .set CYREG_B0_P2_U1_CFG23, 0x400104d7 - 3687 .set CYREG_B0_P2_U1_CFG24, 0x400104d8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 160 - - - 3688 .set CYREG_B0_P2_U1_CFG25, 0x400104d9 - 3689 .set CYREG_B0_P2_U1_CFG26, 0x400104da - 3690 .set CYREG_B0_P2_U1_CFG27, 0x400104db - 3691 .set CYREG_B0_P2_U1_CFG28, 0x400104dc - 3692 .set CYREG_B0_P2_U1_CFG29, 0x400104dd - 3693 .set CYREG_B0_P2_U1_CFG30, 0x400104de - 3694 .set CYREG_B0_P2_U1_CFG31, 0x400104df - 3695 .set CYREG_B0_P2_U1_DCFG0, 0x400104e0 - 3696 .set CYREG_B0_P2_U1_DCFG1, 0x400104e2 - 3697 .set CYREG_B0_P2_U1_DCFG2, 0x400104e4 - 3698 .set CYREG_B0_P2_U1_DCFG3, 0x400104e6 - 3699 .set CYREG_B0_P2_U1_DCFG4, 0x400104e8 - 3700 .set CYREG_B0_P2_U1_DCFG5, 0x400104ea - 3701 .set CYREG_B0_P2_U1_DCFG6, 0x400104ec - 3702 .set CYREG_B0_P2_U1_DCFG7, 0x400104ee - 3703 .set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 - 3704 .set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef - 3705 .set CYDEV_UCFG_B0_P3_BASE, 0x40010600 - 3706 .set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef - 3707 .set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 - 3708 .set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 - 3709 .set CYREG_B0_P3_U0_PLD_IT0, 0x40010600 - 3710 .set CYREG_B0_P3_U0_PLD_IT1, 0x40010604 - 3711 .set CYREG_B0_P3_U0_PLD_IT2, 0x40010608 - 3712 .set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c - 3713 .set CYREG_B0_P3_U0_PLD_IT4, 0x40010610 - 3714 .set CYREG_B0_P3_U0_PLD_IT5, 0x40010614 - 3715 .set CYREG_B0_P3_U0_PLD_IT6, 0x40010618 - 3716 .set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c - 3717 .set CYREG_B0_P3_U0_PLD_IT8, 0x40010620 - 3718 .set CYREG_B0_P3_U0_PLD_IT9, 0x40010624 - 3719 .set CYREG_B0_P3_U0_PLD_IT10, 0x40010628 - 3720 .set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c - 3721 .set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630 - 3722 .set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632 - 3723 .set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634 - 3724 .set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636 - 3725 .set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 - 3726 .set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a - 3727 .set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c - 3728 .set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e - 3729 .set CYREG_B0_P3_U0_CFG0, 0x40010640 - 3730 .set CYREG_B0_P3_U0_CFG1, 0x40010641 - 3731 .set CYREG_B0_P3_U0_CFG2, 0x40010642 - 3732 .set CYREG_B0_P3_U0_CFG3, 0x40010643 - 3733 .set CYREG_B0_P3_U0_CFG4, 0x40010644 - 3734 .set CYREG_B0_P3_U0_CFG5, 0x40010645 - 3735 .set CYREG_B0_P3_U0_CFG6, 0x40010646 - 3736 .set CYREG_B0_P3_U0_CFG7, 0x40010647 - 3737 .set CYREG_B0_P3_U0_CFG8, 0x40010648 - 3738 .set CYREG_B0_P3_U0_CFG9, 0x40010649 - 3739 .set CYREG_B0_P3_U0_CFG10, 0x4001064a - 3740 .set CYREG_B0_P3_U0_CFG11, 0x4001064b - 3741 .set CYREG_B0_P3_U0_CFG12, 0x4001064c - 3742 .set CYREG_B0_P3_U0_CFG13, 0x4001064d - 3743 .set CYREG_B0_P3_U0_CFG14, 0x4001064e - 3744 .set CYREG_B0_P3_U0_CFG15, 0x4001064f - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 161 - - - 3745 .set CYREG_B0_P3_U0_CFG16, 0x40010650 - 3746 .set CYREG_B0_P3_U0_CFG17, 0x40010651 - 3747 .set CYREG_B0_P3_U0_CFG18, 0x40010652 - 3748 .set CYREG_B0_P3_U0_CFG19, 0x40010653 - 3749 .set CYREG_B0_P3_U0_CFG20, 0x40010654 - 3750 .set CYREG_B0_P3_U0_CFG21, 0x40010655 - 3751 .set CYREG_B0_P3_U0_CFG22, 0x40010656 - 3752 .set CYREG_B0_P3_U0_CFG23, 0x40010657 - 3753 .set CYREG_B0_P3_U0_CFG24, 0x40010658 - 3754 .set CYREG_B0_P3_U0_CFG25, 0x40010659 - 3755 .set CYREG_B0_P3_U0_CFG26, 0x4001065a - 3756 .set CYREG_B0_P3_U0_CFG27, 0x4001065b - 3757 .set CYREG_B0_P3_U0_CFG28, 0x4001065c - 3758 .set CYREG_B0_P3_U0_CFG29, 0x4001065d - 3759 .set CYREG_B0_P3_U0_CFG30, 0x4001065e - 3760 .set CYREG_B0_P3_U0_CFG31, 0x4001065f - 3761 .set CYREG_B0_P3_U0_DCFG0, 0x40010660 - 3762 .set CYREG_B0_P3_U0_DCFG1, 0x40010662 - 3763 .set CYREG_B0_P3_U0_DCFG2, 0x40010664 - 3764 .set CYREG_B0_P3_U0_DCFG3, 0x40010666 - 3765 .set CYREG_B0_P3_U0_DCFG4, 0x40010668 - 3766 .set CYREG_B0_P3_U0_DCFG5, 0x4001066a - 3767 .set CYREG_B0_P3_U0_DCFG6, 0x4001066c - 3768 .set CYREG_B0_P3_U0_DCFG7, 0x4001066e - 3769 .set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 - 3770 .set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 - 3771 .set CYREG_B0_P3_U1_PLD_IT0, 0x40010680 - 3772 .set CYREG_B0_P3_U1_PLD_IT1, 0x40010684 - 3773 .set CYREG_B0_P3_U1_PLD_IT2, 0x40010688 - 3774 .set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c - 3775 .set CYREG_B0_P3_U1_PLD_IT4, 0x40010690 - 3776 .set CYREG_B0_P3_U1_PLD_IT5, 0x40010694 - 3777 .set CYREG_B0_P3_U1_PLD_IT6, 0x40010698 - 3778 .set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c - 3779 .set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0 - 3780 .set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4 - 3781 .set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8 - 3782 .set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac - 3783 .set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0 - 3784 .set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2 - 3785 .set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4 - 3786 .set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6 - 3787 .set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 - 3788 .set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba - 3789 .set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc - 3790 .set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be - 3791 .set CYREG_B0_P3_U1_CFG0, 0x400106c0 - 3792 .set CYREG_B0_P3_U1_CFG1, 0x400106c1 - 3793 .set CYREG_B0_P3_U1_CFG2, 0x400106c2 - 3794 .set CYREG_B0_P3_U1_CFG3, 0x400106c3 - 3795 .set CYREG_B0_P3_U1_CFG4, 0x400106c4 - 3796 .set CYREG_B0_P3_U1_CFG5, 0x400106c5 - 3797 .set CYREG_B0_P3_U1_CFG6, 0x400106c6 - 3798 .set CYREG_B0_P3_U1_CFG7, 0x400106c7 - 3799 .set CYREG_B0_P3_U1_CFG8, 0x400106c8 - 3800 .set CYREG_B0_P3_U1_CFG9, 0x400106c9 - 3801 .set CYREG_B0_P3_U1_CFG10, 0x400106ca - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 162 - - - 3802 .set CYREG_B0_P3_U1_CFG11, 0x400106cb - 3803 .set CYREG_B0_P3_U1_CFG12, 0x400106cc - 3804 .set CYREG_B0_P3_U1_CFG13, 0x400106cd - 3805 .set CYREG_B0_P3_U1_CFG14, 0x400106ce - 3806 .set CYREG_B0_P3_U1_CFG15, 0x400106cf - 3807 .set CYREG_B0_P3_U1_CFG16, 0x400106d0 - 3808 .set CYREG_B0_P3_U1_CFG17, 0x400106d1 - 3809 .set CYREG_B0_P3_U1_CFG18, 0x400106d2 - 3810 .set CYREG_B0_P3_U1_CFG19, 0x400106d3 - 3811 .set CYREG_B0_P3_U1_CFG20, 0x400106d4 - 3812 .set CYREG_B0_P3_U1_CFG21, 0x400106d5 - 3813 .set CYREG_B0_P3_U1_CFG22, 0x400106d6 - 3814 .set CYREG_B0_P3_U1_CFG23, 0x400106d7 - 3815 .set CYREG_B0_P3_U1_CFG24, 0x400106d8 - 3816 .set CYREG_B0_P3_U1_CFG25, 0x400106d9 - 3817 .set CYREG_B0_P3_U1_CFG26, 0x400106da - 3818 .set CYREG_B0_P3_U1_CFG27, 0x400106db - 3819 .set CYREG_B0_P3_U1_CFG28, 0x400106dc - 3820 .set CYREG_B0_P3_U1_CFG29, 0x400106dd - 3821 .set CYREG_B0_P3_U1_CFG30, 0x400106de - 3822 .set CYREG_B0_P3_U1_CFG31, 0x400106df - 3823 .set CYREG_B0_P3_U1_DCFG0, 0x400106e0 - 3824 .set CYREG_B0_P3_U1_DCFG1, 0x400106e2 - 3825 .set CYREG_B0_P3_U1_DCFG2, 0x400106e4 - 3826 .set CYREG_B0_P3_U1_DCFG3, 0x400106e6 - 3827 .set CYREG_B0_P3_U1_DCFG4, 0x400106e8 - 3828 .set CYREG_B0_P3_U1_DCFG5, 0x400106ea - 3829 .set CYREG_B0_P3_U1_DCFG6, 0x400106ec - 3830 .set CYREG_B0_P3_U1_DCFG7, 0x400106ee - 3831 .set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 - 3832 .set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef - 3833 .set CYDEV_UCFG_B0_P4_BASE, 0x40010800 - 3834 .set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef - 3835 .set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 - 3836 .set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 - 3837 .set CYREG_B0_P4_U0_PLD_IT0, 0x40010800 - 3838 .set CYREG_B0_P4_U0_PLD_IT1, 0x40010804 - 3839 .set CYREG_B0_P4_U0_PLD_IT2, 0x40010808 - 3840 .set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c - 3841 .set CYREG_B0_P4_U0_PLD_IT4, 0x40010810 - 3842 .set CYREG_B0_P4_U0_PLD_IT5, 0x40010814 - 3843 .set CYREG_B0_P4_U0_PLD_IT6, 0x40010818 - 3844 .set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c - 3845 .set CYREG_B0_P4_U0_PLD_IT8, 0x40010820 - 3846 .set CYREG_B0_P4_U0_PLD_IT9, 0x40010824 - 3847 .set CYREG_B0_P4_U0_PLD_IT10, 0x40010828 - 3848 .set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c - 3849 .set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830 - 3850 .set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832 - 3851 .set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834 - 3852 .set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836 - 3853 .set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 - 3854 .set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a - 3855 .set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c - 3856 .set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e - 3857 .set CYREG_B0_P4_U0_CFG0, 0x40010840 - 3858 .set CYREG_B0_P4_U0_CFG1, 0x40010841 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 163 - - - 3859 .set CYREG_B0_P4_U0_CFG2, 0x40010842 - 3860 .set CYREG_B0_P4_U0_CFG3, 0x40010843 - 3861 .set CYREG_B0_P4_U0_CFG4, 0x40010844 - 3862 .set CYREG_B0_P4_U0_CFG5, 0x40010845 - 3863 .set CYREG_B0_P4_U0_CFG6, 0x40010846 - 3864 .set CYREG_B0_P4_U0_CFG7, 0x40010847 - 3865 .set CYREG_B0_P4_U0_CFG8, 0x40010848 - 3866 .set CYREG_B0_P4_U0_CFG9, 0x40010849 - 3867 .set CYREG_B0_P4_U0_CFG10, 0x4001084a - 3868 .set CYREG_B0_P4_U0_CFG11, 0x4001084b - 3869 .set CYREG_B0_P4_U0_CFG12, 0x4001084c - 3870 .set CYREG_B0_P4_U0_CFG13, 0x4001084d - 3871 .set CYREG_B0_P4_U0_CFG14, 0x4001084e - 3872 .set CYREG_B0_P4_U0_CFG15, 0x4001084f - 3873 .set CYREG_B0_P4_U0_CFG16, 0x40010850 - 3874 .set CYREG_B0_P4_U0_CFG17, 0x40010851 - 3875 .set CYREG_B0_P4_U0_CFG18, 0x40010852 - 3876 .set CYREG_B0_P4_U0_CFG19, 0x40010853 - 3877 .set CYREG_B0_P4_U0_CFG20, 0x40010854 - 3878 .set CYREG_B0_P4_U0_CFG21, 0x40010855 - 3879 .set CYREG_B0_P4_U0_CFG22, 0x40010856 - 3880 .set CYREG_B0_P4_U0_CFG23, 0x40010857 - 3881 .set CYREG_B0_P4_U0_CFG24, 0x40010858 - 3882 .set CYREG_B0_P4_U0_CFG25, 0x40010859 - 3883 .set CYREG_B0_P4_U0_CFG26, 0x4001085a - 3884 .set CYREG_B0_P4_U0_CFG27, 0x4001085b - 3885 .set CYREG_B0_P4_U0_CFG28, 0x4001085c - 3886 .set CYREG_B0_P4_U0_CFG29, 0x4001085d - 3887 .set CYREG_B0_P4_U0_CFG30, 0x4001085e - 3888 .set CYREG_B0_P4_U0_CFG31, 0x4001085f - 3889 .set CYREG_B0_P4_U0_DCFG0, 0x40010860 - 3890 .set CYREG_B0_P4_U0_DCFG1, 0x40010862 - 3891 .set CYREG_B0_P4_U0_DCFG2, 0x40010864 - 3892 .set CYREG_B0_P4_U0_DCFG3, 0x40010866 - 3893 .set CYREG_B0_P4_U0_DCFG4, 0x40010868 - 3894 .set CYREG_B0_P4_U0_DCFG5, 0x4001086a - 3895 .set CYREG_B0_P4_U0_DCFG6, 0x4001086c - 3896 .set CYREG_B0_P4_U0_DCFG7, 0x4001086e - 3897 .set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 - 3898 .set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 - 3899 .set CYREG_B0_P4_U1_PLD_IT0, 0x40010880 - 3900 .set CYREG_B0_P4_U1_PLD_IT1, 0x40010884 - 3901 .set CYREG_B0_P4_U1_PLD_IT2, 0x40010888 - 3902 .set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c - 3903 .set CYREG_B0_P4_U1_PLD_IT4, 0x40010890 - 3904 .set CYREG_B0_P4_U1_PLD_IT5, 0x40010894 - 3905 .set CYREG_B0_P4_U1_PLD_IT6, 0x40010898 - 3906 .set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c - 3907 .set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0 - 3908 .set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4 - 3909 .set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8 - 3910 .set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac - 3911 .set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0 - 3912 .set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2 - 3913 .set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4 - 3914 .set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6 - 3915 .set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 164 - - - 3916 .set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba - 3917 .set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc - 3918 .set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be - 3919 .set CYREG_B0_P4_U1_CFG0, 0x400108c0 - 3920 .set CYREG_B0_P4_U1_CFG1, 0x400108c1 - 3921 .set CYREG_B0_P4_U1_CFG2, 0x400108c2 - 3922 .set CYREG_B0_P4_U1_CFG3, 0x400108c3 - 3923 .set CYREG_B0_P4_U1_CFG4, 0x400108c4 - 3924 .set CYREG_B0_P4_U1_CFG5, 0x400108c5 - 3925 .set CYREG_B0_P4_U1_CFG6, 0x400108c6 - 3926 .set CYREG_B0_P4_U1_CFG7, 0x400108c7 - 3927 .set CYREG_B0_P4_U1_CFG8, 0x400108c8 - 3928 .set CYREG_B0_P4_U1_CFG9, 0x400108c9 - 3929 .set CYREG_B0_P4_U1_CFG10, 0x400108ca - 3930 .set CYREG_B0_P4_U1_CFG11, 0x400108cb - 3931 .set CYREG_B0_P4_U1_CFG12, 0x400108cc - 3932 .set CYREG_B0_P4_U1_CFG13, 0x400108cd - 3933 .set CYREG_B0_P4_U1_CFG14, 0x400108ce - 3934 .set CYREG_B0_P4_U1_CFG15, 0x400108cf - 3935 .set CYREG_B0_P4_U1_CFG16, 0x400108d0 - 3936 .set CYREG_B0_P4_U1_CFG17, 0x400108d1 - 3937 .set CYREG_B0_P4_U1_CFG18, 0x400108d2 - 3938 .set CYREG_B0_P4_U1_CFG19, 0x400108d3 - 3939 .set CYREG_B0_P4_U1_CFG20, 0x400108d4 - 3940 .set CYREG_B0_P4_U1_CFG21, 0x400108d5 - 3941 .set CYREG_B0_P4_U1_CFG22, 0x400108d6 - 3942 .set CYREG_B0_P4_U1_CFG23, 0x400108d7 - 3943 .set CYREG_B0_P4_U1_CFG24, 0x400108d8 - 3944 .set CYREG_B0_P4_U1_CFG25, 0x400108d9 - 3945 .set CYREG_B0_P4_U1_CFG26, 0x400108da - 3946 .set CYREG_B0_P4_U1_CFG27, 0x400108db - 3947 .set CYREG_B0_P4_U1_CFG28, 0x400108dc - 3948 .set CYREG_B0_P4_U1_CFG29, 0x400108dd - 3949 .set CYREG_B0_P4_U1_CFG30, 0x400108de - 3950 .set CYREG_B0_P4_U1_CFG31, 0x400108df - 3951 .set CYREG_B0_P4_U1_DCFG0, 0x400108e0 - 3952 .set CYREG_B0_P4_U1_DCFG1, 0x400108e2 - 3953 .set CYREG_B0_P4_U1_DCFG2, 0x400108e4 - 3954 .set CYREG_B0_P4_U1_DCFG3, 0x400108e6 - 3955 .set CYREG_B0_P4_U1_DCFG4, 0x400108e8 - 3956 .set CYREG_B0_P4_U1_DCFG5, 0x400108ea - 3957 .set CYREG_B0_P4_U1_DCFG6, 0x400108ec - 3958 .set CYREG_B0_P4_U1_DCFG7, 0x400108ee - 3959 .set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 - 3960 .set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef - 3961 .set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 - 3962 .set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef - 3963 .set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 - 3964 .set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 - 3965 .set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00 - 3966 .set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04 - 3967 .set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08 - 3968 .set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c - 3969 .set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10 - 3970 .set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14 - 3971 .set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18 - 3972 .set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 165 - - - 3973 .set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20 - 3974 .set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24 - 3975 .set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28 - 3976 .set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c - 3977 .set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30 - 3978 .set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32 - 3979 .set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34 - 3980 .set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36 - 3981 .set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 - 3982 .set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a - 3983 .set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c - 3984 .set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e - 3985 .set CYREG_B0_P5_U0_CFG0, 0x40010a40 - 3986 .set CYREG_B0_P5_U0_CFG1, 0x40010a41 - 3987 .set CYREG_B0_P5_U0_CFG2, 0x40010a42 - 3988 .set CYREG_B0_P5_U0_CFG3, 0x40010a43 - 3989 .set CYREG_B0_P5_U0_CFG4, 0x40010a44 - 3990 .set CYREG_B0_P5_U0_CFG5, 0x40010a45 - 3991 .set CYREG_B0_P5_U0_CFG6, 0x40010a46 - 3992 .set CYREG_B0_P5_U0_CFG7, 0x40010a47 - 3993 .set CYREG_B0_P5_U0_CFG8, 0x40010a48 - 3994 .set CYREG_B0_P5_U0_CFG9, 0x40010a49 - 3995 .set CYREG_B0_P5_U0_CFG10, 0x40010a4a - 3996 .set CYREG_B0_P5_U0_CFG11, 0x40010a4b - 3997 .set CYREG_B0_P5_U0_CFG12, 0x40010a4c - 3998 .set CYREG_B0_P5_U0_CFG13, 0x40010a4d - 3999 .set CYREG_B0_P5_U0_CFG14, 0x40010a4e - 4000 .set CYREG_B0_P5_U0_CFG15, 0x40010a4f - 4001 .set CYREG_B0_P5_U0_CFG16, 0x40010a50 - 4002 .set CYREG_B0_P5_U0_CFG17, 0x40010a51 - 4003 .set CYREG_B0_P5_U0_CFG18, 0x40010a52 - 4004 .set CYREG_B0_P5_U0_CFG19, 0x40010a53 - 4005 .set CYREG_B0_P5_U0_CFG20, 0x40010a54 - 4006 .set CYREG_B0_P5_U0_CFG21, 0x40010a55 - 4007 .set CYREG_B0_P5_U0_CFG22, 0x40010a56 - 4008 .set CYREG_B0_P5_U0_CFG23, 0x40010a57 - 4009 .set CYREG_B0_P5_U0_CFG24, 0x40010a58 - 4010 .set CYREG_B0_P5_U0_CFG25, 0x40010a59 - 4011 .set CYREG_B0_P5_U0_CFG26, 0x40010a5a - 4012 .set CYREG_B0_P5_U0_CFG27, 0x40010a5b - 4013 .set CYREG_B0_P5_U0_CFG28, 0x40010a5c - 4014 .set CYREG_B0_P5_U0_CFG29, 0x40010a5d - 4015 .set CYREG_B0_P5_U0_CFG30, 0x40010a5e - 4016 .set CYREG_B0_P5_U0_CFG31, 0x40010a5f - 4017 .set CYREG_B0_P5_U0_DCFG0, 0x40010a60 - 4018 .set CYREG_B0_P5_U0_DCFG1, 0x40010a62 - 4019 .set CYREG_B0_P5_U0_DCFG2, 0x40010a64 - 4020 .set CYREG_B0_P5_U0_DCFG3, 0x40010a66 - 4021 .set CYREG_B0_P5_U0_DCFG4, 0x40010a68 - 4022 .set CYREG_B0_P5_U0_DCFG5, 0x40010a6a - 4023 .set CYREG_B0_P5_U0_DCFG6, 0x40010a6c - 4024 .set CYREG_B0_P5_U0_DCFG7, 0x40010a6e - 4025 .set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 - 4026 .set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 - 4027 .set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80 - 4028 .set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84 - 4029 .set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 166 - - - 4030 .set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c - 4031 .set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90 - 4032 .set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94 - 4033 .set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98 - 4034 .set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c - 4035 .set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0 - 4036 .set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4 - 4037 .set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8 - 4038 .set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac - 4039 .set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0 - 4040 .set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2 - 4041 .set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4 - 4042 .set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6 - 4043 .set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 - 4044 .set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba - 4045 .set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc - 4046 .set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe - 4047 .set CYREG_B0_P5_U1_CFG0, 0x40010ac0 - 4048 .set CYREG_B0_P5_U1_CFG1, 0x40010ac1 - 4049 .set CYREG_B0_P5_U1_CFG2, 0x40010ac2 - 4050 .set CYREG_B0_P5_U1_CFG3, 0x40010ac3 - 4051 .set CYREG_B0_P5_U1_CFG4, 0x40010ac4 - 4052 .set CYREG_B0_P5_U1_CFG5, 0x40010ac5 - 4053 .set CYREG_B0_P5_U1_CFG6, 0x40010ac6 - 4054 .set CYREG_B0_P5_U1_CFG7, 0x40010ac7 - 4055 .set CYREG_B0_P5_U1_CFG8, 0x40010ac8 - 4056 .set CYREG_B0_P5_U1_CFG9, 0x40010ac9 - 4057 .set CYREG_B0_P5_U1_CFG10, 0x40010aca - 4058 .set CYREG_B0_P5_U1_CFG11, 0x40010acb - 4059 .set CYREG_B0_P5_U1_CFG12, 0x40010acc - 4060 .set CYREG_B0_P5_U1_CFG13, 0x40010acd - 4061 .set CYREG_B0_P5_U1_CFG14, 0x40010ace - 4062 .set CYREG_B0_P5_U1_CFG15, 0x40010acf - 4063 .set CYREG_B0_P5_U1_CFG16, 0x40010ad0 - 4064 .set CYREG_B0_P5_U1_CFG17, 0x40010ad1 - 4065 .set CYREG_B0_P5_U1_CFG18, 0x40010ad2 - 4066 .set CYREG_B0_P5_U1_CFG19, 0x40010ad3 - 4067 .set CYREG_B0_P5_U1_CFG20, 0x40010ad4 - 4068 .set CYREG_B0_P5_U1_CFG21, 0x40010ad5 - 4069 .set CYREG_B0_P5_U1_CFG22, 0x40010ad6 - 4070 .set CYREG_B0_P5_U1_CFG23, 0x40010ad7 - 4071 .set CYREG_B0_P5_U1_CFG24, 0x40010ad8 - 4072 .set CYREG_B0_P5_U1_CFG25, 0x40010ad9 - 4073 .set CYREG_B0_P5_U1_CFG26, 0x40010ada - 4074 .set CYREG_B0_P5_U1_CFG27, 0x40010adb - 4075 .set CYREG_B0_P5_U1_CFG28, 0x40010adc - 4076 .set CYREG_B0_P5_U1_CFG29, 0x40010add - 4077 .set CYREG_B0_P5_U1_CFG30, 0x40010ade - 4078 .set CYREG_B0_P5_U1_CFG31, 0x40010adf - 4079 .set CYREG_B0_P5_U1_DCFG0, 0x40010ae0 - 4080 .set CYREG_B0_P5_U1_DCFG1, 0x40010ae2 - 4081 .set CYREG_B0_P5_U1_DCFG2, 0x40010ae4 - 4082 .set CYREG_B0_P5_U1_DCFG3, 0x40010ae6 - 4083 .set CYREG_B0_P5_U1_DCFG4, 0x40010ae8 - 4084 .set CYREG_B0_P5_U1_DCFG5, 0x40010aea - 4085 .set CYREG_B0_P5_U1_DCFG6, 0x40010aec - 4086 .set CYREG_B0_P5_U1_DCFG7, 0x40010aee - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 167 - - - 4087 .set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 - 4088 .set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef - 4089 .set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 - 4090 .set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef - 4091 .set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 - 4092 .set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 - 4093 .set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00 - 4094 .set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04 - 4095 .set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08 - 4096 .set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c - 4097 .set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10 - 4098 .set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14 - 4099 .set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18 - 4100 .set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c - 4101 .set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20 - 4102 .set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24 - 4103 .set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28 - 4104 .set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c - 4105 .set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30 - 4106 .set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32 - 4107 .set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34 - 4108 .set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36 - 4109 .set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 - 4110 .set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a - 4111 .set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c - 4112 .set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e - 4113 .set CYREG_B0_P6_U0_CFG0, 0x40010c40 - 4114 .set CYREG_B0_P6_U0_CFG1, 0x40010c41 - 4115 .set CYREG_B0_P6_U0_CFG2, 0x40010c42 - 4116 .set CYREG_B0_P6_U0_CFG3, 0x40010c43 - 4117 .set CYREG_B0_P6_U0_CFG4, 0x40010c44 - 4118 .set CYREG_B0_P6_U0_CFG5, 0x40010c45 - 4119 .set CYREG_B0_P6_U0_CFG6, 0x40010c46 - 4120 .set CYREG_B0_P6_U0_CFG7, 0x40010c47 - 4121 .set CYREG_B0_P6_U0_CFG8, 0x40010c48 - 4122 .set CYREG_B0_P6_U0_CFG9, 0x40010c49 - 4123 .set CYREG_B0_P6_U0_CFG10, 0x40010c4a - 4124 .set CYREG_B0_P6_U0_CFG11, 0x40010c4b - 4125 .set CYREG_B0_P6_U0_CFG12, 0x40010c4c - 4126 .set CYREG_B0_P6_U0_CFG13, 0x40010c4d - 4127 .set CYREG_B0_P6_U0_CFG14, 0x40010c4e - 4128 .set CYREG_B0_P6_U0_CFG15, 0x40010c4f - 4129 .set CYREG_B0_P6_U0_CFG16, 0x40010c50 - 4130 .set CYREG_B0_P6_U0_CFG17, 0x40010c51 - 4131 .set CYREG_B0_P6_U0_CFG18, 0x40010c52 - 4132 .set CYREG_B0_P6_U0_CFG19, 0x40010c53 - 4133 .set CYREG_B0_P6_U0_CFG20, 0x40010c54 - 4134 .set CYREG_B0_P6_U0_CFG21, 0x40010c55 - 4135 .set CYREG_B0_P6_U0_CFG22, 0x40010c56 - 4136 .set CYREG_B0_P6_U0_CFG23, 0x40010c57 - 4137 .set CYREG_B0_P6_U0_CFG24, 0x40010c58 - 4138 .set CYREG_B0_P6_U0_CFG25, 0x40010c59 - 4139 .set CYREG_B0_P6_U0_CFG26, 0x40010c5a - 4140 .set CYREG_B0_P6_U0_CFG27, 0x40010c5b - 4141 .set CYREG_B0_P6_U0_CFG28, 0x40010c5c - 4142 .set CYREG_B0_P6_U0_CFG29, 0x40010c5d - 4143 .set CYREG_B0_P6_U0_CFG30, 0x40010c5e - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 168 - - - 4144 .set CYREG_B0_P6_U0_CFG31, 0x40010c5f - 4145 .set CYREG_B0_P6_U0_DCFG0, 0x40010c60 - 4146 .set CYREG_B0_P6_U0_DCFG1, 0x40010c62 - 4147 .set CYREG_B0_P6_U0_DCFG2, 0x40010c64 - 4148 .set CYREG_B0_P6_U0_DCFG3, 0x40010c66 - 4149 .set CYREG_B0_P6_U0_DCFG4, 0x40010c68 - 4150 .set CYREG_B0_P6_U0_DCFG5, 0x40010c6a - 4151 .set CYREG_B0_P6_U0_DCFG6, 0x40010c6c - 4152 .set CYREG_B0_P6_U0_DCFG7, 0x40010c6e - 4153 .set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 - 4154 .set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 - 4155 .set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80 - 4156 .set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84 - 4157 .set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88 - 4158 .set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c - 4159 .set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90 - 4160 .set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94 - 4161 .set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98 - 4162 .set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c - 4163 .set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0 - 4164 .set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4 - 4165 .set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8 - 4166 .set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac - 4167 .set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0 - 4168 .set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2 - 4169 .set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4 - 4170 .set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6 - 4171 .set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 - 4172 .set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba - 4173 .set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc - 4174 .set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe - 4175 .set CYREG_B0_P6_U1_CFG0, 0x40010cc0 - 4176 .set CYREG_B0_P6_U1_CFG1, 0x40010cc1 - 4177 .set CYREG_B0_P6_U1_CFG2, 0x40010cc2 - 4178 .set CYREG_B0_P6_U1_CFG3, 0x40010cc3 - 4179 .set CYREG_B0_P6_U1_CFG4, 0x40010cc4 - 4180 .set CYREG_B0_P6_U1_CFG5, 0x40010cc5 - 4181 .set CYREG_B0_P6_U1_CFG6, 0x40010cc6 - 4182 .set CYREG_B0_P6_U1_CFG7, 0x40010cc7 - 4183 .set CYREG_B0_P6_U1_CFG8, 0x40010cc8 - 4184 .set CYREG_B0_P6_U1_CFG9, 0x40010cc9 - 4185 .set CYREG_B0_P6_U1_CFG10, 0x40010cca - 4186 .set CYREG_B0_P6_U1_CFG11, 0x40010ccb - 4187 .set CYREG_B0_P6_U1_CFG12, 0x40010ccc - 4188 .set CYREG_B0_P6_U1_CFG13, 0x40010ccd - 4189 .set CYREG_B0_P6_U1_CFG14, 0x40010cce - 4190 .set CYREG_B0_P6_U1_CFG15, 0x40010ccf - 4191 .set CYREG_B0_P6_U1_CFG16, 0x40010cd0 - 4192 .set CYREG_B0_P6_U1_CFG17, 0x40010cd1 - 4193 .set CYREG_B0_P6_U1_CFG18, 0x40010cd2 - 4194 .set CYREG_B0_P6_U1_CFG19, 0x40010cd3 - 4195 .set CYREG_B0_P6_U1_CFG20, 0x40010cd4 - 4196 .set CYREG_B0_P6_U1_CFG21, 0x40010cd5 - 4197 .set CYREG_B0_P6_U1_CFG22, 0x40010cd6 - 4198 .set CYREG_B0_P6_U1_CFG23, 0x40010cd7 - 4199 .set CYREG_B0_P6_U1_CFG24, 0x40010cd8 - 4200 .set CYREG_B0_P6_U1_CFG25, 0x40010cd9 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 169 - - - 4201 .set CYREG_B0_P6_U1_CFG26, 0x40010cda - 4202 .set CYREG_B0_P6_U1_CFG27, 0x40010cdb - 4203 .set CYREG_B0_P6_U1_CFG28, 0x40010cdc - 4204 .set CYREG_B0_P6_U1_CFG29, 0x40010cdd - 4205 .set CYREG_B0_P6_U1_CFG30, 0x40010cde - 4206 .set CYREG_B0_P6_U1_CFG31, 0x40010cdf - 4207 .set CYREG_B0_P6_U1_DCFG0, 0x40010ce0 - 4208 .set CYREG_B0_P6_U1_DCFG1, 0x40010ce2 - 4209 .set CYREG_B0_P6_U1_DCFG2, 0x40010ce4 - 4210 .set CYREG_B0_P6_U1_DCFG3, 0x40010ce6 - 4211 .set CYREG_B0_P6_U1_DCFG4, 0x40010ce8 - 4212 .set CYREG_B0_P6_U1_DCFG5, 0x40010cea - 4213 .set CYREG_B0_P6_U1_DCFG6, 0x40010cec - 4214 .set CYREG_B0_P6_U1_DCFG7, 0x40010cee - 4215 .set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 - 4216 .set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef - 4217 .set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 - 4218 .set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef - 4219 .set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 - 4220 .set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 - 4221 .set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00 - 4222 .set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04 - 4223 .set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08 - 4224 .set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c - 4225 .set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10 - 4226 .set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14 - 4227 .set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18 - 4228 .set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c - 4229 .set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20 - 4230 .set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24 - 4231 .set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28 - 4232 .set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c - 4233 .set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30 - 4234 .set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32 - 4235 .set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34 - 4236 .set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36 - 4237 .set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 - 4238 .set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a - 4239 .set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c - 4240 .set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e - 4241 .set CYREG_B0_P7_U0_CFG0, 0x40010e40 - 4242 .set CYREG_B0_P7_U0_CFG1, 0x40010e41 - 4243 .set CYREG_B0_P7_U0_CFG2, 0x40010e42 - 4244 .set CYREG_B0_P7_U0_CFG3, 0x40010e43 - 4245 .set CYREG_B0_P7_U0_CFG4, 0x40010e44 - 4246 .set CYREG_B0_P7_U0_CFG5, 0x40010e45 - 4247 .set CYREG_B0_P7_U0_CFG6, 0x40010e46 - 4248 .set CYREG_B0_P7_U0_CFG7, 0x40010e47 - 4249 .set CYREG_B0_P7_U0_CFG8, 0x40010e48 - 4250 .set CYREG_B0_P7_U0_CFG9, 0x40010e49 - 4251 .set CYREG_B0_P7_U0_CFG10, 0x40010e4a - 4252 .set CYREG_B0_P7_U0_CFG11, 0x40010e4b - 4253 .set CYREG_B0_P7_U0_CFG12, 0x40010e4c - 4254 .set CYREG_B0_P7_U0_CFG13, 0x40010e4d - 4255 .set CYREG_B0_P7_U0_CFG14, 0x40010e4e - 4256 .set CYREG_B0_P7_U0_CFG15, 0x40010e4f - 4257 .set CYREG_B0_P7_U0_CFG16, 0x40010e50 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 170 - - - 4258 .set CYREG_B0_P7_U0_CFG17, 0x40010e51 - 4259 .set CYREG_B0_P7_U0_CFG18, 0x40010e52 - 4260 .set CYREG_B0_P7_U0_CFG19, 0x40010e53 - 4261 .set CYREG_B0_P7_U0_CFG20, 0x40010e54 - 4262 .set CYREG_B0_P7_U0_CFG21, 0x40010e55 - 4263 .set CYREG_B0_P7_U0_CFG22, 0x40010e56 - 4264 .set CYREG_B0_P7_U0_CFG23, 0x40010e57 - 4265 .set CYREG_B0_P7_U0_CFG24, 0x40010e58 - 4266 .set CYREG_B0_P7_U0_CFG25, 0x40010e59 - 4267 .set CYREG_B0_P7_U0_CFG26, 0x40010e5a - 4268 .set CYREG_B0_P7_U0_CFG27, 0x40010e5b - 4269 .set CYREG_B0_P7_U0_CFG28, 0x40010e5c - 4270 .set CYREG_B0_P7_U0_CFG29, 0x40010e5d - 4271 .set CYREG_B0_P7_U0_CFG30, 0x40010e5e - 4272 .set CYREG_B0_P7_U0_CFG31, 0x40010e5f - 4273 .set CYREG_B0_P7_U0_DCFG0, 0x40010e60 - 4274 .set CYREG_B0_P7_U0_DCFG1, 0x40010e62 - 4275 .set CYREG_B0_P7_U0_DCFG2, 0x40010e64 - 4276 .set CYREG_B0_P7_U0_DCFG3, 0x40010e66 - 4277 .set CYREG_B0_P7_U0_DCFG4, 0x40010e68 - 4278 .set CYREG_B0_P7_U0_DCFG5, 0x40010e6a - 4279 .set CYREG_B0_P7_U0_DCFG6, 0x40010e6c - 4280 .set CYREG_B0_P7_U0_DCFG7, 0x40010e6e - 4281 .set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 - 4282 .set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 - 4283 .set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80 - 4284 .set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84 - 4285 .set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88 - 4286 .set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c - 4287 .set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90 - 4288 .set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94 - 4289 .set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98 - 4290 .set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c - 4291 .set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0 - 4292 .set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4 - 4293 .set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8 - 4294 .set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac - 4295 .set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0 - 4296 .set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2 - 4297 .set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4 - 4298 .set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6 - 4299 .set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 - 4300 .set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba - 4301 .set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc - 4302 .set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe - 4303 .set CYREG_B0_P7_U1_CFG0, 0x40010ec0 - 4304 .set CYREG_B0_P7_U1_CFG1, 0x40010ec1 - 4305 .set CYREG_B0_P7_U1_CFG2, 0x40010ec2 - 4306 .set CYREG_B0_P7_U1_CFG3, 0x40010ec3 - 4307 .set CYREG_B0_P7_U1_CFG4, 0x40010ec4 - 4308 .set CYREG_B0_P7_U1_CFG5, 0x40010ec5 - 4309 .set CYREG_B0_P7_U1_CFG6, 0x40010ec6 - 4310 .set CYREG_B0_P7_U1_CFG7, 0x40010ec7 - 4311 .set CYREG_B0_P7_U1_CFG8, 0x40010ec8 - 4312 .set CYREG_B0_P7_U1_CFG9, 0x40010ec9 - 4313 .set CYREG_B0_P7_U1_CFG10, 0x40010eca - 4314 .set CYREG_B0_P7_U1_CFG11, 0x40010ecb - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 171 - - - 4315 .set CYREG_B0_P7_U1_CFG12, 0x40010ecc - 4316 .set CYREG_B0_P7_U1_CFG13, 0x40010ecd - 4317 .set CYREG_B0_P7_U1_CFG14, 0x40010ece - 4318 .set CYREG_B0_P7_U1_CFG15, 0x40010ecf - 4319 .set CYREG_B0_P7_U1_CFG16, 0x40010ed0 - 4320 .set CYREG_B0_P7_U1_CFG17, 0x40010ed1 - 4321 .set CYREG_B0_P7_U1_CFG18, 0x40010ed2 - 4322 .set CYREG_B0_P7_U1_CFG19, 0x40010ed3 - 4323 .set CYREG_B0_P7_U1_CFG20, 0x40010ed4 - 4324 .set CYREG_B0_P7_U1_CFG21, 0x40010ed5 - 4325 .set CYREG_B0_P7_U1_CFG22, 0x40010ed6 - 4326 .set CYREG_B0_P7_U1_CFG23, 0x40010ed7 - 4327 .set CYREG_B0_P7_U1_CFG24, 0x40010ed8 - 4328 .set CYREG_B0_P7_U1_CFG25, 0x40010ed9 - 4329 .set CYREG_B0_P7_U1_CFG26, 0x40010eda - 4330 .set CYREG_B0_P7_U1_CFG27, 0x40010edb - 4331 .set CYREG_B0_P7_U1_CFG28, 0x40010edc - 4332 .set CYREG_B0_P7_U1_CFG29, 0x40010edd - 4333 .set CYREG_B0_P7_U1_CFG30, 0x40010ede - 4334 .set CYREG_B0_P7_U1_CFG31, 0x40010edf - 4335 .set CYREG_B0_P7_U1_DCFG0, 0x40010ee0 - 4336 .set CYREG_B0_P7_U1_DCFG1, 0x40010ee2 - 4337 .set CYREG_B0_P7_U1_DCFG2, 0x40010ee4 - 4338 .set CYREG_B0_P7_U1_DCFG3, 0x40010ee6 - 4339 .set CYREG_B0_P7_U1_DCFG4, 0x40010ee8 - 4340 .set CYREG_B0_P7_U1_DCFG5, 0x40010eea - 4341 .set CYREG_B0_P7_U1_DCFG6, 0x40010eec - 4342 .set CYREG_B0_P7_U1_DCFG7, 0x40010eee - 4343 .set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 - 4344 .set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef - 4345 .set CYDEV_UCFG_B1_BASE, 0x40011000 - 4346 .set CYDEV_UCFG_B1_SIZE, 0x00000fef - 4347 .set CYDEV_UCFG_B1_P2_BASE, 0x40011400 - 4348 .set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef - 4349 .set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 - 4350 .set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 - 4351 .set CYREG_B1_P2_U0_PLD_IT0, 0x40011400 - 4352 .set CYREG_B1_P2_U0_PLD_IT1, 0x40011404 - 4353 .set CYREG_B1_P2_U0_PLD_IT2, 0x40011408 - 4354 .set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c - 4355 .set CYREG_B1_P2_U0_PLD_IT4, 0x40011410 - 4356 .set CYREG_B1_P2_U0_PLD_IT5, 0x40011414 - 4357 .set CYREG_B1_P2_U0_PLD_IT6, 0x40011418 - 4358 .set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c - 4359 .set CYREG_B1_P2_U0_PLD_IT8, 0x40011420 - 4360 .set CYREG_B1_P2_U0_PLD_IT9, 0x40011424 - 4361 .set CYREG_B1_P2_U0_PLD_IT10, 0x40011428 - 4362 .set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c - 4363 .set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430 - 4364 .set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432 - 4365 .set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434 - 4366 .set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436 - 4367 .set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 - 4368 .set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a - 4369 .set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c - 4370 .set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e - 4371 .set CYREG_B1_P2_U0_CFG0, 0x40011440 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 172 - - - 4372 .set CYREG_B1_P2_U0_CFG1, 0x40011441 - 4373 .set CYREG_B1_P2_U0_CFG2, 0x40011442 - 4374 .set CYREG_B1_P2_U0_CFG3, 0x40011443 - 4375 .set CYREG_B1_P2_U0_CFG4, 0x40011444 - 4376 .set CYREG_B1_P2_U0_CFG5, 0x40011445 - 4377 .set CYREG_B1_P2_U0_CFG6, 0x40011446 - 4378 .set CYREG_B1_P2_U0_CFG7, 0x40011447 - 4379 .set CYREG_B1_P2_U0_CFG8, 0x40011448 - 4380 .set CYREG_B1_P2_U0_CFG9, 0x40011449 - 4381 .set CYREG_B1_P2_U0_CFG10, 0x4001144a - 4382 .set CYREG_B1_P2_U0_CFG11, 0x4001144b - 4383 .set CYREG_B1_P2_U0_CFG12, 0x4001144c - 4384 .set CYREG_B1_P2_U0_CFG13, 0x4001144d - 4385 .set CYREG_B1_P2_U0_CFG14, 0x4001144e - 4386 .set CYREG_B1_P2_U0_CFG15, 0x4001144f - 4387 .set CYREG_B1_P2_U0_CFG16, 0x40011450 - 4388 .set CYREG_B1_P2_U0_CFG17, 0x40011451 - 4389 .set CYREG_B1_P2_U0_CFG18, 0x40011452 - 4390 .set CYREG_B1_P2_U0_CFG19, 0x40011453 - 4391 .set CYREG_B1_P2_U0_CFG20, 0x40011454 - 4392 .set CYREG_B1_P2_U0_CFG21, 0x40011455 - 4393 .set CYREG_B1_P2_U0_CFG22, 0x40011456 - 4394 .set CYREG_B1_P2_U0_CFG23, 0x40011457 - 4395 .set CYREG_B1_P2_U0_CFG24, 0x40011458 - 4396 .set CYREG_B1_P2_U0_CFG25, 0x40011459 - 4397 .set CYREG_B1_P2_U0_CFG26, 0x4001145a - 4398 .set CYREG_B1_P2_U0_CFG27, 0x4001145b - 4399 .set CYREG_B1_P2_U0_CFG28, 0x4001145c - 4400 .set CYREG_B1_P2_U0_CFG29, 0x4001145d - 4401 .set CYREG_B1_P2_U0_CFG30, 0x4001145e - 4402 .set CYREG_B1_P2_U0_CFG31, 0x4001145f - 4403 .set CYREG_B1_P2_U0_DCFG0, 0x40011460 - 4404 .set CYREG_B1_P2_U0_DCFG1, 0x40011462 - 4405 .set CYREG_B1_P2_U0_DCFG2, 0x40011464 - 4406 .set CYREG_B1_P2_U0_DCFG3, 0x40011466 - 4407 .set CYREG_B1_P2_U0_DCFG4, 0x40011468 - 4408 .set CYREG_B1_P2_U0_DCFG5, 0x4001146a - 4409 .set CYREG_B1_P2_U0_DCFG6, 0x4001146c - 4410 .set CYREG_B1_P2_U0_DCFG7, 0x4001146e - 4411 .set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 - 4412 .set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 - 4413 .set CYREG_B1_P2_U1_PLD_IT0, 0x40011480 - 4414 .set CYREG_B1_P2_U1_PLD_IT1, 0x40011484 - 4415 .set CYREG_B1_P2_U1_PLD_IT2, 0x40011488 - 4416 .set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c - 4417 .set CYREG_B1_P2_U1_PLD_IT4, 0x40011490 - 4418 .set CYREG_B1_P2_U1_PLD_IT5, 0x40011494 - 4419 .set CYREG_B1_P2_U1_PLD_IT6, 0x40011498 - 4420 .set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c - 4421 .set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0 - 4422 .set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4 - 4423 .set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8 - 4424 .set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac - 4425 .set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0 - 4426 .set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2 - 4427 .set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4 - 4428 .set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 173 - - - 4429 .set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 - 4430 .set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba - 4431 .set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc - 4432 .set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be - 4433 .set CYREG_B1_P2_U1_CFG0, 0x400114c0 - 4434 .set CYREG_B1_P2_U1_CFG1, 0x400114c1 - 4435 .set CYREG_B1_P2_U1_CFG2, 0x400114c2 - 4436 .set CYREG_B1_P2_U1_CFG3, 0x400114c3 - 4437 .set CYREG_B1_P2_U1_CFG4, 0x400114c4 - 4438 .set CYREG_B1_P2_U1_CFG5, 0x400114c5 - 4439 .set CYREG_B1_P2_U1_CFG6, 0x400114c6 - 4440 .set CYREG_B1_P2_U1_CFG7, 0x400114c7 - 4441 .set CYREG_B1_P2_U1_CFG8, 0x400114c8 - 4442 .set CYREG_B1_P2_U1_CFG9, 0x400114c9 - 4443 .set CYREG_B1_P2_U1_CFG10, 0x400114ca - 4444 .set CYREG_B1_P2_U1_CFG11, 0x400114cb - 4445 .set CYREG_B1_P2_U1_CFG12, 0x400114cc - 4446 .set CYREG_B1_P2_U1_CFG13, 0x400114cd - 4447 .set CYREG_B1_P2_U1_CFG14, 0x400114ce - 4448 .set CYREG_B1_P2_U1_CFG15, 0x400114cf - 4449 .set CYREG_B1_P2_U1_CFG16, 0x400114d0 - 4450 .set CYREG_B1_P2_U1_CFG17, 0x400114d1 - 4451 .set CYREG_B1_P2_U1_CFG18, 0x400114d2 - 4452 .set CYREG_B1_P2_U1_CFG19, 0x400114d3 - 4453 .set CYREG_B1_P2_U1_CFG20, 0x400114d4 - 4454 .set CYREG_B1_P2_U1_CFG21, 0x400114d5 - 4455 .set CYREG_B1_P2_U1_CFG22, 0x400114d6 - 4456 .set CYREG_B1_P2_U1_CFG23, 0x400114d7 - 4457 .set CYREG_B1_P2_U1_CFG24, 0x400114d8 - 4458 .set CYREG_B1_P2_U1_CFG25, 0x400114d9 - 4459 .set CYREG_B1_P2_U1_CFG26, 0x400114da - 4460 .set CYREG_B1_P2_U1_CFG27, 0x400114db - 4461 .set CYREG_B1_P2_U1_CFG28, 0x400114dc - 4462 .set CYREG_B1_P2_U1_CFG29, 0x400114dd - 4463 .set CYREG_B1_P2_U1_CFG30, 0x400114de - 4464 .set CYREG_B1_P2_U1_CFG31, 0x400114df - 4465 .set CYREG_B1_P2_U1_DCFG0, 0x400114e0 - 4466 .set CYREG_B1_P2_U1_DCFG1, 0x400114e2 - 4467 .set CYREG_B1_P2_U1_DCFG2, 0x400114e4 - 4468 .set CYREG_B1_P2_U1_DCFG3, 0x400114e6 - 4469 .set CYREG_B1_P2_U1_DCFG4, 0x400114e8 - 4470 .set CYREG_B1_P2_U1_DCFG5, 0x400114ea - 4471 .set CYREG_B1_P2_U1_DCFG6, 0x400114ec - 4472 .set CYREG_B1_P2_U1_DCFG7, 0x400114ee - 4473 .set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 - 4474 .set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef - 4475 .set CYDEV_UCFG_B1_P3_BASE, 0x40011600 - 4476 .set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef - 4477 .set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 - 4478 .set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 - 4479 .set CYREG_B1_P3_U0_PLD_IT0, 0x40011600 - 4480 .set CYREG_B1_P3_U0_PLD_IT1, 0x40011604 - 4481 .set CYREG_B1_P3_U0_PLD_IT2, 0x40011608 - 4482 .set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c - 4483 .set CYREG_B1_P3_U0_PLD_IT4, 0x40011610 - 4484 .set CYREG_B1_P3_U0_PLD_IT5, 0x40011614 - 4485 .set CYREG_B1_P3_U0_PLD_IT6, 0x40011618 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 174 - - - 4486 .set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c - 4487 .set CYREG_B1_P3_U0_PLD_IT8, 0x40011620 - 4488 .set CYREG_B1_P3_U0_PLD_IT9, 0x40011624 - 4489 .set CYREG_B1_P3_U0_PLD_IT10, 0x40011628 - 4490 .set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c - 4491 .set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630 - 4492 .set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632 - 4493 .set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634 - 4494 .set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636 - 4495 .set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 - 4496 .set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a - 4497 .set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c - 4498 .set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e - 4499 .set CYREG_B1_P3_U0_CFG0, 0x40011640 - 4500 .set CYREG_B1_P3_U0_CFG1, 0x40011641 - 4501 .set CYREG_B1_P3_U0_CFG2, 0x40011642 - 4502 .set CYREG_B1_P3_U0_CFG3, 0x40011643 - 4503 .set CYREG_B1_P3_U0_CFG4, 0x40011644 - 4504 .set CYREG_B1_P3_U0_CFG5, 0x40011645 - 4505 .set CYREG_B1_P3_U0_CFG6, 0x40011646 - 4506 .set CYREG_B1_P3_U0_CFG7, 0x40011647 - 4507 .set CYREG_B1_P3_U0_CFG8, 0x40011648 - 4508 .set CYREG_B1_P3_U0_CFG9, 0x40011649 - 4509 .set CYREG_B1_P3_U0_CFG10, 0x4001164a - 4510 .set CYREG_B1_P3_U0_CFG11, 0x4001164b - 4511 .set CYREG_B1_P3_U0_CFG12, 0x4001164c - 4512 .set CYREG_B1_P3_U0_CFG13, 0x4001164d - 4513 .set CYREG_B1_P3_U0_CFG14, 0x4001164e - 4514 .set CYREG_B1_P3_U0_CFG15, 0x4001164f - 4515 .set CYREG_B1_P3_U0_CFG16, 0x40011650 - 4516 .set CYREG_B1_P3_U0_CFG17, 0x40011651 - 4517 .set CYREG_B1_P3_U0_CFG18, 0x40011652 - 4518 .set CYREG_B1_P3_U0_CFG19, 0x40011653 - 4519 .set CYREG_B1_P3_U0_CFG20, 0x40011654 - 4520 .set CYREG_B1_P3_U0_CFG21, 0x40011655 - 4521 .set CYREG_B1_P3_U0_CFG22, 0x40011656 - 4522 .set CYREG_B1_P3_U0_CFG23, 0x40011657 - 4523 .set CYREG_B1_P3_U0_CFG24, 0x40011658 - 4524 .set CYREG_B1_P3_U0_CFG25, 0x40011659 - 4525 .set CYREG_B1_P3_U0_CFG26, 0x4001165a - 4526 .set CYREG_B1_P3_U0_CFG27, 0x4001165b - 4527 .set CYREG_B1_P3_U0_CFG28, 0x4001165c - 4528 .set CYREG_B1_P3_U0_CFG29, 0x4001165d - 4529 .set CYREG_B1_P3_U0_CFG30, 0x4001165e - 4530 .set CYREG_B1_P3_U0_CFG31, 0x4001165f - 4531 .set CYREG_B1_P3_U0_DCFG0, 0x40011660 - 4532 .set CYREG_B1_P3_U0_DCFG1, 0x40011662 - 4533 .set CYREG_B1_P3_U0_DCFG2, 0x40011664 - 4534 .set CYREG_B1_P3_U0_DCFG3, 0x40011666 - 4535 .set CYREG_B1_P3_U0_DCFG4, 0x40011668 - 4536 .set CYREG_B1_P3_U0_DCFG5, 0x4001166a - 4537 .set CYREG_B1_P3_U0_DCFG6, 0x4001166c - 4538 .set CYREG_B1_P3_U0_DCFG7, 0x4001166e - 4539 .set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 - 4540 .set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 - 4541 .set CYREG_B1_P3_U1_PLD_IT0, 0x40011680 - 4542 .set CYREG_B1_P3_U1_PLD_IT1, 0x40011684 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 175 - - - 4543 .set CYREG_B1_P3_U1_PLD_IT2, 0x40011688 - 4544 .set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c - 4545 .set CYREG_B1_P3_U1_PLD_IT4, 0x40011690 - 4546 .set CYREG_B1_P3_U1_PLD_IT5, 0x40011694 - 4547 .set CYREG_B1_P3_U1_PLD_IT6, 0x40011698 - 4548 .set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c - 4549 .set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0 - 4550 .set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4 - 4551 .set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8 - 4552 .set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac - 4553 .set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0 - 4554 .set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2 - 4555 .set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4 - 4556 .set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6 - 4557 .set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 - 4558 .set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba - 4559 .set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc - 4560 .set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be - 4561 .set CYREG_B1_P3_U1_CFG0, 0x400116c0 - 4562 .set CYREG_B1_P3_U1_CFG1, 0x400116c1 - 4563 .set CYREG_B1_P3_U1_CFG2, 0x400116c2 - 4564 .set CYREG_B1_P3_U1_CFG3, 0x400116c3 - 4565 .set CYREG_B1_P3_U1_CFG4, 0x400116c4 - 4566 .set CYREG_B1_P3_U1_CFG5, 0x400116c5 - 4567 .set CYREG_B1_P3_U1_CFG6, 0x400116c6 - 4568 .set CYREG_B1_P3_U1_CFG7, 0x400116c7 - 4569 .set CYREG_B1_P3_U1_CFG8, 0x400116c8 - 4570 .set CYREG_B1_P3_U1_CFG9, 0x400116c9 - 4571 .set CYREG_B1_P3_U1_CFG10, 0x400116ca - 4572 .set CYREG_B1_P3_U1_CFG11, 0x400116cb - 4573 .set CYREG_B1_P3_U1_CFG12, 0x400116cc - 4574 .set CYREG_B1_P3_U1_CFG13, 0x400116cd - 4575 .set CYREG_B1_P3_U1_CFG14, 0x400116ce - 4576 .set CYREG_B1_P3_U1_CFG15, 0x400116cf - 4577 .set CYREG_B1_P3_U1_CFG16, 0x400116d0 - 4578 .set CYREG_B1_P3_U1_CFG17, 0x400116d1 - 4579 .set CYREG_B1_P3_U1_CFG18, 0x400116d2 - 4580 .set CYREG_B1_P3_U1_CFG19, 0x400116d3 - 4581 .set CYREG_B1_P3_U1_CFG20, 0x400116d4 - 4582 .set CYREG_B1_P3_U1_CFG21, 0x400116d5 - 4583 .set CYREG_B1_P3_U1_CFG22, 0x400116d6 - 4584 .set CYREG_B1_P3_U1_CFG23, 0x400116d7 - 4585 .set CYREG_B1_P3_U1_CFG24, 0x400116d8 - 4586 .set CYREG_B1_P3_U1_CFG25, 0x400116d9 - 4587 .set CYREG_B1_P3_U1_CFG26, 0x400116da - 4588 .set CYREG_B1_P3_U1_CFG27, 0x400116db - 4589 .set CYREG_B1_P3_U1_CFG28, 0x400116dc - 4590 .set CYREG_B1_P3_U1_CFG29, 0x400116dd - 4591 .set CYREG_B1_P3_U1_CFG30, 0x400116de - 4592 .set CYREG_B1_P3_U1_CFG31, 0x400116df - 4593 .set CYREG_B1_P3_U1_DCFG0, 0x400116e0 - 4594 .set CYREG_B1_P3_U1_DCFG1, 0x400116e2 - 4595 .set CYREG_B1_P3_U1_DCFG2, 0x400116e4 - 4596 .set CYREG_B1_P3_U1_DCFG3, 0x400116e6 - 4597 .set CYREG_B1_P3_U1_DCFG4, 0x400116e8 - 4598 .set CYREG_B1_P3_U1_DCFG5, 0x400116ea - 4599 .set CYREG_B1_P3_U1_DCFG6, 0x400116ec - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 176 - - - 4600 .set CYREG_B1_P3_U1_DCFG7, 0x400116ee - 4601 .set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 - 4602 .set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef - 4603 .set CYDEV_UCFG_B1_P4_BASE, 0x40011800 - 4604 .set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef - 4605 .set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 - 4606 .set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 - 4607 .set CYREG_B1_P4_U0_PLD_IT0, 0x40011800 - 4608 .set CYREG_B1_P4_U0_PLD_IT1, 0x40011804 - 4609 .set CYREG_B1_P4_U0_PLD_IT2, 0x40011808 - 4610 .set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c - 4611 .set CYREG_B1_P4_U0_PLD_IT4, 0x40011810 - 4612 .set CYREG_B1_P4_U0_PLD_IT5, 0x40011814 - 4613 .set CYREG_B1_P4_U0_PLD_IT6, 0x40011818 - 4614 .set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c - 4615 .set CYREG_B1_P4_U0_PLD_IT8, 0x40011820 - 4616 .set CYREG_B1_P4_U0_PLD_IT9, 0x40011824 - 4617 .set CYREG_B1_P4_U0_PLD_IT10, 0x40011828 - 4618 .set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c - 4619 .set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830 - 4620 .set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832 - 4621 .set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834 - 4622 .set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836 - 4623 .set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 - 4624 .set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a - 4625 .set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c - 4626 .set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e - 4627 .set CYREG_B1_P4_U0_CFG0, 0x40011840 - 4628 .set CYREG_B1_P4_U0_CFG1, 0x40011841 - 4629 .set CYREG_B1_P4_U0_CFG2, 0x40011842 - 4630 .set CYREG_B1_P4_U0_CFG3, 0x40011843 - 4631 .set CYREG_B1_P4_U0_CFG4, 0x40011844 - 4632 .set CYREG_B1_P4_U0_CFG5, 0x40011845 - 4633 .set CYREG_B1_P4_U0_CFG6, 0x40011846 - 4634 .set CYREG_B1_P4_U0_CFG7, 0x40011847 - 4635 .set CYREG_B1_P4_U0_CFG8, 0x40011848 - 4636 .set CYREG_B1_P4_U0_CFG9, 0x40011849 - 4637 .set CYREG_B1_P4_U0_CFG10, 0x4001184a - 4638 .set CYREG_B1_P4_U0_CFG11, 0x4001184b - 4639 .set CYREG_B1_P4_U0_CFG12, 0x4001184c - 4640 .set CYREG_B1_P4_U0_CFG13, 0x4001184d - 4641 .set CYREG_B1_P4_U0_CFG14, 0x4001184e - 4642 .set CYREG_B1_P4_U0_CFG15, 0x4001184f - 4643 .set CYREG_B1_P4_U0_CFG16, 0x40011850 - 4644 .set CYREG_B1_P4_U0_CFG17, 0x40011851 - 4645 .set CYREG_B1_P4_U0_CFG18, 0x40011852 - 4646 .set CYREG_B1_P4_U0_CFG19, 0x40011853 - 4647 .set CYREG_B1_P4_U0_CFG20, 0x40011854 - 4648 .set CYREG_B1_P4_U0_CFG21, 0x40011855 - 4649 .set CYREG_B1_P4_U0_CFG22, 0x40011856 - 4650 .set CYREG_B1_P4_U0_CFG23, 0x40011857 - 4651 .set CYREG_B1_P4_U0_CFG24, 0x40011858 - 4652 .set CYREG_B1_P4_U0_CFG25, 0x40011859 - 4653 .set CYREG_B1_P4_U0_CFG26, 0x4001185a - 4654 .set CYREG_B1_P4_U0_CFG27, 0x4001185b - 4655 .set CYREG_B1_P4_U0_CFG28, 0x4001185c - 4656 .set CYREG_B1_P4_U0_CFG29, 0x4001185d - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 177 - - - 4657 .set CYREG_B1_P4_U0_CFG30, 0x4001185e - 4658 .set CYREG_B1_P4_U0_CFG31, 0x4001185f - 4659 .set CYREG_B1_P4_U0_DCFG0, 0x40011860 - 4660 .set CYREG_B1_P4_U0_DCFG1, 0x40011862 - 4661 .set CYREG_B1_P4_U0_DCFG2, 0x40011864 - 4662 .set CYREG_B1_P4_U0_DCFG3, 0x40011866 - 4663 .set CYREG_B1_P4_U0_DCFG4, 0x40011868 - 4664 .set CYREG_B1_P4_U0_DCFG5, 0x4001186a - 4665 .set CYREG_B1_P4_U0_DCFG6, 0x4001186c - 4666 .set CYREG_B1_P4_U0_DCFG7, 0x4001186e - 4667 .set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 - 4668 .set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 - 4669 .set CYREG_B1_P4_U1_PLD_IT0, 0x40011880 - 4670 .set CYREG_B1_P4_U1_PLD_IT1, 0x40011884 - 4671 .set CYREG_B1_P4_U1_PLD_IT2, 0x40011888 - 4672 .set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c - 4673 .set CYREG_B1_P4_U1_PLD_IT4, 0x40011890 - 4674 .set CYREG_B1_P4_U1_PLD_IT5, 0x40011894 - 4675 .set CYREG_B1_P4_U1_PLD_IT6, 0x40011898 - 4676 .set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c - 4677 .set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0 - 4678 .set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4 - 4679 .set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8 - 4680 .set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac - 4681 .set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0 - 4682 .set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2 - 4683 .set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4 - 4684 .set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6 - 4685 .set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 - 4686 .set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba - 4687 .set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc - 4688 .set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be - 4689 .set CYREG_B1_P4_U1_CFG0, 0x400118c0 - 4690 .set CYREG_B1_P4_U1_CFG1, 0x400118c1 - 4691 .set CYREG_B1_P4_U1_CFG2, 0x400118c2 - 4692 .set CYREG_B1_P4_U1_CFG3, 0x400118c3 - 4693 .set CYREG_B1_P4_U1_CFG4, 0x400118c4 - 4694 .set CYREG_B1_P4_U1_CFG5, 0x400118c5 - 4695 .set CYREG_B1_P4_U1_CFG6, 0x400118c6 - 4696 .set CYREG_B1_P4_U1_CFG7, 0x400118c7 - 4697 .set CYREG_B1_P4_U1_CFG8, 0x400118c8 - 4698 .set CYREG_B1_P4_U1_CFG9, 0x400118c9 - 4699 .set CYREG_B1_P4_U1_CFG10, 0x400118ca - 4700 .set CYREG_B1_P4_U1_CFG11, 0x400118cb - 4701 .set CYREG_B1_P4_U1_CFG12, 0x400118cc - 4702 .set CYREG_B1_P4_U1_CFG13, 0x400118cd - 4703 .set CYREG_B1_P4_U1_CFG14, 0x400118ce - 4704 .set CYREG_B1_P4_U1_CFG15, 0x400118cf - 4705 .set CYREG_B1_P4_U1_CFG16, 0x400118d0 - 4706 .set CYREG_B1_P4_U1_CFG17, 0x400118d1 - 4707 .set CYREG_B1_P4_U1_CFG18, 0x400118d2 - 4708 .set CYREG_B1_P4_U1_CFG19, 0x400118d3 - 4709 .set CYREG_B1_P4_U1_CFG20, 0x400118d4 - 4710 .set CYREG_B1_P4_U1_CFG21, 0x400118d5 - 4711 .set CYREG_B1_P4_U1_CFG22, 0x400118d6 - 4712 .set CYREG_B1_P4_U1_CFG23, 0x400118d7 - 4713 .set CYREG_B1_P4_U1_CFG24, 0x400118d8 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 178 - - - 4714 .set CYREG_B1_P4_U1_CFG25, 0x400118d9 - 4715 .set CYREG_B1_P4_U1_CFG26, 0x400118da - 4716 .set CYREG_B1_P4_U1_CFG27, 0x400118db - 4717 .set CYREG_B1_P4_U1_CFG28, 0x400118dc - 4718 .set CYREG_B1_P4_U1_CFG29, 0x400118dd - 4719 .set CYREG_B1_P4_U1_CFG30, 0x400118de - 4720 .set CYREG_B1_P4_U1_CFG31, 0x400118df - 4721 .set CYREG_B1_P4_U1_DCFG0, 0x400118e0 - 4722 .set CYREG_B1_P4_U1_DCFG1, 0x400118e2 - 4723 .set CYREG_B1_P4_U1_DCFG2, 0x400118e4 - 4724 .set CYREG_B1_P4_U1_DCFG3, 0x400118e6 - 4725 .set CYREG_B1_P4_U1_DCFG4, 0x400118e8 - 4726 .set CYREG_B1_P4_U1_DCFG5, 0x400118ea - 4727 .set CYREG_B1_P4_U1_DCFG6, 0x400118ec - 4728 .set CYREG_B1_P4_U1_DCFG7, 0x400118ee - 4729 .set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 - 4730 .set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef - 4731 .set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 - 4732 .set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef - 4733 .set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 - 4734 .set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 - 4735 .set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00 - 4736 .set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04 - 4737 .set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08 - 4738 .set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c - 4739 .set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10 - 4740 .set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14 - 4741 .set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18 - 4742 .set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c - 4743 .set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20 - 4744 .set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24 - 4745 .set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28 - 4746 .set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c - 4747 .set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30 - 4748 .set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32 - 4749 .set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34 - 4750 .set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36 - 4751 .set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 - 4752 .set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a - 4753 .set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c - 4754 .set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e - 4755 .set CYREG_B1_P5_U0_CFG0, 0x40011a40 - 4756 .set CYREG_B1_P5_U0_CFG1, 0x40011a41 - 4757 .set CYREG_B1_P5_U0_CFG2, 0x40011a42 - 4758 .set CYREG_B1_P5_U0_CFG3, 0x40011a43 - 4759 .set CYREG_B1_P5_U0_CFG4, 0x40011a44 - 4760 .set CYREG_B1_P5_U0_CFG5, 0x40011a45 - 4761 .set CYREG_B1_P5_U0_CFG6, 0x40011a46 - 4762 .set CYREG_B1_P5_U0_CFG7, 0x40011a47 - 4763 .set CYREG_B1_P5_U0_CFG8, 0x40011a48 - 4764 .set CYREG_B1_P5_U0_CFG9, 0x40011a49 - 4765 .set CYREG_B1_P5_U0_CFG10, 0x40011a4a - 4766 .set CYREG_B1_P5_U0_CFG11, 0x40011a4b - 4767 .set CYREG_B1_P5_U0_CFG12, 0x40011a4c - 4768 .set CYREG_B1_P5_U0_CFG13, 0x40011a4d - 4769 .set CYREG_B1_P5_U0_CFG14, 0x40011a4e - 4770 .set CYREG_B1_P5_U0_CFG15, 0x40011a4f - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 179 - - - 4771 .set CYREG_B1_P5_U0_CFG16, 0x40011a50 - 4772 .set CYREG_B1_P5_U0_CFG17, 0x40011a51 - 4773 .set CYREG_B1_P5_U0_CFG18, 0x40011a52 - 4774 .set CYREG_B1_P5_U0_CFG19, 0x40011a53 - 4775 .set CYREG_B1_P5_U0_CFG20, 0x40011a54 - 4776 .set CYREG_B1_P5_U0_CFG21, 0x40011a55 - 4777 .set CYREG_B1_P5_U0_CFG22, 0x40011a56 - 4778 .set CYREG_B1_P5_U0_CFG23, 0x40011a57 - 4779 .set CYREG_B1_P5_U0_CFG24, 0x40011a58 - 4780 .set CYREG_B1_P5_U0_CFG25, 0x40011a59 - 4781 .set CYREG_B1_P5_U0_CFG26, 0x40011a5a - 4782 .set CYREG_B1_P5_U0_CFG27, 0x40011a5b - 4783 .set CYREG_B1_P5_U0_CFG28, 0x40011a5c - 4784 .set CYREG_B1_P5_U0_CFG29, 0x40011a5d - 4785 .set CYREG_B1_P5_U0_CFG30, 0x40011a5e - 4786 .set CYREG_B1_P5_U0_CFG31, 0x40011a5f - 4787 .set CYREG_B1_P5_U0_DCFG0, 0x40011a60 - 4788 .set CYREG_B1_P5_U0_DCFG1, 0x40011a62 - 4789 .set CYREG_B1_P5_U0_DCFG2, 0x40011a64 - 4790 .set CYREG_B1_P5_U0_DCFG3, 0x40011a66 - 4791 .set CYREG_B1_P5_U0_DCFG4, 0x40011a68 - 4792 .set CYREG_B1_P5_U0_DCFG5, 0x40011a6a - 4793 .set CYREG_B1_P5_U0_DCFG6, 0x40011a6c - 4794 .set CYREG_B1_P5_U0_DCFG7, 0x40011a6e - 4795 .set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 - 4796 .set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 - 4797 .set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80 - 4798 .set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84 - 4799 .set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88 - 4800 .set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c - 4801 .set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90 - 4802 .set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94 - 4803 .set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98 - 4804 .set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c - 4805 .set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0 - 4806 .set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4 - 4807 .set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8 - 4808 .set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac - 4809 .set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0 - 4810 .set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2 - 4811 .set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4 - 4812 .set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6 - 4813 .set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 - 4814 .set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba - 4815 .set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc - 4816 .set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe - 4817 .set CYREG_B1_P5_U1_CFG0, 0x40011ac0 - 4818 .set CYREG_B1_P5_U1_CFG1, 0x40011ac1 - 4819 .set CYREG_B1_P5_U1_CFG2, 0x40011ac2 - 4820 .set CYREG_B1_P5_U1_CFG3, 0x40011ac3 - 4821 .set CYREG_B1_P5_U1_CFG4, 0x40011ac4 - 4822 .set CYREG_B1_P5_U1_CFG5, 0x40011ac5 - 4823 .set CYREG_B1_P5_U1_CFG6, 0x40011ac6 - 4824 .set CYREG_B1_P5_U1_CFG7, 0x40011ac7 - 4825 .set CYREG_B1_P5_U1_CFG8, 0x40011ac8 - 4826 .set CYREG_B1_P5_U1_CFG9, 0x40011ac9 - 4827 .set CYREG_B1_P5_U1_CFG10, 0x40011aca - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 180 - - - 4828 .set CYREG_B1_P5_U1_CFG11, 0x40011acb - 4829 .set CYREG_B1_P5_U1_CFG12, 0x40011acc - 4830 .set CYREG_B1_P5_U1_CFG13, 0x40011acd - 4831 .set CYREG_B1_P5_U1_CFG14, 0x40011ace - 4832 .set CYREG_B1_P5_U1_CFG15, 0x40011acf - 4833 .set CYREG_B1_P5_U1_CFG16, 0x40011ad0 - 4834 .set CYREG_B1_P5_U1_CFG17, 0x40011ad1 - 4835 .set CYREG_B1_P5_U1_CFG18, 0x40011ad2 - 4836 .set CYREG_B1_P5_U1_CFG19, 0x40011ad3 - 4837 .set CYREG_B1_P5_U1_CFG20, 0x40011ad4 - 4838 .set CYREG_B1_P5_U1_CFG21, 0x40011ad5 - 4839 .set CYREG_B1_P5_U1_CFG22, 0x40011ad6 - 4840 .set CYREG_B1_P5_U1_CFG23, 0x40011ad7 - 4841 .set CYREG_B1_P5_U1_CFG24, 0x40011ad8 - 4842 .set CYREG_B1_P5_U1_CFG25, 0x40011ad9 - 4843 .set CYREG_B1_P5_U1_CFG26, 0x40011ada - 4844 .set CYREG_B1_P5_U1_CFG27, 0x40011adb - 4845 .set CYREG_B1_P5_U1_CFG28, 0x40011adc - 4846 .set CYREG_B1_P5_U1_CFG29, 0x40011add - 4847 .set CYREG_B1_P5_U1_CFG30, 0x40011ade - 4848 .set CYREG_B1_P5_U1_CFG31, 0x40011adf - 4849 .set CYREG_B1_P5_U1_DCFG0, 0x40011ae0 - 4850 .set CYREG_B1_P5_U1_DCFG1, 0x40011ae2 - 4851 .set CYREG_B1_P5_U1_DCFG2, 0x40011ae4 - 4852 .set CYREG_B1_P5_U1_DCFG3, 0x40011ae6 - 4853 .set CYREG_B1_P5_U1_DCFG4, 0x40011ae8 - 4854 .set CYREG_B1_P5_U1_DCFG5, 0x40011aea - 4855 .set CYREG_B1_P5_U1_DCFG6, 0x40011aec - 4856 .set CYREG_B1_P5_U1_DCFG7, 0x40011aee - 4857 .set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 - 4858 .set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef - 4859 .set CYDEV_UCFG_DSI0_BASE, 0x40014000 - 4860 .set CYDEV_UCFG_DSI0_SIZE, 0x000000ef - 4861 .set CYDEV_UCFG_DSI1_BASE, 0x40014100 - 4862 .set CYDEV_UCFG_DSI1_SIZE, 0x000000ef - 4863 .set CYDEV_UCFG_DSI2_BASE, 0x40014200 - 4864 .set CYDEV_UCFG_DSI2_SIZE, 0x000000ef - 4865 .set CYDEV_UCFG_DSI3_BASE, 0x40014300 - 4866 .set CYDEV_UCFG_DSI3_SIZE, 0x000000ef - 4867 .set CYDEV_UCFG_DSI4_BASE, 0x40014400 - 4868 .set CYDEV_UCFG_DSI4_SIZE, 0x000000ef - 4869 .set CYDEV_UCFG_DSI5_BASE, 0x40014500 - 4870 .set CYDEV_UCFG_DSI5_SIZE, 0x000000ef - 4871 .set CYDEV_UCFG_DSI6_BASE, 0x40014600 - 4872 .set CYDEV_UCFG_DSI6_SIZE, 0x000000ef - 4873 .set CYDEV_UCFG_DSI7_BASE, 0x40014700 - 4874 .set CYDEV_UCFG_DSI7_SIZE, 0x000000ef - 4875 .set CYDEV_UCFG_DSI8_BASE, 0x40014800 - 4876 .set CYDEV_UCFG_DSI8_SIZE, 0x000000ef - 4877 .set CYDEV_UCFG_DSI9_BASE, 0x40014900 - 4878 .set CYDEV_UCFG_DSI9_SIZE, 0x000000ef - 4879 .set CYDEV_UCFG_DSI12_BASE, 0x40014c00 - 4880 .set CYDEV_UCFG_DSI12_SIZE, 0x000000ef - 4881 .set CYDEV_UCFG_DSI13_BASE, 0x40014d00 - 4882 .set CYDEV_UCFG_DSI13_SIZE, 0x000000ef - 4883 .set CYDEV_UCFG_BCTL0_BASE, 0x40015000 - 4884 .set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 181 - - - 4885 .set CYREG_BCTL0_MDCLK_EN, 0x40015000 - 4886 .set CYREG_BCTL0_MBCLK_EN, 0x40015001 - 4887 .set CYREG_BCTL0_WAIT_CFG, 0x40015002 - 4888 .set CYREG_BCTL0_BANK_CTL, 0x40015003 - 4889 .set CYREG_BCTL0_UDB_TEST_3, 0x40015007 - 4890 .set CYREG_BCTL0_DCLK_EN0, 0x40015008 - 4891 .set CYREG_BCTL0_BCLK_EN0, 0x40015009 - 4892 .set CYREG_BCTL0_DCLK_EN1, 0x4001500a - 4893 .set CYREG_BCTL0_BCLK_EN1, 0x4001500b - 4894 .set CYREG_BCTL0_DCLK_EN2, 0x4001500c - 4895 .set CYREG_BCTL0_BCLK_EN2, 0x4001500d - 4896 .set CYREG_BCTL0_DCLK_EN3, 0x4001500e - 4897 .set CYREG_BCTL0_BCLK_EN3, 0x4001500f - 4898 .set CYDEV_UCFG_BCTL1_BASE, 0x40015010 - 4899 .set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 - 4900 .set CYREG_BCTL1_MDCLK_EN, 0x40015010 - 4901 .set CYREG_BCTL1_MBCLK_EN, 0x40015011 - 4902 .set CYREG_BCTL1_WAIT_CFG, 0x40015012 - 4903 .set CYREG_BCTL1_BANK_CTL, 0x40015013 - 4904 .set CYREG_BCTL1_UDB_TEST_3, 0x40015017 - 4905 .set CYREG_BCTL1_DCLK_EN0, 0x40015018 - 4906 .set CYREG_BCTL1_BCLK_EN0, 0x40015019 - 4907 .set CYREG_BCTL1_DCLK_EN1, 0x4001501a - 4908 .set CYREG_BCTL1_BCLK_EN1, 0x4001501b - 4909 .set CYREG_BCTL1_DCLK_EN2, 0x4001501c - 4910 .set CYREG_BCTL1_BCLK_EN2, 0x4001501d - 4911 .set CYREG_BCTL1_DCLK_EN3, 0x4001501e - 4912 .set CYREG_BCTL1_BCLK_EN3, 0x4001501f - 4913 .set CYDEV_IDMUX_BASE, 0x40015100 - 4914 .set CYDEV_IDMUX_SIZE, 0x00000016 - 4915 .set CYREG_IDMUX_IRQ_CTL0, 0x40015100 - 4916 .set CYREG_IDMUX_IRQ_CTL1, 0x40015101 - 4917 .set CYREG_IDMUX_IRQ_CTL2, 0x40015102 - 4918 .set CYREG_IDMUX_IRQ_CTL3, 0x40015103 - 4919 .set CYREG_IDMUX_IRQ_CTL4, 0x40015104 - 4920 .set CYREG_IDMUX_IRQ_CTL5, 0x40015105 - 4921 .set CYREG_IDMUX_IRQ_CTL6, 0x40015106 - 4922 .set CYREG_IDMUX_IRQ_CTL7, 0x40015107 - 4923 .set CYREG_IDMUX_DRQ_CTL0, 0x40015110 - 4924 .set CYREG_IDMUX_DRQ_CTL1, 0x40015111 - 4925 .set CYREG_IDMUX_DRQ_CTL2, 0x40015112 - 4926 .set CYREG_IDMUX_DRQ_CTL3, 0x40015113 - 4927 .set CYREG_IDMUX_DRQ_CTL4, 0x40015114 - 4928 .set CYREG_IDMUX_DRQ_CTL5, 0x40015115 - 4929 .set CYDEV_CACHERAM_BASE, 0x40030000 - 4930 .set CYDEV_CACHERAM_SIZE, 0x00000400 - 4931 .set CYREG_CACHERAM_DATA_MBASE, 0x40030000 - 4932 .set CYREG_CACHERAM_DATA_MSIZE, 0x00000400 - 4933 .set CYDEV_SFR_BASE, 0x40050100 - 4934 .set CYDEV_SFR_SIZE, 0x000000fb - 4935 .set CYREG_SFR_GPIO0, 0x40050180 - 4936 .set CYREG_SFR_GPIRD0, 0x40050189 - 4937 .set CYREG_SFR_GPIO0_SEL, 0x4005018a - 4938 .set CYREG_SFR_GPIO1, 0x40050190 - 4939 .set CYREG_SFR_GPIRD1, 0x40050191 - 4940 .set CYREG_SFR_GPIO2, 0x40050198 - 4941 .set CYREG_SFR_GPIRD2, 0x40050199 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 182 - - - 4942 .set CYREG_SFR_GPIO2_SEL, 0x4005019a - 4943 .set CYREG_SFR_GPIO1_SEL, 0x400501a2 - 4944 .set CYREG_SFR_GPIO3, 0x400501b0 - 4945 .set CYREG_SFR_GPIRD3, 0x400501b1 - 4946 .set CYREG_SFR_GPIO3_SEL, 0x400501b2 - 4947 .set CYREG_SFR_GPIO4, 0x400501c0 - 4948 .set CYREG_SFR_GPIRD4, 0x400501c1 - 4949 .set CYREG_SFR_GPIO4_SEL, 0x400501c2 - 4950 .set CYREG_SFR_GPIO5, 0x400501c8 - 4951 .set CYREG_SFR_GPIRD5, 0x400501c9 - 4952 .set CYREG_SFR_GPIO5_SEL, 0x400501ca - 4953 .set CYREG_SFR_GPIO6, 0x400501d8 - 4954 .set CYREG_SFR_GPIRD6, 0x400501d9 - 4955 .set CYREG_SFR_GPIO6_SEL, 0x400501da - 4956 .set CYREG_SFR_GPIO12, 0x400501e8 - 4957 .set CYREG_SFR_GPIRD12, 0x400501e9 - 4958 .set CYREG_SFR_GPIO12_SEL, 0x400501f2 - 4959 .set CYREG_SFR_GPIO15, 0x400501f8 - 4960 .set CYREG_SFR_GPIRD15, 0x400501f9 - 4961 .set CYREG_SFR_GPIO15_SEL, 0x400501fa - 4962 .set CYDEV_P3BA_BASE, 0x40050300 - 4963 .set CYDEV_P3BA_SIZE, 0x0000002b - 4964 .set CYREG_P3BA_Y_START, 0x40050300 - 4965 .set CYREG_P3BA_YROLL, 0x40050301 - 4966 .set CYREG_P3BA_YCFG, 0x40050302 - 4967 .set CYREG_P3BA_X_START1, 0x40050303 - 4968 .set CYREG_P3BA_X_START2, 0x40050304 - 4969 .set CYREG_P3BA_XROLL1, 0x40050305 - 4970 .set CYREG_P3BA_XROLL2, 0x40050306 - 4971 .set CYREG_P3BA_XINC, 0x40050307 - 4972 .set CYREG_P3BA_XCFG, 0x40050308 - 4973 .set CYREG_P3BA_OFFSETADDR1, 0x40050309 - 4974 .set CYREG_P3BA_OFFSETADDR2, 0x4005030a - 4975 .set CYREG_P3BA_OFFSETADDR3, 0x4005030b - 4976 .set CYREG_P3BA_ABSADDR1, 0x4005030c - 4977 .set CYREG_P3BA_ABSADDR2, 0x4005030d - 4978 .set CYREG_P3BA_ABSADDR3, 0x4005030e - 4979 .set CYREG_P3BA_ABSADDR4, 0x4005030f - 4980 .set CYREG_P3BA_DATCFG1, 0x40050310 - 4981 .set CYREG_P3BA_DATCFG2, 0x40050311 - 4982 .set CYREG_P3BA_CMP_RSLT1, 0x40050314 - 4983 .set CYREG_P3BA_CMP_RSLT2, 0x40050315 - 4984 .set CYREG_P3BA_CMP_RSLT3, 0x40050316 - 4985 .set CYREG_P3BA_CMP_RSLT4, 0x40050317 - 4986 .set CYREG_P3BA_DATA_REG1, 0x40050318 - 4987 .set CYREG_P3BA_DATA_REG2, 0x40050319 - 4988 .set CYREG_P3BA_DATA_REG3, 0x4005031a - 4989 .set CYREG_P3BA_DATA_REG4, 0x4005031b - 4990 .set CYREG_P3BA_EXP_DATA1, 0x4005031c - 4991 .set CYREG_P3BA_EXP_DATA2, 0x4005031d - 4992 .set CYREG_P3BA_EXP_DATA3, 0x4005031e - 4993 .set CYREG_P3BA_EXP_DATA4, 0x4005031f - 4994 .set CYREG_P3BA_MSTR_HRDATA1, 0x40050320 - 4995 .set CYREG_P3BA_MSTR_HRDATA2, 0x40050321 - 4996 .set CYREG_P3BA_MSTR_HRDATA3, 0x40050322 - 4997 .set CYREG_P3BA_MSTR_HRDATA4, 0x40050323 - 4998 .set CYREG_P3BA_BIST_EN, 0x40050324 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 183 - - - 4999 .set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325 - 5000 .set CYREG_P3BA_SEQCFG1, 0x40050326 - 5001 .set CYREG_P3BA_SEQCFG2, 0x40050327 - 5002 .set CYREG_P3BA_Y_CURR, 0x40050328 - 5003 .set CYREG_P3BA_X_CURR1, 0x40050329 - 5004 .set CYREG_P3BA_X_CURR2, 0x4005032a - 5005 .set CYDEV_PANTHER_BASE, 0x40080000 - 5006 .set CYDEV_PANTHER_SIZE, 0x00000020 - 5007 .set CYREG_PANTHER_STCALIB_CFG, 0x40080000 - 5008 .set CYREG_PANTHER_WAITPIPE, 0x40080004 - 5009 .set CYREG_PANTHER_TRACE_CFG, 0x40080008 - 5010 .set CYREG_PANTHER_DBG_CFG, 0x4008000c - 5011 .set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018 - 5012 .set CYREG_PANTHER_DEVICE_ID, 0x4008001c - 5013 .set CYDEV_FLSECC_BASE, 0x48000000 - 5014 .set CYDEV_FLSECC_SIZE, 0x00008000 - 5015 .set CYREG_FLSECC_DATA_MBASE, 0x48000000 - 5016 .set CYREG_FLSECC_DATA_MSIZE, 0x00008000 - 5017 .set CYDEV_FLSHID_BASE, 0x49000000 - 5018 .set CYDEV_FLSHID_SIZE, 0x00000200 - 5019 .set CYREG_FLSHID_RSVD_MBASE, 0x49000000 - 5020 .set CYREG_FLSHID_RSVD_MSIZE, 0x00000080 - 5021 .set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080 - 5022 .set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080 - 5023 .set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 - 5024 .set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 - 5025 .set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 - 5026 .set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101 - 5027 .set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 - 5028 .set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 - 5029 .set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 - 5030 .set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 - 5031 .set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 - 5032 .set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107 - 5033 .set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 - 5034 .set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 - 5035 .set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a - 5036 .set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b - 5037 .set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c - 5038 .set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d - 5039 .set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e - 5040 .set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f - 5041 .set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 - 5042 .set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 - 5043 .set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 - 5044 .set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 - 5045 .set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 - 5046 .set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 - 5047 .set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 - 5048 .set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 - 5049 .set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 - 5050 .set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 - 5051 .set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a - 5052 .set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b - 5053 .set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c - 5054 .set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d - 5055 .set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 184 - - - 5056 .set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f - 5057 .set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 - 5058 .set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 - 5059 .set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 - 5060 .set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 - 5061 .set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 - 5062 .set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 - 5063 .set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 - 5064 .set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 - 5065 .set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 - 5066 .set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 - 5067 .set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a - 5068 .set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b - 5069 .set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c - 5070 .set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d - 5071 .set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e - 5072 .set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f - 5073 .set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 - 5074 .set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 - 5075 .set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 - 5076 .set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 - 5077 .set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 - 5078 .set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 - 5079 .set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 - 5080 .set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 - 5081 .set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 - 5082 .set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 - 5083 .set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a - 5084 .set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b - 5085 .set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c - 5086 .set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d - 5087 .set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e - 5088 .set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f - 5089 .set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 - 5090 .set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 - 5091 .set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 - 5092 .set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac - 5093 .set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae - 5094 .set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 - 5095 .set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 - 5096 .set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 - 5097 .set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 - 5098 .set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 - 5099 .set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba - 5100 .set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce - 5101 .set CYDEV_EXTMEM_BASE, 0x60000000 - 5102 .set CYDEV_EXTMEM_SIZE, 0x00800000 - 5103 .set CYREG_EXTMEM_DATA_MBASE, 0x60000000 - 5104 .set CYREG_EXTMEM_DATA_MSIZE, 0x00800000 - 5105 .set CYDEV_ITM_BASE, 0xe0000000 - 5106 .set CYDEV_ITM_SIZE, 0x00001000 - 5107 .set CYREG_ITM_TRACE_EN, 0xe0000e00 - 5108 .set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40 - 5109 .set CYREG_ITM_TRACE_CTRL, 0xe0000e80 - 5110 .set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0 - 5111 .set CYREG_ITM_LOCK_STATUS, 0xe0000fb4 - 5112 .set CYREG_ITM_PID4, 0xe0000fd0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 185 - - - 5113 .set CYREG_ITM_PID5, 0xe0000fd4 - 5114 .set CYREG_ITM_PID6, 0xe0000fd8 - 5115 .set CYREG_ITM_PID7, 0xe0000fdc - 5116 .set CYREG_ITM_PID0, 0xe0000fe0 - 5117 .set CYREG_ITM_PID1, 0xe0000fe4 - 5118 .set CYREG_ITM_PID2, 0xe0000fe8 - 5119 .set CYREG_ITM_PID3, 0xe0000fec - 5120 .set CYREG_ITM_CID0, 0xe0000ff0 - 5121 .set CYREG_ITM_CID1, 0xe0000ff4 - 5122 .set CYREG_ITM_CID2, 0xe0000ff8 - 5123 .set CYREG_ITM_CID3, 0xe0000ffc - 5124 .set CYDEV_DWT_BASE, 0xe0001000 - 5125 .set CYDEV_DWT_SIZE, 0x0000005c - 5126 .set CYREG_DWT_CTRL, 0xe0001000 - 5127 .set CYREG_DWT_CYCLE_COUNT, 0xe0001004 - 5128 .set CYREG_DWT_CPI_COUNT, 0xe0001008 - 5129 .set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c - 5130 .set CYREG_DWT_SLEEP_COUNT, 0xe0001010 - 5131 .set CYREG_DWT_LSU_COUNT, 0xe0001014 - 5132 .set CYREG_DWT_FOLD_COUNT, 0xe0001018 - 5133 .set CYREG_DWT_PC_SAMPLE, 0xe000101c - 5134 .set CYREG_DWT_COMP_0, 0xe0001020 - 5135 .set CYREG_DWT_MASK_0, 0xe0001024 - 5136 .set CYREG_DWT_FUNCTION_0, 0xe0001028 - 5137 .set CYREG_DWT_COMP_1, 0xe0001030 - 5138 .set CYREG_DWT_MASK_1, 0xe0001034 - 5139 .set CYREG_DWT_FUNCTION_1, 0xe0001038 - 5140 .set CYREG_DWT_COMP_2, 0xe0001040 - 5141 .set CYREG_DWT_MASK_2, 0xe0001044 - 5142 .set CYREG_DWT_FUNCTION_2, 0xe0001048 - 5143 .set CYREG_DWT_COMP_3, 0xe0001050 - 5144 .set CYREG_DWT_MASK_3, 0xe0001054 - 5145 .set CYREG_DWT_FUNCTION_3, 0xe0001058 - 5146 .set CYDEV_FPB_BASE, 0xe0002000 - 5147 .set CYDEV_FPB_SIZE, 0x00001000 - 5148 .set CYREG_FPB_CTRL, 0xe0002000 - 5149 .set CYREG_FPB_REMAP, 0xe0002004 - 5150 .set CYREG_FPB_FP_COMP_0, 0xe0002008 - 5151 .set CYREG_FPB_FP_COMP_1, 0xe000200c - 5152 .set CYREG_FPB_FP_COMP_2, 0xe0002010 - 5153 .set CYREG_FPB_FP_COMP_3, 0xe0002014 - 5154 .set CYREG_FPB_FP_COMP_4, 0xe0002018 - 5155 .set CYREG_FPB_FP_COMP_5, 0xe000201c - 5156 .set CYREG_FPB_FP_COMP_6, 0xe0002020 - 5157 .set CYREG_FPB_FP_COMP_7, 0xe0002024 - 5158 .set CYREG_FPB_PID4, 0xe0002fd0 - 5159 .set CYREG_FPB_PID5, 0xe0002fd4 - 5160 .set CYREG_FPB_PID6, 0xe0002fd8 - 5161 .set CYREG_FPB_PID7, 0xe0002fdc - 5162 .set CYREG_FPB_PID0, 0xe0002fe0 - 5163 .set CYREG_FPB_PID1, 0xe0002fe4 - 5164 .set CYREG_FPB_PID2, 0xe0002fe8 - 5165 .set CYREG_FPB_PID3, 0xe0002fec - 5166 .set CYREG_FPB_CID0, 0xe0002ff0 - 5167 .set CYREG_FPB_CID1, 0xe0002ff4 - 5168 .set CYREG_FPB_CID2, 0xe0002ff8 - 5169 .set CYREG_FPB_CID3, 0xe0002ffc - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 186 - - - 5170 .set CYDEV_NVIC_BASE, 0xe000e000 - 5171 .set CYDEV_NVIC_SIZE, 0x00000d3c - 5172 .set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004 - 5173 .set CYREG_NVIC_SYSTICK_CTL, 0xe000e010 - 5174 .set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014 - 5175 .set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018 - 5176 .set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c - 5177 .set CYREG_NVIC_SETENA0, 0xe000e100 - 5178 .set CYREG_NVIC_CLRENA0, 0xe000e180 - 5179 .set CYREG_NVIC_SETPEND0, 0xe000e200 - 5180 .set CYREG_NVIC_CLRPEND0, 0xe000e280 - 5181 .set CYREG_NVIC_ACTIVE0, 0xe000e300 - 5182 .set CYREG_NVIC_PRI_0, 0xe000e400 - 5183 .set CYREG_NVIC_PRI_1, 0xe000e401 - 5184 .set CYREG_NVIC_PRI_2, 0xe000e402 - 5185 .set CYREG_NVIC_PRI_3, 0xe000e403 - 5186 .set CYREG_NVIC_PRI_4, 0xe000e404 - 5187 .set CYREG_NVIC_PRI_5, 0xe000e405 - 5188 .set CYREG_NVIC_PRI_6, 0xe000e406 - 5189 .set CYREG_NVIC_PRI_7, 0xe000e407 - 5190 .set CYREG_NVIC_PRI_8, 0xe000e408 - 5191 .set CYREG_NVIC_PRI_9, 0xe000e409 - 5192 .set CYREG_NVIC_PRI_10, 0xe000e40a - 5193 .set CYREG_NVIC_PRI_11, 0xe000e40b - 5194 .set CYREG_NVIC_PRI_12, 0xe000e40c - 5195 .set CYREG_NVIC_PRI_13, 0xe000e40d - 5196 .set CYREG_NVIC_PRI_14, 0xe000e40e - 5197 .set CYREG_NVIC_PRI_15, 0xe000e40f - 5198 .set CYREG_NVIC_PRI_16, 0xe000e410 - 5199 .set CYREG_NVIC_PRI_17, 0xe000e411 - 5200 .set CYREG_NVIC_PRI_18, 0xe000e412 - 5201 .set CYREG_NVIC_PRI_19, 0xe000e413 - 5202 .set CYREG_NVIC_PRI_20, 0xe000e414 - 5203 .set CYREG_NVIC_PRI_21, 0xe000e415 - 5204 .set CYREG_NVIC_PRI_22, 0xe000e416 - 5205 .set CYREG_NVIC_PRI_23, 0xe000e417 - 5206 .set CYREG_NVIC_PRI_24, 0xe000e418 - 5207 .set CYREG_NVIC_PRI_25, 0xe000e419 - 5208 .set CYREG_NVIC_PRI_26, 0xe000e41a - 5209 .set CYREG_NVIC_PRI_27, 0xe000e41b - 5210 .set CYREG_NVIC_PRI_28, 0xe000e41c - 5211 .set CYREG_NVIC_PRI_29, 0xe000e41d - 5212 .set CYREG_NVIC_PRI_30, 0xe000e41e - 5213 .set CYREG_NVIC_PRI_31, 0xe000e41f - 5214 .set CYREG_NVIC_CPUID_BASE, 0xe000ed00 - 5215 .set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04 - 5216 .set CYREG_NVIC_VECT_OFFSET, 0xe000ed08 - 5217 .set CYREG_NVIC_APPLN_INTR, 0xe000ed0c - 5218 .set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10 - 5219 .set CYREG_NVIC_CFG_CONTROL, 0xe000ed14 - 5220 .set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 - 5221 .set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c - 5222 .set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 - 5223 .set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24 - 5224 .set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 - 5225 .set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29 - 5226 .set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 187 - - - 5227 .set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c - 5228 .set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 - 5229 .set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 - 5230 .set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38 - 5231 .set CYDEV_CORE_DBG_BASE, 0xe000edf0 - 5232 .set CYDEV_CORE_DBG_SIZE, 0x00000010 - 5233 .set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0 - 5234 .set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4 - 5235 .set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8 - 5236 .set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc - 5237 .set CYDEV_TPIU_BASE, 0xe0040000 - 5238 .set CYDEV_TPIU_SIZE, 0x00001000 - 5239 .set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 - 5240 .set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 - 5241 .set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 - 5242 .set CYREG_TPIU_PROTOCOL, 0xe00400f0 - 5243 .set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300 - 5244 .set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304 - 5245 .set CYREG_TPIU_TRIGGER, 0xe0040ee8 - 5246 .set CYREG_TPIU_ITETMDATA, 0xe0040eec - 5247 .set CYREG_TPIU_ITATBCTR2, 0xe0040ef0 - 5248 .set CYREG_TPIU_ITATBCTR0, 0xe0040ef8 - 5249 .set CYREG_TPIU_ITITMDATA, 0xe0040efc - 5250 .set CYREG_TPIU_ITCTRL, 0xe0040f00 - 5251 .set CYREG_TPIU_DEVID, 0xe0040fc8 - 5252 .set CYREG_TPIU_DEVTYPE, 0xe0040fcc - 5253 .set CYREG_TPIU_PID4, 0xe0040fd0 - 5254 .set CYREG_TPIU_PID5, 0xe0040fd4 - 5255 .set CYREG_TPIU_PID6, 0xe0040fd8 - 5256 .set CYREG_TPIU_PID7, 0xe0040fdc - 5257 .set CYREG_TPIU_PID0, 0xe0040fe0 - 5258 .set CYREG_TPIU_PID1, 0xe0040fe4 - 5259 .set CYREG_TPIU_PID2, 0xe0040fe8 - 5260 .set CYREG_TPIU_PID3, 0xe0040fec - 5261 .set CYREG_TPIU_CID0, 0xe0040ff0 - 5262 .set CYREG_TPIU_CID1, 0xe0040ff4 - 5263 .set CYREG_TPIU_CID2, 0xe0040ff8 - 5264 .set CYREG_TPIU_CID3, 0xe0040ffc - 5265 .set CYDEV_ETM_BASE, 0xe0041000 - 5266 .set CYDEV_ETM_SIZE, 0x00001000 - 5267 .set CYREG_ETM_CTL, 0xe0041000 - 5268 .set CYREG_ETM_CFG_CODE, 0xe0041004 - 5269 .set CYREG_ETM_TRIG_EVENT, 0xe0041008 - 5270 .set CYREG_ETM_STATUS, 0xe0041010 - 5271 .set CYREG_ETM_SYS_CFG, 0xe0041014 - 5272 .set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020 - 5273 .set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024 - 5274 .set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c - 5275 .set CYREG_ETM_SYNC_FREQ, 0xe00411e0 - 5276 .set CYREG_ETM_ETM_ID, 0xe00411e4 - 5277 .set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8 - 5278 .set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 - 5279 .set CYREG_ETM_CS_TRACE_ID, 0xe0041200 - 5280 .set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300 - 5281 .set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304 - 5282 .set CYREG_ETM_PDSR, 0xe0041314 - 5283 .set CYREG_ETM_ITMISCIN, 0xe0041ee0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 188 - - - 5284 .set CYREG_ETM_ITTRIGOUT, 0xe0041ee8 - 5285 .set CYREG_ETM_ITATBCTR2, 0xe0041ef0 - 5286 .set CYREG_ETM_ITATBCTR0, 0xe0041ef8 - 5287 .set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00 - 5288 .set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0 - 5289 .set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4 - 5290 .set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0 - 5291 .set CYREG_ETM_LOCK_STATUS, 0xe0041fb4 - 5292 .set CYREG_ETM_AUTH_STATUS, 0xe0041fb8 - 5293 .set CYREG_ETM_DEV_TYPE, 0xe0041fcc - 5294 .set CYREG_ETM_PID4, 0xe0041fd0 - 5295 .set CYREG_ETM_PID5, 0xe0041fd4 - 5296 .set CYREG_ETM_PID6, 0xe0041fd8 - 5297 .set CYREG_ETM_PID7, 0xe0041fdc - 5298 .set CYREG_ETM_PID0, 0xe0041fe0 - 5299 .set CYREG_ETM_PID1, 0xe0041fe4 - 5300 .set CYREG_ETM_PID2, 0xe0041fe8 - 5301 .set CYREG_ETM_PID3, 0xe0041fec - 5302 .set CYREG_ETM_CID0, 0xe0041ff0 - 5303 .set CYREG_ETM_CID1, 0xe0041ff4 - 5304 .set CYREG_ETM_CID2, 0xe0041ff8 - 5305 .set CYREG_ETM_CID3, 0xe0041ffc - 5306 .set CYDEV_ROM_TABLE_BASE, 0xe00ff000 - 5307 .set CYDEV_ROM_TABLE_SIZE, 0x00001000 - 5308 .set CYREG_ROM_TABLE_NVIC, 0xe00ff000 - 5309 .set CYREG_ROM_TABLE_DWT, 0xe00ff004 - 5310 .set CYREG_ROM_TABLE_FPB, 0xe00ff008 - 5311 .set CYREG_ROM_TABLE_ITM, 0xe00ff00c - 5312 .set CYREG_ROM_TABLE_TPIU, 0xe00ff010 - 5313 .set CYREG_ROM_TABLE_ETM, 0xe00ff014 - 5314 .set CYREG_ROM_TABLE_END, 0xe00ff018 - 5315 .set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc - 5316 .set CYREG_ROM_TABLE_PID4, 0xe00fffd0 - 5317 .set CYREG_ROM_TABLE_PID5, 0xe00fffd4 - 5318 .set CYREG_ROM_TABLE_PID6, 0xe00fffd8 - 5319 .set CYREG_ROM_TABLE_PID7, 0xe00fffdc - 5320 .set CYREG_ROM_TABLE_PID0, 0xe00fffe0 - 5321 .set CYREG_ROM_TABLE_PID1, 0xe00fffe4 - 5322 .set CYREG_ROM_TABLE_PID2, 0xe00fffe8 - 5323 .set CYREG_ROM_TABLE_PID3, 0xe00fffec - 5324 .set CYREG_ROM_TABLE_CID0, 0xe00ffff0 - 5325 .set CYREG_ROM_TABLE_CID1, 0xe00ffff4 - 5326 .set CYREG_ROM_TABLE_CID2, 0xe00ffff8 - 5327 .set CYREG_ROM_TABLE_CID3, 0xe00ffffc - 5328 .set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE - 5329 .set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE - 5330 .set CYDEV_FLS_SECTOR_SIZE, 0x00010000 - 5331 .set CYDEV_FLS_ROW_SIZE, 0x00000100 - 5332 .set CYDEV_ECC_SECTOR_SIZE, 0x00002000 - 5333 .set CYDEV_ECC_ROW_SIZE, 0x00000020 - 5334 .set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 - 5335 .set CYDEV_EEPROM_ROW_SIZE, 0x00000010 - 5336 .set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE - 5337 .set CYCLK_LD_DISABLE, 0x00000004 - 5338 .set CYCLK_LD_SYNC_EN, 0x00000002 - 5339 .set CYCLK_LD_LOAD, 0x00000001 - 5340 .set CYCLK_PIPE, 0x00000080 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 189 - - - 5341 .set CYCLK_SSS, 0x00000040 - 5342 .set CYCLK_EARLY, 0x00000020 - 5343 .set CYCLK_DUTY, 0x00000010 - 5344 .set CYCLK_SYNC, 0x00000008 - 5345 .set CYCLK_SRC_SEL_CLK_SYNC_D, 0 - 5346 .set CYCLK_SRC_SEL_SYNC_DIG, 0 - 5347 .set CYCLK_SRC_SEL_IMO, 1 - 5348 .set CYCLK_SRC_SEL_XTAL_MHZ, 2 - 5349 .set CYCLK_SRC_SEL_XTALM, 2 - 5350 .set CYCLK_SRC_SEL_ILO, 3 - 5351 .set CYCLK_SRC_SEL_PLL, 4 - 5352 .set CYCLK_SRC_SEL_XTAL_KHZ, 5 - 5353 .set CYCLK_SRC_SEL_XTALK, 5 - 5354 .set CYCLK_SRC_SEL_DSI_G, 6 - 5355 .set CYCLK_SRC_SEL_DSI_D, 7 - 5356 .set CYCLK_SRC_SEL_CLK_SYNC_A, 0 - 5357 .set CYCLK_SRC_SEL_DSI_A, 7 - 5 - 6 /* USBFS_bus_reset */ - 7 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 - 8 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 - 9 .set USBFS_bus_reset__INTC_MASK, 0x800000 - 10 .set USBFS_bus_reset__INTC_NUMBER, 23 - 11 .set USBFS_bus_reset__INTC_PRIOR_NUM, 7 - 12 .set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 - 13 .set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 - 14 .set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - 15 - 16 /* USBFS_arb_int */ - 17 .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 - 18 .set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 - 19 .set USBFS_arb_int__INTC_MASK, 0x400000 - 20 .set USBFS_arb_int__INTC_NUMBER, 22 - 21 .set USBFS_arb_int__INTC_PRIOR_NUM, 7 - 22 .set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 - 23 .set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 - 24 .set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - 25 - 26 /* USBFS_sof_int */ - 27 .set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 - 28 .set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 - 29 .set USBFS_sof_int__INTC_MASK, 0x200000 - 30 .set USBFS_sof_int__INTC_NUMBER, 21 - 31 .set USBFS_sof_int__INTC_PRIOR_NUM, 7 - 32 .set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 - 33 .set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 - 34 .set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - 35 - 36 /* SCSI_Out_DBx */ - 37 .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG - 38 .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX - 39 .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE - 40 .set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK - 41 .set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP - 42 .set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL - 43 .set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0 - 44 .set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 190 - - - 45 .set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2 - 46 .set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR - 47 .set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS - 48 .set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 49 .set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN - 50 .set SCSI_Out_DBx__0__MASK, 0x08 - 51 .set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3 - 52 .set SCSI_Out_DBx__0__PORT, 6 - 53 .set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT - 54 .set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 55 .set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 56 .set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - 57 .set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 58 .set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 59 .set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - 60 .set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 61 .set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS - 62 .set SCSI_Out_DBx__0__SHIFT, 3 - 63 .set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW - 64 .set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG - 65 .set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX - 66 .set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE - 67 .set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK - 68 .set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP - 69 .set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL - 70 .set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0 - 71 .set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1 - 72 .set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2 - 73 .set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR - 74 .set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS - 75 .set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 76 .set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN - 77 .set SCSI_Out_DBx__1__MASK, 0x04 - 78 .set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2 - 79 .set SCSI_Out_DBx__1__PORT, 6 - 80 .set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT - 81 .set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 82 .set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 83 .set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - 84 .set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 85 .set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 86 .set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - 87 .set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 88 .set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS - 89 .set SCSI_Out_DBx__1__SHIFT, 2 - 90 .set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW - 91 .set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG - 92 .set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX - 93 .set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE - 94 .set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK - 95 .set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP - 96 .set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL - 97 .set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0 - 98 .set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1 - 99 .set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2 - 100 .set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR - 101 .set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 191 - - - 102 .set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 103 .set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN - 104 .set SCSI_Out_DBx__2__MASK, 0x02 - 105 .set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1 - 106 .set SCSI_Out_DBx__2__PORT, 6 - 107 .set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT - 108 .set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 109 .set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 110 .set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - 111 .set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 112 .set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 113 .set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - 114 .set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 115 .set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS - 116 .set SCSI_Out_DBx__2__SHIFT, 1 - 117 .set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW - 118 .set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG - 119 .set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX - 120 .set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE - 121 .set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK - 122 .set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP - 123 .set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL - 124 .set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0 - 125 .set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1 - 126 .set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2 - 127 .set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR - 128 .set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS - 129 .set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 130 .set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN - 131 .set SCSI_Out_DBx__3__MASK, 0x01 - 132 .set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0 - 133 .set SCSI_Out_DBx__3__PORT, 6 - 134 .set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT - 135 .set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 136 .set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 137 .set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - 138 .set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 139 .set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 140 .set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - 141 .set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 142 .set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS - 143 .set SCSI_Out_DBx__3__SHIFT, 0 - 144 .set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW - 145 .set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG - 146 .set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX - 147 .set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE - 148 .set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK - 149 .set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP - 150 .set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL - 151 .set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0 - 152 .set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1 - 153 .set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2 - 154 .set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR - 155 .set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS - 156 .set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 157 .set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN - 158 .set SCSI_Out_DBx__4__MASK, 0x80 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 192 - - - 159 .set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7 - 160 .set SCSI_Out_DBx__4__PORT, 4 - 161 .set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT - 162 .set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 163 .set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 164 .set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 165 .set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 166 .set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 167 .set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 168 .set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 169 .set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS - 170 .set SCSI_Out_DBx__4__SHIFT, 7 - 171 .set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW - 172 .set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG - 173 .set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX - 174 .set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE - 175 .set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK - 176 .set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP - 177 .set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL - 178 .set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0 - 179 .set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1 - 180 .set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2 - 181 .set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR - 182 .set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS - 183 .set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 184 .set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN - 185 .set SCSI_Out_DBx__5__MASK, 0x40 - 186 .set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6 - 187 .set SCSI_Out_DBx__5__PORT, 4 - 188 .set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT - 189 .set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 190 .set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 191 .set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 192 .set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 193 .set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 194 .set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 195 .set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 196 .set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS - 197 .set SCSI_Out_DBx__5__SHIFT, 6 - 198 .set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW - 199 .set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG - 200 .set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX - 201 .set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE - 202 .set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK - 203 .set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP - 204 .set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL - 205 .set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0 - 206 .set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1 - 207 .set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2 - 208 .set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR - 209 .set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS - 210 .set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 211 .set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN - 212 .set SCSI_Out_DBx__6__MASK, 0x20 - 213 .set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5 - 214 .set SCSI_Out_DBx__6__PORT, 4 - 215 .set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 193 - - - 216 .set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 217 .set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 218 .set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 219 .set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 220 .set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 221 .set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 222 .set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 223 .set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS - 224 .set SCSI_Out_DBx__6__SHIFT, 5 - 225 .set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW - 226 .set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG - 227 .set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX - 228 .set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE - 229 .set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK - 230 .set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP - 231 .set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL - 232 .set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0 - 233 .set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1 - 234 .set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2 - 235 .set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR - 236 .set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS - 237 .set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 238 .set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN - 239 .set SCSI_Out_DBx__7__MASK, 0x10 - 240 .set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4 - 241 .set SCSI_Out_DBx__7__PORT, 4 - 242 .set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT - 243 .set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 244 .set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 245 .set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 246 .set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 247 .set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 248 .set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 249 .set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 250 .set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS - 251 .set SCSI_Out_DBx__7__SHIFT, 4 - 252 .set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW - 253 .set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG - 254 .set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX - 255 .set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE - 256 .set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK - 257 .set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP - 258 .set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL - 259 .set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0 - 260 .set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1 - 261 .set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2 - 262 .set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR - 263 .set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS - 264 .set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 265 .set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN - 266 .set SCSI_Out_DBx__DB0__MASK, 0x08 - 267 .set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3 - 268 .set SCSI_Out_DBx__DB0__PORT, 6 - 269 .set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT - 270 .set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 271 .set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 272 .set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 194 - - - 273 .set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 274 .set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 275 .set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - 276 .set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 277 .set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS - 278 .set SCSI_Out_DBx__DB0__SHIFT, 3 - 279 .set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW - 280 .set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG - 281 .set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX - 282 .set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE - 283 .set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK - 284 .set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP - 285 .set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL - 286 .set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0 - 287 .set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1 - 288 .set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2 - 289 .set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR - 290 .set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS - 291 .set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 292 .set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN - 293 .set SCSI_Out_DBx__DB1__MASK, 0x04 - 294 .set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2 - 295 .set SCSI_Out_DBx__DB1__PORT, 6 - 296 .set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT - 297 .set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 298 .set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 299 .set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - 300 .set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 301 .set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 302 .set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - 303 .set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 304 .set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS - 305 .set SCSI_Out_DBx__DB1__SHIFT, 2 - 306 .set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW - 307 .set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG - 308 .set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX - 309 .set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE - 310 .set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK - 311 .set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP - 312 .set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL - 313 .set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0 - 314 .set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1 - 315 .set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2 - 316 .set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR - 317 .set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS - 318 .set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 319 .set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN - 320 .set SCSI_Out_DBx__DB2__MASK, 0x02 - 321 .set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1 - 322 .set SCSI_Out_DBx__DB2__PORT, 6 - 323 .set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT - 324 .set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 325 .set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 326 .set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - 327 .set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 328 .set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 329 .set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 195 - - - 330 .set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 331 .set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS - 332 .set SCSI_Out_DBx__DB2__SHIFT, 1 - 333 .set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW - 334 .set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG - 335 .set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX - 336 .set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE - 337 .set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK - 338 .set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP - 339 .set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL - 340 .set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0 - 341 .set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1 - 342 .set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2 - 343 .set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR - 344 .set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS - 345 .set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG - 346 .set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN - 347 .set SCSI_Out_DBx__DB3__MASK, 0x01 - 348 .set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0 - 349 .set SCSI_Out_DBx__DB3__PORT, 6 - 350 .set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT - 351 .set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL - 352 .set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN - 353 .set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 - 354 .set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 - 355 .set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 - 356 .set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 - 357 .set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT - 358 .set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS - 359 .set SCSI_Out_DBx__DB3__SHIFT, 0 - 360 .set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW - 361 .set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG - 362 .set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX - 363 .set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE - 364 .set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK - 365 .set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP - 366 .set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL - 367 .set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0 - 368 .set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1 - 369 .set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2 - 370 .set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR - 371 .set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS - 372 .set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 373 .set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN - 374 .set SCSI_Out_DBx__DB4__MASK, 0x80 - 375 .set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7 - 376 .set SCSI_Out_DBx__DB4__PORT, 4 - 377 .set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT - 378 .set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 379 .set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 380 .set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 381 .set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 382 .set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 383 .set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 384 .set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 385 .set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS - 386 .set SCSI_Out_DBx__DB4__SHIFT, 7 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 196 - - - 387 .set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW - 388 .set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG - 389 .set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX - 390 .set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE - 391 .set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK - 392 .set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP - 393 .set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL - 394 .set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0 - 395 .set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1 - 396 .set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2 - 397 .set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR - 398 .set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS - 399 .set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 400 .set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN - 401 .set SCSI_Out_DBx__DB5__MASK, 0x40 - 402 .set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6 - 403 .set SCSI_Out_DBx__DB5__PORT, 4 - 404 .set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT - 405 .set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 406 .set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 407 .set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 408 .set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 409 .set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 410 .set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 411 .set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 412 .set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS - 413 .set SCSI_Out_DBx__DB5__SHIFT, 6 - 414 .set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW - 415 .set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG - 416 .set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX - 417 .set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE - 418 .set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK - 419 .set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP - 420 .set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL - 421 .set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0 - 422 .set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1 - 423 .set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2 - 424 .set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR - 425 .set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS - 426 .set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 427 .set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN - 428 .set SCSI_Out_DBx__DB6__MASK, 0x20 - 429 .set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5 - 430 .set SCSI_Out_DBx__DB6__PORT, 4 - 431 .set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT - 432 .set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 433 .set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 434 .set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 435 .set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 436 .set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 437 .set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 438 .set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 439 .set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS - 440 .set SCSI_Out_DBx__DB6__SHIFT, 5 - 441 .set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW - 442 .set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG - 443 .set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 197 - - - 444 .set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE - 445 .set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK - 446 .set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP - 447 .set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL - 448 .set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0 - 449 .set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1 - 450 .set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2 - 451 .set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR - 452 .set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS - 453 .set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 454 .set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN - 455 .set SCSI_Out_DBx__DB7__MASK, 0x10 - 456 .set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4 - 457 .set SCSI_Out_DBx__DB7__PORT, 4 - 458 .set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT - 459 .set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 460 .set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 461 .set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 462 .set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 463 .set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 464 .set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 465 .set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 466 .set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS - 467 .set SCSI_Out_DBx__DB7__SHIFT, 4 - 468 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW - 469 - 470 /* USBFS_dp_int */ - 471 .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 - 472 .set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 - 473 .set USBFS_dp_int__INTC_MASK, 0x1000 - 474 .set USBFS_dp_int__INTC_NUMBER, 12 - 475 .set USBFS_dp_int__INTC_PRIOR_NUM, 7 - 476 .set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 - 477 .set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 - 478 .set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - 479 - 480 /* USBFS_ep_0 */ - 481 .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 - 482 .set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 - 483 .set USBFS_ep_0__INTC_MASK, 0x1000000 - 484 .set USBFS_ep_0__INTC_NUMBER, 24 - 485 .set USBFS_ep_0__INTC_PRIOR_NUM, 7 - 486 .set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 - 487 .set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 - 488 .set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - 489 - 490 /* USBFS_ep_1 */ - 491 .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 - 492 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 - 493 .set USBFS_ep_1__INTC_MASK, 0x01 - 494 .set USBFS_ep_1__INTC_NUMBER, 0 - 495 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 - 496 .set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 - 497 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 - 498 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - 499 - 500 /* USBFS_ep_2 */ - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 198 - - - 501 .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 - 502 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 - 503 .set USBFS_ep_2__INTC_MASK, 0x02 - 504 .set USBFS_ep_2__INTC_NUMBER, 1 - 505 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 - 506 .set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 - 507 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 - 508 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - 509 - 510 /* SD_PULLUP */ - 511 .set SD_PULLUP__0__MASK, 0x02 - 512 .set SD_PULLUP__0__PC, CYREG_PRT3_PC1 - 513 .set SD_PULLUP__0__PORT, 3 - 514 .set SD_PULLUP__0__SHIFT, 1 - 515 .set SD_PULLUP__1__MASK, 0x04 - 516 .set SD_PULLUP__1__PC, CYREG_PRT3_PC2 - 517 .set SD_PULLUP__1__PORT, 3 - 518 .set SD_PULLUP__1__SHIFT, 2 - 519 .set SD_PULLUP__2__MASK, 0x08 - 520 .set SD_PULLUP__2__PC, CYREG_PRT3_PC3 - 521 .set SD_PULLUP__2__PORT, 3 - 522 .set SD_PULLUP__2__SHIFT, 3 - 523 .set SD_PULLUP__3__MASK, 0x10 - 524 .set SD_PULLUP__3__PC, CYREG_PRT3_PC4 - 525 .set SD_PULLUP__3__PORT, 3 - 526 .set SD_PULLUP__3__SHIFT, 4 - 527 .set SD_PULLUP__4__MASK, 0x20 - 528 .set SD_PULLUP__4__PC, CYREG_PRT3_PC5 - 529 .set SD_PULLUP__4__PORT, 3 - 530 .set SD_PULLUP__4__SHIFT, 5 - 531 .set SD_PULLUP__AG, CYREG_PRT3_AG - 532 .set SD_PULLUP__AMUX, CYREG_PRT3_AMUX - 533 .set SD_PULLUP__BIE, CYREG_PRT3_BIE - 534 .set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK - 535 .set SD_PULLUP__BYP, CYREG_PRT3_BYP - 536 .set SD_PULLUP__CTL, CYREG_PRT3_CTL - 537 .set SD_PULLUP__DM0, CYREG_PRT3_DM0 - 538 .set SD_PULLUP__DM1, CYREG_PRT3_DM1 - 539 .set SD_PULLUP__DM2, CYREG_PRT3_DM2 - 540 .set SD_PULLUP__DR, CYREG_PRT3_DR - 541 .set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS - 542 .set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG - 543 .set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN - 544 .set SD_PULLUP__MASK, 0x3E - 545 .set SD_PULLUP__PORT, 3 - 546 .set SD_PULLUP__PRT, CYREG_PRT3_PRT - 547 .set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL - 548 .set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN - 549 .set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 - 550 .set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 - 551 .set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 - 552 .set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 - 553 .set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT - 554 .set SD_PULLUP__PS, CYREG_PRT3_PS - 555 .set SD_PULLUP__SHIFT, 1 - 556 .set SD_PULLUP__SLW, CYREG_PRT3_SLW - 557 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 199 - - - 558 /* USBFS_USB */ - 559 .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG - 560 .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG - 561 .set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN - 562 .set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR - 563 .set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG - 564 .set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN - 565 .set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR - 566 .set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG - 567 .set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN - 568 .set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR - 569 .set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG - 570 .set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN - 571 .set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR - 572 .set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG - 573 .set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN - 574 .set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR - 575 .set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG - 576 .set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN - 577 .set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR - 578 .set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG - 579 .set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN - 580 .set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR - 581 .set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG - 582 .set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN - 583 .set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR - 584 .set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN - 585 .set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR - 586 .set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR - 587 .set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA - 588 .set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB - 589 .set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA - 590 .set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB - 591 .set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR - 592 .set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA - 593 .set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB - 594 .set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA - 595 .set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB - 596 .set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR - 597 .set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA - 598 .set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB - 599 .set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA - 600 .set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB - 601 .set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR - 602 .set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA - 603 .set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB - 604 .set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA - 605 .set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB - 606 .set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR - 607 .set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA - 608 .set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB - 609 .set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA - 610 .set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB - 611 .set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR - 612 .set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA - 613 .set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB - 614 .set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 200 - - - 615 .set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB - 616 .set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR - 617 .set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA - 618 .set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB - 619 .set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA - 620 .set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB - 621 .set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR - 622 .set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA - 623 .set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB - 624 .set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA - 625 .set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB - 626 .set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE - 627 .set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT - 628 .set USBFS_USB__CR0, CYREG_USB_CR0 - 629 .set USBFS_USB__CR1, CYREG_USB_CR1 - 630 .set USBFS_USB__CWA, CYREG_USB_CWA - 631 .set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB - 632 .set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES - 633 .set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB - 634 .set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG - 635 .set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT - 636 .set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR - 637 .set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 - 638 .set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 - 639 .set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 - 640 .set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 - 641 .set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 - 642 .set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 - 643 .set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 - 644 .set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 - 645 .set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE - 646 .set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE - 647 .set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE - 648 .set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 - 649 .set USBFS_USB__PM_ACT_MSK, 0x01 - 650 .set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 - 651 .set USBFS_USB__PM_STBY_MSK, 0x01 - 652 .set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 - 653 .set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 - 654 .set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 - 655 .set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 - 656 .set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 - 657 .set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 - 658 .set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 - 659 .set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 - 660 .set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 - 661 .set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 - 662 .set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 - 663 .set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 - 664 .set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 - 665 .set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 - 666 .set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 - 667 .set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 - 668 .set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 - 669 .set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 - 670 .set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 - 671 .set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 201 - - - 672 .set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 - 673 .set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 - 674 .set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 - 675 .set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 - 676 .set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN - 677 .set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR - 678 .set USBFS_USB__SOF0, CYREG_USB_SOF0 - 679 .set USBFS_USB__SOF1, CYREG_USB_SOF1 - 680 .set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 - 681 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 - 682 .set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN - 683 - 684 /* SCSI_Out */ - 685 .set SCSI_Out__0__AG, CYREG_PRT4_AG - 686 .set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX - 687 .set SCSI_Out__0__BIE, CYREG_PRT4_BIE - 688 .set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK - 689 .set SCSI_Out__0__BYP, CYREG_PRT4_BYP - 690 .set SCSI_Out__0__CTL, CYREG_PRT4_CTL - 691 .set SCSI_Out__0__DM0, CYREG_PRT4_DM0 - 692 .set SCSI_Out__0__DM1, CYREG_PRT4_DM1 - 693 .set SCSI_Out__0__DM2, CYREG_PRT4_DM2 - 694 .set SCSI_Out__0__DR, CYREG_PRT4_DR - 695 .set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS - 696 .set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 697 .set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN - 698 .set SCSI_Out__0__MASK, 0x08 - 699 .set SCSI_Out__0__PC, CYREG_PRT4_PC3 - 700 .set SCSI_Out__0__PORT, 4 - 701 .set SCSI_Out__0__PRT, CYREG_PRT4_PRT - 702 .set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 703 .set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 704 .set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 705 .set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 706 .set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 707 .set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 708 .set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 709 .set SCSI_Out__0__PS, CYREG_PRT4_PS - 710 .set SCSI_Out__0__SHIFT, 3 - 711 .set SCSI_Out__0__SLW, CYREG_PRT4_SLW - 712 .set SCSI_Out__1__AG, CYREG_PRT4_AG - 713 .set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX - 714 .set SCSI_Out__1__BIE, CYREG_PRT4_BIE - 715 .set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK - 716 .set SCSI_Out__1__BYP, CYREG_PRT4_BYP - 717 .set SCSI_Out__1__CTL, CYREG_PRT4_CTL - 718 .set SCSI_Out__1__DM0, CYREG_PRT4_DM0 - 719 .set SCSI_Out__1__DM1, CYREG_PRT4_DM1 - 720 .set SCSI_Out__1__DM2, CYREG_PRT4_DM2 - 721 .set SCSI_Out__1__DR, CYREG_PRT4_DR - 722 .set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS - 723 .set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 724 .set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN - 725 .set SCSI_Out__1__MASK, 0x04 - 726 .set SCSI_Out__1__PC, CYREG_PRT4_PC2 - 727 .set SCSI_Out__1__PORT, 4 - 728 .set SCSI_Out__1__PRT, CYREG_PRT4_PRT - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 202 - - - 729 .set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 730 .set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 731 .set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 732 .set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 733 .set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 734 .set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 735 .set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 736 .set SCSI_Out__1__PS, CYREG_PRT4_PS - 737 .set SCSI_Out__1__SHIFT, 2 - 738 .set SCSI_Out__1__SLW, CYREG_PRT4_SLW - 739 .set SCSI_Out__2__AG, CYREG_PRT0_AG - 740 .set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX - 741 .set SCSI_Out__2__BIE, CYREG_PRT0_BIE - 742 .set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK - 743 .set SCSI_Out__2__BYP, CYREG_PRT0_BYP - 744 .set SCSI_Out__2__CTL, CYREG_PRT0_CTL - 745 .set SCSI_Out__2__DM0, CYREG_PRT0_DM0 - 746 .set SCSI_Out__2__DM1, CYREG_PRT0_DM1 - 747 .set SCSI_Out__2__DM2, CYREG_PRT0_DM2 - 748 .set SCSI_Out__2__DR, CYREG_PRT0_DR - 749 .set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS - 750 .set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 751 .set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN - 752 .set SCSI_Out__2__MASK, 0x80 - 753 .set SCSI_Out__2__PC, CYREG_PRT0_PC7 - 754 .set SCSI_Out__2__PORT, 0 - 755 .set SCSI_Out__2__PRT, CYREG_PRT0_PRT - 756 .set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 757 .set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 758 .set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 759 .set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 760 .set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 761 .set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 762 .set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 763 .set SCSI_Out__2__PS, CYREG_PRT0_PS - 764 .set SCSI_Out__2__SHIFT, 7 - 765 .set SCSI_Out__2__SLW, CYREG_PRT0_SLW - 766 .set SCSI_Out__3__AG, CYREG_PRT0_AG - 767 .set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX - 768 .set SCSI_Out__3__BIE, CYREG_PRT0_BIE - 769 .set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK - 770 .set SCSI_Out__3__BYP, CYREG_PRT0_BYP - 771 .set SCSI_Out__3__CTL, CYREG_PRT0_CTL - 772 .set SCSI_Out__3__DM0, CYREG_PRT0_DM0 - 773 .set SCSI_Out__3__DM1, CYREG_PRT0_DM1 - 774 .set SCSI_Out__3__DM2, CYREG_PRT0_DM2 - 775 .set SCSI_Out__3__DR, CYREG_PRT0_DR - 776 .set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS - 777 .set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 778 .set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN - 779 .set SCSI_Out__3__MASK, 0x40 - 780 .set SCSI_Out__3__PC, CYREG_PRT0_PC6 - 781 .set SCSI_Out__3__PORT, 0 - 782 .set SCSI_Out__3__PRT, CYREG_PRT0_PRT - 783 .set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 784 .set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 785 .set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 203 - - - 786 .set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 787 .set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 788 .set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 789 .set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 790 .set SCSI_Out__3__PS, CYREG_PRT0_PS - 791 .set SCSI_Out__3__SHIFT, 6 - 792 .set SCSI_Out__3__SLW, CYREG_PRT0_SLW - 793 .set SCSI_Out__4__AG, CYREG_PRT0_AG - 794 .set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX - 795 .set SCSI_Out__4__BIE, CYREG_PRT0_BIE - 796 .set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK - 797 .set SCSI_Out__4__BYP, CYREG_PRT0_BYP - 798 .set SCSI_Out__4__CTL, CYREG_PRT0_CTL - 799 .set SCSI_Out__4__DM0, CYREG_PRT0_DM0 - 800 .set SCSI_Out__4__DM1, CYREG_PRT0_DM1 - 801 .set SCSI_Out__4__DM2, CYREG_PRT0_DM2 - 802 .set SCSI_Out__4__DR, CYREG_PRT0_DR - 803 .set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS - 804 .set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 805 .set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN - 806 .set SCSI_Out__4__MASK, 0x20 - 807 .set SCSI_Out__4__PC, CYREG_PRT0_PC5 - 808 .set SCSI_Out__4__PORT, 0 - 809 .set SCSI_Out__4__PRT, CYREG_PRT0_PRT - 810 .set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 811 .set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 812 .set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 813 .set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 814 .set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 815 .set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 816 .set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 817 .set SCSI_Out__4__PS, CYREG_PRT0_PS - 818 .set SCSI_Out__4__SHIFT, 5 - 819 .set SCSI_Out__4__SLW, CYREG_PRT0_SLW - 820 .set SCSI_Out__5__AG, CYREG_PRT0_AG - 821 .set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX - 822 .set SCSI_Out__5__BIE, CYREG_PRT0_BIE - 823 .set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK - 824 .set SCSI_Out__5__BYP, CYREG_PRT0_BYP - 825 .set SCSI_Out__5__CTL, CYREG_PRT0_CTL - 826 .set SCSI_Out__5__DM0, CYREG_PRT0_DM0 - 827 .set SCSI_Out__5__DM1, CYREG_PRT0_DM1 - 828 .set SCSI_Out__5__DM2, CYREG_PRT0_DM2 - 829 .set SCSI_Out__5__DR, CYREG_PRT0_DR - 830 .set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS - 831 .set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 832 .set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN - 833 .set SCSI_Out__5__MASK, 0x10 - 834 .set SCSI_Out__5__PC, CYREG_PRT0_PC4 - 835 .set SCSI_Out__5__PORT, 0 - 836 .set SCSI_Out__5__PRT, CYREG_PRT0_PRT - 837 .set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 838 .set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 839 .set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 840 .set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 841 .set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 842 .set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 204 - - - 843 .set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 844 .set SCSI_Out__5__PS, CYREG_PRT0_PS - 845 .set SCSI_Out__5__SHIFT, 4 - 846 .set SCSI_Out__5__SLW, CYREG_PRT0_SLW - 847 .set SCSI_Out__6__AG, CYREG_PRT0_AG - 848 .set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX - 849 .set SCSI_Out__6__BIE, CYREG_PRT0_BIE - 850 .set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK - 851 .set SCSI_Out__6__BYP, CYREG_PRT0_BYP - 852 .set SCSI_Out__6__CTL, CYREG_PRT0_CTL - 853 .set SCSI_Out__6__DM0, CYREG_PRT0_DM0 - 854 .set SCSI_Out__6__DM1, CYREG_PRT0_DM1 - 855 .set SCSI_Out__6__DM2, CYREG_PRT0_DM2 - 856 .set SCSI_Out__6__DR, CYREG_PRT0_DR - 857 .set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS - 858 .set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 859 .set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN - 860 .set SCSI_Out__6__MASK, 0x08 - 861 .set SCSI_Out__6__PC, CYREG_PRT0_PC3 - 862 .set SCSI_Out__6__PORT, 0 - 863 .set SCSI_Out__6__PRT, CYREG_PRT0_PRT - 864 .set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 865 .set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 866 .set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 867 .set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 868 .set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 869 .set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 870 .set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 871 .set SCSI_Out__6__PS, CYREG_PRT0_PS - 872 .set SCSI_Out__6__SHIFT, 3 - 873 .set SCSI_Out__6__SLW, CYREG_PRT0_SLW - 874 .set SCSI_Out__7__AG, CYREG_PRT0_AG - 875 .set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX - 876 .set SCSI_Out__7__BIE, CYREG_PRT0_BIE - 877 .set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK - 878 .set SCSI_Out__7__BYP, CYREG_PRT0_BYP - 879 .set SCSI_Out__7__CTL, CYREG_PRT0_CTL - 880 .set SCSI_Out__7__DM0, CYREG_PRT0_DM0 - 881 .set SCSI_Out__7__DM1, CYREG_PRT0_DM1 - 882 .set SCSI_Out__7__DM2, CYREG_PRT0_DM2 - 883 .set SCSI_Out__7__DR, CYREG_PRT0_DR - 884 .set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS - 885 .set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 886 .set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN - 887 .set SCSI_Out__7__MASK, 0x04 - 888 .set SCSI_Out__7__PC, CYREG_PRT0_PC2 - 889 .set SCSI_Out__7__PORT, 0 - 890 .set SCSI_Out__7__PRT, CYREG_PRT0_PRT - 891 .set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 892 .set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 893 .set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 894 .set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 895 .set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 896 .set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 897 .set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 898 .set SCSI_Out__7__PS, CYREG_PRT0_PS - 899 .set SCSI_Out__7__SHIFT, 2 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 205 - - - 900 .set SCSI_Out__7__SLW, CYREG_PRT0_SLW - 901 .set SCSI_Out__8__AG, CYREG_PRT0_AG - 902 .set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX - 903 .set SCSI_Out__8__BIE, CYREG_PRT0_BIE - 904 .set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK - 905 .set SCSI_Out__8__BYP, CYREG_PRT0_BYP - 906 .set SCSI_Out__8__CTL, CYREG_PRT0_CTL - 907 .set SCSI_Out__8__DM0, CYREG_PRT0_DM0 - 908 .set SCSI_Out__8__DM1, CYREG_PRT0_DM1 - 909 .set SCSI_Out__8__DM2, CYREG_PRT0_DM2 - 910 .set SCSI_Out__8__DR, CYREG_PRT0_DR - 911 .set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS - 912 .set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 913 .set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN - 914 .set SCSI_Out__8__MASK, 0x02 - 915 .set SCSI_Out__8__PC, CYREG_PRT0_PC1 - 916 .set SCSI_Out__8__PORT, 0 - 917 .set SCSI_Out__8__PRT, CYREG_PRT0_PRT - 918 .set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 919 .set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 920 .set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 921 .set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 922 .set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 923 .set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 924 .set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 925 .set SCSI_Out__8__PS, CYREG_PRT0_PS - 926 .set SCSI_Out__8__SHIFT, 1 - 927 .set SCSI_Out__8__SLW, CYREG_PRT0_SLW - 928 .set SCSI_Out__9__AG, CYREG_PRT0_AG - 929 .set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX - 930 .set SCSI_Out__9__BIE, CYREG_PRT0_BIE - 931 .set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK - 932 .set SCSI_Out__9__BYP, CYREG_PRT0_BYP - 933 .set SCSI_Out__9__CTL, CYREG_PRT0_CTL - 934 .set SCSI_Out__9__DM0, CYREG_PRT0_DM0 - 935 .set SCSI_Out__9__DM1, CYREG_PRT0_DM1 - 936 .set SCSI_Out__9__DM2, CYREG_PRT0_DM2 - 937 .set SCSI_Out__9__DR, CYREG_PRT0_DR - 938 .set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS - 939 .set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 940 .set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN - 941 .set SCSI_Out__9__MASK, 0x01 - 942 .set SCSI_Out__9__PC, CYREG_PRT0_PC0 - 943 .set SCSI_Out__9__PORT, 0 - 944 .set SCSI_Out__9__PRT, CYREG_PRT0_PRT - 945 .set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 946 .set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 947 .set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 948 .set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 949 .set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 950 .set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 951 .set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 952 .set SCSI_Out__9__PS, CYREG_PRT0_PS - 953 .set SCSI_Out__9__SHIFT, 0 - 954 .set SCSI_Out__9__SLW, CYREG_PRT0_SLW - 955 .set SCSI_Out__ACK__AG, CYREG_PRT0_AG - 956 .set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 206 - - - 957 .set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE - 958 .set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK - 959 .set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP - 960 .set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL - 961 .set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0 - 962 .set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1 - 963 .set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2 - 964 .set SCSI_Out__ACK__DR, CYREG_PRT0_DR - 965 .set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS - 966 .set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 967 .set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN - 968 .set SCSI_Out__ACK__MASK, 0x40 - 969 .set SCSI_Out__ACK__PC, CYREG_PRT0_PC6 - 970 .set SCSI_Out__ACK__PORT, 0 - 971 .set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT - 972 .set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 973 .set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 974 .set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 975 .set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 976 .set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 977 .set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 978 .set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 979 .set SCSI_Out__ACK__PS, CYREG_PRT0_PS - 980 .set SCSI_Out__ACK__SHIFT, 6 - 981 .set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW - 982 .set SCSI_Out__ATN__AG, CYREG_PRT4_AG - 983 .set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX - 984 .set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE - 985 .set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK - 986 .set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP - 987 .set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL - 988 .set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0 - 989 .set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1 - 990 .set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2 - 991 .set SCSI_Out__ATN__DR, CYREG_PRT4_DR - 992 .set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS - 993 .set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 994 .set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN - 995 .set SCSI_Out__ATN__MASK, 0x04 - 996 .set SCSI_Out__ATN__PC, CYREG_PRT4_PC2 - 997 .set SCSI_Out__ATN__PORT, 4 - 998 .set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT - 999 .set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 1000 .set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 1001 .set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 1002 .set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 1003 .set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 1004 .set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 1005 .set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 1006 .set SCSI_Out__ATN__PS, CYREG_PRT4_PS - 1007 .set SCSI_Out__ATN__SHIFT, 2 - 1008 .set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW - 1009 .set SCSI_Out__BSY__AG, CYREG_PRT0_AG - 1010 .set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX - 1011 .set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE - 1012 .set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK - 1013 .set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 207 - - - 1014 .set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL - 1015 .set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0 - 1016 .set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1 - 1017 .set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2 - 1018 .set SCSI_Out__BSY__DR, CYREG_PRT0_DR - 1019 .set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS - 1020 .set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1021 .set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN - 1022 .set SCSI_Out__BSY__MASK, 0x80 - 1023 .set SCSI_Out__BSY__PC, CYREG_PRT0_PC7 - 1024 .set SCSI_Out__BSY__PORT, 0 - 1025 .set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT - 1026 .set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1027 .set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1028 .set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1029 .set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1030 .set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1031 .set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1032 .set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1033 .set SCSI_Out__BSY__PS, CYREG_PRT0_PS - 1034 .set SCSI_Out__BSY__SHIFT, 7 - 1035 .set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW - 1036 .set SCSI_Out__CD__AG, CYREG_PRT0_AG - 1037 .set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX - 1038 .set SCSI_Out__CD__BIE, CYREG_PRT0_BIE - 1039 .set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK - 1040 .set SCSI_Out__CD__BYP, CYREG_PRT0_BYP - 1041 .set SCSI_Out__CD__CTL, CYREG_PRT0_CTL - 1042 .set SCSI_Out__CD__DM0, CYREG_PRT0_DM0 - 1043 .set SCSI_Out__CD__DM1, CYREG_PRT0_DM1 - 1044 .set SCSI_Out__CD__DM2, CYREG_PRT0_DM2 - 1045 .set SCSI_Out__CD__DR, CYREG_PRT0_DR - 1046 .set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS - 1047 .set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1048 .set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN - 1049 .set SCSI_Out__CD__MASK, 0x04 - 1050 .set SCSI_Out__CD__PC, CYREG_PRT0_PC2 - 1051 .set SCSI_Out__CD__PORT, 0 - 1052 .set SCSI_Out__CD__PRT, CYREG_PRT0_PRT - 1053 .set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1054 .set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1055 .set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1056 .set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1057 .set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1058 .set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1059 .set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1060 .set SCSI_Out__CD__PS, CYREG_PRT0_PS - 1061 .set SCSI_Out__CD__SHIFT, 2 - 1062 .set SCSI_Out__CD__SLW, CYREG_PRT0_SLW - 1063 .set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG - 1064 .set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX - 1065 .set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE - 1066 .set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK - 1067 .set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP - 1068 .set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL - 1069 .set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0 - 1070 .set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 208 - - - 1071 .set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2 - 1072 .set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR - 1073 .set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS - 1074 .set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG - 1075 .set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN - 1076 .set SCSI_Out__DBP_raw__MASK, 0x08 - 1077 .set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3 - 1078 .set SCSI_Out__DBP_raw__PORT, 4 - 1079 .set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT - 1080 .set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL - 1081 .set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN - 1082 .set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 - 1083 .set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 - 1084 .set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 - 1085 .set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 - 1086 .set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT - 1087 .set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS - 1088 .set SCSI_Out__DBP_raw__SHIFT, 3 - 1089 .set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW - 1090 .set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG - 1091 .set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX - 1092 .set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE - 1093 .set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK - 1094 .set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP - 1095 .set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL - 1096 .set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0 - 1097 .set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1 - 1098 .set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2 - 1099 .set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR - 1100 .set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS - 1101 .set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1102 .set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN - 1103 .set SCSI_Out__IO_raw__MASK, 0x01 - 1104 .set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0 - 1105 .set SCSI_Out__IO_raw__PORT, 0 - 1106 .set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT - 1107 .set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1108 .set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1109 .set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1110 .set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1111 .set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1112 .set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1113 .set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1114 .set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS - 1115 .set SCSI_Out__IO_raw__SHIFT, 0 - 1116 .set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW - 1117 .set SCSI_Out__MSG__AG, CYREG_PRT0_AG - 1118 .set SCSI_Out__MSG__AMUX, CYREG_PRT0_AMUX - 1119 .set SCSI_Out__MSG__BIE, CYREG_PRT0_BIE - 1120 .set SCSI_Out__MSG__BIT_MASK, CYREG_PRT0_BIT_MASK - 1121 .set SCSI_Out__MSG__BYP, CYREG_PRT0_BYP - 1122 .set SCSI_Out__MSG__CTL, CYREG_PRT0_CTL - 1123 .set SCSI_Out__MSG__DM0, CYREG_PRT0_DM0 - 1124 .set SCSI_Out__MSG__DM1, CYREG_PRT0_DM1 - 1125 .set SCSI_Out__MSG__DM2, CYREG_PRT0_DM2 - 1126 .set SCSI_Out__MSG__DR, CYREG_PRT0_DR - 1127 .set SCSI_Out__MSG__INP_DIS, CYREG_PRT0_INP_DIS - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 209 - - - 1128 .set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1129 .set SCSI_Out__MSG__LCD_EN, CYREG_PRT0_LCD_EN - 1130 .set SCSI_Out__MSG__MASK, 0x10 - 1131 .set SCSI_Out__MSG__PC, CYREG_PRT0_PC4 - 1132 .set SCSI_Out__MSG__PORT, 0 - 1133 .set SCSI_Out__MSG__PRT, CYREG_PRT0_PRT - 1134 .set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1135 .set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1136 .set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1137 .set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1138 .set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1139 .set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1140 .set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1141 .set SCSI_Out__MSG__PS, CYREG_PRT0_PS - 1142 .set SCSI_Out__MSG__SHIFT, 4 - 1143 .set SCSI_Out__MSG__SLW, CYREG_PRT0_SLW - 1144 .set SCSI_Out__REQ__AG, CYREG_PRT0_AG - 1145 .set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX - 1146 .set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE - 1147 .set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK - 1148 .set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP - 1149 .set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL - 1150 .set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0 - 1151 .set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1 - 1152 .set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2 - 1153 .set SCSI_Out__REQ__DR, CYREG_PRT0_DR - 1154 .set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS - 1155 .set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1156 .set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN - 1157 .set SCSI_Out__REQ__MASK, 0x02 - 1158 .set SCSI_Out__REQ__PC, CYREG_PRT0_PC1 - 1159 .set SCSI_Out__REQ__PORT, 0 - 1160 .set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT - 1161 .set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1162 .set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1163 .set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1164 .set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1165 .set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1166 .set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1167 .set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1168 .set SCSI_Out__REQ__PS, CYREG_PRT0_PS - 1169 .set SCSI_Out__REQ__SHIFT, 1 - 1170 .set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW - 1171 .set SCSI_Out__RST__AG, CYREG_PRT0_AG - 1172 .set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX - 1173 .set SCSI_Out__RST__BIE, CYREG_PRT0_BIE - 1174 .set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK - 1175 .set SCSI_Out__RST__BYP, CYREG_PRT0_BYP - 1176 .set SCSI_Out__RST__CTL, CYREG_PRT0_CTL - 1177 .set SCSI_Out__RST__DM0, CYREG_PRT0_DM0 - 1178 .set SCSI_Out__RST__DM1, CYREG_PRT0_DM1 - 1179 .set SCSI_Out__RST__DM2, CYREG_PRT0_DM2 - 1180 .set SCSI_Out__RST__DR, CYREG_PRT0_DR - 1181 .set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS - 1182 .set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1183 .set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN - 1184 .set SCSI_Out__RST__MASK, 0x20 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 210 - - - 1185 .set SCSI_Out__RST__PC, CYREG_PRT0_PC5 - 1186 .set SCSI_Out__RST__PORT, 0 - 1187 .set SCSI_Out__RST__PRT, CYREG_PRT0_PRT - 1188 .set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1189 .set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1190 .set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1191 .set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1192 .set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1193 .set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1194 .set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1195 .set SCSI_Out__RST__PS, CYREG_PRT0_PS - 1196 .set SCSI_Out__RST__SHIFT, 5 - 1197 .set SCSI_Out__RST__SLW, CYREG_PRT0_SLW - 1198 .set SCSI_Out__SEL__AG, CYREG_PRT0_AG - 1199 .set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX - 1200 .set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE - 1201 .set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK - 1202 .set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP - 1203 .set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL - 1204 .set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 - 1205 .set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 - 1206 .set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 - 1207 .set SCSI_Out__SEL__DR, CYREG_PRT0_DR - 1208 .set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS - 1209 .set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG - 1210 .set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN - 1211 .set SCSI_Out__SEL__MASK, 0x08 - 1212 .set SCSI_Out__SEL__PC, CYREG_PRT0_PC3 - 1213 .set SCSI_Out__SEL__PORT, 0 - 1214 .set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT - 1215 .set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL - 1216 .set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN - 1217 .set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 - 1218 .set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 - 1219 .set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 - 1220 .set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 - 1221 .set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT - 1222 .set SCSI_Out__SEL__PS, CYREG_PRT0_PS - 1223 .set SCSI_Out__SEL__SHIFT, 3 - 1224 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW - 1225 - 1226 /* USBFS_Dm */ - 1227 .set USBFS_Dm__0__MASK, 0x80 - 1228 .set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 - 1229 .set USBFS_Dm__0__PORT, 15 - 1230 .set USBFS_Dm__0__SHIFT, 7 - 1231 .set USBFS_Dm__AG, CYREG_PRT15_AG - 1232 .set USBFS_Dm__AMUX, CYREG_PRT15_AMUX - 1233 .set USBFS_Dm__BIE, CYREG_PRT15_BIE - 1234 .set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK - 1235 .set USBFS_Dm__BYP, CYREG_PRT15_BYP - 1236 .set USBFS_Dm__CTL, CYREG_PRT15_CTL - 1237 .set USBFS_Dm__DM0, CYREG_PRT15_DM0 - 1238 .set USBFS_Dm__DM1, CYREG_PRT15_DM1 - 1239 .set USBFS_Dm__DM2, CYREG_PRT15_DM2 - 1240 .set USBFS_Dm__DR, CYREG_PRT15_DR - 1241 .set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 211 - - - 1242 .set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG - 1243 .set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN - 1244 .set USBFS_Dm__MASK, 0x80 - 1245 .set USBFS_Dm__PORT, 15 - 1246 .set USBFS_Dm__PRT, CYREG_PRT15_PRT - 1247 .set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL - 1248 .set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN - 1249 .set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 - 1250 .set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 - 1251 .set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 - 1252 .set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 - 1253 .set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT - 1254 .set USBFS_Dm__PS, CYREG_PRT15_PS - 1255 .set USBFS_Dm__SHIFT, 7 - 1256 .set USBFS_Dm__SLW, CYREG_PRT15_SLW - 1257 - 1258 /* USBFS_Dp */ - 1259 .set USBFS_Dp__0__MASK, 0x40 - 1260 .set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 - 1261 .set USBFS_Dp__0__PORT, 15 - 1262 .set USBFS_Dp__0__SHIFT, 6 - 1263 .set USBFS_Dp__AG, CYREG_PRT15_AG - 1264 .set USBFS_Dp__AMUX, CYREG_PRT15_AMUX - 1265 .set USBFS_Dp__BIE, CYREG_PRT15_BIE - 1266 .set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK - 1267 .set USBFS_Dp__BYP, CYREG_PRT15_BYP - 1268 .set USBFS_Dp__CTL, CYREG_PRT15_CTL - 1269 .set USBFS_Dp__DM0, CYREG_PRT15_DM0 - 1270 .set USBFS_Dp__DM1, CYREG_PRT15_DM1 - 1271 .set USBFS_Dp__DM2, CYREG_PRT15_DM2 - 1272 .set USBFS_Dp__DR, CYREG_PRT15_DR - 1273 .set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS - 1274 .set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT - 1275 .set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG - 1276 .set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN - 1277 .set USBFS_Dp__MASK, 0x40 - 1278 .set USBFS_Dp__PORT, 15 - 1279 .set USBFS_Dp__PRT, CYREG_PRT15_PRT - 1280 .set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL - 1281 .set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN - 1282 .set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 - 1283 .set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 - 1284 .set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 - 1285 .set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 - 1286 .set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT - 1287 .set USBFS_Dp__PS, CYREG_PRT15_PS - 1288 .set USBFS_Dp__SHIFT, 6 - 1289 .set USBFS_Dp__SLW, CYREG_PRT15_SLW - 1290 .set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 - 1291 - 1292 /* Miscellaneous */ - 1293 /* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a f - 1294 .set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0 - 1295 .set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 - 1296 .set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 - 1297 .set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 - 1298 .set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 212 - - - 1299 .set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 - 1300 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 - 1301 .set CYDEV_CHIP_MEMBER_5B, 4 - 1302 .set CYDEV_CHIP_FAMILY_PSOC5, 3 - 1303 .set CYDEV_CHIP_DIE_PSOC5LP, 4 - 1304 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP - 1305 .set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1 - 1306 .set BCLK__BUS_CLK__HZ, 64000000 - 1307 .set BCLK__BUS_CLK__KHZ, 64000 - 1308 .set BCLK__BUS_CLK__MHZ, 64 - 1309 .set CYDEV_BOOTLOADER_APPLICATIONS, 1 - 1310 .set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0 - 1311 .set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1 - 1312 .set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS - 1313 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT - 1314 .set CYDEV_CHIP_DIE_LEOPARD, 1 - 1315 .set CYDEV_CHIP_DIE_PANTHER, 3 - 1316 .set CYDEV_CHIP_DIE_PSOC4A, 2 - 1317 .set CYDEV_CHIP_DIE_UNKNOWN, 0 - 1318 .set CYDEV_CHIP_FAMILY_PSOC3, 1 - 1319 .set CYDEV_CHIP_FAMILY_PSOC4, 2 - 1320 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0 - 1321 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 - 1322 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 - 1323 .set CYDEV_CHIP_MEMBER_3A, 1 - 1324 .set CYDEV_CHIP_MEMBER_4A, 2 - 1325 .set CYDEV_CHIP_MEMBER_5A, 3 - 1326 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 - 1327 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B - 1328 .set CYDEV_CHIP_REVISION_3A_ES1, 0 - 1329 .set CYDEV_CHIP_REVISION_3A_ES2, 1 - 1330 .set CYDEV_CHIP_REVISION_3A_ES3, 3 - 1331 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 - 1332 .set CYDEV_CHIP_REVISION_4A_ES0, 17 - 1333 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 - 1334 .set CYDEV_CHIP_REVISION_5A_ES0, 0 - 1335 .set CYDEV_CHIP_REVISION_5A_ES1, 1 - 1336 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 - 1337 .set CYDEV_CHIP_REVISION_5B_ES0, 0 - 1338 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION - 1339 .set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION - 1340 .set CYDEV_CHIP_REV_LEOPARD_ES1, 0 - 1341 .set CYDEV_CHIP_REV_LEOPARD_ES2, 1 - 1342 .set CYDEV_CHIP_REV_LEOPARD_ES3, 3 - 1343 .set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 - 1344 .set CYDEV_CHIP_REV_PANTHER_ES0, 0 - 1345 .set CYDEV_CHIP_REV_PANTHER_ES1, 1 - 1346 .set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 - 1347 .set CYDEV_CHIP_REV_PSOC4A_ES0, 17 - 1348 .set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 - 1349 .set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 - 1350 .set CYDEV_CONFIGURATION_COMPRESSED, 1 - 1351 .set CYDEV_CONFIGURATION_DMA, 0 - 1352 .set CYDEV_CONFIGURATION_ECC, 0 - 1353 .set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED - 1354 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED - 1355 .set CYDEV_CONFIGURATION_MODE_DMA, 2 - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 213 - - - 1356 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 - 1357 .set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn - 1358 .set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 - 1359 .set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 - 1360 .set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV - 1361 .set CYDEV_DEBUGGING_DPS_Disable, 3 - 1362 .set CYDEV_DEBUGGING_DPS_JTAG_4, 1 - 1363 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0 - 1364 .set CYDEV_DEBUGGING_DPS_SWD, 2 - 1365 .set CYDEV_DEBUGGING_ENABLE, 1 - 1366 .set CYDEV_DEBUGGING_XRES, 0 - 1367 .set CYDEV_DEBUG_ENABLE_MASK, 0x20 - 1368 .set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG - 1369 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24 - 1370 .set CYDEV_ECC_ENABLE, 0 - 1371 .set CYDEV_HEAP_SIZE, 0x0800 - 1372 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 - 1373 .set CYDEV_INTR_RISING, 0x00000000 - 1374 .set CYDEV_PROJ_TYPE, 1 - 1375 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 - 1376 .set CYDEV_PROJ_TYPE_LOADABLE, 2 - 1377 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 - 1378 .set CYDEV_PROJ_TYPE_STANDARD, 0 - 1379 .set CYDEV_PROTECTION_ENABLE, 0 - 1380 .set CYDEV_STACK_SIZE, 0x2000 - 1381 .set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 - 1382 .set CYDEV_USE_BUNDLED_CMSIS, 1 - 1383 .set CYDEV_VARIABLE_VDDA, 0 - 1384 .set CYDEV_VDDA_MV, 5000 - 1385 .set CYDEV_VDDD_MV, 5000 - 1386 .set CYDEV_VDDIO0_MV, 5000 - 1387 .set CYDEV_VDDIO1_MV, 5000 - 1388 .set CYDEV_VDDIO2_MV, 5000 - 1389 .set CYDEV_VDDIO3_MV, 5000 - 1390 .set CYDEV_VIO0, 5 - 1391 .set CYDEV_VIO0_MV, 5000 - 1392 .set CYDEV_VIO1, 5 - 1393 .set CYDEV_VIO1_MV, 5000 - 1394 .set CYDEV_VIO2, 5 - 1395 .set CYDEV_VIO2_MV, 5000 - 1396 .set CYDEV_VIO3, 5 - 1397 .set CYDEV_VIO3_MV, 5000 - 1398 .set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO - 1399 .set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS - 1400 .set DMA_CHANNELS_USED__MASK0, 0x00000000 - 1401 .set CYDEV_BOOTLOADER_ENABLE, 1 - 1402 .endif - 16 - 17 .syntax unified - 18 .text - 19 .thumb - 20 - 21 - 22 /******************************************************************************* - 23 * Function Name: CyDelayCycles - 24 ******************************************************************************** - 25 * - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 214 - - - 26 * Summary: - 27 * Delays for the specified number of cycles. - 28 * - 29 * Parameters: - 30 * uint32 cycles: number of cycles to delay. - 31 * - 32 * Return: - 33 * None - 34 * - 35 *******************************************************************************/ - 36 /* void CyDelayCycles(uint32 cycles) */ - 37 .align 3 /* Align to 8 byte boundary (2^n) */ - 38 .global CyDelayCycles - 39 .func CyDelayCycles, CyDelayCycles - 40 .type CyDelayCycles, %function - 41 .thumb_func - 42 CyDelayCycles: /* cycles bytes */ - 43 /* If ICache is enabled */ - 44 .ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1 - 45 - 46 0000 0230 ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ - 47 0002 8008 LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ - 48 0004 00F00580 BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ - 49 0008 00BF NOP /* 1 2 Loop alignment padding */ - 50 - 51 CyDelayCycles_loop: - 52 000a 0138 SUBS r0, r0, #1 /* 1 2 */ - 53 000c 0046 MOV r0, r0 /* 1 2 Pad loop to power of two cycles */ - 54 000e 7FF4FCAF BNE CyDelayCycles_loop /* 2 2 */ - 55 - 56 CyDelayCycles_done: - 57 0012 7047 BX lr /* 3 2 */ - 58 - 59 .else - 60 - 61 CMP r0, #20 /* 1 2 If delay is short - jump to cycle */ - 62 BLS CyDelayCycles_short /* 1 2 */ - 63 PUSH {r1} /* 2 2 PUSH r1 to stack */ - 64 MOVS r1, #1 /* 1 2 */ - 65 - 66 SUBS r0, r0, #20 /* 1 2 Subtract overhead */ - 67 LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */ - 68 LDRB r1, [r1, #0] /* 2 2 */ - 69 ANDS r1, #0xC0 /* 1 2 */ - 70 - 71 LSRS r1, r1, #6 /* 1 2 */ - 72 PUSH {r2} /* 1 2 PUSH r2 to stack */ - 73 LDR r2, =cy_flash_cycles /* 2 2 */ - 74 LDRB r1, [r2, r1] /* 2 2 */ - 75 - 76 POP {r2} /* 2 2 POP r2 from stack */ - 77 NOP /* 1 2 Alignment padding */ - 78 NOP /* 1 2 Alignment padding */ - 79 NOP /* 1 2 Alignment padding */ - 80 - 81 CyDelayCycles_loop: - 82 SBCS r0, r0, r1 /* 1 2 */ - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 215 - - - 83 BPL CyDelayCycles_loop /* 3 2 */ - 84 NOP /* 1 2 Loop alignment padding */ - 85 NOP /* 1 2 Loop alignment padding */ - 86 - 87 POP {r1} /* 2 2 POP r1 from stack */ - 88 CyDelayCycles_done: - 89 BX lr /* 3 2 */ - 90 NOP /* 1 2 Alignment padding */ - 91 NOP /* 1 2 Alignment padding */ - 92 - 93 CyDelayCycles_short: - 94 SBCS r0, r0, #4 /* 1 2 */ - 95 BPL CyDelayCycles_short /* 3 2 */ - 96 BX lr /* 3 2 */ - 97 - 98 cy_flash_cycles: - 99 .byte 0x0B - 100 .byte 0x05 - 101 .byte 0x07 - 102 .byte 0x09 - 103 .endif - 104 - 105 .endfunc - 106 - 107 - 108 /******************************************************************************* - 109 * Function Name: CyEnterCriticalSection - 110 ******************************************************************************** - 111 * - 112 * Summary: - 113 * CyEnterCriticalSection disables interrupts and returns a value indicating - 114 * whether interrupts were previously enabled (the actual value depends on - 115 * whether the device is PSoC 3 or PSoC 5). - 116 * - 117 * Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit - 118 * with interrupts still enabled. The test and set of the interrupt bits is not - 119 * atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid - 120 * corrupting processor state, it must be the policy that all interrupt routines - 121 * restore the interrupt enable bits as they were found on entry. - 122 * - 123 * Parameters: - 124 * None - 125 * - 126 * Return: - 127 * uint8 - 128 * Returns 0 if interrupts were previously enabled or 1 if interrupts - 129 * were previously disabled. - 130 * - 131 *******************************************************************************/ - 132 /* uint8 CyEnterCriticalSection(void) */ - 133 .global CyEnterCriticalSection - 134 .func CyEnterCriticalSection, CyEnterCriticalSection - 135 .type CyEnterCriticalSection, %function - 136 .thumb_func - 137 CyEnterCriticalSection: - 138 0014 EFF31080 MRS r0, PRIMASK /* Save and return interrupt state */ - 139 0018 72B6 CPSID I /* Disable interrupts */ - ARM GAS .\Generated_Source\PSoC5\CyBootAsmGnu.s page 216 - - - 140 001a 7047 BX lr - 141 .endfunc - 142 - 143 - 144 /******************************************************************************* - 145 * Function Name: CyExitCriticalSection - 146 ******************************************************************************** - 147 * - 148 * Summary: - 149 * CyExitCriticalSection re-enables interrupts if they were enabled before - 150 * CyEnterCriticalSection was called. The argument should be the value returned - 151 * from CyEnterCriticalSection. - 152 * - 153 * Parameters: - 154 * uint8 savedIntrStatus: - 155 * Saved interrupt status returned by the CyEnterCriticalSection function. - 156 * - 157 * Return: - 158 * None - 159 * - 160 *******************************************************************************/ - 161 /* void CyExitCriticalSection(uint8 savedIntrStatus) */ - 162 .global CyExitCriticalSection - 163 .func CyExitCriticalSection, CyExitCriticalSection - 164 .type CyExitCriticalSection, %function - 165 .thumb_func - 166 CyExitCriticalSection: - 167 001c 80F31088 MSR PRIMASK, r0 /* Restore interrupt state */ - 168 0020 7047 BX lr - 169 .endfunc - 170 - 171 0022 00BFAFF3 .end - 171 0080 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyBootAsmGnu.o deleted file mode 100755 index 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a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CyDmac.lst +++ /dev/null @@ -1,6089 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "CyDmac.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.CyDmacConfigure,"ax",%progbits - 19 .align 1 - 20 .global CyDmacConfigure - 21 .thumb - 22 .thumb_func - 23 .type CyDmacConfigure, %function - 24 CyDmacConfigure: - 25 .LFB0: - 26 .file 1 ".\\Generated_Source\\PSoC5\\CyDmac.c" - 1:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/CyDmac.c **** * File Name: CyDmac.c - 3:.\Generated_Source\PSoC5/CyDmac.c **** * Version 4.0 - 4:.\Generated_Source\PSoC5/CyDmac.c **** * - 5:.\Generated_Source\PSoC5/CyDmac.c **** * Description: - 6:.\Generated_Source\PSoC5/CyDmac.c **** * Provides an API for the DMAC component. The API includes functions for the - 7:.\Generated_Source\PSoC5/CyDmac.c **** * DMA controller, DMA channels and Transfer Descriptors. - 8:.\Generated_Source\PSoC5/CyDmac.c **** * - 9:.\Generated_Source\PSoC5/CyDmac.c **** * This API is the library version not the auto generated code that gets - 10:.\Generated_Source\PSoC5/CyDmac.c **** * generated when the user places a DMA component on the schematic. - 11:.\Generated_Source\PSoC5/CyDmac.c **** * - 12:.\Generated_Source\PSoC5/CyDmac.c **** * The auto generated code would use the APi's in this module. - 13:.\Generated_Source\PSoC5/CyDmac.c **** * - 14:.\Generated_Source\PSoC5/CyDmac.c **** * Note: - 15:.\Generated_Source\PSoC5/CyDmac.c **** * This code is endian agnostic. - 16:.\Generated_Source\PSoC5/CyDmac.c **** * - 17:.\Generated_Source\PSoC5/CyDmac.c **** * The Transfer Descriptor memory can be used as regular memory if the TD's are - 18:.\Generated_Source\PSoC5/CyDmac.c **** * not being used. - 19:.\Generated_Source\PSoC5/CyDmac.c **** * - 20:.\Generated_Source\PSoC5/CyDmac.c **** * This code uses the first byte of each TD to manage the free list of TD's. - 21:.\Generated_Source\PSoC5/CyDmac.c **** * The user can over write this once the TD is allocated. - 22:.\Generated_Source\PSoC5/CyDmac.c **** * - 23:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 24:.\Generated_Source\PSoC5/CyDmac.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 25:.\Generated_Source\PSoC5/CyDmac.c **** * You may use this file only in accordance with the license, terms, conditions, - 26:.\Generated_Source\PSoC5/CyDmac.c **** * disclaimers, and limitations in the end user license agreement accompanying - 27:.\Generated_Source\PSoC5/CyDmac.c **** * the software package with which this file was provided. - 28:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 29:.\Generated_Source\PSoC5/CyDmac.c **** - 30:.\Generated_Source\PSoC5/CyDmac.c **** #include "CyDmac.h" - 31:.\Generated_Source\PSoC5/CyDmac.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 2 - - - 32:.\Generated_Source\PSoC5/CyDmac.c **** - 33:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 34:.\Generated_Source\PSoC5/CyDmac.c **** * The following variables are initialized from CyDmacConfigure() function that - 35:.\Generated_Source\PSoC5/CyDmac.c **** * is executed from initialize_psoc() at the early initialization stage. - 36:.\Generated_Source\PSoC5/CyDmac.c **** * In case of IAR EW IDE, initialize_psoc() is executed before the data sections - 37:.\Generated_Source\PSoC5/CyDmac.c **** * are initialized. To avoid zeroing, these variables should be initialized - 38:.\Generated_Source\PSoC5/CyDmac.c **** * properly during segments initialization as well. - 39:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 40:.\Generated_Source\PSoC5/CyDmac.c **** static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free eleme - 41:.\Generated_Source\PSoC5/CyDmac.c **** static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available - 42:.\Generated_Source\PSoC5/CyDmac.c **** static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel owne - 43:.\Generated_Source\PSoC5/CyDmac.c **** - 44:.\Generated_Source\PSoC5/CyDmac.c **** - 45:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 46:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmacConfigure - 47:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 48:.\Generated_Source\PSoC5/CyDmac.c **** * - 49:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 50:.\Generated_Source\PSoC5/CyDmac.c **** * Creates a linked list of all the TDs to be allocated. This function is called - 51:.\Generated_Source\PSoC5/CyDmac.c **** * by the startup code; you do not normally need to call it. You could call this - 52:.\Generated_Source\PSoC5/CyDmac.c **** * function if all of the DMA channels are inactive. - 53:.\Generated_Source\PSoC5/CyDmac.c **** * - 54:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 55:.\Generated_Source\PSoC5/CyDmac.c **** * None - 56:.\Generated_Source\PSoC5/CyDmac.c **** * - 57:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 58:.\Generated_Source\PSoC5/CyDmac.c **** * None - 59:.\Generated_Source\PSoC5/CyDmac.c **** * - 60:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 61:.\Generated_Source\PSoC5/CyDmac.c **** void CyDmacConfigure(void) - 62:.\Generated_Source\PSoC5/CyDmac.c **** { - 27 .loc 1 62 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 63:.\Generated_Source\PSoC5/CyDmac.c **** uint8 dmaIndex; - 64:.\Generated_Source\PSoC5/CyDmac.c **** - 65:.\Generated_Source\PSoC5/CyDmac.c **** /* Set TD list variables. */ - 66:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); - 32 .loc 1 66 0 - 33 0000 084B ldr r3, .L5 - 34 0002 7F22 movs r2, #127 - 67:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; - 35 .loc 1 67 0 - 36 0004 8020 movs r0, #128 - 37 0006 0849 ldr r1, .L5+4 - 66:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); - 38 .loc 1 66 0 - 39 0008 1A70 strb r2, [r3, #0] - 40 .loc 1 67 0 - 41 000a 5870 strb r0, [r3, #1] - 42 .LVL0: - 43 000c 7E22 movs r2, #126 - 44 .LVL1: - 45 .L2: - 46 000e 531E subs r3, r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 3 - - - 68:.\Generated_Source\PSoC5/CyDmac.c **** - 69:.\Generated_Source\PSoC5/CyDmac.c **** /* Make TD free list. */ - 70:.\Generated_Source\PSoC5/CyDmac.c **** for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--) - 71:.\Generated_Source\PSoC5/CyDmac.c **** { - 72:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u); - 47 .loc 1 72 0 discriminator 2 - 48 0010 01F80829 strb r2, [r1], #-8 - 49 0014 DAB2 uxtb r2, r3 - 70:.\Generated_Source\PSoC5/CyDmac.c **** for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--) - 50 .loc 1 70 0 discriminator 2 - 51 0016 FF2A cmp r2, #255 - 52 0018 F9D1 bne .L2 - 73:.\Generated_Source\PSoC5/CyDmac.c **** } - 74:.\Generated_Source\PSoC5/CyDmac.c **** - 75:.\Generated_Source\PSoC5/CyDmac.c **** /* Make the last one point to zero. */ - 76:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u; - 53 .loc 1 76 0 - 54 001a 0449 ldr r1, .L5+8 - 55 001c 0020 movs r0, #0 - 56 001e 0870 strb r0, [r1, #0] - 57 0020 7047 bx lr - 58 .L6: - 59 0022 00BF .align 2 - 60 .L5: - 61 0024 00000000 .word .LANCHOR0 - 62 0028 F87B0040 .word 1073773560 - 63 002c 00780040 .word 1073772544 - 64 .cfi_endproc - 65 .LFE0: - 66 .size CyDmacConfigure, .-CyDmacConfigure - 67 .section .text.CyDmacError,"ax",%progbits - 68 .align 1 - 69 .global CyDmacError - 70 .thumb - 71 .thumb_func - 72 .type CyDmacError, %function - 73 CyDmacError: - 74 .LFB1: - 77:.\Generated_Source\PSoC5/CyDmac.c **** } - 78:.\Generated_Source\PSoC5/CyDmac.c **** - 79:.\Generated_Source\PSoC5/CyDmac.c **** - 80:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 81:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmacError - 82:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 83:.\Generated_Source\PSoC5/CyDmac.c **** * - 84:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 85:.\Generated_Source\PSoC5/CyDmac.c **** * Returns errors of the last failed DMA transaction. - 86:.\Generated_Source\PSoC5/CyDmac.c **** * - 87:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 88:.\Generated_Source\PSoC5/CyDmac.c **** * None - 89:.\Generated_Source\PSoC5/CyDmac.c **** * - 90:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 91:.\Generated_Source\PSoC5/CyDmac.c **** * Errors of the last failed DMA transaction. - 92:.\Generated_Source\PSoC5/CyDmac.c **** * - 93:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_PERIPH_ERR: - 94:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when a peripheral responds to a bus transaction with an error - 95:.\Generated_Source\PSoC5/CyDmac.c **** * response. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 4 - - - 96:.\Generated_Source\PSoC5/CyDmac.c **** * - 97:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_UNPOP_ACC: - 98:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when an access is attempted to an invalid address. - 99:.\Generated_Source\PSoC5/CyDmac.c **** * - 100:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_BUS_TIMEOUT: - 101:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values - 102:.\Generated_Source\PSoC5/CyDmac.c **** * are determined by the BUS_TIMEOUT field in the PHUBCFG register. - 103:.\Generated_Source\PSoC5/CyDmac.c **** * - 104:.\Generated_Source\PSoC5/CyDmac.c **** * Theory: - 105:.\Generated_Source\PSoC5/CyDmac.c **** * Once an error occurs the error bits are sticky and are only cleared by a - 106:.\Generated_Source\PSoC5/CyDmac.c **** * write 1 to the error register. - 107:.\Generated_Source\PSoC5/CyDmac.c **** * - 108:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 109:.\Generated_Source\PSoC5/CyDmac.c **** uint8 CyDmacError(void) - 110:.\Generated_Source\PSoC5/CyDmac.c **** { - 75 .loc 1 110 0 - 76 .cfi_startproc - 77 @ args = 0, pretend = 0, frame = 0 - 78 @ frame_needed = 0, uses_anonymous_args = 0 - 79 @ link register save eliminated. - 111:.\Generated_Source\PSoC5/CyDmac.c **** return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR)); - 80 .loc 1 111 0 - 81 0000 024B ldr r3, .L8 - 82 0002 1868 ldr r0, [r3, #0] - 112:.\Generated_Source\PSoC5/CyDmac.c **** } - 83 .loc 1 112 0 - 84 0004 00F00F00 and r0, r0, #15 - 85 0008 7047 bx lr - 86 .L9: - 87 000a 00BF .align 2 - 88 .L8: - 89 000c 04700040 .word 1073770500 - 90 .cfi_endproc - 91 .LFE1: - 92 .size CyDmacError, .-CyDmacError - 93 .section .text.CyDmacClearError,"ax",%progbits - 94 .align 1 - 95 .global CyDmacClearError - 96 .thumb - 97 .thumb_func - 98 .type CyDmacClearError, %function - 99 CyDmacClearError: - 100 .LFB2: - 113:.\Generated_Source\PSoC5/CyDmac.c **** - 114:.\Generated_Source\PSoC5/CyDmac.c **** - 115:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 116:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmacClearError - 117:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 118:.\Generated_Source\PSoC5/CyDmac.c **** * - 119:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 120:.\Generated_Source\PSoC5/CyDmac.c **** * Clears the error bits in the error register of the DMAC. - 121:.\Generated_Source\PSoC5/CyDmac.c **** * - 122:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 123:.\Generated_Source\PSoC5/CyDmac.c **** * error: - 124:.\Generated_Source\PSoC5/CyDmac.c **** * Clears the error bits in the DMAC error register. - 125:.\Generated_Source\PSoC5/CyDmac.c **** * - 126:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_PERIPH_ERR: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 5 - - - 127:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when a peripheral responds to a bus transaction with an error - 128:.\Generated_Source\PSoC5/CyDmac.c **** * response. - 129:.\Generated_Source\PSoC5/CyDmac.c **** * - 130:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_UNPOP_ACC: - 131:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when an access is attempted to an invalid address. - 132:.\Generated_Source\PSoC5/CyDmac.c **** * - 133:.\Generated_Source\PSoC5/CyDmac.c **** * DMAC_BUS_TIMEOUT: - 134:.\Generated_Source\PSoC5/CyDmac.c **** * Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values - 135:.\Generated_Source\PSoC5/CyDmac.c **** * are determined by the BUS_TIMEOUT field in the PHUBCFG register. - 136:.\Generated_Source\PSoC5/CyDmac.c **** * - 137:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 138:.\Generated_Source\PSoC5/CyDmac.c **** * None - 139:.\Generated_Source\PSoC5/CyDmac.c **** * - 140:.\Generated_Source\PSoC5/CyDmac.c **** * Theory: - 141:.\Generated_Source\PSoC5/CyDmac.c **** * Once an error occurs the error bits are sticky and are only cleared by a - 142:.\Generated_Source\PSoC5/CyDmac.c **** * write 1 to the error register. - 143:.\Generated_Source\PSoC5/CyDmac.c **** * - 144:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 145:.\Generated_Source\PSoC5/CyDmac.c **** void CyDmacClearError(uint8 error) - 146:.\Generated_Source\PSoC5/CyDmac.c **** { - 101 .loc 1 146 0 - 102 .cfi_startproc - 103 @ args = 0, pretend = 0, frame = 0 - 104 @ frame_needed = 0, uses_anonymous_args = 0 - 105 @ link register save eliminated. - 106 .LVL2: - 147:.\Generated_Source\PSoC5/CyDmac.c **** *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error)); - 107 .loc 1 147 0 - 108 0000 024B ldr r3, .L11 - 109 0002 00F00F00 and r0, r0, #15 - 110 .LVL3: - 111 0006 1860 str r0, [r3, #0] - 112 0008 7047 bx lr - 113 .L12: - 114 000a 00BF .align 2 - 115 .L11: - 116 000c 04700040 .word 1073770500 - 117 .cfi_endproc - 118 .LFE2: - 119 .size CyDmacClearError, .-CyDmacClearError - 120 .section .text.CyDmacErrorAddress,"ax",%progbits - 121 .align 1 - 122 .global CyDmacErrorAddress - 123 .thumb - 124 .thumb_func - 125 .type CyDmacErrorAddress, %function - 126 CyDmacErrorAddress: - 127 .LFB3: - 148:.\Generated_Source\PSoC5/CyDmac.c **** } - 149:.\Generated_Source\PSoC5/CyDmac.c **** - 150:.\Generated_Source\PSoC5/CyDmac.c **** - 151:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 152:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmacErrorAddress - 153:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 154:.\Generated_Source\PSoC5/CyDmac.c **** * - 155:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 156:.\Generated_Source\PSoC5/CyDmac.c **** * When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 6 - - - 157:.\Generated_Source\PSoC5/CyDmac.c **** * address of the error is written to the error address register and can be read - 158:.\Generated_Source\PSoC5/CyDmac.c **** * with this function. - 159:.\Generated_Source\PSoC5/CyDmac.c **** * - 160:.\Generated_Source\PSoC5/CyDmac.c **** * If there are multiple errors, only the address of the first is saved. - 161:.\Generated_Source\PSoC5/CyDmac.c **** * - 162:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 163:.\Generated_Source\PSoC5/CyDmac.c **** * None - 164:.\Generated_Source\PSoC5/CyDmac.c **** * - 165:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 166:.\Generated_Source\PSoC5/CyDmac.c **** * The address that caused the error. - 167:.\Generated_Source\PSoC5/CyDmac.c **** * - 168:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 169:.\Generated_Source\PSoC5/CyDmac.c **** uint32 CyDmacErrorAddress(void) - 170:.\Generated_Source\PSoC5/CyDmac.c **** { - 128 .loc 1 170 0 - 129 .cfi_startproc - 130 @ args = 0, pretend = 0, frame = 0 - 131 @ frame_needed = 0, uses_anonymous_args = 0 - 132 @ link register save eliminated. - 171:.\Generated_Source\PSoC5/CyDmac.c **** return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR)); - 133 .loc 1 171 0 - 134 0000 014B ldr r3, .L14 - 135 0002 1868 ldr r0, [r3, #0] - 172:.\Generated_Source\PSoC5/CyDmac.c **** } - 136 .loc 1 172 0 - 137 0004 7047 bx lr - 138 .L15: - 139 0006 00BF .align 2 - 140 .L14: - 141 0008 08700040 .word 1073770504 - 142 .cfi_endproc - 143 .LFE3: - 144 .size CyDmacErrorAddress, .-CyDmacErrorAddress - 145 .section .text.CyDmaChAlloc,"ax",%progbits - 146 .align 1 - 147 .global CyDmaChAlloc - 148 .thumb - 149 .thumb_func - 150 .type CyDmaChAlloc, %function - 151 CyDmaChAlloc: - 152 .LFB4: - 173:.\Generated_Source\PSoC5/CyDmac.c **** - 174:.\Generated_Source\PSoC5/CyDmac.c **** - 175:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 176:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChAlloc - 177:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 178:.\Generated_Source\PSoC5/CyDmac.c **** * - 179:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 180:.\Generated_Source\PSoC5/CyDmac.c **** * Allocates a channel from the DMAC to be used in all functions that require a - 181:.\Generated_Source\PSoC5/CyDmac.c **** * channel handle. - 182:.\Generated_Source\PSoC5/CyDmac.c **** * - 183:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 184:.\Generated_Source\PSoC5/CyDmac.c **** * None - 185:.\Generated_Source\PSoC5/CyDmac.c **** * - 186:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 187:.\Generated_Source\PSoC5/CyDmac.c **** * The allocated channel number. Zero is a valid channel number. - 188:.\Generated_Source\PSoC5/CyDmac.c **** * DMA_INVALID_CHANNEL is returned if there are no channels available. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 7 - - - 189:.\Generated_Source\PSoC5/CyDmac.c **** * - 190:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 191:.\Generated_Source\PSoC5/CyDmac.c **** uint8 CyDmaChAlloc(void) - 192:.\Generated_Source\PSoC5/CyDmac.c **** { - 153 .loc 1 192 0 - 154 .cfi_startproc - 155 @ args = 0, pretend = 0, frame = 0 - 156 @ frame_needed = 0, uses_anonymous_args = 0 - 157 .LVL4: - 158 0000 10B5 push {r4, lr} - 159 .LCFI0: - 160 .cfi_def_cfa_offset 8 - 161 .cfi_offset 4, -8 - 162 .cfi_offset 14, -4 - 193:.\Generated_Source\PSoC5/CyDmac.c **** uint8 interruptState; - 194:.\Generated_Source\PSoC5/CyDmac.c **** uint8 dmaIndex; - 195:.\Generated_Source\PSoC5/CyDmac.c **** uint32 channel = 1u; - 196:.\Generated_Source\PSoC5/CyDmac.c **** - 197:.\Generated_Source\PSoC5/CyDmac.c **** - 198:.\Generated_Source\PSoC5/CyDmac.c **** /* Enter critical section! */ - 199:.\Generated_Source\PSoC5/CyDmac.c **** interruptState = CyEnterCriticalSection(); - 163 .loc 1 199 0 - 164 0002 FFF7FEFF bl CyEnterCriticalSection - 165 .LVL5: - 200:.\Generated_Source\PSoC5/CyDmac.c **** - 201:.\Generated_Source\PSoC5/CyDmac.c **** /* Look for a free channel. */ - 202:.\Generated_Source\PSoC5/CyDmac.c **** for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) - 203:.\Generated_Source\PSoC5/CyDmac.c **** { - 204:.\Generated_Source\PSoC5/CyDmac.c **** if(0uL == (CyDmaChannels & channel)) - 166 .loc 1 204 0 - 167 0006 0A4B ldr r3, .L21 - 195:.\Generated_Source\PSoC5/CyDmac.c **** uint32 channel = 1u; - 168 .loc 1 195 0 - 169 0008 0121 movs r1, #1 - 170 .loc 1 204 0 - 171 000a 1A68 ldr r2, [r3, #0] - 202:.\Generated_Source\PSoC5/CyDmac.c **** for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) - 172 .loc 1 202 0 - 173 000c 0024 movs r4, #0 - 174 .LVL6: - 175 .L19: - 176 .loc 1 204 0 - 177 000e 1142 tst r1, r2 - 178 0010 04D1 bne .L17 - 205:.\Generated_Source\PSoC5/CyDmac.c **** { - 206:.\Generated_Source\PSoC5/CyDmac.c **** /* Mark the channel as used. */ - 207:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaChannels |= channel; - 179 .loc 1 207 0 - 180 0012 42EA0103 orr r3, r2, r1 - 181 0016 064A ldr r2, .L21 - 182 0018 1360 str r3, [r2, #0] - 183 001a 05E0 b .L18 - 184 .L17: - 202:.\Generated_Source\PSoC5/CyDmac.c **** for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) - 185 .loc 1 202 0 - 186 001c 0134 adds r4, r4, #1 - 187 001e E4B2 uxtb r4, r4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 8 - - - 208:.\Generated_Source\PSoC5/CyDmac.c **** break; - 209:.\Generated_Source\PSoC5/CyDmac.c **** } - 210:.\Generated_Source\PSoC5/CyDmac.c **** - 211:.\Generated_Source\PSoC5/CyDmac.c **** channel <<= 1u; - 188 .loc 1 211 0 - 189 0020 4900 lsls r1, r1, #1 - 190 .LVL7: - 202:.\Generated_Source\PSoC5/CyDmac.c **** for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) - 191 .loc 1 202 0 - 192 0022 182C cmp r4, #24 - 193 0024 F3D1 bne .L19 - 212:.\Generated_Source\PSoC5/CyDmac.c **** } - 213:.\Generated_Source\PSoC5/CyDmac.c **** - 214:.\Generated_Source\PSoC5/CyDmac.c **** if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS) - 215:.\Generated_Source\PSoC5/CyDmac.c **** { - 216:.\Generated_Source\PSoC5/CyDmac.c **** dmaIndex = CY_DMA_INVALID_CHANNEL; - 194 .loc 1 216 0 - 195 0026 FF24 movs r4, #255 - 196 .LVL8: - 197 .L18: - 217:.\Generated_Source\PSoC5/CyDmac.c **** } - 218:.\Generated_Source\PSoC5/CyDmac.c **** - 219:.\Generated_Source\PSoC5/CyDmac.c **** /* Exit critical section! */ - 220:.\Generated_Source\PSoC5/CyDmac.c **** CyExitCriticalSection(interruptState); - 198 .loc 1 220 0 - 199 0028 FFF7FEFF bl CyExitCriticalSection - 200 .LVL9: - 221:.\Generated_Source\PSoC5/CyDmac.c **** - 222:.\Generated_Source\PSoC5/CyDmac.c **** return(dmaIndex); - 223:.\Generated_Source\PSoC5/CyDmac.c **** } - 201 .loc 1 223 0 - 202 002c 2046 mov r0, r4 - 203 002e 10BD pop {r4, pc} - 204 .L22: - 205 .align 2 - 206 .L21: - 207 0030 00000000 .word .LANCHOR1 - 208 .cfi_endproc - 209 .LFE4: - 210 .size CyDmaChAlloc, .-CyDmaChAlloc - 211 .section .text.CyDmaChFree,"ax",%progbits - 212 .align 1 - 213 .global CyDmaChFree - 214 .thumb - 215 .thumb_func - 216 .type CyDmaChFree, %function - 217 CyDmaChFree: - 218 .LFB5: - 224:.\Generated_Source\PSoC5/CyDmac.c **** - 225:.\Generated_Source\PSoC5/CyDmac.c **** - 226:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 227:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChFree - 228:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 229:.\Generated_Source\PSoC5/CyDmac.c **** * - 230:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 231:.\Generated_Source\PSoC5/CyDmac.c **** * Frees a channel allocated by DmaChAlloc(). - 232:.\Generated_Source\PSoC5/CyDmac.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 9 - - - 233:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 234:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 235:.\Generated_Source\PSoC5/CyDmac.c **** * The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 236:.\Generated_Source\PSoC5/CyDmac.c **** * - 237:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 238:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 239:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 240:.\Generated_Source\PSoC5/CyDmac.c **** * - 241:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 242:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChFree(uint8 chHandle) - 243:.\Generated_Source\PSoC5/CyDmac.c **** { - 219 .loc 1 243 0 - 220 .cfi_startproc - 221 @ args = 0, pretend = 0, frame = 0 - 222 @ frame_needed = 0, uses_anonymous_args = 0 - 223 .LVL10: - 244:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 245:.\Generated_Source\PSoC5/CyDmac.c **** uint8 interruptState; - 246:.\Generated_Source\PSoC5/CyDmac.c **** - 247:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 224 .loc 1 247 0 - 225 0000 1728 cmp r0, #23 - 243:.\Generated_Source\PSoC5/CyDmac.c **** { - 226 .loc 1 243 0 - 227 0002 38B5 push {r3, r4, r5, lr} - 228 .LCFI1: - 229 .cfi_def_cfa_offset 16 - 230 .cfi_offset 3, -16 - 231 .cfi_offset 4, -12 - 232 .cfi_offset 5, -8 - 233 .cfi_offset 14, -4 - 243:.\Generated_Source\PSoC5/CyDmac.c **** { - 234 .loc 1 243 0 - 235 0004 0546 mov r5, r0 - 236 0006 4FF00104 mov r4, #1 - 237 .loc 1 247 0 - 238 000a 0CD8 bhi .L25 - 248:.\Generated_Source\PSoC5/CyDmac.c **** { - 249:.\Generated_Source\PSoC5/CyDmac.c **** /* Enter critical section */ - 250:.\Generated_Source\PSoC5/CyDmac.c **** interruptState = CyEnterCriticalSection(); - 251:.\Generated_Source\PSoC5/CyDmac.c **** - 252:.\Generated_Source\PSoC5/CyDmac.c **** /* Clear the bit mask that keeps track of ownership. */ - 253:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaChannels &= ~(((uint32) 1u) << chHandle); - 239 .loc 1 253 0 - 240 000c 04FA05F4 lsl r4, r4, r5 - 250:.\Generated_Source\PSoC5/CyDmac.c **** interruptState = CyEnterCriticalSection(); - 241 .loc 1 250 0 - 242 0010 FFF7FEFF bl CyEnterCriticalSection - 243 .LVL11: - 244 .loc 1 253 0 - 245 0014 054B ldr r3, .L26 - 246 0016 1A68 ldr r2, [r3, #0] - 247 0018 22EA0402 bic r2, r2, r4 - 248 001c 1A60 str r2, [r3, #0] - 254:.\Generated_Source\PSoC5/CyDmac.c **** - 255:.\Generated_Source\PSoC5/CyDmac.c **** /* Exit critical section */ - 256:.\Generated_Source\PSoC5/CyDmac.c **** CyExitCriticalSection(interruptState); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 10 - - - 249 .loc 1 256 0 - 250 001e FFF7FEFF bl CyExitCriticalSection - 251 .LVL12: - 257:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 252 .loc 1 257 0 - 253 0022 0020 movs r0, #0 - 254 0024 38BD pop {r3, r4, r5, pc} - 255 .LVL13: - 256 .L25: - 244:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 257 .loc 1 244 0 - 258 0026 2046 mov r0, r4 - 259 .LVL14: - 258:.\Generated_Source\PSoC5/CyDmac.c **** } - 259:.\Generated_Source\PSoC5/CyDmac.c **** - 260:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 261:.\Generated_Source\PSoC5/CyDmac.c **** } - 260 .loc 1 261 0 - 261 0028 38BD pop {r3, r4, r5, pc} - 262 .L27: - 263 002a 00BF .align 2 - 264 .L26: - 265 002c 00000000 .word .LANCHOR1 - 266 .cfi_endproc - 267 .LFE5: - 268 .size CyDmaChFree, .-CyDmaChFree - 269 .section .text.CyDmaChEnable,"ax",%progbits - 270 .align 1 - 271 .global CyDmaChEnable - 272 .thumb - 273 .thumb_func - 274 .type CyDmaChEnable, %function - 275 CyDmaChEnable: - 276 .LFB6: - 262:.\Generated_Source\PSoC5/CyDmac.c **** - 263:.\Generated_Source\PSoC5/CyDmac.c **** - 264:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 265:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChEnable - 266:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 267:.\Generated_Source\PSoC5/CyDmac.c **** * - 268:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 269:.\Generated_Source\PSoC5/CyDmac.c **** * Enables the DMA channel. A software or hardware request still must happen - 270:.\Generated_Source\PSoC5/CyDmac.c **** * before the channel is executed. - 271:.\Generated_Source\PSoC5/CyDmac.c **** * - 272:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 273:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 274:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 275:.\Generated_Source\PSoC5/CyDmac.c **** * - 276:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 preserveTds: - 277:.\Generated_Source\PSoC5/CyDmac.c **** * Preserves the original TD state when the TD has completed. This parameter - 278:.\Generated_Source\PSoC5/CyDmac.c **** * applies to all TDs in the channel. - 279:.\Generated_Source\PSoC5/CyDmac.c **** * - 280:.\Generated_Source\PSoC5/CyDmac.c **** * 0 - When a TD is completed, the DMAC leaves the TD configuration values in - 281:.\Generated_Source\PSoC5/CyDmac.c **** * their current state, and does not restore them to their original state. - 282:.\Generated_Source\PSoC5/CyDmac.c **** * - 283:.\Generated_Source\PSoC5/CyDmac.c **** * 1 - When a TD is completed, the DMAC restores the original configuration - 284:.\Generated_Source\PSoC5/CyDmac.c **** * values of the TD. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 11 - - - 285:.\Generated_Source\PSoC5/CyDmac.c **** * - 286:.\Generated_Source\PSoC5/CyDmac.c **** * When preserveTds is set, the TD slot that equals the channel number becomes - 287:.\Generated_Source\PSoC5/CyDmac.c **** * RESERVED and that becomes where the working registers exist. So, for example, - 288:.\Generated_Source\PSoC5/CyDmac.c **** * if you are using CH06 and preserveTds is set, you are not allowed to use TD - 289:.\Generated_Source\PSoC5/CyDmac.c **** * slot 6. That is reclaimed by the DMA engine for its private use. - 290:.\Generated_Source\PSoC5/CyDmac.c **** * - 291:.\Generated_Source\PSoC5/CyDmac.c **** * Note Do not chain back to a completed TD if the preserveTds for the channel - 292:.\Generated_Source\PSoC5/CyDmac.c **** * is set to 0. When a TD has completed preserveTds for the channel set to 0, - 293:.\Generated_Source\PSoC5/CyDmac.c **** * the transfer count will be at 0. If a TD with a transfer count of 0 is - 294:.\Generated_Source\PSoC5/CyDmac.c **** * started, the TD will transfer an indefinite amount of data. - 295:.\Generated_Source\PSoC5/CyDmac.c **** * - 296:.\Generated_Source\PSoC5/CyDmac.c **** * Take extra precautions when using the hardware request (DRQ) option when the - 297:.\Generated_Source\PSoC5/CyDmac.c **** * preserveTds is set to 0, as you might be requesting the wrong data. - 298:.\Generated_Source\PSoC5/CyDmac.c **** * - 299:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 300:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 301:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 302:.\Generated_Source\PSoC5/CyDmac.c **** * - 303:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 304:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) - 305:.\Generated_Source\PSoC5/CyDmac.c **** { - 277 .loc 1 305 0 - 278 .cfi_startproc - 279 @ args = 0, pretend = 0, frame = 0 - 280 @ frame_needed = 0, uses_anonymous_args = 0 - 281 @ link register save eliminated. - 282 .LVL15: - 306:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 307:.\Generated_Source\PSoC5/CyDmac.c **** - 308:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 283 .loc 1 308 0 - 284 0000 1728 cmp r0, #23 - 285 0002 12D8 bhi .L32 - 286 0004 0201 lsls r2, r0, #4 - 287 0006 0A4B ldr r3, .L34 - 309:.\Generated_Source\PSoC5/CyDmac.c **** { - 310:.\Generated_Source\PSoC5/CyDmac.c **** if (0u != preserveTds) - 288 .loc 1 310 0 - 289 0008 19B1 cbz r1, .L30 - 311:.\Generated_Source\PSoC5/CyDmac.c **** { - 312:.\Generated_Source\PSoC5/CyDmac.c **** /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to - 313:.\Generated_Source\PSoC5/CyDmac.c **** * preserve the original TD chain - 314:.\Generated_Source\PSoC5/CyDmac.c **** */ - 315:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP; - 290 .loc 1 315 0 - 291 000a D15C ldrb r1, [r2, r3] @ zero_extendqisi2 - 292 .LVL16: - 293 000c 41F02001 orr r1, r1, #32 - 294 0010 02E0 b .L33 - 295 .LVL17: - 296 .L30: - 316:.\Generated_Source\PSoC5/CyDmac.c **** } - 317:.\Generated_Source\PSoC5/CyDmac.c **** else - 318:.\Generated_Source\PSoC5/CyDmac.c **** { - 319:.\Generated_Source\PSoC5/CyDmac.c **** /* Store the intermediate and final TD states on top of the original TD chain */ - 320:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP); - 297 .loc 1 320 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 12 - - - 298 0012 D15C ldrb r1, [r2, r3] @ zero_extendqisi2 - 299 .LVL18: - 300 0014 01F0DF01 and r1, r1, #223 - 301 .L33: - 302 0018 D154 strb r1, [r2, r3] - 321:.\Generated_Source\PSoC5/CyDmac.c **** } - 322:.\Generated_Source\PSoC5/CyDmac.c **** - 323:.\Generated_Source\PSoC5/CyDmac.c **** /* Enable channel */ - 324:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN; - 303 .loc 1 324 0 - 304 001a 054B ldr r3, .L34 - 305 001c 0001 lsls r0, r0, #4 - 306 .LVL19: - 307 001e C25C ldrb r2, [r0, r3] @ zero_extendqisi2 - 308 0020 42F00101 orr r1, r2, #1 - 309 0024 C154 strb r1, [r0, r3] - 310 .LVL20: - 325:.\Generated_Source\PSoC5/CyDmac.c **** - 326:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 311 .loc 1 326 0 - 312 0026 0020 movs r0, #0 - 313 0028 7047 bx lr - 314 .LVL21: - 315 .L32: - 306:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 316 .loc 1 306 0 - 317 002a 0120 movs r0, #1 - 318 .LVL22: - 327:.\Generated_Source\PSoC5/CyDmac.c **** } - 328:.\Generated_Source\PSoC5/CyDmac.c **** - 329:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 330:.\Generated_Source\PSoC5/CyDmac.c **** } - 319 .loc 1 330 0 - 320 002c 7047 bx lr - 321 .L35: - 322 002e 00BF .align 2 - 323 .L34: - 324 0030 10700040 .word 1073770512 - 325 .cfi_endproc - 326 .LFE6: - 327 .size CyDmaChEnable, .-CyDmaChEnable - 328 .section .text.CyDmaChDisable,"ax",%progbits - 329 .align 1 - 330 .global CyDmaChDisable - 331 .thumb - 332 .thumb_func - 333 .type CyDmaChDisable, %function - 334 CyDmaChDisable: - 335 .LFB7: - 331:.\Generated_Source\PSoC5/CyDmac.c **** - 332:.\Generated_Source\PSoC5/CyDmac.c **** - 333:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 334:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChDisable - 335:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 336:.\Generated_Source\PSoC5/CyDmac.c **** * - 337:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 338:.\Generated_Source\PSoC5/CyDmac.c **** * Disables the DMA channel. Once this function is called, CyDmaChStatus() may - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 13 - - - 339:.\Generated_Source\PSoC5/CyDmac.c **** * be called to determine when the channel is disabled and which TDs were being - 340:.\Generated_Source\PSoC5/CyDmac.c **** * executed. - 341:.\Generated_Source\PSoC5/CyDmac.c **** * - 342:.\Generated_Source\PSoC5/CyDmac.c **** * If it is currently executing it will allow the current burst to finish - 343:.\Generated_Source\PSoC5/CyDmac.c **** * naturally. - 344:.\Generated_Source\PSoC5/CyDmac.c **** * - 345:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 346:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 347:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 348:.\Generated_Source\PSoC5/CyDmac.c **** * - 349:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 350:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 351:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 352:.\Generated_Source\PSoC5/CyDmac.c **** * - 353:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 354:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChDisable(uint8 chHandle) - 355:.\Generated_Source\PSoC5/CyDmac.c **** { - 336 .loc 1 355 0 - 337 .cfi_startproc - 338 @ args = 0, pretend = 0, frame = 0 - 339 @ frame_needed = 0, uses_anonymous_args = 0 - 340 @ link register save eliminated. - 341 .LVL23: - 356:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 357:.\Generated_Source\PSoC5/CyDmac.c **** - 358:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 342 .loc 1 358 0 - 343 0000 1728 cmp r0, #23 - 344 0002 0BD8 bhi .L38 - 359:.\Generated_Source\PSoC5/CyDmac.c **** { - 360:.\Generated_Source\PSoC5/CyDmac.c **** /*********************************************************************** - 361:.\Generated_Source\PSoC5/CyDmac.c **** * Should not change configuration information of a DMA channel when it - 362:.\Generated_Source\PSoC5/CyDmac.c **** * is active (or vulnerable to becoming active). - 363:.\Generated_Source\PSoC5/CyDmac.c **** ***********************************************************************/ - 364:.\Generated_Source\PSoC5/CyDmac.c **** - 365:.\Generated_Source\PSoC5/CyDmac.c **** /* Disable channel */ - 366:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN)); - 345 .loc 1 366 0 - 346 0004 064B ldr r3, .L39 - 347 0006 0001 lsls r0, r0, #4 - 348 .LVL24: - 349 0008 C25C ldrb r2, [r0, r3] @ zero_extendqisi2 - 350 000a 02F0FE01 and r1, r2, #254 - 351 000e C154 strb r1, [r0, r3] - 367:.\Generated_Source\PSoC5/CyDmac.c **** - 368:.\Generated_Source\PSoC5/CyDmac.c **** /* Store the intermediate and final TD states on top of the original TD chain */ - 369:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP)); - 352 .loc 1 369 0 - 353 0010 C25C ldrb r2, [r0, r3] @ zero_extendqisi2 - 354 0012 02F0DF01 and r1, r2, #223 - 355 0016 C154 strb r1, [r0, r3] - 356 .LVL25: - 370:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 357 .loc 1 370 0 - 358 0018 0020 movs r0, #0 - 359 001a 7047 bx lr - 360 .LVL26: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 14 - - - 361 .L38: - 356:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 362 .loc 1 356 0 - 363 001c 0120 movs r0, #1 - 364 .LVL27: - 371:.\Generated_Source\PSoC5/CyDmac.c **** } - 372:.\Generated_Source\PSoC5/CyDmac.c **** - 373:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 374:.\Generated_Source\PSoC5/CyDmac.c **** } - 365 .loc 1 374 0 - 366 001e 7047 bx lr - 367 .L40: - 368 .align 2 - 369 .L39: - 370 0020 10700040 .word 1073770512 - 371 .cfi_endproc - 372 .LFE7: - 373 .size CyDmaChDisable, .-CyDmaChDisable - 374 .section .text.CyDmaClearPendingDrq,"ax",%progbits - 375 .align 1 - 376 .global CyDmaClearPendingDrq - 377 .thumb - 378 .thumb_func - 379 .type CyDmaClearPendingDrq, %function - 380 CyDmaClearPendingDrq: - 381 .LFB8: - 375:.\Generated_Source\PSoC5/CyDmac.c **** - 376:.\Generated_Source\PSoC5/CyDmac.c **** - 377:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 378:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaClearPendingDrq - 379:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 380:.\Generated_Source\PSoC5/CyDmac.c **** * - 381:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 382:.\Generated_Source\PSoC5/CyDmac.c **** * Clears pending DMA data request. - 383:.\Generated_Source\PSoC5/CyDmac.c **** * - 384:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 385:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 386:.\Generated_Source\PSoC5/CyDmac.c **** * Handle to the dma channel. - 387:.\Generated_Source\PSoC5/CyDmac.c **** * - 388:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 389:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 390:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 391:.\Generated_Source\PSoC5/CyDmac.c **** * - 392:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 393:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaClearPendingDrq(uint8 chHandle) - 394:.\Generated_Source\PSoC5/CyDmac.c **** { - 382 .loc 1 394 0 - 383 .cfi_startproc - 384 @ args = 0, pretend = 0, frame = 0 - 385 @ frame_needed = 0, uses_anonymous_args = 0 - 386 @ link register save eliminated. - 387 .LVL28: - 395:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 396:.\Generated_Source\PSoC5/CyDmac.c **** - 397:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 388 .loc 1 397 0 - 389 0000 1728 cmp r0, #23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 15 - - - 390 0002 0CD8 bhi .L43 - 398:.\Generated_Source\PSoC5/CyDmac.c **** { - 399:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN; - 391 .loc 1 399 0 - 392 0004 074A ldr r2, .L44 - 393 0006 0001 lsls r0, r0, #4 - 394 .LVL29: - 395 0008 8318 adds r3, r0, r2 - 396 000a 1979 ldrb r1, [r3, #4] @ zero_extendqisi2 - 397 000c 41F00401 orr r1, r1, #4 - 398 0010 1971 strb r1, [r3, #4] - 400:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u; - 399 .loc 1 400 0 - 400 0012 835C ldrb r3, [r0, r2] @ zero_extendqisi2 - 401 0014 43F00101 orr r1, r3, #1 - 402 0018 8154 strb r1, [r0, r2] - 403 .LVL30: - 401:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 404 .loc 1 401 0 - 405 001a 0020 movs r0, #0 - 406 001c 7047 bx lr - 407 .LVL31: - 408 .L43: - 395:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 409 .loc 1 395 0 - 410 001e 0120 movs r0, #1 - 411 .LVL32: - 402:.\Generated_Source\PSoC5/CyDmac.c **** } - 403:.\Generated_Source\PSoC5/CyDmac.c **** - 404:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 405:.\Generated_Source\PSoC5/CyDmac.c **** } - 412 .loc 1 405 0 - 413 0020 7047 bx lr - 414 .L45: - 415 0022 00BF .align 2 - 416 .L44: - 417 0024 10700040 .word 1073770512 - 418 .cfi_endproc - 419 .LFE8: - 420 .size CyDmaClearPendingDrq, .-CyDmaClearPendingDrq - 421 .section .text.CyDmaChPriority,"ax",%progbits - 422 .align 1 - 423 .global CyDmaChPriority - 424 .thumb - 425 .thumb_func - 426 .type CyDmaChPriority, %function - 427 CyDmaChPriority: - 428 .LFB9: - 406:.\Generated_Source\PSoC5/CyDmac.c **** - 407:.\Generated_Source\PSoC5/CyDmac.c **** - 408:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 409:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChPriority - 410:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 411:.\Generated_Source\PSoC5/CyDmac.c **** * - 412:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 413:.\Generated_Source\PSoC5/CyDmac.c **** * Sets the priority of a DMA channel. You can use this function when you want - 414:.\Generated_Source\PSoC5/CyDmac.c **** * to change the priority at run time. If the priority remains the same for a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 16 - - - 415:.\Generated_Source\PSoC5/CyDmac.c **** * DMA channel, then you can configure the priority in the .cydwr file. - 416:.\Generated_Source\PSoC5/CyDmac.c **** * - 417:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 418:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 419:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 420:.\Generated_Source\PSoC5/CyDmac.c **** * - 421:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 priority: - 422:.\Generated_Source\PSoC5/CyDmac.c **** * Priority to set the channel to, 0 - 7. - 423:.\Generated_Source\PSoC5/CyDmac.c **** * - 424:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 425:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 426:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 427:.\Generated_Source\PSoC5/CyDmac.c **** * - 428:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 429:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) - 430:.\Generated_Source\PSoC5/CyDmac.c **** { - 429 .loc 1 430 0 - 430 .cfi_startproc - 431 @ args = 0, pretend = 0, frame = 0 - 432 @ frame_needed = 0, uses_anonymous_args = 0 - 433 @ link register save eliminated. - 434 .LVL33: - 431:.\Generated_Source\PSoC5/CyDmac.c **** uint8 value; - 432:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 433:.\Generated_Source\PSoC5/CyDmac.c **** - 434:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 435 .loc 1 434 0 - 436 0000 1728 cmp r0, #23 - 437 0002 0BD8 bhi .L48 - 435:.\Generated_Source\PSoC5/CyDmac.c **** { - 436:.\Generated_Source\PSoC5/CyDmac.c **** value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); - 438 .loc 1 436 0 - 439 0004 064B ldr r3, .L49 - 440 0006 0001 lsls r0, r0, #4 - 441 .LVL34: - 442 0008 C25C ldrb r2, [r0, r3] @ zero_extendqisi2 - 443 .LVL35: - 437:.\Generated_Source\PSoC5/CyDmac.c **** - 438:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u - 444 .loc 1 438 0 - 445 000a 01F00701 and r1, r1, #7 - 446 .LVL36: - 436:.\Generated_Source\PSoC5/CyDmac.c **** value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); - 447 .loc 1 436 0 - 448 000e 02F0F102 and r2, r2, #241 - 449 .LVL37: - 450 .loc 1 438 0 - 451 0012 42EA4101 orr r1, r2, r1, lsl #1 - 452 0016 C154 strb r1, [r0, r3] - 453 .LVL38: - 439:.\Generated_Source\PSoC5/CyDmac.c **** - 440:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 454 .loc 1 440 0 - 455 0018 0020 movs r0, #0 - 456 001a 7047 bx lr - 457 .LVL39: - 458 .L48: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 17 - - - 432:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 459 .loc 1 432 0 - 460 001c 0120 movs r0, #1 - 461 .LVL40: - 441:.\Generated_Source\PSoC5/CyDmac.c **** } - 442:.\Generated_Source\PSoC5/CyDmac.c **** - 443:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 444:.\Generated_Source\PSoC5/CyDmac.c **** } - 462 .loc 1 444 0 - 463 001e 7047 bx lr - 464 .L50: - 465 .align 2 - 466 .L49: - 467 0020 10700040 .word 1073770512 - 468 .cfi_endproc - 469 .LFE9: - 470 .size CyDmaChPriority, .-CyDmaChPriority - 471 .section .text.CyDmaChSetExtendedAddress,"ax",%progbits - 472 .align 1 - 473 .global CyDmaChSetExtendedAddress - 474 .thumb - 475 .thumb_func - 476 .type CyDmaChSetExtendedAddress, %function - 477 CyDmaChSetExtendedAddress: - 478 .LFB10: - 445:.\Generated_Source\PSoC5/CyDmac.c **** - 446:.\Generated_Source\PSoC5/CyDmac.c **** - 447:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 448:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChSetExtendedAddress - 449:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 450:.\Generated_Source\PSoC5/CyDmac.c **** * - 451:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 452:.\Generated_Source\PSoC5/CyDmac.c **** * Sets the high 16 bits of the source and destination addresses for the DMA - 453:.\Generated_Source\PSoC5/CyDmac.c **** * channel (valid for all TDs in the chain). - 454:.\Generated_Source\PSoC5/CyDmac.c **** * - 455:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 456:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 457:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 458:.\Generated_Source\PSoC5/CyDmac.c **** * - 459:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 source: - 460:.\Generated_Source\PSoC5/CyDmac.c **** * Upper 16 bit address of the DMA transfer source. - 461:.\Generated_Source\PSoC5/CyDmac.c **** * - 462:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 destination: - 463:.\Generated_Source\PSoC5/CyDmac.c **** * Upper 16 bit address of the DMA transfer destination. - 464:.\Generated_Source\PSoC5/CyDmac.c **** * - 465:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 466:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 467:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 468:.\Generated_Source\PSoC5/CyDmac.c **** * - 469:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 470:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ - 471:.\Generated_Source\PSoC5/CyDmac.c **** - 472:.\Generated_Source\PSoC5/CyDmac.c **** { - 479 .loc 1 472 0 - 480 .cfi_startproc - 481 @ args = 0, pretend = 0, frame = 0 - 482 @ frame_needed = 0, uses_anonymous_args = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 18 - - - 483 @ link register save eliminated. - 484 .LVL41: - 473:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 474:.\Generated_Source\PSoC5/CyDmac.c **** reg16 *convert; - 475:.\Generated_Source\PSoC5/CyDmac.c **** - 476:.\Generated_Source\PSoC5/CyDmac.c **** #if(CY_PSOC5) - 477:.\Generated_Source\PSoC5/CyDmac.c **** - 478:.\Generated_Source\PSoC5/CyDmac.c **** /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */ - 479:.\Generated_Source\PSoC5/CyDmac.c **** if(source == 0x1FFFu) - 485 .loc 1 479 0 - 486 0000 41F6FF73 movw r3, #8191 - 480:.\Generated_Source\PSoC5/CyDmac.c **** { - 481:.\Generated_Source\PSoC5/CyDmac.c **** source = 0x2000u; - 487 .loc 1 481 0 - 488 0004 9942 cmp r1, r3 - 489 0006 08BF it eq - 490 0008 4FF40051 moveq r1, #8192 - 491 .LVL42: - 482:.\Generated_Source\PSoC5/CyDmac.c **** } - 483:.\Generated_Source\PSoC5/CyDmac.c **** - 484:.\Generated_Source\PSoC5/CyDmac.c **** if(destination == 0x1FFFu) - 485:.\Generated_Source\PSoC5/CyDmac.c **** { - 486:.\Generated_Source\PSoC5/CyDmac.c **** destination = 0x2000u; - 492 .loc 1 486 0 - 493 000c 9A42 cmp r2, r3 - 494 000e 08BF it eq - 495 0010 4FF40052 moveq r2, #8192 - 496 .LVL43: - 487:.\Generated_Source\PSoC5/CyDmac.c **** } - 488:.\Generated_Source\PSoC5/CyDmac.c **** - 489:.\Generated_Source\PSoC5/CyDmac.c **** #endif /* (CY_PSOC5) */ - 490:.\Generated_Source\PSoC5/CyDmac.c **** - 491:.\Generated_Source\PSoC5/CyDmac.c **** - 492:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 497 .loc 1 492 0 - 498 0014 1728 cmp r0, #23 - 499 0016 08D8 bhi .L57 - 493:.\Generated_Source\PSoC5/CyDmac.c **** { - 494:.\Generated_Source\PSoC5/CyDmac.c **** /* Set source address */ - 495:.\Generated_Source\PSoC5/CyDmac.c **** convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0]; - 500 .loc 1 495 0 - 501 0018 C000 lsls r0, r0, #3 - 502 .LVL44: - 503 001a 00F18043 add r3, r0, #1073741824 - 504 001e 03F5EC40 add r0, r3, #30208 - 505 .LVL45: - 496:.\Generated_Source\PSoC5/CyDmac.c **** CY_SET_REG16(convert, source); - 506 .loc 1 496 0 - 507 0022 8180 strh r1, [r0, #4] @ movhi - 508 .LVL46: - 497:.\Generated_Source\PSoC5/CyDmac.c **** - 498:.\Generated_Source\PSoC5/CyDmac.c **** /* Set destination address */ - 499:.\Generated_Source\PSoC5/CyDmac.c **** convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u]; - 500:.\Generated_Source\PSoC5/CyDmac.c **** CY_SET_REG16(convert, destination); - 509 .loc 1 500 0 - 510 0024 C280 strh r2, [r0, #6] @ movhi - 511 .LVL47: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 19 - - - 501:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 512 .loc 1 501 0 - 513 0026 0020 movs r0, #0 - 514 .LVL48: - 515 0028 7047 bx lr - 516 .LVL49: - 517 .L57: - 473:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 518 .loc 1 473 0 - 519 002a 0120 movs r0, #1 - 520 .LVL50: - 502:.\Generated_Source\PSoC5/CyDmac.c **** } - 503:.\Generated_Source\PSoC5/CyDmac.c **** - 504:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 505:.\Generated_Source\PSoC5/CyDmac.c **** } - 521 .loc 1 505 0 - 522 002c 7047 bx lr - 523 .cfi_endproc - 524 .LFE10: - 525 .size CyDmaChSetExtendedAddress, .-CyDmaChSetExtendedAddress - 526 .section .text.CyDmaChSetInitialTd,"ax",%progbits - 527 .align 1 - 528 .global CyDmaChSetInitialTd - 529 .thumb - 530 .thumb_func - 531 .type CyDmaChSetInitialTd, %function - 532 CyDmaChSetInitialTd: - 533 .LFB11: - 506:.\Generated_Source\PSoC5/CyDmac.c **** - 507:.\Generated_Source\PSoC5/CyDmac.c **** - 508:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 509:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChSetInitialTd - 510:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 511:.\Generated_Source\PSoC5/CyDmac.c **** * - 512:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 513:.\Generated_Source\PSoC5/CyDmac.c **** * Sets the initial TD to be executed for the channel when the CyDmaChEnable() - 514:.\Generated_Source\PSoC5/CyDmac.c **** * function is called. - 515:.\Generated_Source\PSoC5/CyDmac.c **** * - 516:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 517:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 518:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). - 519:.\Generated_Source\PSoC5/CyDmac.c **** * - 520:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 startTd: - 521:.\Generated_Source\PSoC5/CyDmac.c **** * The index of TD to set as the first TD associated with the channel. Zero is - 522:.\Generated_Source\PSoC5/CyDmac.c **** * a valid TD index. - 523:.\Generated_Source\PSoC5/CyDmac.c **** * - 524:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 525:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 526:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 527:.\Generated_Source\PSoC5/CyDmac.c **** * - 528:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 529:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) - 530:.\Generated_Source\PSoC5/CyDmac.c **** { - 534 .loc 1 530 0 - 535 .cfi_startproc - 536 @ args = 0, pretend = 0, frame = 0 - 537 @ frame_needed = 0, uses_anonymous_args = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 20 - - - 538 @ link register save eliminated. - 539 .LVL51: - 531:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 532:.\Generated_Source\PSoC5/CyDmac.c **** - 533:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 540 .loc 1 533 0 - 541 0000 1728 cmp r0, #23 - 542 0002 05D8 bhi .L60 - 534:.\Generated_Source\PSoC5/CyDmac.c **** { - 535:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd; - 543 .loc 1 535 0 - 544 0004 034B ldr r3, .L61 - 545 0006 0001 lsls r0, r0, #4 - 546 .LVL52: - 547 0008 C218 adds r2, r0, r3 - 548 000a 5172 strb r1, [r2, #9] - 549 .LVL53: - 536:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 550 .loc 1 536 0 - 551 000c 0020 movs r0, #0 - 552 000e 7047 bx lr - 553 .LVL54: - 554 .L60: - 531:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 555 .loc 1 531 0 - 556 0010 0120 movs r0, #1 - 557 .LVL55: - 537:.\Generated_Source\PSoC5/CyDmac.c **** } - 538:.\Generated_Source\PSoC5/CyDmac.c **** - 539:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 540:.\Generated_Source\PSoC5/CyDmac.c **** } - 558 .loc 1 540 0 - 559 0012 7047 bx lr - 560 .L62: - 561 .align 2 - 562 .L61: - 563 0014 10700040 .word 1073770512 - 564 .cfi_endproc - 565 .LFE11: - 566 .size CyDmaChSetInitialTd, .-CyDmaChSetInitialTd - 567 .section .text.CyDmaChSetRequest,"ax",%progbits - 568 .align 1 - 569 .global CyDmaChSetRequest - 570 .thumb - 571 .thumb_func - 572 .type CyDmaChSetRequest, %function - 573 CyDmaChSetRequest: - 574 .LFB12: - 541:.\Generated_Source\PSoC5/CyDmac.c **** - 542:.\Generated_Source\PSoC5/CyDmac.c **** - 543:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 544:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChSetRequest - 545:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 546:.\Generated_Source\PSoC5/CyDmac.c **** * - 547:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 548:.\Generated_Source\PSoC5/CyDmac.c **** * Allows the caller to terminate a chain of TDs, terminate one TD, or create a - 549:.\Generated_Source\PSoC5/CyDmac.c **** * direct request to start the DMA channel. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 21 - - - 550:.\Generated_Source\PSoC5/CyDmac.c **** * - 551:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 552:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 553:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 554:.\Generated_Source\PSoC5/CyDmac.c **** * - 555:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 request: - 556:.\Generated_Source\PSoC5/CyDmac.c **** * One of the following constants. Each of the constants is a three-bit value. - 557:.\Generated_Source\PSoC5/CyDmac.c **** * - 558:.\Generated_Source\PSoC5/CyDmac.c **** * CPU_REQ - Create a direct request to start the DMA channel - 559:.\Generated_Source\PSoC5/CyDmac.c **** * CPU_TERM_TD - Terminate one TD - 560:.\Generated_Source\PSoC5/CyDmac.c **** * CPU_TERM_CHAIN - Terminate a chain of TDs - 561:.\Generated_Source\PSoC5/CyDmac.c **** * - 562:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 563:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 564:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 565:.\Generated_Source\PSoC5/CyDmac.c **** * - 566:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 567:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) - 568:.\Generated_Source\PSoC5/CyDmac.c **** { - 575 .loc 1 568 0 - 576 .cfi_startproc - 577 @ args = 0, pretend = 0, frame = 0 - 578 @ frame_needed = 0, uses_anonymous_args = 0 - 579 @ link register save eliminated. - 580 .LVL56: - 569:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 570:.\Generated_Source\PSoC5/CyDmac.c **** - 571:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 581 .loc 1 571 0 - 582 0000 1728 cmp r0, #23 - 583 0002 0AD8 bhi .L65 - 572:.\Generated_Source\PSoC5/CyDmac.c **** { - 573:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_C - 584 .loc 1 573 0 - 585 0004 064B ldr r3, .L66 - 586 0006 0001 lsls r0, r0, #4 - 587 .LVL57: - 588 0008 C018 adds r0, r0, r3 - 589 000a 0279 ldrb r2, [r0, #4] @ zero_extendqisi2 - 590 000c 01F00701 and r1, r1, #7 - 591 .LVL58: - 592 0010 42EA0103 orr r3, r2, r1 - 593 0014 0371 strb r3, [r0, #4] - 594 .LVL59: - 574:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 595 .loc 1 574 0 - 596 0016 0020 movs r0, #0 - 597 0018 7047 bx lr - 598 .LVL60: - 599 .L65: - 569:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 600 .loc 1 569 0 - 601 001a 0120 movs r0, #1 - 602 .LVL61: - 575:.\Generated_Source\PSoC5/CyDmac.c **** } - 576:.\Generated_Source\PSoC5/CyDmac.c **** - 577:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 22 - - - 578:.\Generated_Source\PSoC5/CyDmac.c **** } - 603 .loc 1 578 0 - 604 001c 7047 bx lr - 605 .L67: - 606 001e 00BF .align 2 - 607 .L66: - 608 0020 10700040 .word 1073770512 - 609 .cfi_endproc - 610 .LFE12: - 611 .size CyDmaChSetRequest, .-CyDmaChSetRequest - 612 .section .text.CyDmaChGetRequest,"ax",%progbits - 613 .align 1 - 614 .global CyDmaChGetRequest - 615 .thumb - 616 .thumb_func - 617 .type CyDmaChGetRequest, %function - 618 CyDmaChGetRequest: - 619 .LFB13: - 579:.\Generated_Source\PSoC5/CyDmac.c **** - 580:.\Generated_Source\PSoC5/CyDmac.c **** - 581:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 582:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChGetRequest - 583:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 584:.\Generated_Source\PSoC5/CyDmac.c **** * - 585:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 586:.\Generated_Source\PSoC5/CyDmac.c **** * This function allows the caller of CyDmaChSetRequest() to determine if the - 587:.\Generated_Source\PSoC5/CyDmac.c **** * request was completed. - 588:.\Generated_Source\PSoC5/CyDmac.c **** * - 589:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 590:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 591:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 592:.\Generated_Source\PSoC5/CyDmac.c **** * - 593:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 594:.\Generated_Source\PSoC5/CyDmac.c **** * Returns a three-bit field, corresponding to the three bits of the request, - 595:.\Generated_Source\PSoC5/CyDmac.c **** * which describes the state of the previously posted request. If the value is - 596:.\Generated_Source\PSoC5/CyDmac.c **** * zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is - 597:.\Generated_Source\PSoC5/CyDmac.c **** * invalid. - 598:.\Generated_Source\PSoC5/CyDmac.c **** * - 599:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 600:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChGetRequest(uint8 chHandle) - 601:.\Generated_Source\PSoC5/CyDmac.c **** { - 620 .loc 1 601 0 - 621 .cfi_startproc - 622 @ args = 0, pretend = 0, frame = 0 - 623 @ frame_needed = 0, uses_anonymous_args = 0 - 624 @ link register save eliminated. - 625 .LVL62: - 602:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CY_DMA_INVALID_CHANNEL; - 603:.\Generated_Source\PSoC5/CyDmac.c **** - 604:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 626 .loc 1 604 0 - 627 0000 1728 cmp r0, #23 - 628 0002 06D8 bhi .L70 - 605:.\Generated_Source\PSoC5/CyDmac.c **** { - 606:.\Generated_Source\PSoC5/CyDmac.c **** status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & - 629 .loc 1 606 0 - 630 0004 044B ldr r3, .L71 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 23 - - - 631 0006 0001 lsls r0, r0, #4 - 632 .LVL63: - 633 0008 C118 adds r1, r0, r3 - 634 000a 0A79 ldrb r2, [r1, #4] @ zero_extendqisi2 - 635 000c 02F00700 and r0, r2, #7 - 636 .LVL64: - 637 0010 7047 bx lr - 638 .LVL65: - 639 .L70: - 602:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CY_DMA_INVALID_CHANNEL; - 640 .loc 1 602 0 - 641 0012 FF20 movs r0, #255 - 642 .LVL66: - 607:.\Generated_Source\PSoC5/CyDmac.c **** (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); - 608:.\Generated_Source\PSoC5/CyDmac.c **** } - 609:.\Generated_Source\PSoC5/CyDmac.c **** - 610:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 611:.\Generated_Source\PSoC5/CyDmac.c **** } - 643 .loc 1 611 0 - 644 0014 7047 bx lr - 645 .L72: - 646 0016 00BF .align 2 - 647 .L71: - 648 0018 10700040 .word 1073770512 - 649 .cfi_endproc - 650 .LFE13: - 651 .size CyDmaChGetRequest, .-CyDmaChGetRequest - 652 .section .text.CyDmaChStatus,"ax",%progbits - 653 .align 1 - 654 .global CyDmaChStatus - 655 .thumb - 656 .thumb_func - 657 .type CyDmaChStatus, %function - 658 CyDmaChStatus: - 659 .LFB14: - 612:.\Generated_Source\PSoC5/CyDmac.c **** - 613:.\Generated_Source\PSoC5/CyDmac.c **** - 614:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 615:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChStatus - 616:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 617:.\Generated_Source\PSoC5/CyDmac.c **** * - 618:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 619:.\Generated_Source\PSoC5/CyDmac.c **** * Determines the status of the DMA channel. - 620:.\Generated_Source\PSoC5/CyDmac.c **** * - 621:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 622:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 623:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). - 624:.\Generated_Source\PSoC5/CyDmac.c **** * - 625:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 * currentTd: - 626:.\Generated_Source\PSoC5/CyDmac.c **** * The address to store the index of the current TD. Can be NULL if the value - 627:.\Generated_Source\PSoC5/CyDmac.c **** * is not needed. - 628:.\Generated_Source\PSoC5/CyDmac.c **** * - 629:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 * state: - 630:.\Generated_Source\PSoC5/CyDmac.c **** * The address to store the state of the channel. Can be NULL if the value is - 631:.\Generated_Source\PSoC5/CyDmac.c **** * not needed. - 632:.\Generated_Source\PSoC5/CyDmac.c **** * - 633:.\Generated_Source\PSoC5/CyDmac.c **** * STATUS_TD_ACTIVE - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 24 - - - 634:.\Generated_Source\PSoC5/CyDmac.c **** * 0: Channel is not currently being serviced by DMAC - 635:.\Generated_Source\PSoC5/CyDmac.c **** * 1: Channel is currently being serviced by DMAC - 636:.\Generated_Source\PSoC5/CyDmac.c **** * - 637:.\Generated_Source\PSoC5/CyDmac.c **** * STATUS_CHAIN_ACTIVE - 638:.\Generated_Source\PSoC5/CyDmac.c **** * 0: TD chain is inactive; either no DMA requests have triggered a new chain - 639:.\Generated_Source\PSoC5/CyDmac.c **** * or the previous chain has completed. - 640:.\Generated_Source\PSoC5/CyDmac.c **** * 1: TD chain has been triggered by a DMA request - 641:.\Generated_Source\PSoC5/CyDmac.c **** * - 642:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 643:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 644:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 645:.\Generated_Source\PSoC5/CyDmac.c **** * - 646:.\Generated_Source\PSoC5/CyDmac.c **** * Theory: - 647:.\Generated_Source\PSoC5/CyDmac.c **** * The caller can check on the activity of the Current TD and the Chain. - 648:.\Generated_Source\PSoC5/CyDmac.c **** * - 649:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 650:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) - 651:.\Generated_Source\PSoC5/CyDmac.c **** { - 660 .loc 1 651 0 - 661 .cfi_startproc - 662 @ args = 0, pretend = 0, frame = 0 - 663 @ frame_needed = 0, uses_anonymous_args = 0 - 664 .LVL67: - 652:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 653:.\Generated_Source\PSoC5/CyDmac.c **** - 654:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 665 .loc 1 654 0 - 666 0000 1728 cmp r0, #23 - 651:.\Generated_Source\PSoC5/CyDmac.c **** { - 667 .loc 1 651 0 - 668 0002 10B5 push {r4, lr} - 669 .LCFI2: - 670 .cfi_def_cfa_offset 8 - 671 .cfi_offset 4, -8 - 672 .cfi_offset 14, -4 - 673 .loc 1 654 0 - 674 0004 0FD8 bhi .L76 - 655:.\Generated_Source\PSoC5/CyDmac.c **** { - 656:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != currentTd) - 675 .loc 1 656 0 - 676 0006 31B1 cbz r1, .L75 - 657:.\Generated_Source\PSoC5/CyDmac.c **** { - 658:.\Generated_Source\PSoC5/CyDmac.c **** *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu; - 677 .loc 1 658 0 - 678 0008 084B ldr r3, .L82 - 679 000a 0401 lsls r4, r0, #4 - 680 000c E318 adds r3, r4, r3 - 681 000e 5B7A ldrb r3, [r3, #9] @ zero_extendqisi2 - 682 0010 03F07F03 and r3, r3, #127 - 683 0014 0B70 strb r3, [r1, #0] - 684 .L75: - 659:.\Generated_Source\PSoC5/CyDmac.c **** } - 660:.\Generated_Source\PSoC5/CyDmac.c **** - 661:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != state) - 685 .loc 1 661 0 - 686 0016 22B1 cbz r2, .L81 - 662:.\Generated_Source\PSoC5/CyDmac.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 25 - - - 663:.\Generated_Source\PSoC5/CyDmac.c **** *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; - 687 .loc 1 663 0 - 688 0018 0449 ldr r1, .L82 - 689 .LVL68: - 690 001a 0001 lsls r0, r0, #4 - 691 .LVL69: - 692 001c 4318 adds r3, r0, r1 - 693 001e 187A ldrb r0, [r3, #8] @ zero_extendqisi2 - 694 0020 1070 strb r0, [r2, #0] - 695 .L81: - 664:.\Generated_Source\PSoC5/CyDmac.c **** } - 665:.\Generated_Source\PSoC5/CyDmac.c **** - 666:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 696 .loc 1 666 0 - 697 0022 0020 movs r0, #0 - 698 0024 10BD pop {r4, pc} - 699 .LVL70: - 700 .L76: - 652:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 701 .loc 1 652 0 - 702 0026 0120 movs r0, #1 - 703 .LVL71: - 704 0028 10BD pop {r4, pc} - 705 .L83: - 706 002a 00BF .align 2 - 707 .L82: - 708 002c 10700040 .word 1073770512 - 709 .cfi_endproc - 710 .LFE14: - 711 .size CyDmaChStatus, .-CyDmaChStatus - 712 .section .text.CyDmaChSetConfiguration,"ax",%progbits - 713 .align 1 - 714 .global CyDmaChSetConfiguration - 715 .thumb - 716 .thumb_func - 717 .type CyDmaChSetConfiguration, %function - 718 CyDmaChSetConfiguration: - 719 .LFB15: - 667:.\Generated_Source\PSoC5/CyDmac.c **** } - 668:.\Generated_Source\PSoC5/CyDmac.c **** - 669:.\Generated_Source\PSoC5/CyDmac.c **** return (status); - 670:.\Generated_Source\PSoC5/CyDmac.c **** } - 671:.\Generated_Source\PSoC5/CyDmac.c **** - 672:.\Generated_Source\PSoC5/CyDmac.c **** - 673:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 674:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChSetConfiguration - 675:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 676:.\Generated_Source\PSoC5/CyDmac.c **** * - 677:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 678:.\Generated_Source\PSoC5/CyDmac.c **** * Sets configuration information of the channel. - 679:.\Generated_Source\PSoC5/CyDmac.c **** * - 680:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 681:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: - 682:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). - 683:.\Generated_Source\PSoC5/CyDmac.c **** * - 684:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 burstCount: - 685:.\Generated_Source\PSoC5/CyDmac.c **** * Specifies the size of bursts (1 to 127) the data transfer should be divided - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 26 - - - 686:.\Generated_Source\PSoC5/CyDmac.c **** * into. If this value is zero then the whole transfer is done in one burst. - 687:.\Generated_Source\PSoC5/CyDmac.c **** * - 688:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 requestPerBurst: - 689:.\Generated_Source\PSoC5/CyDmac.c **** * The whole of the data can be split into multiple bursts, if this is - 690:.\Generated_Source\PSoC5/CyDmac.c **** * required to complete the transaction: - 691:.\Generated_Source\PSoC5/CyDmac.c **** * 0: All subsequent bursts after the first burst will be automatically - 692:.\Generated_Source\PSoC5/CyDmac.c **** * requested and carried out - 693:.\Generated_Source\PSoC5/CyDmac.c **** * 1: All subsequent bursts after the first burst must also be individually - 694:.\Generated_Source\PSoC5/CyDmac.c **** * requested. - 695:.\Generated_Source\PSoC5/CyDmac.c **** * - 696:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdDone0: - 697:.\Generated_Source\PSoC5/CyDmac.c **** * Selects one of the TERMOUT0 interrupt lines to signal completion. The line - 698:.\Generated_Source\PSoC5/CyDmac.c **** * connected to the nrq terminal will determine the TERMOUT0_SEL definition and - 699:.\Generated_Source\PSoC5/CyDmac.c **** * should be used as supplied by cyfitter.h - 700:.\Generated_Source\PSoC5/CyDmac.c **** * - 701:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdDone1: - 702:.\Generated_Source\PSoC5/CyDmac.c **** * Selects one of the TERMOUT1 interrupt lines to signal completion. The line - 703:.\Generated_Source\PSoC5/CyDmac.c **** * connected to the nrq terminal will determine the TERMOUT1_SEL definition and - 704:.\Generated_Source\PSoC5/CyDmac.c **** * should be used as supplied by cyfitter.h - 705:.\Generated_Source\PSoC5/CyDmac.c **** * - 706:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdStop: - 707:.\Generated_Source\PSoC5/CyDmac.c **** * Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD - 708:.\Generated_Source\PSoC5/CyDmac.c **** * should terminate. The signal connected to the trq terminal will determine - 709:.\Generated_Source\PSoC5/CyDmac.c **** * which TERMIN (termination request) is used. - 710:.\Generated_Source\PSoC5/CyDmac.c **** * - 711:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 712:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 713:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. - 714:.\Generated_Source\PSoC5/CyDmac.c **** * - 715:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 716:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, - 717:.\Generated_Source\PSoC5/CyDmac.c **** uint8 tdDone0, uint8 tdDone1, uint8 tdStop) - 718:.\Generated_Source\PSoC5/CyDmac.c **** { - 720 .loc 1 718 0 - 721 .cfi_startproc - 722 @ args = 8, pretend = 0, frame = 0 - 723 @ frame_needed = 0, uses_anonymous_args = 0 - 724 .LVL72: - 719:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 720:.\Generated_Source\PSoC5/CyDmac.c **** - 721:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 725 .loc 1 721 0 - 726 0000 1728 cmp r0, #23 - 718:.\Generated_Source\PSoC5/CyDmac.c **** { - 727 .loc 1 718 0 - 728 0002 10B5 push {r4, lr} - 729 .LCFI3: - 730 .cfi_def_cfa_offset 8 - 731 .cfi_offset 4, -8 - 732 .cfi_offset 14, -4 - 733 .loc 1 721 0 - 734 0004 1AD8 bhi .L86 - 722:.\Generated_Source\PSoC5/CyDmac.c **** { - 723:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBur - 735 .loc 1 723 0 - 736 0006 01F07F01 and r1, r1, #127 - 737 .LVL73: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 27 - - - 738 000a C400 lsls r4, r0, #3 - 739 000c 41EAC212 orr r2, r1, r2, lsl #7 - 740 .LVL74: - 724:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & - 741 .loc 1 724 0 - 742 0010 9DF80810 ldrb r1, [sp, #8] @ zero_extendqisi2 - 723:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBur - 743 .loc 1 723 0 - 744 0014 04F18040 add r0, r4, #1073741824 - 745 .LVL75: - 746 .loc 1 724 0 - 747 0018 03F00F03 and r3, r3, #15 - 748 .LVL76: - 723:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBur - 749 .loc 1 723 0 - 750 001c 00F5EC44 add r4, r0, #30208 - 751 0020 D0B2 uxtb r0, r2 - 752 .loc 1 724 0 - 753 0022 43EA0112 orr r2, r3, r1, lsl #4 - 725:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; - 754 .loc 1 725 0 - 755 0026 9DF80C30 ldrb r3, [sp, #12] @ zero_extendqisi2 - 723:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBur - 756 .loc 1 723 0 - 757 002a 2070 strb r0, [r4, #0] - 724:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & - 758 .loc 1 724 0 - 759 002c D0B2 uxtb r0, r2 - 760 002e 6070 strb r0, [r4, #1] - 761 .loc 1 725 0 - 762 0030 03F00F01 and r1, r3, #15 - 726:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */ - 763 .loc 1 726 0 - 764 0034 0020 movs r0, #0 - 725:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; - 765 .loc 1 725 0 - 766 0036 A170 strb r1, [r4, #2] - 767 .loc 1 726 0 - 768 0038 E070 strb r0, [r4, #3] - 769 .LVL77: - 770 003a 10BD pop {r4, pc} - 771 .LVL78: - 772 .L86: - 719:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 773 .loc 1 719 0 - 774 003c 0120 movs r0, #1 - 775 .LVL79: - 727:.\Generated_Source\PSoC5/CyDmac.c **** - 728:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 729:.\Generated_Source\PSoC5/CyDmac.c **** } - 730:.\Generated_Source\PSoC5/CyDmac.c **** - 731:.\Generated_Source\PSoC5/CyDmac.c **** return (status); - 732:.\Generated_Source\PSoC5/CyDmac.c **** } - 776 .loc 1 732 0 - 777 003e 10BD pop {r4, pc} - 778 .cfi_endproc - 779 .LFE15: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 28 - - - 780 .size CyDmaChSetConfiguration, .-CyDmaChSetConfiguration - 781 .section .text.CyDmaTdAllocate,"ax",%progbits - 782 .align 1 - 783 .global CyDmaTdAllocate - 784 .thumb - 785 .thumb_func - 786 .type CyDmaTdAllocate, %function - 787 CyDmaTdAllocate: - 788 .LFB16: - 733:.\Generated_Source\PSoC5/CyDmac.c **** - 734:.\Generated_Source\PSoC5/CyDmac.c **** - 735:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 736:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaTdAllocate - 737:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 738:.\Generated_Source\PSoC5/CyDmac.c **** * - 739:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 740:.\Generated_Source\PSoC5/CyDmac.c **** * Allocates a TD for use with an allocated DMA channel. - 741:.\Generated_Source\PSoC5/CyDmac.c **** * - 742:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 743:.\Generated_Source\PSoC5/CyDmac.c **** * None - 744:.\Generated_Source\PSoC5/CyDmac.c **** * - 745:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 746:.\Generated_Source\PSoC5/CyDmac.c **** * Zero-based index of the TD to be used by the caller. Since there are 128 TDs - 747:.\Generated_Source\PSoC5/CyDmac.c **** * minus the reserved TDs (0 to 23), the value returned would range from 24 to - 748:.\Generated_Source\PSoC5/CyDmac.c **** * 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs - 749:.\Generated_Source\PSoC5/CyDmac.c **** * available. - 750:.\Generated_Source\PSoC5/CyDmac.c **** * - 751:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 752:.\Generated_Source\PSoC5/CyDmac.c **** uint8 CyDmaTdAllocate(void) - 753:.\Generated_Source\PSoC5/CyDmac.c **** { - 789 .loc 1 753 0 - 790 .cfi_startproc - 791 @ args = 0, pretend = 0, frame = 0 - 792 @ frame_needed = 0, uses_anonymous_args = 0 - 793 .LVL80: - 794 0000 10B5 push {r4, lr} - 795 .LCFI4: - 796 .cfi_def_cfa_offset 8 - 797 .cfi_offset 4, -8 - 798 .cfi_offset 14, -4 - 754:.\Generated_Source\PSoC5/CyDmac.c **** uint8 interruptState; - 755:.\Generated_Source\PSoC5/CyDmac.c **** uint8 element = CY_DMA_INVALID_TD; - 756:.\Generated_Source\PSoC5/CyDmac.c **** - 757:.\Generated_Source\PSoC5/CyDmac.c **** /* Enter critical section! */ - 758:.\Generated_Source\PSoC5/CyDmac.c **** interruptState = CyEnterCriticalSection(); - 799 .loc 1 758 0 - 800 0002 FFF7FEFF bl CyEnterCriticalSection - 801 .LVL81: - 759:.\Generated_Source\PSoC5/CyDmac.c **** - 760:.\Generated_Source\PSoC5/CyDmac.c **** if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS) - 802 .loc 1 760 0 - 803 0006 0A4B ldr r3, .L90 - 804 0008 5A78 ldrb r2, [r3, #1] @ zero_extendqisi2 - 805 000a 182A cmp r2, #24 - 806 000c 0AD9 bls .L89 - 761:.\Generated_Source\PSoC5/CyDmac.c **** { - 762:.\Generated_Source\PSoC5/CyDmac.c **** /* Get pointer to the Next available. */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 29 - - - 763:.\Generated_Source\PSoC5/CyDmac.c **** element = CyDmaTdFreeIndex; - 807 .loc 1 763 0 - 808 000e 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 809 .LVL82: - 764:.\Generated_Source\PSoC5/CyDmac.c **** - 765:.\Generated_Source\PSoC5/CyDmac.c **** /* Decrement the count. */ - 766:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdCurrentNumber--; - 810 .loc 1 766 0 - 811 0010 511E subs r1, r2, #1 - 767:.\Generated_Source\PSoC5/CyDmac.c **** - 768:.\Generated_Source\PSoC5/CyDmac.c **** /* Update the next available pointer. */ - 769:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0]; - 812 .loc 1 769 0 - 813 0012 E200 lsls r2, r4, #3 - 766:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdCurrentNumber--; - 814 .loc 1 766 0 - 815 0014 5970 strb r1, [r3, #1] - 816 .loc 1 769 0 - 817 0016 02F18041 add r1, r2, #1073741824 - 818 001a 01F5F042 add r2, r1, #30720 - 819 001e 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 820 0020 1970 strb r1, [r3, #0] - 821 0022 00E0 b .L88 - 822 .LVL83: - 823 .L89: - 755:.\Generated_Source\PSoC5/CyDmac.c **** uint8 element = CY_DMA_INVALID_TD; - 824 .loc 1 755 0 - 825 0024 FF24 movs r4, #255 - 826 .LVL84: - 827 .L88: - 770:.\Generated_Source\PSoC5/CyDmac.c **** } - 771:.\Generated_Source\PSoC5/CyDmac.c **** - 772:.\Generated_Source\PSoC5/CyDmac.c **** /* Exit critical section! */ - 773:.\Generated_Source\PSoC5/CyDmac.c **** CyExitCriticalSection(interruptState); - 828 .loc 1 773 0 - 829 0026 FFF7FEFF bl CyExitCriticalSection - 830 .LVL85: - 774:.\Generated_Source\PSoC5/CyDmac.c **** - 775:.\Generated_Source\PSoC5/CyDmac.c **** return(element); - 776:.\Generated_Source\PSoC5/CyDmac.c **** } - 831 .loc 1 776 0 - 832 002a 2046 mov r0, r4 - 833 002c 10BD pop {r4, pc} - 834 .L91: - 835 002e 00BF .align 2 - 836 .L90: - 837 0030 00000000 .word .LANCHOR0 - 838 .cfi_endproc - 839 .LFE16: - 840 .size CyDmaTdAllocate, .-CyDmaTdAllocate - 841 .section .text.CyDmaTdFree,"ax",%progbits - 842 .align 1 - 843 .global CyDmaTdFree - 844 .thumb - 845 .thumb_func - 846 .type CyDmaTdFree, %function - 847 CyDmaTdFree: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 30 - - - 848 .LFB17: - 777:.\Generated_Source\PSoC5/CyDmac.c **** - 778:.\Generated_Source\PSoC5/CyDmac.c **** - 779:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 780:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaTdFree - 781:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 782:.\Generated_Source\PSoC5/CyDmac.c **** * - 783:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 784:.\Generated_Source\PSoC5/CyDmac.c **** * Returns a TD to the free list. - 785:.\Generated_Source\PSoC5/CyDmac.c **** * - 786:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 787:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdHandle: - 788:.\Generated_Source\PSoC5/CyDmac.c **** * The TD handle returned by the CyDmaTdAllocate(). - 789:.\Generated_Source\PSoC5/CyDmac.c **** * - 790:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 791:.\Generated_Source\PSoC5/CyDmac.c **** * None - 792:.\Generated_Source\PSoC5/CyDmac.c **** * - 793:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 794:.\Generated_Source\PSoC5/CyDmac.c **** void CyDmaTdFree(uint8 tdHandle) - 795:.\Generated_Source\PSoC5/CyDmac.c **** { - 849 .loc 1 795 0 - 850 .cfi_startproc - 851 @ args = 0, pretend = 0, frame = 0 - 852 @ frame_needed = 0, uses_anonymous_args = 0 - 853 .LVL86: - 796:.\Generated_Source\PSoC5/CyDmac.c **** if(tdHandle < CY_DMA_NUMBEROF_TDS) - 854 .loc 1 796 0 - 855 0000 0306 lsls r3, r0, #24 - 795:.\Generated_Source\PSoC5/CyDmac.c **** { - 856 .loc 1 795 0 - 857 0002 10B5 push {r4, lr} - 858 .LCFI5: - 859 .cfi_def_cfa_offset 8 - 860 .cfi_offset 4, -8 - 861 .cfi_offset 14, -4 - 795:.\Generated_Source\PSoC5/CyDmac.c **** { - 862 .loc 1 795 0 - 863 0004 0446 mov r4, r0 - 864 .loc 1 796 0 - 865 0006 11D4 bmi .L92 - 866 .LBB2: - 797:.\Generated_Source\PSoC5/CyDmac.c **** { - 798:.\Generated_Source\PSoC5/CyDmac.c **** /* Enter critical section! */ - 799:.\Generated_Source\PSoC5/CyDmac.c **** uint8 interruptState = CyEnterCriticalSection(); - 867 .loc 1 799 0 - 868 0008 FFF7FEFF bl CyEnterCriticalSection - 869 .LVL87: - 800:.\Generated_Source\PSoC5/CyDmac.c **** - 801:.\Generated_Source\PSoC5/CyDmac.c **** /* Get pointer to the Next available. */ - 802:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; - 870 .loc 1 802 0 - 871 000c 084B ldr r3, .L94 - 872 000e E200 lsls r2, r4, #3 - 873 0010 02F18041 add r1, r2, #1073741824 - 874 0014 01F5F042 add r2, r1, #30720 - 875 0018 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 803:.\Generated_Source\PSoC5/CyDmac.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 31 - - - 804:.\Generated_Source\PSoC5/CyDmac.c **** /* Set new Next Available. */ - 805:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdFreeIndex = tdHandle; - 876 .loc 1 805 0 - 877 001a 1C70 strb r4, [r3, #0] - 802:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; - 878 .loc 1 802 0 - 879 001c 1170 strb r1, [r2, #0] - 806:.\Generated_Source\PSoC5/CyDmac.c **** - 807:.\Generated_Source\PSoC5/CyDmac.c **** /* Keep track of how many left. */ - 808:.\Generated_Source\PSoC5/CyDmac.c **** CyDmaTdCurrentNumber++; - 880 .loc 1 808 0 - 881 001e 5A78 ldrb r2, [r3, #1] @ zero_extendqisi2 - 882 0020 511C adds r1, r2, #1 - 883 0022 5970 strb r1, [r3, #1] - 884 .LBE2: - 809:.\Generated_Source\PSoC5/CyDmac.c **** - 810:.\Generated_Source\PSoC5/CyDmac.c **** /* Exit critical section! */ - 811:.\Generated_Source\PSoC5/CyDmac.c **** CyExitCriticalSection(interruptState); - 812:.\Generated_Source\PSoC5/CyDmac.c **** } - 813:.\Generated_Source\PSoC5/CyDmac.c **** } - 885 .loc 1 813 0 - 886 0024 BDE81040 pop {r4, lr} - 887 .LBB3: - 811:.\Generated_Source\PSoC5/CyDmac.c **** CyExitCriticalSection(interruptState); - 888 .loc 1 811 0 - 889 0028 FFF7FEBF b CyExitCriticalSection - 890 .LVL88: - 891 .L92: - 892 002c 10BD pop {r4, pc} - 893 .L95: - 894 002e 00BF .align 2 - 895 .L94: - 896 0030 00000000 .word .LANCHOR0 - 897 .LBE3: - 898 .cfi_endproc - 899 .LFE17: - 900 .size CyDmaTdFree, .-CyDmaTdFree - 901 .section .text.CyDmaTdFreeCount,"ax",%progbits - 902 .align 1 - 903 .global CyDmaTdFreeCount - 904 .thumb - 905 .thumb_func - 906 .type CyDmaTdFreeCount, %function - 907 CyDmaTdFreeCount: - 908 .LFB18: - 814:.\Generated_Source\PSoC5/CyDmac.c **** - 815:.\Generated_Source\PSoC5/CyDmac.c **** - 816:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 817:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaTdFreeCount - 818:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 819:.\Generated_Source\PSoC5/CyDmac.c **** * - 820:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 821:.\Generated_Source\PSoC5/CyDmac.c **** * Returns the number of free TDs available to be allocated. - 822:.\Generated_Source\PSoC5/CyDmac.c **** * - 823:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 824:.\Generated_Source\PSoC5/CyDmac.c **** * None - 825:.\Generated_Source\PSoC5/CyDmac.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 32 - - - 826:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 827:.\Generated_Source\PSoC5/CyDmac.c **** * The number of free TDs. - 828:.\Generated_Source\PSoC5/CyDmac.c **** * - 829:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 830:.\Generated_Source\PSoC5/CyDmac.c **** uint8 CyDmaTdFreeCount(void) - 831:.\Generated_Source\PSoC5/CyDmac.c **** { - 909 .loc 1 831 0 - 910 .cfi_startproc - 911 @ args = 0, pretend = 0, frame = 0 - 912 @ frame_needed = 0, uses_anonymous_args = 0 - 913 @ link register save eliminated. - 832:.\Generated_Source\PSoC5/CyDmac.c **** return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS); - 914 .loc 1 832 0 - 915 0000 024B ldr r3, .L97 - 916 0002 5878 ldrb r0, [r3, #1] @ zero_extendqisi2 - 917 0004 1838 subs r0, r0, #24 - 833:.\Generated_Source\PSoC5/CyDmac.c **** } - 918 .loc 1 833 0 - 919 0006 C0B2 uxtb r0, r0 - 920 0008 7047 bx lr - 921 .L98: - 922 000a 00BF .align 2 - 923 .L97: - 924 000c 00000000 .word .LANCHOR0 - 925 .cfi_endproc - 926 .LFE18: - 927 .size CyDmaTdFreeCount, .-CyDmaTdFreeCount - 928 .section .text.CyDmaTdSetConfiguration,"ax",%progbits - 929 .align 1 - 930 .global CyDmaTdSetConfiguration - 931 .thumb - 932 .thumb_func - 933 .type CyDmaTdSetConfiguration, %function - 934 CyDmaTdSetConfiguration: - 935 .LFB19: - 834:.\Generated_Source\PSoC5/CyDmac.c **** - 835:.\Generated_Source\PSoC5/CyDmac.c **** - 836:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 837:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaTdSetConfiguration - 838:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 839:.\Generated_Source\PSoC5/CyDmac.c **** * - 840:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 841:.\Generated_Source\PSoC5/CyDmac.c **** * Configures the TD. - 842:.\Generated_Source\PSoC5/CyDmac.c **** * - 843:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 844:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdHandle: - 845:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaTdAlloc(). - 846:.\Generated_Source\PSoC5/CyDmac.c **** * - 847:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 transferCount: - 848:.\Generated_Source\PSoC5/CyDmac.c **** * The size of the data transfer (in bytes) for this TD. A size of zero will - 849:.\Generated_Source\PSoC5/CyDmac.c **** * cause the transfer to continue indefinitely. This parameter is limited to - 850:.\Generated_Source\PSoC5/CyDmac.c **** * 4095 bytes; the TD is not initialized at all when a higher value is passed. - 851:.\Generated_Source\PSoC5/CyDmac.c **** * - 852:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 nextTd: - 853:.\Generated_Source\PSoC5/CyDmac.c **** * Zero based index of the next Transfer Descriptor in the TD chain. Zero is a - 854:.\Generated_Source\PSoC5/CyDmac.c **** * valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. - 855:.\Generated_Source\PSoC5/CyDmac.c **** * DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 33 - - - 856:.\Generated_Source\PSoC5/CyDmac.c **** * further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and - 857:.\Generated_Source\PSoC5/CyDmac.c **** * PSoC 5LP silicons. - 858:.\Generated_Source\PSoC5/CyDmac.c **** * - 859:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 configuration: - 860:.\Generated_Source\PSoC5/CyDmac.c **** * Stores the Bit field of configuration bits. - 861:.\Generated_Source\PSoC5/CyDmac.c **** * - 862:.\Generated_Source\PSoC5/CyDmac.c **** * CY_DMA_TD_SWAP_EN - Perform endian swap - 863:.\Generated_Source\PSoC5/CyDmac.c **** * - 864:.\Generated_Source\PSoC5/CyDmac.c **** * CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes - 865:.\Generated_Source\PSoC5/CyDmac.c **** * - 866:.\Generated_Source\PSoC5/CyDmac.c **** * CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger - 867:.\Generated_Source\PSoC5/CyDmac.c **** * automatically when the current TD completes. - 868:.\Generated_Source\PSoC5/CyDmac.c **** * - 869:.\Generated_Source\PSoC5/CyDmac.c **** * CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq - 870:.\Generated_Source\PSoC5/CyDmac.c **** * input line occurs. The positive edge must occur - 871:.\Generated_Source\PSoC5/CyDmac.c **** * during a burst. That is the only time the DMAC - 872:.\Generated_Source\PSoC5/CyDmac.c **** * will listen for it. - 873:.\Generated_Source\PSoC5/CyDmac.c **** * - 874:.\Generated_Source\PSoC5/CyDmac.c **** * DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will - 875:.\Generated_Source\PSoC5/CyDmac.c **** * generate a pulse. Note that this option is - 876:.\Generated_Source\PSoC5/CyDmac.c **** * instance specific with the instance name followed - 877:.\Generated_Source\PSoC5/CyDmac.c **** * by two underscores. In this example, the instance - 878:.\Generated_Source\PSoC5/CyDmac.c **** * name is DMA. - 879:.\Generated_Source\PSoC5/CyDmac.c **** * - 880:.\Generated_Source\PSoC5/CyDmac.c **** * CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each - 881:.\Generated_Source\PSoC5/CyDmac.c **** * data transaction in the burst. - 882:.\Generated_Source\PSoC5/CyDmac.c **** * - 883:.\Generated_Source\PSoC5/CyDmac.c **** * CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each - 884:.\Generated_Source\PSoC5/CyDmac.c **** * data transaction in the burst. - 885:.\Generated_Source\PSoC5/CyDmac.c **** * - 886:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 887:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 888:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if tdHandle or transferCount is invalid. - 889:.\Generated_Source\PSoC5/CyDmac.c **** * - 890:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 891:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configur - 892:.\Generated_Source\PSoC5/CyDmac.c **** - 893:.\Generated_Source\PSoC5/CyDmac.c **** { - 936 .loc 1 893 0 - 937 .cfi_startproc - 938 @ args = 0, pretend = 0, frame = 0 - 939 @ frame_needed = 0, uses_anonymous_args = 0 - 940 .LVL89: - 894:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 895:.\Generated_Source\PSoC5/CyDmac.c **** - 896:.\Generated_Source\PSoC5/CyDmac.c **** if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount))) - 941 .loc 1 896 0 - 942 0000 10F0800F tst r0, #128 - 893:.\Generated_Source\PSoC5/CyDmac.c **** { - 943 .loc 1 893 0 - 944 0004 30B5 push {r4, r5, lr} - 945 .LCFI6: - 946 .cfi_def_cfa_offset 12 - 947 .cfi_offset 4, -12 - 948 .cfi_offset 5, -8 - 949 .cfi_offset 14, -4 - 950 .loc 1 896 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 34 - - - 951 0006 0CD1 bne .L102 - 952 .loc 1 896 0 is_stmt 0 discriminator 1 - 953 0008 11F47045 ands r5, r1, #61440 - 954 000c 09D1 bne .L102 - 955 .LBB4: - 897:.\Generated_Source\PSoC5/CyDmac.c **** { - 898:.\Generated_Source\PSoC5/CyDmac.c **** /* Set 12 bits transfer count. */ - 899:.\Generated_Source\PSoC5/CyDmac.c **** reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u]; - 956 .loc 1 899 0 is_stmt 1 - 957 000e C400 lsls r4, r0, #3 - 958 0010 04F18040 add r0, r4, #1073741824 - 959 .LVL90: - 960 0014 00F5F044 add r4, r0, #30720 - 961 .LVL91: - 900:.\Generated_Source\PSoC5/CyDmac.c **** CY_SET_REG16(convert, transferCount); - 962 .loc 1 900 0 - 963 0018 2180 strh r1, [r4, #0] @ movhi - 901:.\Generated_Source\PSoC5/CyDmac.c **** - 902:.\Generated_Source\PSoC5/CyDmac.c **** /* Set Next TD pointer. */ - 903:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; - 904:.\Generated_Source\PSoC5/CyDmac.c **** - 905:.\Generated_Source\PSoC5/CyDmac.c **** /* Configure the TD */ - 906:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; - 907:.\Generated_Source\PSoC5/CyDmac.c **** - 908:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 964 .loc 1 908 0 - 965 001a 2846 mov r0, r5 - 903:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; - 966 .loc 1 903 0 - 967 001c A270 strb r2, [r4, #2] - 906:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; - 968 .loc 1 906 0 - 969 001e E370 strb r3, [r4, #3] - 970 .LVL92: - 971 0020 30BD pop {r4, r5, pc} - 972 .LVL93: - 973 .L102: - 974 .LBE4: - 894:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 975 .loc 1 894 0 - 976 0022 0120 movs r0, #1 - 977 .LVL94: - 909:.\Generated_Source\PSoC5/CyDmac.c **** } - 910:.\Generated_Source\PSoC5/CyDmac.c **** - 911:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 912:.\Generated_Source\PSoC5/CyDmac.c **** } - 978 .loc 1 912 0 - 979 0024 30BD pop {r4, r5, pc} - 980 .cfi_endproc - 981 .LFE19: - 982 .size CyDmaTdSetConfiguration, .-CyDmaTdSetConfiguration - 983 .section .text.CyDmaTdGetConfiguration,"ax",%progbits - 984 .align 1 - 985 .global CyDmaTdGetConfiguration - 986 .thumb - 987 .thumb_func - 988 .type CyDmaTdGetConfiguration, %function - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 35 - - - 989 CyDmaTdGetConfiguration: - 990 .LFB20: - 913:.\Generated_Source\PSoC5/CyDmac.c **** - 914:.\Generated_Source\PSoC5/CyDmac.c **** - 915:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 916:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaTdGetConfiguration - 917:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 918:.\Generated_Source\PSoC5/CyDmac.c **** * - 919:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 920:.\Generated_Source\PSoC5/CyDmac.c **** * Retrieves the configuration of the TD. If a NULL pointer is passed as a - 921:.\Generated_Source\PSoC5/CyDmac.c **** * parameter, that parameter is skipped. You may request only the values you are - 922:.\Generated_Source\PSoC5/CyDmac.c **** * interested in. - 923:.\Generated_Source\PSoC5/CyDmac.c **** * - 924:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 925:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdHandle: - 926:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaTdAlloc(). - 927:.\Generated_Source\PSoC5/CyDmac.c **** * - 928:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 * transferCount: - 929:.\Generated_Source\PSoC5/CyDmac.c **** * The address to store the size of the data transfer (in bytes) for this TD. - 930:.\Generated_Source\PSoC5/CyDmac.c **** * A size of zero could indicate that the TD has completed its transfer, or - 931:.\Generated_Source\PSoC5/CyDmac.c **** * that the TD is doing an indefinite transfer. - 932:.\Generated_Source\PSoC5/CyDmac.c **** * - 933:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 * nextTd: - 934:.\Generated_Source\PSoC5/CyDmac.c **** * The address to store the index of the next TD in the TD chain. - 935:.\Generated_Source\PSoC5/CyDmac.c **** * - 936:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 * configuration: - 937:.\Generated_Source\PSoC5/CyDmac.c **** * The address to store the Bit field of configuration bits. - 938:.\Generated_Source\PSoC5/CyDmac.c **** * See CyDmaTdSetConfiguration() function description. - 939:.\Generated_Source\PSoC5/CyDmac.c **** * - 940:.\Generated_Source\PSoC5/CyDmac.c **** * Return: - 941:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. - 942:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if tdHandle is invalid. - 943:.\Generated_Source\PSoC5/CyDmac.c **** * - 944:.\Generated_Source\PSoC5/CyDmac.c **** * Side Effects: - 945:.\Generated_Source\PSoC5/CyDmac.c **** * If a TD has a transfer count of N and is executed, the transfer count becomes - 946:.\Generated_Source\PSoC5/CyDmac.c **** * 0. If it is reexecuted, the Transfer count of zero will be interpreted as a - 947:.\Generated_Source\PSoC5/CyDmac.c **** * request for indefinite transfer. Be careful when requesting a TD with a - 948:.\Generated_Source\PSoC5/CyDmac.c **** * transfer count of zero. - 949:.\Generated_Source\PSoC5/CyDmac.c **** * - 950:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ - 951:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * co - 952:.\Generated_Source\PSoC5/CyDmac.c **** - 953:.\Generated_Source\PSoC5/CyDmac.c **** { - 991 .loc 1 953 0 - 992 .cfi_startproc - 993 @ args = 0, pretend = 0, frame = 0 - 994 @ frame_needed = 0, uses_anonymous_args = 0 - 995 .LVL95: - 954:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 955:.\Generated_Source\PSoC5/CyDmac.c **** - 956:.\Generated_Source\PSoC5/CyDmac.c **** if(tdHandle < CY_DMA_NUMBEROF_TDS) - 996 .loc 1 956 0 - 997 0000 10F0800F tst r0, #128 - 953:.\Generated_Source\PSoC5/CyDmac.c **** { - 998 .loc 1 953 0 - 999 0004 10B5 push {r4, lr} - 1000 .LCFI7: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 36 - - - 1001 .cfi_def_cfa_offset 8 - 1002 .cfi_offset 4, -8 - 1003 .cfi_offset 14, -4 - 1004 .loc 1 956 0 - 1005 0006 1BD1 bne .L107 - 957:.\Generated_Source\PSoC5/CyDmac.c **** { - 958:.\Generated_Source\PSoC5/CyDmac.c **** /* If we have a pointer */ - 959:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != transferCount) - 1006 .loc 1 959 0 - 1007 0008 41B1 cbz r1, .L105 - 1008 .LBB5: - 960:.\Generated_Source\PSoC5/CyDmac.c **** { - 961:.\Generated_Source\PSoC5/CyDmac.c **** /* Get the 12 bits of the transfer count */ - 962:.\Generated_Source\PSoC5/CyDmac.c **** reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0]; - 1009 .loc 1 962 0 - 1010 000a C400 lsls r4, r0, #3 - 1011 000c 04F18044 add r4, r4, #1073741824 - 1012 0010 04F5F044 add r4, r4, #30720 - 1013 .LVL96: - 963:.\Generated_Source\PSoC5/CyDmac.c **** *transferCount = 0x0FFFu & CY_GET_REG16(convert); - 1014 .loc 1 963 0 - 1015 0014 2488 ldrh r4, [r4, #0] - 1016 .LVL97: - 1017 0016 24F47044 bic r4, r4, #61440 - 1018 001a 0C80 strh r4, [r1, #0] @ movhi - 1019 .LVL98: - 1020 .L105: - 1021 .LBE5: - 964:.\Generated_Source\PSoC5/CyDmac.c **** } - 965:.\Generated_Source\PSoC5/CyDmac.c **** - 966:.\Generated_Source\PSoC5/CyDmac.c **** /* If we have a pointer */ - 967:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != nextTd) - 1022 .loc 1 967 0 - 1023 001c 32B1 cbz r2, .L106 - 968:.\Generated_Source\PSoC5/CyDmac.c **** { - 969:.\Generated_Source\PSoC5/CyDmac.c **** /* Get the Next TD pointer */ - 970:.\Generated_Source\PSoC5/CyDmac.c **** *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u]; - 1024 .loc 1 970 0 - 1025 001e C100 lsls r1, r0, #3 - 1026 .LVL99: - 1027 0020 01F18041 add r1, r1, #1073741824 - 1028 0024 01F5F041 add r1, r1, #30720 - 1029 0028 8978 ldrb r1, [r1, #2] @ zero_extendqisi2 - 1030 002a 1170 strb r1, [r2, #0] - 1031 .L106: - 971:.\Generated_Source\PSoC5/CyDmac.c **** } - 972:.\Generated_Source\PSoC5/CyDmac.c **** - 973:.\Generated_Source\PSoC5/CyDmac.c **** /* If we have a pointer */ - 974:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != configuration) - 1032 .loc 1 974 0 - 1033 002c 33B1 cbz r3, .L115 - 975:.\Generated_Source\PSoC5/CyDmac.c **** { - 976:.\Generated_Source\PSoC5/CyDmac.c **** /* Get the configuration the TD */ - 977:.\Generated_Source\PSoC5/CyDmac.c **** *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u]; - 1034 .loc 1 977 0 - 1035 002e C000 lsls r0, r0, #3 - 1036 .LVL100: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 37 - - - 1037 0030 00F18042 add r2, r0, #1073741824 - 1038 .LVL101: - 1039 0034 02F5F041 add r1, r2, #30720 - 1040 0038 C878 ldrb r0, [r1, #3] @ zero_extendqisi2 - 1041 003a 1870 strb r0, [r3, #0] - 1042 .L115: - 978:.\Generated_Source\PSoC5/CyDmac.c **** } - 979:.\Generated_Source\PSoC5/CyDmac.c **** - 980:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 1043 .loc 1 980 0 - 1044 003c 0020 movs r0, #0 - 1045 003e 10BD pop {r4, pc} - 1046 .LVL102: - 1047 .L107: - 954:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 1048 .loc 1 954 0 - 1049 0040 0120 movs r0, #1 - 1050 .LVL103: - 1051 0042 10BD pop {r4, pc} - 1052 .cfi_endproc - 1053 .LFE20: - 1054 .size CyDmaTdGetConfiguration, .-CyDmaTdGetConfiguration - 1055 .section .text.CyDmaTdSetAddress,"ax",%progbits - 1056 .align 1 - 1057 .global CyDmaTdSetAddress - 1058 .thumb - 1059 .thumb_func - 1060 .type CyDmaTdSetAddress, %function - 1061 CyDmaTdSetAddress: - 1062 .LFB21: - 981:.\Generated_Source\PSoC5/CyDmac.c **** } - 982:.\Generated_Source\PSoC5/CyDmac.c **** - 983:.\Generated_Source\PSoC5/CyDmac.c **** return(status); - 984:.\Generated_Source\PSoC5/CyDmac.c **** } - 985:.\Generated_Source\PSoC5/CyDmac.c **** - 986:.\Generated_Source\PSoC5/CyDmac.c **** - 987:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* - 988:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaTdSetAddress - 989:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** - 990:.\Generated_Source\PSoC5/CyDmac.c **** * - 991:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: - 992:.\Generated_Source\PSoC5/CyDmac.c **** * Sets the lower 16 bits of the source and destination addresses for this TD - 993:.\Generated_Source\PSoC5/CyDmac.c **** * only. - 994:.\Generated_Source\PSoC5/CyDmac.c **** * - 995:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: - 996:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdHandle: - 997:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaTdAlloc(). - 998:.\Generated_Source\PSoC5/CyDmac.c **** * - 999:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 source: -1000:.\Generated_Source\PSoC5/CyDmac.c **** * The lower 16 address bits of the source of the data transfer. -1001:.\Generated_Source\PSoC5/CyDmac.c **** * -1002:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 destination: -1003:.\Generated_Source\PSoC5/CyDmac.c **** * The lower 16 address bits of the destination of the data transfer. -1004:.\Generated_Source\PSoC5/CyDmac.c **** * -1005:.\Generated_Source\PSoC5/CyDmac.c **** * Return: -1006:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. -1007:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if tdHandle is invalid. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 38 - - -1008:.\Generated_Source\PSoC5/CyDmac.c **** * -1009:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ -1010:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) -1011:.\Generated_Source\PSoC5/CyDmac.c **** { - 1063 .loc 1 1011 0 - 1064 .cfi_startproc - 1065 @ args = 0, pretend = 0, frame = 0 - 1066 @ frame_needed = 0, uses_anonymous_args = 0 - 1067 @ link register save eliminated. - 1068 .LVL104: -1012:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; -1013:.\Generated_Source\PSoC5/CyDmac.c **** reg16 *convert; -1014:.\Generated_Source\PSoC5/CyDmac.c **** -1015:.\Generated_Source\PSoC5/CyDmac.c **** if(tdHandle < CY_DMA_NUMBEROF_TDS) - 1069 .loc 1 1015 0 - 1070 0000 0306 lsls r3, r0, #24 - 1071 0002 08D4 bmi .L118 -1016:.\Generated_Source\PSoC5/CyDmac.c **** { -1017:.\Generated_Source\PSoC5/CyDmac.c **** /* Set source address */ -1018:.\Generated_Source\PSoC5/CyDmac.c **** convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; - 1072 .loc 1 1018 0 - 1073 0004 C000 lsls r0, r0, #3 - 1074 .LVL105: - 1075 0006 00F18043 add r3, r0, #1073741824 - 1076 000a 03F5F040 add r0, r3, #30720 - 1077 .LVL106: -1019:.\Generated_Source\PSoC5/CyDmac.c **** CY_SET_REG16(convert, source); - 1078 .loc 1 1019 0 - 1079 000e 8180 strh r1, [r0, #4] @ movhi - 1080 .LVL107: -1020:.\Generated_Source\PSoC5/CyDmac.c **** -1021:.\Generated_Source\PSoC5/CyDmac.c **** /* Set destination address */ -1022:.\Generated_Source\PSoC5/CyDmac.c **** convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; -1023:.\Generated_Source\PSoC5/CyDmac.c **** CY_SET_REG16(convert, destination); - 1081 .loc 1 1023 0 - 1082 0010 C280 strh r2, [r0, #6] @ movhi - 1083 .LVL108: -1024:.\Generated_Source\PSoC5/CyDmac.c **** -1025:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 1084 .loc 1 1025 0 - 1085 0012 0020 movs r0, #0 - 1086 .LVL109: - 1087 0014 7047 bx lr - 1088 .LVL110: - 1089 .L118: -1012:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 1090 .loc 1 1012 0 - 1091 0016 0120 movs r0, #1 - 1092 .LVL111: -1026:.\Generated_Source\PSoC5/CyDmac.c **** } -1027:.\Generated_Source\PSoC5/CyDmac.c **** -1028:.\Generated_Source\PSoC5/CyDmac.c **** return(status); -1029:.\Generated_Source\PSoC5/CyDmac.c **** } - 1093 .loc 1 1029 0 - 1094 0018 7047 bx lr - 1095 .cfi_endproc - 1096 .LFE21: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 39 - - - 1097 .size CyDmaTdSetAddress, .-CyDmaTdSetAddress - 1098 .section .text.CyDmaTdGetAddress,"ax",%progbits - 1099 .align 1 - 1100 .global CyDmaTdGetAddress - 1101 .thumb - 1102 .thumb_func - 1103 .type CyDmaTdGetAddress, %function - 1104 CyDmaTdGetAddress: - 1105 .LFB22: -1030:.\Generated_Source\PSoC5/CyDmac.c **** -1031:.\Generated_Source\PSoC5/CyDmac.c **** -1032:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* -1033:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaTdGetAddress -1034:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** -1035:.\Generated_Source\PSoC5/CyDmac.c **** * -1036:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: -1037:.\Generated_Source\PSoC5/CyDmac.c **** * Retrieves the lower 16 bits of the source and/or destination addresses for -1038:.\Generated_Source\PSoC5/CyDmac.c **** * this TD only. If NULL is passed for a pointer parameter, that value is -1039:.\Generated_Source\PSoC5/CyDmac.c **** * skipped. You may request only the values of interest. -1040:.\Generated_Source\PSoC5/CyDmac.c **** * -1041:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: -1042:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 tdHandle: -1043:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaTdAlloc(). -1044:.\Generated_Source\PSoC5/CyDmac.c **** * -1045:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 * source: -1046:.\Generated_Source\PSoC5/CyDmac.c **** * The address to store the lower 16 address bits of the source of the data -1047:.\Generated_Source\PSoC5/CyDmac.c **** * transfer. -1048:.\Generated_Source\PSoC5/CyDmac.c **** * -1049:.\Generated_Source\PSoC5/CyDmac.c **** * uint16 * destination: -1050:.\Generated_Source\PSoC5/CyDmac.c **** * The address to store the lower 16 address bits of the destination of the -1051:.\Generated_Source\PSoC5/CyDmac.c **** * data transfer. -1052:.\Generated_Source\PSoC5/CyDmac.c **** * -1053:.\Generated_Source\PSoC5/CyDmac.c **** * Return: -1054:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. -1055:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if tdHandle is invalid. -1056:.\Generated_Source\PSoC5/CyDmac.c **** * -1057:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ -1058:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) -1059:.\Generated_Source\PSoC5/CyDmac.c **** { - 1106 .loc 1 1059 0 - 1107 .cfi_startproc - 1108 @ args = 0, pretend = 0, frame = 0 - 1109 @ frame_needed = 0, uses_anonymous_args = 0 - 1110 @ link register save eliminated. - 1111 .LVL112: -1060:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; -1061:.\Generated_Source\PSoC5/CyDmac.c **** reg16 *convert; -1062:.\Generated_Source\PSoC5/CyDmac.c **** -1063:.\Generated_Source\PSoC5/CyDmac.c **** if(tdHandle < CY_DMA_NUMBEROF_TDS) - 1112 .loc 1 1063 0 - 1113 0000 0306 lsls r3, r0, #24 - 1114 0002 11D4 bmi .L122 -1064:.\Generated_Source\PSoC5/CyDmac.c **** { -1065:.\Generated_Source\PSoC5/CyDmac.c **** /* If we have a pointer. */ -1066:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != source) - 1115 .loc 1 1066 0 - 1116 0004 31B1 cbz r1, .L121 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 40 - - -1067:.\Generated_Source\PSoC5/CyDmac.c **** { -1068:.\Generated_Source\PSoC5/CyDmac.c **** /* Get source address */ -1069:.\Generated_Source\PSoC5/CyDmac.c **** convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; - 1117 .loc 1 1069 0 - 1118 0006 C300 lsls r3, r0, #3 - 1119 0008 03F18043 add r3, r3, #1073741824 - 1120 000c 03F5F043 add r3, r3, #30720 - 1121 .LVL113: -1070:.\Generated_Source\PSoC5/CyDmac.c **** *source = CY_GET_REG16(convert); - 1122 .loc 1 1070 0 - 1123 0010 9B88 ldrh r3, [r3, #4] - 1124 .LVL114: - 1125 0012 0B80 strh r3, [r1, #0] @ movhi - 1126 .LVL115: - 1127 .L121: -1071:.\Generated_Source\PSoC5/CyDmac.c **** } -1072:.\Generated_Source\PSoC5/CyDmac.c **** -1073:.\Generated_Source\PSoC5/CyDmac.c **** /* If we have a pointer. */ -1074:.\Generated_Source\PSoC5/CyDmac.c **** if(NULL != destination) - 1128 .loc 1 1074 0 - 1129 0014 32B1 cbz r2, .L127 -1075:.\Generated_Source\PSoC5/CyDmac.c **** { -1076:.\Generated_Source\PSoC5/CyDmac.c **** /* Get Destination address. */ -1077:.\Generated_Source\PSoC5/CyDmac.c **** convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; - 1130 .loc 1 1077 0 - 1131 0016 C000 lsls r0, r0, #3 - 1132 .LVL116: - 1133 0018 00F18041 add r1, r0, #1073741824 - 1134 .LVL117: - 1135 001c 01F5F043 add r3, r1, #30720 - 1136 .LVL118: -1078:.\Generated_Source\PSoC5/CyDmac.c **** *destination = CY_GET_REG16(convert); - 1137 .loc 1 1078 0 - 1138 0020 D888 ldrh r0, [r3, #6] - 1139 0022 1080 strh r0, [r2, #0] @ movhi - 1140 .LVL119: - 1141 .L127: -1079:.\Generated_Source\PSoC5/CyDmac.c **** } -1080:.\Generated_Source\PSoC5/CyDmac.c **** -1081:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 1142 .loc 1 1081 0 - 1143 0024 0020 movs r0, #0 - 1144 0026 7047 bx lr - 1145 .LVL120: - 1146 .L122: -1060:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 1147 .loc 1 1060 0 - 1148 0028 0120 movs r0, #1 - 1149 .LVL121: - 1150 002a 7047 bx lr - 1151 .cfi_endproc - 1152 .LFE22: - 1153 .size CyDmaTdGetAddress, .-CyDmaTdGetAddress - 1154 .section .text.CyDmaChRoundRobin,"ax",%progbits - 1155 .align 1 - 1156 .global CyDmaChRoundRobin - 1157 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 41 - - - 1158 .thumb_func - 1159 .type CyDmaChRoundRobin, %function - 1160 CyDmaChRoundRobin: - 1161 .LFB23: -1082:.\Generated_Source\PSoC5/CyDmac.c **** } -1083:.\Generated_Source\PSoC5/CyDmac.c **** -1084:.\Generated_Source\PSoC5/CyDmac.c **** return(status); -1085:.\Generated_Source\PSoC5/CyDmac.c **** } -1086:.\Generated_Source\PSoC5/CyDmac.c **** -1087:.\Generated_Source\PSoC5/CyDmac.c **** -1088:.\Generated_Source\PSoC5/CyDmac.c **** /******************************************************************************* -1089:.\Generated_Source\PSoC5/CyDmac.c **** * Function Name: CyDmaChRoundRobin -1090:.\Generated_Source\PSoC5/CyDmac.c **** ******************************************************************************** -1091:.\Generated_Source\PSoC5/CyDmac.c **** * -1092:.\Generated_Source\PSoC5/CyDmac.c **** * Summary: -1093:.\Generated_Source\PSoC5/CyDmac.c **** * Either enables or disables the Round-Robin scheduling enforcement algorithm. -1094:.\Generated_Source\PSoC5/CyDmac.c **** * Within a priority level a Round-Robin fairness algorithm is enforced. -1095:.\Generated_Source\PSoC5/CyDmac.c **** * -1096:.\Generated_Source\PSoC5/CyDmac.c **** * Parameters: -1097:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 chHandle: -1098:.\Generated_Source\PSoC5/CyDmac.c **** * A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). -1099:.\Generated_Source\PSoC5/CyDmac.c **** * -1100:.\Generated_Source\PSoC5/CyDmac.c **** * uint8 enableRR: -1101:.\Generated_Source\PSoC5/CyDmac.c **** * 0: Disable Round-Robin fairness algorithm -1102:.\Generated_Source\PSoC5/CyDmac.c **** * 1: Enable Round-Robin fairness algorithm -1103:.\Generated_Source\PSoC5/CyDmac.c **** * -1104:.\Generated_Source\PSoC5/CyDmac.c **** * Return: -1105:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_SUCCESS if successful. -1106:.\Generated_Source\PSoC5/CyDmac.c **** * CYRET_BAD_PARAM if chHandle is invalid. -1107:.\Generated_Source\PSoC5/CyDmac.c **** * -1108:.\Generated_Source\PSoC5/CyDmac.c **** *******************************************************************************/ -1109:.\Generated_Source\PSoC5/CyDmac.c **** cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) -1110:.\Generated_Source\PSoC5/CyDmac.c **** { - 1162 .loc 1 1110 0 - 1163 .cfi_startproc - 1164 @ args = 0, pretend = 0, frame = 0 - 1165 @ frame_needed = 0, uses_anonymous_args = 0 - 1166 @ link register save eliminated. - 1167 .LVL122: -1111:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; -1112:.\Generated_Source\PSoC5/CyDmac.c **** -1113:.\Generated_Source\PSoC5/CyDmac.c **** if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - 1168 .loc 1 1113 0 - 1169 0000 1728 cmp r0, #23 - 1170 0002 0DD8 bhi .L131 - 1171 0004 0201 lsls r2, r0, #4 - 1172 0006 074B ldr r3, .L133 -1114:.\Generated_Source\PSoC5/CyDmac.c **** { -1115:.\Generated_Source\PSoC5/CyDmac.c **** if (0u != enableRR) - 1173 .loc 1 1115 0 - 1174 0008 29B1 cbz r1, .L130 -1116:.\Generated_Source\PSoC5/CyDmac.c **** { -1117:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE; - 1175 .loc 1 1117 0 - 1176 000a D05C ldrb r0, [r2, r3] @ zero_extendqisi2 - 1177 .LVL123: - 1178 000c 40F01001 orr r1, r0, #16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 42 - - - 1179 .LVL124: - 1180 0010 D154 strb r1, [r2, r3] - 1181 .L132: -1118:.\Generated_Source\PSoC5/CyDmac.c **** } -1119:.\Generated_Source\PSoC5/CyDmac.c **** else -1120:.\Generated_Source\PSoC5/CyDmac.c **** { -1121:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE); -1122:.\Generated_Source\PSoC5/CyDmac.c **** } -1123:.\Generated_Source\PSoC5/CyDmac.c **** -1124:.\Generated_Source\PSoC5/CyDmac.c **** status = CYRET_SUCCESS; - 1182 .loc 1 1124 0 - 1183 0012 0020 movs r0, #0 - 1184 0014 7047 bx lr - 1185 .LVL125: - 1186 .L130: -1121:.\Generated_Source\PSoC5/CyDmac.c **** CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE); - 1187 .loc 1 1121 0 - 1188 0016 D05C ldrb r0, [r2, r3] @ zero_extendqisi2 - 1189 .LVL126: - 1190 0018 00F0EF01 and r1, r0, #239 - 1191 .LVL127: - 1192 001c D154 strb r1, [r2, r3] - 1193 001e F8E7 b .L132 - 1194 .LVL128: - 1195 .L131: -1111:.\Generated_Source\PSoC5/CyDmac.c **** cystatus status = CYRET_BAD_PARAM; - 1196 .loc 1 1111 0 - 1197 0020 0120 movs r0, #1 - 1198 .LVL129: -1125:.\Generated_Source\PSoC5/CyDmac.c **** } -1126:.\Generated_Source\PSoC5/CyDmac.c **** -1127:.\Generated_Source\PSoC5/CyDmac.c **** return(status); -1128:.\Generated_Source\PSoC5/CyDmac.c **** } - 1199 .loc 1 1128 0 - 1200 0022 7047 bx lr - 1201 .L134: - 1202 .align 2 - 1203 .L133: - 1204 0024 10700040 .word 1073770512 - 1205 .cfi_endproc - 1206 .LFE23: - 1207 .size CyDmaChRoundRobin, .-CyDmaChRoundRobin - 1208 .data - 1209 .set .LANCHOR0,. + 0 - 1210 .type CyDmaTdFreeIndex, %object - 1211 .size CyDmaTdFreeIndex, 1 - 1212 CyDmaTdFreeIndex: - 1213 0000 7F .byte 127 - 1214 .type CyDmaTdCurrentNumber, %object - 1215 .size CyDmaTdCurrentNumber, 1 - 1216 CyDmaTdCurrentNumber: - 1217 0001 80 .byte -128 - 1218 .bss - 1219 .align 2 - 1220 .set .LANCHOR1,. + 0 - 1221 .type CyDmaChannels, %object - 1222 .size CyDmaChannels, 4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 43 - - - 1223 CyDmaChannels: - 1224 0000 00000000 .space 4 - 1225 .text - 1226 .Letext0: - 1227 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 1228 .file 3 ".\\Generated_Source\\PSoC5\\CyDmac.h" - 1229 .file 4 ".\\Generated_Source\\PSoC5\\CyLib.h" - 1230 .section .debug_info,"",%progbits - 1231 .Ldebug_info0: - 1232 0000 B4090000 .4byte 0x9b4 - 1233 0004 0200 .2byte 0x2 - 1234 0006 00000000 .4byte .Ldebug_abbrev0 - 1235 000a 04 .byte 0x4 - 1236 000b 01 .uleb128 0x1 - 1237 000c 0B030000 .4byte .LASF85 - 1238 0010 01 .byte 0x1 - 1239 0011 AE010000 .4byte .LASF86 - 1240 0015 5E020000 .4byte .LASF87 - 1241 0019 18000000 .4byte .Ldebug_ranges0+0x18 - 1242 001d 00000000 .4byte 0 - 1243 0021 00000000 .4byte 0 - 1244 0025 00000000 .4byte .Ldebug_line0 - 1245 0029 02 .uleb128 0x2 - 1246 002a 01 .byte 0x1 - 1247 002b 06 .byte 0x6 - 1248 002c CD000000 .4byte .LASF0 - 1249 0030 02 .uleb128 0x2 - 1250 0031 01 .byte 0x1 - 1251 0032 08 .byte 0x8 - 1252 0033 94030000 .4byte .LASF1 - 1253 0037 02 .uleb128 0x2 - 1254 0038 02 .byte 0x2 - 1255 0039 05 .byte 0x5 - 1256 003a A2030000 .4byte .LASF2 - 1257 003e 02 .uleb128 0x2 - 1258 003f 02 .byte 0x2 - 1259 0040 07 .byte 0x7 - 1260 0041 09020000 .4byte .LASF3 - 1261 0045 02 .uleb128 0x2 - 1262 0046 04 .byte 0x4 - 1263 0047 05 .byte 0x5 - 1264 0048 09010000 .4byte .LASF4 - 1265 004c 02 .uleb128 0x2 - 1266 004d 04 .byte 0x4 - 1267 004e 07 .byte 0x7 - 1268 004f 89010000 .4byte .LASF5 - 1269 0053 02 .uleb128 0x2 - 1270 0054 08 .byte 0x8 - 1271 0055 05 .byte 0x5 - 1272 0056 BF000000 .4byte .LASF6 - 1273 005a 02 .uleb128 0x2 - 1274 005b 08 .byte 0x8 - 1275 005c 07 .byte 0x7 - 1276 005d 87000000 .4byte .LASF7 - 1277 0061 03 .uleb128 0x3 - 1278 0062 04 .byte 0x4 - 1279 0063 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 44 - - - 1280 0064 696E7400 .ascii "int\000" - 1281 0068 02 .uleb128 0x2 - 1282 0069 04 .byte 0x4 - 1283 006a 07 .byte 0x7 - 1284 006b 7C010000 .4byte .LASF8 - 1285 006f 04 .uleb128 0x4 - 1286 0070 28010000 .4byte .LASF9 - 1287 0074 02 .byte 0x2 - 1288 0075 5B .byte 0x5b - 1289 0076 30000000 .4byte 0x30 - 1290 007a 04 .uleb128 0x4 - 1291 007b 00000000 .4byte .LASF10 - 1292 007f 02 .byte 0x2 - 1293 0080 5C .byte 0x5c - 1294 0081 3E000000 .4byte 0x3e - 1295 0085 04 .uleb128 0x4 - 1296 0086 43010000 .4byte .LASF11 - 1297 008a 02 .byte 0x2 - 1298 008b 5D .byte 0x5d - 1299 008c 4C000000 .4byte 0x4c - 1300 0090 02 .uleb128 0x2 - 1301 0091 04 .byte 0x4 - 1302 0092 04 .byte 0x4 - 1303 0093 FF020000 .4byte .LASF12 - 1304 0097 02 .uleb128 0x2 - 1305 0098 08 .byte 0x8 - 1306 0099 04 .byte 0x4 - 1307 009a 2E010000 .4byte .LASF13 - 1308 009e 02 .uleb128 0x2 - 1309 009f 01 .byte 0x1 - 1310 00a0 08 .byte 0x8 - 1311 00a1 F8030000 .4byte .LASF14 - 1312 00a5 04 .uleb128 0x4 - 1313 00a6 B5040000 .4byte .LASF15 - 1314 00aa 02 .byte 0x2 - 1315 00ab E8 .byte 0xe8 - 1316 00ac 4C000000 .4byte 0x4c - 1317 00b0 04 .uleb128 0x4 - 1318 00b1 22010000 .4byte .LASF16 - 1319 00b5 02 .byte 0x2 - 1320 00b6 F1 .byte 0xf1 - 1321 00b7 BB000000 .4byte 0xbb - 1322 00bb 05 .uleb128 0x5 - 1323 00bc 7A000000 .4byte 0x7a - 1324 00c0 04 .uleb128 0x4 - 1325 00c1 8F020000 .4byte .LASF17 - 1326 00c5 02 .byte 0x2 - 1327 00c6 F2 .byte 0xf2 - 1328 00c7 CB000000 .4byte 0xcb - 1329 00cb 05 .uleb128 0x5 - 1330 00cc 85000000 .4byte 0x85 - 1331 00d0 02 .uleb128 0x2 - 1332 00d1 04 .byte 0x4 - 1333 00d2 07 .byte 0x7 - 1334 00d3 A9020000 .4byte .LASF18 - 1335 00d7 06 .uleb128 0x6 - 1336 00d8 85030000 .4byte .LASF24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 45 - - - 1337 00dc 10 .byte 0x10 - 1338 00dd 03 .byte 0x3 - 1339 00de 48 .byte 0x48 - 1340 00df 1C010000 .4byte 0x11c - 1341 00e3 07 .uleb128 0x7 - 1342 00e4 FF010000 .4byte .LASF19 - 1343 00e8 03 .byte 0x3 - 1344 00e9 4A .byte 0x4a - 1345 00ea 2C010000 .4byte 0x12c - 1346 00ee 02 .byte 0x2 - 1347 00ef 23 .byte 0x23 - 1348 00f0 00 .uleb128 0 - 1349 00f1 07 .uleb128 0x7 - 1350 00f2 4A010000 .4byte .LASF20 - 1351 00f6 03 .byte 0x3 - 1352 00f7 4B .byte 0x4b - 1353 00f8 31010000 .4byte 0x131 - 1354 00fc 02 .byte 0x2 - 1355 00fd 23 .byte 0x23 - 1356 00fe 04 .uleb128 0x4 - 1357 00ff 07 .uleb128 0x7 - 1358 0100 9C020000 .4byte .LASF21 - 1359 0104 03 .byte 0x3 - 1360 0105 4C .byte 0x4c - 1361 0106 36010000 .4byte 0x136 - 1362 010a 02 .byte 0x2 - 1363 010b 23 .byte 0x23 - 1364 010c 08 .uleb128 0x8 - 1365 010d 07 .uleb128 0x7 - 1366 010e 51010000 .4byte .LASF22 - 1367 0112 03 .byte 0x3 - 1368 0113 4D .byte 0x4d - 1369 0114 3B010000 .4byte 0x13b - 1370 0118 02 .byte 0x2 - 1371 0119 23 .byte 0x23 - 1372 011a 0C .uleb128 0xc - 1373 011b 00 .byte 0 - 1374 011c 08 .uleb128 0x8 - 1375 011d 6F000000 .4byte 0x6f - 1376 0121 2C010000 .4byte 0x12c - 1377 0125 09 .uleb128 0x9 - 1378 0126 D0000000 .4byte 0xd0 - 1379 012a 03 .byte 0x3 - 1380 012b 00 .byte 0 - 1381 012c 05 .uleb128 0x5 - 1382 012d 1C010000 .4byte 0x11c - 1383 0131 05 .uleb128 0x5 - 1384 0132 1C010000 .4byte 0x11c - 1385 0136 05 .uleb128 0x5 - 1386 0137 1C010000 .4byte 0x11c - 1387 013b 05 .uleb128 0x5 - 1388 013c 1C010000 .4byte 0x11c - 1389 0140 04 .uleb128 0x4 - 1390 0141 18040000 .4byte .LASF23 - 1391 0145 03 .byte 0x3 - 1392 0146 4F .byte 0x4f - 1393 0147 D7000000 .4byte 0xd7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 46 - - - 1394 014b 06 .uleb128 0x6 - 1395 014c 9B010000 .4byte .LASF25 - 1396 0150 08 .byte 0x8 - 1397 0151 03 .byte 0x3 - 1398 0152 52 .byte 0x52 - 1399 0153 74010000 .4byte 0x174 - 1400 0157 07 .uleb128 0x7 - 1401 0158 76040000 .4byte .LASF26 - 1402 015c 03 .byte 0x3 - 1403 015d 54 .byte 0x54 - 1404 015e 74010000 .4byte 0x174 - 1405 0162 02 .byte 0x2 - 1406 0163 23 .byte 0x23 - 1407 0164 00 .uleb128 0 - 1408 0165 07 .uleb128 0x7 - 1409 0166 7B040000 .4byte .LASF27 - 1410 016a 03 .byte 0x3 - 1411 016b 55 .byte 0x55 - 1412 016c 79010000 .4byte 0x179 - 1413 0170 02 .byte 0x2 - 1414 0171 23 .byte 0x23 - 1415 0172 04 .uleb128 0x4 - 1416 0173 00 .byte 0 - 1417 0174 05 .uleb128 0x5 - 1418 0175 1C010000 .4byte 0x11c - 1419 0179 05 .uleb128 0x5 - 1420 017a 1C010000 .4byte 0x11c - 1421 017e 04 .uleb128 0x4 - 1422 017f 1D000000 .4byte .LASF28 - 1423 0183 03 .byte 0x3 - 1424 0184 57 .byte 0x57 - 1425 0185 4B010000 .4byte 0x14b - 1426 0189 06 .uleb128 0x6 - 1427 018a F1000000 .4byte .LASF29 - 1428 018e 08 .byte 0x8 - 1429 018f 03 .byte 0x3 - 1430 0190 5A .byte 0x5a - 1431 0191 B2010000 .4byte 0x1b2 - 1432 0195 0A .uleb128 0xa - 1433 0196 54443000 .ascii "TD0\000" - 1434 019a 03 .byte 0x3 - 1435 019b 5C .byte 0x5c - 1436 019c B2010000 .4byte 0x1b2 - 1437 01a0 02 .byte 0x2 - 1438 01a1 23 .byte 0x23 - 1439 01a2 00 .uleb128 0 - 1440 01a3 0A .uleb128 0xa - 1441 01a4 54443100 .ascii "TD1\000" - 1442 01a8 03 .byte 0x3 - 1443 01a9 5D .byte 0x5d - 1444 01aa B7010000 .4byte 0x1b7 - 1445 01ae 02 .byte 0x2 - 1446 01af 23 .byte 0x23 - 1447 01b0 04 .uleb128 0x4 - 1448 01b1 00 .byte 0 - 1449 01b2 05 .uleb128 0x5 - 1450 01b3 1C010000 .4byte 0x11c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 47 - - - 1451 01b7 05 .uleb128 0x5 - 1452 01b8 1C010000 .4byte 0x11c - 1453 01bc 04 .uleb128 0x4 - 1454 01bd 44040000 .4byte .LASF30 - 1455 01c1 03 .byte 0x3 - 1456 01c2 5F .byte 0x5f - 1457 01c3 89010000 .4byte 0x189 - 1458 01c7 0B .uleb128 0xb - 1459 01c8 01 .byte 0x1 - 1460 01c9 77000000 .4byte .LASF31 - 1461 01cd 01 .byte 0x1 - 1462 01ce 3D .byte 0x3d - 1463 01cf 01 .byte 0x1 - 1464 01d0 00000000 .4byte .LFB0 - 1465 01d4 30000000 .4byte .LFE0 - 1466 01d8 02 .byte 0x2 - 1467 01d9 7D .byte 0x7d - 1468 01da 00 .sleb128 0 - 1469 01db 01 .byte 0x1 - 1470 01dc F0010000 .4byte 0x1f0 - 1471 01e0 0C .uleb128 0xc - 1472 01e1 D6020000 .4byte .LASF35 - 1473 01e5 01 .byte 0x1 - 1474 01e6 3F .byte 0x3f - 1475 01e7 6F000000 .4byte 0x6f - 1476 01eb 00000000 .4byte .LLST0 - 1477 01ef 00 .byte 0 - 1478 01f0 0D .uleb128 0xd - 1479 01f1 01 .byte 0x1 - 1480 01f2 2A020000 .4byte .LASF33 - 1481 01f6 01 .byte 0x1 - 1482 01f7 6D .byte 0x6d - 1483 01f8 01 .byte 0x1 - 1484 01f9 6F000000 .4byte 0x6f - 1485 01fd 00000000 .4byte .LFB1 - 1486 0201 10000000 .4byte .LFE1 - 1487 0205 02 .byte 0x2 - 1488 0206 7D .byte 0x7d - 1489 0207 00 .sleb128 0 - 1490 0208 01 .byte 0x1 - 1491 0209 0B .uleb128 0xb - 1492 020a 01 .byte 0x1 - 1493 020b 4D020000 .4byte .LASF32 - 1494 020f 01 .byte 0x1 - 1495 0210 91 .byte 0x91 - 1496 0211 01 .byte 0x1 - 1497 0212 00000000 .4byte .LFB2 - 1498 0216 10000000 .4byte .LFE2 - 1499 021a 02 .byte 0x2 - 1500 021b 7D .byte 0x7d - 1501 021c 00 .sleb128 0 - 1502 021d 01 .byte 0x1 - 1503 021e 32020000 .4byte 0x232 - 1504 0222 0E .uleb128 0xe - 1505 0223 05030000 .4byte .LASF40 - 1506 0227 01 .byte 0x1 - 1507 0228 91 .byte 0x91 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 48 - - - 1508 0229 6F000000 .4byte 0x6f - 1509 022d 15000000 .4byte .LLST1 - 1510 0231 00 .byte 0 - 1511 0232 0D .uleb128 0xd - 1512 0233 01 .byte 0x1 - 1513 0234 29000000 .4byte .LASF34 - 1514 0238 01 .byte 0x1 - 1515 0239 A9 .byte 0xa9 - 1516 023a 01 .byte 0x1 - 1517 023b 85000000 .4byte 0x85 - 1518 023f 00000000 .4byte .LFB3 - 1519 0243 0C000000 .4byte .LFE3 - 1520 0247 02 .byte 0x2 - 1521 0248 7D .byte 0x7d - 1522 0249 00 .sleb128 0 - 1523 024a 01 .byte 0x1 - 1524 024b 0F .uleb128 0xf - 1525 024c 01 .byte 0x1 - 1526 024d E1030000 .4byte .LASF38 - 1527 0251 01 .byte 0x1 - 1528 0252 BF .byte 0xbf - 1529 0253 01 .byte 0x1 - 1530 0254 6F000000 .4byte 0x6f - 1531 0258 00000000 .4byte .LFB4 - 1532 025c 34000000 .4byte .LFE4 - 1533 0260 36000000 .4byte .LLST2 - 1534 0264 01 .byte 0x1 - 1535 0265 A9020000 .4byte 0x2a9 - 1536 0269 0C .uleb128 0xc - 1537 026a D9000000 .4byte .LASF36 - 1538 026e 01 .byte 0x1 - 1539 026f C1 .byte 0xc1 - 1540 0270 6F000000 .4byte 0x6f - 1541 0274 56000000 .4byte .LLST3 - 1542 0278 0C .uleb128 0xc - 1543 0279 D6020000 .4byte .LASF35 - 1544 027d 01 .byte 0x1 - 1545 027e C2 .byte 0xc2 - 1546 027f 6F000000 .4byte 0x6f - 1547 0283 69000000 .4byte .LLST4 - 1548 0287 0C .uleb128 0xc - 1549 0288 BC030000 .4byte .LASF37 - 1550 028c 01 .byte 0x1 - 1551 028d C3 .byte 0xc3 - 1552 028e 85000000 .4byte 0x85 - 1553 0292 88000000 .4byte .LLST5 - 1554 0296 10 .uleb128 0x10 - 1555 0297 06000000 .4byte .LVL5 - 1556 029b 99090000 .4byte 0x999 - 1557 029f 10 .uleb128 0x10 - 1558 02a0 2C000000 .4byte .LVL9 - 1559 02a4 A7090000 .4byte 0x9a7 - 1560 02a8 00 .byte 0 - 1561 02a9 0F .uleb128 0xf - 1562 02aa 01 .byte 0x1 - 1563 02ab DE040000 .4byte .LASF39 - 1564 02af 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 49 - - - 1565 02b0 F2 .byte 0xf2 - 1566 02b1 01 .byte 0x1 - 1567 02b2 A5000000 .4byte 0xa5 - 1568 02b6 00000000 .4byte .LFB5 - 1569 02ba 30000000 .4byte .LFE5 - 1570 02be A7000000 .4byte .LLST6 - 1571 02c2 01 .byte 0x1 - 1572 02c3 07030000 .4byte 0x307 - 1573 02c7 0E .uleb128 0xe - 1574 02c8 B3030000 .4byte .LASF41 - 1575 02cc 01 .byte 0x1 - 1576 02cd F2 .byte 0xf2 - 1577 02ce 6F000000 .4byte 0x6f - 1578 02d2 C7000000 .4byte .LLST7 - 1579 02d6 0C .uleb128 0xc - 1580 02d7 80040000 .4byte .LASF42 - 1581 02db 01 .byte 0x1 - 1582 02dc F4 .byte 0xf4 - 1583 02dd A5000000 .4byte 0xa5 - 1584 02e1 01010000 .4byte .LLST8 - 1585 02e5 0C .uleb128 0xc - 1586 02e6 D9000000 .4byte .LASF36 - 1587 02ea 01 .byte 0x1 - 1588 02eb F5 .byte 0xf5 - 1589 02ec 6F000000 .4byte 0x6f - 1590 02f0 38010000 .4byte .LLST9 - 1591 02f4 10 .uleb128 0x10 - 1592 02f5 14000000 .4byte .LVL11 - 1593 02f9 99090000 .4byte 0x999 - 1594 02fd 10 .uleb128 0x10 - 1595 02fe 22000000 .4byte .LVL12 - 1596 0302 A7090000 .4byte 0x9a7 - 1597 0306 00 .byte 0 - 1598 0307 11 .uleb128 0x11 - 1599 0308 01 .byte 0x1 - 1600 0309 58000000 .4byte .LASF43 - 1601 030d 01 .byte 0x1 - 1602 030e 3001 .2byte 0x130 - 1603 0310 01 .byte 0x1 - 1604 0311 A5000000 .4byte 0xa5 - 1605 0315 00000000 .4byte .LFB6 - 1606 0319 34000000 .4byte .LFE6 - 1607 031d 02 .byte 0x2 - 1608 031e 7D .byte 0x7d - 1609 031f 00 .sleb128 0 - 1610 0320 01 .byte 0x1 - 1611 0321 56030000 .4byte 0x356 - 1612 0325 12 .uleb128 0x12 - 1613 0326 B3030000 .4byte .LASF41 - 1614 032a 01 .byte 0x1 - 1615 032b 3001 .2byte 0x130 - 1616 032d 6F000000 .4byte 0x6f - 1617 0331 4B010000 .4byte .LLST10 - 1618 0335 12 .uleb128 0x12 - 1619 0336 30040000 .4byte .LASF44 - 1620 033a 01 .byte 0x1 - 1621 033b 3001 .2byte 0x130 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 50 - - - 1622 033d 6F000000 .4byte 0x6f - 1623 0341 85010000 .4byte .LLST11 - 1624 0345 13 .uleb128 0x13 - 1625 0346 80040000 .4byte .LASF42 - 1626 034a 01 .byte 0x1 - 1627 034b 3201 .2byte 0x132 - 1628 034d A5000000 .4byte 0xa5 - 1629 0351 CA010000 .4byte .LLST12 - 1630 0355 00 .byte 0 - 1631 0356 11 .uleb128 0x11 - 1632 0357 01 .byte 0x1 - 1633 0358 D2030000 .4byte .LASF45 - 1634 035c 01 .byte 0x1 - 1635 035d 6201 .2byte 0x162 - 1636 035f 01 .byte 0x1 - 1637 0360 A5000000 .4byte 0xa5 - 1638 0364 00000000 .4byte .LFB7 - 1639 0368 24000000 .4byte .LFE7 - 1640 036c 02 .byte 0x2 - 1641 036d 7D .byte 0x7d - 1642 036e 00 .sleb128 0 - 1643 036f 01 .byte 0x1 - 1644 0370 95030000 .4byte 0x395 - 1645 0374 12 .uleb128 0x12 - 1646 0375 B3030000 .4byte .LASF41 - 1647 0379 01 .byte 0x1 - 1648 037a 6201 .2byte 0x162 - 1649 037c 6F000000 .4byte 0x6f - 1650 0380 01020000 .4byte .LLST13 - 1651 0384 13 .uleb128 0x13 - 1652 0385 80040000 .4byte .LASF42 - 1653 0389 01 .byte 0x1 - 1654 038a 6401 .2byte 0x164 - 1655 038c A5000000 .4byte 0xa5 - 1656 0390 3B020000 .4byte .LLST14 - 1657 0394 00 .byte 0 - 1658 0395 11 .uleb128 0x11 - 1659 0396 01 .byte 0x1 - 1660 0397 DF020000 .4byte .LASF46 - 1661 039b 01 .byte 0x1 - 1662 039c 8901 .2byte 0x189 - 1663 039e 01 .byte 0x1 - 1664 039f A5000000 .4byte 0xa5 - 1665 03a3 00000000 .4byte .LFB8 - 1666 03a7 28000000 .4byte .LFE8 - 1667 03ab 02 .byte 0x2 - 1668 03ac 7D .byte 0x7d - 1669 03ad 00 .sleb128 0 - 1670 03ae 01 .byte 0x1 - 1671 03af D4030000 .4byte 0x3d4 - 1672 03b3 12 .uleb128 0x12 - 1673 03b4 B3030000 .4byte .LASF41 - 1674 03b8 01 .byte 0x1 - 1675 03b9 8901 .2byte 0x189 - 1676 03bb 6F000000 .4byte 0x6f - 1677 03bf 72020000 .4byte .LLST15 - 1678 03c3 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 51 - - - 1679 03c4 80040000 .4byte .LASF42 - 1680 03c8 01 .byte 0x1 - 1681 03c9 8B01 .2byte 0x18b - 1682 03cb A5000000 .4byte 0xa5 - 1683 03cf AC020000 .4byte .LLST16 - 1684 03d3 00 .byte 0 - 1685 03d4 11 .uleb128 0x11 - 1686 03d5 01 .byte 0x1 - 1687 03d6 6C010000 .4byte .LASF47 - 1688 03da 01 .byte 0x1 - 1689 03db AD01 .2byte 0x1ad - 1690 03dd 01 .byte 0x1 - 1691 03de A5000000 .4byte 0xa5 - 1692 03e2 00000000 .4byte .LFB9 - 1693 03e6 24000000 .4byte .LFE9 - 1694 03ea 02 .byte 0x2 - 1695 03eb 7D .byte 0x7d - 1696 03ec 00 .sleb128 0 - 1697 03ed 01 .byte 0x1 - 1698 03ee 33040000 .4byte 0x433 - 1699 03f2 12 .uleb128 0x12 - 1700 03f3 B3030000 .4byte .LASF41 - 1701 03f7 01 .byte 0x1 - 1702 03f8 AD01 .2byte 0x1ad - 1703 03fa 6F000000 .4byte 0x6f - 1704 03fe E3020000 .4byte .LLST17 - 1705 0402 12 .uleb128 0x12 - 1706 0403 FD030000 .4byte .LASF48 - 1707 0407 01 .byte 0x1 - 1708 0408 AD01 .2byte 0x1ad - 1709 040a 6F000000 .4byte 0x6f - 1710 040e 1D030000 .4byte .LLST18 - 1711 0412 13 .uleb128 0x13 - 1712 0413 5A010000 .4byte .LASF49 - 1713 0417 01 .byte 0x1 - 1714 0418 AF01 .2byte 0x1af - 1715 041a 6F000000 .4byte 0x6f - 1716 041e 49030000 .4byte .LLST19 - 1717 0422 13 .uleb128 0x13 - 1718 0423 80040000 .4byte .LASF42 - 1719 0427 01 .byte 0x1 - 1720 0428 B001 .2byte 0x1b0 - 1721 042a A5000000 .4byte 0xa5 - 1722 042e 61030000 .4byte .LLST20 - 1723 0432 00 .byte 0 - 1724 0433 11 .uleb128 0x11 - 1725 0434 01 .byte 0x1 - 1726 0435 D0010000 .4byte .LASF50 - 1727 0439 01 .byte 0x1 - 1728 043a D601 .2byte 0x1d6 - 1729 043c 01 .byte 0x1 - 1730 043d A5000000 .4byte 0xa5 - 1731 0441 00000000 .4byte .LFB10 - 1732 0445 2E000000 .4byte .LFE10 - 1733 0449 02 .byte 0x2 - 1734 044a 7D .byte 0x7d - 1735 044b 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 52 - - - 1736 044c 01 .byte 0x1 - 1737 044d A2040000 .4byte 0x4a2 - 1738 0451 12 .uleb128 0x12 - 1739 0452 B3030000 .4byte .LASF41 - 1740 0456 01 .byte 0x1 - 1741 0457 D601 .2byte 0x1d6 - 1742 0459 6F000000 .4byte 0x6f - 1743 045d 98030000 .4byte .LLST21 - 1744 0461 12 .uleb128 0x12 - 1745 0462 95020000 .4byte .LASF51 - 1746 0466 01 .byte 0x1 - 1747 0467 D601 .2byte 0x1d6 - 1748 0469 7A000000 .4byte 0x7a - 1749 046d D2030000 .4byte .LLST22 - 1750 0471 12 .uleb128 0x12 - 1751 0472 60010000 .4byte .LASF52 - 1752 0476 01 .byte 0x1 - 1753 0477 D601 .2byte 0x1d6 - 1754 0479 7A000000 .4byte 0x7a - 1755 047d E5030000 .4byte .LLST23 - 1756 0481 13 .uleb128 0x13 - 1757 0482 80040000 .4byte .LASF42 - 1758 0486 01 .byte 0x1 - 1759 0487 D901 .2byte 0x1d9 - 1760 0489 A5000000 .4byte 0xa5 - 1761 048d F8030000 .4byte .LLST24 - 1762 0491 13 .uleb128 0x13 - 1763 0492 3C040000 .4byte .LASF53 - 1764 0496 01 .byte 0x1 - 1765 0497 DA01 .2byte 0x1da - 1766 0499 A2040000 .4byte 0x4a2 - 1767 049d 2F040000 .4byte .LLST25 - 1768 04a1 00 .byte 0 - 1769 04a2 14 .uleb128 0x14 - 1770 04a3 04 .byte 0x4 - 1771 04a4 B0000000 .4byte 0xb0 - 1772 04a8 11 .uleb128 0x11 - 1773 04a9 01 .byte 0x1 - 1774 04aa A1040000 .4byte .LASF54 - 1775 04ae 01 .byte 0x1 - 1776 04af 1102 .2byte 0x211 - 1777 04b1 01 .byte 0x1 - 1778 04b2 A5000000 .4byte 0xa5 - 1779 04b6 00000000 .4byte .LFB11 - 1780 04ba 18000000 .4byte .LFE11 - 1781 04be 02 .byte 0x2 - 1782 04bf 7D .byte 0x7d - 1783 04c0 00 .sleb128 0 - 1784 04c1 01 .byte 0x1 - 1785 04c2 F5040000 .4byte 0x4f5 - 1786 04c6 12 .uleb128 0x12 - 1787 04c7 B3030000 .4byte .LASF41 - 1788 04cb 01 .byte 0x1 - 1789 04cc 1102 .2byte 0x211 - 1790 04ce 6F000000 .4byte 0x6f - 1791 04d2 60040000 .4byte .LLST26 - 1792 04d6 15 .uleb128 0x15 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 53 - - - 1793 04d7 4F040000 .4byte .LASF55 - 1794 04db 01 .byte 0x1 - 1795 04dc 1102 .2byte 0x211 - 1796 04de 6F000000 .4byte 0x6f - 1797 04e2 01 .byte 0x1 - 1798 04e3 51 .byte 0x51 - 1799 04e4 13 .uleb128 0x13 - 1800 04e5 80040000 .4byte .LASF42 - 1801 04e9 01 .byte 0x1 - 1802 04ea 1302 .2byte 0x213 - 1803 04ec A5000000 .4byte 0xa5 - 1804 04f0 9A040000 .4byte .LLST27 - 1805 04f4 00 .byte 0 - 1806 04f5 11 .uleb128 0x11 - 1807 04f6 01 .byte 0x1 - 1808 04f7 73030000 .4byte .LASF56 - 1809 04fb 01 .byte 0x1 - 1810 04fc 3702 .2byte 0x237 - 1811 04fe 01 .byte 0x1 - 1812 04ff A5000000 .4byte 0xa5 - 1813 0503 00000000 .4byte .LFB12 - 1814 0507 24000000 .4byte .LFE12 - 1815 050b 02 .byte 0x2 - 1816 050c 7D .byte 0x7d - 1817 050d 00 .sleb128 0 - 1818 050e 01 .byte 0x1 - 1819 050f 44050000 .4byte 0x544 - 1820 0513 12 .uleb128 0x12 - 1821 0514 B3030000 .4byte .LASF41 - 1822 0518 01 .byte 0x1 - 1823 0519 3702 .2byte 0x237 - 1824 051b 6F000000 .4byte 0x6f - 1825 051f D1040000 .4byte .LLST28 - 1826 0523 12 .uleb128 0x12 - 1827 0524 99040000 .4byte .LASF57 - 1828 0528 01 .byte 0x1 - 1829 0529 3702 .2byte 0x237 - 1830 052b 6F000000 .4byte 0x6f - 1831 052f 0B050000 .4byte .LLST29 - 1832 0533 13 .uleb128 0x13 - 1833 0534 80040000 .4byte .LASF42 - 1834 0538 01 .byte 0x1 - 1835 0539 3902 .2byte 0x239 - 1836 053b A5000000 .4byte 0xa5 - 1837 053f 37050000 .4byte .LLST30 - 1838 0543 00 .byte 0 - 1839 0544 11 .uleb128 0x11 - 1840 0545 01 .byte 0x1 - 1841 0546 87040000 .4byte .LASF58 - 1842 054a 01 .byte 0x1 - 1843 054b 5802 .2byte 0x258 - 1844 054d 01 .byte 0x1 - 1845 054e A5000000 .4byte 0xa5 - 1846 0552 00000000 .4byte .LFB13 - 1847 0556 1C000000 .4byte .LFE13 - 1848 055a 02 .byte 0x2 - 1849 055b 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 54 - - - 1850 055c 00 .sleb128 0 - 1851 055d 01 .byte 0x1 - 1852 055e 83050000 .4byte 0x583 - 1853 0562 12 .uleb128 0x12 - 1854 0563 B3030000 .4byte .LASF41 - 1855 0567 01 .byte 0x1 - 1856 0568 5802 .2byte 0x258 - 1857 056a 6F000000 .4byte 0x6f - 1858 056e 6E050000 .4byte .LLST31 - 1859 0572 13 .uleb128 0x13 - 1860 0573 80040000 .4byte .LASF42 - 1861 0577 01 .byte 0x1 - 1862 0578 5A02 .2byte 0x25a - 1863 057a A5000000 .4byte 0xa5 - 1864 057e A8050000 .4byte .LLST32 - 1865 0582 00 .byte 0 - 1866 0583 16 .uleb128 0x16 - 1867 0584 01 .byte 0x1 - 1868 0585 C4030000 .4byte .LASF59 - 1869 0589 01 .byte 0x1 - 1870 058a 8A02 .2byte 0x28a - 1871 058c 01 .byte 0x1 - 1872 058d A5000000 .4byte 0xa5 - 1873 0591 00000000 .4byte .LFB14 - 1874 0595 30000000 .4byte .LFE14 - 1875 0599 E0050000 .4byte .LLST33 - 1876 059d 01 .byte 0x1 - 1877 059e DE050000 .4byte 0x5de - 1878 05a2 12 .uleb128 0x12 - 1879 05a3 B3030000 .4byte .LASF41 - 1880 05a7 01 .byte 0x1 - 1881 05a8 8A02 .2byte 0x28a - 1882 05aa 6F000000 .4byte 0x6f - 1883 05ae 00060000 .4byte .LLST34 - 1884 05b2 12 .uleb128 0x12 - 1885 05b3 EE030000 .4byte .LASF60 - 1886 05b7 01 .byte 0x1 - 1887 05b8 8A02 .2byte 0x28a - 1888 05ba DE050000 .4byte 0x5de - 1889 05be 3A060000 .4byte .LLST35 - 1890 05c2 15 .uleb128 0x15 - 1891 05c3 03010000 .4byte .LASF61 - 1892 05c7 01 .byte 0x1 - 1893 05c8 8A02 .2byte 0x28a - 1894 05ca DE050000 .4byte 0x5de - 1895 05ce 01 .byte 0x1 - 1896 05cf 52 .byte 0x52 - 1897 05d0 17 .uleb128 0x17 - 1898 05d1 80040000 .4byte .LASF42 - 1899 05d5 01 .byte 0x1 - 1900 05d6 8C02 .2byte 0x28c - 1901 05d8 A5000000 .4byte 0xa5 - 1902 05dc 01 .byte 0x1 - 1903 05dd 00 .byte 0 - 1904 05de 14 .uleb128 0x14 - 1905 05df 04 .byte 0x4 - 1906 05e0 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 55 - - - 1907 05e4 16 .uleb128 0x16 - 1908 05e5 01 .byte 0x1 - 1909 05e6 BE040000 .4byte .LASF62 - 1910 05ea 01 .byte 0x1 - 1911 05eb CC02 .2byte 0x2cc - 1912 05ed 01 .byte 0x1 - 1913 05ee A5000000 .4byte 0xa5 - 1914 05f2 00000000 .4byte .LFB15 - 1915 05f6 40000000 .4byte .LFE15 - 1916 05fa 66060000 .4byte .LLST36 - 1917 05fe 01 .byte 0x1 - 1918 05ff 72060000 .4byte 0x672 - 1919 0603 12 .uleb128 0x12 - 1920 0604 B3030000 .4byte .LASF41 - 1921 0608 01 .byte 0x1 - 1922 0609 CC02 .2byte 0x2cc - 1923 060b 6F000000 .4byte 0x6f - 1924 060f 86060000 .4byte .LLST37 - 1925 0613 12 .uleb128 0x12 - 1926 0614 F4020000 .4byte .LASF63 - 1927 0618 01 .byte 0x1 - 1928 0619 CC02 .2byte 0x2cc - 1929 061b 6F000000 .4byte 0x6f - 1930 061f C0060000 .4byte .LLST38 - 1931 0623 12 .uleb128 0x12 - 1932 0624 20040000 .4byte .LASF64 - 1933 0628 01 .byte 0x1 - 1934 0629 CC02 .2byte 0x2cc - 1935 062b 6F000000 .4byte 0x6f - 1936 062f EC060000 .4byte .LLST39 - 1937 0633 12 .uleb128 0x12 - 1938 0634 12010000 .4byte .LASF65 - 1939 0638 01 .byte 0x1 - 1940 0639 CD02 .2byte 0x2cd - 1941 063b 6F000000 .4byte 0x6f - 1942 063f 18070000 .4byte .LLST40 - 1943 0643 15 .uleb128 0x15 - 1944 0644 1A010000 .4byte .LASF66 - 1945 0648 01 .byte 0x1 - 1946 0649 CD02 .2byte 0x2cd - 1947 064b 6F000000 .4byte 0x6f - 1948 064f 02 .byte 0x2 - 1949 0650 91 .byte 0x91 - 1950 0651 00 .sleb128 0 - 1951 0652 15 .uleb128 0x15 - 1952 0653 AC030000 .4byte .LASF67 - 1953 0657 01 .byte 0x1 - 1954 0658 CD02 .2byte 0x2cd - 1955 065a 6F000000 .4byte 0x6f - 1956 065e 02 .byte 0x2 - 1957 065f 91 .byte 0x91 - 1958 0660 04 .sleb128 4 - 1959 0661 13 .uleb128 0x13 - 1960 0662 80040000 .4byte .LASF42 - 1961 0666 01 .byte 0x1 - 1962 0667 CF02 .2byte 0x2cf - 1963 0669 A5000000 .4byte 0xa5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 56 - - - 1964 066d 44070000 .4byte .LLST41 - 1965 0671 00 .byte 0 - 1966 0672 16 .uleb128 0x16 - 1967 0673 01 .byte 0x1 - 1968 0674 3C000000 .4byte .LASF68 - 1969 0678 01 .byte 0x1 - 1970 0679 F002 .2byte 0x2f0 - 1971 067b 01 .byte 0x1 - 1972 067c 6F000000 .4byte 0x6f - 1973 0680 00000000 .4byte .LFB16 - 1974 0684 34000000 .4byte .LFE16 - 1975 0688 7B070000 .4byte .LLST42 - 1976 068c 01 .byte 0x1 - 1977 068d C4060000 .4byte 0x6c4 - 1978 0691 13 .uleb128 0x13 - 1979 0692 D9000000 .4byte .LASF36 - 1980 0696 01 .byte 0x1 - 1981 0697 F202 .2byte 0x2f2 - 1982 0699 6F000000 .4byte 0x6f - 1983 069d 9B070000 .4byte .LLST43 - 1984 06a1 13 .uleb128 0x13 - 1985 06a2 D6040000 .4byte .LASF69 - 1986 06a6 01 .byte 0x1 - 1987 06a7 F302 .2byte 0x2f3 - 1988 06a9 6F000000 .4byte 0x6f - 1989 06ad AE070000 .4byte .LLST44 - 1990 06b1 10 .uleb128 0x10 - 1991 06b2 06000000 .4byte .LVL81 - 1992 06b6 99090000 .4byte 0x999 - 1993 06ba 10 .uleb128 0x10 - 1994 06bb 2A000000 .4byte .LVL85 - 1995 06bf A7090000 .4byte 0x9a7 - 1996 06c3 00 .byte 0 - 1997 06c4 18 .uleb128 0x18 - 1998 06c5 01 .byte 0x1 - 1999 06c6 4C000000 .4byte .LASF70 - 2000 06ca 01 .byte 0x1 - 2001 06cb 1A03 .2byte 0x31a - 2002 06cd 01 .byte 0x1 - 2003 06ce 00000000 .4byte .LFB17 - 2004 06d2 34000000 .4byte .LFE17 - 2005 06d6 EA070000 .4byte .LLST45 - 2006 06da 01 .byte 0x1 - 2007 06db 19070000 .4byte 0x719 - 2008 06df 12 .uleb128 0x12 - 2009 06e0 B6000000 .4byte .LASF71 - 2010 06e4 01 .byte 0x1 - 2011 06e5 1A03 .2byte 0x31a - 2012 06e7 6F000000 .4byte 0x6f - 2013 06eb 0A080000 .4byte .LLST46 - 2014 06ef 19 .uleb128 0x19 - 2015 06f0 00000000 .4byte .Ldebug_ranges0+0 - 2016 06f4 13 .uleb128 0x13 - 2017 06f5 D9000000 .4byte .LASF36 - 2018 06f9 01 .byte 0x1 - 2019 06fa 1F03 .2byte 0x31f - 2020 06fc 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 57 - - - 2021 0700 36080000 .4byte .LLST47 - 2022 0704 10 .uleb128 0x10 - 2023 0705 0C000000 .4byte .LVL87 - 2024 0709 99090000 .4byte 0x999 - 2025 070d 1A .uleb128 0x1a - 2026 070e 2C000000 .4byte .LVL88 - 2027 0712 01 .byte 0x1 - 2028 0713 A7090000 .4byte 0x9a7 - 2029 0717 00 .byte 0 - 2030 0718 00 .byte 0 - 2031 0719 1B .uleb128 0x1b - 2032 071a 01 .byte 0x1 - 2033 071b 66000000 .4byte .LASF72 - 2034 071f 01 .byte 0x1 - 2035 0720 3E03 .2byte 0x33e - 2036 0722 01 .byte 0x1 - 2037 0723 6F000000 .4byte 0x6f - 2038 0727 00000000 .4byte .LFB18 - 2039 072b 10000000 .4byte .LFE18 - 2040 072f 02 .byte 0x2 - 2041 0730 7D .byte 0x7d - 2042 0731 00 .sleb128 0 - 2043 0732 01 .byte 0x1 - 2044 0733 16 .uleb128 0x16 - 2045 0734 01 .byte 0x1 - 2046 0735 9E000000 .4byte .LASF73 - 2047 0739 01 .byte 0x1 - 2048 073a 7B03 .2byte 0x37b - 2049 073c 01 .byte 0x1 - 2050 073d A5000000 .4byte 0xa5 - 2051 0741 00000000 .4byte .LFB19 - 2052 0745 26000000 .4byte .LFE19 - 2053 0749 49080000 .4byte .LLST48 - 2054 074d 01 .byte 0x1 - 2055 074e B7070000 .4byte 0x7b7 - 2056 0752 12 .uleb128 0x12 - 2057 0753 B6000000 .4byte .LASF71 - 2058 0757 01 .byte 0x1 - 2059 0758 7B03 .2byte 0x37b - 2060 075a 6F000000 .4byte 0x6f - 2061 075e 69080000 .4byte .LLST49 - 2062 0762 15 .uleb128 0x15 - 2063 0763 68040000 .4byte .LASF74 - 2064 0767 01 .byte 0x1 - 2065 0768 7B03 .2byte 0x37b - 2066 076a 7A000000 .4byte 0x7a - 2067 076e 01 .byte 0x1 - 2068 076f 51 .byte 0x51 - 2069 0770 15 .uleb128 0x15 - 2070 0771 6C030000 .4byte .LASF75 - 2071 0775 01 .byte 0x1 - 2072 0776 7B03 .2byte 0x37b - 2073 0778 6F000000 .4byte 0x6f - 2074 077c 01 .byte 0x1 - 2075 077d 52 .byte 0x52 - 2076 077e 15 .uleb128 0x15 - 2077 077f 1C020000 .4byte .LASF76 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 58 - - - 2078 0783 01 .byte 0x1 - 2079 0784 7B03 .2byte 0x37b - 2080 0786 6F000000 .4byte 0x6f - 2081 078a 01 .byte 0x1 - 2082 078b 53 .byte 0x53 - 2083 078c 13 .uleb128 0x13 - 2084 078d 80040000 .4byte .LASF42 - 2085 0791 01 .byte 0x1 - 2086 0792 7E03 .2byte 0x37e - 2087 0794 A5000000 .4byte 0xa5 - 2088 0798 A3080000 .4byte .LLST50 - 2089 079c 1C .uleb128 0x1c - 2090 079d 0E000000 .4byte .LBB4 - 2091 07a1 22000000 .4byte .LBE4 - 2092 07a5 13 .uleb128 0x13 - 2093 07a6 3C040000 .4byte .LASF53 - 2094 07aa 01 .byte 0x1 - 2095 07ab 8303 .2byte 0x383 - 2096 07ad A2040000 .4byte 0x4a2 - 2097 07b1 DA080000 .4byte .LLST51 - 2098 07b5 00 .byte 0 - 2099 07b6 00 .byte 0 - 2100 07b7 16 .uleb128 0x16 - 2101 07b8 01 .byte 0x1 - 2102 07b9 54030000 .4byte .LASF77 - 2103 07bd 01 .byte 0x1 - 2104 07be B703 .2byte 0x3b7 - 2105 07c0 01 .byte 0x1 - 2106 07c1 A5000000 .4byte 0xa5 - 2107 07c5 00000000 .4byte .LFB20 - 2108 07c9 44000000 .4byte .LFE20 - 2109 07cd ED080000 .4byte .LLST52 - 2110 07d1 01 .byte 0x1 - 2111 07d2 3C080000 .4byte 0x83c - 2112 07d6 12 .uleb128 0x12 - 2113 07d7 B6000000 .4byte .LASF71 - 2114 07db 01 .byte 0x1 - 2115 07dc B703 .2byte 0x3b7 - 2116 07de 6F000000 .4byte 0x6f - 2117 07e2 0D090000 .4byte .LLST53 - 2118 07e6 12 .uleb128 0x12 - 2119 07e7 68040000 .4byte .LASF74 - 2120 07eb 01 .byte 0x1 - 2121 07ec B703 .2byte 0x3b7 - 2122 07ee 3C080000 .4byte 0x83c - 2123 07f2 47090000 .4byte .LLST54 - 2124 07f6 12 .uleb128 0x12 - 2125 07f7 6C030000 .4byte .LASF75 - 2126 07fb 01 .byte 0x1 - 2127 07fc B703 .2byte 0x3b7 - 2128 07fe DE050000 .4byte 0x5de - 2129 0802 73090000 .4byte .LLST55 - 2130 0806 15 .uleb128 0x15 - 2131 0807 1C020000 .4byte .LASF76 - 2132 080b 01 .byte 0x1 - 2133 080c B703 .2byte 0x3b7 - 2134 080e DE050000 .4byte 0x5de - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 59 - - - 2135 0812 01 .byte 0x1 - 2136 0813 53 .byte 0x53 - 2137 0814 17 .uleb128 0x17 - 2138 0815 80040000 .4byte .LASF42 - 2139 0819 01 .byte 0x1 - 2140 081a BA03 .2byte 0x3ba - 2141 081c A5000000 .4byte 0xa5 - 2142 0820 01 .byte 0x1 - 2143 0821 1C .uleb128 0x1c - 2144 0822 0A000000 .4byte .LBB5 - 2145 0826 1C000000 .4byte .LBE5 - 2146 082a 13 .uleb128 0x13 - 2147 082b 3C040000 .4byte .LASF53 - 2148 082f 01 .byte 0x1 - 2149 0830 C203 .2byte 0x3c2 - 2150 0832 A2040000 .4byte 0x4a2 - 2151 0836 9F090000 .4byte .LLST56 - 2152 083a 00 .byte 0 - 2153 083b 00 .byte 0 - 2154 083c 14 .uleb128 0x14 - 2155 083d 04 .byte 0x4 - 2156 083e 7A000000 .4byte 0x7a - 2157 0842 11 .uleb128 0x11 - 2158 0843 01 .byte 0x1 - 2159 0844 C4020000 .4byte .LASF78 - 2160 0848 01 .byte 0x1 - 2161 0849 F203 .2byte 0x3f2 - 2162 084b 01 .byte 0x1 - 2163 084c A5000000 .4byte 0xa5 - 2164 0850 00000000 .4byte .LFB21 - 2165 0854 1A000000 .4byte .LFE21 - 2166 0858 02 .byte 0x2 - 2167 0859 7D .byte 0x7d - 2168 085a 00 .sleb128 0 - 2169 085b 01 .byte 0x1 - 2170 085c AD080000 .4byte 0x8ad - 2171 0860 12 .uleb128 0x12 - 2172 0861 B6000000 .4byte .LASF71 - 2173 0865 01 .byte 0x1 - 2174 0866 F203 .2byte 0x3f2 - 2175 0868 6F000000 .4byte 0x6f - 2176 086c C7090000 .4byte .LLST57 - 2177 0870 15 .uleb128 0x15 - 2178 0871 95020000 .4byte .LASF51 - 2179 0875 01 .byte 0x1 - 2180 0876 F203 .2byte 0x3f2 - 2181 0878 7A000000 .4byte 0x7a - 2182 087c 01 .byte 0x1 - 2183 087d 51 .byte 0x51 - 2184 087e 15 .uleb128 0x15 - 2185 087f 60010000 .4byte .LASF52 - 2186 0883 01 .byte 0x1 - 2187 0884 F203 .2byte 0x3f2 - 2188 0886 7A000000 .4byte 0x7a - 2189 088a 01 .byte 0x1 - 2190 088b 52 .byte 0x52 - 2191 088c 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 60 - - - 2192 088d 80040000 .4byte .LASF42 - 2193 0891 01 .byte 0x1 - 2194 0892 F403 .2byte 0x3f4 - 2195 0894 A5000000 .4byte 0xa5 - 2196 0898 010A0000 .4byte .LLST58 - 2197 089c 13 .uleb128 0x13 - 2198 089d 3C040000 .4byte .LASF53 - 2199 08a1 01 .byte 0x1 - 2200 08a2 F503 .2byte 0x3f5 - 2201 08a4 A2040000 .4byte 0x4a2 - 2202 08a8 380A0000 .4byte .LLST59 - 2203 08ac 00 .byte 0 - 2204 08ad 11 .uleb128 0x11 - 2205 08ae 01 .byte 0x1 - 2206 08af 06040000 .4byte .LASF79 - 2207 08b3 01 .byte 0x1 - 2208 08b4 2204 .2byte 0x422 - 2209 08b6 01 .byte 0x1 - 2210 08b7 A5000000 .4byte 0xa5 - 2211 08bb 00000000 .4byte .LFB22 - 2212 08bf 2C000000 .4byte .LFE22 - 2213 08c3 02 .byte 0x2 - 2214 08c4 7D .byte 0x7d - 2215 08c5 00 .sleb128 0 - 2216 08c6 01 .byte 0x1 - 2217 08c7 17090000 .4byte 0x917 - 2218 08cb 12 .uleb128 0x12 - 2219 08cc B6000000 .4byte .LASF71 - 2220 08d0 01 .byte 0x1 - 2221 08d1 2204 .2byte 0x422 - 2222 08d3 6F000000 .4byte 0x6f - 2223 08d7 690A0000 .4byte .LLST60 - 2224 08db 12 .uleb128 0x12 - 2225 08dc 95020000 .4byte .LASF51 - 2226 08e0 01 .byte 0x1 - 2227 08e1 2204 .2byte 0x422 - 2228 08e3 3C080000 .4byte 0x83c - 2229 08e7 A30A0000 .4byte .LLST61 - 2230 08eb 15 .uleb128 0x15 - 2231 08ec 60010000 .4byte .LASF52 - 2232 08f0 01 .byte 0x1 - 2233 08f1 2204 .2byte 0x422 - 2234 08f3 3C080000 .4byte 0x83c - 2235 08f7 01 .byte 0x1 - 2236 08f8 52 .byte 0x52 - 2237 08f9 17 .uleb128 0x17 - 2238 08fa 80040000 .4byte .LASF42 - 2239 08fe 01 .byte 0x1 - 2240 08ff 2404 .2byte 0x424 - 2241 0901 A5000000 .4byte 0xa5 - 2242 0905 01 .byte 0x1 - 2243 0906 13 .uleb128 0x13 - 2244 0907 3C040000 .4byte .LASF53 - 2245 090b 01 .byte 0x1 - 2246 090c 2504 .2byte 0x425 - 2247 090e A2040000 .4byte 0x4a2 - 2248 0912 CF0A0000 .4byte .LLST62 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 61 - - - 2249 0916 00 .byte 0 - 2250 0917 11 .uleb128 0x11 - 2251 0918 01 .byte 0x1 - 2252 0919 B2020000 .4byte .LASF80 - 2253 091d 01 .byte 0x1 - 2254 091e 5504 .2byte 0x455 - 2255 0920 01 .byte 0x1 - 2256 0921 A5000000 .4byte 0xa5 - 2257 0925 00000000 .4byte .LFB23 - 2258 0929 28000000 .4byte .LFE23 - 2259 092d 02 .byte 0x2 - 2260 092e 7D .byte 0x7d - 2261 092f 00 .sleb128 0 - 2262 0930 01 .byte 0x1 - 2263 0931 66090000 .4byte 0x966 - 2264 0935 12 .uleb128 0x12 - 2265 0936 B3030000 .4byte .LASF41 - 2266 093a 01 .byte 0x1 - 2267 093b 5504 .2byte 0x455 - 2268 093d 6F000000 .4byte 0x6f - 2269 0941 060B0000 .4byte .LLST63 - 2270 0945 12 .uleb128 0x12 - 2271 0946 E8000000 .4byte .LASF81 - 2272 094a 01 .byte 0x1 - 2273 094b 5504 .2byte 0x455 - 2274 094d 6F000000 .4byte 0x6f - 2275 0951 590B0000 .4byte .LLST64 - 2276 0955 13 .uleb128 0x13 - 2277 0956 80040000 .4byte .LASF42 - 2278 095a 01 .byte 0x1 - 2279 095b 5704 .2byte 0x457 - 2280 095d A5000000 .4byte 0xa5 - 2281 0961 9E0B0000 .4byte .LLST65 - 2282 0965 00 .byte 0 - 2283 0966 1D .uleb128 0x1d - 2284 0967 EA010000 .4byte .LASF82 - 2285 096b 01 .byte 0x1 - 2286 096c 28 .byte 0x28 - 2287 096d 6F000000 .4byte 0x6f - 2288 0971 05 .byte 0x5 - 2289 0972 03 .byte 0x3 - 2290 0973 01000000 .4byte CyDmaTdCurrentNumber - 2291 0977 1D .uleb128 0x1d - 2292 0978 57040000 .4byte .LASF83 - 2293 097c 01 .byte 0x1 - 2294 097d 29 .byte 0x29 - 2295 097e 6F000000 .4byte 0x6f - 2296 0982 05 .byte 0x5 - 2297 0983 03 .byte 0x3 - 2298 0984 00000000 .4byte CyDmaTdFreeIndex - 2299 0988 1D .uleb128 0x1d - 2300 0989 35010000 .4byte .LASF84 - 2301 098d 01 .byte 0x1 - 2302 098e 2A .byte 0x2a - 2303 098f 85000000 .4byte 0x85 - 2304 0993 05 .byte 0x5 - 2305 0994 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 62 - - - 2306 0995 00000000 .4byte CyDmaChannels - 2307 0999 1E .uleb128 0x1e - 2308 099a 01 .byte 0x1 - 2309 099b 36020000 .4byte .LASF88 - 2310 099f 04 .byte 0x4 - 2311 09a0 7E .byte 0x7e - 2312 09a1 01 .byte 0x1 - 2313 09a2 6F000000 .4byte 0x6f - 2314 09a6 01 .byte 0x1 - 2315 09a7 1F .uleb128 0x1f - 2316 09a8 01 .byte 0x1 - 2317 09a9 07000000 .4byte .LASF89 - 2318 09ad 04 .byte 0x4 - 2319 09ae 7F .byte 0x7f - 2320 09af 01 .byte 0x1 - 2321 09b0 01 .byte 0x1 - 2322 09b1 20 .uleb128 0x20 - 2323 09b2 6F000000 .4byte 0x6f - 2324 09b6 00 .byte 0 - 2325 09b7 00 .byte 0 - 2326 .section .debug_abbrev,"",%progbits - 2327 .Ldebug_abbrev0: - 2328 0000 01 .uleb128 0x1 - 2329 0001 11 .uleb128 0x11 - 2330 0002 01 .byte 0x1 - 2331 0003 25 .uleb128 0x25 - 2332 0004 0E .uleb128 0xe - 2333 0005 13 .uleb128 0x13 - 2334 0006 0B .uleb128 0xb - 2335 0007 03 .uleb128 0x3 - 2336 0008 0E .uleb128 0xe - 2337 0009 1B .uleb128 0x1b - 2338 000a 0E .uleb128 0xe - 2339 000b 55 .uleb128 0x55 - 2340 000c 06 .uleb128 0x6 - 2341 000d 11 .uleb128 0x11 - 2342 000e 01 .uleb128 0x1 - 2343 000f 52 .uleb128 0x52 - 2344 0010 01 .uleb128 0x1 - 2345 0011 10 .uleb128 0x10 - 2346 0012 06 .uleb128 0x6 - 2347 0013 00 .byte 0 - 2348 0014 00 .byte 0 - 2349 0015 02 .uleb128 0x2 - 2350 0016 24 .uleb128 0x24 - 2351 0017 00 .byte 0 - 2352 0018 0B .uleb128 0xb - 2353 0019 0B .uleb128 0xb - 2354 001a 3E .uleb128 0x3e - 2355 001b 0B .uleb128 0xb - 2356 001c 03 .uleb128 0x3 - 2357 001d 0E .uleb128 0xe - 2358 001e 00 .byte 0 - 2359 001f 00 .byte 0 - 2360 0020 03 .uleb128 0x3 - 2361 0021 24 .uleb128 0x24 - 2362 0022 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 63 - - - 2363 0023 0B .uleb128 0xb - 2364 0024 0B .uleb128 0xb - 2365 0025 3E .uleb128 0x3e - 2366 0026 0B .uleb128 0xb - 2367 0027 03 .uleb128 0x3 - 2368 0028 08 .uleb128 0x8 - 2369 0029 00 .byte 0 - 2370 002a 00 .byte 0 - 2371 002b 04 .uleb128 0x4 - 2372 002c 16 .uleb128 0x16 - 2373 002d 00 .byte 0 - 2374 002e 03 .uleb128 0x3 - 2375 002f 0E .uleb128 0xe - 2376 0030 3A .uleb128 0x3a - 2377 0031 0B .uleb128 0xb - 2378 0032 3B .uleb128 0x3b - 2379 0033 0B .uleb128 0xb - 2380 0034 49 .uleb128 0x49 - 2381 0035 13 .uleb128 0x13 - 2382 0036 00 .byte 0 - 2383 0037 00 .byte 0 - 2384 0038 05 .uleb128 0x5 - 2385 0039 35 .uleb128 0x35 - 2386 003a 00 .byte 0 - 2387 003b 49 .uleb128 0x49 - 2388 003c 13 .uleb128 0x13 - 2389 003d 00 .byte 0 - 2390 003e 00 .byte 0 - 2391 003f 06 .uleb128 0x6 - 2392 0040 13 .uleb128 0x13 - 2393 0041 01 .byte 0x1 - 2394 0042 03 .uleb128 0x3 - 2395 0043 0E .uleb128 0xe - 2396 0044 0B .uleb128 0xb - 2397 0045 0B .uleb128 0xb - 2398 0046 3A .uleb128 0x3a - 2399 0047 0B .uleb128 0xb - 2400 0048 3B .uleb128 0x3b - 2401 0049 0B .uleb128 0xb - 2402 004a 01 .uleb128 0x1 - 2403 004b 13 .uleb128 0x13 - 2404 004c 00 .byte 0 - 2405 004d 00 .byte 0 - 2406 004e 07 .uleb128 0x7 - 2407 004f 0D .uleb128 0xd - 2408 0050 00 .byte 0 - 2409 0051 03 .uleb128 0x3 - 2410 0052 0E .uleb128 0xe - 2411 0053 3A .uleb128 0x3a - 2412 0054 0B .uleb128 0xb - 2413 0055 3B .uleb128 0x3b - 2414 0056 0B .uleb128 0xb - 2415 0057 49 .uleb128 0x49 - 2416 0058 13 .uleb128 0x13 - 2417 0059 38 .uleb128 0x38 - 2418 005a 0A .uleb128 0xa - 2419 005b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 64 - - - 2420 005c 00 .byte 0 - 2421 005d 08 .uleb128 0x8 - 2422 005e 01 .uleb128 0x1 - 2423 005f 01 .byte 0x1 - 2424 0060 49 .uleb128 0x49 - 2425 0061 13 .uleb128 0x13 - 2426 0062 01 .uleb128 0x1 - 2427 0063 13 .uleb128 0x13 - 2428 0064 00 .byte 0 - 2429 0065 00 .byte 0 - 2430 0066 09 .uleb128 0x9 - 2431 0067 21 .uleb128 0x21 - 2432 0068 00 .byte 0 - 2433 0069 49 .uleb128 0x49 - 2434 006a 13 .uleb128 0x13 - 2435 006b 2F .uleb128 0x2f - 2436 006c 0B .uleb128 0xb - 2437 006d 00 .byte 0 - 2438 006e 00 .byte 0 - 2439 006f 0A .uleb128 0xa - 2440 0070 0D .uleb128 0xd - 2441 0071 00 .byte 0 - 2442 0072 03 .uleb128 0x3 - 2443 0073 08 .uleb128 0x8 - 2444 0074 3A .uleb128 0x3a - 2445 0075 0B .uleb128 0xb - 2446 0076 3B .uleb128 0x3b - 2447 0077 0B .uleb128 0xb - 2448 0078 49 .uleb128 0x49 - 2449 0079 13 .uleb128 0x13 - 2450 007a 38 .uleb128 0x38 - 2451 007b 0A .uleb128 0xa - 2452 007c 00 .byte 0 - 2453 007d 00 .byte 0 - 2454 007e 0B .uleb128 0xb - 2455 007f 2E .uleb128 0x2e - 2456 0080 01 .byte 0x1 - 2457 0081 3F .uleb128 0x3f - 2458 0082 0C .uleb128 0xc - 2459 0083 03 .uleb128 0x3 - 2460 0084 0E .uleb128 0xe - 2461 0085 3A .uleb128 0x3a - 2462 0086 0B .uleb128 0xb - 2463 0087 3B .uleb128 0x3b - 2464 0088 0B .uleb128 0xb - 2465 0089 27 .uleb128 0x27 - 2466 008a 0C .uleb128 0xc - 2467 008b 11 .uleb128 0x11 - 2468 008c 01 .uleb128 0x1 - 2469 008d 12 .uleb128 0x12 - 2470 008e 01 .uleb128 0x1 - 2471 008f 40 .uleb128 0x40 - 2472 0090 0A .uleb128 0xa - 2473 0091 9742 .uleb128 0x2117 - 2474 0093 0C .uleb128 0xc - 2475 0094 01 .uleb128 0x1 - 2476 0095 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 65 - - - 2477 0096 00 .byte 0 - 2478 0097 00 .byte 0 - 2479 0098 0C .uleb128 0xc - 2480 0099 34 .uleb128 0x34 - 2481 009a 00 .byte 0 - 2482 009b 03 .uleb128 0x3 - 2483 009c 0E .uleb128 0xe - 2484 009d 3A .uleb128 0x3a - 2485 009e 0B .uleb128 0xb - 2486 009f 3B .uleb128 0x3b - 2487 00a0 0B .uleb128 0xb - 2488 00a1 49 .uleb128 0x49 - 2489 00a2 13 .uleb128 0x13 - 2490 00a3 02 .uleb128 0x2 - 2491 00a4 06 .uleb128 0x6 - 2492 00a5 00 .byte 0 - 2493 00a6 00 .byte 0 - 2494 00a7 0D .uleb128 0xd - 2495 00a8 2E .uleb128 0x2e - 2496 00a9 00 .byte 0 - 2497 00aa 3F .uleb128 0x3f - 2498 00ab 0C .uleb128 0xc - 2499 00ac 03 .uleb128 0x3 - 2500 00ad 0E .uleb128 0xe - 2501 00ae 3A .uleb128 0x3a - 2502 00af 0B .uleb128 0xb - 2503 00b0 3B .uleb128 0x3b - 2504 00b1 0B .uleb128 0xb - 2505 00b2 27 .uleb128 0x27 - 2506 00b3 0C .uleb128 0xc - 2507 00b4 49 .uleb128 0x49 - 2508 00b5 13 .uleb128 0x13 - 2509 00b6 11 .uleb128 0x11 - 2510 00b7 01 .uleb128 0x1 - 2511 00b8 12 .uleb128 0x12 - 2512 00b9 01 .uleb128 0x1 - 2513 00ba 40 .uleb128 0x40 - 2514 00bb 0A .uleb128 0xa - 2515 00bc 9742 .uleb128 0x2117 - 2516 00be 0C .uleb128 0xc - 2517 00bf 00 .byte 0 - 2518 00c0 00 .byte 0 - 2519 00c1 0E .uleb128 0xe - 2520 00c2 05 .uleb128 0x5 - 2521 00c3 00 .byte 0 - 2522 00c4 03 .uleb128 0x3 - 2523 00c5 0E .uleb128 0xe - 2524 00c6 3A .uleb128 0x3a - 2525 00c7 0B .uleb128 0xb - 2526 00c8 3B .uleb128 0x3b - 2527 00c9 0B .uleb128 0xb - 2528 00ca 49 .uleb128 0x49 - 2529 00cb 13 .uleb128 0x13 - 2530 00cc 02 .uleb128 0x2 - 2531 00cd 06 .uleb128 0x6 - 2532 00ce 00 .byte 0 - 2533 00cf 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 66 - - - 2534 00d0 0F .uleb128 0xf - 2535 00d1 2E .uleb128 0x2e - 2536 00d2 01 .byte 0x1 - 2537 00d3 3F .uleb128 0x3f - 2538 00d4 0C .uleb128 0xc - 2539 00d5 03 .uleb128 0x3 - 2540 00d6 0E .uleb128 0xe - 2541 00d7 3A .uleb128 0x3a - 2542 00d8 0B .uleb128 0xb - 2543 00d9 3B .uleb128 0x3b - 2544 00da 0B .uleb128 0xb - 2545 00db 27 .uleb128 0x27 - 2546 00dc 0C .uleb128 0xc - 2547 00dd 49 .uleb128 0x49 - 2548 00de 13 .uleb128 0x13 - 2549 00df 11 .uleb128 0x11 - 2550 00e0 01 .uleb128 0x1 - 2551 00e1 12 .uleb128 0x12 - 2552 00e2 01 .uleb128 0x1 - 2553 00e3 40 .uleb128 0x40 - 2554 00e4 06 .uleb128 0x6 - 2555 00e5 9742 .uleb128 0x2117 - 2556 00e7 0C .uleb128 0xc - 2557 00e8 01 .uleb128 0x1 - 2558 00e9 13 .uleb128 0x13 - 2559 00ea 00 .byte 0 - 2560 00eb 00 .byte 0 - 2561 00ec 10 .uleb128 0x10 - 2562 00ed 898201 .uleb128 0x4109 - 2563 00f0 00 .byte 0 - 2564 00f1 11 .uleb128 0x11 - 2565 00f2 01 .uleb128 0x1 - 2566 00f3 31 .uleb128 0x31 - 2567 00f4 13 .uleb128 0x13 - 2568 00f5 00 .byte 0 - 2569 00f6 00 .byte 0 - 2570 00f7 11 .uleb128 0x11 - 2571 00f8 2E .uleb128 0x2e - 2572 00f9 01 .byte 0x1 - 2573 00fa 3F .uleb128 0x3f - 2574 00fb 0C .uleb128 0xc - 2575 00fc 03 .uleb128 0x3 - 2576 00fd 0E .uleb128 0xe - 2577 00fe 3A .uleb128 0x3a - 2578 00ff 0B .uleb128 0xb - 2579 0100 3B .uleb128 0x3b - 2580 0101 05 .uleb128 0x5 - 2581 0102 27 .uleb128 0x27 - 2582 0103 0C .uleb128 0xc - 2583 0104 49 .uleb128 0x49 - 2584 0105 13 .uleb128 0x13 - 2585 0106 11 .uleb128 0x11 - 2586 0107 01 .uleb128 0x1 - 2587 0108 12 .uleb128 0x12 - 2588 0109 01 .uleb128 0x1 - 2589 010a 40 .uleb128 0x40 - 2590 010b 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 67 - - - 2591 010c 9742 .uleb128 0x2117 - 2592 010e 0C .uleb128 0xc - 2593 010f 01 .uleb128 0x1 - 2594 0110 13 .uleb128 0x13 - 2595 0111 00 .byte 0 - 2596 0112 00 .byte 0 - 2597 0113 12 .uleb128 0x12 - 2598 0114 05 .uleb128 0x5 - 2599 0115 00 .byte 0 - 2600 0116 03 .uleb128 0x3 - 2601 0117 0E .uleb128 0xe - 2602 0118 3A .uleb128 0x3a - 2603 0119 0B .uleb128 0xb - 2604 011a 3B .uleb128 0x3b - 2605 011b 05 .uleb128 0x5 - 2606 011c 49 .uleb128 0x49 - 2607 011d 13 .uleb128 0x13 - 2608 011e 02 .uleb128 0x2 - 2609 011f 06 .uleb128 0x6 - 2610 0120 00 .byte 0 - 2611 0121 00 .byte 0 - 2612 0122 13 .uleb128 0x13 - 2613 0123 34 .uleb128 0x34 - 2614 0124 00 .byte 0 - 2615 0125 03 .uleb128 0x3 - 2616 0126 0E .uleb128 0xe - 2617 0127 3A .uleb128 0x3a - 2618 0128 0B .uleb128 0xb - 2619 0129 3B .uleb128 0x3b - 2620 012a 05 .uleb128 0x5 - 2621 012b 49 .uleb128 0x49 - 2622 012c 13 .uleb128 0x13 - 2623 012d 02 .uleb128 0x2 - 2624 012e 06 .uleb128 0x6 - 2625 012f 00 .byte 0 - 2626 0130 00 .byte 0 - 2627 0131 14 .uleb128 0x14 - 2628 0132 0F .uleb128 0xf - 2629 0133 00 .byte 0 - 2630 0134 0B .uleb128 0xb - 2631 0135 0B .uleb128 0xb - 2632 0136 49 .uleb128 0x49 - 2633 0137 13 .uleb128 0x13 - 2634 0138 00 .byte 0 - 2635 0139 00 .byte 0 - 2636 013a 15 .uleb128 0x15 - 2637 013b 05 .uleb128 0x5 - 2638 013c 00 .byte 0 - 2639 013d 03 .uleb128 0x3 - 2640 013e 0E .uleb128 0xe - 2641 013f 3A .uleb128 0x3a - 2642 0140 0B .uleb128 0xb - 2643 0141 3B .uleb128 0x3b - 2644 0142 05 .uleb128 0x5 - 2645 0143 49 .uleb128 0x49 - 2646 0144 13 .uleb128 0x13 - 2647 0145 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 68 - - - 2648 0146 0A .uleb128 0xa - 2649 0147 00 .byte 0 - 2650 0148 00 .byte 0 - 2651 0149 16 .uleb128 0x16 - 2652 014a 2E .uleb128 0x2e - 2653 014b 01 .byte 0x1 - 2654 014c 3F .uleb128 0x3f - 2655 014d 0C .uleb128 0xc - 2656 014e 03 .uleb128 0x3 - 2657 014f 0E .uleb128 0xe - 2658 0150 3A .uleb128 0x3a - 2659 0151 0B .uleb128 0xb - 2660 0152 3B .uleb128 0x3b - 2661 0153 05 .uleb128 0x5 - 2662 0154 27 .uleb128 0x27 - 2663 0155 0C .uleb128 0xc - 2664 0156 49 .uleb128 0x49 - 2665 0157 13 .uleb128 0x13 - 2666 0158 11 .uleb128 0x11 - 2667 0159 01 .uleb128 0x1 - 2668 015a 12 .uleb128 0x12 - 2669 015b 01 .uleb128 0x1 - 2670 015c 40 .uleb128 0x40 - 2671 015d 06 .uleb128 0x6 - 2672 015e 9742 .uleb128 0x2117 - 2673 0160 0C .uleb128 0xc - 2674 0161 01 .uleb128 0x1 - 2675 0162 13 .uleb128 0x13 - 2676 0163 00 .byte 0 - 2677 0164 00 .byte 0 - 2678 0165 17 .uleb128 0x17 - 2679 0166 34 .uleb128 0x34 - 2680 0167 00 .byte 0 - 2681 0168 03 .uleb128 0x3 - 2682 0169 0E .uleb128 0xe - 2683 016a 3A .uleb128 0x3a - 2684 016b 0B .uleb128 0xb - 2685 016c 3B .uleb128 0x3b - 2686 016d 05 .uleb128 0x5 - 2687 016e 49 .uleb128 0x49 - 2688 016f 13 .uleb128 0x13 - 2689 0170 1C .uleb128 0x1c - 2690 0171 0B .uleb128 0xb - 2691 0172 00 .byte 0 - 2692 0173 00 .byte 0 - 2693 0174 18 .uleb128 0x18 - 2694 0175 2E .uleb128 0x2e - 2695 0176 01 .byte 0x1 - 2696 0177 3F .uleb128 0x3f - 2697 0178 0C .uleb128 0xc - 2698 0179 03 .uleb128 0x3 - 2699 017a 0E .uleb128 0xe - 2700 017b 3A .uleb128 0x3a - 2701 017c 0B .uleb128 0xb - 2702 017d 3B .uleb128 0x3b - 2703 017e 05 .uleb128 0x5 - 2704 017f 27 .uleb128 0x27 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 69 - - - 2705 0180 0C .uleb128 0xc - 2706 0181 11 .uleb128 0x11 - 2707 0182 01 .uleb128 0x1 - 2708 0183 12 .uleb128 0x12 - 2709 0184 01 .uleb128 0x1 - 2710 0185 40 .uleb128 0x40 - 2711 0186 06 .uleb128 0x6 - 2712 0187 9742 .uleb128 0x2117 - 2713 0189 0C .uleb128 0xc - 2714 018a 01 .uleb128 0x1 - 2715 018b 13 .uleb128 0x13 - 2716 018c 00 .byte 0 - 2717 018d 00 .byte 0 - 2718 018e 19 .uleb128 0x19 - 2719 018f 0B .uleb128 0xb - 2720 0190 01 .byte 0x1 - 2721 0191 55 .uleb128 0x55 - 2722 0192 06 .uleb128 0x6 - 2723 0193 00 .byte 0 - 2724 0194 00 .byte 0 - 2725 0195 1A .uleb128 0x1a - 2726 0196 898201 .uleb128 0x4109 - 2727 0199 00 .byte 0 - 2728 019a 11 .uleb128 0x11 - 2729 019b 01 .uleb128 0x1 - 2730 019c 9542 .uleb128 0x2115 - 2731 019e 0C .uleb128 0xc - 2732 019f 31 .uleb128 0x31 - 2733 01a0 13 .uleb128 0x13 - 2734 01a1 00 .byte 0 - 2735 01a2 00 .byte 0 - 2736 01a3 1B .uleb128 0x1b - 2737 01a4 2E .uleb128 0x2e - 2738 01a5 00 .byte 0 - 2739 01a6 3F .uleb128 0x3f - 2740 01a7 0C .uleb128 0xc - 2741 01a8 03 .uleb128 0x3 - 2742 01a9 0E .uleb128 0xe - 2743 01aa 3A .uleb128 0x3a - 2744 01ab 0B .uleb128 0xb - 2745 01ac 3B .uleb128 0x3b - 2746 01ad 05 .uleb128 0x5 - 2747 01ae 27 .uleb128 0x27 - 2748 01af 0C .uleb128 0xc - 2749 01b0 49 .uleb128 0x49 - 2750 01b1 13 .uleb128 0x13 - 2751 01b2 11 .uleb128 0x11 - 2752 01b3 01 .uleb128 0x1 - 2753 01b4 12 .uleb128 0x12 - 2754 01b5 01 .uleb128 0x1 - 2755 01b6 40 .uleb128 0x40 - 2756 01b7 0A .uleb128 0xa - 2757 01b8 9742 .uleb128 0x2117 - 2758 01ba 0C .uleb128 0xc - 2759 01bb 00 .byte 0 - 2760 01bc 00 .byte 0 - 2761 01bd 1C .uleb128 0x1c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 70 - - - 2762 01be 0B .uleb128 0xb - 2763 01bf 01 .byte 0x1 - 2764 01c0 11 .uleb128 0x11 - 2765 01c1 01 .uleb128 0x1 - 2766 01c2 12 .uleb128 0x12 - 2767 01c3 01 .uleb128 0x1 - 2768 01c4 00 .byte 0 - 2769 01c5 00 .byte 0 - 2770 01c6 1D .uleb128 0x1d - 2771 01c7 34 .uleb128 0x34 - 2772 01c8 00 .byte 0 - 2773 01c9 03 .uleb128 0x3 - 2774 01ca 0E .uleb128 0xe - 2775 01cb 3A .uleb128 0x3a - 2776 01cc 0B .uleb128 0xb - 2777 01cd 3B .uleb128 0x3b - 2778 01ce 0B .uleb128 0xb - 2779 01cf 49 .uleb128 0x49 - 2780 01d0 13 .uleb128 0x13 - 2781 01d1 02 .uleb128 0x2 - 2782 01d2 0A .uleb128 0xa - 2783 01d3 00 .byte 0 - 2784 01d4 00 .byte 0 - 2785 01d5 1E .uleb128 0x1e - 2786 01d6 2E .uleb128 0x2e - 2787 01d7 00 .byte 0 - 2788 01d8 3F .uleb128 0x3f - 2789 01d9 0C .uleb128 0xc - 2790 01da 03 .uleb128 0x3 - 2791 01db 0E .uleb128 0xe - 2792 01dc 3A .uleb128 0x3a - 2793 01dd 0B .uleb128 0xb - 2794 01de 3B .uleb128 0x3b - 2795 01df 0B .uleb128 0xb - 2796 01e0 27 .uleb128 0x27 - 2797 01e1 0C .uleb128 0xc - 2798 01e2 49 .uleb128 0x49 - 2799 01e3 13 .uleb128 0x13 - 2800 01e4 3C .uleb128 0x3c - 2801 01e5 0C .uleb128 0xc - 2802 01e6 00 .byte 0 - 2803 01e7 00 .byte 0 - 2804 01e8 1F .uleb128 0x1f - 2805 01e9 2E .uleb128 0x2e - 2806 01ea 01 .byte 0x1 - 2807 01eb 3F .uleb128 0x3f - 2808 01ec 0C .uleb128 0xc - 2809 01ed 03 .uleb128 0x3 - 2810 01ee 0E .uleb128 0xe - 2811 01ef 3A .uleb128 0x3a - 2812 01f0 0B .uleb128 0xb - 2813 01f1 3B .uleb128 0x3b - 2814 01f2 0B .uleb128 0xb - 2815 01f3 27 .uleb128 0x27 - 2816 01f4 0C .uleb128 0xc - 2817 01f5 3C .uleb128 0x3c - 2818 01f6 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 71 - - - 2819 01f7 00 .byte 0 - 2820 01f8 00 .byte 0 - 2821 01f9 20 .uleb128 0x20 - 2822 01fa 05 .uleb128 0x5 - 2823 01fb 00 .byte 0 - 2824 01fc 49 .uleb128 0x49 - 2825 01fd 13 .uleb128 0x13 - 2826 01fe 00 .byte 0 - 2827 01ff 00 .byte 0 - 2828 0200 00 .byte 0 - 2829 .section .debug_loc,"",%progbits - 2830 .Ldebug_loc0: - 2831 .LLST0: - 2832 0000 0C000000 .4byte .LVL0 - 2833 0004 0E000000 .4byte .LVL1 - 2834 0008 0300 .2byte 0x3 - 2835 000a 08 .byte 0x8 - 2836 000b 7F .byte 0x7f - 2837 000c 9F .byte 0x9f - 2838 000d 00000000 .4byte 0 - 2839 0011 00000000 .4byte 0 - 2840 .LLST1: - 2841 0015 00000000 .4byte .LVL2 - 2842 0019 06000000 .4byte .LVL3 - 2843 001d 0100 .2byte 0x1 - 2844 001f 50 .byte 0x50 - 2845 0020 06000000 .4byte .LVL3 - 2846 0024 10000000 .4byte .LFE2 - 2847 0028 0400 .2byte 0x4 - 2848 002a F3 .byte 0xf3 - 2849 002b 01 .uleb128 0x1 - 2850 002c 50 .byte 0x50 - 2851 002d 9F .byte 0x9f - 2852 002e 00000000 .4byte 0 - 2853 0032 00000000 .4byte 0 - 2854 .LLST2: - 2855 0036 00000000 .4byte .LFB4 - 2856 003a 02000000 .4byte .LCFI0 - 2857 003e 0200 .2byte 0x2 - 2858 0040 7D .byte 0x7d - 2859 0041 00 .sleb128 0 - 2860 0042 02000000 .4byte .LCFI0 - 2861 0046 34000000 .4byte .LFE4 - 2862 004a 0200 .2byte 0x2 - 2863 004c 7D .byte 0x7d - 2864 004d 08 .sleb128 8 - 2865 004e 00000000 .4byte 0 - 2866 0052 00000000 .4byte 0 - 2867 .LLST3: - 2868 0056 06000000 .4byte .LVL5 - 2869 005a 2B000000 .4byte .LVL9-1 - 2870 005e 0100 .2byte 0x1 - 2871 0060 50 .byte 0x50 - 2872 0061 00000000 .4byte 0 - 2873 0065 00000000 .4byte 0 - 2874 .LLST4: - 2875 0069 06000000 .4byte .LVL5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 72 - - - 2876 006d 0E000000 .4byte .LVL6 - 2877 0071 0200 .2byte 0x2 - 2878 0073 30 .byte 0x30 - 2879 0074 9F .byte 0x9f - 2880 0075 22000000 .4byte .LVL7 - 2881 0079 34000000 .4byte .LFE4 - 2882 007d 0100 .2byte 0x1 - 2883 007f 54 .byte 0x54 - 2884 0080 00000000 .4byte 0 - 2885 0084 00000000 .4byte 0 - 2886 .LLST5: - 2887 0088 00000000 .4byte .LVL4 - 2888 008c 0E000000 .4byte .LVL6 - 2889 0090 0200 .2byte 0x2 - 2890 0092 31 .byte 0x31 - 2891 0093 9F .byte 0x9f - 2892 0094 22000000 .4byte .LVL7 - 2893 0098 28000000 .4byte .LVL8 - 2894 009c 0100 .2byte 0x1 - 2895 009e 51 .byte 0x51 - 2896 009f 00000000 .4byte 0 - 2897 00a3 00000000 .4byte 0 - 2898 .LLST6: - 2899 00a7 00000000 .4byte .LFB5 - 2900 00ab 04000000 .4byte .LCFI1 - 2901 00af 0200 .2byte 0x2 - 2902 00b1 7D .byte 0x7d - 2903 00b2 00 .sleb128 0 - 2904 00b3 04000000 .4byte .LCFI1 - 2905 00b7 30000000 .4byte .LFE5 - 2906 00bb 0200 .2byte 0x2 - 2907 00bd 7D .byte 0x7d - 2908 00be 10 .sleb128 16 - 2909 00bf 00000000 .4byte 0 - 2910 00c3 00000000 .4byte 0 - 2911 .LLST7: - 2912 00c7 00000000 .4byte .LVL10 - 2913 00cb 13000000 .4byte .LVL11-1 - 2914 00cf 0100 .2byte 0x1 - 2915 00d1 50 .byte 0x50 - 2916 00d2 13000000 .4byte .LVL11-1 - 2917 00d6 26000000 .4byte .LVL13 - 2918 00da 0400 .2byte 0x4 - 2919 00dc F3 .byte 0xf3 - 2920 00dd 01 .uleb128 0x1 - 2921 00de 50 .byte 0x50 - 2922 00df 9F .byte 0x9f - 2923 00e0 26000000 .4byte .LVL13 - 2924 00e4 28000000 .4byte .LVL14 - 2925 00e8 0100 .2byte 0x1 - 2926 00ea 50 .byte 0x50 - 2927 00eb 28000000 .4byte .LVL14 - 2928 00ef 30000000 .4byte .LFE5 - 2929 00f3 0400 .2byte 0x4 - 2930 00f5 F3 .byte 0xf3 - 2931 00f6 01 .uleb128 0x1 - 2932 00f7 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 73 - - - 2933 00f8 9F .byte 0x9f - 2934 00f9 00000000 .4byte 0 - 2935 00fd 00000000 .4byte 0 - 2936 .LLST8: - 2937 0101 00000000 .4byte .LVL10 - 2938 0105 22000000 .4byte .LVL12 - 2939 0109 0200 .2byte 0x2 - 2940 010b 31 .byte 0x31 - 2941 010c 9F .byte 0x9f - 2942 010d 22000000 .4byte .LVL12 - 2943 0111 26000000 .4byte .LVL13 - 2944 0115 0200 .2byte 0x2 - 2945 0117 30 .byte 0x30 - 2946 0118 9F .byte 0x9f - 2947 0119 26000000 .4byte .LVL13 - 2948 011d 28000000 .4byte .LVL14 - 2949 0121 0200 .2byte 0x2 - 2950 0123 31 .byte 0x31 - 2951 0124 9F .byte 0x9f - 2952 0125 28000000 .4byte .LVL14 - 2953 0129 30000000 .4byte .LFE5 - 2954 012d 0100 .2byte 0x1 - 2955 012f 50 .byte 0x50 - 2956 0130 00000000 .4byte 0 - 2957 0134 00000000 .4byte 0 - 2958 .LLST9: - 2959 0138 14000000 .4byte .LVL11 - 2960 013c 21000000 .4byte .LVL12-1 - 2961 0140 0100 .2byte 0x1 - 2962 0142 50 .byte 0x50 - 2963 0143 00000000 .4byte 0 - 2964 0147 00000000 .4byte 0 - 2965 .LLST10: - 2966 014b 00000000 .4byte .LVL15 - 2967 014f 1E000000 .4byte .LVL19 - 2968 0153 0100 .2byte 0x1 - 2969 0155 50 .byte 0x50 - 2970 0156 1E000000 .4byte .LVL19 - 2971 015a 2A000000 .4byte .LVL21 - 2972 015e 0400 .2byte 0x4 - 2973 0160 F3 .byte 0xf3 - 2974 0161 01 .uleb128 0x1 - 2975 0162 50 .byte 0x50 - 2976 0163 9F .byte 0x9f - 2977 0164 2A000000 .4byte .LVL21 - 2978 0168 2C000000 .4byte .LVL22 - 2979 016c 0100 .2byte 0x1 - 2980 016e 50 .byte 0x50 - 2981 016f 2C000000 .4byte .LVL22 - 2982 0173 34000000 .4byte .LFE6 - 2983 0177 0400 .2byte 0x4 - 2984 0179 F3 .byte 0xf3 - 2985 017a 01 .uleb128 0x1 - 2986 017b 50 .byte 0x50 - 2987 017c 9F .byte 0x9f - 2988 017d 00000000 .4byte 0 - 2989 0181 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 74 - - - 2990 .LLST11: - 2991 0185 00000000 .4byte .LVL15 - 2992 0189 0C000000 .4byte .LVL16 - 2993 018d 0100 .2byte 0x1 - 2994 018f 51 .byte 0x51 - 2995 0190 0C000000 .4byte .LVL16 - 2996 0194 12000000 .4byte .LVL17 - 2997 0198 0400 .2byte 0x4 - 2998 019a F3 .byte 0xf3 - 2999 019b 01 .uleb128 0x1 - 3000 019c 51 .byte 0x51 - 3001 019d 9F .byte 0x9f - 3002 019e 12000000 .4byte .LVL17 - 3003 01a2 14000000 .4byte .LVL18 - 3004 01a6 0100 .2byte 0x1 - 3005 01a8 51 .byte 0x51 - 3006 01a9 14000000 .4byte .LVL18 - 3007 01ad 2A000000 .4byte .LVL21 - 3008 01b1 0400 .2byte 0x4 - 3009 01b3 F3 .byte 0xf3 - 3010 01b4 01 .uleb128 0x1 - 3011 01b5 51 .byte 0x51 - 3012 01b6 9F .byte 0x9f - 3013 01b7 2A000000 .4byte .LVL21 - 3014 01bb 34000000 .4byte .LFE6 - 3015 01bf 0100 .2byte 0x1 - 3016 01c1 51 .byte 0x51 - 3017 01c2 00000000 .4byte 0 - 3018 01c6 00000000 .4byte 0 - 3019 .LLST12: - 3020 01ca 00000000 .4byte .LVL15 - 3021 01ce 26000000 .4byte .LVL20 - 3022 01d2 0200 .2byte 0x2 - 3023 01d4 31 .byte 0x31 - 3024 01d5 9F .byte 0x9f - 3025 01d6 26000000 .4byte .LVL20 - 3026 01da 2A000000 .4byte .LVL21 - 3027 01de 0200 .2byte 0x2 - 3028 01e0 30 .byte 0x30 - 3029 01e1 9F .byte 0x9f - 3030 01e2 2A000000 .4byte .LVL21 - 3031 01e6 2C000000 .4byte .LVL22 - 3032 01ea 0200 .2byte 0x2 - 3033 01ec 31 .byte 0x31 - 3034 01ed 9F .byte 0x9f - 3035 01ee 2C000000 .4byte .LVL22 - 3036 01f2 34000000 .4byte .LFE6 - 3037 01f6 0100 .2byte 0x1 - 3038 01f8 50 .byte 0x50 - 3039 01f9 00000000 .4byte 0 - 3040 01fd 00000000 .4byte 0 - 3041 .LLST13: - 3042 0201 00000000 .4byte .LVL23 - 3043 0205 08000000 .4byte .LVL24 - 3044 0209 0100 .2byte 0x1 - 3045 020b 50 .byte 0x50 - 3046 020c 08000000 .4byte .LVL24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 75 - - - 3047 0210 1C000000 .4byte .LVL26 - 3048 0214 0400 .2byte 0x4 - 3049 0216 F3 .byte 0xf3 - 3050 0217 01 .uleb128 0x1 - 3051 0218 50 .byte 0x50 - 3052 0219 9F .byte 0x9f - 3053 021a 1C000000 .4byte .LVL26 - 3054 021e 1E000000 .4byte .LVL27 - 3055 0222 0100 .2byte 0x1 - 3056 0224 50 .byte 0x50 - 3057 0225 1E000000 .4byte .LVL27 - 3058 0229 24000000 .4byte .LFE7 - 3059 022d 0400 .2byte 0x4 - 3060 022f F3 .byte 0xf3 - 3061 0230 01 .uleb128 0x1 - 3062 0231 50 .byte 0x50 - 3063 0232 9F .byte 0x9f - 3064 0233 00000000 .4byte 0 - 3065 0237 00000000 .4byte 0 - 3066 .LLST14: - 3067 023b 00000000 .4byte .LVL23 - 3068 023f 18000000 .4byte .LVL25 - 3069 0243 0200 .2byte 0x2 - 3070 0245 31 .byte 0x31 - 3071 0246 9F .byte 0x9f - 3072 0247 18000000 .4byte .LVL25 - 3073 024b 1C000000 .4byte .LVL26 - 3074 024f 0200 .2byte 0x2 - 3075 0251 30 .byte 0x30 - 3076 0252 9F .byte 0x9f - 3077 0253 1C000000 .4byte .LVL26 - 3078 0257 1E000000 .4byte .LVL27 - 3079 025b 0200 .2byte 0x2 - 3080 025d 31 .byte 0x31 - 3081 025e 9F .byte 0x9f - 3082 025f 1E000000 .4byte .LVL27 - 3083 0263 24000000 .4byte .LFE7 - 3084 0267 0100 .2byte 0x1 - 3085 0269 50 .byte 0x50 - 3086 026a 00000000 .4byte 0 - 3087 026e 00000000 .4byte 0 - 3088 .LLST15: - 3089 0272 00000000 .4byte .LVL28 - 3090 0276 08000000 .4byte .LVL29 - 3091 027a 0100 .2byte 0x1 - 3092 027c 50 .byte 0x50 - 3093 027d 08000000 .4byte .LVL29 - 3094 0281 1E000000 .4byte .LVL31 - 3095 0285 0400 .2byte 0x4 - 3096 0287 F3 .byte 0xf3 - 3097 0288 01 .uleb128 0x1 - 3098 0289 50 .byte 0x50 - 3099 028a 9F .byte 0x9f - 3100 028b 1E000000 .4byte .LVL31 - 3101 028f 20000000 .4byte .LVL32 - 3102 0293 0100 .2byte 0x1 - 3103 0295 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 76 - - - 3104 0296 20000000 .4byte .LVL32 - 3105 029a 28000000 .4byte .LFE8 - 3106 029e 0400 .2byte 0x4 - 3107 02a0 F3 .byte 0xf3 - 3108 02a1 01 .uleb128 0x1 - 3109 02a2 50 .byte 0x50 - 3110 02a3 9F .byte 0x9f - 3111 02a4 00000000 .4byte 0 - 3112 02a8 00000000 .4byte 0 - 3113 .LLST16: - 3114 02ac 00000000 .4byte .LVL28 - 3115 02b0 1A000000 .4byte .LVL30 - 3116 02b4 0200 .2byte 0x2 - 3117 02b6 31 .byte 0x31 - 3118 02b7 9F .byte 0x9f - 3119 02b8 1A000000 .4byte .LVL30 - 3120 02bc 1E000000 .4byte .LVL31 - 3121 02c0 0200 .2byte 0x2 - 3122 02c2 30 .byte 0x30 - 3123 02c3 9F .byte 0x9f - 3124 02c4 1E000000 .4byte .LVL31 - 3125 02c8 20000000 .4byte .LVL32 - 3126 02cc 0200 .2byte 0x2 - 3127 02ce 31 .byte 0x31 - 3128 02cf 9F .byte 0x9f - 3129 02d0 20000000 .4byte .LVL32 - 3130 02d4 28000000 .4byte .LFE8 - 3131 02d8 0100 .2byte 0x1 - 3132 02da 50 .byte 0x50 - 3133 02db 00000000 .4byte 0 - 3134 02df 00000000 .4byte 0 - 3135 .LLST17: - 3136 02e3 00000000 .4byte .LVL33 - 3137 02e7 08000000 .4byte .LVL34 - 3138 02eb 0100 .2byte 0x1 - 3139 02ed 50 .byte 0x50 - 3140 02ee 08000000 .4byte .LVL34 - 3141 02f2 1C000000 .4byte .LVL39 - 3142 02f6 0400 .2byte 0x4 - 3143 02f8 F3 .byte 0xf3 - 3144 02f9 01 .uleb128 0x1 - 3145 02fa 50 .byte 0x50 - 3146 02fb 9F .byte 0x9f - 3147 02fc 1C000000 .4byte .LVL39 - 3148 0300 1E000000 .4byte .LVL40 - 3149 0304 0100 .2byte 0x1 - 3150 0306 50 .byte 0x50 - 3151 0307 1E000000 .4byte .LVL40 - 3152 030b 24000000 .4byte .LFE9 - 3153 030f 0400 .2byte 0x4 - 3154 0311 F3 .byte 0xf3 - 3155 0312 01 .uleb128 0x1 - 3156 0313 50 .byte 0x50 - 3157 0314 9F .byte 0x9f - 3158 0315 00000000 .4byte 0 - 3159 0319 00000000 .4byte 0 - 3160 .LLST18: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 77 - - - 3161 031d 00000000 .4byte .LVL33 - 3162 0321 0E000000 .4byte .LVL36 - 3163 0325 0100 .2byte 0x1 - 3164 0327 51 .byte 0x51 - 3165 0328 0E000000 .4byte .LVL36 - 3166 032c 1C000000 .4byte .LVL39 - 3167 0330 0400 .2byte 0x4 - 3168 0332 F3 .byte 0xf3 - 3169 0333 01 .uleb128 0x1 - 3170 0334 51 .byte 0x51 - 3171 0335 9F .byte 0x9f - 3172 0336 1C000000 .4byte .LVL39 - 3173 033a 24000000 .4byte .LFE9 - 3174 033e 0100 .2byte 0x1 - 3175 0340 51 .byte 0x51 - 3176 0341 00000000 .4byte 0 - 3177 0345 00000000 .4byte 0 - 3178 .LLST19: - 3179 0349 0A000000 .4byte .LVL35 - 3180 034d 12000000 .4byte .LVL37 - 3181 0351 0600 .2byte 0x6 - 3182 0353 72 .byte 0x72 - 3183 0354 00 .sleb128 0 - 3184 0355 09 .byte 0x9 - 3185 0356 F1 .byte 0xf1 - 3186 0357 1A .byte 0x1a - 3187 0358 9F .byte 0x9f - 3188 0359 00000000 .4byte 0 - 3189 035d 00000000 .4byte 0 - 3190 .LLST20: - 3191 0361 00000000 .4byte .LVL33 - 3192 0365 18000000 .4byte .LVL38 - 3193 0369 0200 .2byte 0x2 - 3194 036b 31 .byte 0x31 - 3195 036c 9F .byte 0x9f - 3196 036d 18000000 .4byte .LVL38 - 3197 0371 1C000000 .4byte .LVL39 - 3198 0375 0200 .2byte 0x2 - 3199 0377 30 .byte 0x30 - 3200 0378 9F .byte 0x9f - 3201 0379 1C000000 .4byte .LVL39 - 3202 037d 1E000000 .4byte .LVL40 - 3203 0381 0200 .2byte 0x2 - 3204 0383 31 .byte 0x31 - 3205 0384 9F .byte 0x9f - 3206 0385 1E000000 .4byte .LVL40 - 3207 0389 24000000 .4byte .LFE9 - 3208 038d 0100 .2byte 0x1 - 3209 038f 50 .byte 0x50 - 3210 0390 00000000 .4byte 0 - 3211 0394 00000000 .4byte 0 - 3212 .LLST21: - 3213 0398 00000000 .4byte .LVL41 - 3214 039c 1A000000 .4byte .LVL44 - 3215 03a0 0100 .2byte 0x1 - 3216 03a2 50 .byte 0x50 - 3217 03a3 1A000000 .4byte .LVL44 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 78 - - - 3218 03a7 2A000000 .4byte .LVL49 - 3219 03ab 0400 .2byte 0x4 - 3220 03ad F3 .byte 0xf3 - 3221 03ae 01 .uleb128 0x1 - 3222 03af 50 .byte 0x50 - 3223 03b0 9F .byte 0x9f - 3224 03b1 2A000000 .4byte .LVL49 - 3225 03b5 2C000000 .4byte .LVL50 - 3226 03b9 0100 .2byte 0x1 - 3227 03bb 50 .byte 0x50 - 3228 03bc 2C000000 .4byte .LVL50 - 3229 03c0 2E000000 .4byte .LFE10 - 3230 03c4 0400 .2byte 0x4 - 3231 03c6 F3 .byte 0xf3 - 3232 03c7 01 .uleb128 0x1 - 3233 03c8 50 .byte 0x50 - 3234 03c9 9F .byte 0x9f - 3235 03ca 00000000 .4byte 0 - 3236 03ce 00000000 .4byte 0 - 3237 .LLST22: - 3238 03d2 00000000 .4byte .LVL41 - 3239 03d6 0C000000 .4byte .LVL42 - 3240 03da 0100 .2byte 0x1 - 3241 03dc 51 .byte 0x51 - 3242 03dd 00000000 .4byte 0 - 3243 03e1 00000000 .4byte 0 - 3244 .LLST23: - 3245 03e5 00000000 .4byte .LVL41 - 3246 03e9 14000000 .4byte .LVL43 - 3247 03ed 0100 .2byte 0x1 - 3248 03ef 52 .byte 0x52 - 3249 03f0 00000000 .4byte 0 - 3250 03f4 00000000 .4byte 0 - 3251 .LLST24: - 3252 03f8 00000000 .4byte .LVL41 - 3253 03fc 26000000 .4byte .LVL47 - 3254 0400 0200 .2byte 0x2 - 3255 0402 31 .byte 0x31 - 3256 0403 9F .byte 0x9f - 3257 0404 26000000 .4byte .LVL47 - 3258 0408 2A000000 .4byte .LVL49 - 3259 040c 0200 .2byte 0x2 - 3260 040e 30 .byte 0x30 - 3261 040f 9F .byte 0x9f - 3262 0410 2A000000 .4byte .LVL49 - 3263 0414 2C000000 .4byte .LVL50 - 3264 0418 0200 .2byte 0x2 - 3265 041a 31 .byte 0x31 - 3266 041b 9F .byte 0x9f - 3267 041c 2C000000 .4byte .LVL50 - 3268 0420 2E000000 .4byte .LFE10 - 3269 0424 0100 .2byte 0x1 - 3270 0426 50 .byte 0x50 - 3271 0427 00000000 .4byte 0 - 3272 042b 00000000 .4byte 0 - 3273 .LLST25: - 3274 042f 22000000 .4byte .LVL45 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 79 - - - 3275 0433 24000000 .4byte .LVL46 - 3276 0437 0300 .2byte 0x3 - 3277 0439 70 .byte 0x70 - 3278 043a 04 .sleb128 4 - 3279 043b 9F .byte 0x9f - 3280 043c 24000000 .4byte .LVL46 - 3281 0440 28000000 .4byte .LVL48 - 3282 0444 0300 .2byte 0x3 - 3283 0446 70 .byte 0x70 - 3284 0447 06 .sleb128 6 - 3285 0448 9F .byte 0x9f - 3286 0449 28000000 .4byte .LVL48 - 3287 044d 2A000000 .4byte .LVL49 - 3288 0451 0500 .2byte 0x5 - 3289 0453 73 .byte 0x73 - 3290 0454 86EC01 .sleb128 30214 - 3291 0457 9F .byte 0x9f - 3292 0458 00000000 .4byte 0 - 3293 045c 00000000 .4byte 0 - 3294 .LLST26: - 3295 0460 00000000 .4byte .LVL51 - 3296 0464 08000000 .4byte .LVL52 - 3297 0468 0100 .2byte 0x1 - 3298 046a 50 .byte 0x50 - 3299 046b 08000000 .4byte .LVL52 - 3300 046f 10000000 .4byte .LVL54 - 3301 0473 0400 .2byte 0x4 - 3302 0475 F3 .byte 0xf3 - 3303 0476 01 .uleb128 0x1 - 3304 0477 50 .byte 0x50 - 3305 0478 9F .byte 0x9f - 3306 0479 10000000 .4byte .LVL54 - 3307 047d 12000000 .4byte .LVL55 - 3308 0481 0100 .2byte 0x1 - 3309 0483 50 .byte 0x50 - 3310 0484 12000000 .4byte .LVL55 - 3311 0488 18000000 .4byte .LFE11 - 3312 048c 0400 .2byte 0x4 - 3313 048e F3 .byte 0xf3 - 3314 048f 01 .uleb128 0x1 - 3315 0490 50 .byte 0x50 - 3316 0491 9F .byte 0x9f - 3317 0492 00000000 .4byte 0 - 3318 0496 00000000 .4byte 0 - 3319 .LLST27: - 3320 049a 00000000 .4byte .LVL51 - 3321 049e 0C000000 .4byte .LVL53 - 3322 04a2 0200 .2byte 0x2 - 3323 04a4 31 .byte 0x31 - 3324 04a5 9F .byte 0x9f - 3325 04a6 0C000000 .4byte .LVL53 - 3326 04aa 10000000 .4byte .LVL54 - 3327 04ae 0200 .2byte 0x2 - 3328 04b0 30 .byte 0x30 - 3329 04b1 9F .byte 0x9f - 3330 04b2 10000000 .4byte .LVL54 - 3331 04b6 12000000 .4byte .LVL55 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 80 - - - 3332 04ba 0200 .2byte 0x2 - 3333 04bc 31 .byte 0x31 - 3334 04bd 9F .byte 0x9f - 3335 04be 12000000 .4byte .LVL55 - 3336 04c2 18000000 .4byte .LFE11 - 3337 04c6 0100 .2byte 0x1 - 3338 04c8 50 .byte 0x50 - 3339 04c9 00000000 .4byte 0 - 3340 04cd 00000000 .4byte 0 - 3341 .LLST28: - 3342 04d1 00000000 .4byte .LVL56 - 3343 04d5 08000000 .4byte .LVL57 - 3344 04d9 0100 .2byte 0x1 - 3345 04db 50 .byte 0x50 - 3346 04dc 08000000 .4byte .LVL57 - 3347 04e0 1A000000 .4byte .LVL60 - 3348 04e4 0400 .2byte 0x4 - 3349 04e6 F3 .byte 0xf3 - 3350 04e7 01 .uleb128 0x1 - 3351 04e8 50 .byte 0x50 - 3352 04e9 9F .byte 0x9f - 3353 04ea 1A000000 .4byte .LVL60 - 3354 04ee 1C000000 .4byte .LVL61 - 3355 04f2 0100 .2byte 0x1 - 3356 04f4 50 .byte 0x50 - 3357 04f5 1C000000 .4byte .LVL61 - 3358 04f9 24000000 .4byte .LFE12 - 3359 04fd 0400 .2byte 0x4 - 3360 04ff F3 .byte 0xf3 - 3361 0500 01 .uleb128 0x1 - 3362 0501 50 .byte 0x50 - 3363 0502 9F .byte 0x9f - 3364 0503 00000000 .4byte 0 - 3365 0507 00000000 .4byte 0 - 3366 .LLST29: - 3367 050b 00000000 .4byte .LVL56 - 3368 050f 10000000 .4byte .LVL58 - 3369 0513 0100 .2byte 0x1 - 3370 0515 51 .byte 0x51 - 3371 0516 10000000 .4byte .LVL58 - 3372 051a 1A000000 .4byte .LVL60 - 3373 051e 0400 .2byte 0x4 - 3374 0520 F3 .byte 0xf3 - 3375 0521 01 .uleb128 0x1 - 3376 0522 51 .byte 0x51 - 3377 0523 9F .byte 0x9f - 3378 0524 1A000000 .4byte .LVL60 - 3379 0528 24000000 .4byte .LFE12 - 3380 052c 0100 .2byte 0x1 - 3381 052e 51 .byte 0x51 - 3382 052f 00000000 .4byte 0 - 3383 0533 00000000 .4byte 0 - 3384 .LLST30: - 3385 0537 00000000 .4byte .LVL56 - 3386 053b 16000000 .4byte .LVL59 - 3387 053f 0200 .2byte 0x2 - 3388 0541 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 81 - - - 3389 0542 9F .byte 0x9f - 3390 0543 16000000 .4byte .LVL59 - 3391 0547 1A000000 .4byte .LVL60 - 3392 054b 0200 .2byte 0x2 - 3393 054d 30 .byte 0x30 - 3394 054e 9F .byte 0x9f - 3395 054f 1A000000 .4byte .LVL60 - 3396 0553 1C000000 .4byte .LVL61 - 3397 0557 0200 .2byte 0x2 - 3398 0559 31 .byte 0x31 - 3399 055a 9F .byte 0x9f - 3400 055b 1C000000 .4byte .LVL61 - 3401 055f 24000000 .4byte .LFE12 - 3402 0563 0100 .2byte 0x1 - 3403 0565 50 .byte 0x50 - 3404 0566 00000000 .4byte 0 - 3405 056a 00000000 .4byte 0 - 3406 .LLST31: - 3407 056e 00000000 .4byte .LVL62 - 3408 0572 08000000 .4byte .LVL63 - 3409 0576 0100 .2byte 0x1 - 3410 0578 50 .byte 0x50 - 3411 0579 08000000 .4byte .LVL63 - 3412 057d 12000000 .4byte .LVL65 - 3413 0581 0400 .2byte 0x4 - 3414 0583 F3 .byte 0xf3 - 3415 0584 01 .uleb128 0x1 - 3416 0585 50 .byte 0x50 - 3417 0586 9F .byte 0x9f - 3418 0587 12000000 .4byte .LVL65 - 3419 058b 14000000 .4byte .LVL66 - 3420 058f 0100 .2byte 0x1 - 3421 0591 50 .byte 0x50 - 3422 0592 14000000 .4byte .LVL66 - 3423 0596 1C000000 .4byte .LFE13 - 3424 059a 0400 .2byte 0x4 - 3425 059c F3 .byte 0xf3 - 3426 059d 01 .uleb128 0x1 - 3427 059e 50 .byte 0x50 - 3428 059f 9F .byte 0x9f - 3429 05a0 00000000 .4byte 0 - 3430 05a4 00000000 .4byte 0 - 3431 .LLST32: - 3432 05a8 00000000 .4byte .LVL62 - 3433 05ac 10000000 .4byte .LVL64 - 3434 05b0 0300 .2byte 0x3 - 3435 05b2 08 .byte 0x8 - 3436 05b3 FF .byte 0xff - 3437 05b4 9F .byte 0x9f - 3438 05b5 10000000 .4byte .LVL64 - 3439 05b9 12000000 .4byte .LVL65 - 3440 05bd 0100 .2byte 0x1 - 3441 05bf 50 .byte 0x50 - 3442 05c0 12000000 .4byte .LVL65 - 3443 05c4 14000000 .4byte .LVL66 - 3444 05c8 0300 .2byte 0x3 - 3445 05ca 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 82 - - - 3446 05cb FF .byte 0xff - 3447 05cc 9F .byte 0x9f - 3448 05cd 14000000 .4byte .LVL66 - 3449 05d1 1C000000 .4byte .LFE13 - 3450 05d5 0100 .2byte 0x1 - 3451 05d7 50 .byte 0x50 - 3452 05d8 00000000 .4byte 0 - 3453 05dc 00000000 .4byte 0 - 3454 .LLST33: - 3455 05e0 00000000 .4byte .LFB14 - 3456 05e4 04000000 .4byte .LCFI2 - 3457 05e8 0200 .2byte 0x2 - 3458 05ea 7D .byte 0x7d - 3459 05eb 00 .sleb128 0 - 3460 05ec 04000000 .4byte .LCFI2 - 3461 05f0 30000000 .4byte .LFE14 - 3462 05f4 0200 .2byte 0x2 - 3463 05f6 7D .byte 0x7d - 3464 05f7 08 .sleb128 8 - 3465 05f8 00000000 .4byte 0 - 3466 05fc 00000000 .4byte 0 - 3467 .LLST34: - 3468 0600 00000000 .4byte .LVL67 - 3469 0604 1C000000 .4byte .LVL69 - 3470 0608 0100 .2byte 0x1 - 3471 060a 50 .byte 0x50 - 3472 060b 1C000000 .4byte .LVL69 - 3473 060f 26000000 .4byte .LVL70 - 3474 0613 0400 .2byte 0x4 - 3475 0615 F3 .byte 0xf3 - 3476 0616 01 .uleb128 0x1 - 3477 0617 50 .byte 0x50 - 3478 0618 9F .byte 0x9f - 3479 0619 26000000 .4byte .LVL70 - 3480 061d 28000000 .4byte .LVL71 - 3481 0621 0100 .2byte 0x1 - 3482 0623 50 .byte 0x50 - 3483 0624 28000000 .4byte .LVL71 - 3484 0628 30000000 .4byte .LFE14 - 3485 062c 0400 .2byte 0x4 - 3486 062e F3 .byte 0xf3 - 3487 062f 01 .uleb128 0x1 - 3488 0630 50 .byte 0x50 - 3489 0631 9F .byte 0x9f - 3490 0632 00000000 .4byte 0 - 3491 0636 00000000 .4byte 0 - 3492 .LLST35: - 3493 063a 00000000 .4byte .LVL67 - 3494 063e 1A000000 .4byte .LVL68 - 3495 0642 0100 .2byte 0x1 - 3496 0644 51 .byte 0x51 - 3497 0645 1A000000 .4byte .LVL68 - 3498 0649 26000000 .4byte .LVL70 - 3499 064d 0400 .2byte 0x4 - 3500 064f F3 .byte 0xf3 - 3501 0650 01 .uleb128 0x1 - 3502 0651 51 .byte 0x51 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 83 - - - 3503 0652 9F .byte 0x9f - 3504 0653 26000000 .4byte .LVL70 - 3505 0657 30000000 .4byte .LFE14 - 3506 065b 0100 .2byte 0x1 - 3507 065d 51 .byte 0x51 - 3508 065e 00000000 .4byte 0 - 3509 0662 00000000 .4byte 0 - 3510 .LLST36: - 3511 0666 00000000 .4byte .LFB15 - 3512 066a 04000000 .4byte .LCFI3 - 3513 066e 0200 .2byte 0x2 - 3514 0670 7D .byte 0x7d - 3515 0671 00 .sleb128 0 - 3516 0672 04000000 .4byte .LCFI3 - 3517 0676 40000000 .4byte .LFE15 - 3518 067a 0200 .2byte 0x2 - 3519 067c 7D .byte 0x7d - 3520 067d 08 .sleb128 8 - 3521 067e 00000000 .4byte 0 - 3522 0682 00000000 .4byte 0 - 3523 .LLST37: - 3524 0686 00000000 .4byte .LVL72 - 3525 068a 18000000 .4byte .LVL75 - 3526 068e 0100 .2byte 0x1 - 3527 0690 50 .byte 0x50 - 3528 0691 18000000 .4byte .LVL75 - 3529 0695 3C000000 .4byte .LVL78 - 3530 0699 0400 .2byte 0x4 - 3531 069b F3 .byte 0xf3 - 3532 069c 01 .uleb128 0x1 - 3533 069d 50 .byte 0x50 - 3534 069e 9F .byte 0x9f - 3535 069f 3C000000 .4byte .LVL78 - 3536 06a3 3E000000 .4byte .LVL79 - 3537 06a7 0100 .2byte 0x1 - 3538 06a9 50 .byte 0x50 - 3539 06aa 3E000000 .4byte .LVL79 - 3540 06ae 40000000 .4byte .LFE15 - 3541 06b2 0400 .2byte 0x4 - 3542 06b4 F3 .byte 0xf3 - 3543 06b5 01 .uleb128 0x1 - 3544 06b6 50 .byte 0x50 - 3545 06b7 9F .byte 0x9f - 3546 06b8 00000000 .4byte 0 - 3547 06bc 00000000 .4byte 0 - 3548 .LLST38: - 3549 06c0 00000000 .4byte .LVL72 - 3550 06c4 0A000000 .4byte .LVL73 - 3551 06c8 0100 .2byte 0x1 - 3552 06ca 51 .byte 0x51 - 3553 06cb 0A000000 .4byte .LVL73 - 3554 06cf 3C000000 .4byte .LVL78 - 3555 06d3 0400 .2byte 0x4 - 3556 06d5 F3 .byte 0xf3 - 3557 06d6 01 .uleb128 0x1 - 3558 06d7 51 .byte 0x51 - 3559 06d8 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 84 - - - 3560 06d9 3C000000 .4byte .LVL78 - 3561 06dd 40000000 .4byte .LFE15 - 3562 06e1 0100 .2byte 0x1 - 3563 06e3 51 .byte 0x51 - 3564 06e4 00000000 .4byte 0 - 3565 06e8 00000000 .4byte 0 - 3566 .LLST39: - 3567 06ec 00000000 .4byte .LVL72 - 3568 06f0 10000000 .4byte .LVL74 - 3569 06f4 0100 .2byte 0x1 - 3570 06f6 52 .byte 0x52 - 3571 06f7 10000000 .4byte .LVL74 - 3572 06fb 3C000000 .4byte .LVL78 - 3573 06ff 0400 .2byte 0x4 - 3574 0701 F3 .byte 0xf3 - 3575 0702 01 .uleb128 0x1 - 3576 0703 52 .byte 0x52 - 3577 0704 9F .byte 0x9f - 3578 0705 3C000000 .4byte .LVL78 - 3579 0709 40000000 .4byte .LFE15 - 3580 070d 0100 .2byte 0x1 - 3581 070f 52 .byte 0x52 - 3582 0710 00000000 .4byte 0 - 3583 0714 00000000 .4byte 0 - 3584 .LLST40: - 3585 0718 00000000 .4byte .LVL72 - 3586 071c 1C000000 .4byte .LVL76 - 3587 0720 0100 .2byte 0x1 - 3588 0722 53 .byte 0x53 - 3589 0723 1C000000 .4byte .LVL76 - 3590 0727 3C000000 .4byte .LVL78 - 3591 072b 0400 .2byte 0x4 - 3592 072d F3 .byte 0xf3 - 3593 072e 01 .uleb128 0x1 - 3594 072f 53 .byte 0x53 - 3595 0730 9F .byte 0x9f - 3596 0731 3C000000 .4byte .LVL78 - 3597 0735 40000000 .4byte .LFE15 - 3598 0739 0100 .2byte 0x1 - 3599 073b 53 .byte 0x53 - 3600 073c 00000000 .4byte 0 - 3601 0740 00000000 .4byte 0 - 3602 .LLST41: - 3603 0744 00000000 .4byte .LVL72 - 3604 0748 3A000000 .4byte .LVL77 - 3605 074c 0200 .2byte 0x2 - 3606 074e 31 .byte 0x31 - 3607 074f 9F .byte 0x9f - 3608 0750 3A000000 .4byte .LVL77 - 3609 0754 3C000000 .4byte .LVL78 - 3610 0758 0200 .2byte 0x2 - 3611 075a 30 .byte 0x30 - 3612 075b 9F .byte 0x9f - 3613 075c 3C000000 .4byte .LVL78 - 3614 0760 3E000000 .4byte .LVL79 - 3615 0764 0200 .2byte 0x2 - 3616 0766 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 85 - - - 3617 0767 9F .byte 0x9f - 3618 0768 3E000000 .4byte .LVL79 - 3619 076c 40000000 .4byte .LFE15 - 3620 0770 0100 .2byte 0x1 - 3621 0772 50 .byte 0x50 - 3622 0773 00000000 .4byte 0 - 3623 0777 00000000 .4byte 0 - 3624 .LLST42: - 3625 077b 00000000 .4byte .LFB16 - 3626 077f 02000000 .4byte .LCFI4 - 3627 0783 0200 .2byte 0x2 - 3628 0785 7D .byte 0x7d - 3629 0786 00 .sleb128 0 - 3630 0787 02000000 .4byte .LCFI4 - 3631 078b 34000000 .4byte .LFE16 - 3632 078f 0200 .2byte 0x2 - 3633 0791 7D .byte 0x7d - 3634 0792 08 .sleb128 8 - 3635 0793 00000000 .4byte 0 - 3636 0797 00000000 .4byte 0 - 3637 .LLST43: - 3638 079b 06000000 .4byte .LVL81 - 3639 079f 29000000 .4byte .LVL85-1 - 3640 07a3 0100 .2byte 0x1 - 3641 07a5 50 .byte 0x50 - 3642 07a6 00000000 .4byte 0 - 3643 07aa 00000000 .4byte 0 - 3644 .LLST44: - 3645 07ae 00000000 .4byte .LVL80 - 3646 07b2 10000000 .4byte .LVL82 - 3647 07b6 0300 .2byte 0x3 - 3648 07b8 09 .byte 0x9 - 3649 07b9 FF .byte 0xff - 3650 07ba 9F .byte 0x9f - 3651 07bb 10000000 .4byte .LVL82 - 3652 07bf 24000000 .4byte .LVL83 - 3653 07c3 0500 .2byte 0x5 - 3654 07c5 03 .byte 0x3 - 3655 07c6 00000000 .4byte CyDmaTdFreeIndex - 3656 07ca 24000000 .4byte .LVL83 - 3657 07ce 26000000 .4byte .LVL84 - 3658 07d2 0300 .2byte 0x3 - 3659 07d4 09 .byte 0x9 - 3660 07d5 FF .byte 0xff - 3661 07d6 9F .byte 0x9f - 3662 07d7 26000000 .4byte .LVL84 - 3663 07db 34000000 .4byte .LFE16 - 3664 07df 0100 .2byte 0x1 - 3665 07e1 54 .byte 0x54 - 3666 07e2 00000000 .4byte 0 - 3667 07e6 00000000 .4byte 0 - 3668 .LLST45: - 3669 07ea 00000000 .4byte .LFB17 - 3670 07ee 04000000 .4byte .LCFI5 - 3671 07f2 0200 .2byte 0x2 - 3672 07f4 7D .byte 0x7d - 3673 07f5 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 86 - - - 3674 07f6 04000000 .4byte .LCFI5 - 3675 07fa 34000000 .4byte .LFE17 - 3676 07fe 0200 .2byte 0x2 - 3677 0800 7D .byte 0x7d - 3678 0801 08 .sleb128 8 - 3679 0802 00000000 .4byte 0 - 3680 0806 00000000 .4byte 0 - 3681 .LLST46: - 3682 080a 00000000 .4byte .LVL86 - 3683 080e 0B000000 .4byte .LVL87-1 - 3684 0812 0100 .2byte 0x1 - 3685 0814 50 .byte 0x50 - 3686 0815 0B000000 .4byte .LVL87-1 - 3687 0819 2C000000 .4byte .LVL88 - 3688 081d 0400 .2byte 0x4 - 3689 081f F3 .byte 0xf3 - 3690 0820 01 .uleb128 0x1 - 3691 0821 50 .byte 0x50 - 3692 0822 9F .byte 0x9f - 3693 0823 2C000000 .4byte .LVL88 - 3694 0827 34000000 .4byte .LFE17 - 3695 082b 0100 .2byte 0x1 - 3696 082d 50 .byte 0x50 - 3697 082e 00000000 .4byte 0 - 3698 0832 00000000 .4byte 0 - 3699 .LLST47: - 3700 0836 0C000000 .4byte .LVL87 - 3701 083a 2B000000 .4byte .LVL88-1 - 3702 083e 0100 .2byte 0x1 - 3703 0840 50 .byte 0x50 - 3704 0841 00000000 .4byte 0 - 3705 0845 00000000 .4byte 0 - 3706 .LLST48: - 3707 0849 00000000 .4byte .LFB19 - 3708 084d 06000000 .4byte .LCFI6 - 3709 0851 0200 .2byte 0x2 - 3710 0853 7D .byte 0x7d - 3711 0854 00 .sleb128 0 - 3712 0855 06000000 .4byte .LCFI6 - 3713 0859 26000000 .4byte .LFE19 - 3714 085d 0200 .2byte 0x2 - 3715 085f 7D .byte 0x7d - 3716 0860 0C .sleb128 12 - 3717 0861 00000000 .4byte 0 - 3718 0865 00000000 .4byte 0 - 3719 .LLST49: - 3720 0869 00000000 .4byte .LVL89 - 3721 086d 14000000 .4byte .LVL90 - 3722 0871 0100 .2byte 0x1 - 3723 0873 50 .byte 0x50 - 3724 0874 14000000 .4byte .LVL90 - 3725 0878 22000000 .4byte .LVL93 - 3726 087c 0400 .2byte 0x4 - 3727 087e F3 .byte 0xf3 - 3728 087f 01 .uleb128 0x1 - 3729 0880 50 .byte 0x50 - 3730 0881 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 87 - - - 3731 0882 22000000 .4byte .LVL93 - 3732 0886 24000000 .4byte .LVL94 - 3733 088a 0100 .2byte 0x1 - 3734 088c 50 .byte 0x50 - 3735 088d 24000000 .4byte .LVL94 - 3736 0891 26000000 .4byte .LFE19 - 3737 0895 0400 .2byte 0x4 - 3738 0897 F3 .byte 0xf3 - 3739 0898 01 .uleb128 0x1 - 3740 0899 50 .byte 0x50 - 3741 089a 9F .byte 0x9f - 3742 089b 00000000 .4byte 0 - 3743 089f 00000000 .4byte 0 - 3744 .LLST50: - 3745 08a3 00000000 .4byte .LVL89 - 3746 08a7 20000000 .4byte .LVL92 - 3747 08ab 0200 .2byte 0x2 - 3748 08ad 31 .byte 0x31 - 3749 08ae 9F .byte 0x9f - 3750 08af 20000000 .4byte .LVL92 - 3751 08b3 22000000 .4byte .LVL93 - 3752 08b7 0200 .2byte 0x2 - 3753 08b9 30 .byte 0x30 - 3754 08ba 9F .byte 0x9f - 3755 08bb 22000000 .4byte .LVL93 - 3756 08bf 24000000 .4byte .LVL94 - 3757 08c3 0200 .2byte 0x2 - 3758 08c5 31 .byte 0x31 - 3759 08c6 9F .byte 0x9f - 3760 08c7 24000000 .4byte .LVL94 - 3761 08cb 26000000 .4byte .LFE19 - 3762 08cf 0100 .2byte 0x1 - 3763 08d1 50 .byte 0x50 - 3764 08d2 00000000 .4byte 0 - 3765 08d6 00000000 .4byte 0 - 3766 .LLST51: - 3767 08da 18000000 .4byte .LVL91 - 3768 08de 22000000 .4byte .LVL93 - 3769 08e2 0100 .2byte 0x1 - 3770 08e4 54 .byte 0x54 - 3771 08e5 00000000 .4byte 0 - 3772 08e9 00000000 .4byte 0 - 3773 .LLST52: - 3774 08ed 00000000 .4byte .LFB20 - 3775 08f1 06000000 .4byte .LCFI7 - 3776 08f5 0200 .2byte 0x2 - 3777 08f7 7D .byte 0x7d - 3778 08f8 00 .sleb128 0 - 3779 08f9 06000000 .4byte .LCFI7 - 3780 08fd 44000000 .4byte .LFE20 - 3781 0901 0200 .2byte 0x2 - 3782 0903 7D .byte 0x7d - 3783 0904 08 .sleb128 8 - 3784 0905 00000000 .4byte 0 - 3785 0909 00000000 .4byte 0 - 3786 .LLST53: - 3787 090d 00000000 .4byte .LVL95 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 88 - - - 3788 0911 30000000 .4byte .LVL100 - 3789 0915 0100 .2byte 0x1 - 3790 0917 50 .byte 0x50 - 3791 0918 30000000 .4byte .LVL100 - 3792 091c 40000000 .4byte .LVL102 - 3793 0920 0400 .2byte 0x4 - 3794 0922 F3 .byte 0xf3 - 3795 0923 01 .uleb128 0x1 - 3796 0924 50 .byte 0x50 - 3797 0925 9F .byte 0x9f - 3798 0926 40000000 .4byte .LVL102 - 3799 092a 42000000 .4byte .LVL103 - 3800 092e 0100 .2byte 0x1 - 3801 0930 50 .byte 0x50 - 3802 0931 42000000 .4byte .LVL103 - 3803 0935 44000000 .4byte .LFE20 - 3804 0939 0400 .2byte 0x4 - 3805 093b F3 .byte 0xf3 - 3806 093c 01 .uleb128 0x1 - 3807 093d 50 .byte 0x50 - 3808 093e 9F .byte 0x9f - 3809 093f 00000000 .4byte 0 - 3810 0943 00000000 .4byte 0 - 3811 .LLST54: - 3812 0947 00000000 .4byte .LVL95 - 3813 094b 20000000 .4byte .LVL99 - 3814 094f 0100 .2byte 0x1 - 3815 0951 51 .byte 0x51 - 3816 0952 20000000 .4byte .LVL99 - 3817 0956 40000000 .4byte .LVL102 - 3818 095a 0400 .2byte 0x4 - 3819 095c F3 .byte 0xf3 - 3820 095d 01 .uleb128 0x1 - 3821 095e 51 .byte 0x51 - 3822 095f 9F .byte 0x9f - 3823 0960 40000000 .4byte .LVL102 - 3824 0964 44000000 .4byte .LFE20 - 3825 0968 0100 .2byte 0x1 - 3826 096a 51 .byte 0x51 - 3827 096b 00000000 .4byte 0 - 3828 096f 00000000 .4byte 0 - 3829 .LLST55: - 3830 0973 00000000 .4byte .LVL95 - 3831 0977 34000000 .4byte .LVL101 - 3832 097b 0100 .2byte 0x1 - 3833 097d 52 .byte 0x52 - 3834 097e 34000000 .4byte .LVL101 - 3835 0982 40000000 .4byte .LVL102 - 3836 0986 0400 .2byte 0x4 - 3837 0988 F3 .byte 0xf3 - 3838 0989 01 .uleb128 0x1 - 3839 098a 52 .byte 0x52 - 3840 098b 9F .byte 0x9f - 3841 098c 40000000 .4byte .LVL102 - 3842 0990 44000000 .4byte .LFE20 - 3843 0994 0100 .2byte 0x1 - 3844 0996 52 .byte 0x52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 89 - - - 3845 0997 00000000 .4byte 0 - 3846 099b 00000000 .4byte 0 - 3847 .LLST56: - 3848 099f 14000000 .4byte .LVL96 - 3849 09a3 16000000 .4byte .LVL97 - 3850 09a7 0100 .2byte 0x1 - 3851 09a9 54 .byte 0x54 - 3852 09aa 16000000 .4byte .LVL97 - 3853 09ae 1C000000 .4byte .LVL98 - 3854 09b2 0B00 .2byte 0xb - 3855 09b4 70 .byte 0x70 - 3856 09b5 00 .sleb128 0 - 3857 09b6 33 .byte 0x33 - 3858 09b7 24 .byte 0x24 - 3859 09b8 23 .byte 0x23 - 3860 09b9 80F08180 .uleb128 0x40007800 - 3860 04 - 3861 09be 9F .byte 0x9f - 3862 09bf 00000000 .4byte 0 - 3863 09c3 00000000 .4byte 0 - 3864 .LLST57: - 3865 09c7 00000000 .4byte .LVL104 - 3866 09cb 06000000 .4byte .LVL105 - 3867 09cf 0100 .2byte 0x1 - 3868 09d1 50 .byte 0x50 - 3869 09d2 06000000 .4byte .LVL105 - 3870 09d6 16000000 .4byte .LVL110 - 3871 09da 0400 .2byte 0x4 - 3872 09dc F3 .byte 0xf3 - 3873 09dd 01 .uleb128 0x1 - 3874 09de 50 .byte 0x50 - 3875 09df 9F .byte 0x9f - 3876 09e0 16000000 .4byte .LVL110 - 3877 09e4 18000000 .4byte .LVL111 - 3878 09e8 0100 .2byte 0x1 - 3879 09ea 50 .byte 0x50 - 3880 09eb 18000000 .4byte .LVL111 - 3881 09ef 1A000000 .4byte .LFE21 - 3882 09f3 0400 .2byte 0x4 - 3883 09f5 F3 .byte 0xf3 - 3884 09f6 01 .uleb128 0x1 - 3885 09f7 50 .byte 0x50 - 3886 09f8 9F .byte 0x9f - 3887 09f9 00000000 .4byte 0 - 3888 09fd 00000000 .4byte 0 - 3889 .LLST58: - 3890 0a01 00000000 .4byte .LVL104 - 3891 0a05 12000000 .4byte .LVL108 - 3892 0a09 0200 .2byte 0x2 - 3893 0a0b 31 .byte 0x31 - 3894 0a0c 9F .byte 0x9f - 3895 0a0d 12000000 .4byte .LVL108 - 3896 0a11 16000000 .4byte .LVL110 - 3897 0a15 0200 .2byte 0x2 - 3898 0a17 30 .byte 0x30 - 3899 0a18 9F .byte 0x9f - 3900 0a19 16000000 .4byte .LVL110 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 90 - - - 3901 0a1d 18000000 .4byte .LVL111 - 3902 0a21 0200 .2byte 0x2 - 3903 0a23 31 .byte 0x31 - 3904 0a24 9F .byte 0x9f - 3905 0a25 18000000 .4byte .LVL111 - 3906 0a29 1A000000 .4byte .LFE21 - 3907 0a2d 0100 .2byte 0x1 - 3908 0a2f 50 .byte 0x50 - 3909 0a30 00000000 .4byte 0 - 3910 0a34 00000000 .4byte 0 - 3911 .LLST59: - 3912 0a38 0E000000 .4byte .LVL106 - 3913 0a3c 10000000 .4byte .LVL107 - 3914 0a40 0300 .2byte 0x3 - 3915 0a42 70 .byte 0x70 - 3916 0a43 04 .sleb128 4 - 3917 0a44 9F .byte 0x9f - 3918 0a45 10000000 .4byte .LVL107 - 3919 0a49 14000000 .4byte .LVL109 - 3920 0a4d 0300 .2byte 0x3 - 3921 0a4f 70 .byte 0x70 - 3922 0a50 06 .sleb128 6 - 3923 0a51 9F .byte 0x9f - 3924 0a52 14000000 .4byte .LVL109 - 3925 0a56 16000000 .4byte .LVL110 - 3926 0a5a 0500 .2byte 0x5 - 3927 0a5c 73 .byte 0x73 - 3928 0a5d 86F001 .sleb128 30726 - 3929 0a60 9F .byte 0x9f - 3930 0a61 00000000 .4byte 0 - 3931 0a65 00000000 .4byte 0 - 3932 .LLST60: - 3933 0a69 00000000 .4byte .LVL112 - 3934 0a6d 18000000 .4byte .LVL116 - 3935 0a71 0100 .2byte 0x1 - 3936 0a73 50 .byte 0x50 - 3937 0a74 18000000 .4byte .LVL116 - 3938 0a78 28000000 .4byte .LVL120 - 3939 0a7c 0400 .2byte 0x4 - 3940 0a7e F3 .byte 0xf3 - 3941 0a7f 01 .uleb128 0x1 - 3942 0a80 50 .byte 0x50 - 3943 0a81 9F .byte 0x9f - 3944 0a82 28000000 .4byte .LVL120 - 3945 0a86 2A000000 .4byte .LVL121 - 3946 0a8a 0100 .2byte 0x1 - 3947 0a8c 50 .byte 0x50 - 3948 0a8d 2A000000 .4byte .LVL121 - 3949 0a91 2C000000 .4byte .LFE22 - 3950 0a95 0400 .2byte 0x4 - 3951 0a97 F3 .byte 0xf3 - 3952 0a98 01 .uleb128 0x1 - 3953 0a99 50 .byte 0x50 - 3954 0a9a 9F .byte 0x9f - 3955 0a9b 00000000 .4byte 0 - 3956 0a9f 00000000 .4byte 0 - 3957 .LLST61: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 91 - - - 3958 0aa3 00000000 .4byte .LVL112 - 3959 0aa7 1C000000 .4byte .LVL117 - 3960 0aab 0100 .2byte 0x1 - 3961 0aad 51 .byte 0x51 - 3962 0aae 1C000000 .4byte .LVL117 - 3963 0ab2 28000000 .4byte .LVL120 - 3964 0ab6 0400 .2byte 0x4 - 3965 0ab8 F3 .byte 0xf3 - 3966 0ab9 01 .uleb128 0x1 - 3967 0aba 51 .byte 0x51 - 3968 0abb 9F .byte 0x9f - 3969 0abc 28000000 .4byte .LVL120 - 3970 0ac0 2C000000 .4byte .LFE22 - 3971 0ac4 0100 .2byte 0x1 - 3972 0ac6 51 .byte 0x51 - 3973 0ac7 00000000 .4byte 0 - 3974 0acb 00000000 .4byte 0 - 3975 .LLST62: - 3976 0acf 10000000 .4byte .LVL113 - 3977 0ad3 12000000 .4byte .LVL114 - 3978 0ad7 0300 .2byte 0x3 - 3979 0ad9 73 .byte 0x73 - 3980 0ada 04 .sleb128 4 - 3981 0adb 9F .byte 0x9f - 3982 0adc 12000000 .4byte .LVL114 - 3983 0ae0 14000000 .4byte .LVL115 - 3984 0ae4 0B00 .2byte 0xb - 3985 0ae6 70 .byte 0x70 - 3986 0ae7 00 .sleb128 0 - 3987 0ae8 33 .byte 0x33 - 3988 0ae9 24 .byte 0x24 - 3989 0aea 23 .byte 0x23 - 3990 0aeb 84F08180 .uleb128 0x40007804 - 3990 04 - 3991 0af0 9F .byte 0x9f - 3992 0af1 20000000 .4byte .LVL118 - 3993 0af5 24000000 .4byte .LVL119 - 3994 0af9 0300 .2byte 0x3 - 3995 0afb 73 .byte 0x73 - 3996 0afc 06 .sleb128 6 - 3997 0afd 9F .byte 0x9f - 3998 0afe 00000000 .4byte 0 - 3999 0b02 00000000 .4byte 0 - 4000 .LLST63: - 4001 0b06 00000000 .4byte .LVL122 - 4002 0b0a 0C000000 .4byte .LVL123 - 4003 0b0e 0100 .2byte 0x1 - 4004 0b10 50 .byte 0x50 - 4005 0b11 0C000000 .4byte .LVL123 - 4006 0b15 16000000 .4byte .LVL125 - 4007 0b19 0400 .2byte 0x4 - 4008 0b1b F3 .byte 0xf3 - 4009 0b1c 01 .uleb128 0x1 - 4010 0b1d 50 .byte 0x50 - 4011 0b1e 9F .byte 0x9f - 4012 0b1f 16000000 .4byte .LVL125 - 4013 0b23 18000000 .4byte .LVL126 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 92 - - - 4014 0b27 0100 .2byte 0x1 - 4015 0b29 50 .byte 0x50 - 4016 0b2a 18000000 .4byte .LVL126 - 4017 0b2e 20000000 .4byte .LVL128 - 4018 0b32 0400 .2byte 0x4 - 4019 0b34 F3 .byte 0xf3 - 4020 0b35 01 .uleb128 0x1 - 4021 0b36 50 .byte 0x50 - 4022 0b37 9F .byte 0x9f - 4023 0b38 20000000 .4byte .LVL128 - 4024 0b3c 22000000 .4byte .LVL129 - 4025 0b40 0100 .2byte 0x1 - 4026 0b42 50 .byte 0x50 - 4027 0b43 22000000 .4byte .LVL129 - 4028 0b47 28000000 .4byte .LFE23 - 4029 0b4b 0400 .2byte 0x4 - 4030 0b4d F3 .byte 0xf3 - 4031 0b4e 01 .uleb128 0x1 - 4032 0b4f 50 .byte 0x50 - 4033 0b50 9F .byte 0x9f - 4034 0b51 00000000 .4byte 0 - 4035 0b55 00000000 .4byte 0 - 4036 .LLST64: - 4037 0b59 00000000 .4byte .LVL122 - 4038 0b5d 10000000 .4byte .LVL124 - 4039 0b61 0100 .2byte 0x1 - 4040 0b63 51 .byte 0x51 - 4041 0b64 10000000 .4byte .LVL124 - 4042 0b68 16000000 .4byte .LVL125 - 4043 0b6c 0400 .2byte 0x4 - 4044 0b6e F3 .byte 0xf3 - 4045 0b6f 01 .uleb128 0x1 - 4046 0b70 51 .byte 0x51 - 4047 0b71 9F .byte 0x9f - 4048 0b72 16000000 .4byte .LVL125 - 4049 0b76 1C000000 .4byte .LVL127 - 4050 0b7a 0100 .2byte 0x1 - 4051 0b7c 51 .byte 0x51 - 4052 0b7d 1C000000 .4byte .LVL127 - 4053 0b81 20000000 .4byte .LVL128 - 4054 0b85 0400 .2byte 0x4 - 4055 0b87 F3 .byte 0xf3 - 4056 0b88 01 .uleb128 0x1 - 4057 0b89 51 .byte 0x51 - 4058 0b8a 9F .byte 0x9f - 4059 0b8b 20000000 .4byte .LVL128 - 4060 0b8f 28000000 .4byte .LFE23 - 4061 0b93 0100 .2byte 0x1 - 4062 0b95 51 .byte 0x51 - 4063 0b96 00000000 .4byte 0 - 4064 0b9a 00000000 .4byte 0 - 4065 .LLST65: - 4066 0b9e 00000000 .4byte .LVL122 - 4067 0ba2 22000000 .4byte .LVL129 - 4068 0ba6 0200 .2byte 0x2 - 4069 0ba8 31 .byte 0x31 - 4070 0ba9 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 93 - - - 4071 0baa 22000000 .4byte .LVL129 - 4072 0bae 28000000 .4byte .LFE23 - 4073 0bb2 0100 .2byte 0x1 - 4074 0bb4 50 .byte 0x50 - 4075 0bb5 00000000 .4byte 0 - 4076 0bb9 00000000 .4byte 0 - 4077 .section .debug_aranges,"",%progbits - 4078 0000 D4000000 .4byte 0xd4 - 4079 0004 0200 .2byte 0x2 - 4080 0006 00000000 .4byte .Ldebug_info0 - 4081 000a 04 .byte 0x4 - 4082 000b 00 .byte 0 - 4083 000c 0000 .2byte 0 - 4084 000e 0000 .2byte 0 - 4085 0010 00000000 .4byte .LFB0 - 4086 0014 30000000 .4byte .LFE0-.LFB0 - 4087 0018 00000000 .4byte .LFB1 - 4088 001c 10000000 .4byte .LFE1-.LFB1 - 4089 0020 00000000 .4byte .LFB2 - 4090 0024 10000000 .4byte .LFE2-.LFB2 - 4091 0028 00000000 .4byte .LFB3 - 4092 002c 0C000000 .4byte .LFE3-.LFB3 - 4093 0030 00000000 .4byte .LFB4 - 4094 0034 34000000 .4byte .LFE4-.LFB4 - 4095 0038 00000000 .4byte .LFB5 - 4096 003c 30000000 .4byte .LFE5-.LFB5 - 4097 0040 00000000 .4byte .LFB6 - 4098 0044 34000000 .4byte .LFE6-.LFB6 - 4099 0048 00000000 .4byte .LFB7 - 4100 004c 24000000 .4byte .LFE7-.LFB7 - 4101 0050 00000000 .4byte .LFB8 - 4102 0054 28000000 .4byte .LFE8-.LFB8 - 4103 0058 00000000 .4byte .LFB9 - 4104 005c 24000000 .4byte .LFE9-.LFB9 - 4105 0060 00000000 .4byte .LFB10 - 4106 0064 2E000000 .4byte .LFE10-.LFB10 - 4107 0068 00000000 .4byte .LFB11 - 4108 006c 18000000 .4byte .LFE11-.LFB11 - 4109 0070 00000000 .4byte .LFB12 - 4110 0074 24000000 .4byte .LFE12-.LFB12 - 4111 0078 00000000 .4byte .LFB13 - 4112 007c 1C000000 .4byte .LFE13-.LFB13 - 4113 0080 00000000 .4byte .LFB14 - 4114 0084 30000000 .4byte .LFE14-.LFB14 - 4115 0088 00000000 .4byte .LFB15 - 4116 008c 40000000 .4byte .LFE15-.LFB15 - 4117 0090 00000000 .4byte .LFB16 - 4118 0094 34000000 .4byte .LFE16-.LFB16 - 4119 0098 00000000 .4byte .LFB17 - 4120 009c 34000000 .4byte .LFE17-.LFB17 - 4121 00a0 00000000 .4byte .LFB18 - 4122 00a4 10000000 .4byte .LFE18-.LFB18 - 4123 00a8 00000000 .4byte .LFB19 - 4124 00ac 26000000 .4byte .LFE19-.LFB19 - 4125 00b0 00000000 .4byte .LFB20 - 4126 00b4 44000000 .4byte .LFE20-.LFB20 - 4127 00b8 00000000 .4byte .LFB21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 94 - - - 4128 00bc 1A000000 .4byte .LFE21-.LFB21 - 4129 00c0 00000000 .4byte .LFB22 - 4130 00c4 2C000000 .4byte .LFE22-.LFB22 - 4131 00c8 00000000 .4byte .LFB23 - 4132 00cc 28000000 .4byte .LFE23-.LFB23 - 4133 00d0 00000000 .4byte 0 - 4134 00d4 00000000 .4byte 0 - 4135 .section .debug_ranges,"",%progbits - 4136 .Ldebug_ranges0: - 4137 0000 08000000 .4byte .LBB2 - 4138 0004 24000000 .4byte .LBE2 - 4139 0008 28000000 .4byte .LBB3 - 4140 000c 34000000 .4byte .LBE3 - 4141 0010 00000000 .4byte 0 - 4142 0014 00000000 .4byte 0 - 4143 0018 00000000 .4byte .LFB0 - 4144 001c 30000000 .4byte .LFE0 - 4145 0020 00000000 .4byte .LFB1 - 4146 0024 10000000 .4byte .LFE1 - 4147 0028 00000000 .4byte .LFB2 - 4148 002c 10000000 .4byte .LFE2 - 4149 0030 00000000 .4byte .LFB3 - 4150 0034 0C000000 .4byte .LFE3 - 4151 0038 00000000 .4byte .LFB4 - 4152 003c 34000000 .4byte .LFE4 - 4153 0040 00000000 .4byte .LFB5 - 4154 0044 30000000 .4byte .LFE5 - 4155 0048 00000000 .4byte .LFB6 - 4156 004c 34000000 .4byte .LFE6 - 4157 0050 00000000 .4byte .LFB7 - 4158 0054 24000000 .4byte .LFE7 - 4159 0058 00000000 .4byte .LFB8 - 4160 005c 28000000 .4byte .LFE8 - 4161 0060 00000000 .4byte .LFB9 - 4162 0064 24000000 .4byte .LFE9 - 4163 0068 00000000 .4byte .LFB10 - 4164 006c 2E000000 .4byte .LFE10 - 4165 0070 00000000 .4byte .LFB11 - 4166 0074 18000000 .4byte .LFE11 - 4167 0078 00000000 .4byte .LFB12 - 4168 007c 24000000 .4byte .LFE12 - 4169 0080 00000000 .4byte .LFB13 - 4170 0084 1C000000 .4byte .LFE13 - 4171 0088 00000000 .4byte .LFB14 - 4172 008c 30000000 .4byte .LFE14 - 4173 0090 00000000 .4byte .LFB15 - 4174 0094 40000000 .4byte .LFE15 - 4175 0098 00000000 .4byte .LFB16 - 4176 009c 34000000 .4byte .LFE16 - 4177 00a0 00000000 .4byte .LFB17 - 4178 00a4 34000000 .4byte .LFE17 - 4179 00a8 00000000 .4byte .LFB18 - 4180 00ac 10000000 .4byte .LFE18 - 4181 00b0 00000000 .4byte .LFB19 - 4182 00b4 26000000 .4byte .LFE19 - 4183 00b8 00000000 .4byte .LFB20 - 4184 00bc 44000000 .4byte .LFE20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 95 - - - 4185 00c0 00000000 .4byte .LFB21 - 4186 00c4 1A000000 .4byte .LFE21 - 4187 00c8 00000000 .4byte .LFB22 - 4188 00cc 2C000000 .4byte .LFE22 - 4189 00d0 00000000 .4byte .LFB23 - 4190 00d4 28000000 .4byte .LFE23 - 4191 00d8 00000000 .4byte 0 - 4192 00dc 00000000 .4byte 0 - 4193 .section .debug_line,"",%progbits - 4194 .Ldebug_line0: - 4195 0000 E9020000 .section .debug_str,"MS",%progbits,1 - 4195 02005C00 - 4195 00000201 - 4195 FB0E0D00 - 4195 01010101 - 4196 .LASF10: - 4197 0000 75696E74 .ascii "uint16\000" - 4197 313600 - 4198 .LASF89: - 4199 0007 43794578 .ascii "CyExitCriticalSection\000" - 4199 69744372 - 4199 69746963 - 4199 616C5365 - 4199 6374696F - 4200 .LASF28: - 4201 001d 646D6163 .ascii "dmac_cfgmem\000" - 4201 5F636667 - 4201 6D656D00 - 4202 .LASF34: - 4203 0029 4379446D .ascii "CyDmacErrorAddress\000" - 4203 61634572 - 4203 726F7241 - 4203 64647265 - 4203 737300 - 4204 .LASF68: - 4205 003c 4379446D .ascii "CyDmaTdAllocate\000" - 4205 61546441 - 4205 6C6C6F63 - 4205 61746500 - 4206 .LASF70: - 4207 004c 4379446D .ascii "CyDmaTdFree\000" - 4207 61546446 - 4207 72656500 - 4208 .LASF43: - 4209 0058 4379446D .ascii "CyDmaChEnable\000" - 4209 61436845 - 4209 6E61626C - 4209 6500 - 4210 .LASF72: - 4211 0066 4379446D .ascii "CyDmaTdFreeCount\000" - 4211 61546446 - 4211 72656543 - 4211 6F756E74 - 4211 00 - 4212 .LASF31: - 4213 0077 4379446D .ascii "CyDmacConfigure\000" - 4213 6163436F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 96 - - - 4213 6E666967 - 4213 75726500 - 4214 .LASF7: - 4215 0087 6C6F6E67 .ascii "long long unsigned int\000" - 4215 206C6F6E - 4215 6720756E - 4215 7369676E - 4215 65642069 - 4216 .LASF73: - 4217 009e 4379446D .ascii "CyDmaTdSetConfiguration\000" - 4217 61546453 - 4217 6574436F - 4217 6E666967 - 4217 75726174 - 4218 .LASF71: - 4219 00b6 74644861 .ascii "tdHandle\000" - 4219 6E646C65 - 4219 00 - 4220 .LASF6: - 4221 00bf 6C6F6E67 .ascii "long long int\000" - 4221 206C6F6E - 4221 6720696E - 4221 7400 - 4222 .LASF0: - 4223 00cd 7369676E .ascii "signed char\000" - 4223 65642063 - 4223 68617200 - 4224 .LASF36: - 4225 00d9 696E7465 .ascii "interruptState\000" - 4225 72727570 - 4225 74537461 - 4225 746500 - 4226 .LASF81: - 4227 00e8 656E6162 .ascii "enableRR\000" - 4227 6C655252 - 4227 00 - 4228 .LASF29: - 4229 00f1 646D6163 .ascii "dmac_tdmem_struct\000" - 4229 5F74646D - 4229 656D5F73 - 4229 74727563 - 4229 7400 - 4230 .LASF61: - 4231 0103 73746174 .ascii "state\000" - 4231 6500 - 4232 .LASF4: - 4233 0109 6C6F6E67 .ascii "long int\000" - 4233 20696E74 - 4233 00 - 4234 .LASF65: - 4235 0112 7464446F .ascii "tdDone0\000" - 4235 6E653000 - 4236 .LASF66: - 4237 011a 7464446F .ascii "tdDone1\000" - 4237 6E653100 - 4238 .LASF16: - 4239 0122 72656731 .ascii "reg16\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 97 - - - 4239 3600 - 4240 .LASF9: - 4241 0128 75696E74 .ascii "uint8\000" - 4241 3800 - 4242 .LASF13: - 4243 012e 646F7562 .ascii "double\000" - 4243 6C6500 - 4244 .LASF84: - 4245 0135 4379446D .ascii "CyDmaChannels\000" - 4245 61436861 - 4245 6E6E656C - 4245 7300 - 4246 .LASF11: - 4247 0143 75696E74 .ascii "uint32\000" - 4247 333200 - 4248 .LASF20: - 4249 014a 61637469 .ascii "action\000" - 4249 6F6E00 - 4250 .LASF22: - 4251 0151 72657365 .ascii "reserved\000" - 4251 72766564 - 4251 00 - 4252 .LASF49: - 4253 015a 76616C75 .ascii "value\000" - 4253 6500 - 4254 .LASF52: - 4255 0160 64657374 .ascii "destination\000" - 4255 696E6174 - 4255 696F6E00 - 4256 .LASF47: - 4257 016c 4379446D .ascii "CyDmaChPriority\000" - 4257 61436850 - 4257 72696F72 - 4257 69747900 - 4258 .LASF8: - 4259 017c 756E7369 .ascii "unsigned int\000" - 4259 676E6564 - 4259 20696E74 - 4259 00 - 4260 .LASF5: - 4261 0189 6C6F6E67 .ascii "long unsigned int\000" - 4261 20756E73 - 4261 69676E65 - 4261 6420696E - 4261 7400 - 4262 .LASF25: - 4263 019b 646D6163 .ascii "dmac_cfgmem_struct\000" - 4263 5F636667 - 4263 6D656D5F - 4263 73747275 - 4263 637400 - 4264 .LASF86: - 4265 01ae 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\CyDmac.c\000" - 4265 6E657261 - 4265 7465645F - 4265 536F7572 - 4265 63655C50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 98 - - - 4266 .LASF50: - 4267 01d0 4379446D .ascii "CyDmaChSetExtendedAddress\000" - 4267 61436853 - 4267 65744578 - 4267 74656E64 - 4267 65644164 - 4268 .LASF82: - 4269 01ea 4379446D .ascii "CyDmaTdCurrentNumber\000" - 4269 61546443 - 4269 75727265 - 4269 6E744E75 - 4269 6D626572 - 4270 .LASF19: - 4271 01ff 62617369 .ascii "basic_cfg\000" - 4271 635F6366 - 4271 6700 - 4272 .LASF3: - 4273 0209 73686F72 .ascii "short unsigned int\000" - 4273 7420756E - 4273 7369676E - 4273 65642069 - 4273 6E7400 - 4274 .LASF76: - 4275 021c 636F6E66 .ascii "configuration\000" - 4275 69677572 - 4275 6174696F - 4275 6E00 - 4276 .LASF33: - 4277 022a 4379446D .ascii "CyDmacError\000" - 4277 61634572 - 4277 726F7200 - 4278 .LASF88: - 4279 0236 4379456E .ascii "CyEnterCriticalSection\000" - 4279 74657243 - 4279 72697469 - 4279 63616C53 - 4279 65637469 - 4280 .LASF32: - 4281 024d 4379446D .ascii "CyDmacClearError\000" - 4281 6163436C - 4281 65617245 - 4281 72726F72 - 4281 00 - 4282 .LASF87: - 4283 025e 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 4283 43534932 - 4283 53445C73 - 4283 6F667477 - 4283 6172655C - 4284 028d 6E00 .ascii "n\000" - 4285 .LASF17: - 4286 028f 72656733 .ascii "reg32\000" - 4286 3200 - 4287 .LASF51: - 4288 0295 736F7572 .ascii "source\000" - 4288 636500 - 4289 .LASF21: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc1lqS7m.s page 99 - - - 4290 029c 62617369 .ascii "basic_status\000" - 4290 635F7374 - 4290 61747573 - 4290 00 - 4291 .LASF18: - 4292 02a9 73697A65 .ascii "sizetype\000" - 4292 74797065 - 4292 00 - 4293 .LASF80: - 4294 02b2 4379446D .ascii "CyDmaChRoundRobin\000" - 4294 61436852 - 4294 6F756E64 - 4294 526F6269 - 4294 6E00 - 4295 .LASF78: - 4296 02c4 4379446D .ascii "CyDmaTdSetAddress\000" - 4296 61546453 - 4296 65744164 - 4296 64726573 - 4296 7300 - 4297 .LASF35: - 4298 02d6 646D6149 .ascii "dmaIndex\000" - 4298 6E646578 - 4298 00 - 4299 .LASF46: - 4300 02df 4379446D .ascii "CyDmaClearPendingDrq\000" - 4300 61436C65 - 4300 61725065 - 4300 6E64696E - 4300 67447271 - 4301 .LASF63: - 4302 02f4 62757273 .ascii "burstCount\000" - 4302 74436F75 - 4302 6E7400 - 4303 .LASF12: - 4304 02ff 666C6F61 .ascii "float\000" - 4304 7400 - 4305 .LASF40: - 4306 0305 6572726F .ascii "error\000" - 4306 7200 - 4307 .LASF85: - 4308 030b 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 4308 4320342E - 4308 372E3320 - 4308 32303133 - 4308 30333132 - 4309 033e 616E6368 .ascii "anch revision 196615]\000" - 4309 20726576 - 4309 6973696F - 4309 6E203139 - 4309 36363135 - 4310 .LASF77: - 4311 0354 4379446D .ascii "CyDmaTdGetConfiguration\000" - 4311 61546447 - 4311 6574436F - 4311 6E666967 - 4311 75726174 - ARM GAS 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- - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "CyFlash.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.CySetTempInt.part.0,"ax",%progbits - 19 .align 1 - 20 .thumb - 21 .thumb_func - 22 .type CySetTempInt.part.0, %function - 23 CySetTempInt.part.0: - 24 .LFB13: - 25 .file 1 ".\\Generated_Source\\PSoC5\\CyFlash.c" - 1:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/CyFlash.c **** * File Name: CyFlash.c - 3:.\Generated_Source\PSoC5/CyFlash.c **** * Version 4.0 - 4:.\Generated_Source\PSoC5/CyFlash.c **** * - 5:.\Generated_Source\PSoC5/CyFlash.c **** * Description: - 6:.\Generated_Source\PSoC5/CyFlash.c **** * Provides an API for the FLASH/EEPROM. - 7:.\Generated_Source\PSoC5/CyFlash.c **** * - 8:.\Generated_Source\PSoC5/CyFlash.c **** * Note: - 9:.\Generated_Source\PSoC5/CyFlash.c **** * This code is endian agnostic. - 10:.\Generated_Source\PSoC5/CyFlash.c **** * - 11:.\Generated_Source\PSoC5/CyFlash.c **** * Note: - 12:.\Generated_Source\PSoC5/CyFlash.c **** * Documentation of the API's in this file is located in the - 13:.\Generated_Source\PSoC5/CyFlash.c **** * System Reference Guide provided with PSoC Creator. - 14:.\Generated_Source\PSoC5/CyFlash.c **** * - 15:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 16:.\Generated_Source\PSoC5/CyFlash.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 17:.\Generated_Source\PSoC5/CyFlash.c **** * You may use this file only in accordance with the license, terms, conditions, - 18:.\Generated_Source\PSoC5/CyFlash.c **** * disclaimers, and limitations in the end user license agreement accompanying - 19:.\Generated_Source\PSoC5/CyFlash.c **** * the software package with which this file was provided. - 20:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 21:.\Generated_Source\PSoC5/CyFlash.c **** - 22:.\Generated_Source\PSoC5/CyFlash.c **** #include "CyFlash.h" - 23:.\Generated_Source\PSoC5/CyFlash.c **** - 24:.\Generated_Source\PSoC5/CyFlash.c **** - 25:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 26:.\Generated_Source\PSoC5/CyFlash.c **** * Holds die temperature, updated by CySetTemp(). Used for flash writting. - 27:.\Generated_Source\PSoC5/CyFlash.c **** * The first byte is the sign of the temperature (0 = negative, 1 = positive). - 28:.\Generated_Source\PSoC5/CyFlash.c **** * The second byte is the magnitude. - 29:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 30:.\Generated_Source\PSoC5/CyFlash.c **** uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; - 31:.\Generated_Source\PSoC5/CyFlash.c **** - 32:.\Generated_Source\PSoC5/CyFlash.c **** #if(CYDEV_ECC_ENABLE == 0) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 2 - - - 33:.\Generated_Source\PSoC5/CyFlash.c **** static uint8 * rowBuffer = 0; - 34:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CYDEV_ECC_ENABLE == 0) */ - 35:.\Generated_Source\PSoC5/CyFlash.c **** - 36:.\Generated_Source\PSoC5/CyFlash.c **** - 37:.\Generated_Source\PSoC5/CyFlash.c **** static cystatus CySetTempInt(void); - 38:.\Generated_Source\PSoC5/CyFlash.c **** - 39:.\Generated_Source\PSoC5/CyFlash.c **** - 40:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 41:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyFlash_Start - 42:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 43:.\Generated_Source\PSoC5/CyFlash.c **** * - 44:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 45:.\Generated_Source\PSoC5/CyFlash.c **** * Enable the Flash. - 46:.\Generated_Source\PSoC5/CyFlash.c **** * - 47:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 48:.\Generated_Source\PSoC5/CyFlash.c **** * None - 49:.\Generated_Source\PSoC5/CyFlash.c **** * - 50:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 51:.\Generated_Source\PSoC5/CyFlash.c **** * None - 52:.\Generated_Source\PSoC5/CyFlash.c **** * - 53:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 54:.\Generated_Source\PSoC5/CyFlash.c **** void CyFlash_Start(void) - 55:.\Generated_Source\PSoC5/CyFlash.c **** { - 56:.\Generated_Source\PSoC5/CyFlash.c **** /* Active Power Mode */ - 57:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; - 58:.\Generated_Source\PSoC5/CyFlash.c **** - 59:.\Generated_Source\PSoC5/CyFlash.c **** /* Standby Power Mode */ - 60:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; - 61:.\Generated_Source\PSoC5/CyFlash.c **** - 62:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(CY_FLASH_EE_STARTUP_DELAY); - 63:.\Generated_Source\PSoC5/CyFlash.c **** } - 64:.\Generated_Source\PSoC5/CyFlash.c **** - 65:.\Generated_Source\PSoC5/CyFlash.c **** - 66:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 67:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyFlash_Stop - 68:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 69:.\Generated_Source\PSoC5/CyFlash.c **** * - 70:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 71:.\Generated_Source\PSoC5/CyFlash.c **** * Disable the Flash. - 72:.\Generated_Source\PSoC5/CyFlash.c **** * - 73:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 74:.\Generated_Source\PSoC5/CyFlash.c **** * None - 75:.\Generated_Source\PSoC5/CyFlash.c **** * - 76:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 77:.\Generated_Source\PSoC5/CyFlash.c **** * None - 78:.\Generated_Source\PSoC5/CyFlash.c **** * - 79:.\Generated_Source\PSoC5/CyFlash.c **** * Side Effects: - 80:.\Generated_Source\PSoC5/CyFlash.c **** * This setting is ignored as long as the CPU is currently running. This will - 81:.\Generated_Source\PSoC5/CyFlash.c **** * only take effect when the CPU is later disabled. - 82:.\Generated_Source\PSoC5/CyFlash.c **** * - 83:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 84:.\Generated_Source\PSoC5/CyFlash.c **** void CyFlash_Stop(void) - 85:.\Generated_Source\PSoC5/CyFlash.c **** { - 86:.\Generated_Source\PSoC5/CyFlash.c **** /* Active Power Mode */ - 87:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); - 88:.\Generated_Source\PSoC5/CyFlash.c **** - 89:.\Generated_Source\PSoC5/CyFlash.c **** /* Standby Power Mode */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 3 - - - 90:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); - 91:.\Generated_Source\PSoC5/CyFlash.c **** } - 92:.\Generated_Source\PSoC5/CyFlash.c **** - 93:.\Generated_Source\PSoC5/CyFlash.c **** - 94:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 95:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CySetTempInt - 96:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 97:.\Generated_Source\PSoC5/CyFlash.c **** * - 98:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 99:.\Generated_Source\PSoC5/CyFlash.c **** * Sends a command to the SPC to read the die temperature. Sets a global value - 100:.\Generated_Source\PSoC5/CyFlash.c **** * used by the Write functions. This function must be called once before - 101:.\Generated_Source\PSoC5/CyFlash.c **** * executing a series of Flash writing functions. - 102:.\Generated_Source\PSoC5/CyFlash.c **** * - 103:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 104:.\Generated_Source\PSoC5/CyFlash.c **** * None - 105:.\Generated_Source\PSoC5/CyFlash.c **** * - 106:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 107:.\Generated_Source\PSoC5/CyFlash.c **** * status: - 108:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_SUCCESS - if successful - 109:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_LOCKED - if Flash writing already in use - 110:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_UNKNOWN - if there was an SPC error - 111:.\Generated_Source\PSoC5/CyFlash.c **** * - 112:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 113:.\Generated_Source\PSoC5/CyFlash.c **** static cystatus CySetTempInt(void) - 26 .loc 1 113 0 - 27 .cfi_startproc - 28 @ args = 0, pretend = 0, frame = 0 - 29 @ frame_needed = 0, uses_anonymous_args = 0 - 114:.\Generated_Source\PSoC5/CyFlash.c **** { - 115:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status; - 116:.\Generated_Source\PSoC5/CyFlash.c **** - 117:.\Generated_Source\PSoC5/CyFlash.c **** /* Make sure SPC is powered */ - 118:.\Generated_Source\PSoC5/CyFlash.c **** CySpcStart(); - 119:.\Generated_Source\PSoC5/CyFlash.c **** - 120:.\Generated_Source\PSoC5/CyFlash.c **** /* Plan for failure. */ - 121:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_UNKNOWN; - 122:.\Generated_Source\PSoC5/CyFlash.c **** - 123:.\Generated_Source\PSoC5/CyFlash.c **** if(CySpcLock() == CYRET_SUCCESS) - 124:.\Generated_Source\PSoC5/CyFlash.c **** { - 125:.\Generated_Source\PSoC5/CyFlash.c **** /* Write the command. */ - 126:.\Generated_Source\PSoC5/CyFlash.c **** if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) - 30 .loc 1 126 0 - 31 0000 0120 movs r0, #1 - 113:.\Generated_Source\PSoC5/CyFlash.c **** static cystatus CySetTempInt(void) - 32 .loc 1 113 0 - 33 0002 10B5 push {r4, lr} - 34 .LCFI0: - 35 .cfi_def_cfa_offset 8 - 36 .cfi_offset 4, -8 - 37 .cfi_offset 14, -4 - 38 .loc 1 126 0 - 39 0004 FFF7FEFF bl CySpcGetTemp - 40 .LVL0: - 41 0008 0728 cmp r0, #7 - 42 000a 09D0 beq .L14 - 43 .L7: - 121:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_UNKNOWN; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 4 - - - 44 .loc 1 121 0 - 45 000c 4FF0FF34 mov r4, #-1 - 46 0010 17E0 b .L3 - 47 .L20: - 127:.\Generated_Source\PSoC5/CyFlash.c **** { - 128:.\Generated_Source\PSoC5/CyFlash.c **** do - 129:.\Generated_Source\PSoC5/CyFlash.c **** { - 130:.\Generated_Source\PSoC5/CyFlash.c **** if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_ - 131:.\Generated_Source\PSoC5/CyFlash.c **** { - 132:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_SUCCESS; - 133:.\Generated_Source\PSoC5/CyFlash.c **** - 134:.\Generated_Source\PSoC5/CyFlash.c **** while(CY_SPC_BUSY) - 135:.\Generated_Source\PSoC5/CyFlash.c **** { - 136:.\Generated_Source\PSoC5/CyFlash.c **** /* Spin until idle. */ - 137:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(1u); - 138:.\Generated_Source\PSoC5/CyFlash.c **** } - 139:.\Generated_Source\PSoC5/CyFlash.c **** break; - 140:.\Generated_Source\PSoC5/CyFlash.c **** } - 141:.\Generated_Source\PSoC5/CyFlash.c **** - 142:.\Generated_Source\PSoC5/CyFlash.c **** } while(CY_SPC_BUSY); - 48 .loc 1 142 0 - 49 0012 0E4B ldr r3, .L23 - 50 0014 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 51 0016 00F00201 and r1, r0, #2 - 52 001a CAB2 uxtb r2, r1 - 53 001c 002A cmp r2, #0 - 54 001e F5D1 bne .L7 - 55 .L14: - 130:.\Generated_Source\PSoC5/CyFlash.c **** if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_ - 56 .loc 1 130 0 - 57 0020 0221 movs r1, #2 - 58 0022 0B48 ldr r0, .L23+4 - 59 0024 FFF7FEFF bl CySpcReadData - 60 .LVL1: - 61 0028 0228 cmp r0, #2 - 62 002a F2D1 bne .L20 - 63 .L16: - 134:.\Generated_Source\PSoC5/CyFlash.c **** while(CY_SPC_BUSY) - 64 .loc 1 134 0 - 65 002c 074C ldr r4, .L23 - 66 002e 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 67 0030 03F00200 and r0, r3, #2 - 68 0034 C1B2 uxtb r1, r0 - 69 0036 19B9 cbnz r1, .L22 - 70 .L6: - 137:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(1u); - 71 .loc 1 137 0 - 72 0038 0120 movs r0, #1 - 73 003a FFF7FEFF bl CyDelayUs - 74 .LVL2: - 75 003e F5E7 b .L16 - 76 .L22: - 132:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_SUCCESS; - 77 .loc 1 132 0 - 78 0040 0024 movs r4, #0 - 79 .L3: - 80 .LVL3: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 5 - - - 143:.\Generated_Source\PSoC5/CyFlash.c **** } - 144:.\Generated_Source\PSoC5/CyFlash.c **** - 145:.\Generated_Source\PSoC5/CyFlash.c **** CySpcUnlock(); - 81 .loc 1 145 0 - 82 0042 FFF7FEFF bl CySpcUnlock - 83 .LVL4: - 146:.\Generated_Source\PSoC5/CyFlash.c **** } - 147:.\Generated_Source\PSoC5/CyFlash.c **** else - 148:.\Generated_Source\PSoC5/CyFlash.c **** { - 149:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_LOCKED; - 150:.\Generated_Source\PSoC5/CyFlash.c **** } - 151:.\Generated_Source\PSoC5/CyFlash.c **** - 152:.\Generated_Source\PSoC5/CyFlash.c **** return (status); - 153:.\Generated_Source\PSoC5/CyFlash.c **** } - 84 .loc 1 153 0 - 85 0046 2046 mov r0, r4 - 86 0048 10BD pop {r4, pc} - 87 .L24: - 88 004a 00BF .align 2 - 89 .L23: - 90 004c 22470040 .word 1073760034 - 91 0050 00000000 .word dieTemperature - 92 .cfi_endproc - 93 .LFE13: - 94 .size CySetTempInt.part.0, .-CySetTempInt.part.0 - 95 .section .text.CyFlash_Start,"ax",%progbits - 96 .align 1 - 97 .global CyFlash_Start - 98 .thumb - 99 .thumb_func - 100 .type CyFlash_Start, %function - 101 CyFlash_Start: - 102 .LFB0: - 55:.\Generated_Source\PSoC5/CyFlash.c **** { - 103 .loc 1 55 0 - 104 .cfi_startproc - 105 @ args = 0, pretend = 0, frame = 0 - 106 @ frame_needed = 0, uses_anonymous_args = 0 - 107 @ link register save eliminated. - 57:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; - 108 .loc 1 57 0 - 109 0000 054B ldr r3, .L26 - 110 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 111 0004 42F00100 orr r0, r2, #1 - 112 0008 1870 strb r0, [r3, #0] - 60:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; - 113 .loc 1 60 0 - 114 000a 197C ldrb r1, [r3, #16] @ zero_extendqisi2 - 62:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(CY_FLASH_EE_STARTUP_DELAY); - 115 .loc 1 62 0 - 116 000c 0520 movs r0, #5 - 60:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; - 117 .loc 1 60 0 - 118 000e 41F00102 orr r2, r1, #1 - 119 0012 1A74 strb r2, [r3, #16] - 63:.\Generated_Source\PSoC5/CyFlash.c **** } - 120 .loc 1 63 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 6 - - - 62:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(CY_FLASH_EE_STARTUP_DELAY); - 121 .loc 1 62 0 - 122 0014 FFF7FEBF b CyDelayUs - 123 .LVL5: - 124 .L27: - 125 .align 2 - 126 .L26: - 127 0018 AC430040 .word 1073759148 - 128 .cfi_endproc - 129 .LFE0: - 130 .size CyFlash_Start, .-CyFlash_Start - 131 .section .text.CyFlash_Stop,"ax",%progbits - 132 .align 1 - 133 .global CyFlash_Stop - 134 .thumb - 135 .thumb_func - 136 .type CyFlash_Stop, %function - 137 CyFlash_Stop: - 138 .LFB1: - 85:.\Generated_Source\PSoC5/CyFlash.c **** { - 139 .loc 1 85 0 - 140 .cfi_startproc - 141 @ args = 0, pretend = 0, frame = 0 - 142 @ frame_needed = 0, uses_anonymous_args = 0 - 143 @ link register save eliminated. - 87:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); - 144 .loc 1 87 0 - 145 0000 044B ldr r3, .L29 - 146 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 147 0004 02F0FE00 and r0, r2, #254 - 148 0008 1870 strb r0, [r3, #0] - 90:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); - 149 .loc 1 90 0 - 150 000a 197C ldrb r1, [r3, #16] @ zero_extendqisi2 - 151 000c 01F0FE02 and r2, r1, #254 - 152 0010 1A74 strb r2, [r3, #16] - 153 0012 7047 bx lr - 154 .L30: - 155 .align 2 - 156 .L29: - 157 0014 AC430040 .word 1073759148 - 158 .cfi_endproc - 159 .LFE1: - 160 .size CyFlash_Stop, .-CyFlash_Stop - 161 .section .text.CySetTemp,"ax",%progbits - 162 .align 1 - 163 .global CySetTemp - 164 .thumb - 165 .thumb_func - 166 .type CySetTemp, %function - 167 CySetTemp: - 168 .LFB3: - 154:.\Generated_Source\PSoC5/CyFlash.c **** - 155:.\Generated_Source\PSoC5/CyFlash.c **** - 156:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 157:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CySetTemp - 158:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 7 - - - 159:.\Generated_Source\PSoC5/CyFlash.c **** * - 160:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 161:.\Generated_Source\PSoC5/CyFlash.c **** * This is a wraparound for CySetTempInt(). It is used to return second - 162:.\Generated_Source\PSoC5/CyFlash.c **** * successful read of temperature value. - 163:.\Generated_Source\PSoC5/CyFlash.c **** * - 164:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 165:.\Generated_Source\PSoC5/CyFlash.c **** * None - 166:.\Generated_Source\PSoC5/CyFlash.c **** * - 167:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 168:.\Generated_Source\PSoC5/CyFlash.c **** * status: - 169:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_SUCCESS if successful. - 170:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_LOCKED if Flash writing already in use - 171:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_UNKNOWN if there was an SPC error. - 172:.\Generated_Source\PSoC5/CyFlash.c **** * - 173:.\Generated_Source\PSoC5/CyFlash.c **** * uint8 dieTemperature[2]: - 174:.\Generated_Source\PSoC5/CyFlash.c **** * Holds die temperature for the flash writting algorithm. The first byte is - 175:.\Generated_Source\PSoC5/CyFlash.c **** * the sign of the temperature (0 = negative, 1 = positive). The second byte is - 176:.\Generated_Source\PSoC5/CyFlash.c **** * the magnitude. - 177:.\Generated_Source\PSoC5/CyFlash.c **** * - 178:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 179:.\Generated_Source\PSoC5/CyFlash.c **** cystatus CySetTemp(void) - 180:.\Generated_Source\PSoC5/CyFlash.c **** { - 169 .loc 1 180 0 - 170 .cfi_startproc - 171 @ args = 0, pretend = 0, frame = 0 - 172 @ frame_needed = 0, uses_anonymous_args = 0 - 173 0000 08B5 push {r3, lr} - 174 .LCFI1: - 175 .cfi_def_cfa_offset 8 - 176 .cfi_offset 3, -8 - 177 .cfi_offset 14, -4 - 178 .LBB6: - 179 .LBB7: - 118:.\Generated_Source\PSoC5/CyFlash.c **** CySpcStart(); - 180 .loc 1 118 0 - 181 0002 FFF7FEFF bl CySpcStart - 182 .LVL6: - 123:.\Generated_Source\PSoC5/CyFlash.c **** if(CySpcLock() == CYRET_SUCCESS) - 183 .loc 1 123 0 - 184 0006 FFF7FEFF bl CySpcLock - 185 .LVL7: - 186 000a 58B9 cbnz r0, .L34 - 187 000c FFF7FEFF bl CySetTempInt.part.0 - 188 .LVL8: - 189 .LBE7: - 190 .LBE6: - 181:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status = CySetTempInt(); - 182:.\Generated_Source\PSoC5/CyFlash.c **** - 183:.\Generated_Source\PSoC5/CyFlash.c **** if(status == CYRET_SUCCESS) - 191 .loc 1 183 0 - 192 0010 48B9 cbnz r0, .L32 - 193 .LBB9: - 194 .LBB10: - 118:.\Generated_Source\PSoC5/CyFlash.c **** CySpcStart(); - 195 .loc 1 118 0 - 196 0012 FFF7FEFF bl CySpcStart - 197 .LVL9: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 8 - - - 123:.\Generated_Source\PSoC5/CyFlash.c **** if(CySpcLock() == CYRET_SUCCESS) - 198 .loc 1 123 0 - 199 0016 FFF7FEFF bl CySpcLock - 200 .LVL10: - 201 001a 18B9 cbnz r0, .L34 - 202 .LBE10: - 203 .LBE9: - 184:.\Generated_Source\PSoC5/CyFlash.c **** { - 185:.\Generated_Source\PSoC5/CyFlash.c **** status = CySetTempInt(); - 186:.\Generated_Source\PSoC5/CyFlash.c **** } - 187:.\Generated_Source\PSoC5/CyFlash.c **** - 188:.\Generated_Source\PSoC5/CyFlash.c **** return (status); - 189:.\Generated_Source\PSoC5/CyFlash.c **** } - 204 .loc 1 189 0 - 205 001c BDE80840 pop {r3, lr} - 206 0020 FFF7FEBF b CySetTempInt.part.0 - 207 .LVL11: - 208 .L34: - 209 .LBB11: - 210 .LBB8: - 149:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_LOCKED; - 211 .loc 1 149 0 - 212 0024 0420 movs r0, #4 - 213 .L32: - 214 .LVL12: - 215 .LBE8: - 216 .LBE11: - 217 .loc 1 189 0 - 218 0026 08BD pop {r3, pc} - 219 .cfi_endproc - 220 .LFE3: - 221 .size CySetTemp, .-CySetTemp - 222 .section .text.CySetFlashEEBuffer,"ax",%progbits - 223 .align 1 - 224 .global CySetFlashEEBuffer - 225 .thumb - 226 .thumb_func - 227 .type CySetFlashEEBuffer, %function - 228 CySetFlashEEBuffer: - 229 .LFB4: - 190:.\Generated_Source\PSoC5/CyFlash.c **** - 191:.\Generated_Source\PSoC5/CyFlash.c **** - 192:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 193:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CySetFlashEEBuffer - 194:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 195:.\Generated_Source\PSoC5/CyFlash.c **** * - 196:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 197:.\Generated_Source\PSoC5/CyFlash.c **** * Sets the user supplied temporary buffer to store SPC data while performing - 198:.\Generated_Source\PSoC5/CyFlash.c **** * flash and EEPROM commands. This buffer is only necessary when Flash ECC is - 199:.\Generated_Source\PSoC5/CyFlash.c **** * disabled. - 200:.\Generated_Source\PSoC5/CyFlash.c **** * - 201:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 202:.\Generated_Source\PSoC5/CyFlash.c **** * buffer: - 203:.\Generated_Source\PSoC5/CyFlash.c **** * Address of block of memory to store temporary memory. The size of the block - 204:.\Generated_Source\PSoC5/CyFlash.c **** * of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. - 205:.\Generated_Source\PSoC5/CyFlash.c **** * - 206:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 9 - - - 207:.\Generated_Source\PSoC5/CyFlash.c **** * status: - 208:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_SUCCESS if successful. - 209:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_BAD_PARAM if the buffer is NULL - 210:.\Generated_Source\PSoC5/CyFlash.c **** * - 211:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 212:.\Generated_Source\PSoC5/CyFlash.c **** cystatus CySetFlashEEBuffer(uint8 * buffer) - 213:.\Generated_Source\PSoC5/CyFlash.c **** { - 230 .loc 1 213 0 - 231 .cfi_startproc - 232 @ args = 0, pretend = 0, frame = 0 - 233 @ frame_needed = 0, uses_anonymous_args = 0 - 234 .LVL13: - 235 0000 38B5 push {r3, r4, r5, lr} - 236 .LCFI2: - 237 .cfi_def_cfa_offset 16 - 238 .cfi_offset 3, -16 - 239 .cfi_offset 4, -12 - 240 .cfi_offset 5, -8 - 241 .cfi_offset 14, -4 - 242 .loc 1 213 0 - 243 0002 0446 mov r4, r0 - 214:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status = CYRET_SUCCESS; - 215:.\Generated_Source\PSoC5/CyFlash.c **** - 216:.\Generated_Source\PSoC5/CyFlash.c **** CySpcStart(); - 244 .loc 1 216 0 - 245 0004 FFF7FEFF bl CySpcStart - 246 .LVL14: - 217:.\Generated_Source\PSoC5/CyFlash.c **** - 218:.\Generated_Source\PSoC5/CyFlash.c **** #if(CYDEV_ECC_ENABLE == 0) - 219:.\Generated_Source\PSoC5/CyFlash.c **** - 220:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL == buffer) - 247 .loc 1 220 0 - 248 0008 4CB1 cbz r4, .L37 - 221:.\Generated_Source\PSoC5/CyFlash.c **** { - 222:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_BAD_PARAM; - 223:.\Generated_Source\PSoC5/CyFlash.c **** } - 224:.\Generated_Source\PSoC5/CyFlash.c **** else if(CySpcLock() != CYRET_SUCCESS) - 249 .loc 1 224 0 - 250 000a FFF7FEFF bl CySpcLock - 251 .LVL15: - 252 000e 0546 mov r5, r0 - 253 0010 38B9 cbnz r0, .L38 - 225:.\Generated_Source\PSoC5/CyFlash.c **** { - 226:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_LOCKED; - 227:.\Generated_Source\PSoC5/CyFlash.c **** } - 228:.\Generated_Source\PSoC5/CyFlash.c **** else - 229:.\Generated_Source\PSoC5/CyFlash.c **** { - 230:.\Generated_Source\PSoC5/CyFlash.c **** rowBuffer = buffer; - 254 .loc 1 230 0 - 255 0012 054B ldr r3, .L39 - 256 0014 1C60 str r4, [r3, #0] - 231:.\Generated_Source\PSoC5/CyFlash.c **** CySpcUnlock(); - 257 .loc 1 231 0 - 258 0016 FFF7FEFF bl CySpcUnlock - 259 .LVL16: - 214:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status = CYRET_SUCCESS; - 260 .loc 1 214 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 10 - - - 261 001a 2846 mov r0, r5 - 262 001c 38BD pop {r3, r4, r5, pc} - 263 .L37: - 222:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_BAD_PARAM; - 264 .loc 1 222 0 - 265 001e 0120 movs r0, #1 - 266 0020 38BD pop {r3, r4, r5, pc} - 267 .L38: - 226:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_LOCKED; - 268 .loc 1 226 0 - 269 0022 0420 movs r0, #4 - 270 .LVL17: - 232:.\Generated_Source\PSoC5/CyFlash.c **** } - 233:.\Generated_Source\PSoC5/CyFlash.c **** - 234:.\Generated_Source\PSoC5/CyFlash.c **** #else - 235:.\Generated_Source\PSoC5/CyFlash.c **** - 236:.\Generated_Source\PSoC5/CyFlash.c **** /* To supress the warning */ - 237:.\Generated_Source\PSoC5/CyFlash.c **** buffer = buffer; - 238:.\Generated_Source\PSoC5/CyFlash.c **** - 239:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CYDEV_ECC_ENABLE == 0u) */ - 240:.\Generated_Source\PSoC5/CyFlash.c **** - 241:.\Generated_Source\PSoC5/CyFlash.c **** return(status); - 242:.\Generated_Source\PSoC5/CyFlash.c **** } - 271 .loc 1 242 0 - 272 0024 38BD pop {r3, r4, r5, pc} - 273 .L40: - 274 0026 00BF .align 2 - 275 .L39: - 276 0028 00000000 .word .LANCHOR0 - 277 .cfi_endproc - 278 .LFE4: - 279 .size CySetFlashEEBuffer, .-CySetFlashEEBuffer - 280 .section .text.CyWriteRowFull,"ax",%progbits - 281 .align 1 - 282 .global CyWriteRowFull - 283 .thumb - 284 .thumb_func - 285 .type CyWriteRowFull, %function - 286 CyWriteRowFull: - 287 .LFB7: - 243:.\Generated_Source\PSoC5/CyFlash.c **** - 244:.\Generated_Source\PSoC5/CyFlash.c **** - 245:.\Generated_Source\PSoC5/CyFlash.c **** #if(CYDEV_ECC_ENABLE == 1) - 246:.\Generated_Source\PSoC5/CyFlash.c **** - 247:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 248:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyWriteRowData - 249:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 250:.\Generated_Source\PSoC5/CyFlash.c **** * - 251:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 252:.\Generated_Source\PSoC5/CyFlash.c **** * Sends a command to the SPC to load and program a row of data in - 253:.\Generated_Source\PSoC5/CyFlash.c **** * Flash or EEPROM. - 254:.\Generated_Source\PSoC5/CyFlash.c **** * - 255:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 256:.\Generated_Source\PSoC5/CyFlash.c **** * arrayID: ID of the array to write. - 257:.\Generated_Source\PSoC5/CyFlash.c **** * The type of write, Flash or EEPROM, is determined from the array ID. - 258:.\Generated_Source\PSoC5/CyFlash.c **** * The arrays in the part are sequential starting at the first ID for the - 259:.\Generated_Source\PSoC5/CyFlash.c **** * specific memory type. The array ID for the Flash memory lasts from 0x00 to - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 11 - - - 260:.\Generated_Source\PSoC5/CyFlash.c **** * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. - 261:.\Generated_Source\PSoC5/CyFlash.c **** * rowAddress: rowAddress of flash row to program. - 262:.\Generated_Source\PSoC5/CyFlash.c **** * rowData: Array of bytes to write. - 263:.\Generated_Source\PSoC5/CyFlash.c **** * - 264:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 265:.\Generated_Source\PSoC5/CyFlash.c **** * status: - 266:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_SUCCESS if successful. - 267:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_LOCKED if the SPC is already in use. - 268:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_CANCELED if command not accepted - 269:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_UNKNOWN if there was an SPC error. - 270:.\Generated_Source\PSoC5/CyFlash.c **** * - 271:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 272:.\Generated_Source\PSoC5/CyFlash.c **** cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) - 273:.\Generated_Source\PSoC5/CyFlash.c **** { - 274:.\Generated_Source\PSoC5/CyFlash.c **** uint16 rowSize; - 275:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status; - 276:.\Generated_Source\PSoC5/CyFlash.c **** - 277:.\Generated_Source\PSoC5/CyFlash.c **** rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZ - 278:.\Generated_Source\PSoC5/CyFlash.c **** status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); - 279:.\Generated_Source\PSoC5/CyFlash.c **** - 280:.\Generated_Source\PSoC5/CyFlash.c **** return(status); - 281:.\Generated_Source\PSoC5/CyFlash.c **** } - 282:.\Generated_Source\PSoC5/CyFlash.c **** - 283:.\Generated_Source\PSoC5/CyFlash.c **** #else - 284:.\Generated_Source\PSoC5/CyFlash.c **** - 285:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 286:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyWriteRowData - 287:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 288:.\Generated_Source\PSoC5/CyFlash.c **** * - 289:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 290:.\Generated_Source\PSoC5/CyFlash.c **** * Sends a command to the SPC to load and program a row of data in - 291:.\Generated_Source\PSoC5/CyFlash.c **** * Flash or EEPROM. - 292:.\Generated_Source\PSoC5/CyFlash.c **** * - 293:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 294:.\Generated_Source\PSoC5/CyFlash.c **** * arrayID : ID of the array to write. - 295:.\Generated_Source\PSoC5/CyFlash.c **** * The type of write, Flash or EEPROM, is determined from the array ID. - 296:.\Generated_Source\PSoC5/CyFlash.c **** * The arrays in the part are sequential starting at the first ID for the - 297:.\Generated_Source\PSoC5/CyFlash.c **** * specific memory type. The array ID for the Flash memory lasts from 0x00 to - 298:.\Generated_Source\PSoC5/CyFlash.c **** * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. - 299:.\Generated_Source\PSoC5/CyFlash.c **** * rowAddress : rowAddress of flash row to program. - 300:.\Generated_Source\PSoC5/CyFlash.c **** * rowData : Array of bytes to write. - 301:.\Generated_Source\PSoC5/CyFlash.c **** * - 302:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 303:.\Generated_Source\PSoC5/CyFlash.c **** * status: - 304:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_SUCCESS if successful. - 305:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_LOCKED if the SPC is already in use. - 306:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_CANCELED if command not accepted - 307:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_UNKNOWN if there was an SPC error. - 308:.\Generated_Source\PSoC5/CyFlash.c **** * - 309:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 310:.\Generated_Source\PSoC5/CyFlash.c **** cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) - 311:.\Generated_Source\PSoC5/CyFlash.c **** { - 312:.\Generated_Source\PSoC5/CyFlash.c **** uint8 i; - 313:.\Generated_Source\PSoC5/CyFlash.c **** uint32 offset; - 314:.\Generated_Source\PSoC5/CyFlash.c **** uint16 rowSize; - 315:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status; - 316:.\Generated_Source\PSoC5/CyFlash.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 12 - - - 317:.\Generated_Source\PSoC5/CyFlash.c **** /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ - 318:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL != rowBuffer) - 319:.\Generated_Source\PSoC5/CyFlash.c **** { - 320:.\Generated_Source\PSoC5/CyFlash.c **** if(arrayId > CY_SPC_LAST_FLASH_ARRAYID) - 321:.\Generated_Source\PSoC5/CyFlash.c **** { - 322:.\Generated_Source\PSoC5/CyFlash.c **** rowSize = CYDEV_EEPROM_ROW_SIZE; - 323:.\Generated_Source\PSoC5/CyFlash.c **** } - 324:.\Generated_Source\PSoC5/CyFlash.c **** else - 325:.\Generated_Source\PSoC5/CyFlash.c **** { - 326:.\Generated_Source\PSoC5/CyFlash.c **** rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE; - 327:.\Generated_Source\PSoC5/CyFlash.c **** - 328:.\Generated_Source\PSoC5/CyFlash.c **** /* Save the ECC area. */ - 329:.\Generated_Source\PSoC5/CyFlash.c **** offset = CYDEV_ECC_BASE + - 330:.\Generated_Source\PSoC5/CyFlash.c **** ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) + - 331:.\Generated_Source\PSoC5/CyFlash.c **** ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE); - 332:.\Generated_Source\PSoC5/CyFlash.c **** - 333:.\Generated_Source\PSoC5/CyFlash.c **** for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) - 334:.\Generated_Source\PSoC5/CyFlash.c **** { - 335:.\Generated_Source\PSoC5/CyFlash.c **** *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset - 336:.\Generated_Source\PSoC5/CyFlash.c **** } - 337:.\Generated_Source\PSoC5/CyFlash.c **** } - 338:.\Generated_Source\PSoC5/CyFlash.c **** - 339:.\Generated_Source\PSoC5/CyFlash.c **** /* Copy the rowdata to the temporary buffer. */ - 340:.\Generated_Source\PSoC5/CyFlash.c **** #if(CY_PSOC3) - 341:.\Generated_Source\PSoC5/CyFlash.c **** (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZ - 342:.\Generated_Source\PSoC5/CyFlash.c **** #else - 343:.\Generated_Source\PSoC5/CyFlash.c **** (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); - 344:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CY_PSOC3) */ - 345:.\Generated_Source\PSoC5/CyFlash.c **** - 346:.\Generated_Source\PSoC5/CyFlash.c **** status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize); - 347:.\Generated_Source\PSoC5/CyFlash.c **** } - 348:.\Generated_Source\PSoC5/CyFlash.c **** else - 349:.\Generated_Source\PSoC5/CyFlash.c **** { - 350:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_UNKNOWN; - 351:.\Generated_Source\PSoC5/CyFlash.c **** } - 352:.\Generated_Source\PSoC5/CyFlash.c **** - 353:.\Generated_Source\PSoC5/CyFlash.c **** return(status); - 354:.\Generated_Source\PSoC5/CyFlash.c **** } - 355:.\Generated_Source\PSoC5/CyFlash.c **** - 356:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CYDEV_ECC_ENABLE == 0u) */ - 357:.\Generated_Source\PSoC5/CyFlash.c **** - 358:.\Generated_Source\PSoC5/CyFlash.c **** - 359:.\Generated_Source\PSoC5/CyFlash.c **** #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) - 360:.\Generated_Source\PSoC5/CyFlash.c **** - 361:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 362:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyWriteRowConfig - 363:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 364:.\Generated_Source\PSoC5/CyFlash.c **** * - 365:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 366:.\Generated_Source\PSoC5/CyFlash.c **** * Sends a command to the SPC to load and program a row of config data in flash. - 367:.\Generated_Source\PSoC5/CyFlash.c **** * This function is only valid for Flash array IDs (not for EEPROM). - 368:.\Generated_Source\PSoC5/CyFlash.c **** * - 369:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 370:.\Generated_Source\PSoC5/CyFlash.c **** * arrayId: ID of the array to write - 371:.\Generated_Source\PSoC5/CyFlash.c **** * The arrays in the part are sequential starting at the first ID for the - 372:.\Generated_Source\PSoC5/CyFlash.c **** * specific memory type. The array ID for the Flash memory lasts - 373:.\Generated_Source\PSoC5/CyFlash.c **** * from 0x00 to 0x3F. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 13 - - - 374:.\Generated_Source\PSoC5/CyFlash.c **** * rowAddress: Address of the sector to erase. - 375:.\Generated_Source\PSoC5/CyFlash.c **** * rowECC: Array of bytes to write. - 376:.\Generated_Source\PSoC5/CyFlash.c **** * - 377:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 378:.\Generated_Source\PSoC5/CyFlash.c **** * status: - 379:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_SUCCESS if successful. - 380:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_LOCKED if the SPC is already in use. - 381:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_CANCELED if command not accepted - 382:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_UNKNOWN if there was an SPC error. - 383:.\Generated_Source\PSoC5/CyFlash.c **** * - 384:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 385:.\Generated_Source\PSoC5/CyFlash.c **** cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\ - 386:.\Generated_Source\PSoC5/CyFlash.c **** - 387:.\Generated_Source\PSoC5/CyFlash.c **** { - 388:.\Generated_Source\PSoC5/CyFlash.c **** uint32 offset; - 389:.\Generated_Source\PSoC5/CyFlash.c **** uint16 i; - 390:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status; - 391:.\Generated_Source\PSoC5/CyFlash.c **** - 392:.\Generated_Source\PSoC5/CyFlash.c **** /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ - 393:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL != rowBuffer) - 394:.\Generated_Source\PSoC5/CyFlash.c **** { - 395:.\Generated_Source\PSoC5/CyFlash.c **** /* Read the existing flash data. */ - 396:.\Generated_Source\PSoC5/CyFlash.c **** offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) + - 397:.\Generated_Source\PSoC5/CyFlash.c **** ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE); - 398:.\Generated_Source\PSoC5/CyFlash.c **** - 399:.\Generated_Source\PSoC5/CyFlash.c **** #if (CYDEV_FLS_BASE != 0u) - 400:.\Generated_Source\PSoC5/CyFlash.c **** offset += CYDEV_FLS_BASE; - 401:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CYDEV_FLS_BASE != 0u) */ - 402:.\Generated_Source\PSoC5/CyFlash.c **** - 403:.\Generated_Source\PSoC5/CyFlash.c **** for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) - 404:.\Generated_Source\PSoC5/CyFlash.c **** { - 405:.\Generated_Source\PSoC5/CyFlash.c **** rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); - 406:.\Generated_Source\PSoC5/CyFlash.c **** } - 407:.\Generated_Source\PSoC5/CyFlash.c **** - 408:.\Generated_Source\PSoC5/CyFlash.c **** #if(CY_PSOC3) - 409:.\Generated_Source\PSoC5/CyFlash.c **** (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], - 410:.\Generated_Source\PSoC5/CyFlash.c **** (void *)(uint32)rowECC, - 411:.\Generated_Source\PSoC5/CyFlash.c **** (int16)CYDEV_ECC_ROW_SIZE); - 412:.\Generated_Source\PSoC5/CyFlash.c **** #else - 413:.\Generated_Source\PSoC5/CyFlash.c **** (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], - 414:.\Generated_Source\PSoC5/CyFlash.c **** (const void *)rowECC, - 415:.\Generated_Source\PSoC5/CyFlash.c **** CYDEV_ECC_ROW_SIZE); - 416:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CY_PSOC3) */ - 417:.\Generated_Source\PSoC5/CyFlash.c **** - 418:.\Generated_Source\PSoC5/CyFlash.c **** status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ - 419:.\Generated_Source\PSoC5/CyFlash.c **** } - 420:.\Generated_Source\PSoC5/CyFlash.c **** else - 421:.\Generated_Source\PSoC5/CyFlash.c **** { - 422:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_UNKNOWN; - 423:.\Generated_Source\PSoC5/CyFlash.c **** } - 424:.\Generated_Source\PSoC5/CyFlash.c **** - 425:.\Generated_Source\PSoC5/CyFlash.c **** return (status); - 426:.\Generated_Source\PSoC5/CyFlash.c **** } - 427:.\Generated_Source\PSoC5/CyFlash.c **** - 428:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ - 429:.\Generated_Source\PSoC5/CyFlash.c **** - 430:.\Generated_Source\PSoC5/CyFlash.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 14 - - - 431:.\Generated_Source\PSoC5/CyFlash.c **** - 432:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 433:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyWriteRowFull - 434:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 435:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 436:.\Generated_Source\PSoC5/CyFlash.c **** * Sends a command to the SPC to load and program a row of data in flash. - 437:.\Generated_Source\PSoC5/CyFlash.c **** * rowData array is expected to contain Flash and ECC data if needed. - 438:.\Generated_Source\PSoC5/CyFlash.c **** * - 439:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 440:.\Generated_Source\PSoC5/CyFlash.c **** * arrayId: FLASH or EEPROM array id. - 441:.\Generated_Source\PSoC5/CyFlash.c **** * rowData: Pointer to a row of data to write. - 442:.\Generated_Source\PSoC5/CyFlash.c **** * rowNumber: Zero based number of the row. - 443:.\Generated_Source\PSoC5/CyFlash.c **** * rowSize: Size of the row. - 444:.\Generated_Source\PSoC5/CyFlash.c **** * - 445:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 446:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_SUCCESS if successful. - 447:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_LOCKED if the SPC is already in use. - 448:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_CANCELED if command not accepted - 449:.\Generated_Source\PSoC5/CyFlash.c **** * CYRET_UNKNOWN if there was an SPC error. - 450:.\Generated_Source\PSoC5/CyFlash.c **** * - 451:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 452:.\Generated_Source\PSoC5/CyFlash.c **** cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ - 453:.\Generated_Source\PSoC5/CyFlash.c **** - 454:.\Generated_Source\PSoC5/CyFlash.c **** { - 288 .loc 1 454 0 - 289 .cfi_startproc - 290 @ args = 0, pretend = 0, frame = 0 - 291 @ frame_needed = 0, uses_anonymous_args = 0 - 292 .LVL18: - 293 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 294 .LCFI3: - 295 .cfi_def_cfa_offset 24 - 296 .cfi_offset 3, -24 - 297 .cfi_offset 4, -20 - 298 .cfi_offset 5, -16 - 299 .cfi_offset 6, -12 - 300 .cfi_offset 7, -8 - 301 .cfi_offset 14, -4 - 302 .loc 1 454 0 - 303 0002 0546 mov r5, r0 - 304 0004 0E46 mov r6, r1 - 305 0006 1746 mov r7, r2 - 306 0008 1C46 mov r4, r3 - 455:.\Generated_Source\PSoC5/CyFlash.c **** cystatus status; - 456:.\Generated_Source\PSoC5/CyFlash.c **** - 457:.\Generated_Source\PSoC5/CyFlash.c **** if(CySpcLock() == CYRET_SUCCESS) - 307 .loc 1 457 0 - 308 000a FFF7FEFF bl CySpcLock - 309 .LVL19: - 310 000e F0B9 cbnz r0, .L49 - 311 .LVL20: - 312 .LBB14: - 313 .LBB15: - 458:.\Generated_Source\PSoC5/CyFlash.c **** { - 459:.\Generated_Source\PSoC5/CyFlash.c **** /* Load row data into SPC internal latch */ - 460:.\Generated_Source\PSoC5/CyFlash.c **** status = CySpcLoadRow(arrayId, rowData, rowSize); - 314 .loc 1 460 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 15 - - - 315 0010 2246 mov r2, r4 - 316 0012 2846 mov r0, r5 - 317 0014 3946 mov r1, r7 - 318 0016 FFF7FEFF bl CySpcLoadRow - 319 .LVL21: - 461:.\Generated_Source\PSoC5/CyFlash.c **** - 462:.\Generated_Source\PSoC5/CyFlash.c **** if(CYRET_STARTED == status) - 320 .loc 1 462 0 - 321 001a 0728 cmp r0, #7 - 460:.\Generated_Source\PSoC5/CyFlash.c **** status = CySpcLoadRow(arrayId, rowData, rowSize); - 322 .loc 1 460 0 - 323 001c 0446 mov r4, r0 - 324 .LVL22: - 325 .loc 1 462 0 - 326 001e 13D1 bne .L44 - 327 .LVL23: - 328 .L57: - 463:.\Generated_Source\PSoC5/CyFlash.c **** { - 464:.\Generated_Source\PSoC5/CyFlash.c **** while(CY_SPC_BUSY) - 329 .loc 1 464 0 - 330 0020 1D4B ldr r3, .L64 - 331 0022 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 332 0024 02F00200 and r0, r2, #2 - 333 0028 C1B2 uxtb r1, r0 - 334 002a 19B9 cbnz r1, .L62 - 335 .L45: - 465:.\Generated_Source\PSoC5/CyFlash.c **** { - 466:.\Generated_Source\PSoC5/CyFlash.c **** /* Wait for SPC to finish and get SPC status */ - 467:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(1u); - 336 .loc 1 467 0 - 337 002c 0120 movs r0, #1 - 338 002e FFF7FEFF bl CyDelayUs - 339 .LVL24: - 340 0032 F5E7 b .L57 - 341 .L62: - 468:.\Generated_Source\PSoC5/CyFlash.c **** } - 469:.\Generated_Source\PSoC5/CyFlash.c **** - 470:.\Generated_Source\PSoC5/CyFlash.c **** /* Hide SPC status */ - 471:.\Generated_Source\PSoC5/CyFlash.c **** if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) - 342 .loc 1 471 0 - 343 0034 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 344 .LVL25: - 345 0036 04F00202 and r2, r4, #2 - 346 003a D0B2 uxtb r0, r2 - 347 003c 10B1 cbz r0, .L51 - 348 003e 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 349 0040 9B08 lsrs r3, r3, #2 - 350 0042 06D0 beq .L46 - 351 .L51: - 472:.\Generated_Source\PSoC5/CyFlash.c **** { - 473:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_SUCCESS; - 474:.\Generated_Source\PSoC5/CyFlash.c **** } - 475:.\Generated_Source\PSoC5/CyFlash.c **** else - 476:.\Generated_Source\PSoC5/CyFlash.c **** { - 477:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_UNKNOWN; - 478:.\Generated_Source\PSoC5/CyFlash.c **** } - 479:.\Generated_Source\PSoC5/CyFlash.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 16 - - - 480:.\Generated_Source\PSoC5/CyFlash.c **** if(CYRET_SUCCESS == status) - 481:.\Generated_Source\PSoC5/CyFlash.c **** { - 482:.\Generated_Source\PSoC5/CyFlash.c **** /* Erase and program flash with the data from SPC interval latch */ - 483:.\Generated_Source\PSoC5/CyFlash.c **** status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); - 484:.\Generated_Source\PSoC5/CyFlash.c **** - 485:.\Generated_Source\PSoC5/CyFlash.c **** if(CYRET_STARTED == status) - 486:.\Generated_Source\PSoC5/CyFlash.c **** { - 487:.\Generated_Source\PSoC5/CyFlash.c **** while(CY_SPC_BUSY) - 488:.\Generated_Source\PSoC5/CyFlash.c **** { - 489:.\Generated_Source\PSoC5/CyFlash.c **** /* Wait for SPC to finish and get SPC status */ - 490:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(1u); - 491:.\Generated_Source\PSoC5/CyFlash.c **** } - 492:.\Generated_Source\PSoC5/CyFlash.c **** - 493:.\Generated_Source\PSoC5/CyFlash.c **** /* Hide SPC status */ - 494:.\Generated_Source\PSoC5/CyFlash.c **** if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) - 495:.\Generated_Source\PSoC5/CyFlash.c **** { - 496:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_SUCCESS; - 497:.\Generated_Source\PSoC5/CyFlash.c **** } - 498:.\Generated_Source\PSoC5/CyFlash.c **** else - 499:.\Generated_Source\PSoC5/CyFlash.c **** { - 500:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_UNKNOWN; - 352 .loc 1 500 0 - 353 0044 4FF0FF34 mov r4, #-1 - 354 .L44: - 355 .LVL26: - 501:.\Generated_Source\PSoC5/CyFlash.c **** } - 502:.\Generated_Source\PSoC5/CyFlash.c **** } - 503:.\Generated_Source\PSoC5/CyFlash.c **** } - 504:.\Generated_Source\PSoC5/CyFlash.c **** - 505:.\Generated_Source\PSoC5/CyFlash.c **** } - 506:.\Generated_Source\PSoC5/CyFlash.c **** - 507:.\Generated_Source\PSoC5/CyFlash.c **** CySpcUnlock(); - 356 .loc 1 507 0 - 357 0048 FFF7FEFF bl CySpcUnlock - 358 .LVL27: - 359 004c 22E0 b .L61 - 360 .LVL28: - 361 .L49: - 362 .LBE15: - 363 .LBE14: - 508:.\Generated_Source\PSoC5/CyFlash.c **** } - 509:.\Generated_Source\PSoC5/CyFlash.c **** else - 510:.\Generated_Source\PSoC5/CyFlash.c **** { - 511:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_LOCKED; - 364 .loc 1 511 0 - 365 004e 0424 movs r4, #4 - 366 .LVL29: - 367 0050 20E0 b .L61 - 368 .LVL30: - 369 .L46: - 370 .LBB17: - 371 .LBB16: - 483:.\Generated_Source\PSoC5/CyFlash.c **** status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); - 372 .loc 1 483 0 - 373 0052 124C ldr r4, .L64+4 - 374 0054 2846 mov r0, r5 - 375 0056 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 17 - - - 376 0058 6378 ldrb r3, [r4, #1] @ zero_extendqisi2 - 377 005a 3146 mov r1, r6 - 378 005c FFF7FEFF bl CySpcWriteRow - 379 .LVL31: - 485:.\Generated_Source\PSoC5/CyFlash.c **** if(CYRET_STARTED == status) - 380 .loc 1 485 0 - 381 0060 0728 cmp r0, #7 - 483:.\Generated_Source\PSoC5/CyFlash.c **** status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); - 382 .loc 1 483 0 - 383 0062 0446 mov r4, r0 - 384 .LVL32: - 485:.\Generated_Source\PSoC5/CyFlash.c **** if(CYRET_STARTED == status) - 385 .loc 1 485 0 - 386 0064 F0D1 bne .L44 - 387 .LVL33: - 388 .L58: - 487:.\Generated_Source\PSoC5/CyFlash.c **** while(CY_SPC_BUSY) - 389 .loc 1 487 0 - 390 0066 0C49 ldr r1, .L64 - 391 0068 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 392 006a 02F00200 and r0, r2, #2 - 393 006e C3B2 uxtb r3, r0 - 394 0070 1BB9 cbnz r3, .L63 - 395 .L47: - 490:.\Generated_Source\PSoC5/CyFlash.c **** CyDelayUs(1u); - 396 .loc 1 490 0 - 397 0072 0120 movs r0, #1 - 398 0074 FFF7FEFF bl CyDelayUs - 399 .LVL34: - 400 0078 F5E7 b .L58 - 401 .L63: - 494:.\Generated_Source\PSoC5/CyFlash.c **** if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) - 402 .loc 1 494 0 - 403 007a 0C78 ldrb r4, [r1, #0] @ zero_extendqisi2 - 404 .LVL35: - 405 007c 04F00202 and r2, r4, #2 - 406 0080 D0B2 uxtb r0, r2 - 407 0082 0028 cmp r0, #0 - 408 0084 DED0 beq .L51 - 409 0086 0978 ldrb r1, [r1, #0] @ zero_extendqisi2 - 496:.\Generated_Source\PSoC5/CyFlash.c **** status = CYRET_SUCCESS; - 410 .loc 1 496 0 - 411 0088 8B08 lsrs r3, r1, #2 - 412 008a 14BF ite ne - 413 008c 4FF0FF34 movne r4, #-1 - 414 0090 0024 moveq r4, #0 - 415 0092 D9E7 b .L44 - 416 .LVL36: - 417 .L61: - 418 .LBE16: - 419 .LBE17: - 512:.\Generated_Source\PSoC5/CyFlash.c **** } - 513:.\Generated_Source\PSoC5/CyFlash.c **** - 514:.\Generated_Source\PSoC5/CyFlash.c **** return(status); - 515:.\Generated_Source\PSoC5/CyFlash.c **** } - 420 .loc 1 515 0 - 421 0094 2046 mov r0, r4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 18 - - - 422 0096 F8BD pop {r3, r4, r5, r6, r7, pc} - 423 .L65: - 424 .align 2 - 425 .L64: - 426 0098 22470040 .word 1073760034 - 427 009c 00000000 .word dieTemperature - 428 .cfi_endproc - 429 .LFE7: - 430 .size CyWriteRowFull, .-CyWriteRowFull - 431 .section .text.CyWriteRowConfig,"ax",%progbits - 432 .align 1 - 433 .global CyWriteRowConfig - 434 .thumb - 435 .thumb_func - 436 .type CyWriteRowConfig, %function - 437 CyWriteRowConfig: - 438 .LFB6: - 387:.\Generated_Source\PSoC5/CyFlash.c **** { - 439 .loc 1 387 0 - 440 .cfi_startproc - 441 @ args = 0, pretend = 0, frame = 0 - 442 @ frame_needed = 0, uses_anonymous_args = 0 - 443 .LVL37: - 393:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL != rowBuffer) - 444 .loc 1 393 0 - 445 0000 104B ldr r3, .L72 - 387:.\Generated_Source\PSoC5/CyFlash.c **** { - 446 .loc 1 387 0 - 447 0002 70B5 push {r4, r5, r6, lr} - 448 .LCFI4: - 449 .cfi_def_cfa_offset 16 - 450 .cfi_offset 4, -16 - 451 .cfi_offset 5, -12 - 452 .cfi_offset 6, -8 - 453 .cfi_offset 14, -4 - 393:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL != rowBuffer) - 454 .loc 1 393 0 - 455 0004 1C68 ldr r4, [r3, #0] - 456 0006 D4B1 cbz r4, .L67 - 396:.\Generated_Source\PSoC5/CyFlash.c **** offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) + - 457 .loc 1 396 0 - 458 0008 01EB0026 add r6, r1, r0, lsl #8 - 459 000c 3602 lsls r6, r6, #8 - 460 .LVL38: - 461 000e 0023 movs r3, #0 - 462 .LVL39: - 463 .L68: - 405:.\Generated_Source\PSoC5/CyFlash.c **** rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); - 464 .loc 1 405 0 discriminator 2 - 465 0010 9D5D ldrb r5, [r3, r6] @ zero_extendqisi2 - 466 0012 E554 strb r5, [r4, r3] - 467 0014 0133 adds r3, r3, #1 - 403:.\Generated_Source\PSoC5/CyFlash.c **** for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) - 468 .loc 1 403 0 discriminator 2 - 469 0016 B3F5807F cmp r3, #256 - 470 001a F9D1 bne .L68 - 413:.\Generated_Source\PSoC5/CyFlash.c **** (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 19 - - - 471 .loc 1 413 0 - 472 001c 04F58073 add r3, r4, #256 - 473 0020 02F12005 add r5, r2, #32 - 474 .LVL40: - 475 .L69: - 476 0024 52F8046B ldr r6, [r2], #4 @ unaligned - 477 0028 AA42 cmp r2, r5 - 478 002a 43F8046B str r6, [r3], #4 @ unaligned - 479 002e F9D1 bne .L69 - 418:.\Generated_Source\PSoC5/CyFlash.c **** status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ - 480 .loc 1 418 0 - 481 0030 2246 mov r2, r4 - 482 0032 4FF49073 mov r3, #288 - 426:.\Generated_Source\PSoC5/CyFlash.c **** } - 483 .loc 1 426 0 - 484 0036 BDE87040 pop {r4, r5, r6, lr} - 418:.\Generated_Source\PSoC5/CyFlash.c **** status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ - 485 .loc 1 418 0 - 486 003a FFF7FEBF b CyWriteRowFull - 487 .LVL41: - 488 .L67: - 426:.\Generated_Source\PSoC5/CyFlash.c **** } - 489 .loc 1 426 0 - 490 003e 4FF0FF30 mov r0, #-1 - 491 .LVL42: - 492 0042 70BD pop {r4, r5, r6, pc} - 493 .L73: - 494 .align 2 - 495 .L72: - 496 0044 00000000 .word .LANCHOR0 - 497 .cfi_endproc - 498 .LFE6: - 499 .size CyWriteRowConfig, .-CyWriteRowConfig - 500 .section .text.CyWriteRowData,"ax",%progbits - 501 .align 1 - 502 .global CyWriteRowData - 503 .thumb - 504 .thumb_func - 505 .type CyWriteRowData, %function - 506 CyWriteRowData: - 507 .LFB5: - 311:.\Generated_Source\PSoC5/CyFlash.c **** { - 508 .loc 1 311 0 - 509 .cfi_startproc - 510 @ args = 0, pretend = 0, frame = 0 - 511 @ frame_needed = 0, uses_anonymous_args = 0 - 512 .LVL43: - 318:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL != rowBuffer) - 513 .loc 1 318 0 - 514 0000 154B ldr r3, .L80 - 311:.\Generated_Source\PSoC5/CyFlash.c **** { - 515 .loc 1 311 0 - 516 0002 2DE9F041 push {r4, r5, r6, r7, r8, lr} - 517 .LCFI5: - 518 .cfi_def_cfa_offset 24 - 519 .cfi_offset 4, -24 - 520 .cfi_offset 5, -20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 20 - - - 521 .cfi_offset 6, -16 - 522 .cfi_offset 7, -12 - 523 .cfi_offset 8, -8 - 524 .cfi_offset 14, -4 - 318:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL != rowBuffer) - 525 .loc 1 318 0 - 526 0006 1C68 ldr r4, [r3, #0] - 311:.\Generated_Source\PSoC5/CyFlash.c **** { - 527 .loc 1 311 0 - 528 0008 0546 mov r5, r0 - 529 000a 0F46 mov r7, r1 - 318:.\Generated_Source\PSoC5/CyFlash.c **** if(NULL != rowBuffer) - 530 .loc 1 318 0 - 531 000c 04B3 cbz r4, .L75 - 320:.\Generated_Source\PSoC5/CyFlash.c **** if(arrayId > CY_SPC_LAST_FLASH_ARRAYID) - 532 .loc 1 320 0 - 533 000e 3F28 cmp r0, #63 - 534 0010 0FD8 bhi .L78 - 535 .LVL44: - 330:.\Generated_Source\PSoC5/CyFlash.c **** ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) + - 536 .loc 1 330 0 - 537 0012 00F51036 add r6, r0, #147456 - 538 0016 01EB0620 add r0, r1, r6, lsl #8 - 539 .LVL45: - 329:.\Generated_Source\PSoC5/CyFlash.c **** offset = CYDEV_ECC_BASE + - 540 .loc 1 329 0 - 541 001a 4601 lsls r6, r0, #5 - 542 .LVL46: - 543 001c 0023 movs r3, #0 - 544 .LVL47: - 545 .L77: - 335:.\Generated_Source\PSoC5/CyFlash.c **** *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset - 546 .loc 1 335 0 discriminator 2 - 547 001e 985D ldrb r0, [r3, r6] @ zero_extendqisi2 - 310:.\Generated_Source\PSoC5/CyFlash.c **** cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) - 548 .loc 1 310 0 discriminator 2 - 549 0020 E118 adds r1, r4, r3 - 550 0022 0133 adds r3, r3, #1 - 333:.\Generated_Source\PSoC5/CyFlash.c **** for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) - 551 .loc 1 333 0 discriminator 2 - 552 0024 202B cmp r3, #32 - 335:.\Generated_Source\PSoC5/CyFlash.c **** *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset - 553 .loc 1 335 0 discriminator 2 - 554 0026 81F80001 strb r0, [r1, #256] - 333:.\Generated_Source\PSoC5/CyFlash.c **** for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) - 555 .loc 1 333 0 discriminator 2 - 556 002a F8D1 bne .L77 - 326:.\Generated_Source\PSoC5/CyFlash.c **** rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE; - 557 .loc 1 326 0 - 558 002c 4FF49076 mov r6, #288 - 559 .LVL48: - 560 0030 00E0 b .L76 - 561 .LVL49: - 562 .L78: - 322:.\Generated_Source\PSoC5/CyFlash.c **** rowSize = CYDEV_EEPROM_ROW_SIZE; - 563 .loc 1 322 0 - 564 0032 1026 movs r6, #16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 21 - - - 565 .LVL50: - 566 .L76: - 343:.\Generated_Source\PSoC5/CyFlash.c **** (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); - 567 .loc 1 343 0 - 568 0034 1146 mov r1, r2 - 569 0036 2046 mov r0, r4 - 570 0038 4FF48072 mov r2, #256 - 571 .LVL51: - 572 003c FFF7FEFF bl memcpy - 573 .LVL52: - 346:.\Generated_Source\PSoC5/CyFlash.c **** status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize); - 574 .loc 1 346 0 - 575 0040 2846 mov r0, r5 - 576 0042 3946 mov r1, r7 - 577 0044 2246 mov r2, r4 - 578 0046 3346 mov r3, r6 - 354:.\Generated_Source\PSoC5/CyFlash.c **** } - 579 .loc 1 354 0 - 580 0048 BDE8F041 pop {r4, r5, r6, r7, r8, lr} - 346:.\Generated_Source\PSoC5/CyFlash.c **** status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize); - 581 .loc 1 346 0 - 582 004c FFF7FEBF b CyWriteRowFull - 583 .LVL53: - 584 .L75: - 354:.\Generated_Source\PSoC5/CyFlash.c **** } - 585 .loc 1 354 0 - 586 0050 4FF0FF30 mov r0, #-1 - 587 .LVL54: - 588 0054 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 589 .L81: - 590 .align 2 - 591 .L80: - 592 0058 00000000 .word .LANCHOR0 - 593 .cfi_endproc - 594 .LFE5: - 595 .size CyWriteRowData, .-CyWriteRowData - 596 .section .text.CyFlash_SetWaitCycles,"ax",%progbits - 597 .align 1 - 598 .global CyFlash_SetWaitCycles - 599 .thumb - 600 .thumb_func - 601 .type CyFlash_SetWaitCycles, %function - 602 CyFlash_SetWaitCycles: - 603 .LFB8: - 516:.\Generated_Source\PSoC5/CyFlash.c **** - 517:.\Generated_Source\PSoC5/CyFlash.c **** - 518:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 519:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyFlash_SetWaitCycles - 520:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 521:.\Generated_Source\PSoC5/CyFlash.c **** * - 522:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 523:.\Generated_Source\PSoC5/CyFlash.c **** * Sets the number of clock cycles the cache will wait before it samples data - 524:.\Generated_Source\PSoC5/CyFlash.c **** * coming back from Flash. This function must be called before increasing CPU - 525:.\Generated_Source\PSoC5/CyFlash.c **** * clock frequency. It can optionally be called after lowering CPU clock - 526:.\Generated_Source\PSoC5/CyFlash.c **** * frequency in order to improve CPU performance. - 527:.\Generated_Source\PSoC5/CyFlash.c **** * - 528:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 22 - - - 529:.\Generated_Source\PSoC5/CyFlash.c **** * uint8 freq: - 530:.\Generated_Source\PSoC5/CyFlash.c **** * Frequency of operation in Megahertz. - 531:.\Generated_Source\PSoC5/CyFlash.c **** * - 532:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 533:.\Generated_Source\PSoC5/CyFlash.c **** * None - 534:.\Generated_Source\PSoC5/CyFlash.c **** * - 535:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 536:.\Generated_Source\PSoC5/CyFlash.c **** void CyFlash_SetWaitCycles(uint8 freq) - 537:.\Generated_Source\PSoC5/CyFlash.c **** { - 604 .loc 1 537 0 - 605 .cfi_startproc - 606 @ args = 0, pretend = 0, frame = 0 - 607 @ frame_needed = 0, uses_anonymous_args = 0 - 608 .LVL55: - 609 0000 10B5 push {r4, lr} - 610 .LCFI6: - 611 .cfi_def_cfa_offset 8 - 612 .cfi_offset 4, -8 - 613 .cfi_offset 14, -4 - 614 .loc 1 537 0 - 615 0002 0446 mov r4, r0 - 538:.\Generated_Source\PSoC5/CyFlash.c **** uint8 interruptState; - 539:.\Generated_Source\PSoC5/CyFlash.c **** - 540:.\Generated_Source\PSoC5/CyFlash.c **** /* Save current global interrupt enable and disable it */ - 541:.\Generated_Source\PSoC5/CyFlash.c **** interruptState = CyEnterCriticalSection(); - 616 .loc 1 541 0 - 617 0004 FFF7FEFF bl CyEnterCriticalSection - 618 .LVL56: - 619 0008 0D4B ldr r3, .L88 - 542:.\Generated_Source\PSoC5/CyFlash.c **** - 543:.\Generated_Source\PSoC5/CyFlash.c **** /*************************************************************************** - 544:.\Generated_Source\PSoC5/CyFlash.c **** * The number of clock cycles the cache will wait before it samples data - 545:.\Generated_Source\PSoC5/CyFlash.c **** * coming back from Flash must be equal or greater to to the CPU frequency - 546:.\Generated_Source\PSoC5/CyFlash.c **** * outlined in clock cycles. - 547:.\Generated_Source\PSoC5/CyFlash.c **** ***************************************************************************/ - 548:.\Generated_Source\PSoC5/CyFlash.c **** - 549:.\Generated_Source\PSoC5/CyFlash.c **** #if (CY_PSOC3) - 550:.\Generated_Source\PSoC5/CyFlash.c **** - 551:.\Generated_Source\PSoC5/CyFlash.c **** if (freq <= 22u) - 552:.\Generated_Source\PSoC5/CyFlash.c **** { - 553:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - 554:.\Generated_Source\PSoC5/CyFlash.c **** ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - 555:.\Generated_Source\PSoC5/CyFlash.c **** } - 556:.\Generated_Source\PSoC5/CyFlash.c **** else if (freq <= 44u) - 557:.\Generated_Source\PSoC5/CyFlash.c **** { - 558:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - 559:.\Generated_Source\PSoC5/CyFlash.c **** ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - 560:.\Generated_Source\PSoC5/CyFlash.c **** } - 561:.\Generated_Source\PSoC5/CyFlash.c **** else - 562:.\Generated_Source\PSoC5/CyFlash.c **** { - 563:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - 564:.\Generated_Source\PSoC5/CyFlash.c **** ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - 565:.\Generated_Source\PSoC5/CyFlash.c **** } - 566:.\Generated_Source\PSoC5/CyFlash.c **** - 567:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CY_PSOC3) */ - 568:.\Generated_Source\PSoC5/CyFlash.c **** - 569:.\Generated_Source\PSoC5/CyFlash.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 23 - - - 570:.\Generated_Source\PSoC5/CyFlash.c **** #if (CY_PSOC5) - 571:.\Generated_Source\PSoC5/CyFlash.c **** - 572:.\Generated_Source\PSoC5/CyFlash.c **** if (freq <= 16u) - 620 .loc 1 572 0 - 621 000a 102C cmp r4, #16 - 573:.\Generated_Source\PSoC5/CyFlash.c **** { - 574:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - 622 .loc 1 574 0 - 623 000c 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 572:.\Generated_Source\PSoC5/CyFlash.c **** if (freq <= 16u) - 624 .loc 1 572 0 - 625 000e 04D8 bhi .L83 - 626 .loc 1 574 0 - 627 0010 02F03F02 and r2, r2, #63 - 628 0014 42F04002 orr r2, r2, #64 - 629 0018 0CE0 b .L87 - 630 .L83: - 575:.\Generated_Source\PSoC5/CyFlash.c **** ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - 576:.\Generated_Source\PSoC5/CyFlash.c **** } - 577:.\Generated_Source\PSoC5/CyFlash.c **** else if (freq <= 33u) - 631 .loc 1 577 0 - 632 001a 212C cmp r4, #33 - 633 001c 04D8 bhi .L85 - 578:.\Generated_Source\PSoC5/CyFlash.c **** { - 579:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - 634 .loc 1 579 0 - 635 001e 02F03F01 and r1, r2, #63 - 636 0022 41F08002 orr r2, r1, #128 - 637 0026 05E0 b .L87 - 638 .L85: - 580:.\Generated_Source\PSoC5/CyFlash.c **** ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - 581:.\Generated_Source\PSoC5/CyFlash.c **** } - 582:.\Generated_Source\PSoC5/CyFlash.c **** else if (freq <= 50u) - 639 .loc 1 582 0 - 640 0028 322C cmp r4, #50 - 583:.\Generated_Source\PSoC5/CyFlash.c **** { - 584:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - 641 .loc 1 584 0 - 642 002a 94BF ite ls - 643 002c 42F0C002 orrls r2, r2, #192 - 585:.\Generated_Source\PSoC5/CyFlash.c **** ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - 586:.\Generated_Source\PSoC5/CyFlash.c **** } - 587:.\Generated_Source\PSoC5/CyFlash.c **** else - 588:.\Generated_Source\PSoC5/CyFlash.c **** { - 589:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - 644 .loc 1 589 0 - 645 0030 02F03F02 andhi r2, r2, #63 - 646 .L87: - 647 0034 1A70 strb r2, [r3, #0] - 590:.\Generated_Source\PSoC5/CyFlash.c **** ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - 591:.\Generated_Source\PSoC5/CyFlash.c **** } - 592:.\Generated_Source\PSoC5/CyFlash.c **** - 593:.\Generated_Source\PSoC5/CyFlash.c **** #endif /* (CY_PSOC5) */ - 594:.\Generated_Source\PSoC5/CyFlash.c **** - 595:.\Generated_Source\PSoC5/CyFlash.c **** /* Restore global interrupt enable state */ - 596:.\Generated_Source\PSoC5/CyFlash.c **** CyExitCriticalSection(interruptState); - 597:.\Generated_Source\PSoC5/CyFlash.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 24 - - - 648 .loc 1 597 0 - 649 0036 BDE81040 pop {r4, lr} - 596:.\Generated_Source\PSoC5/CyFlash.c **** CyExitCriticalSection(interruptState); - 650 .loc 1 596 0 - 651 003a FFF7FEBF b CyExitCriticalSection - 652 .LVL57: - 653 .L89: - 654 003e 00BF .align 2 - 655 .L88: - 656 0040 00480040 .word 1073760256 - 657 .cfi_endproc - 658 .LFE8: - 659 .size CyFlash_SetWaitCycles, .-CyFlash_SetWaitCycles - 660 .section .text.CyEEPROM_Start,"ax",%progbits - 661 .align 1 - 662 .global CyEEPROM_Start - 663 .thumb - 664 .thumb_func - 665 .type CyEEPROM_Start, %function - 666 CyEEPROM_Start: - 667 .LFB9: - 598:.\Generated_Source\PSoC5/CyFlash.c **** - 599:.\Generated_Source\PSoC5/CyFlash.c **** - 600:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 601:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyEEPROM_Start - 602:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 603:.\Generated_Source\PSoC5/CyFlash.c **** * - 604:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 605:.\Generated_Source\PSoC5/CyFlash.c **** * Enable the EEPROM. - 606:.\Generated_Source\PSoC5/CyFlash.c **** * - 607:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 608:.\Generated_Source\PSoC5/CyFlash.c **** * None - 609:.\Generated_Source\PSoC5/CyFlash.c **** * - 610:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 611:.\Generated_Source\PSoC5/CyFlash.c **** * None - 612:.\Generated_Source\PSoC5/CyFlash.c **** * - 613:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 614:.\Generated_Source\PSoC5/CyFlash.c **** void CyEEPROM_Start(void) - 615:.\Generated_Source\PSoC5/CyFlash.c **** { - 668 .loc 1 615 0 - 669 .cfi_startproc - 670 @ args = 0, pretend = 0, frame = 0 - 671 @ frame_needed = 0, uses_anonymous_args = 0 - 672 @ link register save eliminated. - 616:.\Generated_Source\PSoC5/CyFlash.c **** /* Active Power Mode */ - 617:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; - 673 .loc 1 617 0 - 674 0000 044B ldr r3, .L91 - 675 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 676 0004 42F01000 orr r0, r2, #16 - 677 0008 1870 strb r0, [r3, #0] - 618:.\Generated_Source\PSoC5/CyFlash.c **** - 619:.\Generated_Source\PSoC5/CyFlash.c **** /* Standby Power Mode */ - 620:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; - 678 .loc 1 620 0 - 679 000a 197C ldrb r1, [r3, #16] @ zero_extendqisi2 - 680 000c 41F01002 orr r2, r1, #16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 25 - - - 681 0010 1A74 strb r2, [r3, #16] - 682 0012 7047 bx lr - 683 .L92: - 684 .align 2 - 685 .L91: - 686 0014 AC430040 .word 1073759148 - 687 .cfi_endproc - 688 .LFE9: - 689 .size CyEEPROM_Start, .-CyEEPROM_Start - 690 .section .text.CyEEPROM_Stop,"ax",%progbits - 691 .align 1 - 692 .global CyEEPROM_Stop - 693 .thumb - 694 .thumb_func - 695 .type CyEEPROM_Stop, %function - 696 CyEEPROM_Stop: - 697 .LFB10: - 621:.\Generated_Source\PSoC5/CyFlash.c **** } - 622:.\Generated_Source\PSoC5/CyFlash.c **** - 623:.\Generated_Source\PSoC5/CyFlash.c **** - 624:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 625:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyEEPROM_Stop - 626:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 627:.\Generated_Source\PSoC5/CyFlash.c **** * - 628:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 629:.\Generated_Source\PSoC5/CyFlash.c **** * Disable the EEPROM. - 630:.\Generated_Source\PSoC5/CyFlash.c **** * - 631:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 632:.\Generated_Source\PSoC5/CyFlash.c **** * None - 633:.\Generated_Source\PSoC5/CyFlash.c **** * - 634:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 635:.\Generated_Source\PSoC5/CyFlash.c **** * None - 636:.\Generated_Source\PSoC5/CyFlash.c **** * - 637:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 638:.\Generated_Source\PSoC5/CyFlash.c **** void CyEEPROM_Stop (void) - 639:.\Generated_Source\PSoC5/CyFlash.c **** { - 698 .loc 1 639 0 - 699 .cfi_startproc - 700 @ args = 0, pretend = 0, frame = 0 - 701 @ frame_needed = 0, uses_anonymous_args = 0 - 702 @ link register save eliminated. - 640:.\Generated_Source\PSoC5/CyFlash.c **** /* Active Power Mode */ - 641:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); - 703 .loc 1 641 0 - 704 0000 044B ldr r3, .L94 - 705 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 706 0004 02F0EF00 and r0, r2, #239 - 707 0008 1870 strb r0, [r3, #0] - 642:.\Generated_Source\PSoC5/CyFlash.c **** - 643:.\Generated_Source\PSoC5/CyFlash.c **** /* Standby Power Mode */ - 644:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); - 708 .loc 1 644 0 - 709 000a 197C ldrb r1, [r3, #16] @ zero_extendqisi2 - 710 000c 01F0EF02 and r2, r1, #239 - 711 0010 1A74 strb r2, [r3, #16] - 712 0012 7047 bx lr - 713 .L95: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 26 - - - 714 .align 2 - 715 .L94: - 716 0014 AC430040 .word 1073759148 - 717 .cfi_endproc - 718 .LFE10: - 719 .size CyEEPROM_Stop, .-CyEEPROM_Stop - 720 .section .text.CyEEPROM_ReadReserve,"ax",%progbits - 721 .align 1 - 722 .global CyEEPROM_ReadReserve - 723 .thumb - 724 .thumb_func - 725 .type CyEEPROM_ReadReserve, %function - 726 CyEEPROM_ReadReserve: - 727 .LFB11: - 645:.\Generated_Source\PSoC5/CyFlash.c **** } - 646:.\Generated_Source\PSoC5/CyFlash.c **** - 647:.\Generated_Source\PSoC5/CyFlash.c **** - 648:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 649:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyEEPROM_ReadReserve - 650:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 651:.\Generated_Source\PSoC5/CyFlash.c **** * - 652:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 653:.\Generated_Source\PSoC5/CyFlash.c **** * Request access to the EEPROM for reading and wait until access is available. - 654:.\Generated_Source\PSoC5/CyFlash.c **** * - 655:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 656:.\Generated_Source\PSoC5/CyFlash.c **** * None - 657:.\Generated_Source\PSoC5/CyFlash.c **** * - 658:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 659:.\Generated_Source\PSoC5/CyFlash.c **** * None - 660:.\Generated_Source\PSoC5/CyFlash.c **** * - 661:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 662:.\Generated_Source\PSoC5/CyFlash.c **** void CyEEPROM_ReadReserve(void) - 663:.\Generated_Source\PSoC5/CyFlash.c **** { - 728 .loc 1 663 0 - 729 .cfi_startproc - 730 @ args = 0, pretend = 0, frame = 0 - 731 @ frame_needed = 0, uses_anonymous_args = 0 - 732 @ link register save eliminated. - 664:.\Generated_Source\PSoC5/CyFlash.c **** /* Make a request for PHUB to have access */ - 665:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ; - 733 .loc 1 665 0 - 734 0000 064B ldr r3, .L102 - 735 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 736 0004 42F00100 orr r0, r2, #1 - 737 0008 1870 strb r0, [r3, #0] - 738 .L97: - 666:.\Generated_Source\PSoC5/CyFlash.c **** - 667:.\Generated_Source\PSoC5/CyFlash.c **** while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK)) - 739 .loc 1 667 0 discriminator 1 - 740 000a 0449 ldr r1, .L102 - 741 000c 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 742 000e 03F00202 and r2, r3, #2 - 743 0012 D0B2 uxtb r0, r2 - 744 0014 0028 cmp r0, #0 - 745 0016 F8D0 beq .L97 - 668:.\Generated_Source\PSoC5/CyFlash.c **** { - 669:.\Generated_Source\PSoC5/CyFlash.c **** /* Wait for acknowledgement from PHUB */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 27 - - - 670:.\Generated_Source\PSoC5/CyFlash.c **** } - 671:.\Generated_Source\PSoC5/CyFlash.c **** } - 746 .loc 1 671 0 - 747 0018 7047 bx lr - 748 .L103: - 749 001a 00BF .align 2 - 750 .L102: - 751 001c 02470040 .word 1073760002 - 752 .cfi_endproc - 753 .LFE11: - 754 .size CyEEPROM_ReadReserve, .-CyEEPROM_ReadReserve - 755 .section .text.CyEEPROM_ReadRelease,"ax",%progbits - 756 .align 1 - 757 .global CyEEPROM_ReadRelease - 758 .thumb - 759 .thumb_func - 760 .type CyEEPROM_ReadRelease, %function - 761 CyEEPROM_ReadRelease: - 762 .LFB12: - 672:.\Generated_Source\PSoC5/CyFlash.c **** - 673:.\Generated_Source\PSoC5/CyFlash.c **** - 674:.\Generated_Source\PSoC5/CyFlash.c **** /******************************************************************************* - 675:.\Generated_Source\PSoC5/CyFlash.c **** * Function Name: CyEEPROM_ReadRelease - 676:.\Generated_Source\PSoC5/CyFlash.c **** ******************************************************************************** - 677:.\Generated_Source\PSoC5/CyFlash.c **** * - 678:.\Generated_Source\PSoC5/CyFlash.c **** * Summary: - 679:.\Generated_Source\PSoC5/CyFlash.c **** * Release the read reservation of the EEPROM. - 680:.\Generated_Source\PSoC5/CyFlash.c **** * - 681:.\Generated_Source\PSoC5/CyFlash.c **** * Parameters: - 682:.\Generated_Source\PSoC5/CyFlash.c **** * None - 683:.\Generated_Source\PSoC5/CyFlash.c **** * - 684:.\Generated_Source\PSoC5/CyFlash.c **** * Return: - 685:.\Generated_Source\PSoC5/CyFlash.c **** * None - 686:.\Generated_Source\PSoC5/CyFlash.c **** * - 687:.\Generated_Source\PSoC5/CyFlash.c **** *******************************************************************************/ - 688:.\Generated_Source\PSoC5/CyFlash.c **** void CyEEPROM_ReadRelease(void) - 689:.\Generated_Source\PSoC5/CyFlash.c **** { - 763 .loc 1 689 0 - 764 .cfi_startproc - 765 @ args = 0, pretend = 0, frame = 0 - 766 @ frame_needed = 0, uses_anonymous_args = 0 - 767 @ link register save eliminated. - 690:.\Generated_Source\PSoC5/CyFlash.c **** *CY_FLASH_EE_SCR_PTR |= 0x00u; - 768 .loc 1 690 0 - 769 0000 014B ldr r3, .L105 - 770 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 771 0004 1A70 strb r2, [r3, #0] - 772 0006 7047 bx lr - 773 .L106: - 774 .align 2 - 775 .L105: - 776 0008 02470040 .word 1073760002 - 777 .cfi_endproc - 778 .LFE12: - 779 .size CyEEPROM_ReadRelease, .-CyEEPROM_ReadRelease - 780 .comm dieTemperature,2,1 - 781 .bss - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 28 - - - 782 .align 2 - 783 .set .LANCHOR0,. + 0 - 784 .type rowBuffer, %object - 785 .size rowBuffer, 4 - 786 rowBuffer: - 787 0000 00000000 .space 4 - 788 .text - 789 .Letext0: - 790 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 791 .file 3 ".\\Generated_Source\\PSoC5\\CySpc.h" - 792 .file 4 ".\\Generated_Source\\PSoC5\\CyLib.h" - 793 .section .debug_info,"",%progbits - 794 .Ldebug_info0: - 795 0000 22070000 .4byte 0x722 - 796 0004 0200 .2byte 0x2 - 797 0006 00000000 .4byte .Ldebug_abbrev0 - 798 000a 04 .byte 0x4 - 799 000b 01 .uleb128 0x1 - 800 000c 81020000 .4byte .LASF52 - 801 0010 01 .byte 0x1 - 802 0011 CA020000 .4byte .LASF53 - 803 0015 F1000000 .4byte .LASF54 - 804 0019 60000000 .4byte .Ldebug_ranges0+0x60 - 805 001d 00000000 .4byte 0 - 806 0021 00000000 .4byte 0 - 807 0025 00000000 .4byte .Ldebug_line0 - 808 0029 02 .uleb128 0x2 - 809 002a 01 .byte 0x1 - 810 002b 06 .byte 0x6 - 811 002c 05030000 .4byte .LASF0 - 812 0030 02 .uleb128 0x2 - 813 0031 01 .byte 0x1 - 814 0032 08 .byte 0x8 - 815 0033 50010000 .4byte .LASF1 - 816 0037 02 .uleb128 0x2 - 817 0038 02 .byte 0x2 - 818 0039 05 .byte 0x5 - 819 003a 7A010000 .4byte .LASF2 - 820 003e 02 .uleb128 0x2 - 821 003f 02 .byte 0x2 - 822 0040 07 .byte 0x7 - 823 0041 3F000000 .4byte .LASF3 - 824 0045 02 .uleb128 0x2 - 825 0046 04 .byte 0x4 - 826 0047 05 .byte 0x5 - 827 0048 ED020000 .4byte .LASF4 - 828 004c 02 .uleb128 0x2 - 829 004d 04 .byte 0x4 - 830 004e 07 .byte 0x7 - 831 004f DF000000 .4byte .LASF5 - 832 0053 02 .uleb128 0x2 - 833 0054 08 .byte 0x8 - 834 0055 05 .byte 0x5 - 835 0056 42020000 .4byte .LASF6 - 836 005a 02 .uleb128 0x2 - 837 005b 08 .byte 0x8 - 838 005c 07 .byte 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 29 - - - 839 005d 83000000 .4byte .LASF7 - 840 0061 03 .uleb128 0x3 - 841 0062 04 .byte 0x4 - 842 0063 05 .byte 0x5 - 843 0064 696E7400 .ascii "int\000" - 844 0068 02 .uleb128 0x2 - 845 0069 04 .byte 0x4 - 846 006a 07 .byte 0x7 - 847 006b D5010000 .4byte .LASF8 - 848 006f 04 .uleb128 0x4 - 849 0070 22010000 .4byte .LASF9 - 850 0074 02 .byte 0x2 - 851 0075 5B .byte 0x5b - 852 0076 30000000 .4byte 0x30 - 853 007a 04 .uleb128 0x4 - 854 007b A6010000 .4byte .LASF10 - 855 007f 02 .byte 0x2 - 856 0080 5C .byte 0x5c - 857 0081 3E000000 .4byte 0x3e - 858 0085 04 .uleb128 0x4 - 859 0086 B7010000 .4byte .LASF11 - 860 008a 02 .byte 0x2 - 861 008b 5D .byte 0x5d - 862 008c 4C000000 .4byte 0x4c - 863 0090 02 .uleb128 0x2 - 864 0091 04 .byte 0x4 - 865 0092 04 .byte 0x4 - 866 0093 67000000 .4byte .LASF12 - 867 0097 02 .uleb128 0x2 - 868 0098 08 .byte 0x8 - 869 0099 04 .byte 0x4 - 870 009a 5E010000 .4byte .LASF13 - 871 009e 02 .uleb128 0x2 - 872 009f 01 .byte 0x1 - 873 00a0 08 .byte 0x8 - 874 00a1 F6020000 .4byte .LASF14 - 875 00a5 04 .uleb128 0x4 - 876 00a6 00000000 .4byte .LASF15 - 877 00aa 02 .byte 0x2 - 878 00ab E8 .byte 0xe8 - 879 00ac 4C000000 .4byte 0x4c - 880 00b0 04 .uleb128 0x4 - 881 00b1 09000000 .4byte .LASF16 - 882 00b5 02 .byte 0x2 - 883 00b6 F0 .byte 0xf0 - 884 00b7 BB000000 .4byte 0xbb - 885 00bb 05 .uleb128 0x5 - 886 00bc 6F000000 .4byte 0x6f - 887 00c0 02 .uleb128 0x2 - 888 00c1 04 .byte 0x4 - 889 00c2 07 .byte 0x7 - 890 00c3 2F020000 .4byte .LASF17 - 891 00c7 06 .uleb128 0x6 - 892 00c8 04 .byte 0x4 - 893 00c9 07 .uleb128 0x7 - 894 00ca 61020000 .4byte .LASF55 - 895 00ce 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 30 - - - 896 00cf 71 .byte 0x71 - 897 00d0 01 .byte 0x1 - 898 00d1 A5000000 .4byte 0xa5 - 899 00d5 01 .byte 0x1 - 900 00d6 E6000000 .4byte 0xe6 - 901 00da 08 .uleb128 0x8 - 902 00db 60000000 .4byte .LASF22 - 903 00df 01 .byte 0x1 - 904 00e0 73 .byte 0x73 - 905 00e1 A5000000 .4byte 0xa5 - 906 00e5 00 .byte 0 - 907 00e6 09 .uleb128 0x9 - 908 00e7 01 .byte 0x1 - 909 00e8 11030000 .4byte .LASF41 - 910 00ec 01 .byte 0x1 - 911 00ed C401 .2byte 0x1c4 - 912 00ef 01 .byte 0x1 - 913 00f0 A5000000 .4byte 0xa5 - 914 00f4 01 .byte 0x1 - 915 00f5 36010000 .4byte 0x136 - 916 00f9 0A .uleb128 0xa - 917 00fa 28010000 .4byte .LASF18 - 918 00fe 01 .byte 0x1 - 919 00ff C401 .2byte 0x1c4 - 920 0101 6F000000 .4byte 0x6f - 921 0105 0A .uleb128 0xa - 922 0106 FB020000 .4byte .LASF19 - 923 010a 01 .byte 0x1 - 924 010b C401 .2byte 0x1c4 - 925 010d 7A000000 .4byte 0x7a - 926 0111 0A .uleb128 0xa - 927 0112 B9000000 .4byte .LASF20 - 928 0116 01 .byte 0x1 - 929 0117 C401 .2byte 0x1c4 - 930 0119 36010000 .4byte 0x136 - 931 011d 0A .uleb128 0xa - 932 011e 72010000 .4byte .LASF21 - 933 0122 01 .byte 0x1 - 934 0123 C401 .2byte 0x1c4 - 935 0125 7A000000 .4byte 0x7a - 936 0129 0B .uleb128 0xb - 937 012a 60000000 .4byte .LASF22 - 938 012e 01 .byte 0x1 - 939 012f C701 .2byte 0x1c7 - 940 0131 A5000000 .4byte 0xa5 - 941 0135 00 .byte 0 - 942 0136 0C .uleb128 0xc - 943 0137 04 .byte 0x4 - 944 0138 3C010000 .4byte 0x13c - 945 013c 0D .uleb128 0xd - 946 013d 6F000000 .4byte 0x6f - 947 0141 0E .uleb128 0xe - 948 0142 C9000000 .4byte 0xc9 - 949 0146 00000000 .4byte .LFB13 - 950 014a 54000000 .4byte .LFE13 - 951 014e 00000000 .4byte .LLST0 - 952 0152 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 31 - - - 953 0153 AA010000 .4byte 0x1aa - 954 0157 0F .uleb128 0xf - 955 0158 DA000000 .4byte 0xda - 956 015c 01 .byte 0x1 - 957 015d 54 .byte 0x54 - 958 015e 10 .uleb128 0x10 - 959 015f 08000000 .4byte .LVL0 - 960 0163 2B060000 .4byte 0x62b - 961 0167 71010000 .4byte 0x171 - 962 016b 11 .uleb128 0x11 - 963 016c 01 .byte 0x1 - 964 016d 50 .byte 0x50 - 965 016e 01 .byte 0x1 - 966 016f 31 .byte 0x31 - 967 0170 00 .byte 0 - 968 0171 10 .uleb128 0x10 - 969 0172 28000000 .4byte .LVL1 - 970 0176 43060000 .4byte 0x643 - 971 017a 8D010000 .4byte 0x18d - 972 017e 11 .uleb128 0x11 - 973 017f 01 .byte 0x1 - 974 0180 51 .byte 0x51 - 975 0181 01 .byte 0x1 - 976 0182 32 .byte 0x32 - 977 0183 11 .uleb128 0x11 - 978 0184 01 .byte 0x1 - 979 0185 50 .byte 0x50 - 980 0186 05 .byte 0x5 - 981 0187 03 .byte 0x3 - 982 0188 00000000 .4byte dieTemperature - 983 018c 00 .byte 0 - 984 018d 10 .uleb128 0x10 - 985 018e 3E000000 .4byte .LVL2 - 986 0192 60060000 .4byte 0x660 - 987 0196 A0010000 .4byte 0x1a0 - 988 019a 11 .uleb128 0x11 - 989 019b 01 .byte 0x1 - 990 019c 50 .byte 0x50 - 991 019d 01 .byte 0x1 - 992 019e 31 .byte 0x31 - 993 019f 00 .byte 0 - 994 01a0 12 .uleb128 0x12 - 995 01a1 46000000 .4byte .LVL4 - 996 01a5 74060000 .4byte 0x674 - 997 01a9 00 .byte 0 - 998 01aa 13 .uleb128 0x13 - 999 01ab 01 .byte 0x1 - 1000 01ac E2010000 .4byte .LASF31 - 1001 01b0 01 .byte 0x1 - 1002 01b1 36 .byte 0x36 - 1003 01b2 01 .byte 0x1 - 1004 01b3 00000000 .4byte .LFB0 - 1005 01b7 1C000000 .4byte .LFE0 - 1006 01bb 02 .byte 0x2 - 1007 01bc 7D .byte 0x7d - 1008 01bd 00 .sleb128 0 - 1009 01be 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 32 - - - 1010 01bf D4010000 .4byte 0x1d4 - 1011 01c3 14 .uleb128 0x14 - 1012 01c4 18000000 .4byte .LVL5 - 1013 01c8 01 .byte 0x1 - 1014 01c9 60060000 .4byte 0x660 - 1015 01cd 11 .uleb128 0x11 - 1016 01ce 01 .byte 0x1 - 1017 01cf 50 .byte 0x50 - 1018 01d0 01 .byte 0x1 - 1019 01d1 35 .byte 0x35 - 1020 01d2 00 .byte 0 - 1021 01d3 00 .byte 0 - 1022 01d4 15 .uleb128 0x15 - 1023 01d5 01 .byte 0x1 - 1024 01d6 65010000 .4byte .LASF35 - 1025 01da 01 .byte 0x1 - 1026 01db 54 .byte 0x54 - 1027 01dc 01 .byte 0x1 - 1028 01dd 00000000 .4byte .LFB1 - 1029 01e1 18000000 .4byte .LFE1 - 1030 01e5 02 .byte 0x2 - 1031 01e6 7D .byte 0x7d - 1032 01e7 00 .sleb128 0 - 1033 01e8 01 .byte 0x1 - 1034 01e9 16 .uleb128 0x16 - 1035 01ea 01 .byte 0x1 - 1036 01eb 38020000 .4byte .LASF23 - 1037 01ef 01 .byte 0x1 - 1038 01f0 B3 .byte 0xb3 - 1039 01f1 01 .byte 0x1 - 1040 01f2 A5000000 .4byte 0xa5 - 1041 01f6 00000000 .4byte .LFB3 - 1042 01fa 28000000 .4byte .LFE3 - 1043 01fe 20000000 .4byte .LLST1 - 1044 0202 01 .byte 0x1 - 1045 0203 96020000 .4byte 0x296 - 1046 0207 17 .uleb128 0x17 - 1047 0208 60000000 .4byte .LASF22 - 1048 020c 01 .byte 0x1 - 1049 020d B5 .byte 0xb5 - 1050 020e A5000000 .4byte 0xa5 - 1051 0212 01 .byte 0x1 - 1052 0213 50 .byte 0x50 - 1053 0214 18 .uleb128 0x18 - 1054 0215 C9000000 .4byte 0xc9 - 1055 0219 02000000 .4byte .LBB6 - 1056 021d 00000000 .4byte .Ldebug_ranges0+0 - 1057 0221 01 .byte 0x1 - 1058 0222 B5 .byte 0xb5 - 1059 0223 49020000 .4byte 0x249 - 1060 0227 19 .uleb128 0x19 - 1061 0228 18000000 .4byte .Ldebug_ranges0+0x18 - 1062 022c 1A .uleb128 0x1a - 1063 022d DA000000 .4byte 0xda - 1064 0231 40000000 .4byte .LLST2 - 1065 0235 12 .uleb128 0x12 - 1066 0236 06000000 .4byte .LVL6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 33 - - - 1067 023a 7E060000 .4byte 0x67e - 1068 023e 12 .uleb128 0x12 - 1069 023f 0A000000 .4byte .LVL7 - 1070 0243 88060000 .4byte 0x688 - 1071 0247 00 .byte 0 - 1072 0248 00 .byte 0 - 1073 0249 1B .uleb128 0x1b - 1074 024a C9000000 .4byte 0xc9 - 1075 024e 12000000 .4byte .LBB9 - 1076 0252 1C000000 .4byte .LBE9 - 1077 0256 01 .byte 0x1 - 1078 0257 B9 .byte 0xb9 - 1079 0258 82020000 .4byte 0x282 - 1080 025c 1C .uleb128 0x1c - 1081 025d 12000000 .4byte .LBB10 - 1082 0261 1C000000 .4byte .LBE10 - 1083 0265 1A .uleb128 0x1a - 1084 0266 DA000000 .4byte 0xda - 1085 026a 60000000 .4byte .LLST3 - 1086 026e 12 .uleb128 0x12 - 1087 026f 16000000 .4byte .LVL9 - 1088 0273 7E060000 .4byte 0x67e - 1089 0277 12 .uleb128 0x12 - 1090 0278 1A000000 .4byte .LVL10 - 1091 027c 88060000 .4byte 0x688 - 1092 0280 00 .byte 0 - 1093 0281 00 .byte 0 - 1094 0282 12 .uleb128 0x12 - 1095 0283 10000000 .4byte .LVL8 - 1096 0287 41010000 .4byte 0x141 - 1097 028b 1D .uleb128 0x1d - 1098 028c 24000000 .4byte .LVL11 - 1099 0290 01 .byte 0x1 - 1100 0291 41010000 .4byte 0x141 - 1101 0295 00 .byte 0 - 1102 0296 16 .uleb128 0x16 - 1103 0297 01 .byte 0x1 - 1104 0298 9A000000 .4byte .LASF24 - 1105 029c 01 .byte 0x1 - 1106 029d D4 .byte 0xd4 - 1107 029e 01 .byte 0x1 - 1108 029f A5000000 .4byte 0xa5 - 1109 02a3 00000000 .4byte .LFB4 - 1110 02a7 2C000000 .4byte .LFE4 - 1111 02ab 75000000 .4byte .LLST4 - 1112 02af 01 .byte 0x1 - 1113 02b0 EE020000 .4byte 0x2ee - 1114 02b4 1E .uleb128 0x1e - 1115 02b5 7A020000 .4byte .LASF26 - 1116 02b9 01 .byte 0x1 - 1117 02ba D4 .byte 0xd4 - 1118 02bb EE020000 .4byte 0x2ee - 1119 02bf 95000000 .4byte .LLST5 - 1120 02c3 1F .uleb128 0x1f - 1121 02c4 60000000 .4byte .LASF22 - 1122 02c8 01 .byte 0x1 - 1123 02c9 D6 .byte 0xd6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 34 - - - 1124 02ca A5000000 .4byte 0xa5 - 1125 02ce B3000000 .4byte .LLST6 - 1126 02d2 12 .uleb128 0x12 - 1127 02d3 08000000 .4byte .LVL14 - 1128 02d7 7E060000 .4byte 0x67e - 1129 02db 12 .uleb128 0x12 - 1130 02dc 0E000000 .4byte .LVL15 - 1131 02e0 88060000 .4byte 0x688 - 1132 02e4 12 .uleb128 0x12 - 1133 02e5 1A000000 .4byte .LVL16 - 1134 02e9 74060000 .4byte 0x674 - 1135 02ed 00 .byte 0 - 1136 02ee 0C .uleb128 0xc - 1137 02ef 04 .byte 0x4 - 1138 02f0 6F000000 .4byte 0x6f - 1139 02f4 0E .uleb128 0xe - 1140 02f5 E6000000 .4byte 0xe6 - 1141 02f9 00000000 .4byte .LFB7 - 1142 02fd A0000000 .4byte .LFE7 - 1143 0301 D2000000 .4byte .LLST7 - 1144 0305 01 .byte 0x1 - 1145 0306 EE030000 .4byte 0x3ee - 1146 030a 20 .uleb128 0x20 - 1147 030b F9000000 .4byte 0xf9 - 1148 030f F2000000 .4byte .LLST8 - 1149 0313 20 .uleb128 0x20 - 1150 0314 05010000 .4byte 0x105 - 1151 0318 13010000 .4byte .LLST9 - 1152 031c 20 .uleb128 0x20 - 1153 031d 11010000 .4byte 0x111 - 1154 0321 34010000 .4byte .LLST10 - 1155 0325 20 .uleb128 0x20 - 1156 0326 1D010000 .4byte 0x11d - 1157 032a 52010000 .4byte .LLST11 - 1158 032e 1A .uleb128 0x1a - 1159 032f 29010000 .4byte 0x129 - 1160 0333 73010000 .4byte .LLST12 - 1161 0337 21 .uleb128 0x21 - 1162 0338 E6000000 .4byte 0xe6 - 1163 033c 10000000 .4byte .LBB14 - 1164 0340 30000000 .4byte .Ldebug_ranges0+0x30 - 1165 0344 01 .byte 0x1 - 1166 0345 C401 .2byte 0x1c4 - 1167 0347 E4030000 .4byte 0x3e4 - 1168 034b 20 .uleb128 0x20 - 1169 034c 1D010000 .4byte 0x11d - 1170 0350 86010000 .4byte .LLST13 - 1171 0354 20 .uleb128 0x20 - 1172 0355 11010000 .4byte 0x111 - 1173 0359 99010000 .4byte .LLST14 - 1174 035d 20 .uleb128 0x20 - 1175 035e 05010000 .4byte 0x105 - 1176 0362 B7010000 .4byte .LLST15 - 1177 0366 20 .uleb128 0x20 - 1178 0367 F9000000 .4byte 0xf9 - 1179 036b D5010000 .4byte .LLST16 - 1180 036f 19 .uleb128 0x19 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 35 - - - 1181 0370 48000000 .4byte .Ldebug_ranges0+0x48 - 1182 0374 1A .uleb128 0x1a - 1183 0375 29010000 .4byte 0x129 - 1184 0379 F3010000 .4byte .LLST17 - 1185 037d 10 .uleb128 0x10 - 1186 037e 1A000000 .4byte .LVL21 - 1187 0382 96060000 .4byte 0x696 - 1188 0386 9D030000 .4byte 0x39d - 1189 038a 11 .uleb128 0x11 - 1190 038b 01 .byte 0x1 - 1191 038c 52 .byte 0x52 - 1192 038d 02 .byte 0x2 - 1193 038e 74 .byte 0x74 - 1194 038f 00 .sleb128 0 - 1195 0390 11 .uleb128 0x11 - 1196 0391 01 .byte 0x1 - 1197 0392 51 .byte 0x51 - 1198 0393 02 .byte 0x2 - 1199 0394 77 .byte 0x77 - 1200 0395 00 .sleb128 0 - 1201 0396 11 .uleb128 0x11 - 1202 0397 01 .byte 0x1 - 1203 0398 50 .byte 0x50 - 1204 0399 02 .byte 0x2 - 1205 039a 75 .byte 0x75 - 1206 039b 00 .sleb128 0 - 1207 039c 00 .byte 0 - 1208 039d 10 .uleb128 0x10 - 1209 039e 32000000 .4byte .LVL24 - 1210 03a2 60060000 .4byte 0x660 - 1211 03a6 B0030000 .4byte 0x3b0 - 1212 03aa 11 .uleb128 0x11 - 1213 03ab 01 .byte 0x1 - 1214 03ac 50 .byte 0x50 - 1215 03ad 01 .byte 0x1 - 1216 03ae 31 .byte 0x31 - 1217 03af 00 .byte 0 - 1218 03b0 12 .uleb128 0x12 - 1219 03b1 4C000000 .4byte .LVL27 - 1220 03b5 74060000 .4byte 0x674 - 1221 03b9 10 .uleb128 0x10 - 1222 03ba 60000000 .4byte .LVL31 - 1223 03be B8060000 .4byte 0x6b8 - 1224 03c2 D3030000 .4byte 0x3d3 - 1225 03c6 11 .uleb128 0x11 - 1226 03c7 01 .byte 0x1 - 1227 03c8 51 .byte 0x51 - 1228 03c9 02 .byte 0x2 - 1229 03ca 76 .byte 0x76 - 1230 03cb 00 .sleb128 0 - 1231 03cc 11 .uleb128 0x11 - 1232 03cd 01 .byte 0x1 - 1233 03ce 50 .byte 0x50 - 1234 03cf 02 .byte 0x2 - 1235 03d0 75 .byte 0x75 - 1236 03d1 00 .sleb128 0 - 1237 03d2 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 36 - - - 1238 03d3 22 .uleb128 0x22 - 1239 03d4 78000000 .4byte .LVL34 - 1240 03d8 60060000 .4byte 0x660 - 1241 03dc 11 .uleb128 0x11 - 1242 03dd 01 .byte 0x1 - 1243 03de 50 .byte 0x50 - 1244 03df 01 .byte 0x1 - 1245 03e0 31 .byte 0x31 - 1246 03e1 00 .byte 0 - 1247 03e2 00 .byte 0 - 1248 03e3 00 .byte 0 - 1249 03e4 12 .uleb128 0x12 - 1250 03e5 0E000000 .4byte .LVL19 - 1251 03e9 88060000 .4byte 0x688 - 1252 03ed 00 .byte 0 - 1253 03ee 23 .uleb128 0x23 - 1254 03ef 01 .byte 0x1 - 1255 03f0 3F010000 .4byte .LASF25 - 1256 03f4 01 .byte 0x1 - 1257 03f5 8101 .2byte 0x181 - 1258 03f7 01 .byte 0x1 - 1259 03f8 A5000000 .4byte 0xa5 - 1260 03fc 00000000 .4byte .LFB6 - 1261 0400 48000000 .4byte .LFE6 - 1262 0404 3E020000 .4byte .LLST18 - 1263 0408 01 .byte 0x1 - 1264 0409 81040000 .4byte 0x481 - 1265 040d 24 .uleb128 0x24 - 1266 040e 28010000 .4byte .LASF18 - 1267 0412 01 .byte 0x1 - 1268 0413 8101 .2byte 0x181 - 1269 0415 6F000000 .4byte 0x6f - 1270 0419 5E020000 .4byte .LLST19 - 1271 041d 24 .uleb128 0x24 - 1272 041e 20030000 .4byte .LASF27 - 1273 0422 01 .byte 0x1 - 1274 0423 8101 .2byte 0x181 - 1275 0425 7A000000 .4byte 0x7a - 1276 0429 98020000 .4byte .LLST20 - 1277 042d 24 .uleb128 0x24 - 1278 042e 06020000 .4byte .LASF28 - 1279 0432 01 .byte 0x1 - 1280 0433 8101 .2byte 0x181 - 1281 0435 36010000 .4byte 0x136 - 1282 0439 C4020000 .4byte .LLST21 - 1283 043d 25 .uleb128 0x25 - 1284 043e 6E020000 .4byte .LASF29 - 1285 0442 01 .byte 0x1 - 1286 0443 8401 .2byte 0x184 - 1287 0445 85000000 .4byte 0x85 - 1288 0449 EF020000 .4byte .LLST22 - 1289 044d 26 .uleb128 0x26 - 1290 044e 6900 .ascii "i\000" - 1291 0450 01 .byte 0x1 - 1292 0451 8501 .2byte 0x185 - 1293 0453 7A000000 .4byte 0x7a - 1294 0457 16030000 .4byte .LLST23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 37 - - - 1295 045b 27 .uleb128 0x27 - 1296 045c 60000000 .4byte .LASF22 - 1297 0460 01 .byte 0x1 - 1298 0461 8601 .2byte 0x186 - 1299 0463 A5000000 .4byte 0xa5 - 1300 0467 7F .sleb128 -1 - 1301 0468 14 .uleb128 0x14 - 1302 0469 3E000000 .4byte .LVL41 - 1303 046d 01 .byte 0x1 - 1304 046e E6000000 .4byte 0xe6 - 1305 0472 11 .uleb128 0x11 - 1306 0473 01 .byte 0x1 - 1307 0474 53 .byte 0x53 - 1308 0475 03 .byte 0x3 - 1309 0476 0A .byte 0xa - 1310 0477 2001 .2byte 0x120 - 1311 0479 11 .uleb128 0x11 - 1312 047a 01 .byte 0x1 - 1313 047b 52 .byte 0x52 - 1314 047c 02 .byte 0x2 - 1315 047d 74 .byte 0x74 - 1316 047e 00 .sleb128 0 - 1317 047f 00 .byte 0 - 1318 0480 00 .byte 0 - 1319 0481 23 .uleb128 0x23 - 1320 0482 01 .byte 0x1 - 1321 0483 2B030000 .4byte .LASF30 - 1322 0487 01 .byte 0x1 - 1323 0488 3601 .2byte 0x136 - 1324 048a 01 .byte 0x1 - 1325 048b A5000000 .4byte 0xa5 - 1326 048f 00000000 .4byte .LFB5 - 1327 0493 5C000000 .4byte .LFE5 - 1328 0497 2A030000 .4byte .LLST24 - 1329 049b 01 .byte 0x1 - 1330 049c 51050000 .4byte 0x551 - 1331 04a0 24 .uleb128 0x24 - 1332 04a1 28010000 .4byte .LASF18 - 1333 04a5 01 .byte 0x1 - 1334 04a6 3601 .2byte 0x136 - 1335 04a8 6F000000 .4byte 0x6f - 1336 04ac 4A030000 .4byte .LLST25 - 1337 04b0 24 .uleb128 0x24 - 1338 04b1 20030000 .4byte .LASF27 - 1339 04b5 01 .byte 0x1 - 1340 04b6 3601 .2byte 0x136 - 1341 04b8 7A000000 .4byte 0x7a - 1342 04bc 9D030000 .4byte .LLST26 - 1343 04c0 24 .uleb128 0x24 - 1344 04c1 B9000000 .4byte .LASF20 - 1345 04c5 01 .byte 0x1 - 1346 04c6 3601 .2byte 0x136 - 1347 04c8 36010000 .4byte 0x136 - 1348 04cc E2030000 .4byte .LLST27 - 1349 04d0 26 .uleb128 0x26 - 1350 04d1 6900 .ascii "i\000" - 1351 04d3 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 38 - - - 1352 04d4 3801 .2byte 0x138 - 1353 04d6 6F000000 .4byte 0x6f - 1354 04da 19040000 .4byte .LLST28 - 1355 04de 25 .uleb128 0x25 - 1356 04df 6E020000 .4byte .LASF29 - 1357 04e3 01 .byte 0x1 - 1358 04e4 3901 .2byte 0x139 - 1359 04e6 85000000 .4byte 0x85 - 1360 04ea 2D040000 .4byte .LLST29 - 1361 04ee 25 .uleb128 0x25 - 1362 04ef 72010000 .4byte .LASF21 - 1363 04f3 01 .byte 0x1 - 1364 04f4 3A01 .2byte 0x13a - 1365 04f6 7A000000 .4byte 0x7a - 1366 04fa 56040000 .4byte .LLST30 - 1367 04fe 27 .uleb128 0x27 - 1368 04ff 60000000 .4byte .LASF22 - 1369 0503 01 .byte 0x1 - 1370 0504 3B01 .2byte 0x13b - 1371 0506 A5000000 .4byte 0xa5 - 1372 050a 7F .sleb128 -1 - 1373 050b 10 .uleb128 0x10 - 1374 050c 40000000 .4byte .LVL52 - 1375 0510 DF060000 .4byte 0x6df - 1376 0514 2D050000 .4byte 0x52d - 1377 0518 11 .uleb128 0x11 - 1378 0519 01 .byte 0x1 - 1379 051a 52 .byte 0x52 - 1380 051b 03 .byte 0x3 - 1381 051c 0A .byte 0xa - 1382 051d 0001 .2byte 0x100 - 1383 051f 11 .uleb128 0x11 - 1384 0520 01 .byte 0x1 - 1385 0521 51 .byte 0x51 - 1386 0522 03 .byte 0x3 - 1387 0523 F3 .byte 0xf3 - 1388 0524 01 .uleb128 0x1 - 1389 0525 52 .byte 0x52 - 1390 0526 11 .uleb128 0x11 - 1391 0527 01 .byte 0x1 - 1392 0528 50 .byte 0x50 - 1393 0529 02 .byte 0x2 - 1394 052a 74 .byte 0x74 - 1395 052b 00 .sleb128 0 - 1396 052c 00 .byte 0 - 1397 052d 14 .uleb128 0x14 - 1398 052e 50000000 .4byte .LVL53 - 1399 0532 01 .byte 0x1 - 1400 0533 E6000000 .4byte 0xe6 - 1401 0537 11 .uleb128 0x11 - 1402 0538 01 .byte 0x1 - 1403 0539 53 .byte 0x53 - 1404 053a 02 .byte 0x2 - 1405 053b 76 .byte 0x76 - 1406 053c 00 .sleb128 0 - 1407 053d 11 .uleb128 0x11 - 1408 053e 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 39 - - - 1409 053f 52 .byte 0x52 - 1410 0540 02 .byte 0x2 - 1411 0541 74 .byte 0x74 - 1412 0542 00 .sleb128 0 - 1413 0543 11 .uleb128 0x11 - 1414 0544 01 .byte 0x1 - 1415 0545 51 .byte 0x51 - 1416 0546 02 .byte 0x2 - 1417 0547 77 .byte 0x77 - 1418 0548 00 .sleb128 0 - 1419 0549 11 .uleb128 0x11 - 1420 054a 01 .byte 0x1 - 1421 054b 50 .byte 0x50 - 1422 054c 02 .byte 0x2 - 1423 054d 75 .byte 0x75 - 1424 054e 00 .sleb128 0 - 1425 054f 00 .byte 0 - 1426 0550 00 .byte 0 - 1427 0551 28 .uleb128 0x28 - 1428 0552 01 .byte 0x1 - 1429 0553 6D000000 .4byte .LASF32 - 1430 0557 01 .byte 0x1 - 1431 0558 1802 .2byte 0x218 - 1432 055a 01 .byte 0x1 - 1433 055b 00000000 .4byte .LFB8 - 1434 055f 44000000 .4byte .LFE8 - 1435 0563 77040000 .4byte .LLST31 - 1436 0567 01 .byte 0x1 - 1437 0568 A0050000 .4byte 0x5a0 - 1438 056c 24 .uleb128 0x24 - 1439 056d 75020000 .4byte .LASF33 - 1440 0571 01 .byte 0x1 - 1441 0572 1802 .2byte 0x218 - 1442 0574 6F000000 .4byte 0x6f - 1443 0578 97040000 .4byte .LLST32 - 1444 057c 25 .uleb128 0x25 - 1445 057d D0000000 .4byte .LASF34 - 1446 0581 01 .byte 0x1 - 1447 0582 1A02 .2byte 0x21a - 1448 0584 6F000000 .4byte 0x6f - 1449 0588 B8040000 .4byte .LLST33 - 1450 058c 12 .uleb128 0x12 - 1451 058d 08000000 .4byte .LVL56 - 1452 0591 07070000 .4byte 0x707 - 1453 0595 1D .uleb128 0x1d - 1454 0596 3E000000 .4byte .LVL57 - 1455 059a 01 .byte 0x1 - 1456 059b 15070000 .4byte 0x715 - 1457 059f 00 .byte 0 - 1458 05a0 29 .uleb128 0x29 - 1459 05a1 01 .byte 0x1 - 1460 05a2 C1000000 .4byte .LASF36 - 1461 05a6 01 .byte 0x1 - 1462 05a7 6602 .2byte 0x266 - 1463 05a9 01 .byte 0x1 - 1464 05aa 00000000 .4byte .LFB9 - 1465 05ae 18000000 .4byte .LFE9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 40 - - - 1466 05b2 02 .byte 0x2 - 1467 05b3 7D .byte 0x7d - 1468 05b4 00 .sleb128 0 - 1469 05b5 01 .byte 0x1 - 1470 05b6 29 .uleb128 0x29 - 1471 05b7 01 .byte 0x1 - 1472 05b8 18000000 .4byte .LASF37 - 1473 05bc 01 .byte 0x1 - 1474 05bd 7E02 .2byte 0x27e - 1475 05bf 01 .byte 0x1 - 1476 05c0 00000000 .4byte .LFB10 - 1477 05c4 18000000 .4byte .LFE10 - 1478 05c8 02 .byte 0x2 - 1479 05c9 7D .byte 0x7d - 1480 05ca 00 .sleb128 0 - 1481 05cb 01 .byte 0x1 - 1482 05cc 29 .uleb128 0x29 - 1483 05cd 01 .byte 0x1 - 1484 05ce 0D020000 .4byte .LASF38 - 1485 05d2 01 .byte 0x1 - 1486 05d3 9602 .2byte 0x296 - 1487 05d5 01 .byte 0x1 - 1488 05d6 00000000 .4byte .LFB11 - 1489 05da 20000000 .4byte .LFE11 - 1490 05de 02 .byte 0x2 - 1491 05df 7D .byte 0x7d - 1492 05e0 00 .sleb128 0 - 1493 05e1 01 .byte 0x1 - 1494 05e2 29 .uleb128 0x29 - 1495 05e3 01 .byte 0x1 - 1496 05e4 84010000 .4byte .LASF39 - 1497 05e8 01 .byte 0x1 - 1498 05e9 B002 .2byte 0x2b0 - 1499 05eb 01 .byte 0x1 - 1500 05ec 00000000 .4byte .LFB12 - 1501 05f0 0C000000 .4byte .LFE12 - 1502 05f4 02 .byte 0x2 - 1503 05f5 7D .byte 0x7d - 1504 05f6 00 .sleb128 0 - 1505 05f7 01 .byte 0x1 - 1506 05f8 17 .uleb128 0x17 - 1507 05f9 0E000000 .4byte .LASF40 - 1508 05fd 01 .byte 0x1 - 1509 05fe 21 .byte 0x21 - 1510 05ff EE020000 .4byte 0x2ee - 1511 0603 05 .byte 0x5 - 1512 0604 03 .byte 0x3 - 1513 0605 00000000 .4byte rowBuffer - 1514 0609 2A .uleb128 0x2a - 1515 060a 6F000000 .4byte 0x6f - 1516 060e 19060000 .4byte 0x619 - 1517 0612 2B .uleb128 0x2b - 1518 0613 C0000000 .4byte 0xc0 - 1519 0617 01 .byte 0x1 - 1520 0618 00 .byte 0 - 1521 0619 2C .uleb128 0x2c - 1522 061a 30010000 .4byte .LASF56 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 41 - - - 1523 061e 01 .byte 0x1 - 1524 061f 1E .byte 0x1e - 1525 0620 09060000 .4byte 0x609 - 1526 0624 01 .byte 0x1 - 1527 0625 05 .byte 0x5 - 1528 0626 03 .byte 0x3 - 1529 0627 00000000 .4byte dieTemperature - 1530 062b 2D .uleb128 0x2d - 1531 062c 01 .byte 0x1 - 1532 062d 99010000 .4byte .LASF42 - 1533 0631 03 .byte 0x3 - 1534 0632 2B .byte 0x2b - 1535 0633 01 .byte 0x1 - 1536 0634 A5000000 .4byte 0xa5 - 1537 0638 01 .byte 0x1 - 1538 0639 43060000 .4byte 0x643 - 1539 063d 2E .uleb128 0x2e - 1540 063e 6F000000 .4byte 0x6f - 1541 0642 00 .byte 0 - 1542 0643 2D .uleb128 0x2d - 1543 0644 01 .byte 0x1 - 1544 0645 52000000 .4byte .LASF43 - 1545 0649 03 .byte 0x3 - 1546 064a 24 .byte 0x24 - 1547 064b 01 .byte 0x1 - 1548 064c 6F000000 .4byte 0x6f - 1549 0650 01 .byte 0x1 - 1550 0651 60060000 .4byte 0x660 - 1551 0655 2E .uleb128 0x2e - 1552 0656 EE020000 .4byte 0x2ee - 1553 065a 2E .uleb128 0x2e - 1554 065b 6F000000 .4byte 0x6f - 1555 065f 00 .byte 0 - 1556 0660 2F .uleb128 0x2f - 1557 0661 01 .byte 0x1 - 1558 0662 50020000 .4byte .LASF48 - 1559 0666 04 .byte 0x4 - 1560 0667 78 .byte 0x78 - 1561 0668 01 .byte 0x1 - 1562 0669 01 .byte 0x1 - 1563 066a 74060000 .4byte 0x674 - 1564 066e 2E .uleb128 0x2e - 1565 066f 7A000000 .4byte 0x7a - 1566 0673 00 .byte 0 - 1567 0674 30 .uleb128 0x30 - 1568 0675 01 .byte 0x1 - 1569 0676 AD000000 .4byte .LASF44 - 1570 067a 03 .byte 0x3 - 1571 067b 2D .byte 0x2d - 1572 067c 01 .byte 0x1 - 1573 067d 01 .byte 0x1 - 1574 067e 30 .uleb128 0x30 - 1575 067f 01 .byte 0x1 - 1576 0680 26000000 .4byte .LASF45 - 1577 0684 03 .byte 0x3 - 1578 0685 22 .byte 0x22 - 1579 0686 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 42 - - - 1580 0687 01 .byte 0x1 - 1581 0688 31 .uleb128 0x31 - 1582 0689 01 .byte 0x1 - 1583 068a AD010000 .4byte .LASF50 - 1584 068e 03 .byte 0x3 - 1585 068f 2C .byte 0x2c - 1586 0690 01 .byte 0x1 - 1587 0691 A5000000 .4byte 0xa5 - 1588 0695 01 .byte 0x1 - 1589 0696 2D .uleb128 0x2d - 1590 0697 01 .byte 0x1 - 1591 0698 22020000 .4byte .LASF46 - 1592 069c 03 .byte 0x3 - 1593 069d 27 .byte 0x27 - 1594 069e 01 .byte 0x1 - 1595 069f A5000000 .4byte 0xa5 - 1596 06a3 01 .byte 0x1 - 1597 06a4 B8060000 .4byte 0x6b8 - 1598 06a8 2E .uleb128 0x2e - 1599 06a9 6F000000 .4byte 0x6f - 1600 06ad 2E .uleb128 0x2e - 1601 06ae 36010000 .4byte 0x136 - 1602 06b2 2E .uleb128 0x2e - 1603 06b3 7A000000 .4byte 0x7a - 1604 06b7 00 .byte 0 - 1605 06b8 2D .uleb128 0x2d - 1606 06b9 01 .byte 0x1 - 1607 06ba 31000000 .4byte .LASF47 - 1608 06be 03 .byte 0x3 - 1609 06bf 28 .byte 0x28 - 1610 06c0 01 .byte 0x1 - 1611 06c1 A5000000 .4byte 0xa5 - 1612 06c5 01 .byte 0x1 - 1613 06c6 DF060000 .4byte 0x6df - 1614 06ca 2E .uleb128 0x2e - 1615 06cb 6F000000 .4byte 0x6f - 1616 06cf 2E .uleb128 0x2e - 1617 06d0 7A000000 .4byte 0x7a - 1618 06d4 2E .uleb128 0x2e - 1619 06d5 6F000000 .4byte 0x6f - 1620 06d9 2E .uleb128 0x2e - 1621 06da 6F000000 .4byte 0x6f - 1622 06de 00 .byte 0 - 1623 06df 32 .uleb128 0x32 - 1624 06e0 01 .byte 0x1 - 1625 06e1 5A020000 .4byte .LASF49 - 1626 06e5 01 .byte 0x1 - 1627 06e6 C7000000 .4byte 0xc7 - 1628 06ea 01 .byte 0x1 - 1629 06eb 01 .byte 0x1 - 1630 06ec 00070000 .4byte 0x700 - 1631 06f0 2E .uleb128 0x2e - 1632 06f1 C7000000 .4byte 0xc7 - 1633 06f5 2E .uleb128 0x2e - 1634 06f6 00070000 .4byte 0x700 - 1635 06fa 2E .uleb128 0x2e - 1636 06fb C0000000 .4byte 0xc0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 43 - - - 1637 06ff 00 .byte 0 - 1638 0700 0C .uleb128 0xc - 1639 0701 04 .byte 0x4 - 1640 0702 06070000 .4byte 0x706 - 1641 0706 33 .uleb128 0x33 - 1642 0707 31 .uleb128 0x31 - 1643 0708 01 .byte 0x1 - 1644 0709 BE010000 .4byte .LASF51 - 1645 070d 04 .byte 0x4 - 1646 070e 7E .byte 0x7e - 1647 070f 01 .byte 0x1 - 1648 0710 6F000000 .4byte 0x6f - 1649 0714 01 .byte 0x1 - 1650 0715 34 .uleb128 0x34 - 1651 0716 01 .byte 0x1 - 1652 0717 F0010000 .4byte .LASF57 - 1653 071b 04 .byte 0x4 - 1654 071c 7F .byte 0x7f - 1655 071d 01 .byte 0x1 - 1656 071e 01 .byte 0x1 - 1657 071f 2E .uleb128 0x2e - 1658 0720 6F000000 .4byte 0x6f - 1659 0724 00 .byte 0 - 1660 0725 00 .byte 0 - 1661 .section .debug_abbrev,"",%progbits - 1662 .Ldebug_abbrev0: - 1663 0000 01 .uleb128 0x1 - 1664 0001 11 .uleb128 0x11 - 1665 0002 01 .byte 0x1 - 1666 0003 25 .uleb128 0x25 - 1667 0004 0E .uleb128 0xe - 1668 0005 13 .uleb128 0x13 - 1669 0006 0B .uleb128 0xb - 1670 0007 03 .uleb128 0x3 - 1671 0008 0E .uleb128 0xe - 1672 0009 1B .uleb128 0x1b - 1673 000a 0E .uleb128 0xe - 1674 000b 55 .uleb128 0x55 - 1675 000c 06 .uleb128 0x6 - 1676 000d 11 .uleb128 0x11 - 1677 000e 01 .uleb128 0x1 - 1678 000f 52 .uleb128 0x52 - 1679 0010 01 .uleb128 0x1 - 1680 0011 10 .uleb128 0x10 - 1681 0012 06 .uleb128 0x6 - 1682 0013 00 .byte 0 - 1683 0014 00 .byte 0 - 1684 0015 02 .uleb128 0x2 - 1685 0016 24 .uleb128 0x24 - 1686 0017 00 .byte 0 - 1687 0018 0B .uleb128 0xb - 1688 0019 0B .uleb128 0xb - 1689 001a 3E .uleb128 0x3e - 1690 001b 0B .uleb128 0xb - 1691 001c 03 .uleb128 0x3 - 1692 001d 0E .uleb128 0xe - 1693 001e 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 44 - - - 1694 001f 00 .byte 0 - 1695 0020 03 .uleb128 0x3 - 1696 0021 24 .uleb128 0x24 - 1697 0022 00 .byte 0 - 1698 0023 0B .uleb128 0xb - 1699 0024 0B .uleb128 0xb - 1700 0025 3E .uleb128 0x3e - 1701 0026 0B .uleb128 0xb - 1702 0027 03 .uleb128 0x3 - 1703 0028 08 .uleb128 0x8 - 1704 0029 00 .byte 0 - 1705 002a 00 .byte 0 - 1706 002b 04 .uleb128 0x4 - 1707 002c 16 .uleb128 0x16 - 1708 002d 00 .byte 0 - 1709 002e 03 .uleb128 0x3 - 1710 002f 0E .uleb128 0xe - 1711 0030 3A .uleb128 0x3a - 1712 0031 0B .uleb128 0xb - 1713 0032 3B .uleb128 0x3b - 1714 0033 0B .uleb128 0xb - 1715 0034 49 .uleb128 0x49 - 1716 0035 13 .uleb128 0x13 - 1717 0036 00 .byte 0 - 1718 0037 00 .byte 0 - 1719 0038 05 .uleb128 0x5 - 1720 0039 35 .uleb128 0x35 - 1721 003a 00 .byte 0 - 1722 003b 49 .uleb128 0x49 - 1723 003c 13 .uleb128 0x13 - 1724 003d 00 .byte 0 - 1725 003e 00 .byte 0 - 1726 003f 06 .uleb128 0x6 - 1727 0040 0F .uleb128 0xf - 1728 0041 00 .byte 0 - 1729 0042 0B .uleb128 0xb - 1730 0043 0B .uleb128 0xb - 1731 0044 00 .byte 0 - 1732 0045 00 .byte 0 - 1733 0046 07 .uleb128 0x7 - 1734 0047 2E .uleb128 0x2e - 1735 0048 01 .byte 0x1 - 1736 0049 03 .uleb128 0x3 - 1737 004a 0E .uleb128 0xe - 1738 004b 3A .uleb128 0x3a - 1739 004c 0B .uleb128 0xb - 1740 004d 3B .uleb128 0x3b - 1741 004e 0B .uleb128 0xb - 1742 004f 27 .uleb128 0x27 - 1743 0050 0C .uleb128 0xc - 1744 0051 49 .uleb128 0x49 - 1745 0052 13 .uleb128 0x13 - 1746 0053 20 .uleb128 0x20 - 1747 0054 0B .uleb128 0xb - 1748 0055 01 .uleb128 0x1 - 1749 0056 13 .uleb128 0x13 - 1750 0057 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 45 - - - 1751 0058 00 .byte 0 - 1752 0059 08 .uleb128 0x8 - 1753 005a 34 .uleb128 0x34 - 1754 005b 00 .byte 0 - 1755 005c 03 .uleb128 0x3 - 1756 005d 0E .uleb128 0xe - 1757 005e 3A .uleb128 0x3a - 1758 005f 0B .uleb128 0xb - 1759 0060 3B .uleb128 0x3b - 1760 0061 0B .uleb128 0xb - 1761 0062 49 .uleb128 0x49 - 1762 0063 13 .uleb128 0x13 - 1763 0064 00 .byte 0 - 1764 0065 00 .byte 0 - 1765 0066 09 .uleb128 0x9 - 1766 0067 2E .uleb128 0x2e - 1767 0068 01 .byte 0x1 - 1768 0069 3F .uleb128 0x3f - 1769 006a 0C .uleb128 0xc - 1770 006b 03 .uleb128 0x3 - 1771 006c 0E .uleb128 0xe - 1772 006d 3A .uleb128 0x3a - 1773 006e 0B .uleb128 0xb - 1774 006f 3B .uleb128 0x3b - 1775 0070 05 .uleb128 0x5 - 1776 0071 27 .uleb128 0x27 - 1777 0072 0C .uleb128 0xc - 1778 0073 49 .uleb128 0x49 - 1779 0074 13 .uleb128 0x13 - 1780 0075 20 .uleb128 0x20 - 1781 0076 0B .uleb128 0xb - 1782 0077 01 .uleb128 0x1 - 1783 0078 13 .uleb128 0x13 - 1784 0079 00 .byte 0 - 1785 007a 00 .byte 0 - 1786 007b 0A .uleb128 0xa - 1787 007c 05 .uleb128 0x5 - 1788 007d 00 .byte 0 - 1789 007e 03 .uleb128 0x3 - 1790 007f 0E .uleb128 0xe - 1791 0080 3A .uleb128 0x3a - 1792 0081 0B .uleb128 0xb - 1793 0082 3B .uleb128 0x3b - 1794 0083 05 .uleb128 0x5 - 1795 0084 49 .uleb128 0x49 - 1796 0085 13 .uleb128 0x13 - 1797 0086 00 .byte 0 - 1798 0087 00 .byte 0 - 1799 0088 0B .uleb128 0xb - 1800 0089 34 .uleb128 0x34 - 1801 008a 00 .byte 0 - 1802 008b 03 .uleb128 0x3 - 1803 008c 0E .uleb128 0xe - 1804 008d 3A .uleb128 0x3a - 1805 008e 0B .uleb128 0xb - 1806 008f 3B .uleb128 0x3b - 1807 0090 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 46 - - - 1808 0091 49 .uleb128 0x49 - 1809 0092 13 .uleb128 0x13 - 1810 0093 00 .byte 0 - 1811 0094 00 .byte 0 - 1812 0095 0C .uleb128 0xc - 1813 0096 0F .uleb128 0xf - 1814 0097 00 .byte 0 - 1815 0098 0B .uleb128 0xb - 1816 0099 0B .uleb128 0xb - 1817 009a 49 .uleb128 0x49 - 1818 009b 13 .uleb128 0x13 - 1819 009c 00 .byte 0 - 1820 009d 00 .byte 0 - 1821 009e 0D .uleb128 0xd - 1822 009f 26 .uleb128 0x26 - 1823 00a0 00 .byte 0 - 1824 00a1 49 .uleb128 0x49 - 1825 00a2 13 .uleb128 0x13 - 1826 00a3 00 .byte 0 - 1827 00a4 00 .byte 0 - 1828 00a5 0E .uleb128 0xe - 1829 00a6 2E .uleb128 0x2e - 1830 00a7 01 .byte 0x1 - 1831 00a8 31 .uleb128 0x31 - 1832 00a9 13 .uleb128 0x13 - 1833 00aa 11 .uleb128 0x11 - 1834 00ab 01 .uleb128 0x1 - 1835 00ac 12 .uleb128 0x12 - 1836 00ad 01 .uleb128 0x1 - 1837 00ae 40 .uleb128 0x40 - 1838 00af 06 .uleb128 0x6 - 1839 00b0 9742 .uleb128 0x2117 - 1840 00b2 0C .uleb128 0xc - 1841 00b3 01 .uleb128 0x1 - 1842 00b4 13 .uleb128 0x13 - 1843 00b5 00 .byte 0 - 1844 00b6 00 .byte 0 - 1845 00b7 0F .uleb128 0xf - 1846 00b8 34 .uleb128 0x34 - 1847 00b9 00 .byte 0 - 1848 00ba 31 .uleb128 0x31 - 1849 00bb 13 .uleb128 0x13 - 1850 00bc 02 .uleb128 0x2 - 1851 00bd 0A .uleb128 0xa - 1852 00be 00 .byte 0 - 1853 00bf 00 .byte 0 - 1854 00c0 10 .uleb128 0x10 - 1855 00c1 898201 .uleb128 0x4109 - 1856 00c4 01 .byte 0x1 - 1857 00c5 11 .uleb128 0x11 - 1858 00c6 01 .uleb128 0x1 - 1859 00c7 31 .uleb128 0x31 - 1860 00c8 13 .uleb128 0x13 - 1861 00c9 01 .uleb128 0x1 - 1862 00ca 13 .uleb128 0x13 - 1863 00cb 00 .byte 0 - 1864 00cc 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 47 - - - 1865 00cd 11 .uleb128 0x11 - 1866 00ce 8A8201 .uleb128 0x410a - 1867 00d1 00 .byte 0 - 1868 00d2 02 .uleb128 0x2 - 1869 00d3 0A .uleb128 0xa - 1870 00d4 9142 .uleb128 0x2111 - 1871 00d6 0A .uleb128 0xa - 1872 00d7 00 .byte 0 - 1873 00d8 00 .byte 0 - 1874 00d9 12 .uleb128 0x12 - 1875 00da 898201 .uleb128 0x4109 - 1876 00dd 00 .byte 0 - 1877 00de 11 .uleb128 0x11 - 1878 00df 01 .uleb128 0x1 - 1879 00e0 31 .uleb128 0x31 - 1880 00e1 13 .uleb128 0x13 - 1881 00e2 00 .byte 0 - 1882 00e3 00 .byte 0 - 1883 00e4 13 .uleb128 0x13 - 1884 00e5 2E .uleb128 0x2e - 1885 00e6 01 .byte 0x1 - 1886 00e7 3F .uleb128 0x3f - 1887 00e8 0C .uleb128 0xc - 1888 00e9 03 .uleb128 0x3 - 1889 00ea 0E .uleb128 0xe - 1890 00eb 3A .uleb128 0x3a - 1891 00ec 0B .uleb128 0xb - 1892 00ed 3B .uleb128 0x3b - 1893 00ee 0B .uleb128 0xb - 1894 00ef 27 .uleb128 0x27 - 1895 00f0 0C .uleb128 0xc - 1896 00f1 11 .uleb128 0x11 - 1897 00f2 01 .uleb128 0x1 - 1898 00f3 12 .uleb128 0x12 - 1899 00f4 01 .uleb128 0x1 - 1900 00f5 40 .uleb128 0x40 - 1901 00f6 0A .uleb128 0xa - 1902 00f7 9742 .uleb128 0x2117 - 1903 00f9 0C .uleb128 0xc - 1904 00fa 01 .uleb128 0x1 - 1905 00fb 13 .uleb128 0x13 - 1906 00fc 00 .byte 0 - 1907 00fd 00 .byte 0 - 1908 00fe 14 .uleb128 0x14 - 1909 00ff 898201 .uleb128 0x4109 - 1910 0102 01 .byte 0x1 - 1911 0103 11 .uleb128 0x11 - 1912 0104 01 .uleb128 0x1 - 1913 0105 9542 .uleb128 0x2115 - 1914 0107 0C .uleb128 0xc - 1915 0108 31 .uleb128 0x31 - 1916 0109 13 .uleb128 0x13 - 1917 010a 00 .byte 0 - 1918 010b 00 .byte 0 - 1919 010c 15 .uleb128 0x15 - 1920 010d 2E .uleb128 0x2e - 1921 010e 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 48 - - - 1922 010f 3F .uleb128 0x3f - 1923 0110 0C .uleb128 0xc - 1924 0111 03 .uleb128 0x3 - 1925 0112 0E .uleb128 0xe - 1926 0113 3A .uleb128 0x3a - 1927 0114 0B .uleb128 0xb - 1928 0115 3B .uleb128 0x3b - 1929 0116 0B .uleb128 0xb - 1930 0117 27 .uleb128 0x27 - 1931 0118 0C .uleb128 0xc - 1932 0119 11 .uleb128 0x11 - 1933 011a 01 .uleb128 0x1 - 1934 011b 12 .uleb128 0x12 - 1935 011c 01 .uleb128 0x1 - 1936 011d 40 .uleb128 0x40 - 1937 011e 0A .uleb128 0xa - 1938 011f 9742 .uleb128 0x2117 - 1939 0121 0C .uleb128 0xc - 1940 0122 00 .byte 0 - 1941 0123 00 .byte 0 - 1942 0124 16 .uleb128 0x16 - 1943 0125 2E .uleb128 0x2e - 1944 0126 01 .byte 0x1 - 1945 0127 3F .uleb128 0x3f - 1946 0128 0C .uleb128 0xc - 1947 0129 03 .uleb128 0x3 - 1948 012a 0E .uleb128 0xe - 1949 012b 3A .uleb128 0x3a - 1950 012c 0B .uleb128 0xb - 1951 012d 3B .uleb128 0x3b - 1952 012e 0B .uleb128 0xb - 1953 012f 27 .uleb128 0x27 - 1954 0130 0C .uleb128 0xc - 1955 0131 49 .uleb128 0x49 - 1956 0132 13 .uleb128 0x13 - 1957 0133 11 .uleb128 0x11 - 1958 0134 01 .uleb128 0x1 - 1959 0135 12 .uleb128 0x12 - 1960 0136 01 .uleb128 0x1 - 1961 0137 40 .uleb128 0x40 - 1962 0138 06 .uleb128 0x6 - 1963 0139 9742 .uleb128 0x2117 - 1964 013b 0C .uleb128 0xc - 1965 013c 01 .uleb128 0x1 - 1966 013d 13 .uleb128 0x13 - 1967 013e 00 .byte 0 - 1968 013f 00 .byte 0 - 1969 0140 17 .uleb128 0x17 - 1970 0141 34 .uleb128 0x34 - 1971 0142 00 .byte 0 - 1972 0143 03 .uleb128 0x3 - 1973 0144 0E .uleb128 0xe - 1974 0145 3A .uleb128 0x3a - 1975 0146 0B .uleb128 0xb - 1976 0147 3B .uleb128 0x3b - 1977 0148 0B .uleb128 0xb - 1978 0149 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 49 - - - 1979 014a 13 .uleb128 0x13 - 1980 014b 02 .uleb128 0x2 - 1981 014c 0A .uleb128 0xa - 1982 014d 00 .byte 0 - 1983 014e 00 .byte 0 - 1984 014f 18 .uleb128 0x18 - 1985 0150 1D .uleb128 0x1d - 1986 0151 01 .byte 0x1 - 1987 0152 31 .uleb128 0x31 - 1988 0153 13 .uleb128 0x13 - 1989 0154 52 .uleb128 0x52 - 1990 0155 01 .uleb128 0x1 - 1991 0156 55 .uleb128 0x55 - 1992 0157 06 .uleb128 0x6 - 1993 0158 58 .uleb128 0x58 - 1994 0159 0B .uleb128 0xb - 1995 015a 59 .uleb128 0x59 - 1996 015b 0B .uleb128 0xb - 1997 015c 01 .uleb128 0x1 - 1998 015d 13 .uleb128 0x13 - 1999 015e 00 .byte 0 - 2000 015f 00 .byte 0 - 2001 0160 19 .uleb128 0x19 - 2002 0161 0B .uleb128 0xb - 2003 0162 01 .byte 0x1 - 2004 0163 55 .uleb128 0x55 - 2005 0164 06 .uleb128 0x6 - 2006 0165 00 .byte 0 - 2007 0166 00 .byte 0 - 2008 0167 1A .uleb128 0x1a - 2009 0168 34 .uleb128 0x34 - 2010 0169 00 .byte 0 - 2011 016a 31 .uleb128 0x31 - 2012 016b 13 .uleb128 0x13 - 2013 016c 02 .uleb128 0x2 - 2014 016d 06 .uleb128 0x6 - 2015 016e 00 .byte 0 - 2016 016f 00 .byte 0 - 2017 0170 1B .uleb128 0x1b - 2018 0171 1D .uleb128 0x1d - 2019 0172 01 .byte 0x1 - 2020 0173 31 .uleb128 0x31 - 2021 0174 13 .uleb128 0x13 - 2022 0175 11 .uleb128 0x11 - 2023 0176 01 .uleb128 0x1 - 2024 0177 12 .uleb128 0x12 - 2025 0178 01 .uleb128 0x1 - 2026 0179 58 .uleb128 0x58 - 2027 017a 0B .uleb128 0xb - 2028 017b 59 .uleb128 0x59 - 2029 017c 0B .uleb128 0xb - 2030 017d 01 .uleb128 0x1 - 2031 017e 13 .uleb128 0x13 - 2032 017f 00 .byte 0 - 2033 0180 00 .byte 0 - 2034 0181 1C .uleb128 0x1c - 2035 0182 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 50 - - - 2036 0183 01 .byte 0x1 - 2037 0184 11 .uleb128 0x11 - 2038 0185 01 .uleb128 0x1 - 2039 0186 12 .uleb128 0x12 - 2040 0187 01 .uleb128 0x1 - 2041 0188 00 .byte 0 - 2042 0189 00 .byte 0 - 2043 018a 1D .uleb128 0x1d - 2044 018b 898201 .uleb128 0x4109 - 2045 018e 00 .byte 0 - 2046 018f 11 .uleb128 0x11 - 2047 0190 01 .uleb128 0x1 - 2048 0191 9542 .uleb128 0x2115 - 2049 0193 0C .uleb128 0xc - 2050 0194 31 .uleb128 0x31 - 2051 0195 13 .uleb128 0x13 - 2052 0196 00 .byte 0 - 2053 0197 00 .byte 0 - 2054 0198 1E .uleb128 0x1e - 2055 0199 05 .uleb128 0x5 - 2056 019a 00 .byte 0 - 2057 019b 03 .uleb128 0x3 - 2058 019c 0E .uleb128 0xe - 2059 019d 3A .uleb128 0x3a - 2060 019e 0B .uleb128 0xb - 2061 019f 3B .uleb128 0x3b - 2062 01a0 0B .uleb128 0xb - 2063 01a1 49 .uleb128 0x49 - 2064 01a2 13 .uleb128 0x13 - 2065 01a3 02 .uleb128 0x2 - 2066 01a4 06 .uleb128 0x6 - 2067 01a5 00 .byte 0 - 2068 01a6 00 .byte 0 - 2069 01a7 1F .uleb128 0x1f - 2070 01a8 34 .uleb128 0x34 - 2071 01a9 00 .byte 0 - 2072 01aa 03 .uleb128 0x3 - 2073 01ab 0E .uleb128 0xe - 2074 01ac 3A .uleb128 0x3a - 2075 01ad 0B .uleb128 0xb - 2076 01ae 3B .uleb128 0x3b - 2077 01af 0B .uleb128 0xb - 2078 01b0 49 .uleb128 0x49 - 2079 01b1 13 .uleb128 0x13 - 2080 01b2 02 .uleb128 0x2 - 2081 01b3 06 .uleb128 0x6 - 2082 01b4 00 .byte 0 - 2083 01b5 00 .byte 0 - 2084 01b6 20 .uleb128 0x20 - 2085 01b7 05 .uleb128 0x5 - 2086 01b8 00 .byte 0 - 2087 01b9 31 .uleb128 0x31 - 2088 01ba 13 .uleb128 0x13 - 2089 01bb 02 .uleb128 0x2 - 2090 01bc 06 .uleb128 0x6 - 2091 01bd 00 .byte 0 - 2092 01be 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 51 - - - 2093 01bf 21 .uleb128 0x21 - 2094 01c0 1D .uleb128 0x1d - 2095 01c1 01 .byte 0x1 - 2096 01c2 31 .uleb128 0x31 - 2097 01c3 13 .uleb128 0x13 - 2098 01c4 52 .uleb128 0x52 - 2099 01c5 01 .uleb128 0x1 - 2100 01c6 55 .uleb128 0x55 - 2101 01c7 06 .uleb128 0x6 - 2102 01c8 58 .uleb128 0x58 - 2103 01c9 0B .uleb128 0xb - 2104 01ca 59 .uleb128 0x59 - 2105 01cb 05 .uleb128 0x5 - 2106 01cc 01 .uleb128 0x1 - 2107 01cd 13 .uleb128 0x13 - 2108 01ce 00 .byte 0 - 2109 01cf 00 .byte 0 - 2110 01d0 22 .uleb128 0x22 - 2111 01d1 898201 .uleb128 0x4109 - 2112 01d4 01 .byte 0x1 - 2113 01d5 11 .uleb128 0x11 - 2114 01d6 01 .uleb128 0x1 - 2115 01d7 31 .uleb128 0x31 - 2116 01d8 13 .uleb128 0x13 - 2117 01d9 00 .byte 0 - 2118 01da 00 .byte 0 - 2119 01db 23 .uleb128 0x23 - 2120 01dc 2E .uleb128 0x2e - 2121 01dd 01 .byte 0x1 - 2122 01de 3F .uleb128 0x3f - 2123 01df 0C .uleb128 0xc - 2124 01e0 03 .uleb128 0x3 - 2125 01e1 0E .uleb128 0xe - 2126 01e2 3A .uleb128 0x3a - 2127 01e3 0B .uleb128 0xb - 2128 01e4 3B .uleb128 0x3b - 2129 01e5 05 .uleb128 0x5 - 2130 01e6 27 .uleb128 0x27 - 2131 01e7 0C .uleb128 0xc - 2132 01e8 49 .uleb128 0x49 - 2133 01e9 13 .uleb128 0x13 - 2134 01ea 11 .uleb128 0x11 - 2135 01eb 01 .uleb128 0x1 - 2136 01ec 12 .uleb128 0x12 - 2137 01ed 01 .uleb128 0x1 - 2138 01ee 40 .uleb128 0x40 - 2139 01ef 06 .uleb128 0x6 - 2140 01f0 9742 .uleb128 0x2117 - 2141 01f2 0C .uleb128 0xc - 2142 01f3 01 .uleb128 0x1 - 2143 01f4 13 .uleb128 0x13 - 2144 01f5 00 .byte 0 - 2145 01f6 00 .byte 0 - 2146 01f7 24 .uleb128 0x24 - 2147 01f8 05 .uleb128 0x5 - 2148 01f9 00 .byte 0 - 2149 01fa 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 52 - - - 2150 01fb 0E .uleb128 0xe - 2151 01fc 3A .uleb128 0x3a - 2152 01fd 0B .uleb128 0xb - 2153 01fe 3B .uleb128 0x3b - 2154 01ff 05 .uleb128 0x5 - 2155 0200 49 .uleb128 0x49 - 2156 0201 13 .uleb128 0x13 - 2157 0202 02 .uleb128 0x2 - 2158 0203 06 .uleb128 0x6 - 2159 0204 00 .byte 0 - 2160 0205 00 .byte 0 - 2161 0206 25 .uleb128 0x25 - 2162 0207 34 .uleb128 0x34 - 2163 0208 00 .byte 0 - 2164 0209 03 .uleb128 0x3 - 2165 020a 0E .uleb128 0xe - 2166 020b 3A .uleb128 0x3a - 2167 020c 0B .uleb128 0xb - 2168 020d 3B .uleb128 0x3b - 2169 020e 05 .uleb128 0x5 - 2170 020f 49 .uleb128 0x49 - 2171 0210 13 .uleb128 0x13 - 2172 0211 02 .uleb128 0x2 - 2173 0212 06 .uleb128 0x6 - 2174 0213 00 .byte 0 - 2175 0214 00 .byte 0 - 2176 0215 26 .uleb128 0x26 - 2177 0216 34 .uleb128 0x34 - 2178 0217 00 .byte 0 - 2179 0218 03 .uleb128 0x3 - 2180 0219 08 .uleb128 0x8 - 2181 021a 3A .uleb128 0x3a - 2182 021b 0B .uleb128 0xb - 2183 021c 3B .uleb128 0x3b - 2184 021d 05 .uleb128 0x5 - 2185 021e 49 .uleb128 0x49 - 2186 021f 13 .uleb128 0x13 - 2187 0220 02 .uleb128 0x2 - 2188 0221 06 .uleb128 0x6 - 2189 0222 00 .byte 0 - 2190 0223 00 .byte 0 - 2191 0224 27 .uleb128 0x27 - 2192 0225 34 .uleb128 0x34 - 2193 0226 00 .byte 0 - 2194 0227 03 .uleb128 0x3 - 2195 0228 0E .uleb128 0xe - 2196 0229 3A .uleb128 0x3a - 2197 022a 0B .uleb128 0xb - 2198 022b 3B .uleb128 0x3b - 2199 022c 05 .uleb128 0x5 - 2200 022d 49 .uleb128 0x49 - 2201 022e 13 .uleb128 0x13 - 2202 022f 1C .uleb128 0x1c - 2203 0230 0D .uleb128 0xd - 2204 0231 00 .byte 0 - 2205 0232 00 .byte 0 - 2206 0233 28 .uleb128 0x28 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 53 - - - 2207 0234 2E .uleb128 0x2e - 2208 0235 01 .byte 0x1 - 2209 0236 3F .uleb128 0x3f - 2210 0237 0C .uleb128 0xc - 2211 0238 03 .uleb128 0x3 - 2212 0239 0E .uleb128 0xe - 2213 023a 3A .uleb128 0x3a - 2214 023b 0B .uleb128 0xb - 2215 023c 3B .uleb128 0x3b - 2216 023d 05 .uleb128 0x5 - 2217 023e 27 .uleb128 0x27 - 2218 023f 0C .uleb128 0xc - 2219 0240 11 .uleb128 0x11 - 2220 0241 01 .uleb128 0x1 - 2221 0242 12 .uleb128 0x12 - 2222 0243 01 .uleb128 0x1 - 2223 0244 40 .uleb128 0x40 - 2224 0245 06 .uleb128 0x6 - 2225 0246 9742 .uleb128 0x2117 - 2226 0248 0C .uleb128 0xc - 2227 0249 01 .uleb128 0x1 - 2228 024a 13 .uleb128 0x13 - 2229 024b 00 .byte 0 - 2230 024c 00 .byte 0 - 2231 024d 29 .uleb128 0x29 - 2232 024e 2E .uleb128 0x2e - 2233 024f 00 .byte 0 - 2234 0250 3F .uleb128 0x3f - 2235 0251 0C .uleb128 0xc - 2236 0252 03 .uleb128 0x3 - 2237 0253 0E .uleb128 0xe - 2238 0254 3A .uleb128 0x3a - 2239 0255 0B .uleb128 0xb - 2240 0256 3B .uleb128 0x3b - 2241 0257 05 .uleb128 0x5 - 2242 0258 27 .uleb128 0x27 - 2243 0259 0C .uleb128 0xc - 2244 025a 11 .uleb128 0x11 - 2245 025b 01 .uleb128 0x1 - 2246 025c 12 .uleb128 0x12 - 2247 025d 01 .uleb128 0x1 - 2248 025e 40 .uleb128 0x40 - 2249 025f 0A .uleb128 0xa - 2250 0260 9742 .uleb128 0x2117 - 2251 0262 0C .uleb128 0xc - 2252 0263 00 .byte 0 - 2253 0264 00 .byte 0 - 2254 0265 2A .uleb128 0x2a - 2255 0266 01 .uleb128 0x1 - 2256 0267 01 .byte 0x1 - 2257 0268 49 .uleb128 0x49 - 2258 0269 13 .uleb128 0x13 - 2259 026a 01 .uleb128 0x1 - 2260 026b 13 .uleb128 0x13 - 2261 026c 00 .byte 0 - 2262 026d 00 .byte 0 - 2263 026e 2B .uleb128 0x2b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 54 - - - 2264 026f 21 .uleb128 0x21 - 2265 0270 00 .byte 0 - 2266 0271 49 .uleb128 0x49 - 2267 0272 13 .uleb128 0x13 - 2268 0273 2F .uleb128 0x2f - 2269 0274 0B .uleb128 0xb - 2270 0275 00 .byte 0 - 2271 0276 00 .byte 0 - 2272 0277 2C .uleb128 0x2c - 2273 0278 34 .uleb128 0x34 - 2274 0279 00 .byte 0 - 2275 027a 03 .uleb128 0x3 - 2276 027b 0E .uleb128 0xe - 2277 027c 3A .uleb128 0x3a - 2278 027d 0B .uleb128 0xb - 2279 027e 3B .uleb128 0x3b - 2280 027f 0B .uleb128 0xb - 2281 0280 49 .uleb128 0x49 - 2282 0281 13 .uleb128 0x13 - 2283 0282 3F .uleb128 0x3f - 2284 0283 0C .uleb128 0xc - 2285 0284 02 .uleb128 0x2 - 2286 0285 0A .uleb128 0xa - 2287 0286 00 .byte 0 - 2288 0287 00 .byte 0 - 2289 0288 2D .uleb128 0x2d - 2290 0289 2E .uleb128 0x2e - 2291 028a 01 .byte 0x1 - 2292 028b 3F .uleb128 0x3f - 2293 028c 0C .uleb128 0xc - 2294 028d 03 .uleb128 0x3 - 2295 028e 0E .uleb128 0xe - 2296 028f 3A .uleb128 0x3a - 2297 0290 0B .uleb128 0xb - 2298 0291 3B .uleb128 0x3b - 2299 0292 0B .uleb128 0xb - 2300 0293 27 .uleb128 0x27 - 2301 0294 0C .uleb128 0xc - 2302 0295 49 .uleb128 0x49 - 2303 0296 13 .uleb128 0x13 - 2304 0297 3C .uleb128 0x3c - 2305 0298 0C .uleb128 0xc - 2306 0299 01 .uleb128 0x1 - 2307 029a 13 .uleb128 0x13 - 2308 029b 00 .byte 0 - 2309 029c 00 .byte 0 - 2310 029d 2E .uleb128 0x2e - 2311 029e 05 .uleb128 0x5 - 2312 029f 00 .byte 0 - 2313 02a0 49 .uleb128 0x49 - 2314 02a1 13 .uleb128 0x13 - 2315 02a2 00 .byte 0 - 2316 02a3 00 .byte 0 - 2317 02a4 2F .uleb128 0x2f - 2318 02a5 2E .uleb128 0x2e - 2319 02a6 01 .byte 0x1 - 2320 02a7 3F .uleb128 0x3f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 55 - - - 2321 02a8 0C .uleb128 0xc - 2322 02a9 03 .uleb128 0x3 - 2323 02aa 0E .uleb128 0xe - 2324 02ab 3A .uleb128 0x3a - 2325 02ac 0B .uleb128 0xb - 2326 02ad 3B .uleb128 0x3b - 2327 02ae 0B .uleb128 0xb - 2328 02af 27 .uleb128 0x27 - 2329 02b0 0C .uleb128 0xc - 2330 02b1 3C .uleb128 0x3c - 2331 02b2 0C .uleb128 0xc - 2332 02b3 01 .uleb128 0x1 - 2333 02b4 13 .uleb128 0x13 - 2334 02b5 00 .byte 0 - 2335 02b6 00 .byte 0 - 2336 02b7 30 .uleb128 0x30 - 2337 02b8 2E .uleb128 0x2e - 2338 02b9 00 .byte 0 - 2339 02ba 3F .uleb128 0x3f - 2340 02bb 0C .uleb128 0xc - 2341 02bc 03 .uleb128 0x3 - 2342 02bd 0E .uleb128 0xe - 2343 02be 3A .uleb128 0x3a - 2344 02bf 0B .uleb128 0xb - 2345 02c0 3B .uleb128 0x3b - 2346 02c1 0B .uleb128 0xb - 2347 02c2 27 .uleb128 0x27 - 2348 02c3 0C .uleb128 0xc - 2349 02c4 3C .uleb128 0x3c - 2350 02c5 0C .uleb128 0xc - 2351 02c6 00 .byte 0 - 2352 02c7 00 .byte 0 - 2353 02c8 31 .uleb128 0x31 - 2354 02c9 2E .uleb128 0x2e - 2355 02ca 00 .byte 0 - 2356 02cb 3F .uleb128 0x3f - 2357 02cc 0C .uleb128 0xc - 2358 02cd 03 .uleb128 0x3 - 2359 02ce 0E .uleb128 0xe - 2360 02cf 3A .uleb128 0x3a - 2361 02d0 0B .uleb128 0xb - 2362 02d1 3B .uleb128 0x3b - 2363 02d2 0B .uleb128 0xb - 2364 02d3 27 .uleb128 0x27 - 2365 02d4 0C .uleb128 0xc - 2366 02d5 49 .uleb128 0x49 - 2367 02d6 13 .uleb128 0x13 - 2368 02d7 3C .uleb128 0x3c - 2369 02d8 0C .uleb128 0xc - 2370 02d9 00 .byte 0 - 2371 02da 00 .byte 0 - 2372 02db 32 .uleb128 0x32 - 2373 02dc 2E .uleb128 0x2e - 2374 02dd 01 .byte 0x1 - 2375 02de 3F .uleb128 0x3f - 2376 02df 0C .uleb128 0xc - 2377 02e0 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 56 - - - 2378 02e1 0E .uleb128 0xe - 2379 02e2 27 .uleb128 0x27 - 2380 02e3 0C .uleb128 0xc - 2381 02e4 49 .uleb128 0x49 - 2382 02e5 13 .uleb128 0x13 - 2383 02e6 34 .uleb128 0x34 - 2384 02e7 0C .uleb128 0xc - 2385 02e8 3C .uleb128 0x3c - 2386 02e9 0C .uleb128 0xc - 2387 02ea 01 .uleb128 0x1 - 2388 02eb 13 .uleb128 0x13 - 2389 02ec 00 .byte 0 - 2390 02ed 00 .byte 0 - 2391 02ee 33 .uleb128 0x33 - 2392 02ef 26 .uleb128 0x26 - 2393 02f0 00 .byte 0 - 2394 02f1 00 .byte 0 - 2395 02f2 00 .byte 0 - 2396 02f3 34 .uleb128 0x34 - 2397 02f4 2E .uleb128 0x2e - 2398 02f5 01 .byte 0x1 - 2399 02f6 3F .uleb128 0x3f - 2400 02f7 0C .uleb128 0xc - 2401 02f8 03 .uleb128 0x3 - 2402 02f9 0E .uleb128 0xe - 2403 02fa 3A .uleb128 0x3a - 2404 02fb 0B .uleb128 0xb - 2405 02fc 3B .uleb128 0x3b - 2406 02fd 0B .uleb128 0xb - 2407 02fe 27 .uleb128 0x27 - 2408 02ff 0C .uleb128 0xc - 2409 0300 3C .uleb128 0x3c - 2410 0301 0C .uleb128 0xc - 2411 0302 00 .byte 0 - 2412 0303 00 .byte 0 - 2413 0304 00 .byte 0 - 2414 .section .debug_loc,"",%progbits - 2415 .Ldebug_loc0: - 2416 .LLST0: - 2417 0000 00000000 .4byte .LFB13 - 2418 0004 04000000 .4byte .LCFI0 - 2419 0008 0200 .2byte 0x2 - 2420 000a 7D .byte 0x7d - 2421 000b 00 .sleb128 0 - 2422 000c 04000000 .4byte .LCFI0 - 2423 0010 54000000 .4byte .LFE13 - 2424 0014 0200 .2byte 0x2 - 2425 0016 7D .byte 0x7d - 2426 0017 08 .sleb128 8 - 2427 0018 00000000 .4byte 0 - 2428 001c 00000000 .4byte 0 - 2429 .LLST1: - 2430 0020 00000000 .4byte .LFB3 - 2431 0024 02000000 .4byte .LCFI1 - 2432 0028 0200 .2byte 0x2 - 2433 002a 7D .byte 0x7d - 2434 002b 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 57 - - - 2435 002c 02000000 .4byte .LCFI1 - 2436 0030 28000000 .4byte .LFE3 - 2437 0034 0200 .2byte 0x2 - 2438 0036 7D .byte 0x7d - 2439 0037 08 .sleb128 8 - 2440 0038 00000000 .4byte 0 - 2441 003c 00000000 .4byte 0 - 2442 .LLST2: - 2443 0040 06000000 .4byte .LVL6 - 2444 0044 10000000 .4byte .LVL8 - 2445 0048 0300 .2byte 0x3 - 2446 004a 09 .byte 0x9 - 2447 004b FF .byte 0xff - 2448 004c 9F .byte 0x9f - 2449 004d 10000000 .4byte .LVL8 - 2450 0051 15000000 .4byte .LVL9-1 - 2451 0055 0100 .2byte 0x1 - 2452 0057 50 .byte 0x50 - 2453 0058 00000000 .4byte 0 - 2454 005c 00000000 .4byte 0 - 2455 .LLST3: - 2456 0060 16000000 .4byte .LVL9 - 2457 0064 24000000 .4byte .LVL11 - 2458 0068 0300 .2byte 0x3 - 2459 006a 09 .byte 0x9 - 2460 006b FF .byte 0xff - 2461 006c 9F .byte 0x9f - 2462 006d 00000000 .4byte 0 - 2463 0071 00000000 .4byte 0 - 2464 .LLST4: - 2465 0075 00000000 .4byte .LFB4 - 2466 0079 02000000 .4byte .LCFI2 - 2467 007d 0200 .2byte 0x2 - 2468 007f 7D .byte 0x7d - 2469 0080 00 .sleb128 0 - 2470 0081 02000000 .4byte .LCFI2 - 2471 0085 2C000000 .4byte .LFE4 - 2472 0089 0200 .2byte 0x2 - 2473 008b 7D .byte 0x7d - 2474 008c 10 .sleb128 16 - 2475 008d 00000000 .4byte 0 - 2476 0091 00000000 .4byte 0 - 2477 .LLST5: - 2478 0095 00000000 .4byte .LVL13 - 2479 0099 07000000 .4byte .LVL14-1 - 2480 009d 0100 .2byte 0x1 - 2481 009f 50 .byte 0x50 - 2482 00a0 07000000 .4byte .LVL14-1 - 2483 00a4 2C000000 .4byte .LFE4 - 2484 00a8 0100 .2byte 0x1 - 2485 00aa 54 .byte 0x54 - 2486 00ab 00000000 .4byte 0 - 2487 00af 00000000 .4byte 0 - 2488 .LLST6: - 2489 00b3 00000000 .4byte .LVL13 - 2490 00b7 24000000 .4byte .LVL17 - 2491 00bb 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 58 - - - 2492 00bd 30 .byte 0x30 - 2493 00be 9F .byte 0x9f - 2494 00bf 24000000 .4byte .LVL17 - 2495 00c3 2C000000 .4byte .LFE4 - 2496 00c7 0100 .2byte 0x1 - 2497 00c9 50 .byte 0x50 - 2498 00ca 00000000 .4byte 0 - 2499 00ce 00000000 .4byte 0 - 2500 .LLST7: - 2501 00d2 00000000 .4byte .LFB7 - 2502 00d6 02000000 .4byte .LCFI3 - 2503 00da 0200 .2byte 0x2 - 2504 00dc 7D .byte 0x7d - 2505 00dd 00 .sleb128 0 - 2506 00de 02000000 .4byte .LCFI3 - 2507 00e2 A0000000 .4byte .LFE7 - 2508 00e6 0200 .2byte 0x2 - 2509 00e8 7D .byte 0x7d - 2510 00e9 18 .sleb128 24 - 2511 00ea 00000000 .4byte 0 - 2512 00ee 00000000 .4byte 0 - 2513 .LLST8: - 2514 00f2 00000000 .4byte .LVL18 - 2515 00f6 0D000000 .4byte .LVL19-1 - 2516 00fa 0100 .2byte 0x1 - 2517 00fc 50 .byte 0x50 - 2518 00fd 0D000000 .4byte .LVL19-1 - 2519 0101 A0000000 .4byte .LFE7 - 2520 0105 0400 .2byte 0x4 - 2521 0107 F3 .byte 0xf3 - 2522 0108 01 .uleb128 0x1 - 2523 0109 50 .byte 0x50 - 2524 010a 9F .byte 0x9f - 2525 010b 00000000 .4byte 0 - 2526 010f 00000000 .4byte 0 - 2527 .LLST9: - 2528 0113 00000000 .4byte .LVL18 - 2529 0117 0D000000 .4byte .LVL19-1 - 2530 011b 0100 .2byte 0x1 - 2531 011d 51 .byte 0x51 - 2532 011e 0D000000 .4byte .LVL19-1 - 2533 0122 A0000000 .4byte .LFE7 - 2534 0126 0400 .2byte 0x4 - 2535 0128 F3 .byte 0xf3 - 2536 0129 01 .uleb128 0x1 - 2537 012a 51 .byte 0x51 - 2538 012b 9F .byte 0x9f - 2539 012c 00000000 .4byte 0 - 2540 0130 00000000 .4byte 0 - 2541 .LLST10: - 2542 0134 00000000 .4byte .LVL18 - 2543 0138 0D000000 .4byte .LVL19-1 - 2544 013c 0100 .2byte 0x1 - 2545 013e 52 .byte 0x52 - 2546 013f 0D000000 .4byte .LVL19-1 - 2547 0143 A0000000 .4byte .LFE7 - 2548 0147 0100 .2byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 59 - - - 2549 0149 57 .byte 0x57 - 2550 014a 00000000 .4byte 0 - 2551 014e 00000000 .4byte 0 - 2552 .LLST11: - 2553 0152 00000000 .4byte .LVL18 - 2554 0156 0D000000 .4byte .LVL19-1 - 2555 015a 0100 .2byte 0x1 - 2556 015c 53 .byte 0x53 - 2557 015d 0D000000 .4byte .LVL19-1 - 2558 0161 A0000000 .4byte .LFE7 - 2559 0165 0400 .2byte 0x4 - 2560 0167 F3 .byte 0xf3 - 2561 0168 01 .uleb128 0x1 - 2562 0169 53 .byte 0x53 - 2563 016a 9F .byte 0x9f - 2564 016b 00000000 .4byte 0 - 2565 016f 00000000 .4byte 0 - 2566 .LLST12: - 2567 0173 50000000 .4byte .LVL29 - 2568 0177 52000000 .4byte .LVL30 - 2569 017b 0100 .2byte 0x1 - 2570 017d 54 .byte 0x54 - 2571 017e 00000000 .4byte 0 - 2572 0182 00000000 .4byte 0 - 2573 .LLST13: - 2574 0186 10000000 .4byte .LVL20 - 2575 018a 1E000000 .4byte .LVL22 - 2576 018e 0100 .2byte 0x1 - 2577 0190 54 .byte 0x54 - 2578 0191 00000000 .4byte 0 - 2579 0195 00000000 .4byte 0 - 2580 .LLST14: - 2581 0199 10000000 .4byte .LVL20 - 2582 019d 4E000000 .4byte .LVL28 - 2583 01a1 0100 .2byte 0x1 - 2584 01a3 57 .byte 0x57 - 2585 01a4 52000000 .4byte .LVL30 - 2586 01a8 94000000 .4byte .LVL36 - 2587 01ac 0100 .2byte 0x1 - 2588 01ae 57 .byte 0x57 - 2589 01af 00000000 .4byte 0 - 2590 01b3 00000000 .4byte 0 - 2591 .LLST15: - 2592 01b7 10000000 .4byte .LVL20 - 2593 01bb 4E000000 .4byte .LVL28 - 2594 01bf 0100 .2byte 0x1 - 2595 01c1 56 .byte 0x56 - 2596 01c2 52000000 .4byte .LVL30 - 2597 01c6 94000000 .4byte .LVL36 - 2598 01ca 0100 .2byte 0x1 - 2599 01cc 56 .byte 0x56 - 2600 01cd 00000000 .4byte 0 - 2601 01d1 00000000 .4byte 0 - 2602 .LLST16: - 2603 01d5 10000000 .4byte .LVL20 - 2604 01d9 4E000000 .4byte .LVL28 - 2605 01dd 0100 .2byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 60 - - - 2606 01df 55 .byte 0x55 - 2607 01e0 52000000 .4byte .LVL30 - 2608 01e4 94000000 .4byte .LVL36 - 2609 01e8 0100 .2byte 0x1 - 2610 01ea 55 .byte 0x55 - 2611 01eb 00000000 .4byte 0 - 2612 01ef 00000000 .4byte 0 - 2613 .LLST17: - 2614 01f3 1E000000 .4byte .LVL22 - 2615 01f7 20000000 .4byte .LVL23 - 2616 01fb 0100 .2byte 0x1 - 2617 01fd 50 .byte 0x50 - 2618 01fe 20000000 .4byte .LVL23 - 2619 0202 36000000 .4byte .LVL25 - 2620 0206 0100 .2byte 0x1 - 2621 0208 54 .byte 0x54 - 2622 0209 48000000 .4byte .LVL26 - 2623 020d 4E000000 .4byte .LVL28 - 2624 0211 0100 .2byte 0x1 - 2625 0213 54 .byte 0x54 - 2626 0214 52000000 .4byte .LVL30 - 2627 0218 64000000 .4byte .LVL32 - 2628 021c 0200 .2byte 0x2 - 2629 021e 30 .byte 0x30 - 2630 021f 9F .byte 0x9f - 2631 0220 64000000 .4byte .LVL32 - 2632 0224 66000000 .4byte .LVL33 - 2633 0228 0100 .2byte 0x1 - 2634 022a 50 .byte 0x50 - 2635 022b 66000000 .4byte .LVL33 - 2636 022f 7C000000 .4byte .LVL35 - 2637 0233 0100 .2byte 0x1 - 2638 0235 54 .byte 0x54 - 2639 0236 00000000 .4byte 0 - 2640 023a 00000000 .4byte 0 - 2641 .LLST18: - 2642 023e 00000000 .4byte .LFB6 - 2643 0242 04000000 .4byte .LCFI4 - 2644 0246 0200 .2byte 0x2 - 2645 0248 7D .byte 0x7d - 2646 0249 00 .sleb128 0 - 2647 024a 04000000 .4byte .LCFI4 - 2648 024e 48000000 .4byte .LFE6 - 2649 0252 0200 .2byte 0x2 - 2650 0254 7D .byte 0x7d - 2651 0255 10 .sleb128 16 - 2652 0256 00000000 .4byte 0 - 2653 025a 00000000 .4byte 0 - 2654 .LLST19: - 2655 025e 00000000 .4byte .LVL37 - 2656 0262 3D000000 .4byte .LVL41-1 - 2657 0266 0100 .2byte 0x1 - 2658 0268 50 .byte 0x50 - 2659 0269 3D000000 .4byte .LVL41-1 - 2660 026d 3E000000 .4byte .LVL41 - 2661 0271 0400 .2byte 0x4 - 2662 0273 F3 .byte 0xf3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 61 - - - 2663 0274 01 .uleb128 0x1 - 2664 0275 50 .byte 0x50 - 2665 0276 9F .byte 0x9f - 2666 0277 3E000000 .4byte .LVL41 - 2667 027b 42000000 .4byte .LVL42 - 2668 027f 0100 .2byte 0x1 - 2669 0281 50 .byte 0x50 - 2670 0282 42000000 .4byte .LVL42 - 2671 0286 48000000 .4byte .LFE6 - 2672 028a 0400 .2byte 0x4 - 2673 028c F3 .byte 0xf3 - 2674 028d 01 .uleb128 0x1 - 2675 028e 50 .byte 0x50 - 2676 028f 9F .byte 0x9f - 2677 0290 00000000 .4byte 0 - 2678 0294 00000000 .4byte 0 - 2679 .LLST20: - 2680 0298 00000000 .4byte .LVL37 - 2681 029c 3D000000 .4byte .LVL41-1 - 2682 02a0 0100 .2byte 0x1 - 2683 02a2 51 .byte 0x51 - 2684 02a3 3D000000 .4byte .LVL41-1 - 2685 02a7 3E000000 .4byte .LVL41 - 2686 02ab 0400 .2byte 0x4 - 2687 02ad F3 .byte 0xf3 - 2688 02ae 01 .uleb128 0x1 - 2689 02af 51 .byte 0x51 - 2690 02b0 9F .byte 0x9f - 2691 02b1 3E000000 .4byte .LVL41 - 2692 02b5 48000000 .4byte .LFE6 - 2693 02b9 0100 .2byte 0x1 - 2694 02bb 51 .byte 0x51 - 2695 02bc 00000000 .4byte 0 - 2696 02c0 00000000 .4byte 0 - 2697 .LLST21: - 2698 02c4 00000000 .4byte .LVL37 - 2699 02c8 24000000 .4byte .LVL40 - 2700 02cc 0100 .2byte 0x1 - 2701 02ce 52 .byte 0x52 - 2702 02cf 24000000 .4byte .LVL40 - 2703 02d3 3E000000 .4byte .LVL41 - 2704 02d7 0300 .2byte 0x3 - 2705 02d9 75 .byte 0x75 - 2706 02da 60 .sleb128 -32 - 2707 02db 9F .byte 0x9f - 2708 02dc 3E000000 .4byte .LVL41 - 2709 02e0 48000000 .4byte .LFE6 - 2710 02e4 0100 .2byte 0x1 - 2711 02e6 52 .byte 0x52 - 2712 02e7 00000000 .4byte 0 - 2713 02eb 00000000 .4byte 0 - 2714 .LLST22: - 2715 02ef 0E000000 .4byte .LVL38 - 2716 02f3 24000000 .4byte .LVL40 - 2717 02f7 0100 .2byte 0x1 - 2718 02f9 56 .byte 0x56 - 2719 02fa 24000000 .4byte .LVL40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 62 - - - 2720 02fe 3D000000 .4byte .LVL41-1 - 2721 0302 0A00 .2byte 0xa - 2722 0304 70 .byte 0x70 - 2723 0305 00 .sleb128 0 - 2724 0306 38 .byte 0x38 - 2725 0307 24 .byte 0x24 - 2726 0308 71 .byte 0x71 - 2727 0309 00 .sleb128 0 - 2728 030a 22 .byte 0x22 - 2729 030b 38 .byte 0x38 - 2730 030c 24 .byte 0x24 - 2731 030d 9F .byte 0x9f - 2732 030e 00000000 .4byte 0 - 2733 0312 00000000 .4byte 0 - 2734 .LLST23: - 2735 0316 0E000000 .4byte .LVL38 - 2736 031a 10000000 .4byte .LVL39 - 2737 031e 0200 .2byte 0x2 - 2738 0320 30 .byte 0x30 - 2739 0321 9F .byte 0x9f - 2740 0322 00000000 .4byte 0 - 2741 0326 00000000 .4byte 0 - 2742 .LLST24: - 2743 032a 00000000 .4byte .LFB5 - 2744 032e 06000000 .4byte .LCFI5 - 2745 0332 0200 .2byte 0x2 - 2746 0334 7D .byte 0x7d - 2747 0335 00 .sleb128 0 - 2748 0336 06000000 .4byte .LCFI5 - 2749 033a 5C000000 .4byte .LFE5 - 2750 033e 0200 .2byte 0x2 - 2751 0340 7D .byte 0x7d - 2752 0341 18 .sleb128 24 - 2753 0342 00000000 .4byte 0 - 2754 0346 00000000 .4byte 0 - 2755 .LLST25: - 2756 034a 00000000 .4byte .LVL43 - 2757 034e 1A000000 .4byte .LVL45 - 2758 0352 0100 .2byte 0x1 - 2759 0354 50 .byte 0x50 - 2760 0355 1A000000 .4byte .LVL45 - 2761 0359 32000000 .4byte .LVL49 - 2762 035d 0400 .2byte 0x4 - 2763 035f F3 .byte 0xf3 - 2764 0360 01 .uleb128 0x1 - 2765 0361 50 .byte 0x50 - 2766 0362 9F .byte 0x9f - 2767 0363 32000000 .4byte .LVL49 - 2768 0367 34000000 .4byte .LVL50 - 2769 036b 0100 .2byte 0x1 - 2770 036d 50 .byte 0x50 - 2771 036e 34000000 .4byte .LVL50 - 2772 0372 50000000 .4byte .LVL53 - 2773 0376 0400 .2byte 0x4 - 2774 0378 F3 .byte 0xf3 - 2775 0379 01 .uleb128 0x1 - 2776 037a 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 63 - - - 2777 037b 9F .byte 0x9f - 2778 037c 50000000 .4byte .LVL53 - 2779 0380 54000000 .4byte .LVL54 - 2780 0384 0100 .2byte 0x1 - 2781 0386 50 .byte 0x50 - 2782 0387 54000000 .4byte .LVL54 - 2783 038b 5C000000 .4byte .LFE5 - 2784 038f 0400 .2byte 0x4 - 2785 0391 F3 .byte 0xf3 - 2786 0392 01 .uleb128 0x1 - 2787 0393 50 .byte 0x50 - 2788 0394 9F .byte 0x9f - 2789 0395 00000000 .4byte 0 - 2790 0399 00000000 .4byte 0 - 2791 .LLST26: - 2792 039d 00000000 .4byte .LVL43 - 2793 03a1 1E000000 .4byte .LVL47 - 2794 03a5 0100 .2byte 0x1 - 2795 03a7 51 .byte 0x51 - 2796 03a8 1E000000 .4byte .LVL47 - 2797 03ac 32000000 .4byte .LVL49 - 2798 03b0 0400 .2byte 0x4 - 2799 03b2 F3 .byte 0xf3 - 2800 03b3 01 .uleb128 0x1 - 2801 03b4 51 .byte 0x51 - 2802 03b5 9F .byte 0x9f - 2803 03b6 32000000 .4byte .LVL49 - 2804 03ba 34000000 .4byte .LVL50 - 2805 03be 0100 .2byte 0x1 - 2806 03c0 51 .byte 0x51 - 2807 03c1 34000000 .4byte .LVL50 - 2808 03c5 50000000 .4byte .LVL53 - 2809 03c9 0400 .2byte 0x4 - 2810 03cb F3 .byte 0xf3 - 2811 03cc 01 .uleb128 0x1 - 2812 03cd 51 .byte 0x51 - 2813 03ce 9F .byte 0x9f - 2814 03cf 50000000 .4byte .LVL53 - 2815 03d3 5C000000 .4byte .LFE5 - 2816 03d7 0100 .2byte 0x1 - 2817 03d9 51 .byte 0x51 - 2818 03da 00000000 .4byte 0 - 2819 03de 00000000 .4byte 0 - 2820 .LLST27: - 2821 03e2 00000000 .4byte .LVL43 - 2822 03e6 3C000000 .4byte .LVL51 - 2823 03ea 0100 .2byte 0x1 - 2824 03ec 52 .byte 0x52 - 2825 03ed 3C000000 .4byte .LVL51 - 2826 03f1 3F000000 .4byte .LVL52-1 - 2827 03f5 0100 .2byte 0x1 - 2828 03f7 51 .byte 0x51 - 2829 03f8 3F000000 .4byte .LVL52-1 - 2830 03fc 50000000 .4byte .LVL53 - 2831 0400 0400 .2byte 0x4 - 2832 0402 F3 .byte 0xf3 - 2833 0403 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 64 - - - 2834 0404 52 .byte 0x52 - 2835 0405 9F .byte 0x9f - 2836 0406 50000000 .4byte .LVL53 - 2837 040a 5C000000 .4byte .LFE5 - 2838 040e 0100 .2byte 0x1 - 2839 0410 52 .byte 0x52 - 2840 0411 00000000 .4byte 0 - 2841 0415 00000000 .4byte 0 - 2842 .LLST28: - 2843 0419 1C000000 .4byte .LVL46 - 2844 041d 1E000000 .4byte .LVL47 - 2845 0421 0200 .2byte 0x2 - 2846 0423 30 .byte 0x30 - 2847 0424 9F .byte 0x9f - 2848 0425 00000000 .4byte 0 - 2849 0429 00000000 .4byte 0 - 2850 .LLST29: - 2851 042d 1C000000 .4byte .LVL46 - 2852 0431 30000000 .4byte .LVL48 - 2853 0435 0100 .2byte 0x1 - 2854 0437 56 .byte 0x56 - 2855 0438 30000000 .4byte .LVL48 - 2856 043c 32000000 .4byte .LVL49 - 2857 0440 0C00 .2byte 0xc - 2858 0442 75 .byte 0x75 - 2859 0443 808009 .sleb128 147456 - 2860 0446 38 .byte 0x38 - 2861 0447 24 .byte 0x24 - 2862 0448 77 .byte 0x77 - 2863 0449 00 .sleb128 0 - 2864 044a 22 .byte 0x22 - 2865 044b 35 .byte 0x35 - 2866 044c 24 .byte 0x24 - 2867 044d 9F .byte 0x9f - 2868 044e 00000000 .4byte 0 - 2869 0452 00000000 .4byte 0 - 2870 .LLST30: - 2871 0456 12000000 .4byte .LVL44 - 2872 045a 32000000 .4byte .LVL49 - 2873 045e 0400 .2byte 0x4 - 2874 0460 0A .byte 0xa - 2875 0461 2001 .2byte 0x120 - 2876 0463 9F .byte 0x9f - 2877 0464 34000000 .4byte .LVL50 - 2878 0468 50000000 .4byte .LVL53 - 2879 046c 0100 .2byte 0x1 - 2880 046e 56 .byte 0x56 - 2881 046f 00000000 .4byte 0 - 2882 0473 00000000 .4byte 0 - 2883 .LLST31: - 2884 0477 00000000 .4byte .LFB8 - 2885 047b 02000000 .4byte .LCFI6 - 2886 047f 0200 .2byte 0x2 - 2887 0481 7D .byte 0x7d - 2888 0482 00 .sleb128 0 - 2889 0483 02000000 .4byte .LCFI6 - 2890 0487 44000000 .4byte .LFE8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 65 - - - 2891 048b 0200 .2byte 0x2 - 2892 048d 7D .byte 0x7d - 2893 048e 08 .sleb128 8 - 2894 048f 00000000 .4byte 0 - 2895 0493 00000000 .4byte 0 - 2896 .LLST32: - 2897 0497 00000000 .4byte .LVL55 - 2898 049b 07000000 .4byte .LVL56-1 - 2899 049f 0100 .2byte 0x1 - 2900 04a1 50 .byte 0x50 - 2901 04a2 07000000 .4byte .LVL56-1 - 2902 04a6 44000000 .4byte .LFE8 - 2903 04aa 0400 .2byte 0x4 - 2904 04ac F3 .byte 0xf3 - 2905 04ad 01 .uleb128 0x1 - 2906 04ae 50 .byte 0x50 - 2907 04af 9F .byte 0x9f - 2908 04b0 00000000 .4byte 0 - 2909 04b4 00000000 .4byte 0 - 2910 .LLST33: - 2911 04b8 08000000 .4byte .LVL56 - 2912 04bc 3D000000 .4byte .LVL57-1 - 2913 04c0 0100 .2byte 0x1 - 2914 04c2 50 .byte 0x50 - 2915 04c3 00000000 .4byte 0 - 2916 04c7 00000000 .4byte 0 - 2917 .section .debug_aranges,"",%progbits - 2918 0000 7C000000 .4byte 0x7c - 2919 0004 0200 .2byte 0x2 - 2920 0006 00000000 .4byte .Ldebug_info0 - 2921 000a 04 .byte 0x4 - 2922 000b 00 .byte 0 - 2923 000c 0000 .2byte 0 - 2924 000e 0000 .2byte 0 - 2925 0010 00000000 .4byte .LFB13 - 2926 0014 54000000 .4byte .LFE13-.LFB13 - 2927 0018 00000000 .4byte .LFB0 - 2928 001c 1C000000 .4byte .LFE0-.LFB0 - 2929 0020 00000000 .4byte .LFB1 - 2930 0024 18000000 .4byte .LFE1-.LFB1 - 2931 0028 00000000 .4byte .LFB3 - 2932 002c 28000000 .4byte .LFE3-.LFB3 - 2933 0030 00000000 .4byte .LFB4 - 2934 0034 2C000000 .4byte .LFE4-.LFB4 - 2935 0038 00000000 .4byte .LFB7 - 2936 003c A0000000 .4byte .LFE7-.LFB7 - 2937 0040 00000000 .4byte .LFB6 - 2938 0044 48000000 .4byte .LFE6-.LFB6 - 2939 0048 00000000 .4byte .LFB5 - 2940 004c 5C000000 .4byte .LFE5-.LFB5 - 2941 0050 00000000 .4byte .LFB8 - 2942 0054 44000000 .4byte .LFE8-.LFB8 - 2943 0058 00000000 .4byte .LFB9 - 2944 005c 18000000 .4byte .LFE9-.LFB9 - 2945 0060 00000000 .4byte .LFB10 - 2946 0064 18000000 .4byte .LFE10-.LFB10 - 2947 0068 00000000 .4byte .LFB11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 66 - - - 2948 006c 20000000 .4byte .LFE11-.LFB11 - 2949 0070 00000000 .4byte .LFB12 - 2950 0074 0C000000 .4byte .LFE12-.LFB12 - 2951 0078 00000000 .4byte 0 - 2952 007c 00000000 .4byte 0 - 2953 .section .debug_ranges,"",%progbits - 2954 .Ldebug_ranges0: - 2955 0000 02000000 .4byte .LBB6 - 2956 0004 10000000 .4byte .LBE6 - 2957 0008 24000000 .4byte .LBB11 - 2958 000c 26000000 .4byte .LBE11 - 2959 0010 00000000 .4byte 0 - 2960 0014 00000000 .4byte 0 - 2961 0018 02000000 .4byte .LBB7 - 2962 001c 10000000 .4byte .LBE7 - 2963 0020 24000000 .4byte .LBB8 - 2964 0024 26000000 .4byte .LBE8 - 2965 0028 00000000 .4byte 0 - 2966 002c 00000000 .4byte 0 - 2967 0030 10000000 .4byte .LBB14 - 2968 0034 4E000000 .4byte .LBE14 - 2969 0038 52000000 .4byte .LBB17 - 2970 003c 94000000 .4byte .LBE17 - 2971 0040 00000000 .4byte 0 - 2972 0044 00000000 .4byte 0 - 2973 0048 10000000 .4byte .LBB15 - 2974 004c 4E000000 .4byte .LBE15 - 2975 0050 52000000 .4byte .LBB16 - 2976 0054 94000000 .4byte .LBE16 - 2977 0058 00000000 .4byte 0 - 2978 005c 00000000 .4byte 0 - 2979 0060 00000000 .4byte .LFB13 - 2980 0064 54000000 .4byte .LFE13 - 2981 0068 00000000 .4byte .LFB0 - 2982 006c 1C000000 .4byte .LFE0 - 2983 0070 00000000 .4byte .LFB1 - 2984 0074 18000000 .4byte .LFE1 - 2985 0078 00000000 .4byte .LFB3 - 2986 007c 28000000 .4byte .LFE3 - 2987 0080 00000000 .4byte .LFB4 - 2988 0084 2C000000 .4byte .LFE4 - 2989 0088 00000000 .4byte .LFB7 - 2990 008c A0000000 .4byte .LFE7 - 2991 0090 00000000 .4byte .LFB6 - 2992 0094 48000000 .4byte .LFE6 - 2993 0098 00000000 .4byte .LFB5 - 2994 009c 5C000000 .4byte .LFE5 - 2995 00a0 00000000 .4byte .LFB8 - 2996 00a4 44000000 .4byte .LFE8 - 2997 00a8 00000000 .4byte .LFB9 - 2998 00ac 18000000 .4byte .LFE9 - 2999 00b0 00000000 .4byte .LFB10 - 3000 00b4 18000000 .4byte .LFE10 - 3001 00b8 00000000 .4byte .LFB11 - 3002 00bc 20000000 .4byte .LFE11 - 3003 00c0 00000000 .4byte .LFB12 - 3004 00c4 0C000000 .4byte .LFE12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 67 - - - 3005 00c8 00000000 .4byte 0 - 3006 00cc 00000000 .4byte 0 - 3007 .section .debug_line,"",%progbits - 3008 .Ldebug_line0: - 3009 0000 FD010000 .section .debug_str,"MS",%progbits,1 - 3009 02005C00 - 3009 00000201 - 3009 FB0E0D00 - 3009 01010101 - 3010 .LASF15: - 3011 0000 63797374 .ascii "cystatus\000" - 3011 61747573 - 3011 00 - 3012 .LASF16: - 3013 0009 72656738 .ascii "reg8\000" - 3013 00 - 3014 .LASF40: - 3015 000e 726F7742 .ascii "rowBuffer\000" - 3015 75666665 - 3015 7200 - 3016 .LASF37: - 3017 0018 43794545 .ascii "CyEEPROM_Stop\000" - 3017 50524F4D - 3017 5F53746F - 3017 7000 - 3018 .LASF45: - 3019 0026 43795370 .ascii "CySpcStart\000" - 3019 63537461 - 3019 727400 - 3020 .LASF47: - 3021 0031 43795370 .ascii "CySpcWriteRow\000" - 3021 63577269 - 3021 7465526F - 3021 7700 - 3022 .LASF3: - 3023 003f 73686F72 .ascii "short unsigned int\000" - 3023 7420756E - 3023 7369676E - 3023 65642069 - 3023 6E7400 - 3024 .LASF43: - 3025 0052 43795370 .ascii "CySpcReadData\000" - 3025 63526561 - 3025 64446174 - 3025 6100 - 3026 .LASF22: - 3027 0060 73746174 .ascii "status\000" - 3027 757300 - 3028 .LASF12: - 3029 0067 666C6F61 .ascii "float\000" - 3029 7400 - 3030 .LASF32: - 3031 006d 4379466C .ascii "CyFlash_SetWaitCycles\000" - 3031 6173685F - 3031 53657457 - 3031 61697443 - 3031 79636C65 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 68 - - - 3032 .LASF7: - 3033 0083 6C6F6E67 .ascii "long long unsigned int\000" - 3033 206C6F6E - 3033 6720756E - 3033 7369676E - 3033 65642069 - 3034 .LASF24: - 3035 009a 43795365 .ascii "CySetFlashEEBuffer\000" - 3035 74466C61 - 3035 73684545 - 3035 42756666 - 3035 657200 - 3036 .LASF44: - 3037 00ad 43795370 .ascii "CySpcUnlock\000" - 3037 63556E6C - 3037 6F636B00 - 3038 .LASF20: - 3039 00b9 726F7744 .ascii "rowData\000" - 3039 61746100 - 3040 .LASF36: - 3041 00c1 43794545 .ascii "CyEEPROM_Start\000" - 3041 50524F4D - 3041 5F537461 - 3041 727400 - 3042 .LASF34: - 3043 00d0 696E7465 .ascii "interruptState\000" - 3043 72727570 - 3043 74537461 - 3043 746500 - 3044 .LASF5: - 3045 00df 6C6F6E67 .ascii "long unsigned int\000" - 3045 20756E73 - 3045 69676E65 - 3045 6420696E - 3045 7400 - 3046 .LASF54: - 3047 00f1 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 3047 43534932 - 3047 53445C73 - 3047 6F667477 - 3047 6172655C - 3048 0120 6E00 .ascii "n\000" - 3049 .LASF9: - 3050 0122 75696E74 .ascii "uint8\000" - 3050 3800 - 3051 .LASF18: - 3052 0128 61727261 .ascii "arrayId\000" - 3052 79496400 - 3053 .LASF56: - 3054 0130 64696554 .ascii "dieTemperature\000" - 3054 656D7065 - 3054 72617475 - 3054 726500 - 3055 .LASF25: - 3056 013f 43795772 .ascii "CyWriteRowConfig\000" - 3056 69746552 - 3056 6F77436F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPOj4Rp.s page 69 - - - 3056 6E666967 - 3056 00 - 3057 .LASF1: - 3058 0150 756E7369 .ascii "unsigned char\000" - 3058 676E6564 - 3058 20636861 - 3058 7200 - 3059 .LASF13: - 3060 015e 646F7562 .ascii "double\000" - 3060 6C6500 - 3061 .LASF35: - 3062 0165 4379466C .ascii "CyFlash_Stop\000" - 3062 6173685F - 3062 53746F70 - 3062 00 - 3063 .LASF21: - 3064 0172 726F7753 .ascii "rowSize\000" - 3064 697A6500 - 3065 .LASF2: - 3066 017a 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202:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); - 203:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 5 - - - 204:.\Generated_Source\PSoC5/CyLib.c **** ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); - 205:.\Generated_Source\PSoC5/CyLib.c **** } - 206:.\Generated_Source\PSoC5/CyLib.c **** else - 207:.\Generated_Source\PSoC5/CyLib.c **** { - 208:.\Generated_Source\PSoC5/CyLib.c **** /*********************************************************************** - 209:.\Generated_Source\PSoC5/CyLib.c **** * Halt CPU in debug mode if: - 210:.\Generated_Source\PSoC5/CyLib.c **** * - P divider is less than required - 211:.\Generated_Source\PSoC5/CyLib.c **** * - Q divider is out of range - 212:.\Generated_Source\PSoC5/CyLib.c **** * - pump current is out of range - 213:.\Generated_Source\PSoC5/CyLib.c **** ***********************************************************************/ - 214:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); - 215:.\Generated_Source\PSoC5/CyLib.c **** } - 216:.\Generated_Source\PSoC5/CyLib.c **** - 217:.\Generated_Source\PSoC5/CyLib.c **** } - 218:.\Generated_Source\PSoC5/CyLib.c **** - 219:.\Generated_Source\PSoC5/CyLib.c **** - 220:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 221:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyPLL_OUT_SetSource - 222:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 223:.\Generated_Source\PSoC5/CyLib.c **** * - 224:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 225:.\Generated_Source\PSoC5/CyLib.c **** * Sets the input clock source to the PLL. The PLL must be disabled before - 226:.\Generated_Source\PSoC5/CyLib.c **** * calling this function. - 227:.\Generated_Source\PSoC5/CyLib.c **** * - 228:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 229:.\Generated_Source\PSoC5/CyLib.c **** * source: One of the three available PLL clock sources - 230:.\Generated_Source\PSoC5/CyLib.c **** * CY_PLL_SOURCE_IMO : IMO - 231:.\Generated_Source\PSoC5/CyLib.c **** * CY_PLL_SOURCE_XTAL : MHz Crystal - 232:.\Generated_Source\PSoC5/CyLib.c **** * CY_PLL_SOURCE_DSI : DSI - 233:.\Generated_Source\PSoC5/CyLib.c **** * - 234:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 235:.\Generated_Source\PSoC5/CyLib.c **** * None - 236:.\Generated_Source\PSoC5/CyLib.c **** * - 237:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 238:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased - 239:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - 240:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - 241:.\Generated_Source\PSoC5/CyLib.c **** * with appropriate parameter. It can be optionally called if CPU clock - 242:.\Generated_Source\PSoC5/CyLib.c **** * frequency is lowered in order to improve CPU performance. - 243:.\Generated_Source\PSoC5/CyLib.c **** * See CyFlash_SetWaitCycles() description for more information. - 244:.\Generated_Source\PSoC5/CyLib.c **** * - 245:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 246:.\Generated_Source\PSoC5/CyLib.c **** void CyPLL_OUT_SetSource(uint8 source) - 247:.\Generated_Source\PSoC5/CyLib.c **** { - 248:.\Generated_Source\PSoC5/CyLib.c **** /* Halt CPU in debug mode if PLL is enabled */ - 249:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); - 250:.\Generated_Source\PSoC5/CyLib.c **** - 251:.\Generated_Source\PSoC5/CyLib.c **** switch(source) - 252:.\Generated_Source\PSoC5/CyLib.c **** { - 253:.\Generated_Source\PSoC5/CyLib.c **** case CY_PLL_SOURCE_IMO: - 254:.\Generated_Source\PSoC5/CyLib.c **** case CY_PLL_SOURCE_XTAL: - 255:.\Generated_Source\PSoC5/CyLib.c **** case CY_PLL_SOURCE_DSI: - 256:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | sou - 257:.\Generated_Source\PSoC5/CyLib.c **** break; - 258:.\Generated_Source\PSoC5/CyLib.c **** - 259:.\Generated_Source\PSoC5/CyLib.c **** default: - 260:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 6 - - - 261:.\Generated_Source\PSoC5/CyLib.c **** break; - 262:.\Generated_Source\PSoC5/CyLib.c **** } - 263:.\Generated_Source\PSoC5/CyLib.c **** } - 264:.\Generated_Source\PSoC5/CyLib.c **** - 265:.\Generated_Source\PSoC5/CyLib.c **** - 266:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 267:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_Start - 268:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 269:.\Generated_Source\PSoC5/CyLib.c **** * - 270:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 271:.\Generated_Source\PSoC5/CyLib.c **** * Enables the IMO. Optionally waits at least 6 us for it to settle. - 272:.\Generated_Source\PSoC5/CyLib.c **** * - 273:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 274:.\Generated_Source\PSoC5/CyLib.c **** * uint8 wait: - 275:.\Generated_Source\PSoC5/CyLib.c **** * 0: Return immediately after configuration - 276:.\Generated_Source\PSoC5/CyLib.c **** * 1: Wait for at least 6 us for the IMO to settle. - 277:.\Generated_Source\PSoC5/CyLib.c **** * - 278:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 279:.\Generated_Source\PSoC5/CyLib.c **** * None - 280:.\Generated_Source\PSoC5/CyLib.c **** * - 281:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 282:.\Generated_Source\PSoC5/CyLib.c **** * If wait is enabled: This function wses the Fast Time Wheel to time the wait. - 283:.\Generated_Source\PSoC5/CyLib.c **** * Any other use of the Fast Time Wheel will be stopped during the period of - 284:.\Generated_Source\PSoC5/CyLib.c **** * this function and then restored. This function also uses the 100 KHz ILO. - 285:.\Generated_Source\PSoC5/CyLib.c **** * If not enabled, this function will enable the 100 KHz ILO for the period of - 286:.\Generated_Source\PSoC5/CyLib.c **** * this function. - 287:.\Generated_Source\PSoC5/CyLib.c **** * - 288:.\Generated_Source\PSoC5/CyLib.c **** * No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or - 289:.\Generated_Source\PSoC5/CyLib.c **** * Once Per Second interrupt may be made by interrupt routines during the period - 290:.\Generated_Source\PSoC5/CyLib.c **** * of this function execution. The current operation of the ILO, Central Time - 291:.\Generated_Source\PSoC5/CyLib.c **** * Wheel and Once Per Second interrupt are maintained during the operation of - 292:.\Generated_Source\PSoC5/CyLib.c **** * this function provided the reading of the Power Manager Interrupt Status - 293:.\Generated_Source\PSoC5/CyLib.c **** * Register is only done using the CyPmReadStatus() function. - 294:.\Generated_Source\PSoC5/CyLib.c **** * - 295:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 296:.\Generated_Source\PSoC5/CyLib.c **** void CyIMO_Start(uint8 wait) - 297:.\Generated_Source\PSoC5/CyLib.c **** { - 298:.\Generated_Source\PSoC5/CyLib.c **** uint8 pmFtwCfg2Reg; - 299:.\Generated_Source\PSoC5/CyLib.c **** uint8 pmFtwCfg0Reg; - 300:.\Generated_Source\PSoC5/CyLib.c **** uint8 ilo100KhzEnable; - 301:.\Generated_Source\PSoC5/CyLib.c **** - 302:.\Generated_Source\PSoC5/CyLib.c **** - 303:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; - 304:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; - 305:.\Generated_Source\PSoC5/CyLib.c **** - 306:.\Generated_Source\PSoC5/CyLib.c **** if(0u != wait) - 307:.\Generated_Source\PSoC5/CyLib.c **** { - 308:.\Generated_Source\PSoC5/CyLib.c **** /* Need to turn on the 100KHz ILO if it happens to not already be running.*/ - 309:.\Generated_Source\PSoC5/CyLib.c **** ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - 310:.\Generated_Source\PSoC5/CyLib.c **** pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; - 311:.\Generated_Source\PSoC5/CyLib.c **** pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; - 312:.\Generated_Source\PSoC5/CyLib.c **** - 313:.\Generated_Source\PSoC5/CyLib.c **** CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); - 314:.\Generated_Source\PSoC5/CyLib.c **** - 315:.\Generated_Source\PSoC5/CyLib.c **** while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) - 316:.\Generated_Source\PSoC5/CyLib.c **** { - 317:.\Generated_Source\PSoC5/CyLib.c **** /* Wait for the interrupt status */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 7 - - - 318:.\Generated_Source\PSoC5/CyLib.c **** } - 319:.\Generated_Source\PSoC5/CyLib.c **** - 320:.\Generated_Source\PSoC5/CyLib.c **** if(0u == ilo100KhzEnable) - 321:.\Generated_Source\PSoC5/CyLib.c **** { - 322:.\Generated_Source\PSoC5/CyLib.c **** CyILO_Stop100K(); - 323:.\Generated_Source\PSoC5/CyLib.c **** } - 324:.\Generated_Source\PSoC5/CyLib.c **** - 325:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; - 326:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; - 327:.\Generated_Source\PSoC5/CyLib.c **** } - 328:.\Generated_Source\PSoC5/CyLib.c **** } - 329:.\Generated_Source\PSoC5/CyLib.c **** - 330:.\Generated_Source\PSoC5/CyLib.c **** - 331:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 332:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_Stop - 333:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 334:.\Generated_Source\PSoC5/CyLib.c **** * - 335:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 336:.\Generated_Source\PSoC5/CyLib.c **** * Disables the IMO. - 337:.\Generated_Source\PSoC5/CyLib.c **** * - 338:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 339:.\Generated_Source\PSoC5/CyLib.c **** * None - 340:.\Generated_Source\PSoC5/CyLib.c **** * - 341:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 342:.\Generated_Source\PSoC5/CyLib.c **** * None - 343:.\Generated_Source\PSoC5/CyLib.c **** * - 344:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 345:.\Generated_Source\PSoC5/CyLib.c **** void CyIMO_Stop(void) - 346:.\Generated_Source\PSoC5/CyLib.c **** { - 347:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); - 348:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); - 349:.\Generated_Source\PSoC5/CyLib.c **** } - 350:.\Generated_Source\PSoC5/CyLib.c **** - 351:.\Generated_Source\PSoC5/CyLib.c **** - 352:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 353:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyUSB_PowerOnCheck - 354:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 355:.\Generated_Source\PSoC5/CyLib.c **** * - 356:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 357:.\Generated_Source\PSoC5/CyLib.c **** * Returns the USB power status value. A private function to cy_boot. - 358:.\Generated_Source\PSoC5/CyLib.c **** * - 359:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 360:.\Generated_Source\PSoC5/CyLib.c **** * None - 361:.\Generated_Source\PSoC5/CyLib.c **** * - 362:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 363:.\Generated_Source\PSoC5/CyLib.c **** * uint8: one if the USB is enabled, 0 if not enabled. - 364:.\Generated_Source\PSoC5/CyLib.c **** * - 365:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 366:.\Generated_Source\PSoC5/CyLib.c **** static uint8 CyUSB_PowerOnCheck(void) - 367:.\Generated_Source\PSoC5/CyLib.c **** { - 368:.\Generated_Source\PSoC5/CyLib.c **** uint8 poweredOn = 0u; - 369:.\Generated_Source\PSoC5/CyLib.c **** - 370:.\Generated_Source\PSoC5/CyLib.c **** /* Check whether device is in Active or AltActiv and if USB is powered on */ - 371:.\Generated_Source\PSoC5/CyLib.c **** if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && - 372:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || - 373:.\Generated_Source\PSoC5/CyLib.c **** (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && - 374:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 8 - - - 375:.\Generated_Source\PSoC5/CyLib.c **** { - 376:.\Generated_Source\PSoC5/CyLib.c **** poweredOn = 1u; - 377:.\Generated_Source\PSoC5/CyLib.c **** } - 378:.\Generated_Source\PSoC5/CyLib.c **** - 379:.\Generated_Source\PSoC5/CyLib.c **** return (poweredOn); - 380:.\Generated_Source\PSoC5/CyLib.c **** } - 381:.\Generated_Source\PSoC5/CyLib.c **** - 382:.\Generated_Source\PSoC5/CyLib.c **** - 383:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 384:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_SetTrimValue - 385:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 386:.\Generated_Source\PSoC5/CyLib.c **** * - 387:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 388:.\Generated_Source\PSoC5/CyLib.c **** * Sets the IMO factory trim values. - 389:.\Generated_Source\PSoC5/CyLib.c **** * - 390:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 391:.\Generated_Source\PSoC5/CyLib.c **** * uint8 freq - frequency for which trims must be set - 392:.\Generated_Source\PSoC5/CyLib.c **** * - 393:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 394:.\Generated_Source\PSoC5/CyLib.c **** * None - 395:.\Generated_Source\PSoC5/CyLib.c **** * - 396:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 397:.\Generated_Source\PSoC5/CyLib.c **** static void CyIMO_SetTrimValue(uint8 freq) - 398:.\Generated_Source\PSoC5/CyLib.c **** { - 26 .loc 1 398 0 - 27 .cfi_startproc - 28 @ args = 0, pretend = 0, frame = 0 - 29 @ frame_needed = 0, uses_anonymous_args = 0 - 30 @ link register save eliminated. - 31 .LVL0: - 32 .LBB10: - 33 .LBB11: - 371:.\Generated_Source\PSoC5/CyLib.c **** if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && - 34 .loc 1 371 0 - 35 0000 204B ldr r3, .L19 - 36 0002 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 37 0004 4A07 lsls r2, r1, #29 - 38 0006 03D1 bne .L2 - 372:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || - 39 .loc 1 372 0 - 40 0008 1F4A ldr r2, .L19+4 - 41 000a 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 371:.\Generated_Source\PSoC5/CyLib.c **** if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && - 42 .loc 1 371 0 - 43 000c DB07 lsls r3, r3, #31 - 44 000e 30D4 bmi .L3 - 45 .L2: - 373:.\Generated_Source\PSoC5/CyLib.c **** (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && - 46 .loc 1 373 0 - 47 0010 1C49 ldr r1, .L19 - 48 0012 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 372:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || - 49 .loc 1 372 0 - 50 0014 02F00703 and r3, r2, #7 - 51 0018 012B cmp r3, #1 - 52 001a 05D1 bne .L15 - 374:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 9 - - - 53 .loc 1 374 0 - 54 001c 1B49 ldr r1, .L19+8 - 55 001e 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 373:.\Generated_Source\PSoC5/CyLib.c **** (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && - 56 .loc 1 373 0 - 57 0020 12F00103 ands r3, r2, #1 - 58 0024 25D1 bne .L3 - 59 0026 00E0 b .L4 - 60 .L15: - 372:.\Generated_Source\PSoC5/CyLib.c **** (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || - 61 .loc 1 372 0 - 62 0028 0023 movs r3, #0 - 63 .LVL1: - 64 .L4: - 65 .LBE11: - 66 .LBE10: - 399:.\Generated_Source\PSoC5/CyLib.c **** uint8 usbPowerOn = CyUSB_PowerOnCheck(); - 400:.\Generated_Source\PSoC5/CyLib.c **** - 401:.\Generated_Source\PSoC5/CyLib.c **** /* If USB is powered */ - 402:.\Generated_Source\PSoC5/CyLib.c **** if(usbPowerOn == 1u) - 403:.\Generated_Source\PSoC5/CyLib.c **** { - 404:.\Generated_Source\PSoC5/CyLib.c **** /* Unlock USB write */ - 405:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); - 406:.\Generated_Source\PSoC5/CyLib.c **** } - 407:.\Generated_Source\PSoC5/CyLib.c **** switch(freq) - 67 .loc 1 407 0 - 68 002a 0828 cmp r0, #8 - 69 002c 28D8 bhi .L1 - 70 002e DFE800F0 tbb [pc, r0] - 71 .L14: - 72 0032 05 .byte (.L6-.L14)/2 - 73 0033 07 .byte (.L7-.L14)/2 - 74 0034 09 .byte (.L8-.L14)/2 - 75 0035 0B .byte (.L9-.L14)/2 - 76 0036 0D .byte (.L10-.L14)/2 - 77 0037 0F .byte (.L11-.L14)/2 - 78 0038 11 .byte (.L12-.L14)/2 - 79 0039 27 .byte (.L1-.L14)/2 - 80 003a 15 .byte (.L13-.L14)/2 - 81 003b 00 .align 1 - 82 .L6: - 408:.\Generated_Source\PSoC5/CyLib.c **** { - 409:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_3MHZ: - 410:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR); - 83 .loc 1 410 0 - 84 003c 144A ldr r2, .L19+12 - 85 003e 0AE0 b .L17 - 86 .L7: - 411:.\Generated_Source\PSoC5/CyLib.c **** break; - 412:.\Generated_Source\PSoC5/CyLib.c **** - 413:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_6MHZ: - 414:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR); - 87 .loc 1 414 0 - 88 0040 144A ldr r2, .L19+16 - 89 0042 08E0 b .L17 - 90 .L8: - 415:.\Generated_Source\PSoC5/CyLib.c **** break; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 10 - - - 416:.\Generated_Source\PSoC5/CyLib.c **** - 417:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_12MHZ: - 418:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR); - 91 .loc 1 418 0 - 92 0044 144A ldr r2, .L19+20 - 93 0046 06E0 b .L17 - 94 .L9: - 419:.\Generated_Source\PSoC5/CyLib.c **** break; - 420:.\Generated_Source\PSoC5/CyLib.c **** - 421:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_24MHZ: - 422:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR); - 95 .loc 1 422 0 - 96 0048 144A ldr r2, .L19+24 - 97 004a 04E0 b .L17 - 98 .L10: - 423:.\Generated_Source\PSoC5/CyLib.c **** break; - 424:.\Generated_Source\PSoC5/CyLib.c **** - 425:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_48MHZ: - 426:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR); - 99 .loc 1 426 0 - 100 004c 144A ldr r2, .L19+28 - 101 004e 02E0 b .L17 - 102 .L11: - 427:.\Generated_Source\PSoC5/CyLib.c **** break; - 428:.\Generated_Source\PSoC5/CyLib.c **** - 429:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_62MHZ: - 430:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR); - 103 .loc 1 430 0 - 104 0050 144A ldr r2, .L19+32 - 105 0052 00E0 b .L17 - 106 .L12: - 431:.\Generated_Source\PSoC5/CyLib.c **** break; - 432:.\Generated_Source\PSoC5/CyLib.c **** - 433:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC5) - 434:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_74MHZ: - 435:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR); - 107 .loc 1 435 0 - 108 0054 144A ldr r2, .L19+36 - 109 .L17: - 110 0056 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 111 0058 144B ldr r3, .L19+40 - 112 005a 08E0 b .L16 - 113 .L13: - 436:.\Generated_Source\PSoC5/CyLib.c **** break; - 437:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC5) */ - 438:.\Generated_Source\PSoC5/CyLib.c **** - 439:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_USB: - 440:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR); - 114 .loc 1 440 0 - 115 005c 1448 ldr r0, .L19+44 - 116 .LVL2: - 117 005e 134A ldr r2, .L19+40 - 118 0060 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 119 0062 1170 strb r1, [r2, #0] - 441:.\Generated_Source\PSoC5/CyLib.c **** - 442:.\Generated_Source\PSoC5/CyLib.c **** /* If USB is powered */ - 443:.\Generated_Source\PSoC5/CyLib.c **** if(usbPowerOn == 1u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 11 - - - 120 .loc 1 443 0 - 121 0064 63B1 cbz r3, .L1 - 444:.\Generated_Source\PSoC5/CyLib.c **** { - 445:.\Generated_Source\PSoC5/CyLib.c **** /* Lock the USB Oscillator */ - 446:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN; - 122 .loc 1 446 0 - 123 0066 134B ldr r3, .L19+48 - 124 0068 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 125 006a 40F00201 orr r1, r0, #2 - 126 .L16: - 127 006e 1970 strb r1, [r3, #0] - 128 0070 7047 bx lr - 129 .LVL3: - 130 .L3: - 405:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); - 131 .loc 1 405 0 - 132 0072 104B ldr r3, .L19+48 - 133 0074 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 134 0076 01F0FD02 and r2, r1, #253 - 135 007a 1A70 strb r2, [r3, #0] - 136 007c 0123 movs r3, #1 - 137 007e D4E7 b .L4 - 138 .LVL4: - 139 .L1: - 140 0080 7047 bx lr - 141 .L20: - 142 0082 00BF .align 2 - 143 .L19: - 144 0084 93430040 .word 1073759123 - 145 0088 A5430040 .word 1073759141 - 146 008c B5430040 .word 1073759157 - 147 0090 08010049 .word 1224737032 - 148 0094 09010049 .word 1224737033 - 149 0098 0A010049 .word 1224737034 - 150 009c 0B010049 .word 1224737035 - 151 00a0 89010049 .word 1224737161 - 152 00a4 0C010049 .word 1224737036 - 153 00a8 0D010049 .word 1224737037 - 154 00ac A1460040 .word 1073759905 - 155 00b0 0F010049 .word 1224737039 - 156 00b4 09600040 .word 1073766409 - 157 .cfi_endproc - 158 .LFE7: - 159 .size CyIMO_SetTrimValue, .-CyIMO_SetTrimValue - 160 .section .text.CyBusClk_Internal_SetDivider,"ax",%progbits - 161 .align 1 - 162 .thumb - 163 .thumb_func - 164 .type CyBusClk_Internal_SetDivider, %function - 165 CyBusClk_Internal_SetDivider: - 166 .LFB14: - 447:.\Generated_Source\PSoC5/CyLib.c **** } - 448:.\Generated_Source\PSoC5/CyLib.c **** break; - 449:.\Generated_Source\PSoC5/CyLib.c **** - 450:.\Generated_Source\PSoC5/CyLib.c **** default: - 451:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); - 452:.\Generated_Source\PSoC5/CyLib.c **** break; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 12 - - - 453:.\Generated_Source\PSoC5/CyLib.c **** } - 454:.\Generated_Source\PSoC5/CyLib.c **** - 455:.\Generated_Source\PSoC5/CyLib.c **** } - 456:.\Generated_Source\PSoC5/CyLib.c **** - 457:.\Generated_Source\PSoC5/CyLib.c **** - 458:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 459:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_SetFreq - 460:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 461:.\Generated_Source\PSoC5/CyLib.c **** * - 462:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 463:.\Generated_Source\PSoC5/CyLib.c **** * Sets the frequency of the IMO. Changes may be made while the IMO is running. - 464:.\Generated_Source\PSoC5/CyLib.c **** * - 465:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 466:.\Generated_Source\PSoC5/CyLib.c **** * freq: Frequency of IMO operation - 467:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_3MHZ to set 3 MHz - 468:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_6MHZ to set 6 MHz - 469:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_12MHZ to set 12 MHz - 470:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_24MHZ to set 24 MHz - 471:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_48MHZ to set 48 MHz - 472:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_62MHZ to set 62.6 MHz - 473:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) - 474:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) - 475:.\Generated_Source\PSoC5/CyLib.c **** * - 476:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 477:.\Generated_Source\PSoC5/CyLib.c **** * None - 478:.\Generated_Source\PSoC5/CyLib.c **** * - 479:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 480:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased - 481:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - 482:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - 483:.\Generated_Source\PSoC5/CyLib.c **** * with appropriate parameter. It can be optionally called if CPU clock - 484:.\Generated_Source\PSoC5/CyLib.c **** * frequency is lowered in order to improve CPU performance. - 485:.\Generated_Source\PSoC5/CyLib.c **** * See CyFlash_SetWaitCycles() description for more information. - 486:.\Generated_Source\PSoC5/CyLib.c **** * - 487:.\Generated_Source\PSoC5/CyLib.c **** * When the USB setting is chosen, the USB clock locking circuit is enabled. - 488:.\Generated_Source\PSoC5/CyLib.c **** * Otherwise this circuit is disabled. The USB block must be powered before - 489:.\Generated_Source\PSoC5/CyLib.c **** * selecting the USB setting. - 490:.\Generated_Source\PSoC5/CyLib.c **** * - 491:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 492:.\Generated_Source\PSoC5/CyLib.c **** void CyIMO_SetFreq(uint8 freq) - 493:.\Generated_Source\PSoC5/CyLib.c **** { - 494:.\Generated_Source\PSoC5/CyLib.c **** uint8 currentFreq; - 495:.\Generated_Source\PSoC5/CyLib.c **** uint8 nextFreq; - 496:.\Generated_Source\PSoC5/CyLib.c **** - 497:.\Generated_Source\PSoC5/CyLib.c **** /*************************************************************************** - 498:.\Generated_Source\PSoC5/CyLib.c **** * When changing the IMO frequency the Trim values must also be set - 499:.\Generated_Source\PSoC5/CyLib.c **** * accordingly.This requires reading the current frequency. If the new - 500:.\Generated_Source\PSoC5/CyLib.c **** * frequency is faster, then set the new trim and then change the frequency, - 501:.\Generated_Source\PSoC5/CyLib.c **** * otherwise change the frequency and then set the new trim values. - 502:.\Generated_Source\PSoC5/CyLib.c **** ***************************************************************************/ - 503:.\Generated_Source\PSoC5/CyLib.c **** - 504:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); - 505:.\Generated_Source\PSoC5/CyLib.c **** - 506:.\Generated_Source\PSoC5/CyLib.c **** /* Check if the requested frequency is USB. */ - 507:.\Generated_Source\PSoC5/CyLib.c **** nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; - 508:.\Generated_Source\PSoC5/CyLib.c **** - 509:.\Generated_Source\PSoC5/CyLib.c **** switch (currentFreq) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 13 - - - 510:.\Generated_Source\PSoC5/CyLib.c **** { - 511:.\Generated_Source\PSoC5/CyLib.c **** case 0u: - 512:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_12MHZ; - 513:.\Generated_Source\PSoC5/CyLib.c **** break; - 514:.\Generated_Source\PSoC5/CyLib.c **** - 515:.\Generated_Source\PSoC5/CyLib.c **** case 1u: - 516:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_6MHZ; - 517:.\Generated_Source\PSoC5/CyLib.c **** break; - 518:.\Generated_Source\PSoC5/CyLib.c **** - 519:.\Generated_Source\PSoC5/CyLib.c **** case 2u: - 520:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_24MHZ; - 521:.\Generated_Source\PSoC5/CyLib.c **** break; - 522:.\Generated_Source\PSoC5/CyLib.c **** - 523:.\Generated_Source\PSoC5/CyLib.c **** case 3u: - 524:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_3MHZ; - 525:.\Generated_Source\PSoC5/CyLib.c **** break; - 526:.\Generated_Source\PSoC5/CyLib.c **** - 527:.\Generated_Source\PSoC5/CyLib.c **** case 4u: - 528:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_48MHZ; - 529:.\Generated_Source\PSoC5/CyLib.c **** break; - 530:.\Generated_Source\PSoC5/CyLib.c **** - 531:.\Generated_Source\PSoC5/CyLib.c **** case 5u: - 532:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_62MHZ; - 533:.\Generated_Source\PSoC5/CyLib.c **** break; - 534:.\Generated_Source\PSoC5/CyLib.c **** - 535:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC5) - 536:.\Generated_Source\PSoC5/CyLib.c **** case 6u: - 537:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_74MHZ; - 538:.\Generated_Source\PSoC5/CyLib.c **** break; - 539:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC5) */ - 540:.\Generated_Source\PSoC5/CyLib.c **** - 541:.\Generated_Source\PSoC5/CyLib.c **** default: - 542:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); - 543:.\Generated_Source\PSoC5/CyLib.c **** break; - 544:.\Generated_Source\PSoC5/CyLib.c **** } - 545:.\Generated_Source\PSoC5/CyLib.c **** - 546:.\Generated_Source\PSoC5/CyLib.c **** if (nextFreq >= currentFreq) - 547:.\Generated_Source\PSoC5/CyLib.c **** { - 548:.\Generated_Source\PSoC5/CyLib.c **** /* Set the new trim first */ - 549:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_SetTrimValue(freq); - 550:.\Generated_Source\PSoC5/CyLib.c **** } - 551:.\Generated_Source\PSoC5/CyLib.c **** - 552:.\Generated_Source\PSoC5/CyLib.c **** /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ - 553:.\Generated_Source\PSoC5/CyLib.c **** switch(freq) - 554:.\Generated_Source\PSoC5/CyLib.c **** { - 555:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_3MHZ: - 556:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 557:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - 558:.\Generated_Source\PSoC5/CyLib.c **** break; - 559:.\Generated_Source\PSoC5/CyLib.c **** - 560:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_6MHZ: - 561:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 562:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - 563:.\Generated_Source\PSoC5/CyLib.c **** break; - 564:.\Generated_Source\PSoC5/CyLib.c **** - 565:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_12MHZ: - 566:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 14 - - - 567:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - 568:.\Generated_Source\PSoC5/CyLib.c **** break; - 569:.\Generated_Source\PSoC5/CyLib.c **** - 570:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_24MHZ: - 571:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 572:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - 573:.\Generated_Source\PSoC5/CyLib.c **** break; - 574:.\Generated_Source\PSoC5/CyLib.c **** - 575:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_48MHZ: - 576:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 577:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - 578:.\Generated_Source\PSoC5/CyLib.c **** break; - 579:.\Generated_Source\PSoC5/CyLib.c **** - 580:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_62MHZ: - 581:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 582:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - 583:.\Generated_Source\PSoC5/CyLib.c **** break; - 584:.\Generated_Source\PSoC5/CyLib.c **** - 585:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC5) - 586:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_74MHZ: - 587:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 588:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - 589:.\Generated_Source\PSoC5/CyLib.c **** break; - 590:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC5) */ - 591:.\Generated_Source\PSoC5/CyLib.c **** - 592:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_FREQ_USB: - 593:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 594:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET; - 595:.\Generated_Source\PSoC5/CyLib.c **** break; - 596:.\Generated_Source\PSoC5/CyLib.c **** - 597:.\Generated_Source\PSoC5/CyLib.c **** default: - 598:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); - 599:.\Generated_Source\PSoC5/CyLib.c **** break; - 600:.\Generated_Source\PSoC5/CyLib.c **** } - 601:.\Generated_Source\PSoC5/CyLib.c **** - 602:.\Generated_Source\PSoC5/CyLib.c **** /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */ - 603:.\Generated_Source\PSoC5/CyLib.c **** if (freq == CY_IMO_FREQ_USB) - 604:.\Generated_Source\PSoC5/CyLib.c **** { - 605:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_EnableDoubler(); - 606:.\Generated_Source\PSoC5/CyLib.c **** } - 607:.\Generated_Source\PSoC5/CyLib.c **** else - 608:.\Generated_Source\PSoC5/CyLib.c **** { - 609:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_DisableDoubler(); - 610:.\Generated_Source\PSoC5/CyLib.c **** } - 611:.\Generated_Source\PSoC5/CyLib.c **** - 612:.\Generated_Source\PSoC5/CyLib.c **** if (nextFreq < currentFreq) - 613:.\Generated_Source\PSoC5/CyLib.c **** { - 614:.\Generated_Source\PSoC5/CyLib.c **** /* Set the new trim after setting the frequency */ - 615:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_SetTrimValue(freq); - 616:.\Generated_Source\PSoC5/CyLib.c **** } - 617:.\Generated_Source\PSoC5/CyLib.c **** } - 618:.\Generated_Source\PSoC5/CyLib.c **** - 619:.\Generated_Source\PSoC5/CyLib.c **** - 620:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 621:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_SetSource - 622:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 623:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 15 - - - 624:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 625:.\Generated_Source\PSoC5/CyLib.c **** * Sets the source of the clock output from the IMO block. - 626:.\Generated_Source\PSoC5/CyLib.c **** * - 627:.\Generated_Source\PSoC5/CyLib.c **** * The output from the IMO is by default the IMO itself. Optionally the MHz - 628:.\Generated_Source\PSoC5/CyLib.c **** * Crystal or a DSI input can be the source of the IMO output instead. - 629:.\Generated_Source\PSoC5/CyLib.c **** * - 630:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 631:.\Generated_Source\PSoC5/CyLib.c **** * source: CY_IMO_SOURCE_DSI to set the DSI as source. - 632:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_SOURCE_XTAL to set the MHz as source. - 633:.\Generated_Source\PSoC5/CyLib.c **** * CY_IMO_SOURCE_IMO to set the IMO itself. - 634:.\Generated_Source\PSoC5/CyLib.c **** * - 635:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 636:.\Generated_Source\PSoC5/CyLib.c **** * None - 637:.\Generated_Source\PSoC5/CyLib.c **** * - 638:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 639:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased - 640:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - 641:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - 642:.\Generated_Source\PSoC5/CyLib.c **** * with appropriate parameter. It can be optionally called if CPU clock - 643:.\Generated_Source\PSoC5/CyLib.c **** * frequency is lowered in order to improve CPU performance. - 644:.\Generated_Source\PSoC5/CyLib.c **** * See CyFlash_SetWaitCycles() description for more information. - 645:.\Generated_Source\PSoC5/CyLib.c **** * - 646:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 647:.\Generated_Source\PSoC5/CyLib.c **** void CyIMO_SetSource(uint8 source) - 648:.\Generated_Source\PSoC5/CyLib.c **** { - 649:.\Generated_Source\PSoC5/CyLib.c **** switch(source) - 650:.\Generated_Source\PSoC5/CyLib.c **** { - 651:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_SOURCE_DSI: - 652:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); - 653:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; - 654:.\Generated_Source\PSoC5/CyLib.c **** break; - 655:.\Generated_Source\PSoC5/CyLib.c **** - 656:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_SOURCE_XTAL: - 657:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; - 658:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; - 659:.\Generated_Source\PSoC5/CyLib.c **** break; - 660:.\Generated_Source\PSoC5/CyLib.c **** - 661:.\Generated_Source\PSoC5/CyLib.c **** case CY_IMO_SOURCE_IMO: - 662:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); - 663:.\Generated_Source\PSoC5/CyLib.c **** break; - 664:.\Generated_Source\PSoC5/CyLib.c **** - 665:.\Generated_Source\PSoC5/CyLib.c **** default: - 666:.\Generated_Source\PSoC5/CyLib.c **** /* Incorrect source value */ - 667:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(0u != 0u); - 668:.\Generated_Source\PSoC5/CyLib.c **** break; - 669:.\Generated_Source\PSoC5/CyLib.c **** } - 670:.\Generated_Source\PSoC5/CyLib.c **** } - 671:.\Generated_Source\PSoC5/CyLib.c **** - 672:.\Generated_Source\PSoC5/CyLib.c **** - 673:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 674:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_EnableDoubler - 675:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 676:.\Generated_Source\PSoC5/CyLib.c **** * - 677:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 678:.\Generated_Source\PSoC5/CyLib.c **** * Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz - 679:.\Generated_Source\PSoC5/CyLib.c **** * input to a 48 MHz output for use by the USB block. - 680:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 16 - - - 681:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 682:.\Generated_Source\PSoC5/CyLib.c **** * None - 683:.\Generated_Source\PSoC5/CyLib.c **** * - 684:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 685:.\Generated_Source\PSoC5/CyLib.c **** * None - 686:.\Generated_Source\PSoC5/CyLib.c **** * - 687:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 688:.\Generated_Source\PSoC5/CyLib.c **** void CyIMO_EnableDoubler(void) - 689:.\Generated_Source\PSoC5/CyLib.c **** { - 690:.\Generated_Source\PSoC5/CyLib.c **** /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */ - 691:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; - 692:.\Generated_Source\PSoC5/CyLib.c **** } - 693:.\Generated_Source\PSoC5/CyLib.c **** - 694:.\Generated_Source\PSoC5/CyLib.c **** - 695:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 696:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIMO_DisableDoubler - 697:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 698:.\Generated_Source\PSoC5/CyLib.c **** * - 699:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 700:.\Generated_Source\PSoC5/CyLib.c **** * Disables the IMO doubler. - 701:.\Generated_Source\PSoC5/CyLib.c **** * - 702:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 703:.\Generated_Source\PSoC5/CyLib.c **** * None - 704:.\Generated_Source\PSoC5/CyLib.c **** * - 705:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 706:.\Generated_Source\PSoC5/CyLib.c **** * None - 707:.\Generated_Source\PSoC5/CyLib.c **** * - 708:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 709:.\Generated_Source\PSoC5/CyLib.c **** void CyIMO_DisableDoubler(void) - 710:.\Generated_Source\PSoC5/CyLib.c **** { - 711:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); - 712:.\Generated_Source\PSoC5/CyLib.c **** } - 713:.\Generated_Source\PSoC5/CyLib.c **** - 714:.\Generated_Source\PSoC5/CyLib.c **** - 715:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 716:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyMasterClk_SetSource - 717:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 718:.\Generated_Source\PSoC5/CyLib.c **** * - 719:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 720:.\Generated_Source\PSoC5/CyLib.c **** * Sets the source of the master clock. - 721:.\Generated_Source\PSoC5/CyLib.c **** * - 722:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 723:.\Generated_Source\PSoC5/CyLib.c **** * source: One of the four available Master clock sources. - 724:.\Generated_Source\PSoC5/CyLib.c **** * CY_MASTER_SOURCE_IMO - 725:.\Generated_Source\PSoC5/CyLib.c **** * CY_MASTER_SOURCE_PLL - 726:.\Generated_Source\PSoC5/CyLib.c **** * CY_MASTER_SOURCE_XTAL - 727:.\Generated_Source\PSoC5/CyLib.c **** * CY_MASTER_SOURCE_DSI - 728:.\Generated_Source\PSoC5/CyLib.c **** * - 729:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 730:.\Generated_Source\PSoC5/CyLib.c **** * None - 731:.\Generated_Source\PSoC5/CyLib.c **** * - 732:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 733:.\Generated_Source\PSoC5/CyLib.c **** * The current source and the new source must both be running and stable before - 734:.\Generated_Source\PSoC5/CyLib.c **** * calling this function. - 735:.\Generated_Source\PSoC5/CyLib.c **** * - 736:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased - 737:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 17 - - - 738:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - 739:.\Generated_Source\PSoC5/CyLib.c **** * with appropriate parameter. It can be optionally called if CPU clock - 740:.\Generated_Source\PSoC5/CyLib.c **** * frequency is lowered in order to improve CPU performance. - 741:.\Generated_Source\PSoC5/CyLib.c **** * See CyFlash_SetWaitCycles() description for more information. - 742:.\Generated_Source\PSoC5/CyLib.c **** * - 743:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 744:.\Generated_Source\PSoC5/CyLib.c **** void CyMasterClk_SetSource(uint8 source) - 745:.\Generated_Source\PSoC5/CyLib.c **** { - 746:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | - 747:.\Generated_Source\PSoC5/CyLib.c **** (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); - 748:.\Generated_Source\PSoC5/CyLib.c **** } - 749:.\Generated_Source\PSoC5/CyLib.c **** - 750:.\Generated_Source\PSoC5/CyLib.c **** - 751:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 752:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyMasterClk_SetDivider - 753:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 754:.\Generated_Source\PSoC5/CyLib.c **** * - 755:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 756:.\Generated_Source\PSoC5/CyLib.c **** * Sets the divider value used to generate Master Clock. - 757:.\Generated_Source\PSoC5/CyLib.c **** * - 758:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 759:.\Generated_Source\PSoC5/CyLib.c **** * uint8 divider: - 760:.\Generated_Source\PSoC5/CyLib.c **** * Valid range [0-255]. The clock will be divided by this value + 1. - 761:.\Generated_Source\PSoC5/CyLib.c **** * For example to divide by 2 this parameter should be set to 1. - 762:.\Generated_Source\PSoC5/CyLib.c **** * - 763:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 764:.\Generated_Source\PSoC5/CyLib.c **** * None - 765:.\Generated_Source\PSoC5/CyLib.c **** * - 766:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 767:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased - 768:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - 769:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - 770:.\Generated_Source\PSoC5/CyLib.c **** * with appropriate parameter. It can be optionally called if CPU clock - 771:.\Generated_Source\PSoC5/CyLib.c **** * frequency is lowered in order to improve CPU performance. - 772:.\Generated_Source\PSoC5/CyLib.c **** * See CyFlash_SetWaitCycles() description for more information. - 773:.\Generated_Source\PSoC5/CyLib.c **** * - 774:.\Generated_Source\PSoC5/CyLib.c **** * When changing the Master or Bus clock divider value from div-by-n to div-by-1 - 775:.\Generated_Source\PSoC5/CyLib.c **** * the first clock cycle output after the div-by-1 can be up to 4 ns shorter - 776:.\Generated_Source\PSoC5/CyLib.c **** * than the final/expected div-by-1 period. - 777:.\Generated_Source\PSoC5/CyLib.c **** * - 778:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 779:.\Generated_Source\PSoC5/CyLib.c **** void CyMasterClk_SetDivider(uint8 divider) - 780:.\Generated_Source\PSoC5/CyLib.c **** { - 781:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_MSTR0_REG = divider; - 782:.\Generated_Source\PSoC5/CyLib.c **** } - 783:.\Generated_Source\PSoC5/CyLib.c **** - 784:.\Generated_Source\PSoC5/CyLib.c **** - 785:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 786:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyBusClk_Internal_SetDivider - 787:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 788:.\Generated_Source\PSoC5/CyLib.c **** * - 789:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 790:.\Generated_Source\PSoC5/CyLib.c **** * Function used by CyBusClk_SetDivider(). For internal use only. - 791:.\Generated_Source\PSoC5/CyLib.c **** * - 792:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 793:.\Generated_Source\PSoC5/CyLib.c **** * divider: Valid range [0-65535]. - 794:.\Generated_Source\PSoC5/CyLib.c **** * The clock will be divided by this value + 1. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 18 - - - 795:.\Generated_Source\PSoC5/CyLib.c **** * For example to divide by 2 this parameter should be set to 1. - 796:.\Generated_Source\PSoC5/CyLib.c **** * - 797:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 798:.\Generated_Source\PSoC5/CyLib.c **** * None - 799:.\Generated_Source\PSoC5/CyLib.c **** * - 800:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 801:.\Generated_Source\PSoC5/CyLib.c **** static void CyBusClk_Internal_SetDivider(uint16 divider) - 802:.\Generated_Source\PSoC5/CyLib.c **** { - 167 .loc 1 802 0 - 168 .cfi_startproc - 169 @ args = 0, pretend = 0, frame = 0 - 170 @ frame_needed = 0, uses_anonymous_args = 0 - 171 @ link register save eliminated. - 172 .LVL5: - 803:.\Generated_Source\PSoC5/CyLib.c **** /* Mask bits to enable shadow loads */ - 804:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; - 173 .loc 1 804 0 - 174 0000 0D4B ldr r3, .L22 - 175 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 176 0004 02F0F001 and r1, r2, #240 - 805:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; - 177 .loc 1 805 0 - 178 0008 0022 movs r2, #0 - 804:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; - 179 .loc 1 804 0 - 180 000a 1970 strb r1, [r3, #0] - 181 .loc 1 805 0 - 182 000c 03F8042C strb r2, [r3, #-4] - 806:.\Generated_Source\PSoC5/CyLib.c **** - 807:.\Generated_Source\PSoC5/CyLib.c **** /* Enable mask bits to enable shadow loads */ - 808:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; - 183 .loc 1 808 0 - 184 0010 13F80C1C ldrb r1, [r3, #-12] @ zero_extendqisi2 - 185 0014 41F08002 orr r2, r1, #128 - 809:.\Generated_Source\PSoC5/CyLib.c **** - 810:.\Generated_Source\PSoC5/CyLib.c **** /* Update Shadow Divider Value Register with the new divider */ - 811:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); - 186 .loc 1 811 0 - 187 0018 C1B2 uxtb r1, r0 - 812:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); - 188 .loc 1 812 0 - 189 001a 000A lsrs r0, r0, #8 - 190 .LVL6: - 808:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; - 191 .loc 1 808 0 - 192 001c 03F80C2C strb r2, [r3, #-12] - 811:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); - 193 .loc 1 811 0 - 194 0020 03F8121C strb r1, [r3, #-18] - 195 .loc 1 812 0 - 196 0024 03F8110C strb r0, [r3, #-17] - 813:.\Generated_Source\PSoC5/CyLib.c **** - 814:.\Generated_Source\PSoC5/CyLib.c **** - 815:.\Generated_Source\PSoC5/CyLib.c **** /*************************************************************************** - 816:.\Generated_Source\PSoC5/CyLib.c **** * Copy shadow value defined in Shadow Divider Value Register - 817:.\Generated_Source\PSoC5/CyLib.c **** * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all - 818:.\Generated_Source\PSoC5/CyLib.c **** * dividers selected in Analog and Digital Clock Mask Registers - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 19 - - - 819:.\Generated_Source\PSoC5/CyLib.c **** * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). - 820:.\Generated_Source\PSoC5/CyLib.c **** ***************************************************************************/ - 821:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; - 197 .loc 1 821 0 - 198 0028 13F8132C ldrb r2, [r3, #-19] @ zero_extendqisi2 - 199 002c 42F00101 orr r1, r2, #1 - 200 0030 03F8131C strb r1, [r3, #-19] - 201 0034 7047 bx lr - 202 .L23: - 203 0036 00BF .align 2 - 204 .L22: - 205 0038 14400040 .word 1073758228 - 206 .cfi_endproc - 207 .LFE14: - 208 .size CyBusClk_Internal_SetDivider, .-CyBusClk_Internal_SetDivider - 209 .section .text.CyPLL_OUT_Stop,"ax",%progbits - 210 .align 1 - 211 .global CyPLL_OUT_Stop - 212 .thumb - 213 .thumb_func - 214 .type CyPLL_OUT_Stop, %function - 215 CyPLL_OUT_Stop: - 216 .LFB1: - 154:.\Generated_Source\PSoC5/CyLib.c **** { - 217 .loc 1 154 0 - 218 .cfi_startproc - 219 @ args = 0, pretend = 0, frame = 0 - 220 @ frame_needed = 0, uses_anonymous_args = 0 - 221 @ link register save eliminated. - 155:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); - 222 .loc 1 155 0 - 223 0000 024B ldr r3, .L25 - 224 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 225 0004 02F0FE00 and r0, r2, #254 - 226 0008 1870 strb r0, [r3, #0] - 227 000a 7047 bx lr - 228 .L26: - 229 .align 2 - 230 .L25: - 231 000c 20420040 .word 1073758752 - 232 .cfi_endproc - 233 .LFE1: - 234 .size CyPLL_OUT_Stop, .-CyPLL_OUT_Stop - 235 .section .text.CyPLL_OUT_SetPQ,"ax",%progbits - 236 .align 1 - 237 .global CyPLL_OUT_SetPQ - 238 .thumb - 239 .thumb_func - 240 .type CyPLL_OUT_SetPQ, %function - 241 CyPLL_OUT_SetPQ: - 242 .LFB2: - 192:.\Generated_Source\PSoC5/CyLib.c **** { - 243 .loc 1 192 0 - 244 .cfi_startproc - 245 @ args = 0, pretend = 0, frame = 0 - 246 @ frame_needed = 0, uses_anonymous_args = 0 - 247 @ link register save eliminated. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 20 - - - 248 .LVL7: - 196:.\Generated_Source\PSoC5/CyLib.c **** if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && - 249 .loc 1 196 0 - 250 0000 0728 cmp r0, #7 - 251 0002 14D9 bls .L27 - 196:.\Generated_Source\PSoC5/CyLib.c **** if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && - 252 .loc 1 196 0 is_stmt 0 discriminator 1 - 253 0004 1029 cmp r1, #16 - 254 0006 12D8 bhi .L27 - 197:.\Generated_Source\PSoC5/CyLib.c **** (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && - 255 .loc 1 197 0 is_stmt 1 - 256 0008 89B1 cbz r1, .L27 - 197:.\Generated_Source\PSoC5/CyLib.c **** (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && - 257 .loc 1 197 0 is_stmt 0 discriminator 1 - 258 000a 82B1 cbz r2, .L27 - 198:.\Generated_Source\PSoC5/CyLib.c **** (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) - 259 .loc 1 198 0 is_stmt 1 - 260 000c 072A cmp r2, #7 - 261 000e 0ED8 bhi .L27 - 201:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_P_REG = pDiv; - 262 .loc 1 201 0 - 263 0010 074B ldr r3, .L35 - 202:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); - 264 .loc 1 202 0 - 265 0012 0139 subs r1, r1, #1 - 266 .LVL8: - 201:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_P_REG = pDiv; - 267 .loc 1 201 0 - 268 0014 1870 strb r0, [r3, #0] - 202:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); - 269 .loc 1 202 0 - 270 0016 C8B2 uxtb r0, r1 - 271 .LVL9: - 272 0018 5870 strb r0, [r3, #1] - 203:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | - 273 .loc 1 203 0 - 274 001a 13F8011C ldrb r1, [r3, #-1] @ zero_extendqisi2 - 204:.\Generated_Source\PSoC5/CyLib.c **** ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); - 275 .loc 1 204 0 - 276 001e 013A subs r2, r2, #1 - 277 .LVL10: - 203:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | - 278 .loc 1 203 0 - 279 0020 01F08F00 and r0, r1, #143 - 280 0024 40EA0211 orr r1, r0, r2, lsl #4 - 281 0028 CAB2 uxtb r2, r1 - 282 002a 03F8012C strb r2, [r3, #-1] - 283 .LVL11: - 284 .L27: - 285 002e 7047 bx lr - 286 .L36: - 287 .align 2 - 288 .L35: - 289 0030 22420040 .word 1073758754 - 290 .cfi_endproc - 291 .LFE2: - 292 .size CyPLL_OUT_SetPQ, .-CyPLL_OUT_SetPQ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 21 - - - 293 .section .text.CyPLL_OUT_SetSource,"ax",%progbits - 294 .align 1 - 295 .global CyPLL_OUT_SetSource - 296 .thumb - 297 .thumb_func - 298 .type CyPLL_OUT_SetSource, %function - 299 CyPLL_OUT_SetSource: - 300 .LFB3: - 247:.\Generated_Source\PSoC5/CyLib.c **** { - 301 .loc 1 247 0 - 302 .cfi_startproc - 303 @ args = 0, pretend = 0, frame = 0 - 304 @ frame_needed = 0, uses_anonymous_args = 0 - 305 @ link register save eliminated. - 306 .LVL12: - 251:.\Generated_Source\PSoC5/CyLib.c **** switch(source) - 307 .loc 1 251 0 - 308 0000 0228 cmp r0, #2 - 309 0002 06D8 bhi .L37 - 256:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | sou - 310 .loc 1 256 0 - 311 0004 4FF04023 mov r3, #1073758208 - 312 0008 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 313 000a 02F0FC01 and r1, r2, #252 - 314 000e 0843 orrs r0, r0, r1 - 315 .LVL13: - 316 0010 1870 strb r0, [r3, #0] - 317 .L37: - 318 0012 7047 bx lr - 319 .cfi_endproc - 320 .LFE3: - 321 .size CyPLL_OUT_SetSource, .-CyPLL_OUT_SetSource - 322 .section .text.CyIMO_Stop,"ax",%progbits - 323 .align 1 - 324 .global CyIMO_Stop - 325 .thumb - 326 .thumb_func - 327 .type CyIMO_Stop, %function - 328 CyIMO_Stop: - 329 .LFB5: - 346:.\Generated_Source\PSoC5/CyLib.c **** { - 330 .loc 1 346 0 - 331 .cfi_startproc - 332 @ args = 0, pretend = 0, frame = 0 - 333 @ frame_needed = 0, uses_anonymous_args = 0 - 334 @ link register save eliminated. - 347:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); - 335 .loc 1 347 0 - 336 0000 044B ldr r3, .L41 - 337 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 338 0004 02F0EF00 and r0, r2, #239 - 339 0008 1870 strb r0, [r3, #0] - 348:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); - 340 .loc 1 348 0 - 341 000a 197C ldrb r1, [r3, #16] @ zero_extendqisi2 - 342 000c 01F0EF02 and r2, r1, #239 - 343 0010 1A74 strb r2, [r3, #16] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 22 - - - 344 0012 7047 bx lr - 345 .L42: - 346 .align 2 - 347 .L41: - 348 0014 A0430040 .word 1073759136 - 349 .cfi_endproc - 350 .LFE5: - 351 .size CyIMO_Stop, .-CyIMO_Stop - 352 .section .text.CyIMO_SetSource,"ax",%progbits - 353 .align 1 - 354 .global CyIMO_SetSource - 355 .thumb - 356 .thumb_func - 357 .type CyIMO_SetSource, %function - 358 CyIMO_SetSource: - 359 .LFB9: - 648:.\Generated_Source\PSoC5/CyLib.c **** { - 360 .loc 1 648 0 - 361 .cfi_startproc - 362 @ args = 0, pretend = 0, frame = 0 - 363 @ frame_needed = 0, uses_anonymous_args = 0 - 364 @ link register save eliminated. - 365 .LVL14: - 649:.\Generated_Source\PSoC5/CyLib.c **** switch(source) - 366 .loc 1 649 0 - 367 0000 0128 cmp r0, #1 - 368 0002 08D0 beq .L46 - 369 0004 14D3 bcc .L45 - 370 0006 0228 cmp r0, #2 - 371 0008 17D1 bne .L43 - 652:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); - 372 .loc 1 652 0 - 373 000a 4FF04023 mov r3, #1073758208 - 374 000e 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 375 0010 02F0BF00 and r0, r2, #191 - 376 .LVL15: - 377 0014 04E0 b .L48 - 378 .LVL16: - 379 .L46: - 657:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; - 380 .loc 1 657 0 - 381 0016 4FF04023 mov r3, #1073758208 - 382 001a 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 383 001c 42F04000 orr r0, r2, #64 - 384 .LVL17: - 385 .L48: - 386 0020 1870 strb r0, [r3, #0] - 658:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; - 387 .loc 1 658 0 - 388 0022 93F80012 ldrb r1, [r3, #512] @ zero_extendqisi2 - 389 0026 41F02002 orr r2, r1, #32 - 390 002a 83F80022 strb r2, [r3, #512] - 659:.\Generated_Source\PSoC5/CyLib.c **** break; - 391 .loc 1 659 0 - 392 002e 7047 bx lr - 393 .LVL18: - 394 .L45: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 23 - - - 662:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); - 395 .loc 1 662 0 - 396 0030 024B ldr r3, .L49 - 397 0032 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 398 .LVL19: - 399 0034 00F0DF01 and r1, r0, #223 - 400 0038 1970 strb r1, [r3, #0] - 401 .L43: - 402 003a 7047 bx lr - 403 .L50: - 404 .align 2 - 405 .L49: - 406 003c 00420040 .word 1073758720 - 407 .cfi_endproc - 408 .LFE9: - 409 .size CyIMO_SetSource, .-CyIMO_SetSource - 410 .section .text.CyIMO_EnableDoubler,"ax",%progbits - 411 .align 1 - 412 .global CyIMO_EnableDoubler - 413 .thumb - 414 .thumb_func - 415 .type CyIMO_EnableDoubler, %function - 416 CyIMO_EnableDoubler: - 417 .LFB10: - 689:.\Generated_Source\PSoC5/CyLib.c **** { - 418 .loc 1 689 0 - 419 .cfi_startproc - 420 @ args = 0, pretend = 0, frame = 0 - 421 @ frame_needed = 0, uses_anonymous_args = 0 - 422 @ link register save eliminated. - 691:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; - 423 .loc 1 691 0 - 424 0000 024B ldr r3, .L52 - 425 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 426 0004 42F01000 orr r0, r2, #16 - 427 0008 1870 strb r0, [r3, #0] - 428 000a 7047 bx lr - 429 .L53: - 430 .align 2 - 431 .L52: - 432 000c 00420040 .word 1073758720 - 433 .cfi_endproc - 434 .LFE10: - 435 .size CyIMO_EnableDoubler, .-CyIMO_EnableDoubler - 436 .section .text.CyIMO_DisableDoubler,"ax",%progbits - 437 .align 1 - 438 .global CyIMO_DisableDoubler - 439 .thumb - 440 .thumb_func - 441 .type CyIMO_DisableDoubler, %function - 442 CyIMO_DisableDoubler: - 443 .LFB11: - 710:.\Generated_Source\PSoC5/CyLib.c **** { - 444 .loc 1 710 0 - 445 .cfi_startproc - 446 @ args = 0, pretend = 0, frame = 0 - 447 @ frame_needed = 0, uses_anonymous_args = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 24 - - - 448 @ link register save eliminated. - 711:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); - 449 .loc 1 711 0 - 450 0000 024B ldr r3, .L55 - 451 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 452 0004 02F0EF00 and r0, r2, #239 - 453 0008 1870 strb r0, [r3, #0] - 454 000a 7047 bx lr - 455 .L56: - 456 .align 2 - 457 .L55: - 458 000c 00420040 .word 1073758720 - 459 .cfi_endproc - 460 .LFE11: - 461 .size CyIMO_DisableDoubler, .-CyIMO_DisableDoubler - 462 .section .text.CyIMO_SetFreq,"ax",%progbits - 463 .align 1 - 464 .global CyIMO_SetFreq - 465 .thumb - 466 .thumb_func - 467 .type CyIMO_SetFreq, %function - 468 CyIMO_SetFreq: - 469 .LFB8: - 493:.\Generated_Source\PSoC5/CyLib.c **** { - 470 .loc 1 493 0 - 471 .cfi_startproc - 472 @ args = 0, pretend = 0, frame = 0 - 473 @ frame_needed = 0, uses_anonymous_args = 0 - 474 .LVL20: - 475 0000 70B5 push {r4, r5, r6, lr} - 476 .LCFI0: - 477 .cfi_def_cfa_offset 16 - 478 .cfi_offset 4, -16 - 479 .cfi_offset 5, -12 - 480 .cfi_offset 6, -8 - 481 .cfi_offset 14, -4 - 504:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); - 482 .loc 1 504 0 - 483 0002 344B ldr r3, .L82 - 507:.\Generated_Source\PSoC5/CyLib.c **** nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; - 484 .loc 1 507 0 - 485 0004 0828 cmp r0, #8 - 486 0006 14BF ite ne - 487 0008 0646 movne r6, r0 - 488 000a 0326 moveq r6, #3 - 504:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); - 489 .loc 1 504 0 - 490 000c 1D78 ldrb r5, [r3, #0] @ zero_extendqisi2 - 493:.\Generated_Source\PSoC5/CyLib.c **** { - 491 .loc 1 493 0 - 492 000e 0446 mov r4, r0 - 504:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); - 493 .loc 1 504 0 - 494 0010 05F00705 and r5, r5, #7 - 495 .LVL21: - 509:.\Generated_Source\PSoC5/CyLib.c **** switch (currentFreq) - 496 .loc 1 509 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 25 - - - 497 0014 022D cmp r5, #2 - 498 0016 05D0 beq .L61 - 509:.\Generated_Source\PSoC5/CyLib.c **** switch (currentFreq) - 499 .loc 1 509 0 is_stmt 0 discriminator 3 - 500 0018 032D cmp r5, #3 - 501 001a 07D0 beq .L80 - 512:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_12MHZ; - 502 .loc 1 512 0 is_stmt 1 discriminator 3 - 503 001c 002D cmp r5, #0 - 504 001e 08BF it eq - 505 0020 0225 moveq r5, #2 - 506 .LVL22: - 507 0022 00E0 b .L59 - 508 .LVL23: - 509 .L61: - 520:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_24MHZ; - 510 .loc 1 520 0 - 511 0024 0325 movs r5, #3 - 512 .LVL24: - 513 .L59: - 546:.\Generated_Source\PSoC5/CyLib.c **** if (nextFreq >= currentFreq) - 514 .loc 1 546 0 - 515 0026 AE42 cmp r6, r5 - 516 0028 04D3 bcc .L63 - 517 002a 00E0 b .L62 - 518 .LVL25: - 519 .L80: - 524:.\Generated_Source\PSoC5/CyLib.c **** currentFreq = CY_IMO_FREQ_3MHZ; - 520 .loc 1 524 0 - 521 002c 0025 movs r5, #0 - 522 .LVL26: - 523 .L62: - 549:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_SetTrimValue(freq); - 524 .loc 1 549 0 - 525 002e 2046 mov r0, r4 - 526 .LVL27: - 527 0030 FFF7FEFF bl CyIMO_SetTrimValue - 528 .LVL28: - 529 .L63: - 553:.\Generated_Source\PSoC5/CyLib.c **** switch(freq) - 530 .loc 1 553 0 - 531 0034 082C cmp r4, #8 - 532 0036 3ED8 bhi .L64 - 533 0038 DFE804F0 tbb [pc, r4] - 534 .L73: - 535 003c 05 .byte (.L65-.L73)/2 - 536 003d 0C .byte (.L66-.L73)/2 - 537 003e 13 .byte (.L67-.L73)/2 - 538 003f 18 .byte (.L68-.L73)/2 - 539 0040 1F .byte (.L69-.L73)/2 - 540 0041 26 .byte (.L70-.L73)/2 - 541 0042 2D .byte (.L71-.L73)/2 - 542 0043 3D .byte (.L64-.L73)/2 - 543 0044 35 .byte (.L72-.L73)/2 - 544 0045 00 .align 1 - 545 .L65: - 556:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 26 - - - 546 .loc 1 556 0 - 547 0046 2348 ldr r0, .L82 - 548 0048 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 549 004a 02F0B801 and r1, r2, #184 - 550 004e 41F00303 orr r3, r1, #3 - 551 0052 26E0 b .L81 - 552 .L66: - 561:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 553 .loc 1 561 0 - 554 0054 1F48 ldr r0, .L82 - 555 0056 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 556 0058 01F0B803 and r3, r1, #184 - 557 005c 43F00103 orr r3, r3, #1 - 558 0060 1FE0 b .L81 - 559 .L67: - 566:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 560 .loc 1 566 0 - 561 0062 1C48 ldr r0, .L82 - 562 0064 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 563 0066 02F0B803 and r3, r2, #184 - 564 006a 1AE0 b .L81 - 565 .L68: - 571:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 566 .loc 1 571 0 - 567 006c 1948 ldr r0, .L82 - 568 006e 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 569 0070 01F0B803 and r3, r1, #184 - 570 0074 43F00203 orr r3, r3, #2 - 571 0078 13E0 b .L81 - 572 .L69: - 576:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 573 .loc 1 576 0 - 574 007a 1648 ldr r0, .L82 - 575 007c 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 576 007e 03F0B802 and r2, r3, #184 - 577 0082 42F00403 orr r3, r2, #4 - 578 0086 0CE0 b .L81 - 579 .L70: - 581:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 580 .loc 1 581 0 - 581 0088 1248 ldr r0, .L82 - 582 008a 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 583 008c 02F0B801 and r1, r2, #184 - 584 0090 41F00503 orr r3, r1, #5 - 585 0094 05E0 b .L81 - 586 .L71: - 587:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 587 .loc 1 587 0 - 588 0096 0F48 ldr r0, .L82 - 589 0098 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 590 009a 02F0B801 and r1, r2, #184 - 591 009e 41F00603 orr r3, r1, #6 - 592 .L81: - 593 00a2 0370 strb r3, [r0, #0] - 589:.\Generated_Source\PSoC5/CyLib.c **** break; - 594 .loc 1 589 0 - 595 00a4 0CE0 b .L76 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 27 - - - 596 .L72: - 593:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) - 597 .loc 1 593 0 - 598 00a6 0B48 ldr r0, .L82 - 599 00a8 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 600 00aa 02F0B801 and r1, r2, #184 - 601 00ae 41F04203 orr r3, r1, #66 - 602 00b2 0370 strb r3, [r0, #0] - 603 00b4 01E0 b .L75 - 604 .L64: - 603:.\Generated_Source\PSoC5/CyLib.c **** if (freq == CY_IMO_FREQ_USB) - 605 .loc 1 603 0 - 606 00b6 082C cmp r4, #8 - 607 00b8 02D1 bne .L76 - 608 .L75: - 605:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_EnableDoubler(); - 609 .loc 1 605 0 - 610 00ba FFF7FEFF bl CyIMO_EnableDoubler - 611 .LVL29: - 612 00be 01E0 b .L77 - 613 .L76: - 609:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_DisableDoubler(); - 614 .loc 1 609 0 - 615 00c0 FFF7FEFF bl CyIMO_DisableDoubler - 616 .LVL30: - 617 .L77: - 612:.\Generated_Source\PSoC5/CyLib.c **** if (nextFreq < currentFreq) - 618 .loc 1 612 0 - 619 00c4 AE42 cmp r6, r5 - 620 00c6 04D2 bcs .L57 - 615:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_SetTrimValue(freq); - 621 .loc 1 615 0 - 622 00c8 2046 mov r0, r4 - 617:.\Generated_Source\PSoC5/CyLib.c **** } - 623 .loc 1 617 0 - 624 00ca BDE87040 pop {r4, r5, r6, lr} - 615:.\Generated_Source\PSoC5/CyLib.c **** CyIMO_SetTrimValue(freq); - 625 .loc 1 615 0 - 626 00ce FFF7FEBF b CyIMO_SetTrimValue - 627 .LVL31: - 628 .L57: - 629 00d2 70BD pop {r4, r5, r6, pc} - 630 .L83: - 631 .align 2 - 632 .L82: - 633 00d4 00420040 .word 1073758720 - 634 .cfi_endproc - 635 .LFE8: - 636 .size CyIMO_SetFreq, .-CyIMO_SetFreq - 637 .section .text.CyMasterClk_SetSource,"ax",%progbits - 638 .align 1 - 639 .global CyMasterClk_SetSource - 640 .thumb - 641 .thumb_func - 642 .type CyMasterClk_SetSource, %function - 643 CyMasterClk_SetSource: - 644 .LFB12: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 28 - - - 745:.\Generated_Source\PSoC5/CyLib.c **** { - 645 .loc 1 745 0 - 646 .cfi_startproc - 647 @ args = 0, pretend = 0, frame = 0 - 648 @ frame_needed = 0, uses_anonymous_args = 0 - 649 @ link register save eliminated. - 650 .LVL32: - 746:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | - 651 .loc 1 746 0 - 652 0000 044B ldr r3, .L85 - 653 0002 00F00300 and r0, r0, #3 - 654 .LVL33: - 655 0006 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 656 0008 02F0FC01 and r1, r2, #252 - 657 000c 40EA0102 orr r2, r0, r1 - 658 0010 1A70 strb r2, [r3, #0] - 659 0012 7047 bx lr - 660 .L86: - 661 .align 2 - 662 .L85: - 663 0014 05400040 .word 1073758213 - 664 .cfi_endproc - 665 .LFE12: - 666 .size CyMasterClk_SetSource, .-CyMasterClk_SetSource - 667 .section .text.CyMasterClk_SetDivider,"ax",%progbits - 668 .align 1 - 669 .global CyMasterClk_SetDivider - 670 .thumb - 671 .thumb_func - 672 .type CyMasterClk_SetDivider, %function - 673 CyMasterClk_SetDivider: - 674 .LFB13: - 780:.\Generated_Source\PSoC5/CyLib.c **** { - 675 .loc 1 780 0 - 676 .cfi_startproc - 677 @ args = 0, pretend = 0, frame = 0 - 678 @ frame_needed = 0, uses_anonymous_args = 0 - 679 @ link register save eliminated. - 680 .LVL34: - 781:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_MSTR0_REG = divider; - 681 .loc 1 781 0 - 682 0000 014B ldr r3, .L88 - 683 0002 1870 strb r0, [r3, #0] - 684 0004 7047 bx lr - 685 .L89: - 686 0006 00BF .align 2 - 687 .L88: - 688 0008 04400040 .word 1073758212 - 689 .cfi_endproc - 690 .LFE13: - 691 .size CyMasterClk_SetDivider, .-CyMasterClk_SetDivider - 692 .section .text.CyBusClk_SetDivider,"ax",%progbits - 693 .align 1 - 694 .global CyBusClk_SetDivider - 695 .thumb - 696 .thumb_func - 697 .type CyBusClk_SetDivider, %function - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 29 - - - 698 CyBusClk_SetDivider: - 699 .LFB15: - 822:.\Generated_Source\PSoC5/CyLib.c **** } - 823:.\Generated_Source\PSoC5/CyLib.c **** - 824:.\Generated_Source\PSoC5/CyLib.c **** - 825:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 826:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyBusClk_SetDivider - 827:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 828:.\Generated_Source\PSoC5/CyLib.c **** * - 829:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 830:.\Generated_Source\PSoC5/CyLib.c **** * Sets the divider value used to generate Bus Clock. - 831:.\Generated_Source\PSoC5/CyLib.c **** * - 832:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 833:.\Generated_Source\PSoC5/CyLib.c **** * divider: Valid range [0-65535]. The clock will be divided by this value + 1. - 834:.\Generated_Source\PSoC5/CyLib.c **** * For example to divide by 2 this parameter should be set to 1. - 835:.\Generated_Source\PSoC5/CyLib.c **** * - 836:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 837:.\Generated_Source\PSoC5/CyLib.c **** * None - 838:.\Generated_Source\PSoC5/CyLib.c **** * - 839:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 840:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased - 841:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - 842:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - 843:.\Generated_Source\PSoC5/CyLib.c **** * with appropriate parameter. It can be optionally called if CPU clock - 844:.\Generated_Source\PSoC5/CyLib.c **** * frequency is lowered in order to improve CPU performance. - 845:.\Generated_Source\PSoC5/CyLib.c **** * See CyFlash_SetWaitCycles() description for more information. - 846:.\Generated_Source\PSoC5/CyLib.c **** * - 847:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 848:.\Generated_Source\PSoC5/CyLib.c **** void CyBusClk_SetDivider(uint16 divider) - 849:.\Generated_Source\PSoC5/CyLib.c **** { - 700 .loc 1 849 0 - 701 .cfi_startproc - 702 @ args = 0, pretend = 0, frame = 0 - 703 @ frame_needed = 0, uses_anonymous_args = 0 - 704 .LVL35: - 705 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 706 .LCFI1: - 707 .cfi_def_cfa_offset 24 - 708 .cfi_offset 3, -24 - 709 .cfi_offset 4, -20 - 710 .cfi_offset 5, -16 - 711 .cfi_offset 6, -12 - 712 .cfi_offset 7, -8 - 713 .cfi_offset 14, -4 - 714 .loc 1 849 0 - 715 0002 0446 mov r4, r0 - 850:.\Generated_Source\PSoC5/CyLib.c **** uint8 masterClkDiv; - 851:.\Generated_Source\PSoC5/CyLib.c **** uint16 busClkDiv; - 852:.\Generated_Source\PSoC5/CyLib.c **** uint8 interruptState; - 853:.\Generated_Source\PSoC5/CyLib.c **** - 854:.\Generated_Source\PSoC5/CyLib.c **** interruptState = CyEnterCriticalSection(); - 716 .loc 1 854 0 - 717 0004 FFF7FEFF bl CyEnterCriticalSection - 718 .LVL36: - 855:.\Generated_Source\PSoC5/CyLib.c **** - 856:.\Generated_Source\PSoC5/CyLib.c **** /* Work around to set the bus clock divider value */ - 857:.\Generated_Source\PSoC5/CyLib.c **** busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 30 - - - 719 .loc 1 857 0 - 720 0008 154B ldr r3, .L100 - 854:.\Generated_Source\PSoC5/CyLib.c **** interruptState = CyEnterCriticalSection(); - 721 .loc 1 854 0 - 722 000a 0646 mov r6, r0 - 723 .LVL37: - 858:.\Generated_Source\PSoC5/CyLib.c **** busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG; - 724 .loc 1 858 0 - 725 000c 581E subs r0, r3, #1 - 726 .LVL38: - 857:.\Generated_Source\PSoC5/CyLib.c **** busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); - 727 .loc 1 857 0 - 728 000e 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 729 .LVL39: - 730 .loc 1 858 0 - 731 0010 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 732 .LVL40: - 859:.\Generated_Source\PSoC5/CyLib.c **** - 860:.\Generated_Source\PSoC5/CyLib.c **** if ((divider == 0u) || (busClkDiv == 0u)) - 733 .loc 1 860 0 - 734 0012 14B1 cbz r4, .L91 - 735 .loc 1 860 0 is_stmt 0 discriminator 1 - 736 0014 51EA0223 orrs r3, r1, r2, lsl #8 - 737 0018 1AD1 bne .L92 - 738 .L91: - 861:.\Generated_Source\PSoC5/CyLib.c **** { - 862:.\Generated_Source\PSoC5/CyLib.c **** /* Save away the master clock divider value */ - 863:.\Generated_Source\PSoC5/CyLib.c **** masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; - 739 .loc 1 863 0 is_stmt 1 - 740 001a 124D ldr r5, .L100+4 - 741 001c 2B78 ldrb r3, [r5, #0] @ zero_extendqisi2 - 864:.\Generated_Source\PSoC5/CyLib.c **** - 865:.\Generated_Source\PSoC5/CyLib.c **** if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) - 742 .loc 1 865 0 - 743 001e 062B cmp r3, #6 - 863:.\Generated_Source\PSoC5/CyLib.c **** masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; - 744 .loc 1 863 0 - 745 0020 1F46 mov r7, r3 - 746 .LVL41: - 747 .loc 1 865 0 - 748 0022 01D8 bhi .L93 - 749 .LVL42: - 750 .LBB12: - 751 .LBB13: - 781:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_MSTR0_REG = divider; - 752 .loc 1 781 0 - 753 0024 0722 movs r2, #7 - 754 .LVL43: - 755 0026 2A70 strb r2, [r5, #0] - 756 .LVL44: - 757 .L93: - 758 0028 0F4D ldr r5, .L100+8 - 759 .LBE13: - 760 .LBE12: - 866:.\Generated_Source\PSoC5/CyLib.c **** { - 867:.\Generated_Source\PSoC5/CyLib.c **** /* Set master clock divider to 7 */ - 868:.\Generated_Source\PSoC5/CyLib.c **** CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 31 - - - 869:.\Generated_Source\PSoC5/CyLib.c **** } - 870:.\Generated_Source\PSoC5/CyLib.c **** - 871:.\Generated_Source\PSoC5/CyLib.c **** if (divider == 0u) - 761 .loc 1 871 0 - 762 002a 3CB9 cbnz r4, .L94 - 872:.\Generated_Source\PSoC5/CyLib.c **** { - 873:.\Generated_Source\PSoC5/CyLib.c **** /* Set the SSS bit and the divider register desired value */ - 874:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; - 763 .loc 1 874 0 - 764 002c 2B78 ldrb r3, [r5, #0] @ zero_extendqisi2 - 765 .LVL45: - 875:.\Generated_Source\PSoC5/CyLib.c **** CyBusClk_Internal_SetDivider(divider); - 766 .loc 1 875 0 - 767 002e 2046 mov r0, r4 - 874:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; - 768 .loc 1 874 0 - 769 0030 43F04002 orr r2, r3, #64 - 770 0034 2A70 strb r2, [r5, #0] - 771 .loc 1 875 0 - 772 0036 FFF7FEFF bl CyBusClk_Internal_SetDivider - 773 .LVL46: - 774 003a 06E0 b .L95 - 775 .LVL47: - 776 .L94: - 876:.\Generated_Source\PSoC5/CyLib.c **** } - 877:.\Generated_Source\PSoC5/CyLib.c **** else - 878:.\Generated_Source\PSoC5/CyLib.c **** { - 879:.\Generated_Source\PSoC5/CyLib.c **** CyBusClk_Internal_SetDivider(divider); - 777 .loc 1 879 0 - 778 003c 2046 mov r0, r4 - 779 003e FFF7FEFF bl CyBusClk_Internal_SetDivider - 780 .LVL48: - 880:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); - 781 .loc 1 880 0 - 782 0042 2878 ldrb r0, [r5, #0] @ zero_extendqisi2 - 783 0044 00F0BF01 and r1, r0, #191 - 784 0048 2970 strb r1, [r5, #0] - 785 .L95: - 786 .LVL49: - 787 .LBB14: - 788 .LBB15: - 781:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_MSTR0_REG = divider; - 789 .loc 1 781 0 - 790 004a 0648 ldr r0, .L100+4 - 791 004c 0770 strb r7, [r0, #0] - 792 004e 02E0 b .L96 - 793 .LVL50: - 794 .L92: - 795 .LBE15: - 796 .LBE14: - 881:.\Generated_Source\PSoC5/CyLib.c **** } - 882:.\Generated_Source\PSoC5/CyLib.c **** - 883:.\Generated_Source\PSoC5/CyLib.c **** /* Restore the master clock */ - 884:.\Generated_Source\PSoC5/CyLib.c **** CyMasterClk_SetDivider(masterClkDiv); - 885:.\Generated_Source\PSoC5/CyLib.c **** } - 886:.\Generated_Source\PSoC5/CyLib.c **** else - 887:.\Generated_Source\PSoC5/CyLib.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 32 - - - 888:.\Generated_Source\PSoC5/CyLib.c **** CyBusClk_Internal_SetDivider(divider); - 797 .loc 1 888 0 - 798 0050 2046 mov r0, r4 - 799 0052 FFF7FEFF bl CyBusClk_Internal_SetDivider - 800 .LVL51: - 801 .L96: - 889:.\Generated_Source\PSoC5/CyLib.c **** } - 890:.\Generated_Source\PSoC5/CyLib.c **** - 891:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); - 802 .loc 1 891 0 - 803 0056 3046 mov r0, r6 - 892:.\Generated_Source\PSoC5/CyLib.c **** } - 804 .loc 1 892 0 - 805 0058 BDE8F840 pop {r3, r4, r5, r6, r7, lr} - 891:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); - 806 .loc 1 891 0 - 807 005c FFF7FEBF b CyExitCriticalSection - 808 .LVL52: - 809 .L101: - 810 .align 2 - 811 .L100: - 812 0060 07400040 .word 1073758215 - 813 0064 04400040 .word 1073758212 - 814 0068 08400040 .word 1073758216 - 815 .cfi_endproc - 816 .LFE15: - 817 .size CyBusClk_SetDivider, .-CyBusClk_SetDivider - 818 .section .text.CyUsbClk_SetSource,"ax",%progbits - 819 .align 1 - 820 .global CyUsbClk_SetSource - 821 .thumb - 822 .thumb_func - 823 .type CyUsbClk_SetSource, %function - 824 CyUsbClk_SetSource: - 825 .LFB16: - 893:.\Generated_Source\PSoC5/CyLib.c **** - 894:.\Generated_Source\PSoC5/CyLib.c **** - 895:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC3) - 896:.\Generated_Source\PSoC5/CyLib.c **** - 897:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 898:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyCpuClk_SetDivider - 899:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 900:.\Generated_Source\PSoC5/CyLib.c **** * - 901:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 902:.\Generated_Source\PSoC5/CyLib.c **** * Sets the divider value used to generate the CPU Clock. Only applicable for - 903:.\Generated_Source\PSoC5/CyLib.c **** * PSoC 3 parts. - 904:.\Generated_Source\PSoC5/CyLib.c **** * - 905:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 906:.\Generated_Source\PSoC5/CyLib.c **** * divider: Valid range [0-15]. The clock will be divided by this value + 1. - 907:.\Generated_Source\PSoC5/CyLib.c **** * For example to divide by 2 this parameter should be set to 1. - 908:.\Generated_Source\PSoC5/CyLib.c **** * - 909:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 910:.\Generated_Source\PSoC5/CyLib.c **** * None - 911:.\Generated_Source\PSoC5/CyLib.c **** * - 912:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 913:.\Generated_Source\PSoC5/CyLib.c **** * If as result of this function execution the CPU clock frequency is increased - 914:.\Generated_Source\PSoC5/CyLib.c **** * then the number of clock cycles the cache will wait before it samples data - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 33 - - - 915:.\Generated_Source\PSoC5/CyLib.c **** * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - 916:.\Generated_Source\PSoC5/CyLib.c **** * with appropriate parameter. It can be optionally called if CPU clock - 917:.\Generated_Source\PSoC5/CyLib.c **** * frequency is lowered in order to improve CPU performance. - 918:.\Generated_Source\PSoC5/CyLib.c **** * See CyFlash_SetWaitCycles() description for more information. - 919:.\Generated_Source\PSoC5/CyLib.c **** * - 920:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 921:.\Generated_Source\PSoC5/CyLib.c **** void CyCpuClk_SetDivider(uint8 divider) - 922:.\Generated_Source\PSoC5/CyLib.c **** { - 923:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) | - 924:.\Generated_Source\PSoC5/CyLib.c **** ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION)); - 925:.\Generated_Source\PSoC5/CyLib.c **** } - 926:.\Generated_Source\PSoC5/CyLib.c **** - 927:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC3) */ - 928:.\Generated_Source\PSoC5/CyLib.c **** - 929:.\Generated_Source\PSoC5/CyLib.c **** - 930:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 931:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyUsbClk_SetSource - 932:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 933:.\Generated_Source\PSoC5/CyLib.c **** * - 934:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 935:.\Generated_Source\PSoC5/CyLib.c **** * Sets the source of the USB clock. - 936:.\Generated_Source\PSoC5/CyLib.c **** * - 937:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 938:.\Generated_Source\PSoC5/CyLib.c **** * source: One of the four available USB clock sources - 939:.\Generated_Source\PSoC5/CyLib.c **** * CY_LIB_USB_CLK_IMO2X - IMO 2x - 940:.\Generated_Source\PSoC5/CyLib.c **** * CY_LIB_USB_CLK_IMO - IMO - 941:.\Generated_Source\PSoC5/CyLib.c **** * CY_LIB_USB_CLK_PLL - PLL - 942:.\Generated_Source\PSoC5/CyLib.c **** * CY_LIB_USB_CLK_DSI - DSI - 943:.\Generated_Source\PSoC5/CyLib.c **** * - 944:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 945:.\Generated_Source\PSoC5/CyLib.c **** * None - 946:.\Generated_Source\PSoC5/CyLib.c **** * - 947:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 948:.\Generated_Source\PSoC5/CyLib.c **** void CyUsbClk_SetSource(uint8 source) - 949:.\Generated_Source\PSoC5/CyLib.c **** { - 826 .loc 1 949 0 - 827 .cfi_startproc - 828 @ args = 0, pretend = 0, frame = 0 - 829 @ frame_needed = 0, uses_anonymous_args = 0 - 830 @ link register save eliminated. - 831 .LVL53: - 950:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK - 832 .loc 1 950 0 - 833 0000 044B ldr r3, .L103 - 834 0002 00F00300 and r0, r0, #3 - 835 .LVL54: - 836 0006 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 837 0008 02F0FC01 and r1, r2, #252 - 838 000c 40EA0102 orr r2, r0, r1 - 839 0010 1A70 strb r2, [r3, #0] - 840 0012 7047 bx lr - 841 .L104: - 842 .align 2 - 843 .L103: - 844 0014 09400040 .word 1073758217 - 845 .cfi_endproc - 846 .LFE16: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 34 - - - 847 .size CyUsbClk_SetSource, .-CyUsbClk_SetSource - 848 .section .text.CyILO_Start1K,"ax",%progbits - 849 .align 1 - 850 .global CyILO_Start1K - 851 .thumb - 852 .thumb_func - 853 .type CyILO_Start1K, %function - 854 CyILO_Start1K: - 855 .LFB17: - 951:.\Generated_Source\PSoC5/CyLib.c **** (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source); - 952:.\Generated_Source\PSoC5/CyLib.c **** } - 953:.\Generated_Source\PSoC5/CyLib.c **** - 954:.\Generated_Source\PSoC5/CyLib.c **** - 955:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 956:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_Start1K - 957:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 958:.\Generated_Source\PSoC5/CyLib.c **** * - 959:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 960:.\Generated_Source\PSoC5/CyLib.c **** * Enables the ILO 1 KHz oscillator. - 961:.\Generated_Source\PSoC5/CyLib.c **** * - 962:.\Generated_Source\PSoC5/CyLib.c **** * Note The ILO 1 KHz oscillator is always enabled by default, regardless of the - 963:.\Generated_Source\PSoC5/CyLib.c **** * selection in the Clock Editor. Therefore, this API is only needed if the - 964:.\Generated_Source\PSoC5/CyLib.c **** * oscillator was turned off manually. - 965:.\Generated_Source\PSoC5/CyLib.c **** * - 966:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 967:.\Generated_Source\PSoC5/CyLib.c **** * None - 968:.\Generated_Source\PSoC5/CyLib.c **** * - 969:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 970:.\Generated_Source\PSoC5/CyLib.c **** * None - 971:.\Generated_Source\PSoC5/CyLib.c **** * - 972:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - 973:.\Generated_Source\PSoC5/CyLib.c **** void CyILO_Start1K(void) - 974:.\Generated_Source\PSoC5/CyLib.c **** { - 856 .loc 1 974 0 - 857 .cfi_startproc - 858 @ args = 0, pretend = 0, frame = 0 - 859 @ frame_needed = 0, uses_anonymous_args = 0 - 860 @ link register save eliminated. - 975:.\Generated_Source\PSoC5/CyLib.c **** /* Set the bit 1 of ILO RS */ - 976:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ; - 861 .loc 1 976 0 - 862 0000 024B ldr r3, .L106 - 863 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 864 0004 42F00200 orr r0, r2, #2 - 865 0008 1870 strb r0, [r3, #0] - 866 000a 7047 bx lr - 867 .L107: - 868 .align 2 - 869 .L106: - 870 000c 00430040 .word 1073758976 - 871 .cfi_endproc - 872 .LFE17: - 873 .size CyILO_Start1K, .-CyILO_Start1K - 874 .section .text.CyILO_Stop1K,"ax",%progbits - 875 .align 1 - 876 .global CyILO_Stop1K - 877 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 35 - - - 878 .thumb_func - 879 .type CyILO_Stop1K, %function - 880 CyILO_Stop1K: - 881 .LFB18: - 977:.\Generated_Source\PSoC5/CyLib.c **** } - 978:.\Generated_Source\PSoC5/CyLib.c **** - 979:.\Generated_Source\PSoC5/CyLib.c **** - 980:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* - 981:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_Stop1K - 982:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** - 983:.\Generated_Source\PSoC5/CyLib.c **** * - 984:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - 985:.\Generated_Source\PSoC5/CyLib.c **** * Disables the ILO 1 KHz oscillator. - 986:.\Generated_Source\PSoC5/CyLib.c **** * - 987:.\Generated_Source\PSoC5/CyLib.c **** * Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power - 988:.\Generated_Source\PSoC5/CyLib.c **** * mode APIs are expected to be used. For more information, refer to the Power - 989:.\Generated_Source\PSoC5/CyLib.c **** * Management section of this document. - 990:.\Generated_Source\PSoC5/CyLib.c **** * - 991:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - 992:.\Generated_Source\PSoC5/CyLib.c **** * None - 993:.\Generated_Source\PSoC5/CyLib.c **** * - 994:.\Generated_Source\PSoC5/CyLib.c **** * Return: - 995:.\Generated_Source\PSoC5/CyLib.c **** * None - 996:.\Generated_Source\PSoC5/CyLib.c **** * - 997:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: - 998:.\Generated_Source\PSoC5/CyLib.c **** * PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. - 999:.\Generated_Source\PSoC5/CyLib.c **** * -1000:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1001:.\Generated_Source\PSoC5/CyLib.c **** void CyILO_Stop1K(void) -1002:.\Generated_Source\PSoC5/CyLib.c **** { - 882 .loc 1 1002 0 - 883 .cfi_startproc - 884 @ args = 0, pretend = 0, frame = 0 - 885 @ frame_needed = 0, uses_anonymous_args = 0 - 886 @ link register save eliminated. -1003:.\Generated_Source\PSoC5/CyLib.c **** /* Clear the bit 1 of ILO RS */ -1004:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ)); - 887 .loc 1 1004 0 - 888 0000 024B ldr r3, .L109 - 889 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 890 0004 02F0FD00 and r0, r2, #253 - 891 0008 1870 strb r0, [r3, #0] - 892 000a 7047 bx lr - 893 .L110: - 894 .align 2 - 895 .L109: - 896 000c 00430040 .word 1073758976 - 897 .cfi_endproc - 898 .LFE18: - 899 .size CyILO_Stop1K, .-CyILO_Stop1K - 900 .section .text.CyILO_Start100K,"ax",%progbits - 901 .align 1 - 902 .global CyILO_Start100K - 903 .thumb - 904 .thumb_func - 905 .type CyILO_Start100K, %function - 906 CyILO_Start100K: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 36 - - - 907 .LFB19: -1005:.\Generated_Source\PSoC5/CyLib.c **** } -1006:.\Generated_Source\PSoC5/CyLib.c **** -1007:.\Generated_Source\PSoC5/CyLib.c **** -1008:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1009:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_Start100K -1010:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1011:.\Generated_Source\PSoC5/CyLib.c **** * -1012:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1013:.\Generated_Source\PSoC5/CyLib.c **** * Enables the ILO 100 KHz oscillator. -1014:.\Generated_Source\PSoC5/CyLib.c **** * -1015:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1016:.\Generated_Source\PSoC5/CyLib.c **** * None -1017:.\Generated_Source\PSoC5/CyLib.c **** * -1018:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1019:.\Generated_Source\PSoC5/CyLib.c **** * None -1020:.\Generated_Source\PSoC5/CyLib.c **** * -1021:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1022:.\Generated_Source\PSoC5/CyLib.c **** void CyILO_Start100K(void) -1023:.\Generated_Source\PSoC5/CyLib.c **** { - 908 .loc 1 1023 0 - 909 .cfi_startproc - 910 @ args = 0, pretend = 0, frame = 0 - 911 @ frame_needed = 0, uses_anonymous_args = 0 - 912 @ link register save eliminated. -1024:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - 913 .loc 1 1024 0 - 914 0000 024B ldr r3, .L112 - 915 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 916 0004 42F00400 orr r0, r2, #4 - 917 0008 1870 strb r0, [r3, #0] - 918 000a 7047 bx lr - 919 .L113: - 920 .align 2 - 921 .L112: - 922 000c 00430040 .word 1073758976 - 923 .cfi_endproc - 924 .LFE19: - 925 .size CyILO_Start100K, .-CyILO_Start100K - 926 .section .text.CyILO_Stop100K,"ax",%progbits - 927 .align 1 - 928 .global CyILO_Stop100K - 929 .thumb - 930 .thumb_func - 931 .type CyILO_Stop100K, %function - 932 CyILO_Stop100K: - 933 .LFB20: -1025:.\Generated_Source\PSoC5/CyLib.c **** } -1026:.\Generated_Source\PSoC5/CyLib.c **** -1027:.\Generated_Source\PSoC5/CyLib.c **** -1028:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1029:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_Stop100K -1030:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1031:.\Generated_Source\PSoC5/CyLib.c **** * -1032:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1033:.\Generated_Source\PSoC5/CyLib.c **** * Disables the ILO 100 KHz oscillator. -1034:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 37 - - -1035:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1036:.\Generated_Source\PSoC5/CyLib.c **** * None -1037:.\Generated_Source\PSoC5/CyLib.c **** * -1038:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1039:.\Generated_Source\PSoC5/CyLib.c **** * None -1040:.\Generated_Source\PSoC5/CyLib.c **** * -1041:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1042:.\Generated_Source\PSoC5/CyLib.c **** void CyILO_Stop100K(void) -1043:.\Generated_Source\PSoC5/CyLib.c **** { - 934 .loc 1 1043 0 - 935 .cfi_startproc - 936 @ args = 0, pretend = 0, frame = 0 - 937 @ frame_needed = 0, uses_anonymous_args = 0 - 938 @ link register save eliminated. -1044:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)); - 939 .loc 1 1044 0 - 940 0000 024B ldr r3, .L115 - 941 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 942 0004 02F0FB00 and r0, r2, #251 - 943 0008 1870 strb r0, [r3, #0] - 944 000a 7047 bx lr - 945 .L116: - 946 .align 2 - 947 .L115: - 948 000c 00430040 .word 1073758976 - 949 .cfi_endproc - 950 .LFE20: - 951 .size CyILO_Stop100K, .-CyILO_Stop100K - 952 .section .text.CyIMO_Start,"ax",%progbits - 953 .align 1 - 954 .global CyIMO_Start - 955 .thumb - 956 .thumb_func - 957 .type CyIMO_Start, %function - 958 CyIMO_Start: - 959 .LFB4: - 297:.\Generated_Source\PSoC5/CyLib.c **** { - 960 .loc 1 297 0 - 961 .cfi_startproc - 962 @ args = 0, pretend = 0, frame = 0 - 963 @ frame_needed = 0, uses_anonymous_args = 0 - 964 .LVL55: - 965 0000 70B5 push {r4, r5, r6, lr} - 966 .LCFI2: - 967 .cfi_def_cfa_offset 16 - 968 .cfi_offset 4, -16 - 969 .cfi_offset 5, -12 - 970 .cfi_offset 6, -8 - 971 .cfi_offset 14, -4 - 303:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; - 972 .loc 1 303 0 - 973 0002 114B ldr r3, .L128 - 974 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 975 0006 42F01001 orr r1, r2, #16 - 976 000a 1970 strb r1, [r3, #0] - 304:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; - 977 .loc 1 304 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 38 - - - 978 000c 1A7C ldrb r2, [r3, #16] @ zero_extendqisi2 - 979 000e 42F01001 orr r1, r2, #16 - 980 0012 1974 strb r1, [r3, #16] - 981 0014 1033 adds r3, r3, #16 - 306:.\Generated_Source\PSoC5/CyLib.c **** if(0u != wait) - 982 .loc 1 306 0 - 983 0016 B0B1 cbz r0, .L117 - 309:.\Generated_Source\PSoC5/CyLib.c **** ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - 984 .loc 1 309 0 - 985 0018 13F8B06C ldrb r6, [r3, #-176] @ zero_extendqisi2 - 310:.\Generated_Source\PSoC5/CyLib.c **** pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; - 986 .loc 1 310 0 - 987 001c 13F8305C ldrb r5, [r3, #-48] @ zero_extendqisi2 - 309:.\Generated_Source\PSoC5/CyLib.c **** ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - 988 .loc 1 309 0 - 989 0020 06F00400 and r0, r6, #4 - 990 .LVL56: - 991 0024 C6B2 uxtb r6, r0 - 992 .LVL57: - 313:.\Generated_Source\PSoC5/CyLib.c **** CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); - 993 .loc 1 313 0 - 994 0026 0020 movs r0, #0 - 995 .LVL58: - 311:.\Generated_Source\PSoC5/CyLib.c **** pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; - 996 .loc 1 311 0 - 997 0028 13F82E4C ldrb r4, [r3, #-46] @ zero_extendqisi2 - 998 .LVL59: - 313:.\Generated_Source\PSoC5/CyLib.c **** CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); - 999 .loc 1 313 0 - 1000 002c FFF7FEFF bl CyPmFtwSetInterval - 1001 .LVL60: - 1002 .L119: - 315:.\Generated_Source\PSoC5/CyLib.c **** while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) - 1003 .loc 1 315 0 discriminator 1 - 1004 0030 0120 movs r0, #1 - 1005 0032 FFF7FEFF bl CyPmReadStatus - 1006 .LVL61: - 1007 0036 C107 lsls r1, r0, #31 - 1008 0038 FAD5 bpl .L119 - 320:.\Generated_Source\PSoC5/CyLib.c **** if(0u == ilo100KhzEnable) - 1009 .loc 1 320 0 - 1010 003a 0EB9 cbnz r6, .L120 - 322:.\Generated_Source\PSoC5/CyLib.c **** CyILO_Stop100K(); - 1011 .loc 1 322 0 - 1012 003c FFF7FEFF bl CyILO_Stop100K - 1013 .LVL62: - 1014 .L120: - 325:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; - 1015 .loc 1 325 0 - 1016 0040 024B ldr r3, .L128+4 - 1017 0042 1D70 strb r5, [r3, #0] - 326:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; - 1018 .loc 1 326 0 - 1019 0044 9C70 strb r4, [r3, #2] - 1020 .LVL63: - 1021 .L117: - 1022 0046 70BD pop {r4, r5, r6, pc} - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 39 - - - 1023 .L129: - 1024 .align 2 - 1025 .L128: - 1026 0048 A0430040 .word 1073759136 - 1027 004c 80430040 .word 1073759104 - 1028 .cfi_endproc - 1029 .LFE4: - 1030 .size CyIMO_Start, .-CyIMO_Start - 1031 .section .text.CyPLL_OUT_Start,"ax",%progbits - 1032 .align 1 - 1033 .global CyPLL_OUT_Start - 1034 .thumb - 1035 .thumb_func - 1036 .type CyPLL_OUT_Start, %function - 1037 CyPLL_OUT_Start: - 1038 .LFB0: - 90:.\Generated_Source\PSoC5/CyLib.c **** { - 1039 .loc 1 90 0 - 1040 .cfi_startproc - 1041 @ args = 0, pretend = 0, frame = 0 - 1042 @ frame_needed = 0, uses_anonymous_args = 0 - 1043 .LVL64: - 1044 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 1045 .LCFI3: - 1046 .cfi_def_cfa_offset 24 - 1047 .cfi_offset 3, -24 - 1048 .cfi_offset 4, -20 - 1049 .cfi_offset 5, -16 - 1050 .cfi_offset 6, -12 - 1051 .cfi_offset 7, -8 - 1052 .cfi_offset 14, -4 - 99:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; - 1053 .loc 1 99 0 - 1054 0002 164B ldr r3, .L145 - 1055 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1056 0006 42F00101 orr r1, r2, #1 - 1057 000a 1970 strb r1, [r3, #0] - 101:.\Generated_Source\PSoC5/CyLib.c **** if(wait != 0u) - 1058 .loc 1 101 0 - 1059 000c 10B3 cbz r0, .L136 - 104:.\Generated_Source\PSoC5/CyLib.c **** iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - 1060 .loc 1 104 0 - 1061 000e 93F8E070 ldrb r7, [r3, #224] @ zero_extendqisi2 - 105:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG; - 1062 .loc 1 105 0 - 1063 0012 93F86061 ldrb r6, [r3, #352] @ zero_extendqisi2 - 104:.\Generated_Source\PSoC5/CyLib.c **** iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - 1064 .loc 1 104 0 - 1065 0016 07F00400 and r0, r7, #4 - 1066 .LVL65: - 1067 001a C7B2 uxtb r7, r0 - 1068 .LVL66: - 108:.\Generated_Source\PSoC5/CyLib.c **** CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); - 1069 .loc 1 108 0 - 1070 001c 1820 movs r0, #24 - 1071 .LVL67: - 106:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 40 - - - 1072 .loc 1 106 0 - 1073 001e 93F86251 ldrb r5, [r3, #354] @ zero_extendqisi2 - 1074 .LVL68: - 108:.\Generated_Source\PSoC5/CyLib.c **** CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); - 1075 .loc 1 108 0 - 1076 0022 FFF7FEFF bl CyPmFtwSetInterval - 1077 .LVL69: - 1078 .L143: - 112:.\Generated_Source\PSoC5/CyLib.c **** while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) - 1079 .loc 1 112 0 discriminator 1 - 1080 0026 0120 movs r0, #1 - 1081 0028 FFF7FEFF bl CyPmReadStatus - 1082 .LVL70: - 1083 002c 10F00101 ands r1, r0, #1 - 1084 0030 08D1 bne .L144 - 1085 .L134: - 115:.\Generated_Source\PSoC5/CyLib.c **** if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) - 1086 .loc 1 115 0 - 1087 0032 0B4C ldr r4, .L145+4 - 1088 0034 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1089 0036 DA07 lsls r2, r3, #31 - 1090 0038 F5D5 bpl .L143 - 117:.\Generated_Source\PSoC5/CyLib.c **** if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) - 1091 .loc 1 117 0 - 1092 003a 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - 1093 003c D407 lsls r4, r2, #31 - 1094 003e F2D5 bpl .L143 - 1095 .L137: - 119:.\Generated_Source\PSoC5/CyLib.c **** status = CYRET_SUCCESS; - 1096 .loc 1 119 0 - 1097 0040 0C46 mov r4, r1 - 1098 0042 00E0 b .L133 - 1099 .L144: - 110:.\Generated_Source\PSoC5/CyLib.c **** status = CYRET_TIMEOUT; - 1100 .loc 1 110 0 - 1101 0044 1024 movs r4, #16 - 1102 .L133: - 1103 .LVL71: - 126:.\Generated_Source\PSoC5/CyLib.c **** if(0u == iloEnableState) - 1104 .loc 1 126 0 - 1105 0046 0FB9 cbnz r7, .L135 - 128:.\Generated_Source\PSoC5/CyLib.c **** CyILO_Stop100K(); - 1106 .loc 1 128 0 - 1107 0048 FFF7FEFF bl CyILO_Stop100K - 1108 .LVL72: - 1109 .L135: - 131:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State; - 1110 .loc 1 131 0 - 1111 004c 0548 ldr r0, .L145+8 - 1112 004e 0670 strb r6, [r0, #0] - 132:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State; - 1113 .loc 1 132 0 - 1114 0050 8570 strb r5, [r0, #2] - 1115 0052 00E0 b .L131 - 1116 .LVL73: - 1117 .L136: - 91:.\Generated_Source\PSoC5/CyLib.c **** cystatus status = CYRET_SUCCESS; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 41 - - - 1118 .loc 1 91 0 - 1119 0054 0446 mov r4, r0 - 1120 .LVL74: - 1121 .L131: - 136:.\Generated_Source\PSoC5/CyLib.c **** } - 1122 .loc 1 136 0 - 1123 0056 2046 mov r0, r4 - 1124 0058 F8BD pop {r3, r4, r5, r6, r7, pc} - 1125 .L146: - 1126 005a 00BF .align 2 - 1127 .L145: - 1128 005c 20420040 .word 1073758752 - 1129 0060 25420040 .word 1073758757 - 1130 0064 80430040 .word 1073759104 - 1131 .cfi_endproc - 1132 .LFE0: - 1133 .size CyPLL_OUT_Start, .-CyPLL_OUT_Start - 1134 .section .text.CyILO_Enable33K,"ax",%progbits - 1135 .align 1 - 1136 .global CyILO_Enable33K - 1137 .thumb - 1138 .thumb_func - 1139 .type CyILO_Enable33K, %function - 1140 CyILO_Enable33K: - 1141 .LFB21: -1045:.\Generated_Source\PSoC5/CyLib.c **** } -1046:.\Generated_Source\PSoC5/CyLib.c **** -1047:.\Generated_Source\PSoC5/CyLib.c **** -1048:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1049:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_Enable33K -1050:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1051:.\Generated_Source\PSoC5/CyLib.c **** * -1052:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1053:.\Generated_Source\PSoC5/CyLib.c **** * Enables the ILO 33 KHz divider. -1054:.\Generated_Source\PSoC5/CyLib.c **** * -1055:.\Generated_Source\PSoC5/CyLib.c **** * Note that the 33 KHz clock is generated from the 100 KHz oscillator, -1056:.\Generated_Source\PSoC5/CyLib.c **** * so it must also be running in order to generate the 33 KHz output. -1057:.\Generated_Source\PSoC5/CyLib.c **** * -1058:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1059:.\Generated_Source\PSoC5/CyLib.c **** * None -1060:.\Generated_Source\PSoC5/CyLib.c **** * -1061:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1062:.\Generated_Source\PSoC5/CyLib.c **** * None -1063:.\Generated_Source\PSoC5/CyLib.c **** * -1064:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1065:.\Generated_Source\PSoC5/CyLib.c **** void CyILO_Enable33K(void) -1066:.\Generated_Source\PSoC5/CyLib.c **** { - 1142 .loc 1 1066 0 - 1143 .cfi_startproc - 1144 @ args = 0, pretend = 0, frame = 0 - 1145 @ frame_needed = 0, uses_anonymous_args = 0 - 1146 @ link register save eliminated. -1067:.\Generated_Source\PSoC5/CyLib.c **** /* Set the bit 5 of ILO RS */ -1068:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ; - 1147 .loc 1 1068 0 - 1148 0000 024B ldr r3, .L148 - 1149 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 42 - - - 1150 0004 42F02000 orr r0, r2, #32 - 1151 0008 1870 strb r0, [r3, #0] - 1152 000a 7047 bx lr - 1153 .L149: - 1154 .align 2 - 1155 .L148: - 1156 000c 00430040 .word 1073758976 - 1157 .cfi_endproc - 1158 .LFE21: - 1159 .size CyILO_Enable33K, .-CyILO_Enable33K - 1160 .section .text.CyILO_Disable33K,"ax",%progbits - 1161 .align 1 - 1162 .global CyILO_Disable33K - 1163 .thumb - 1164 .thumb_func - 1165 .type CyILO_Disable33K, %function - 1166 CyILO_Disable33K: - 1167 .LFB22: -1069:.\Generated_Source\PSoC5/CyLib.c **** } -1070:.\Generated_Source\PSoC5/CyLib.c **** -1071:.\Generated_Source\PSoC5/CyLib.c **** -1072:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1073:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_Disable33K -1074:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1075:.\Generated_Source\PSoC5/CyLib.c **** * -1076:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1077:.\Generated_Source\PSoC5/CyLib.c **** * Disables the ILO 33 KHz divider. -1078:.\Generated_Source\PSoC5/CyLib.c **** * -1079:.\Generated_Source\PSoC5/CyLib.c **** * Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this -1080:.\Generated_Source\PSoC5/CyLib.c **** * API does not disable the 100 KHz clock. -1081:.\Generated_Source\PSoC5/CyLib.c **** * -1082:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1083:.\Generated_Source\PSoC5/CyLib.c **** * None -1084:.\Generated_Source\PSoC5/CyLib.c **** * -1085:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1086:.\Generated_Source\PSoC5/CyLib.c **** * None -1087:.\Generated_Source\PSoC5/CyLib.c **** * -1088:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1089:.\Generated_Source\PSoC5/CyLib.c **** void CyILO_Disable33K(void) -1090:.\Generated_Source\PSoC5/CyLib.c **** { - 1168 .loc 1 1090 0 - 1169 .cfi_startproc - 1170 @ args = 0, pretend = 0, frame = 0 - 1171 @ frame_needed = 0, uses_anonymous_args = 0 - 1172 @ link register save eliminated. -1091:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ)); - 1173 .loc 1 1091 0 - 1174 0000 024B ldr r3, .L151 - 1175 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1176 0004 02F0DF00 and r0, r2, #223 - 1177 0008 1870 strb r0, [r3, #0] - 1178 000a 7047 bx lr - 1179 .L152: - 1180 .align 2 - 1181 .L151: - 1182 000c 00430040 .word 1073758976 - 1183 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 43 - - - 1184 .LFE22: - 1185 .size CyILO_Disable33K, .-CyILO_Disable33K - 1186 .section .text.CyILO_SetSource,"ax",%progbits - 1187 .align 1 - 1188 .global CyILO_SetSource - 1189 .thumb - 1190 .thumb_func - 1191 .type CyILO_SetSource, %function - 1192 CyILO_SetSource: - 1193 .LFB23: -1092:.\Generated_Source\PSoC5/CyLib.c **** } -1093:.\Generated_Source\PSoC5/CyLib.c **** -1094:.\Generated_Source\PSoC5/CyLib.c **** -1095:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1096:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_SetSource -1097:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1098:.\Generated_Source\PSoC5/CyLib.c **** * -1099:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1100:.\Generated_Source\PSoC5/CyLib.c **** * Sets the source of the clock output from the ILO block. -1101:.\Generated_Source\PSoC5/CyLib.c **** * -1102:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1103:.\Generated_Source\PSoC5/CyLib.c **** * source: One of the three available ILO output sources -1104:.\Generated_Source\PSoC5/CyLib.c **** * Value Define Source -1105:.\Generated_Source\PSoC5/CyLib.c **** * 0 CY_ILO_SOURCE_100K ILO 100 KHz -1106:.\Generated_Source\PSoC5/CyLib.c **** * 1 CY_ILO_SOURCE_33K ILO 33 KHz -1107:.\Generated_Source\PSoC5/CyLib.c **** * 2 CY_ILO_SOURCE_1K ILO 1 KHz -1108:.\Generated_Source\PSoC5/CyLib.c **** * -1109:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1110:.\Generated_Source\PSoC5/CyLib.c **** * None -1111:.\Generated_Source\PSoC5/CyLib.c **** * -1112:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1113:.\Generated_Source\PSoC5/CyLib.c **** void CyILO_SetSource(uint8 source) -1114:.\Generated_Source\PSoC5/CyLib.c **** { - 1194 .loc 1 1114 0 - 1195 .cfi_startproc - 1196 @ args = 0, pretend = 0, frame = 0 - 1197 @ frame_needed = 0, uses_anonymous_args = 0 - 1198 @ link register save eliminated. - 1199 .LVL75: -1115:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | - 1200 .loc 1 1115 0 - 1201 0000 4FF04023 mov r3, #1073758208 - 1202 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 -1116:.\Generated_Source\PSoC5/CyLib.c **** (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); - 1203 .loc 1 1116 0 - 1204 0006 8000 lsls r0, r0, #2 - 1205 .LVL76: -1115:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | - 1206 .loc 1 1115 0 - 1207 0008 00F00C01 and r1, r0, #12 - 1208 000c 02F0F302 and r2, r2, #243 - 1209 0010 41EA0200 orr r0, r1, r2 - 1210 0014 1870 strb r0, [r3, #0] - 1211 0016 7047 bx lr - 1212 .cfi_endproc - 1213 .LFE23: - 1214 .size CyILO_SetSource, .-CyILO_SetSource - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 44 - - - 1215 .section .text.CyILO_SetPowerMode,"ax",%progbits - 1216 .align 1 - 1217 .global CyILO_SetPowerMode - 1218 .thumb - 1219 .thumb_func - 1220 .type CyILO_SetPowerMode, %function - 1221 CyILO_SetPowerMode: - 1222 .LFB24: -1117:.\Generated_Source\PSoC5/CyLib.c **** } -1118:.\Generated_Source\PSoC5/CyLib.c **** -1119:.\Generated_Source\PSoC5/CyLib.c **** -1120:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1121:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyILO_SetPowerMode -1122:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1123:.\Generated_Source\PSoC5/CyLib.c **** * -1124:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1125:.\Generated_Source\PSoC5/CyLib.c **** * Sets the power mode used by the ILO during power down. Allows for lower power -1126:.\Generated_Source\PSoC5/CyLib.c **** * down power usage resulting in a slower startup time. -1127:.\Generated_Source\PSoC5/CyLib.c **** * -1128:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1129:.\Generated_Source\PSoC5/CyLib.c **** * uint8 mode -1130:.\Generated_Source\PSoC5/CyLib.c **** * CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down -1131:.\Generated_Source\PSoC5/CyLib.c **** * CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down -1132:.\Generated_Source\PSoC5/CyLib.c **** * -1133:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1134:.\Generated_Source\PSoC5/CyLib.c **** * Prevous power mode state. -1135:.\Generated_Source\PSoC5/CyLib.c **** * -1136:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1137:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyILO_SetPowerMode(uint8 mode) -1138:.\Generated_Source\PSoC5/CyLib.c **** { - 1223 .loc 1 1138 0 - 1224 .cfi_startproc - 1225 @ args = 0, pretend = 0, frame = 0 - 1226 @ frame_needed = 0, uses_anonymous_args = 0 - 1227 @ link register save eliminated. - 1228 .LVL77: -1139:.\Generated_Source\PSoC5/CyLib.c **** uint8 state; -1140:.\Generated_Source\PSoC5/CyLib.c **** -1141:.\Generated_Source\PSoC5/CyLib.c **** /* Get current state. */ -1142:.\Generated_Source\PSoC5/CyLib.c **** state = CY_LIB_SLOWCLK_ILO_CR0_REG; - 1229 .loc 1 1142 0 - 1230 0000 054A ldr r2, .L158 - 1231 0002 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 1232 .LVL78: -1143:.\Generated_Source\PSoC5/CyLib.c **** -1144:.\Generated_Source\PSoC5/CyLib.c **** /* Set the the oscillator power mode. */ -1145:.\Generated_Source\PSoC5/CyLib.c **** if(mode != CY_ILO_FAST_START) - 1233 .loc 1 1145 0 - 1234 0004 10B1 cbz r0, .L155 -1146:.\Generated_Source\PSoC5/CyLib.c **** { -1147:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE); - 1235 .loc 1 1147 0 - 1236 0006 43F01001 orr r1, r3, #16 - 1237 000a 01E0 b .L157 - 1238 .L155: -1148:.\Generated_Source\PSoC5/CyLib.c **** } -1149:.\Generated_Source\PSoC5/CyLib.c **** else - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 45 - - -1150:.\Generated_Source\PSoC5/CyLib.c **** { -1151:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE))); - 1239 .loc 1 1151 0 - 1240 000c 03F0EF01 and r1, r3, #239 - 1241 .L157: - 1242 0010 1170 strb r1, [r2, #0] -1152:.\Generated_Source\PSoC5/CyLib.c **** } -1153:.\Generated_Source\PSoC5/CyLib.c **** -1154:.\Generated_Source\PSoC5/CyLib.c **** /* Return the old mode. */ -1155:.\Generated_Source\PSoC5/CyLib.c **** return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION); -1156:.\Generated_Source\PSoC5/CyLib.c **** } - 1243 .loc 1 1156 0 - 1244 0012 C3F30010 ubfx r0, r3, #4, #1 - 1245 .LVL79: - 1246 0016 7047 bx lr - 1247 .L159: - 1248 .align 2 - 1249 .L158: - 1250 0018 00430040 .word 1073758976 - 1251 .cfi_endproc - 1252 .LFE24: - 1253 .size CyILO_SetPowerMode, .-CyILO_SetPowerMode - 1254 .section .text.CyXTAL_32KHZ_Stop,"ax",%progbits - 1255 .align 1 - 1256 .global CyXTAL_32KHZ_Stop - 1257 .thumb - 1258 .thumb_func - 1259 .type CyXTAL_32KHZ_Stop, %function - 1260 CyXTAL_32KHZ_Stop: - 1261 .LFB26: -1157:.\Generated_Source\PSoC5/CyLib.c **** -1158:.\Generated_Source\PSoC5/CyLib.c **** -1159:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1160:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_32KHZ_Start -1161:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1162:.\Generated_Source\PSoC5/CyLib.c **** * -1163:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1164:.\Generated_Source\PSoC5/CyLib.c **** * Enables the 32 KHz Crystal Oscillator. -1165:.\Generated_Source\PSoC5/CyLib.c **** * -1166:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1167:.\Generated_Source\PSoC5/CyLib.c **** * None -1168:.\Generated_Source\PSoC5/CyLib.c **** * -1169:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1170:.\Generated_Source\PSoC5/CyLib.c **** * None -1171:.\Generated_Source\PSoC5/CyLib.c **** * -1172:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1173:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_32KHZ_Start(void) -1174:.\Generated_Source\PSoC5/CyLib.c **** { -1175:.\Generated_Source\PSoC5/CyLib.c **** volatile uint16 i; -1176:.\Generated_Source\PSoC5/CyLib.c **** -1177:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; -1178:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; -1179:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | -1180:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_LP_DEFAULT; -1181:.\Generated_Source\PSoC5/CyLib.c **** -1182:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC3) -1183:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 46 - - -1184:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC3) */ -1185:.\Generated_Source\PSoC5/CyLib.c **** -1186:.\Generated_Source\PSoC5/CyLib.c **** /* Enable operation of the 32K Crystal Oscillator */ -1187:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; -1188:.\Generated_Source\PSoC5/CyLib.c **** -1189:.\Generated_Source\PSoC5/CyLib.c **** for (i = 1000u; i > 0u; i--) -1190:.\Generated_Source\PSoC5/CyLib.c **** { -1191:.\Generated_Source\PSoC5/CyLib.c **** if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) -1192:.\Generated_Source\PSoC5/CyLib.c **** { -1193:.\Generated_Source\PSoC5/CyLib.c **** /* Ready - switch to the hign power mode */ -1194:.\Generated_Source\PSoC5/CyLib.c **** (void) CyXTAL_32KHZ_SetPowerMode(0u); -1195:.\Generated_Source\PSoC5/CyLib.c **** -1196:.\Generated_Source\PSoC5/CyLib.c **** break; -1197:.\Generated_Source\PSoC5/CyLib.c **** } -1198:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(1u); -1199:.\Generated_Source\PSoC5/CyLib.c **** } -1200:.\Generated_Source\PSoC5/CyLib.c **** } -1201:.\Generated_Source\PSoC5/CyLib.c **** -1202:.\Generated_Source\PSoC5/CyLib.c **** -1203:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1204:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_32KHZ_Stop -1205:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1206:.\Generated_Source\PSoC5/CyLib.c **** * -1207:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1208:.\Generated_Source\PSoC5/CyLib.c **** * Disables the 32KHz Crystal Oscillator. -1209:.\Generated_Source\PSoC5/CyLib.c **** * -1210:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1211:.\Generated_Source\PSoC5/CyLib.c **** * None -1212:.\Generated_Source\PSoC5/CyLib.c **** * -1213:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1214:.\Generated_Source\PSoC5/CyLib.c **** * None -1215:.\Generated_Source\PSoC5/CyLib.c **** * -1216:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1217:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_32KHZ_Stop(void) -1218:.\Generated_Source\PSoC5/CyLib.c **** { - 1262 .loc 1 1218 0 - 1263 .cfi_startproc - 1264 @ args = 0, pretend = 0, frame = 0 - 1265 @ frame_needed = 0, uses_anonymous_args = 0 - 1266 @ link register save eliminated. -1219:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - 1267 .loc 1 1219 0 - 1268 0000 094B ldr r3, .L161 - 1269 0002 F322 movs r2, #243 -1220:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; - 1270 .loc 1 1220 0 - 1271 0004 0949 ldr r1, .L161+4 -1219:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - 1272 .loc 1 1219 0 - 1273 0006 1A70 strb r2, [r3, #0] - 1274 .loc 1 1220 0 - 1275 0008 0020 movs r0, #0 -1221:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - 1276 .loc 1 1221 0 - 1277 000a 094B ldr r3, .L161+8 -1220:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; - 1278 .loc 1 1220 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 47 - - - 1279 000c 0870 strb r0, [r1, #0] - 1280 .loc 1 1221 0 - 1281 000e 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1282 0010 02F0F300 and r0, r2, #243 - 1283 0014 40F00401 orr r1, r0, #4 - 1284 0018 1970 strb r1, [r3, #0] -1222:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_LP_DEFAULT; -1223:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); - 1285 .loc 1 1223 0 - 1286 001a 13F8012C ldrb r2, [r3, #-1] @ zero_extendqisi2 - 1287 001e 02F0FC00 and r0, r2, #252 - 1288 0022 03F8010C strb r0, [r3, #-1] - 1289 0026 7047 bx lr - 1290 .L162: - 1291 .align 2 - 1292 .L161: - 1293 0028 0A430040 .word 1073758986 - 1294 002c 98460040 .word 1073759896 - 1295 0030 09430040 .word 1073758985 - 1296 .cfi_endproc - 1297 .LFE26: - 1298 .size CyXTAL_32KHZ_Stop, .-CyXTAL_32KHZ_Stop - 1299 .section .text.CyXTAL_32KHZ_ReadStatus,"ax",%progbits - 1300 .align 1 - 1301 .global CyXTAL_32KHZ_ReadStatus - 1302 .thumb - 1303 .thumb_func - 1304 .type CyXTAL_32KHZ_ReadStatus, %function - 1305 CyXTAL_32KHZ_ReadStatus: - 1306 .LFB27: -1224:.\Generated_Source\PSoC5/CyLib.c **** -1225:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC3) -1226:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); -1227:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC3) */ -1228:.\Generated_Source\PSoC5/CyLib.c **** } -1229:.\Generated_Source\PSoC5/CyLib.c **** -1230:.\Generated_Source\PSoC5/CyLib.c **** -1231:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1232:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_32KHZ_ReadStatus -1233:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1234:.\Generated_Source\PSoC5/CyLib.c **** * -1235:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1236:.\Generated_Source\PSoC5/CyLib.c **** * Returns status of the 32 KHz oscillator. -1237:.\Generated_Source\PSoC5/CyLib.c **** * -1238:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1239:.\Generated_Source\PSoC5/CyLib.c **** * None -1240:.\Generated_Source\PSoC5/CyLib.c **** * -1241:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1242:.\Generated_Source\PSoC5/CyLib.c **** * Value Define Source -1243:.\Generated_Source\PSoC5/CyLib.c **** * 20 CY_XTAL32K_ANA_STAT Analog measurement -1244:.\Generated_Source\PSoC5/CyLib.c **** * 1: Stable -1245:.\Generated_Source\PSoC5/CyLib.c **** * 0: Not stable -1246:.\Generated_Source\PSoC5/CyLib.c **** * -1247:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1248:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyXTAL_32KHZ_ReadStatus(void) -1249:.\Generated_Source\PSoC5/CyLib.c **** { - 1307 .loc 1 1249 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 48 - - - 1308 .cfi_startproc - 1309 @ args = 0, pretend = 0, frame = 0 - 1310 @ frame_needed = 0, uses_anonymous_args = 0 - 1311 @ link register save eliminated. -1250:.\Generated_Source\PSoC5/CyLib.c **** return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); - 1312 .loc 1 1250 0 - 1313 0000 024B ldr r3, .L164 - 1314 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 -1251:.\Generated_Source\PSoC5/CyLib.c **** } - 1315 .loc 1 1251 0 - 1316 0004 00F02000 and r0, r0, #32 - 1317 0008 7047 bx lr - 1318 .L165: - 1319 000a 00BF .align 2 - 1320 .L164: - 1321 000c 08430040 .word 1073758984 - 1322 .cfi_endproc - 1323 .LFE27: - 1324 .size CyXTAL_32KHZ_ReadStatus, .-CyXTAL_32KHZ_ReadStatus - 1325 .section .text.CyXTAL_Start,"ax",%progbits - 1326 .align 1 - 1327 .global CyXTAL_Start - 1328 .thumb - 1329 .thumb_func - 1330 .type CyXTAL_Start, %function - 1331 CyXTAL_Start: - 1332 .LFB29: -1252:.\Generated_Source\PSoC5/CyLib.c **** -1253:.\Generated_Source\PSoC5/CyLib.c **** -1254:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1255:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_32KHZ_SetPowerMode -1256:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1257:.\Generated_Source\PSoC5/CyLib.c **** * -1258:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1259:.\Generated_Source\PSoC5/CyLib.c **** * Sets the power mode for the 32 KHz oscillator used during sleep mode. -1260:.\Generated_Source\PSoC5/CyLib.c **** * Allows for lower power during sleep when there are fewer sources of noise. -1261:.\Generated_Source\PSoC5/CyLib.c **** * During active mode the oscillator is always run in high power mode. -1262:.\Generated_Source\PSoC5/CyLib.c **** * -1263:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1264:.\Generated_Source\PSoC5/CyLib.c **** * uint8 mode -1265:.\Generated_Source\PSoC5/CyLib.c **** * 0: High power mode -1266:.\Generated_Source\PSoC5/CyLib.c **** * 1: Low power mode during sleep -1267:.\Generated_Source\PSoC5/CyLib.c **** * -1268:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1269:.\Generated_Source\PSoC5/CyLib.c **** * Previous power mode. -1270:.\Generated_Source\PSoC5/CyLib.c **** * -1271:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1272:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) -1273:.\Generated_Source\PSoC5/CyLib.c **** { -1274:.\Generated_Source\PSoC5/CyLib.c **** uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; -1275:.\Generated_Source\PSoC5/CyLib.c **** -1276:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; -1277:.\Generated_Source\PSoC5/CyLib.c **** -1278:.\Generated_Source\PSoC5/CyLib.c **** if(1u == mode) -1279:.\Generated_Source\PSoC5/CyLib.c **** { -1280:.\Generated_Source\PSoC5/CyLib.c **** /* Low power mode during Sleep */ -1281:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 49 - - -1282:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(10u); -1283:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | -1284:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_LP_LOWPOWER; -1285:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(20u); -1286:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; -1287:.\Generated_Source\PSoC5/CyLib.c **** } -1288:.\Generated_Source\PSoC5/CyLib.c **** else -1289:.\Generated_Source\PSoC5/CyLib.c **** { -1290:.\Generated_Source\PSoC5/CyLib.c **** /* High power mode */ -1291:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; -1292:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(10u); -1293:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | -1294:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_LP_DEFAULT; -1295:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); -1296:.\Generated_Source\PSoC5/CyLib.c **** } -1297:.\Generated_Source\PSoC5/CyLib.c **** -1298:.\Generated_Source\PSoC5/CyLib.c **** return(state); -1299:.\Generated_Source\PSoC5/CyLib.c **** } -1300:.\Generated_Source\PSoC5/CyLib.c **** -1301:.\Generated_Source\PSoC5/CyLib.c **** -1302:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1303:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_Start -1304:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1305:.\Generated_Source\PSoC5/CyLib.c **** * -1306:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1307:.\Generated_Source\PSoC5/CyLib.c **** * Enables the megahertz crystal. -1308:.\Generated_Source\PSoC5/CyLib.c **** * -1309:.\Generated_Source\PSoC5/CyLib.c **** * PSoC 3: -1310:.\Generated_Source\PSoC5/CyLib.c **** * Waits until the XERR bit is low (no error) for a millisecond or until the -1311:.\Generated_Source\PSoC5/CyLib.c **** * number of milliseconds specified by the wait parameter has expired. -1312:.\Generated_Source\PSoC5/CyLib.c **** * -1313:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1314:.\Generated_Source\PSoC5/CyLib.c **** * wait: Valid range [0-255]. -1315:.\Generated_Source\PSoC5/CyLib.c **** * This is the timeout value in milliseconds. -1316:.\Generated_Source\PSoC5/CyLib.c **** * The appropriate value is crystal specific. -1317:.\Generated_Source\PSoC5/CyLib.c **** * -1318:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1319:.\Generated_Source\PSoC5/CyLib.c **** * CYRET_SUCCESS - Completed successfully -1320:.\Generated_Source\PSoC5/CyLib.c **** * CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. -1321:.\Generated_Source\PSoC5/CyLib.c **** * -1322:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects and Restrictions: -1323:.\Generated_Source\PSoC5/CyLib.c **** * If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. -1324:.\Generated_Source\PSoC5/CyLib.c **** * Any other use of the Fast Timewheel (FTW) will be stopped during the period -1325:.\Generated_Source\PSoC5/CyLib.c **** * of this function and then restored. -1326:.\Generated_Source\PSoC5/CyLib.c **** * -1327:.\Generated_Source\PSoC5/CyLib.c **** * Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz -1328:.\Generated_Source\PSoC5/CyLib.c **** * ILO for the period of this function. No changes to the setup of the ILO, -1329:.\Generated_Source\PSoC5/CyLib.c **** * Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made -1330:.\Generated_Source\PSoC5/CyLib.c **** * by interrupt routines during the period of this function. -1331:.\Generated_Source\PSoC5/CyLib.c **** * -1332:.\Generated_Source\PSoC5/CyLib.c **** * The current operation of the ILO, Central Timewheel and Once Per Second -1333:.\Generated_Source\PSoC5/CyLib.c **** * interrupt are maintained during the operation of this function provided the -1334:.\Generated_Source\PSoC5/CyLib.c **** * reading of the Power Manager Interrupt Status Register is only done using the -1335:.\Generated_Source\PSoC5/CyLib.c **** * CyPmReadStatus() function. -1336:.\Generated_Source\PSoC5/CyLib.c **** * -1337:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1338:.\Generated_Source\PSoC5/CyLib.c **** cystatus CyXTAL_Start(uint8 wait) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 50 - - -1339:.\Generated_Source\PSoC5/CyLib.c **** { - 1333 .loc 1 1339 0 - 1334 .cfi_startproc - 1335 @ args = 0, pretend = 0, frame = 8 - 1336 @ frame_needed = 0, uses_anonymous_args = 0 - 1337 .LVL80: - 1338 0000 F7B5 push {r0, r1, r2, r4, r5, r6, r7, lr} - 1339 .LCFI4: - 1340 .cfi_def_cfa_offset 32 - 1341 .cfi_offset 0, -32 - 1342 .cfi_offset 1, -28 - 1343 .cfi_offset 2, -24 - 1344 .cfi_offset 4, -20 - 1345 .cfi_offset 5, -16 - 1346 .cfi_offset 6, -12 - 1347 .cfi_offset 7, -8 - 1348 .cfi_offset 14, -4 -1340:.\Generated_Source\PSoC5/CyLib.c **** cystatus status = CYRET_SUCCESS; -1341:.\Generated_Source\PSoC5/CyLib.c **** volatile uint8 timeout = wait; -1342:.\Generated_Source\PSoC5/CyLib.c **** volatile uint8 count; -1343:.\Generated_Source\PSoC5/CyLib.c **** uint8 iloEnableState; -1344:.\Generated_Source\PSoC5/CyLib.c **** uint8 pmTwCfg0Tmp; -1345:.\Generated_Source\PSoC5/CyLib.c **** uint8 pmTwCfg2Tmp; -1346:.\Generated_Source\PSoC5/CyLib.c **** -1347:.\Generated_Source\PSoC5/CyLib.c **** -1348:.\Generated_Source\PSoC5/CyLib.c **** /* Enables the MHz crystal oscillator circuit */ -1349:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; - 1349 .loc 1 1349 0 - 1350 0002 1F4B ldr r3, .L184 -1341:.\Generated_Source\PSoC5/CyLib.c **** volatile uint8 timeout = wait; - 1351 .loc 1 1341 0 - 1352 0004 8DF80600 strb r0, [sp, #6] - 1353 .LVL81: - 1354 .loc 1 1349 0 - 1355 0008 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1356 000a 42F00101 orr r1, r2, #1 - 1357 000e 1970 strb r1, [r3, #0] -1350:.\Generated_Source\PSoC5/CyLib.c **** -1351:.\Generated_Source\PSoC5/CyLib.c **** -1352:.\Generated_Source\PSoC5/CyLib.c **** if(wait > 0u) - 1358 .loc 1 1352 0 - 1359 0010 98B3 cbz r0, .L174 -1353:.\Generated_Source\PSoC5/CyLib.c **** { -1354:.\Generated_Source\PSoC5/CyLib.c **** /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ -1355:.\Generated_Source\PSoC5/CyLib.c **** iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; -1356:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; -1357:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; -1358:.\Generated_Source\PSoC5/CyLib.c **** -1359:.\Generated_Source\PSoC5/CyLib.c **** /* Set 250 us interval */ -1360:.\Generated_Source\PSoC5/CyLib.c **** CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); - 1360 .loc 1 1360 0 - 1361 0012 1820 movs r0, #24 - 1362 .LVL82: -1355:.\Generated_Source\PSoC5/CyLib.c **** iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; - 1363 .loc 1 1355 0 - 1364 0014 93F8F070 ldrb r7, [r3, #240] @ zero_extendqisi2 - 1365 .LVL83: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 51 - - -1356:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; - 1366 .loc 1 1356 0 - 1367 0018 93F87061 ldrb r6, [r3, #368] @ zero_extendqisi2 - 1368 .LVL84: -1357:.\Generated_Source\PSoC5/CyLib.c **** pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; - 1369 .loc 1 1357 0 - 1370 001c 93F87251 ldrb r5, [r3, #370] @ zero_extendqisi2 - 1371 .LVL85: - 1372 .loc 1 1360 0 - 1373 0020 FFF7FEFF bl CyPmFtwSetInterval - 1374 .LVL86: - 1375 .L168: -1361:.\Generated_Source\PSoC5/CyLib.c **** status = CYRET_TIMEOUT; -1362:.\Generated_Source\PSoC5/CyLib.c **** -1363:.\Generated_Source\PSoC5/CyLib.c **** -1364:.\Generated_Source\PSoC5/CyLib.c **** for( ; timeout > 0u; timeout--) - 1376 .loc 1 1364 0 discriminator 1 - 1377 0024 9DF80600 ldrb r0, [sp, #6] @ zero_extendqisi2 - 1378 .LVL87: - 1379 0028 E0B1 cbz r0, .L182 - 1380 .L172: -1365:.\Generated_Source\PSoC5/CyLib.c **** { -1366:.\Generated_Source\PSoC5/CyLib.c **** /* Read XERR bit to clear it */ -1367:.\Generated_Source\PSoC5/CyLib.c **** (void) CY_CLK_XMHZ_CSR_REG; - 1381 .loc 1 1367 0 - 1382 002a 154C ldr r4, .L184 -1368:.\Generated_Source\PSoC5/CyLib.c **** -1369:.\Generated_Source\PSoC5/CyLib.c **** /* Wait for a millisecond - 4 x 250 us */ -1370:.\Generated_Source\PSoC5/CyLib.c **** for(count = 4u; count > 0u; count--) - 1383 .loc 1 1370 0 - 1384 002c 0420 movs r0, #4 - 1385 .LVL88: -1367:.\Generated_Source\PSoC5/CyLib.c **** (void) CY_CLK_XMHZ_CSR_REG; - 1386 .loc 1 1367 0 - 1387 002e 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1388 .L181: - 1389 .LVL89: - 1390 .loc 1 1370 0 - 1391 0030 8DF80700 strb r0, [sp, #7] - 1392 0034 9DF80740 ldrb r4, [sp, #7] @ zero_extendqisi2 - 1393 .LVL90: - 1394 0038 4CB1 cbz r4, .L183 - 1395 .LVL91: - 1396 .L178: -1371:.\Generated_Source\PSoC5/CyLib.c **** { -1372:.\Generated_Source\PSoC5/CyLib.c **** while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) - 1397 .loc 1 1372 0 - 1398 003a 0120 movs r0, #1 - 1399 003c FFF7FEFF bl CyPmReadStatus - 1400 .LVL92: - 1401 0040 C007 lsls r0, r0, #31 - 1402 0042 FAD5 bpl .L178 -1370:.\Generated_Source\PSoC5/CyLib.c **** for(count = 4u; count > 0u; count--) - 1403 .loc 1 1370 0 - 1404 0044 9DF80720 ldrb r2, [sp, #7] @ zero_extendqisi2 - 1405 .LVL93: - 1406 0048 511E subs r1, r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 52 - - - 1407 004a C8B2 uxtb r0, r1 - 1408 .LVL94: - 1409 004c F0E7 b .L181 - 1410 .L183: -1373:.\Generated_Source\PSoC5/CyLib.c **** { -1374:.\Generated_Source\PSoC5/CyLib.c **** /* Wait for the FTW interrupt event */ -1375:.\Generated_Source\PSoC5/CyLib.c **** } -1376:.\Generated_Source\PSoC5/CyLib.c **** } -1377:.\Generated_Source\PSoC5/CyLib.c **** -1378:.\Generated_Source\PSoC5/CyLib.c **** -1379:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************* -1380:.\Generated_Source\PSoC5/CyLib.c **** * High output indicates oscillator failure. -1381:.\Generated_Source\PSoC5/CyLib.c **** * Only can be used after start-up interval (1 ms) is completed. -1382:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************/ -1383:.\Generated_Source\PSoC5/CyLib.c **** if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) - 1411 .loc 1 1383 0 - 1412 004e 0C4B ldr r3, .L184 - 1413 0050 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1414 0052 1106 lsls r1, r2, #24 - 1415 0054 07D5 bpl .L171 -1364:.\Generated_Source\PSoC5/CyLib.c **** for( ; timeout > 0u; timeout--) - 1416 .loc 1 1364 0 - 1417 0056 9DF80610 ldrb r1, [sp, #6] @ zero_extendqisi2 - 1418 .LVL95: - 1419 005a 481E subs r0, r1, #1 - 1420 005c C4B2 uxtb r4, r0 - 1421 .LVL96: - 1422 005e 8DF80640 strb r4, [sp, #6] - 1423 0062 DFE7 b .L168 - 1424 .LVL97: - 1425 .L182: -1361:.\Generated_Source\PSoC5/CyLib.c **** status = CYRET_TIMEOUT; - 1426 .loc 1 1361 0 - 1427 0064 1024 movs r4, #16 - 1428 .L171: - 1429 .LVL98: -1384:.\Generated_Source\PSoC5/CyLib.c **** { -1385:.\Generated_Source\PSoC5/CyLib.c **** status = CYRET_SUCCESS; -1386:.\Generated_Source\PSoC5/CyLib.c **** break; -1387:.\Generated_Source\PSoC5/CyLib.c **** } -1388:.\Generated_Source\PSoC5/CyLib.c **** } -1389:.\Generated_Source\PSoC5/CyLib.c **** -1390:.\Generated_Source\PSoC5/CyLib.c **** -1391:.\Generated_Source\PSoC5/CyLib.c **** /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ -1392:.\Generated_Source\PSoC5/CyLib.c **** if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)) - 1430 .loc 1 1392 0 - 1431 0066 07F00407 and r7, r7, #4 - 1432 .LVL99: - 1433 006a FFB2 uxtb r7, r7 - 1434 006c 0FB9 cbnz r7, .L173 -1393:.\Generated_Source\PSoC5/CyLib.c **** { -1394:.\Generated_Source\PSoC5/CyLib.c **** CyILO_Stop100K(); - 1435 .loc 1 1394 0 - 1436 006e FFF7FEFF bl CyILO_Stop100K - 1437 .LVL100: - 1438 .L173: -1395:.\Generated_Source\PSoC5/CyLib.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 53 - - -1396:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; - 1439 .loc 1 1396 0 - 1440 0072 044B ldr r3, .L184+4 - 1441 0074 1E70 strb r6, [r3, #0] -1397:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp; - 1442 .loc 1 1397 0 - 1443 0076 9D70 strb r5, [r3, #2] - 1444 0078 00E0 b .L167 - 1445 .LVL101: - 1446 .L174: -1340:.\Generated_Source\PSoC5/CyLib.c **** cystatus status = CYRET_SUCCESS; - 1447 .loc 1 1340 0 - 1448 007a 0446 mov r4, r0 - 1449 .LVL102: - 1450 .L167: -1398:.\Generated_Source\PSoC5/CyLib.c **** } -1399:.\Generated_Source\PSoC5/CyLib.c **** -1400:.\Generated_Source\PSoC5/CyLib.c **** return(status); -1401:.\Generated_Source\PSoC5/CyLib.c **** } - 1451 .loc 1 1401 0 - 1452 007c 2046 mov r0, r4 - 1453 .LVL103: - 1454 007e FEBD pop {r1, r2, r3, r4, r5, r6, r7, pc} - 1455 .L185: - 1456 .align 2 - 1457 .L184: - 1458 0080 10420040 .word 1073758736 - 1459 0084 80430040 .word 1073759104 - 1460 .cfi_endproc - 1461 .LFE29: - 1462 .size CyXTAL_Start, .-CyXTAL_Start - 1463 .section .text.CyXTAL_Stop,"ax",%progbits - 1464 .align 1 - 1465 .global CyXTAL_Stop - 1466 .thumb - 1467 .thumb_func - 1468 .type CyXTAL_Stop, %function - 1469 CyXTAL_Stop: - 1470 .LFB30: -1402:.\Generated_Source\PSoC5/CyLib.c **** -1403:.\Generated_Source\PSoC5/CyLib.c **** -1404:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1405:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_Stop -1406:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1407:.\Generated_Source\PSoC5/CyLib.c **** * -1408:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1409:.\Generated_Source\PSoC5/CyLib.c **** * Disables the megahertz crystal oscillator. -1410:.\Generated_Source\PSoC5/CyLib.c **** * -1411:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1412:.\Generated_Source\PSoC5/CyLib.c **** * None -1413:.\Generated_Source\PSoC5/CyLib.c **** * -1414:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1415:.\Generated_Source\PSoC5/CyLib.c **** * None -1416:.\Generated_Source\PSoC5/CyLib.c **** * -1417:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1418:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_Stop(void) -1419:.\Generated_Source\PSoC5/CyLib.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 54 - - - 1471 .loc 1 1419 0 - 1472 .cfi_startproc - 1473 @ args = 0, pretend = 0, frame = 0 - 1474 @ frame_needed = 0, uses_anonymous_args = 0 - 1475 @ link register save eliminated. -1420:.\Generated_Source\PSoC5/CyLib.c **** /* Disable the the oscillator. */ -1421:.\Generated_Source\PSoC5/CyLib.c **** FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); - 1476 .loc 1 1421 0 - 1477 0000 024B ldr r3, .L187 - 1478 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1479 0004 02F0FE00 and r0, r2, #254 - 1480 0008 1870 strb r0, [r3, #0] - 1481 000a 7047 bx lr - 1482 .L188: - 1483 .align 2 - 1484 .L187: - 1485 000c 10420040 .word 1073758736 - 1486 .cfi_endproc - 1487 .LFE30: - 1488 .size CyXTAL_Stop, .-CyXTAL_Stop - 1489 .section .text.CyXTAL_EnableErrStatus,"ax",%progbits - 1490 .align 1 - 1491 .global CyXTAL_EnableErrStatus - 1492 .thumb - 1493 .thumb_func - 1494 .type CyXTAL_EnableErrStatus, %function - 1495 CyXTAL_EnableErrStatus: - 1496 .LFB31: -1422:.\Generated_Source\PSoC5/CyLib.c **** } -1423:.\Generated_Source\PSoC5/CyLib.c **** -1424:.\Generated_Source\PSoC5/CyLib.c **** -1425:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1426:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_EnableErrStatus -1427:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1428:.\Generated_Source\PSoC5/CyLib.c **** * -1429:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1430:.\Generated_Source\PSoC5/CyLib.c **** * Enables the generation of the XERR status bit for the megahertz crystal. -1431:.\Generated_Source\PSoC5/CyLib.c **** * This function is not available for PSoC5. -1432:.\Generated_Source\PSoC5/CyLib.c **** * -1433:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1434:.\Generated_Source\PSoC5/CyLib.c **** * None -1435:.\Generated_Source\PSoC5/CyLib.c **** * -1436:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1437:.\Generated_Source\PSoC5/CyLib.c **** * None -1438:.\Generated_Source\PSoC5/CyLib.c **** * -1439:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1440:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_EnableErrStatus(void) -1441:.\Generated_Source\PSoC5/CyLib.c **** { - 1497 .loc 1 1441 0 - 1498 .cfi_startproc - 1499 @ args = 0, pretend = 0, frame = 0 - 1500 @ frame_needed = 0, uses_anonymous_args = 0 - 1501 @ link register save eliminated. -1442:.\Generated_Source\PSoC5/CyLib.c **** /* If oscillator has insufficient amplitude, XERR bit will be high. */ -1443:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); - 1502 .loc 1 1443 0 - 1503 0000 024B ldr r3, .L190 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 55 - - - 1504 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1505 0004 02F0FB00 and r0, r2, #251 - 1506 0008 1870 strb r0, [r3, #0] - 1507 000a 7047 bx lr - 1508 .L191: - 1509 .align 2 - 1510 .L190: - 1511 000c 10420040 .word 1073758736 - 1512 .cfi_endproc - 1513 .LFE31: - 1514 .size CyXTAL_EnableErrStatus, .-CyXTAL_EnableErrStatus - 1515 .section .text.CyXTAL_DisableErrStatus,"ax",%progbits - 1516 .align 1 - 1517 .global CyXTAL_DisableErrStatus - 1518 .thumb - 1519 .thumb_func - 1520 .type CyXTAL_DisableErrStatus, %function - 1521 CyXTAL_DisableErrStatus: - 1522 .LFB32: -1444:.\Generated_Source\PSoC5/CyLib.c **** } -1445:.\Generated_Source\PSoC5/CyLib.c **** -1446:.\Generated_Source\PSoC5/CyLib.c **** -1447:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1448:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_DisableErrStatus -1449:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1450:.\Generated_Source\PSoC5/CyLib.c **** * -1451:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1452:.\Generated_Source\PSoC5/CyLib.c **** * Disables the generation of the XERR status bit for the megahertz crystal. -1453:.\Generated_Source\PSoC5/CyLib.c **** * This function is not available for PSoC5. -1454:.\Generated_Source\PSoC5/CyLib.c **** * -1455:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1456:.\Generated_Source\PSoC5/CyLib.c **** * None -1457:.\Generated_Source\PSoC5/CyLib.c **** * -1458:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1459:.\Generated_Source\PSoC5/CyLib.c **** * None -1460:.\Generated_Source\PSoC5/CyLib.c **** * -1461:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1462:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_DisableErrStatus(void) -1463:.\Generated_Source\PSoC5/CyLib.c **** { - 1523 .loc 1 1463 0 - 1524 .cfi_startproc - 1525 @ args = 0, pretend = 0, frame = 0 - 1526 @ frame_needed = 0, uses_anonymous_args = 0 - 1527 @ link register save eliminated. -1464:.\Generated_Source\PSoC5/CyLib.c **** /* If oscillator has insufficient amplitude, XERR bit will be high. */ -1465:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; - 1528 .loc 1 1465 0 - 1529 0000 024B ldr r3, .L193 - 1530 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1531 0004 42F00400 orr r0, r2, #4 - 1532 0008 1870 strb r0, [r3, #0] - 1533 000a 7047 bx lr - 1534 .L194: - 1535 .align 2 - 1536 .L193: - 1537 000c 10420040 .word 1073758736 - 1538 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 56 - - - 1539 .LFE32: - 1540 .size CyXTAL_DisableErrStatus, .-CyXTAL_DisableErrStatus - 1541 .section .text.CyXTAL_ReadStatus,"ax",%progbits - 1542 .align 1 - 1543 .global CyXTAL_ReadStatus - 1544 .thumb - 1545 .thumb_func - 1546 .type CyXTAL_ReadStatus, %function - 1547 CyXTAL_ReadStatus: - 1548 .LFB33: -1466:.\Generated_Source\PSoC5/CyLib.c **** } -1467:.\Generated_Source\PSoC5/CyLib.c **** -1468:.\Generated_Source\PSoC5/CyLib.c **** -1469:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1470:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_ReadStatus -1471:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1472:.\Generated_Source\PSoC5/CyLib.c **** * -1473:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1474:.\Generated_Source\PSoC5/CyLib.c **** * Reads the XERR status bit for the megahertz crystal. This status bit is a -1475:.\Generated_Source\PSoC5/CyLib.c **** * sticky clear on read value. This function is not available for PSoC5. -1476:.\Generated_Source\PSoC5/CyLib.c **** * -1477:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1478:.\Generated_Source\PSoC5/CyLib.c **** * None -1479:.\Generated_Source\PSoC5/CyLib.c **** * -1480:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1481:.\Generated_Source\PSoC5/CyLib.c **** * Status -1482:.\Generated_Source\PSoC5/CyLib.c **** * 0: No error -1483:.\Generated_Source\PSoC5/CyLib.c **** * 1: Error -1484:.\Generated_Source\PSoC5/CyLib.c **** * -1485:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1486:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyXTAL_ReadStatus(void) -1487:.\Generated_Source\PSoC5/CyLib.c **** { - 1549 .loc 1 1487 0 - 1550 .cfi_startproc - 1551 @ args = 0, pretend = 0, frame = 0 - 1552 @ frame_needed = 0, uses_anonymous_args = 0 - 1553 @ link register save eliminated. -1488:.\Generated_Source\PSoC5/CyLib.c **** /*************************************************************************** -1489:.\Generated_Source\PSoC5/CyLib.c **** * High output indicates oscillator failure. Only use this after start-up -1490:.\Generated_Source\PSoC5/CyLib.c **** * interval is completed. This can be used for status and failure recovery. -1491:.\Generated_Source\PSoC5/CyLib.c **** ***************************************************************************/ -1492:.\Generated_Source\PSoC5/CyLib.c **** return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); - 1554 .loc 1 1492 0 - 1555 0000 014B ldr r3, .L196 - 1556 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 -1493:.\Generated_Source\PSoC5/CyLib.c **** } - 1557 .loc 1 1493 0 - 1558 0004 C009 lsrs r0, r0, #7 - 1559 0006 7047 bx lr - 1560 .L197: - 1561 .align 2 - 1562 .L196: - 1563 0008 10420040 .word 1073758736 - 1564 .cfi_endproc - 1565 .LFE33: - 1566 .size CyXTAL_ReadStatus, .-CyXTAL_ReadStatus - 1567 .section .text.CyXTAL_EnableFaultRecovery,"ax",%progbits - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 57 - - - 1568 .align 1 - 1569 .global CyXTAL_EnableFaultRecovery - 1570 .thumb - 1571 .thumb_func - 1572 .type CyXTAL_EnableFaultRecovery, %function - 1573 CyXTAL_EnableFaultRecovery: - 1574 .LFB34: -1494:.\Generated_Source\PSoC5/CyLib.c **** -1495:.\Generated_Source\PSoC5/CyLib.c **** -1496:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1497:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_EnableFaultRecovery -1498:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1499:.\Generated_Source\PSoC5/CyLib.c **** * -1500:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1501:.\Generated_Source\PSoC5/CyLib.c **** * Enables the fault recovery circuit which will switch to the IMO in the case -1502:.\Generated_Source\PSoC5/CyLib.c **** * of a fault in the megahertz crystal circuit. The crystal must be up and -1503:.\Generated_Source\PSoC5/CyLib.c **** * running with the XERR bit at 0, before calling this function to prevent -1504:.\Generated_Source\PSoC5/CyLib.c **** * immediate fault switchover. This function is not available for PSoC5. -1505:.\Generated_Source\PSoC5/CyLib.c **** * -1506:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1507:.\Generated_Source\PSoC5/CyLib.c **** * None -1508:.\Generated_Source\PSoC5/CyLib.c **** * -1509:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1510:.\Generated_Source\PSoC5/CyLib.c **** * None -1511:.\Generated_Source\PSoC5/CyLib.c **** * -1512:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1513:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_EnableFaultRecovery(void) -1514:.\Generated_Source\PSoC5/CyLib.c **** { - 1575 .loc 1 1514 0 - 1576 .cfi_startproc - 1577 @ args = 0, pretend = 0, frame = 0 - 1578 @ frame_needed = 0, uses_anonymous_args = 0 - 1579 @ link register save eliminated. -1515:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; - 1580 .loc 1 1515 0 - 1581 0000 024B ldr r3, .L199 - 1582 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1583 0004 42F04000 orr r0, r2, #64 - 1584 0008 1870 strb r0, [r3, #0] - 1585 000a 7047 bx lr - 1586 .L200: - 1587 .align 2 - 1588 .L199: - 1589 000c 10420040 .word 1073758736 - 1590 .cfi_endproc - 1591 .LFE34: - 1592 .size CyXTAL_EnableFaultRecovery, .-CyXTAL_EnableFaultRecovery - 1593 .section .text.CyXTAL_DisableFaultRecovery,"ax",%progbits - 1594 .align 1 - 1595 .global CyXTAL_DisableFaultRecovery - 1596 .thumb - 1597 .thumb_func - 1598 .type CyXTAL_DisableFaultRecovery, %function - 1599 CyXTAL_DisableFaultRecovery: - 1600 .LFB35: -1516:.\Generated_Source\PSoC5/CyLib.c **** } -1517:.\Generated_Source\PSoC5/CyLib.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 58 - - -1518:.\Generated_Source\PSoC5/CyLib.c **** -1519:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1520:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_DisableFaultRecovery -1521:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1522:.\Generated_Source\PSoC5/CyLib.c **** * -1523:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1524:.\Generated_Source\PSoC5/CyLib.c **** * Disables the fault recovery circuit which will switch to the IMO in the case -1525:.\Generated_Source\PSoC5/CyLib.c **** * of a fault in the megahertz crystal circuit. This function is not available -1526:.\Generated_Source\PSoC5/CyLib.c **** * for PSoC5. -1527:.\Generated_Source\PSoC5/CyLib.c **** * -1528:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1529:.\Generated_Source\PSoC5/CyLib.c **** * None -1530:.\Generated_Source\PSoC5/CyLib.c **** * -1531:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1532:.\Generated_Source\PSoC5/CyLib.c **** * None -1533:.\Generated_Source\PSoC5/CyLib.c **** * -1534:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1535:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_DisableFaultRecovery(void) -1536:.\Generated_Source\PSoC5/CyLib.c **** { - 1601 .loc 1 1536 0 - 1602 .cfi_startproc - 1603 @ args = 0, pretend = 0, frame = 0 - 1604 @ frame_needed = 0, uses_anonymous_args = 0 - 1605 @ link register save eliminated. -1537:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); - 1606 .loc 1 1537 0 - 1607 0000 024B ldr r3, .L202 - 1608 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1609 0004 02F0BF00 and r0, r2, #191 - 1610 0008 1870 strb r0, [r3, #0] - 1611 000a 7047 bx lr - 1612 .L203: - 1613 .align 2 - 1614 .L202: - 1615 000c 10420040 .word 1073758736 - 1616 .cfi_endproc - 1617 .LFE35: - 1618 .size CyXTAL_DisableFaultRecovery, .-CyXTAL_DisableFaultRecovery - 1619 .section .text.CyXTAL_SetStartup,"ax",%progbits - 1620 .align 1 - 1621 .global CyXTAL_SetStartup - 1622 .thumb - 1623 .thumb_func - 1624 .type CyXTAL_SetStartup, %function - 1625 CyXTAL_SetStartup: - 1626 .LFB36: -1538:.\Generated_Source\PSoC5/CyLib.c **** } -1539:.\Generated_Source\PSoC5/CyLib.c **** -1540:.\Generated_Source\PSoC5/CyLib.c **** -1541:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1542:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_SetStartup -1543:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1544:.\Generated_Source\PSoC5/CyLib.c **** * -1545:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1546:.\Generated_Source\PSoC5/CyLib.c **** * Sets the startup settings for the crystal. Logic model outputs a frequency -1547:.\Generated_Source\PSoC5/CyLib.c **** * (setting + 4) MHz when enabled. -1548:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 59 - - -1549:.\Generated_Source\PSoC5/CyLib.c **** * This is artificial as the actual frequency is determined by an attached -1550:.\Generated_Source\PSoC5/CyLib.c **** * external crystal. -1551:.\Generated_Source\PSoC5/CyLib.c **** * -1552:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1553:.\Generated_Source\PSoC5/CyLib.c **** * setting: Valid range [0-31]. -1554:.\Generated_Source\PSoC5/CyLib.c **** * Value is dependent on the frequency and quality of the crystal being used. -1555:.\Generated_Source\PSoC5/CyLib.c **** * Refer to the device TRM and datasheet for more information. -1556:.\Generated_Source\PSoC5/CyLib.c **** * -1557:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1558:.\Generated_Source\PSoC5/CyLib.c **** * None -1559:.\Generated_Source\PSoC5/CyLib.c **** * -1560:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1561:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_SetStartup(uint8 setting) -1562:.\Generated_Source\PSoC5/CyLib.c **** { - 1627 .loc 1 1562 0 - 1628 .cfi_startproc - 1629 @ args = 0, pretend = 0, frame = 0 - 1630 @ frame_needed = 0, uses_anonymous_args = 0 - 1631 @ link register save eliminated. - 1632 .LVL104: -1563:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | - 1633 .loc 1 1563 0 - 1634 0000 044B ldr r3, .L205 - 1635 0002 00F01F00 and r0, r0, #31 - 1636 .LVL105: - 1637 0006 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1638 0008 02F0E001 and r1, r2, #224 - 1639 000c 40EA0102 orr r2, r0, r1 - 1640 0010 1A70 strb r2, [r3, #0] - 1641 0012 7047 bx lr - 1642 .L206: - 1643 .align 2 - 1644 .L205: - 1645 0014 12420040 .word 1073758738 - 1646 .cfi_endproc - 1647 .LFE36: - 1648 .size CyXTAL_SetStartup, .-CyXTAL_SetStartup - 1649 .section .text.CyXTAL_SetFbVoltage,"ax",%progbits - 1650 .align 1 - 1651 .global CyXTAL_SetFbVoltage - 1652 .thumb - 1653 .thumb_func - 1654 .type CyXTAL_SetFbVoltage, %function - 1655 CyXTAL_SetFbVoltage: - 1656 .LFB37: -1564:.\Generated_Source\PSoC5/CyLib.c **** (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); -1565:.\Generated_Source\PSoC5/CyLib.c **** } -1566:.\Generated_Source\PSoC5/CyLib.c **** -1567:.\Generated_Source\PSoC5/CyLib.c **** -1568:.\Generated_Source\PSoC5/CyLib.c **** -1569:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1570:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_SetFbVoltage -1571:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1572:.\Generated_Source\PSoC5/CyLib.c **** * -1573:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1574:.\Generated_Source\PSoC5/CyLib.c **** * Sets the feedback reference voltage to use for the crystal circuit. -1575:.\Generated_Source\PSoC5/CyLib.c **** * This function is only available for PSoC3 and PSoC 5LP. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 60 - - -1576:.\Generated_Source\PSoC5/CyLib.c **** * -1577:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1578:.\Generated_Source\PSoC5/CyLib.c **** * setting: Valid range [0-15]. -1579:.\Generated_Source\PSoC5/CyLib.c **** * Refer to the device TRM and datasheet for more information. -1580:.\Generated_Source\PSoC5/CyLib.c **** * -1581:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1582:.\Generated_Source\PSoC5/CyLib.c **** * None -1583:.\Generated_Source\PSoC5/CyLib.c **** * -1584:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1585:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_SetFbVoltage(uint8 setting) -1586:.\Generated_Source\PSoC5/CyLib.c **** { - 1657 .loc 1 1586 0 - 1658 .cfi_startproc - 1659 @ args = 0, pretend = 0, frame = 0 - 1660 @ frame_needed = 0, uses_anonymous_args = 0 - 1661 @ link register save eliminated. - 1662 .LVL106: -1587:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | - 1663 .loc 1 1587 0 - 1664 0000 044B ldr r3, .L208 - 1665 0002 00F00F00 and r0, r0, #15 - 1666 .LVL107: - 1667 0006 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1668 0008 02F0F001 and r1, r2, #240 - 1669 000c 40EA0102 orr r2, r0, r1 - 1670 0010 1A70 strb r2, [r3, #0] - 1671 0012 7047 bx lr - 1672 .L209: - 1673 .align 2 - 1674 .L208: - 1675 0014 13420040 .word 1073758739 - 1676 .cfi_endproc - 1677 .LFE37: - 1678 .size CyXTAL_SetFbVoltage, .-CyXTAL_SetFbVoltage - 1679 .section .text.CyXTAL_SetWdVoltage,"ax",%progbits - 1680 .align 1 - 1681 .global CyXTAL_SetWdVoltage - 1682 .thumb - 1683 .thumb_func - 1684 .type CyXTAL_SetWdVoltage, %function - 1685 CyXTAL_SetWdVoltage: - 1686 .LFB38: -1588:.\Generated_Source\PSoC5/CyLib.c **** (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); -1589:.\Generated_Source\PSoC5/CyLib.c **** } -1590:.\Generated_Source\PSoC5/CyLib.c **** -1591:.\Generated_Source\PSoC5/CyLib.c **** -1592:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1593:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyXTAL_SetWdVoltage -1594:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1595:.\Generated_Source\PSoC5/CyLib.c **** * -1596:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1597:.\Generated_Source\PSoC5/CyLib.c **** * Sets the reference voltage used by the watchdog to detect a failure in the -1598:.\Generated_Source\PSoC5/CyLib.c **** * crystal circuit. This function is only available for PSoC3 and PSoC 5LP. -1599:.\Generated_Source\PSoC5/CyLib.c **** * -1600:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1601:.\Generated_Source\PSoC5/CyLib.c **** * setting: Valid range [0-7]. -1602:.\Generated_Source\PSoC5/CyLib.c **** * Refer to the device TRM and datasheet for more information. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 61 - - -1603:.\Generated_Source\PSoC5/CyLib.c **** * -1604:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1605:.\Generated_Source\PSoC5/CyLib.c **** * None -1606:.\Generated_Source\PSoC5/CyLib.c **** * -1607:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1608:.\Generated_Source\PSoC5/CyLib.c **** void CyXTAL_SetWdVoltage(uint8 setting) -1609:.\Generated_Source\PSoC5/CyLib.c **** { - 1687 .loc 1 1609 0 - 1688 .cfi_startproc - 1689 @ args = 0, pretend = 0, frame = 0 - 1690 @ frame_needed = 0, uses_anonymous_args = 0 - 1691 @ link register save eliminated. - 1692 .LVL108: -1610:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | - 1693 .loc 1 1610 0 - 1694 0000 054B ldr r3, .L211 -1611:.\Generated_Source\PSoC5/CyLib.c **** (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); - 1695 .loc 1 1611 0 - 1696 0002 0001 lsls r0, r0, #4 - 1697 .LVL109: -1610:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | - 1698 .loc 1 1610 0 - 1699 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1700 0006 00F07001 and r1, r0, #112 - 1701 000a 02F08F02 and r2, r2, #143 - 1702 000e 41EA0200 orr r0, r1, r2 - 1703 0012 1870 strb r0, [r3, #0] - 1704 0014 7047 bx lr - 1705 .L212: - 1706 0016 00BF .align 2 - 1707 .L211: - 1708 0018 13420040 .word 1073758739 - 1709 .cfi_endproc - 1710 .LFE38: - 1711 .size CyXTAL_SetWdVoltage, .-CyXTAL_SetWdVoltage - 1712 .section .text.CyHalt,"ax",%progbits - 1713 .align 1 - 1714 .global CyHalt - 1715 .thumb - 1716 .thumb_func - 1717 .type CyHalt, %function - 1718 CyHalt: - 1719 .LFB39: -1612:.\Generated_Source\PSoC5/CyLib.c **** } -1613:.\Generated_Source\PSoC5/CyLib.c **** -1614:.\Generated_Source\PSoC5/CyLib.c **** -1615:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1616:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyHalt -1617:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1618:.\Generated_Source\PSoC5/CyLib.c **** * -1619:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1620:.\Generated_Source\PSoC5/CyLib.c **** * Halts the CPU. -1621:.\Generated_Source\PSoC5/CyLib.c **** * -1622:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1623:.\Generated_Source\PSoC5/CyLib.c **** * uint8 reason: Value to be used during debugging. -1624:.\Generated_Source\PSoC5/CyLib.c **** * -1625:.\Generated_Source\PSoC5/CyLib.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 62 - - -1626:.\Generated_Source\PSoC5/CyLib.c **** * None -1627:.\Generated_Source\PSoC5/CyLib.c **** * -1628:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1629:.\Generated_Source\PSoC5/CyLib.c **** void CyHalt(uint8 reason) CYREENTRANT -1630:.\Generated_Source\PSoC5/CyLib.c **** { - 1720 .loc 1 1630 0 - 1721 .cfi_startproc - 1722 @ args = 0, pretend = 0, frame = 0 - 1723 @ frame_needed = 0, uses_anonymous_args = 0 - 1724 @ link register save eliminated. - 1725 .LVL110: -1631:.\Generated_Source\PSoC5/CyLib.c **** if(0u != reason) -1632:.\Generated_Source\PSoC5/CyLib.c **** { -1633:.\Generated_Source\PSoC5/CyLib.c **** /* To remove unreferenced local variable warning */ -1634:.\Generated_Source\PSoC5/CyLib.c **** } -1635:.\Generated_Source\PSoC5/CyLib.c **** -1636:.\Generated_Source\PSoC5/CyLib.c **** #if defined (__ARMCC_VERSION) -1637:.\Generated_Source\PSoC5/CyLib.c **** __breakpoint(0x0); -1638:.\Generated_Source\PSoC5/CyLib.c **** #elif defined(__GNUC__) || defined (__ICCARM__) -1639:.\Generated_Source\PSoC5/CyLib.c **** __asm(" bkpt 1"); - 1726 .loc 1 1639 0 - 1727 @ 1639 ".\Generated_Source\PSoC5\CyLib.c" 1 - 1728 0000 01BE bkpt 1 - 1729 @ 0 "" 2 - 1730 .thumb - 1731 0002 7047 bx lr - 1732 .cfi_endproc - 1733 .LFE39: - 1734 .size CyHalt, .-CyHalt - 1735 .section .text.CySoftwareReset,"ax",%progbits - 1736 .align 1 - 1737 .global CySoftwareReset - 1738 .thumb - 1739 .thumb_func - 1740 .type CySoftwareReset, %function - 1741 CySoftwareReset: - 1742 .LFB40: -1640:.\Generated_Source\PSoC5/CyLib.c **** #elif defined(__C51__) -1641:.\Generated_Source\PSoC5/CyLib.c **** CYDEV_HALT_CPU; -1642:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (__ARMCC_VERSION) */ -1643:.\Generated_Source\PSoC5/CyLib.c **** } -1644:.\Generated_Source\PSoC5/CyLib.c **** -1645:.\Generated_Source\PSoC5/CyLib.c **** -1646:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1647:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CySoftwareReset -1648:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1649:.\Generated_Source\PSoC5/CyLib.c **** * -1650:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1651:.\Generated_Source\PSoC5/CyLib.c **** * Forces a software reset of the device. -1652:.\Generated_Source\PSoC5/CyLib.c **** * -1653:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1654:.\Generated_Source\PSoC5/CyLib.c **** * None -1655:.\Generated_Source\PSoC5/CyLib.c **** * -1656:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1657:.\Generated_Source\PSoC5/CyLib.c **** * None -1658:.\Generated_Source\PSoC5/CyLib.c **** * -1659:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 63 - - -1660:.\Generated_Source\PSoC5/CyLib.c **** void CySoftwareReset(void) -1661:.\Generated_Source\PSoC5/CyLib.c **** { - 1743 .loc 1 1661 0 - 1744 .cfi_startproc - 1745 @ args = 0, pretend = 0, frame = 0 - 1746 @ frame_needed = 0, uses_anonymous_args = 0 - 1747 @ link register save eliminated. -1662:.\Generated_Source\PSoC5/CyLib.c **** CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET; - 1748 .loc 1 1662 0 - 1749 0000 024B ldr r3, .L215 - 1750 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1751 0004 42F00100 orr r0, r2, #1 - 1752 0008 1870 strb r0, [r3, #0] - 1753 000a 7047 bx lr - 1754 .L216: - 1755 .align 2 - 1756 .L215: - 1757 000c F6460040 .word 1073759990 - 1758 .cfi_endproc - 1759 .LFE40: - 1760 .size CySoftwareReset, .-CySoftwareReset - 1761 .section .text.CyDelay,"ax",%progbits - 1762 .align 1 - 1763 .global CyDelay - 1764 .thumb - 1765 .thumb_func - 1766 .type CyDelay, %function - 1767 CyDelay: - 1768 .LFB41: -1663:.\Generated_Source\PSoC5/CyLib.c **** } -1664:.\Generated_Source\PSoC5/CyLib.c **** -1665:.\Generated_Source\PSoC5/CyLib.c **** -1666:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1667:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyDelay -1668:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1669:.\Generated_Source\PSoC5/CyLib.c **** * -1670:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1671:.\Generated_Source\PSoC5/CyLib.c **** * Blocks for milliseconds. -1672:.\Generated_Source\PSoC5/CyLib.c **** * -1673:.\Generated_Source\PSoC5/CyLib.c **** * Note: -1674:.\Generated_Source\PSoC5/CyLib.c **** * CyDelay has been implemented with the instruction cache assumed enabled. When -1675:.\Generated_Source\PSoC5/CyLib.c **** * instruction cache is disabled on PSoC5, CyDelay will be two times larger. For -1676:.\Generated_Source\PSoC5/CyLib.c **** * example, with instruction cache disabled CyDelay(100) would result in about -1677:.\Generated_Source\PSoC5/CyLib.c **** * 200 ms delay instead of 100 ms. -1678:.\Generated_Source\PSoC5/CyLib.c **** * -1679:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1680:.\Generated_Source\PSoC5/CyLib.c **** * milliseconds: number of milliseconds to delay. -1681:.\Generated_Source\PSoC5/CyLib.c **** * -1682:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1683:.\Generated_Source\PSoC5/CyLib.c **** * None -1684:.\Generated_Source\PSoC5/CyLib.c **** * -1685:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1686:.\Generated_Source\PSoC5/CyLib.c **** void CyDelay(uint32 milliseconds) CYREENTRANT -1687:.\Generated_Source\PSoC5/CyLib.c **** { - 1769 .loc 1 1687 0 - 1770 .cfi_startproc - 1771 @ args = 0, pretend = 0, frame = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 64 - - - 1772 @ frame_needed = 0, uses_anonymous_args = 0 - 1773 .LVL111: - 1774 0000 10B5 push {r4, lr} - 1775 .LCFI5: - 1776 .cfi_def_cfa_offset 8 - 1777 .cfi_offset 4, -8 - 1778 .cfi_offset 14, -4 - 1779 0002 0446 mov r4, r0 - 1780 .LVL112: - 1781 .L218: -1688:.\Generated_Source\PSoC5/CyLib.c **** while (milliseconds > 32768u) - 1782 .loc 1 1688 0 discriminator 1 - 1783 0004 B4F5004F cmp r4, #32768 - 1784 0008 064B ldr r3, .L221 - 1785 000a 05D9 bls .L220 - 1786 .L219: -1689:.\Generated_Source\PSoC5/CyLib.c **** { -1690:.\Generated_Source\PSoC5/CyLib.c **** /*********************************************************************** -1691:.\Generated_Source\PSoC5/CyLib.c **** * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz -1692:.\Generated_Source\PSoC5/CyLib.c **** * overflows at about 42 seconds. -1693:.\Generated_Source\PSoC5/CyLib.c **** ***********************************************************************/ -1694:.\Generated_Source\PSoC5/CyLib.c **** CyDelayCycles(cydelay_32k_ms); - 1787 .loc 1 1694 0 - 1788 000c 1868 ldr r0, [r3, #0] - 1789 000e FFF7FEFF bl CyDelayCycles - 1790 .LVL113: -1695:.\Generated_Source\PSoC5/CyLib.c **** milliseconds = ((uint32)(milliseconds - 32768u)); - 1791 .loc 1 1695 0 - 1792 0012 A4F50044 sub r4, r4, #32768 - 1793 .LVL114: - 1794 0016 F5E7 b .L218 - 1795 .L220: -1696:.\Generated_Source\PSoC5/CyLib.c **** } -1697:.\Generated_Source\PSoC5/CyLib.c **** -1698:.\Generated_Source\PSoC5/CyLib.c **** CyDelayCycles(milliseconds * cydelay_freq_khz); - 1796 .loc 1 1698 0 - 1797 0018 5868 ldr r0, [r3, #4] - 1798 001a 6043 muls r0, r4, r0 -1699:.\Generated_Source\PSoC5/CyLib.c **** } - 1799 .loc 1 1699 0 - 1800 001c BDE81040 pop {r4, lr} -1698:.\Generated_Source\PSoC5/CyLib.c **** CyDelayCycles(milliseconds * cydelay_freq_khz); - 1801 .loc 1 1698 0 - 1802 0020 FFF7FEBF b CyDelayCycles - 1803 .LVL115: - 1804 .L222: - 1805 .align 2 - 1806 .L221: - 1807 0024 00000000 .word .LANCHOR0 - 1808 .cfi_endproc - 1809 .LFE41: - 1810 .size CyDelay, .-CyDelay - 1811 .section .text.CyDelayUs,"ax",%progbits - 1812 .align 1 - 1813 .global CyDelayUs - 1814 .thumb - 1815 .thumb_func - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 65 - - - 1816 .type CyDelayUs, %function - 1817 CyDelayUs: - 1818 .LFB42: -1700:.\Generated_Source\PSoC5/CyLib.c **** -1701:.\Generated_Source\PSoC5/CyLib.c **** -1702:.\Generated_Source\PSoC5/CyLib.c **** #if(!CY_PSOC3) -1703:.\Generated_Source\PSoC5/CyLib.c **** -1704:.\Generated_Source\PSoC5/CyLib.c **** /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ -1705:.\Generated_Source\PSoC5/CyLib.c **** -1706:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1707:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyDelayUs -1708:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1709:.\Generated_Source\PSoC5/CyLib.c **** * -1710:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1711:.\Generated_Source\PSoC5/CyLib.c **** * Blocks for microseconds. -1712:.\Generated_Source\PSoC5/CyLib.c **** * -1713:.\Generated_Source\PSoC5/CyLib.c **** * Note: -1714:.\Generated_Source\PSoC5/CyLib.c **** * CyDelay has been implemented with the instruction cache assumed enabled. -1715:.\Generated_Source\PSoC5/CyLib.c **** * When instruction cache is disabled on PSoC5, CyDelayUs will be two times -1716:.\Generated_Source\PSoC5/CyLib.c **** * larger. Ex: With instruction cache disabled CyDelayUs(100) would result -1717:.\Generated_Source\PSoC5/CyLib.c **** * in about 200us delay instead of 100us. -1718:.\Generated_Source\PSoC5/CyLib.c **** * -1719:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1720:.\Generated_Source\PSoC5/CyLib.c **** * uint16 microseconds: number of microseconds to delay. -1721:.\Generated_Source\PSoC5/CyLib.c **** * -1722:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1723:.\Generated_Source\PSoC5/CyLib.c **** * None -1724:.\Generated_Source\PSoC5/CyLib.c **** * -1725:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: -1726:.\Generated_Source\PSoC5/CyLib.c **** * CyDelayUS has been implemented with the instruction cache assumed enabled. -1727:.\Generated_Source\PSoC5/CyLib.c **** * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times -1728:.\Generated_Source\PSoC5/CyLib.c **** * larger. For example, with instruction cache disabled CyDelayUs(100) would -1729:.\Generated_Source\PSoC5/CyLib.c **** * result in about 200 us delay instead of 100 us. -1730:.\Generated_Source\PSoC5/CyLib.c **** * -1731:.\Generated_Source\PSoC5/CyLib.c **** * If the bus clock frequency is a small non-integer number, the actual delay -1732:.\Generated_Source\PSoC5/CyLib.c **** * can be up to twice as long as the nominal value. The actual delay cannot be -1733:.\Generated_Source\PSoC5/CyLib.c **** * shorter than the nominal one. -1734:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1735:.\Generated_Source\PSoC5/CyLib.c **** void CyDelayUs(uint16 microseconds) CYREENTRANT -1736:.\Generated_Source\PSoC5/CyLib.c **** { - 1819 .loc 1 1736 0 - 1820 .cfi_startproc - 1821 @ args = 0, pretend = 0, frame = 0 - 1822 @ frame_needed = 0, uses_anonymous_args = 0 - 1823 @ link register save eliminated. - 1824 .LVL116: -1737:.\Generated_Source\PSoC5/CyLib.c **** CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); - 1825 .loc 1 1737 0 - 1826 0000 024B ldr r3, .L224 - 1827 0002 197A ldrb r1, [r3, #8] @ zero_extendqisi2 - 1828 0004 4843 muls r0, r1, r0 - 1829 .LVL117: -1738:.\Generated_Source\PSoC5/CyLib.c **** } - 1830 .loc 1 1738 0 -1737:.\Generated_Source\PSoC5/CyLib.c **** CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); - 1831 .loc 1 1737 0 - 1832 0006 FFF7FEBF b CyDelayCycles - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 66 - - - 1833 .LVL118: - 1834 .L225: - 1835 000a 00BF .align 2 - 1836 .L224: - 1837 000c 00000000 .word .LANCHOR0 - 1838 .cfi_endproc - 1839 .LFE42: - 1840 .size CyDelayUs, .-CyDelayUs - 1841 .section .text.CyXTAL_32KHZ_SetPowerMode,"ax",%progbits - 1842 .align 1 - 1843 .global CyXTAL_32KHZ_SetPowerMode - 1844 .thumb - 1845 .thumb_func - 1846 .type CyXTAL_32KHZ_SetPowerMode, %function - 1847 CyXTAL_32KHZ_SetPowerMode: - 1848 .LFB28: -1273:.\Generated_Source\PSoC5/CyLib.c **** { - 1849 .loc 1 1273 0 - 1850 .cfi_startproc - 1851 @ args = 0, pretend = 0, frame = 0 - 1852 @ frame_needed = 0, uses_anonymous_args = 0 - 1853 .LVL119: - 1854 0000 70B5 push {r4, r5, r6, lr} - 1855 .LCFI6: - 1856 .cfi_def_cfa_offset 16 - 1857 .cfi_offset 4, -16 - 1858 .cfi_offset 5, -12 - 1859 .cfi_offset 6, -8 - 1860 .cfi_offset 14, -4 -1274:.\Generated_Source\PSoC5/CyLib.c **** uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; - 1861 .loc 1 1274 0 - 1862 0002 164C ldr r4, .L230 -1276:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - 1863 .loc 1 1276 0 - 1864 0004 164B ldr r3, .L230+4 -1274:.\Generated_Source\PSoC5/CyLib.c **** uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; - 1865 .loc 1 1274 0 - 1866 0006 2678 ldrb r6, [r4, #0] @ zero_extendqisi2 -1276:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - 1867 .loc 1 1276 0 - 1868 0008 F321 movs r1, #243 -1278:.\Generated_Source\PSoC5/CyLib.c **** if(1u == mode) - 1869 .loc 1 1278 0 - 1870 000a 0128 cmp r0, #1 -1276:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - 1871 .loc 1 1276 0 - 1872 000c 1970 strb r1, [r3, #0] -1274:.\Generated_Source\PSoC5/CyLib.c **** uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; - 1873 .loc 1 1274 0 - 1874 000e C6F34006 ubfx r6, r6, #1, #1 - 1875 .LVL120: - 1876 0012 1449 ldr r1, .L230+8 - 1877 0014 144D ldr r5, .L230+12 -1278:.\Generated_Source\PSoC5/CyLib.c **** if(1u == mode) - 1878 .loc 1 1278 0 - 1879 0016 10D1 bne .L227 -1281:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 67 - - - 1880 .loc 1 1281 0 - 1881 0018 0870 strb r0, [r1, #0] -1282:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(10u); - 1882 .loc 1 1282 0 - 1883 001a 0A20 movs r0, #10 - 1884 .LVL121: - 1885 001c FFF7FEFF bl CyDelayUs - 1886 .LVL122: -1283:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - 1887 .loc 1 1283 0 - 1888 0020 2B78 ldrb r3, [r5, #0] @ zero_extendqisi2 -1285:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(20u); - 1889 .loc 1 1285 0 - 1890 0022 1420 movs r0, #20 -1283:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - 1891 .loc 1 1283 0 - 1892 0024 03F0F301 and r1, r3, #243 - 1893 0028 41F00802 orr r2, r1, #8 - 1894 002c 2A70 strb r2, [r5, #0] -1285:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(20u); - 1895 .loc 1 1285 0 - 1896 002e FFF7FEFF bl CyDelayUs - 1897 .LVL123: -1286:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; - 1898 .loc 1 1286 0 - 1899 0032 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 1900 0034 40F00200 orr r0, r0, #2 - 1901 0038 0DE0 b .L229 - 1902 .LVL124: - 1903 .L227: -1291:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; - 1904 .loc 1 1291 0 - 1905 003a 0622 movs r2, #6 - 1906 003c 0A70 strb r2, [r1, #0] -1292:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(10u); - 1907 .loc 1 1292 0 - 1908 003e 0A20 movs r0, #10 - 1909 .LVL125: - 1910 0040 FFF7FEFF bl CyDelayUs - 1911 .LVL126: -1293:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - 1912 .loc 1 1293 0 - 1913 0044 2878 ldrb r0, [r5, #0] @ zero_extendqisi2 - 1914 0046 00F0F303 and r3, r0, #243 - 1915 004a 43F00401 orr r1, r3, #4 - 1916 004e 2970 strb r1, [r5, #0] -1295:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); - 1917 .loc 1 1295 0 - 1918 0050 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - 1919 0052 02F0FD00 and r0, r2, #253 - 1920 .L229: - 1921 0056 2070 strb r0, [r4, #0] -1299:.\Generated_Source\PSoC5/CyLib.c **** } - 1922 .loc 1 1299 0 - 1923 0058 3046 mov r0, r6 - 1924 005a 70BD pop {r4, r5, r6, pc} - 1925 .L231: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 68 - - - 1926 .align 2 - 1927 .L230: - 1928 005c 08430040 .word 1073758984 - 1929 0060 0A430040 .word 1073758986 - 1930 0064 98460040 .word 1073759896 - 1931 0068 09430040 .word 1073758985 - 1932 .cfi_endproc - 1933 .LFE28: - 1934 .size CyXTAL_32KHZ_SetPowerMode, .-CyXTAL_32KHZ_SetPowerMode - 1935 .section .text.CyXTAL_32KHZ_Start,"ax",%progbits - 1936 .align 1 - 1937 .global CyXTAL_32KHZ_Start - 1938 .thumb - 1939 .thumb_func - 1940 .type CyXTAL_32KHZ_Start, %function - 1941 CyXTAL_32KHZ_Start: - 1942 .LFB25: -1174:.\Generated_Source\PSoC5/CyLib.c **** { - 1943 .loc 1 1174 0 - 1944 .cfi_startproc - 1945 @ args = 0, pretend = 0, frame = 8 - 1946 @ frame_needed = 0, uses_anonymous_args = 0 - 1947 0000 07B5 push {r0, r1, r2, lr} - 1948 .LCFI7: - 1949 .cfi_def_cfa_offset 16 - 1950 .cfi_offset 0, -16 - 1951 .cfi_offset 1, -12 - 1952 .cfi_offset 2, -8 - 1953 .cfi_offset 14, -4 -1177:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - 1954 .loc 1 1177 0 - 1955 0002 174B ldr r3, .L238 - 1956 0004 F322 movs r2, #243 -1178:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; - 1957 .loc 1 1178 0 - 1958 0006 1749 ldr r1, .L238+4 -1177:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - 1959 .loc 1 1177 0 - 1960 0008 1A70 strb r2, [r3, #0] -1178:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; - 1961 .loc 1 1178 0 - 1962 000a 0320 movs r0, #3 -1179:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - 1963 .loc 1 1179 0 - 1964 000c 164B ldr r3, .L238+8 -1178:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; - 1965 .loc 1 1178 0 - 1966 000e 0870 strb r0, [r1, #0] -1179:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - 1967 .loc 1 1179 0 - 1968 0010 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1969 0012 02F0F300 and r0, r2, #243 - 1970 0016 40F00401 orr r1, r0, #4 - 1971 001a 1970 strb r1, [r3, #0] -1187:.\Generated_Source\PSoC5/CyLib.c **** CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; - 1972 .loc 1 1187 0 - 1973 001c 13F8012C ldrb r2, [r3, #-1] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 69 - - - 1974 0020 42F00100 orr r0, r2, #1 - 1975 0024 03F8010C strb r0, [r3, #-1] -1189:.\Generated_Source\PSoC5/CyLib.c **** for (i = 1000u; i > 0u; i--) - 1976 .loc 1 1189 0 - 1977 0028 4FF47A73 mov r3, #1000 - 1978 .L237: - 1979 .LVL127: - 1980 002c ADF80630 strh r3, [sp, #6] @ movhi - 1981 0030 BDF80630 ldrh r3, [sp, #6] - 1982 .LVL128: - 1983 0034 99B2 uxth r1, r3 - 1984 0036 89B1 cbz r1, .L232 - 1985 .L236: - 1986 .LBB16: - 1987 .LBB17: -1250:.\Generated_Source\PSoC5/CyLib.c **** return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); - 1988 .loc 1 1250 0 - 1989 0038 0C4A ldr r2, .L238+12 - 1990 003a 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 1991 .LBE17: - 1992 .LBE16: -1191:.\Generated_Source\PSoC5/CyLib.c **** if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) - 1993 .loc 1 1191 0 - 1994 003c 00F02003 and r3, r0, #32 - 1995 0040 D9B2 uxtb r1, r3 - 1996 0042 19B1 cbz r1, .L234 -1194:.\Generated_Source\PSoC5/CyLib.c **** (void) CyXTAL_32KHZ_SetPowerMode(0u); - 1997 .loc 1 1194 0 - 1998 0044 0020 movs r0, #0 - 1999 0046 FFF7FEFF bl CyXTAL_32KHZ_SetPowerMode - 2000 .LVL129: -1196:.\Generated_Source\PSoC5/CyLib.c **** break; - 2001 .loc 1 1196 0 - 2002 004a 07E0 b .L232 - 2003 .L234: -1198:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(1u); - 2004 .loc 1 1198 0 - 2005 004c 0120 movs r0, #1 - 2006 004e FFF7FEFF bl CyDelayUs - 2007 .LVL130: -1189:.\Generated_Source\PSoC5/CyLib.c **** for (i = 1000u; i > 0u; i--) - 2008 .loc 1 1189 0 - 2009 0052 BDF80620 ldrh r2, [sp, #6] - 2010 .LVL131: - 2011 0056 501E subs r0, r2, #1 - 2012 0058 83B2 uxth r3, r0 - 2013 .LVL132: - 2014 005a E7E7 b .L237 - 2015 .LVL133: - 2016 .L232: -1200:.\Generated_Source\PSoC5/CyLib.c **** } - 2017 .loc 1 1200 0 - 2018 005c 0EBD pop {r1, r2, r3, pc} - 2019 .L239: - 2020 005e 00BF .align 2 - 2021 .L238: - 2022 0060 0A430040 .word 1073758986 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 70 - - - 2023 0064 98460040 .word 1073759896 - 2024 0068 09430040 .word 1073758985 - 2025 006c 08430040 .word 1073758984 - 2026 .cfi_endproc - 2027 .LFE25: - 2028 .size CyXTAL_32KHZ_Start, .-CyXTAL_32KHZ_Start - 2029 .section .text.CyDelayFreq,"ax",%progbits - 2030 .align 1 - 2031 .global CyDelayFreq - 2032 .thumb - 2033 .thumb_func - 2034 .type CyDelayFreq, %function - 2035 CyDelayFreq: - 2036 .LFB43: -1739:.\Generated_Source\PSoC5/CyLib.c **** -1740:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (!CY_PSOC3) */ -1741:.\Generated_Source\PSoC5/CyLib.c **** -1742:.\Generated_Source\PSoC5/CyLib.c **** -1743:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1744:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyDelayFreq -1745:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1746:.\Generated_Source\PSoC5/CyLib.c **** * -1747:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1748:.\Generated_Source\PSoC5/CyLib.c **** * Sets clock frequency for CyDelay. -1749:.\Generated_Source\PSoC5/CyLib.c **** * -1750:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1751:.\Generated_Source\PSoC5/CyLib.c **** * freq: Frequency of bus clock in Hertz. -1752:.\Generated_Source\PSoC5/CyLib.c **** * -1753:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1754:.\Generated_Source\PSoC5/CyLib.c **** * None -1755:.\Generated_Source\PSoC5/CyLib.c **** * -1756:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1757:.\Generated_Source\PSoC5/CyLib.c **** void CyDelayFreq(uint32 freq) CYREENTRANT -1758:.\Generated_Source\PSoC5/CyLib.c **** { - 2037 .loc 1 1758 0 - 2038 .cfi_startproc - 2039 @ args = 0, pretend = 0, frame = 0 - 2040 @ frame_needed = 0, uses_anonymous_args = 0 - 2041 @ link register save eliminated. - 2042 .LVL134: - 2043 0000 0C4B ldr r3, .L243 -1759:.\Generated_Source\PSoC5/CyLib.c **** if (freq != 0u) - 2044 .loc 1 1759 0 - 2045 0002 08B1 cbz r0, .L241 -1760:.\Generated_Source\PSoC5/CyLib.c **** { -1761:.\Generated_Source\PSoC5/CyLib.c **** cydelay_freq_hz = freq; - 2046 .loc 1 1761 0 - 2047 0004 D860 str r0, [r3, #12] - 2048 0006 01E0 b .L242 - 2049 .L241: -1762:.\Generated_Source\PSoC5/CyLib.c **** } -1763:.\Generated_Source\PSoC5/CyLib.c **** else -1764:.\Generated_Source\PSoC5/CyLib.c **** { -1765:.\Generated_Source\PSoC5/CyLib.c **** cydelay_freq_hz = BCLK__BUS_CLK__HZ; - 2050 .loc 1 1765 0 - 2051 0008 0B4A ldr r2, .L243+4 - 2052 000a DA60 str r2, [r3, #12] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 71 - - - 2053 .L242: -1766:.\Generated_Source\PSoC5/CyLib.c **** } -1767:.\Generated_Source\PSoC5/CyLib.c **** -1768:.\Generated_Source\PSoC5/CyLib.c **** cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); - 2054 .loc 1 1768 0 - 2055 000c D968 ldr r1, [r3, #12] - 2056 000e 01F57420 add r0, r1, #999424 - 2057 .LVL135: - 2058 0012 00F23F22 addw r2, r0, #575 - 2059 0016 0948 ldr r0, .L243+8 -1769:.\Generated_Source\PSoC5/CyLib.c **** cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; - 2060 .loc 1 1769 0 - 2061 0018 01F2E731 addw r1, r1, #999 -1768:.\Generated_Source\PSoC5/CyLib.c **** cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); - 2062 .loc 1 1768 0 - 2063 001c B2FBF0F2 udiv r2, r2, r0 - 2064 .loc 1 1769 0 - 2065 0020 4FF47A70 mov r0, #1000 -1768:.\Generated_Source\PSoC5/CyLib.c **** cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); - 2066 .loc 1 1768 0 - 2067 0024 1A72 strb r2, [r3, #8] - 2068 .loc 1 1769 0 - 2069 0026 B1FBF0F2 udiv r2, r1, r0 -1770:.\Generated_Source\PSoC5/CyLib.c **** cydelay_32k_ms = 32768u * cydelay_freq_khz; - 2070 .loc 1 1770 0 - 2071 002a D103 lsls r1, r2, #15 -1769:.\Generated_Source\PSoC5/CyLib.c **** cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; - 2072 .loc 1 1769 0 - 2073 002c 5A60 str r2, [r3, #4] - 2074 .loc 1 1770 0 - 2075 002e 1960 str r1, [r3, #0] - 2076 0030 7047 bx lr - 2077 .L244: - 2078 0032 00BF .align 2 - 2079 .L243: - 2080 0034 00000000 .word .LANCHOR0 - 2081 0038 0090D003 .word 64000000 - 2082 003c 40420F00 .word 1000000 - 2083 .cfi_endproc - 2084 .LFE43: - 2085 .size CyDelayFreq, .-CyDelayFreq - 2086 .section .text.CyWdtStart,"ax",%progbits - 2087 .align 1 - 2088 .global CyWdtStart - 2089 .thumb - 2090 .thumb_func - 2091 .type CyWdtStart, %function - 2092 CyWdtStart: - 2093 .LFB44: -1771:.\Generated_Source\PSoC5/CyLib.c **** } -1772:.\Generated_Source\PSoC5/CyLib.c **** -1773:.\Generated_Source\PSoC5/CyLib.c **** -1774:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1775:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyWdtStart -1776:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1777:.\Generated_Source\PSoC5/CyLib.c **** * -1778:.\Generated_Source\PSoC5/CyLib.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 72 - - -1779:.\Generated_Source\PSoC5/CyLib.c **** * Enables the watchdog timer. -1780:.\Generated_Source\PSoC5/CyLib.c **** * -1781:.\Generated_Source\PSoC5/CyLib.c **** * The timer is configured for the specified count interval, the central -1782:.\Generated_Source\PSoC5/CyLib.c **** * timewheel is cleared, the setting for low power mode is configured and the -1783:.\Generated_Source\PSoC5/CyLib.c **** * watchdog timer is enabled. -1784:.\Generated_Source\PSoC5/CyLib.c **** * -1785:.\Generated_Source\PSoC5/CyLib.c **** * Once enabled the watchdog cannot be disabled. The watchdog counts each time -1786:.\Generated_Source\PSoC5/CyLib.c **** * the Central Time Wheel (CTW) reaches the period specified. The watchdog must -1787:.\Generated_Source\PSoC5/CyLib.c **** * be cleared using the CyWdtClear() function before three ticks of the watchdog -1788:.\Generated_Source\PSoC5/CyLib.c **** * timer occur. The CTW is free running, so this will occur after between 2 and -1789:.\Generated_Source\PSoC5/CyLib.c **** * 3 timer periods elapse. -1790:.\Generated_Source\PSoC5/CyLib.c **** * -1791:.\Generated_Source\PSoC5/CyLib.c **** * PSoC5: The watchdog timer should not be used during sleep modes. Since the -1792:.\Generated_Source\PSoC5/CyLib.c **** * WDT cannot be disabled after it is enabled, the WDT timeout period can be -1793:.\Generated_Source\PSoC5/CyLib.c **** * set to be greater than the sleep wakeup period, then feed the dog on each -1794:.\Generated_Source\PSoC5/CyLib.c **** * wakeup from Sleep. -1795:.\Generated_Source\PSoC5/CyLib.c **** * -1796:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1797:.\Generated_Source\PSoC5/CyLib.c **** * ticks: One of the four available timer periods. Once WDT enabled, the -1798:.\Generated_Source\PSoC5/CyLib.c **** interval cannot be changed. -1799:.\Generated_Source\PSoC5/CyLib.c **** * CYWDT_2_TICKS - 4 - 6 ms -1800:.\Generated_Source\PSoC5/CyLib.c **** * CYWDT_16_TICKS - 32 - 48 ms -1801:.\Generated_Source\PSoC5/CyLib.c **** * CYWDT_128_TICKS - 256 - 384 ms -1802:.\Generated_Source\PSoC5/CyLib.c **** * CYWDT_1024_TICKS - 2.048 - 3.072 s -1803:.\Generated_Source\PSoC5/CyLib.c **** * -1804:.\Generated_Source\PSoC5/CyLib.c **** * lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. -1805:.\Generated_Source\PSoC5/CyLib.c **** * The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. -1806:.\Generated_Source\PSoC5/CyLib.c **** * -1807:.\Generated_Source\PSoC5/CyLib.c **** * CYWDT_LPMODE_NOCHANGE - No Change -1808:.\Generated_Source\PSoC5/CyLib.c **** * CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power -1809:.\Generated_Source\PSoC5/CyLib.c **** * mode -1810:.\Generated_Source\PSoC5/CyLib.c **** * CYWDT_LPMODE_DISABLED - Disable WDT during low power mode -1811:.\Generated_Source\PSoC5/CyLib.c **** * -1812:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1813:.\Generated_Source\PSoC5/CyLib.c **** * None -1814:.\Generated_Source\PSoC5/CyLib.c **** * -1815:.\Generated_Source\PSoC5/CyLib.c **** * Side Effects: -1816:.\Generated_Source\PSoC5/CyLib.c **** * PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the -1817:.\Generated_Source\PSoC5/CyLib.c **** * ILO 1 kHz could break the active WDT functionality. -1818:.\Generated_Source\PSoC5/CyLib.c **** * -1819:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1820:.\Generated_Source\PSoC5/CyLib.c **** void CyWdtStart(uint8 ticks, uint8 lpMode) -1821:.\Generated_Source\PSoC5/CyLib.c **** { - 2094 .loc 1 1821 0 - 2095 .cfi_startproc - 2096 @ args = 0, pretend = 0, frame = 0 - 2097 @ frame_needed = 0, uses_anonymous_args = 0 - 2098 @ link register save eliminated. - 2099 .LVL136: -1822:.\Generated_Source\PSoC5/CyLib.c **** /* Set WDT interval */ -1823:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_ - 2100 .loc 1 1823 0 - 2101 0000 0E4B ldr r3, .L246 - 2102 0002 00F00300 and r0, r0, #3 - 2103 .LVL137: - 2104 0006 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 -1824:.\Generated_Source\PSoC5/CyLib.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 73 - - -1825:.\Generated_Source\PSoC5/CyLib.c **** /* Reset CTW to ensure that first watchdog period is full */ -1826:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; -1827:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); -1828:.\Generated_Source\PSoC5/CyLib.c **** -1829:.\Generated_Source\PSoC5/CyLib.c **** /* Setting the low power mode */ -1830:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | - 2105 .loc 1 1830 0 - 2106 0008 4901 lsls r1, r1, #5 - 2107 .LVL138: -1823:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_ - 2108 .loc 1 1823 0 - 2109 000a 02F0FC02 and r2, r2, #252 - 2110 000e 1043 orrs r0, r0, r2 - 2111 0010 1870 strb r0, [r3, #0] -1826:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; - 2112 .loc 1 1826 0 - 2113 0012 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 2114 0014 42F08000 orr r0, r2, #128 - 2115 0018 1870 strb r0, [r3, #0] -1827:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); - 2116 .loc 1 1827 0 - 2117 001a 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 2118 001c 02F07F00 and r0, r2, #127 - 2119 0020 1870 strb r0, [r3, #0] -1831:.\Generated_Source\PSoC5/CyLib.c **** (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); - 2120 .loc 1 1831 0 - 2121 0022 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 -1830:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | - 2122 .loc 1 1830 0 - 2123 0024 01F06000 and r0, r1, #96 - 2124 0028 02F09F02 and r2, r2, #159 - 2125 002c 40EA0201 orr r1, r0, r2 - 2126 0030 1970 strb r1, [r3, #0] -1832:.\Generated_Source\PSoC5/CyLib.c **** -1833:.\Generated_Source\PSoC5/CyLib.c **** /* Enables the watchdog reset */ -1834:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; - 2127 .loc 1 1834 0 - 2128 0032 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 2129 0034 40F01002 orr r2, r0, #16 - 2130 0038 1A70 strb r2, [r3, #0] - 2131 003a 7047 bx lr - 2132 .L247: - 2133 .align 2 - 2134 .L246: - 2135 003c 83430040 .word 1073759107 - 2136 .cfi_endproc - 2137 .LFE44: - 2138 .size CyWdtStart, .-CyWdtStart - 2139 .section .text.CyWdtClear,"ax",%progbits - 2140 .align 1 - 2141 .global CyWdtClear - 2142 .thumb - 2143 .thumb_func - 2144 .type CyWdtClear, %function - 2145 CyWdtClear: - 2146 .LFB45: -1835:.\Generated_Source\PSoC5/CyLib.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 74 - - -1836:.\Generated_Source\PSoC5/CyLib.c **** -1837:.\Generated_Source\PSoC5/CyLib.c **** -1838:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1839:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyWdtClear -1840:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1841:.\Generated_Source\PSoC5/CyLib.c **** * -1842:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1843:.\Generated_Source\PSoC5/CyLib.c **** * Clears (feeds) the watchdog timer. -1844:.\Generated_Source\PSoC5/CyLib.c **** * -1845:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1846:.\Generated_Source\PSoC5/CyLib.c **** * None -1847:.\Generated_Source\PSoC5/CyLib.c **** * -1848:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1849:.\Generated_Source\PSoC5/CyLib.c **** * None -1850:.\Generated_Source\PSoC5/CyLib.c **** * -1851:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1852:.\Generated_Source\PSoC5/CyLib.c **** void CyWdtClear(void) -1853:.\Generated_Source\PSoC5/CyLib.c **** { - 2147 .loc 1 1853 0 - 2148 .cfi_startproc - 2149 @ args = 0, pretend = 0, frame = 0 - 2150 @ frame_needed = 0, uses_anonymous_args = 0 - 2151 @ link register save eliminated. -1854:.\Generated_Source\PSoC5/CyLib.c **** CY_WDT_CR_REG = CY_WDT_CR_FEED; - 2152 .loc 1 1854 0 - 2153 0000 014B ldr r3, .L249 - 2154 0002 0122 movs r2, #1 - 2155 0004 1A70 strb r2, [r3, #0] - 2156 0006 7047 bx lr - 2157 .L250: - 2158 .align 2 - 2159 .L249: - 2160 0008 84430040 .word 1073759108 - 2161 .cfi_endproc - 2162 .LFE45: - 2163 .size CyWdtClear, .-CyWdtClear - 2164 .section .text.CyVdLvDigitEnable,"ax",%progbits - 2165 .align 1 - 2166 .global CyVdLvDigitEnable - 2167 .thumb - 2168 .thumb_func - 2169 .type CyVdLvDigitEnable, %function - 2170 CyVdLvDigitEnable: - 2171 .LFB46: -1855:.\Generated_Source\PSoC5/CyLib.c **** } -1856:.\Generated_Source\PSoC5/CyLib.c **** -1857:.\Generated_Source\PSoC5/CyLib.c **** -1858:.\Generated_Source\PSoC5/CyLib.c **** -1859:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1860:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdLvDigitEnable -1861:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1862:.\Generated_Source\PSoC5/CyLib.c **** * -1863:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1864:.\Generated_Source\PSoC5/CyLib.c **** * Enables the digital low voltage monitors to generate interrupt on Vddd -1865:.\Generated_Source\PSoC5/CyLib.c **** * archives specified threshold and optionally resets device. -1866:.\Generated_Source\PSoC5/CyLib.c **** * -1867:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 75 - - -1868:.\Generated_Source\PSoC5/CyLib.c **** * reset: Option to reset device at a specified Vddd threshold: -1869:.\Generated_Source\PSoC5/CyLib.c **** * 0 - Device is not reset. -1870:.\Generated_Source\PSoC5/CyLib.c **** * 1 - Device is reset. -1871:.\Generated_Source\PSoC5/CyLib.c **** * -1872:.\Generated_Source\PSoC5/CyLib.c **** * threshold: Sets the trip level for the voltage monitor. -1873:.\Generated_Source\PSoC5/CyLib.c **** * Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV -1874:.\Generated_Source\PSoC5/CyLib.c **** * interval. -1875:.\Generated_Source\PSoC5/CyLib.c **** * -1876:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1877:.\Generated_Source\PSoC5/CyLib.c **** * None -1878:.\Generated_Source\PSoC5/CyLib.c **** * -1879:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1880:.\Generated_Source\PSoC5/CyLib.c **** void CyVdLvDigitEnable(uint8 reset, uint8 threshold) -1881:.\Generated_Source\PSoC5/CyLib.c **** { - 2172 .loc 1 1881 0 - 2173 .cfi_startproc - 2174 @ args = 0, pretend = 0, frame = 0 - 2175 @ frame_needed = 0, uses_anonymous_args = 0 - 2176 .LVL139: - 2177 0000 38B5 push {r3, r4, r5, lr} - 2178 .LCFI8: - 2179 .cfi_def_cfa_offset 16 - 2180 .cfi_offset 3, -16 - 2181 .cfi_offset 4, -12 - 2182 .cfi_offset 5, -8 - 2183 .cfi_offset 14, -4 -1882:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLEAR_PTR = 0x01u; - 2184 .loc 1 1882 0 - 2185 0002 144A ldr r2, .L255 - 2186 0004 0123 movs r3, #1 -1883:.\Generated_Source\PSoC5/CyLib.c **** -1884:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - 2187 .loc 1 1884 0 - 2188 0006 144C ldr r4, .L255+4 -1882:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLEAR_PTR = 0x01u; - 2189 .loc 1 1882 0 - 2190 0008 1360 str r3, [r2, #0] -1881:.\Generated_Source\PSoC5/CyLib.c **** { - 2191 .loc 1 1881 0 - 2192 000a 0546 mov r5, r0 - 2193 .loc 1 1884 0 - 2194 000c 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 2195 .LVL140: -1885:.\Generated_Source\PSoC5/CyLib.c **** -1886:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | - 2196 .loc 1 1886 0 - 2197 000e 01F00F01 and r1, r1, #15 - 2198 .LVL141: -1884:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - 2199 .loc 1 1884 0 - 2200 0012 00F0BF02 and r2, r0, #191 - 2201 0016 2270 strb r2, [r4, #0] -1887:.\Generated_Source\PSoC5/CyLib.c **** (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); - 2202 .loc 1 1887 0 - 2203 0018 104A ldr r2, .L255+8 - 2204 001a 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 -1886:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 76 - - - 2205 .loc 1 1886 0 - 2206 001c 00F0F000 and r0, r0, #240 - 2207 0020 0143 orrs r1, r1, r0 - 2208 0022 1170 strb r1, [r2, #0] -1888:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; - 2209 .loc 1 1888 0 - 2210 0024 5078 ldrb r0, [r2, #1] @ zero_extendqisi2 - 2211 0026 1843 orrs r0, r0, r3 - 2212 0028 5070 strb r0, [r2, #1] -1889:.\Generated_Source\PSoC5/CyLib.c **** -1890:.\Generated_Source\PSoC5/CyLib.c **** /* Timeout to eliminate glitches on the LVI/HVI when enabling */ -1891:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(1u); - 2213 .loc 1 1891 0 - 2214 002a 1846 mov r0, r3 - 2215 002c FFF7FEFF bl CyDelayUs - 2216 .LVL142: -1892:.\Generated_Source\PSoC5/CyLib.c **** -1893:.\Generated_Source\PSoC5/CyLib.c **** (void)CY_VD_PERSISTENT_STATUS_REG; - 2217 .loc 1 1893 0 - 2218 0030 0B4B ldr r3, .L255+12 - 2219 0032 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 -1894:.\Generated_Source\PSoC5/CyLib.c **** -1895:.\Generated_Source\PSoC5/CyLib.c **** if(0u != reset) -1896:.\Generated_Source\PSoC5/CyLib.c **** { -1897:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; - 2220 .loc 1 1897 0 - 2221 0034 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 -1895:.\Generated_Source\PSoC5/CyLib.c **** if(0u != reset) - 2222 .loc 1 1895 0 - 2223 0036 15B1 cbz r5, .L252 - 2224 .loc 1 1897 0 - 2225 0038 42F04001 orr r1, r2, #64 - 2226 003c 01E0 b .L254 - 2227 .L252: -1898:.\Generated_Source\PSoC5/CyLib.c **** } -1899:.\Generated_Source\PSoC5/CyLib.c **** else -1900:.\Generated_Source\PSoC5/CyLib.c **** { -1901:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - 2228 .loc 1 1901 0 - 2229 003e 02F0BF01 and r1, r2, #191 - 2230 .L254: -1902:.\Generated_Source\PSoC5/CyLib.c **** } -1903:.\Generated_Source\PSoC5/CyLib.c **** -1904:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLR_PEND_PTR = 0x01u; - 2231 .loc 1 1904 0 - 2232 0042 084B ldr r3, .L255+16 - 2233 0044 0120 movs r0, #1 -1905:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_ENABLE_PTR = 0x01u; - 2234 .loc 1 1905 0 - 2235 0046 A3F5C072 sub r2, r3, #384 -1901:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - 2236 .loc 1 1901 0 - 2237 004a 2170 strb r1, [r4, #0] -1904:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLR_PEND_PTR = 0x01u; - 2238 .loc 1 1904 0 - 2239 004c 1860 str r0, [r3, #0] - 2240 .loc 1 1905 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 77 - - - 2241 004e 1060 str r0, [r2, #0] - 2242 0050 38BD pop {r3, r4, r5, pc} - 2243 .L256: - 2244 0052 00BF .align 2 - 2245 .L255: - 2246 0054 80E100E0 .word -536813184 - 2247 0058 F7460040 .word 1073759991 - 2248 005c F4460040 .word 1073759988 - 2249 0060 FA460040 .word 1073759994 - 2250 0064 80E200E0 .word -536812928 - 2251 .cfi_endproc - 2252 .LFE46: - 2253 .size CyVdLvDigitEnable, .-CyVdLvDigitEnable - 2254 .section .text.CyVdLvAnalogEnable,"ax",%progbits - 2255 .align 1 - 2256 .global CyVdLvAnalogEnable - 2257 .thumb - 2258 .thumb_func - 2259 .type CyVdLvAnalogEnable, %function - 2260 CyVdLvAnalogEnable: - 2261 .LFB47: -1906:.\Generated_Source\PSoC5/CyLib.c **** } -1907:.\Generated_Source\PSoC5/CyLib.c **** -1908:.\Generated_Source\PSoC5/CyLib.c **** -1909:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1910:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdLvAnalogEnable -1911:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1912:.\Generated_Source\PSoC5/CyLib.c **** * -1913:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1914:.\Generated_Source\PSoC5/CyLib.c **** * Enables the analog low voltage monitors to generate interrupt on Vdda -1915:.\Generated_Source\PSoC5/CyLib.c **** * archives specified threshold and optionally resets device. -1916:.\Generated_Source\PSoC5/CyLib.c **** * -1917:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1918:.\Generated_Source\PSoC5/CyLib.c **** * reset: Option to reset device at a specified Vdda threshold: -1919:.\Generated_Source\PSoC5/CyLib.c **** * 0 - Device is not reset. -1920:.\Generated_Source\PSoC5/CyLib.c **** * 1 - Device is reset. -1921:.\Generated_Source\PSoC5/CyLib.c **** * -1922:.\Generated_Source\PSoC5/CyLib.c **** * threshold: Sets the trip level for the voltage monitor. -1923:.\Generated_Source\PSoC5/CyLib.c **** * Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV -1924:.\Generated_Source\PSoC5/CyLib.c **** * interval. -1925:.\Generated_Source\PSoC5/CyLib.c **** * -1926:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1927:.\Generated_Source\PSoC5/CyLib.c **** * None -1928:.\Generated_Source\PSoC5/CyLib.c **** * -1929:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1930:.\Generated_Source\PSoC5/CyLib.c **** void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) -1931:.\Generated_Source\PSoC5/CyLib.c **** { - 2262 .loc 1 1931 0 - 2263 .cfi_startproc - 2264 @ args = 0, pretend = 0, frame = 0 - 2265 @ frame_needed = 0, uses_anonymous_args = 0 - 2266 .LVL143: - 2267 0000 38B5 push {r3, r4, r5, lr} - 2268 .LCFI9: - 2269 .cfi_def_cfa_offset 16 - 2270 .cfi_offset 3, -16 - 2271 .cfi_offset 4, -12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 78 - - - 2272 .cfi_offset 5, -8 - 2273 .cfi_offset 14, -4 -1932:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLEAR_PTR = 0x01u; - 2274 .loc 1 1932 0 - 2275 0002 144A ldr r2, .L261 - 2276 0004 0123 movs r3, #1 -1933:.\Generated_Source\PSoC5/CyLib.c **** -1934:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - 2277 .loc 1 1934 0 - 2278 0006 144C ldr r4, .L261+4 -1932:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLEAR_PTR = 0x01u; - 2279 .loc 1 1932 0 - 2280 0008 1360 str r3, [r2, #0] -1931:.\Generated_Source\PSoC5/CyLib.c **** { - 2281 .loc 1 1931 0 - 2282 000a 0546 mov r5, r0 - 2283 .loc 1 1934 0 - 2284 000c 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 2285 .LVL144: - 2286 000e 00F07F02 and r2, r0, #127 - 2287 0012 2270 strb r2, [r4, #0] -1935:.\Generated_Source\PSoC5/CyLib.c **** -1936:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); - 2288 .loc 1 1936 0 - 2289 0014 114A ldr r2, .L261+8 - 2290 0016 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 2291 0018 00F00F00 and r0, r0, #15 - 2292 001c 40EA0111 orr r1, r0, r1, lsl #4 - 2293 .LVL145: - 2294 0020 C8B2 uxtb r0, r1 - 2295 0022 1070 strb r0, [r2, #0] -1937:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; - 2296 .loc 1 1937 0 - 2297 0024 5178 ldrb r1, [r2, #1] @ zero_extendqisi2 - 2298 0026 41F00200 orr r0, r1, #2 - 2299 002a 5070 strb r0, [r2, #1] -1938:.\Generated_Source\PSoC5/CyLib.c **** -1939:.\Generated_Source\PSoC5/CyLib.c **** /* Timeout to eliminate glitches on the LVI/HVI when enabling */ -1940:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(1u); - 2300 .loc 1 1940 0 - 2301 002c 1846 mov r0, r3 - 2302 002e FFF7FEFF bl CyDelayUs - 2303 .LVL146: -1941:.\Generated_Source\PSoC5/CyLib.c **** -1942:.\Generated_Source\PSoC5/CyLib.c **** (void)CY_VD_PERSISTENT_STATUS_REG; - 2304 .loc 1 1942 0 - 2305 0032 0B4B ldr r3, .L261+12 - 2306 0034 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 -1943:.\Generated_Source\PSoC5/CyLib.c **** -1944:.\Generated_Source\PSoC5/CyLib.c **** if(0u != reset) -1945:.\Generated_Source\PSoC5/CyLib.c **** { -1946:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; - 2307 .loc 1 1946 0 - 2308 0036 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 -1944:.\Generated_Source\PSoC5/CyLib.c **** if(0u != reset) - 2309 .loc 1 1944 0 - 2310 0038 15B1 cbz r5, .L258 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 79 - - - 2311 .loc 1 1946 0 - 2312 003a 42F08001 orr r1, r2, #128 - 2313 003e 01E0 b .L260 - 2314 .L258: -1947:.\Generated_Source\PSoC5/CyLib.c **** } -1948:.\Generated_Source\PSoC5/CyLib.c **** else -1949:.\Generated_Source\PSoC5/CyLib.c **** { -1950:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - 2315 .loc 1 1950 0 - 2316 0040 02F07F01 and r1, r2, #127 - 2317 .L260: -1951:.\Generated_Source\PSoC5/CyLib.c **** } -1952:.\Generated_Source\PSoC5/CyLib.c **** -1953:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLR_PEND_PTR = 0x01u; - 2318 .loc 1 1953 0 - 2319 0044 074B ldr r3, .L261+16 - 2320 0046 0120 movs r0, #1 -1954:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_ENABLE_PTR = 0x01u; - 2321 .loc 1 1954 0 - 2322 0048 A3F5C072 sub r2, r3, #384 -1950:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - 2323 .loc 1 1950 0 - 2324 004c 2170 strb r1, [r4, #0] -1953:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLR_PEND_PTR = 0x01u; - 2325 .loc 1 1953 0 - 2326 004e 1860 str r0, [r3, #0] - 2327 .loc 1 1954 0 - 2328 0050 1060 str r0, [r2, #0] - 2329 0052 38BD pop {r3, r4, r5, pc} - 2330 .L262: - 2331 .align 2 - 2332 .L261: - 2333 0054 80E100E0 .word -536813184 - 2334 0058 F7460040 .word 1073759991 - 2335 005c F4460040 .word 1073759988 - 2336 0060 FA460040 .word 1073759994 - 2337 0064 80E200E0 .word -536812928 - 2338 .cfi_endproc - 2339 .LFE47: - 2340 .size CyVdLvAnalogEnable, .-CyVdLvAnalogEnable - 2341 .section .text.CyVdLvDigitDisable,"ax",%progbits - 2342 .align 1 - 2343 .global CyVdLvDigitDisable - 2344 .thumb - 2345 .thumb_func - 2346 .type CyVdLvDigitDisable, %function - 2347 CyVdLvDigitDisable: - 2348 .LFB48: -1955:.\Generated_Source\PSoC5/CyLib.c **** } -1956:.\Generated_Source\PSoC5/CyLib.c **** -1957:.\Generated_Source\PSoC5/CyLib.c **** -1958:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1959:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdLvDigitDisable -1960:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1961:.\Generated_Source\PSoC5/CyLib.c **** * -1962:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1963:.\Generated_Source\PSoC5/CyLib.c **** * Disables the digital low voltage monitor (interrupt and device reset are - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 80 - - -1964:.\Generated_Source\PSoC5/CyLib.c **** * disabled). -1965:.\Generated_Source\PSoC5/CyLib.c **** * -1966:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1967:.\Generated_Source\PSoC5/CyLib.c **** * None -1968:.\Generated_Source\PSoC5/CyLib.c **** * -1969:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1970:.\Generated_Source\PSoC5/CyLib.c **** * None -1971:.\Generated_Source\PSoC5/CyLib.c **** * -1972:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -1973:.\Generated_Source\PSoC5/CyLib.c **** void CyVdLvDigitDisable(void) -1974:.\Generated_Source\PSoC5/CyLib.c **** { - 2349 .loc 1 1974 0 - 2350 .cfi_startproc - 2351 @ args = 0, pretend = 0, frame = 0 - 2352 @ frame_needed = 0, uses_anonymous_args = 0 - 2353 @ link register save eliminated. -1975:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); - 2354 .loc 1 1975 0 - 2355 0000 064B ldr r3, .L266 - 2356 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 2357 0004 02F0FE00 and r0, r2, #254 - 2358 0008 1870 strb r0, [r3, #0] -1976:.\Generated_Source\PSoC5/CyLib.c **** -1977:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - 2359 .loc 1 1977 0 - 2360 000a 9978 ldrb r1, [r3, #2] @ zero_extendqisi2 - 2361 000c 01F0BF02 and r2, r1, #191 - 2362 0010 9A70 strb r2, [r3, #2] - 2363 .L264: -1978:.\Generated_Source\PSoC5/CyLib.c **** -1979:.\Generated_Source\PSoC5/CyLib.c **** while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) - 2364 .loc 1 1979 0 discriminator 1 - 2365 0012 034B ldr r3, .L266+4 - 2366 0014 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 2367 0016 4307 lsls r3, r0, #29 - 2368 0018 FBD1 bne .L264 -1980:.\Generated_Source\PSoC5/CyLib.c **** { -1981:.\Generated_Source\PSoC5/CyLib.c **** -1982:.\Generated_Source\PSoC5/CyLib.c **** } -1983:.\Generated_Source\PSoC5/CyLib.c **** } - 2369 .loc 1 1983 0 - 2370 001a 7047 bx lr - 2371 .L267: - 2372 .align 2 - 2373 .L266: - 2374 001c F5460040 .word 1073759989 - 2375 0020 FA460040 .word 1073759994 - 2376 .cfi_endproc - 2377 .LFE48: - 2378 .size CyVdLvDigitDisable, .-CyVdLvDigitDisable - 2379 .section .text.CyVdLvAnalogDisable,"ax",%progbits - 2380 .align 1 - 2381 .global CyVdLvAnalogDisable - 2382 .thumb - 2383 .thumb_func - 2384 .type CyVdLvAnalogDisable, %function - 2385 CyVdLvAnalogDisable: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 81 - - - 2386 .LFB49: -1984:.\Generated_Source\PSoC5/CyLib.c **** -1985:.\Generated_Source\PSoC5/CyLib.c **** -1986:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -1987:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdLvAnalogDisable -1988:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -1989:.\Generated_Source\PSoC5/CyLib.c **** * -1990:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -1991:.\Generated_Source\PSoC5/CyLib.c **** * Disables the analog low voltage monitor (interrupt and device reset are -1992:.\Generated_Source\PSoC5/CyLib.c **** * disabled). -1993:.\Generated_Source\PSoC5/CyLib.c **** * -1994:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -1995:.\Generated_Source\PSoC5/CyLib.c **** * None -1996:.\Generated_Source\PSoC5/CyLib.c **** * -1997:.\Generated_Source\PSoC5/CyLib.c **** * Return: -1998:.\Generated_Source\PSoC5/CyLib.c **** * None -1999:.\Generated_Source\PSoC5/CyLib.c **** * -2000:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2001:.\Generated_Source\PSoC5/CyLib.c **** void CyVdLvAnalogDisable(void) -2002:.\Generated_Source\PSoC5/CyLib.c **** { - 2387 .loc 1 2002 0 - 2388 .cfi_startproc - 2389 @ args = 0, pretend = 0, frame = 0 - 2390 @ frame_needed = 0, uses_anonymous_args = 0 - 2391 @ link register save eliminated. -2003:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); - 2392 .loc 1 2003 0 - 2393 0000 064B ldr r3, .L271 - 2394 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 2395 0004 02F0FD00 and r0, r2, #253 - 2396 0008 1870 strb r0, [r3, #0] -2004:.\Generated_Source\PSoC5/CyLib.c **** -2005:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - 2397 .loc 1 2005 0 - 2398 000a 9978 ldrb r1, [r3, #2] @ zero_extendqisi2 - 2399 000c 01F07F02 and r2, r1, #127 - 2400 0010 9A70 strb r2, [r3, #2] - 2401 .L269: -2006:.\Generated_Source\PSoC5/CyLib.c **** -2007:.\Generated_Source\PSoC5/CyLib.c **** while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) - 2402 .loc 1 2007 0 discriminator 1 - 2403 0012 034B ldr r3, .L271+4 - 2404 0014 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 2405 0016 4207 lsls r2, r0, #29 - 2406 0018 FBD1 bne .L269 -2008:.\Generated_Source\PSoC5/CyLib.c **** { -2009:.\Generated_Source\PSoC5/CyLib.c **** -2010:.\Generated_Source\PSoC5/CyLib.c **** } -2011:.\Generated_Source\PSoC5/CyLib.c **** } - 2407 .loc 1 2011 0 - 2408 001a 7047 bx lr - 2409 .L272: - 2410 .align 2 - 2411 .L271: - 2412 001c F5460040 .word 1073759989 - 2413 0020 FA460040 .word 1073759994 - 2414 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 82 - - - 2415 .LFE49: - 2416 .size CyVdLvAnalogDisable, .-CyVdLvAnalogDisable - 2417 .section .text.CyVdHvAnalogEnable,"ax",%progbits - 2418 .align 1 - 2419 .global CyVdHvAnalogEnable - 2420 .thumb - 2421 .thumb_func - 2422 .type CyVdHvAnalogEnable, %function - 2423 CyVdHvAnalogEnable: - 2424 .LFB50: -2012:.\Generated_Source\PSoC5/CyLib.c **** -2013:.\Generated_Source\PSoC5/CyLib.c **** -2014:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2015:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdHvAnalogEnable -2016:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2017:.\Generated_Source\PSoC5/CyLib.c **** * -2018:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2019:.\Generated_Source\PSoC5/CyLib.c **** * Enables the analog high voltage monitors to generate interrupt on -2020:.\Generated_Source\PSoC5/CyLib.c **** * Vdda archives 5.75 V threshold and optionally resets device. -2021:.\Generated_Source\PSoC5/CyLib.c **** * -2022:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2023:.\Generated_Source\PSoC5/CyLib.c **** * None -2024:.\Generated_Source\PSoC5/CyLib.c **** * -2025:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2026:.\Generated_Source\PSoC5/CyLib.c **** * None -2027:.\Generated_Source\PSoC5/CyLib.c **** * -2028:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2029:.\Generated_Source\PSoC5/CyLib.c **** void CyVdHvAnalogEnable(void) -2030:.\Generated_Source\PSoC5/CyLib.c **** { - 2425 .loc 1 2030 0 - 2426 .cfi_startproc - 2427 @ args = 0, pretend = 0, frame = 0 - 2428 @ frame_needed = 0, uses_anonymous_args = 0 - 2429 0000 10B5 push {r4, lr} - 2430 .LCFI10: - 2431 .cfi_def_cfa_offset 8 - 2432 .cfi_offset 4, -8 - 2433 .cfi_offset 14, -4 -2031:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLEAR_PTR = 0x01u; - 2434 .loc 1 2031 0 - 2435 0002 0C4B ldr r3, .L274 -2032:.\Generated_Source\PSoC5/CyLib.c **** -2033:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - 2436 .loc 1 2033 0 - 2437 0004 0C48 ldr r0, .L274+4 -2031:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLEAR_PTR = 0x01u; - 2438 .loc 1 2031 0 - 2439 0006 0124 movs r4, #1 - 2440 0008 1C60 str r4, [r3, #0] - 2441 .loc 1 2033 0 - 2442 000a 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 2443 000c 02F07F01 and r1, r2, #127 - 2444 0010 0170 strb r1, [r0, #0] -2034:.\Generated_Source\PSoC5/CyLib.c **** -2035:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; - 2445 .loc 1 2035 0 - 2446 0012 10F8023C ldrb r3, [r0, #-2] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 83 - - - 2447 0016 43F00402 orr r2, r3, #4 - 2448 001a 00F8022C strb r2, [r0, #-2] -2036:.\Generated_Source\PSoC5/CyLib.c **** -2037:.\Generated_Source\PSoC5/CyLib.c **** /* Timeout to eliminate glitches on the LVI/HVI when enabling */ -2038:.\Generated_Source\PSoC5/CyLib.c **** CyDelayUs(1u); - 2449 .loc 1 2038 0 - 2450 001e 2046 mov r0, r4 - 2451 0020 FFF7FEFF bl CyDelayUs - 2452 .LVL147: -2039:.\Generated_Source\PSoC5/CyLib.c **** -2040:.\Generated_Source\PSoC5/CyLib.c **** (void) CY_VD_PERSISTENT_STATUS_REG; -2041:.\Generated_Source\PSoC5/CyLib.c **** -2042:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLR_PEND_PTR = 0x01u; - 2453 .loc 1 2042 0 - 2454 0024 0549 ldr r1, .L274+8 -2040:.\Generated_Source\PSoC5/CyLib.c **** (void) CY_VD_PERSISTENT_STATUS_REG; - 2455 .loc 1 2040 0 - 2456 0026 0648 ldr r0, .L274+12 - 2457 0028 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 -2043:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_ENABLE_PTR = 0x01u; - 2458 .loc 1 2043 0 - 2459 002a A1F5C073 sub r3, r1, #384 -2042:.\Generated_Source\PSoC5/CyLib.c **** *CY_INT_CLR_PEND_PTR = 0x01u; - 2460 .loc 1 2042 0 - 2461 002e 0C60 str r4, [r1, #0] - 2462 .loc 1 2043 0 - 2463 0030 1C60 str r4, [r3, #0] - 2464 0032 10BD pop {r4, pc} - 2465 .L275: - 2466 .align 2 - 2467 .L274: - 2468 0034 80E100E0 .word -536813184 - 2469 0038 F7460040 .word 1073759991 - 2470 003c 80E200E0 .word -536812928 - 2471 0040 FA460040 .word 1073759994 - 2472 .cfi_endproc - 2473 .LFE50: - 2474 .size CyVdHvAnalogEnable, .-CyVdHvAnalogEnable - 2475 .section .text.CyVdHvAnalogDisable,"ax",%progbits - 2476 .align 1 - 2477 .global CyVdHvAnalogDisable - 2478 .thumb - 2479 .thumb_func - 2480 .type CyVdHvAnalogDisable, %function - 2481 CyVdHvAnalogDisable: - 2482 .LFB51: -2044:.\Generated_Source\PSoC5/CyLib.c **** } -2045:.\Generated_Source\PSoC5/CyLib.c **** -2046:.\Generated_Source\PSoC5/CyLib.c **** -2047:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2048:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdHvAnalogDisable -2049:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2050:.\Generated_Source\PSoC5/CyLib.c **** * -2051:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2052:.\Generated_Source\PSoC5/CyLib.c **** * Disables the analog low voltage monitor -2053:.\Generated_Source\PSoC5/CyLib.c **** * (interrupt and device reset are disabled). -2054:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 84 - - -2055:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2056:.\Generated_Source\PSoC5/CyLib.c **** * None -2057:.\Generated_Source\PSoC5/CyLib.c **** * -2058:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2059:.\Generated_Source\PSoC5/CyLib.c **** * None -2060:.\Generated_Source\PSoC5/CyLib.c **** * -2061:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2062:.\Generated_Source\PSoC5/CyLib.c **** void CyVdHvAnalogDisable(void) -2063:.\Generated_Source\PSoC5/CyLib.c **** { - 2483 .loc 1 2063 0 - 2484 .cfi_startproc - 2485 @ args = 0, pretend = 0, frame = 0 - 2486 @ frame_needed = 0, uses_anonymous_args = 0 - 2487 @ link register save eliminated. -2064:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); - 2488 .loc 1 2064 0 - 2489 0000 024B ldr r3, .L277 - 2490 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 2491 0004 02F0FB00 and r0, r2, #251 - 2492 0008 1870 strb r0, [r3, #0] - 2493 000a 7047 bx lr - 2494 .L278: - 2495 .align 2 - 2496 .L277: - 2497 000c F5460040 .word 1073759989 - 2498 .cfi_endproc - 2499 .LFE51: - 2500 .size CyVdHvAnalogDisable, .-CyVdHvAnalogDisable - 2501 .section .text.CyVdStickyStatus,"ax",%progbits - 2502 .align 1 - 2503 .global CyVdStickyStatus - 2504 .thumb - 2505 .thumb_func - 2506 .type CyVdStickyStatus, %function - 2507 CyVdStickyStatus: - 2508 .LFB52: -2065:.\Generated_Source\PSoC5/CyLib.c **** } -2066:.\Generated_Source\PSoC5/CyLib.c **** -2067:.\Generated_Source\PSoC5/CyLib.c **** -2068:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2069:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdStickyStatus -2070:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2071:.\Generated_Source\PSoC5/CyLib.c **** * -2072:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2073:.\Generated_Source\PSoC5/CyLib.c **** * Manages the Reset and Voltage Detection Status Register 0. -2074:.\Generated_Source\PSoC5/CyLib.c **** * This register has the interrupt status for the HVIA, LVID and LVIA. -2075:.\Generated_Source\PSoC5/CyLib.c **** * This hardware register clears on read. -2076:.\Generated_Source\PSoC5/CyLib.c **** * -2077:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2078:.\Generated_Source\PSoC5/CyLib.c **** * mask: Bits in the shadow register to clear. -2079:.\Generated_Source\PSoC5/CyLib.c **** * Define Definition -2080:.\Generated_Source\PSoC5/CyLib.c **** * CY_VD_LVID Persistent status of digital LVI. -2081:.\Generated_Source\PSoC5/CyLib.c **** * CY_VD_LVIA Persistent status of analog LVI. -2082:.\Generated_Source\PSoC5/CyLib.c **** * CY_VD_HVIA Persistent status of analog HVI. -2083:.\Generated_Source\PSoC5/CyLib.c **** * -2084:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2085:.\Generated_Source\PSoC5/CyLib.c **** * Status. Same enumerated bit values as used for the mask parameter. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 85 - - -2086:.\Generated_Source\PSoC5/CyLib.c **** * -2087:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2088:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyVdStickyStatus(uint8 mask) -2089:.\Generated_Source\PSoC5/CyLib.c **** { - 2509 .loc 1 2089 0 - 2510 .cfi_startproc - 2511 @ args = 0, pretend = 0, frame = 0 - 2512 @ frame_needed = 0, uses_anonymous_args = 0 - 2513 @ link register save eliminated. - 2514 .LVL148: -2090:.\Generated_Source\PSoC5/CyLib.c **** uint8 status; -2091:.\Generated_Source\PSoC5/CyLib.c **** -2092:.\Generated_Source\PSoC5/CyLib.c **** status = CY_VD_PERSISTENT_STATUS_REG; - 2515 .loc 1 2092 0 - 2516 0000 034B ldr r3, .L280 - 2517 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 2518 .LVL149: -2093:.\Generated_Source\PSoC5/CyLib.c **** CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask)); - 2519 .loc 1 2093 0 - 2520 0004 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 2521 0006 21EA0000 bic r0, r1, r0 - 2522 .LVL150: - 2523 000a 1870 strb r0, [r3, #0] -2094:.\Generated_Source\PSoC5/CyLib.c **** -2095:.\Generated_Source\PSoC5/CyLib.c **** return(status); -2096:.\Generated_Source\PSoC5/CyLib.c **** } - 2524 .loc 1 2096 0 - 2525 000c 1046 mov r0, r2 - 2526 000e 7047 bx lr - 2527 .L281: - 2528 .align 2 - 2529 .L280: - 2530 0010 FA460040 .word 1073759994 - 2531 .cfi_endproc - 2532 .LFE52: - 2533 .size CyVdStickyStatus, .-CyVdStickyStatus - 2534 .section .text.CyVdRealTimeStatus,"ax",%progbits - 2535 .align 1 - 2536 .global CyVdRealTimeStatus - 2537 .thumb - 2538 .thumb_func - 2539 .type CyVdRealTimeStatus, %function - 2540 CyVdRealTimeStatus: - 2541 .LFB53: -2097:.\Generated_Source\PSoC5/CyLib.c **** -2098:.\Generated_Source\PSoC5/CyLib.c **** -2099:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2100:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyVdRealTimeStatus -2101:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2102:.\Generated_Source\PSoC5/CyLib.c **** * -2103:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2104:.\Generated_Source\PSoC5/CyLib.c **** * Returns the real time voltage detection status. -2105:.\Generated_Source\PSoC5/CyLib.c **** * -2106:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2107:.\Generated_Source\PSoC5/CyLib.c **** * None -2108:.\Generated_Source\PSoC5/CyLib.c **** * -2109:.\Generated_Source\PSoC5/CyLib.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 86 - - -2110:.\Generated_Source\PSoC5/CyLib.c **** * Status: -2111:.\Generated_Source\PSoC5/CyLib.c **** * Define Definition -2112:.\Generated_Source\PSoC5/CyLib.c **** * CY_VD_LVID Persistent status of digital LVI. -2113:.\Generated_Source\PSoC5/CyLib.c **** * CY_VD_LVIA Persistent status of analog LVI. -2114:.\Generated_Source\PSoC5/CyLib.c **** * CY_VD_HVIA Persistent status of analog HVI. -2115:.\Generated_Source\PSoC5/CyLib.c **** * -2116:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2117:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyVdRealTimeStatus(void) -2118:.\Generated_Source\PSoC5/CyLib.c **** { - 2542 .loc 1 2118 0 - 2543 .cfi_startproc - 2544 @ args = 0, pretend = 0, frame = 0 - 2545 @ frame_needed = 0, uses_anonymous_args = 0 - 2546 0000 10B5 push {r4, lr} - 2547 .LCFI11: - 2548 .cfi_def_cfa_offset 8 - 2549 .cfi_offset 4, -8 - 2550 .cfi_offset 14, -4 -2119:.\Generated_Source\PSoC5/CyLib.c **** uint8 interruptState; -2120:.\Generated_Source\PSoC5/CyLib.c **** uint8 vdFlagsState; -2121:.\Generated_Source\PSoC5/CyLib.c **** -2122:.\Generated_Source\PSoC5/CyLib.c **** interruptState = CyEnterCriticalSection(); - 2551 .loc 1 2122 0 - 2552 0002 FFF7FEFF bl CyEnterCriticalSection - 2553 .LVL151: -2123:.\Generated_Source\PSoC5/CyLib.c **** vdFlagsState = CY_VD_RT_STATUS_REG; - 2554 .loc 1 2123 0 - 2555 0006 034B ldr r3, .L283 - 2556 0008 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 2557 .LVL152: -2124:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); - 2558 .loc 1 2124 0 - 2559 000a FFF7FEFF bl CyExitCriticalSection - 2560 .LVL153: -2125:.\Generated_Source\PSoC5/CyLib.c **** -2126:.\Generated_Source\PSoC5/CyLib.c **** return(vdFlagsState); -2127:.\Generated_Source\PSoC5/CyLib.c **** } - 2561 .loc 1 2127 0 - 2562 000e 2046 mov r0, r4 - 2563 0010 10BD pop {r4, pc} - 2564 .L284: - 2565 0012 00BF .align 2 - 2566 .L283: - 2567 0014 FC460040 .word 1073759996 - 2568 .cfi_endproc - 2569 .LFE53: - 2570 .size CyVdRealTimeStatus, .-CyVdRealTimeStatus - 2571 .section .text.CyDisableInts,"ax",%progbits - 2572 .align 1 - 2573 .global CyDisableInts - 2574 .thumb - 2575 .thumb_func - 2576 .type CyDisableInts, %function - 2577 CyDisableInts: - 2578 .LFB54: -2128:.\Generated_Source\PSoC5/CyLib.c **** -2129:.\Generated_Source\PSoC5/CyLib.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 87 - - -2130:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2131:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyDisableInts -2132:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2133:.\Generated_Source\PSoC5/CyLib.c **** * -2134:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2135:.\Generated_Source\PSoC5/CyLib.c **** * Disables the interrupt enable for each interrupt. -2136:.\Generated_Source\PSoC5/CyLib.c **** * -2137:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2138:.\Generated_Source\PSoC5/CyLib.c **** * None -2139:.\Generated_Source\PSoC5/CyLib.c **** * -2140:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2141:.\Generated_Source\PSoC5/CyLib.c **** * 32 bit mask of previously enabled interrupts. -2142:.\Generated_Source\PSoC5/CyLib.c **** * -2143:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2144:.\Generated_Source\PSoC5/CyLib.c **** uint32 CyDisableInts(void) -2145:.\Generated_Source\PSoC5/CyLib.c **** { - 2579 .loc 1 2145 0 - 2580 .cfi_startproc - 2581 @ args = 0, pretend = 0, frame = 0 - 2582 @ frame_needed = 0, uses_anonymous_args = 0 - 2583 0000 10B5 push {r4, lr} - 2584 .LCFI12: - 2585 .cfi_def_cfa_offset 8 - 2586 .cfi_offset 4, -8 - 2587 .cfi_offset 14, -4 -2146:.\Generated_Source\PSoC5/CyLib.c **** uint32 intState; -2147:.\Generated_Source\PSoC5/CyLib.c **** uint8 interruptState; -2148:.\Generated_Source\PSoC5/CyLib.c **** -2149:.\Generated_Source\PSoC5/CyLib.c **** interruptState = CyEnterCriticalSection(); - 2588 .loc 1 2149 0 - 2589 0002 FFF7FEFF bl CyEnterCriticalSection - 2590 .LVL154: -2150:.\Generated_Source\PSoC5/CyLib.c **** -2151:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC3) -2152:.\Generated_Source\PSoC5/CyLib.c **** -2153:.\Generated_Source\PSoC5/CyLib.c **** /* Get the current interrupt state. */ -2154:.\Generated_Source\PSoC5/CyLib.c **** intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); -2155:.\Generated_Source\PSoC5/CyLib.c **** intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); -2156:.\Generated_Source\PSoC5/CyLib.c **** intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); -2157:.\Generated_Source\PSoC5/CyLib.c **** intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); -2158:.\Generated_Source\PSoC5/CyLib.c **** -2159:.\Generated_Source\PSoC5/CyLib.c **** -2160:.\Generated_Source\PSoC5/CyLib.c **** /* Disable all of the interrupts. */ -2161:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); -2162:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); -2163:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); -2164:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); -2165:.\Generated_Source\PSoC5/CyLib.c **** -2166:.\Generated_Source\PSoC5/CyLib.c **** #else -2167:.\Generated_Source\PSoC5/CyLib.c **** -2168:.\Generated_Source\PSoC5/CyLib.c **** /* Get the current interrupt state. */ -2169:.\Generated_Source\PSoC5/CyLib.c **** intState = CY_GET_REG32(CY_INT_CLEAR_PTR); - 2591 .loc 1 2169 0 - 2592 0006 044B ldr r3, .L286 -2170:.\Generated_Source\PSoC5/CyLib.c **** -2171:.\Generated_Source\PSoC5/CyLib.c **** /* Disable all of the interrupts. */ -2172:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 88 - - - 2593 .loc 1 2172 0 - 2594 0008 4FF0FF32 mov r2, #-1 -2169:.\Generated_Source\PSoC5/CyLib.c **** intState = CY_GET_REG32(CY_INT_CLEAR_PTR); - 2595 .loc 1 2169 0 - 2596 000c 1C68 ldr r4, [r3, #0] - 2597 .LVL155: - 2598 .loc 1 2172 0 - 2599 000e 1A60 str r2, [r3, #0] -2173:.\Generated_Source\PSoC5/CyLib.c **** -2174:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC3) */ -2175:.\Generated_Source\PSoC5/CyLib.c **** -2176:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); - 2600 .loc 1 2176 0 - 2601 0010 FFF7FEFF bl CyExitCriticalSection - 2602 .LVL156: -2177:.\Generated_Source\PSoC5/CyLib.c **** -2178:.\Generated_Source\PSoC5/CyLib.c **** return (intState); -2179:.\Generated_Source\PSoC5/CyLib.c **** } - 2603 .loc 1 2179 0 - 2604 0014 2046 mov r0, r4 - 2605 0016 10BD pop {r4, pc} - 2606 .L287: - 2607 .align 2 - 2608 .L286: - 2609 0018 80E100E0 .word -536813184 - 2610 .cfi_endproc - 2611 .LFE54: - 2612 .size CyDisableInts, .-CyDisableInts - 2613 .section .text.CyEnableInts,"ax",%progbits - 2614 .align 1 - 2615 .global CyEnableInts - 2616 .thumb - 2617 .thumb_func - 2618 .type CyEnableInts, %function - 2619 CyEnableInts: - 2620 .LFB55: -2180:.\Generated_Source\PSoC5/CyLib.c **** -2181:.\Generated_Source\PSoC5/CyLib.c **** -2182:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2183:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyEnableInts -2184:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2185:.\Generated_Source\PSoC5/CyLib.c **** * -2186:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2187:.\Generated_Source\PSoC5/CyLib.c **** * Enables interrupts to a given state. -2188:.\Generated_Source\PSoC5/CyLib.c **** * -2189:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2190:.\Generated_Source\PSoC5/CyLib.c **** * uint32 mask: 32 bit mask of interrupts to enable. -2191:.\Generated_Source\PSoC5/CyLib.c **** * -2192:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2193:.\Generated_Source\PSoC5/CyLib.c **** * None -2194:.\Generated_Source\PSoC5/CyLib.c **** * -2195:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2196:.\Generated_Source\PSoC5/CyLib.c **** void CyEnableInts(uint32 mask) -2197:.\Generated_Source\PSoC5/CyLib.c **** { - 2621 .loc 1 2197 0 - 2622 .cfi_startproc - 2623 @ args = 0, pretend = 0, frame = 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 89 - - - 2624 @ frame_needed = 0, uses_anonymous_args = 0 - 2625 .LVL157: - 2626 0000 10B5 push {r4, lr} - 2627 .LCFI13: - 2628 .cfi_def_cfa_offset 8 - 2629 .cfi_offset 4, -8 - 2630 .cfi_offset 14, -4 - 2631 .loc 1 2197 0 - 2632 0002 0446 mov r4, r0 -2198:.\Generated_Source\PSoC5/CyLib.c **** -2199:.\Generated_Source\PSoC5/CyLib.c **** uint8 interruptState; -2200:.\Generated_Source\PSoC5/CyLib.c **** -2201:.\Generated_Source\PSoC5/CyLib.c **** interruptState = CyEnterCriticalSection(); - 2633 .loc 1 2201 0 - 2634 0004 FFF7FEFF bl CyEnterCriticalSection - 2635 .LVL158: -2202:.\Generated_Source\PSoC5/CyLib.c **** -2203:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC3) -2204:.\Generated_Source\PSoC5/CyLib.c **** -2205:.\Generated_Source\PSoC5/CyLib.c **** /* Set interrupts as enabled. */ -2206:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); -2207:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); -2208:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); -2209:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); -2210:.\Generated_Source\PSoC5/CyLib.c **** -2211:.\Generated_Source\PSoC5/CyLib.c **** #else -2212:.\Generated_Source\PSoC5/CyLib.c **** -2213:.\Generated_Source\PSoC5/CyLib.c **** CY_SET_REG32(CY_INT_ENABLE_PTR, mask); - 2636 .loc 1 2213 0 - 2637 0008 024B ldr r3, .L289 - 2638 000a 1C60 str r4, [r3, #0] -2214:.\Generated_Source\PSoC5/CyLib.c **** -2215:.\Generated_Source\PSoC5/CyLib.c **** #endif /* (CY_PSOC3) */ -2216:.\Generated_Source\PSoC5/CyLib.c **** -2217:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); -2218:.\Generated_Source\PSoC5/CyLib.c **** -2219:.\Generated_Source\PSoC5/CyLib.c **** } - 2639 .loc 1 2219 0 - 2640 000c BDE81040 pop {r4, lr} -2217:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); - 2641 .loc 1 2217 0 - 2642 0010 FFF7FEBF b CyExitCriticalSection - 2643 .LVL159: - 2644 .L290: - 2645 .align 2 - 2646 .L289: - 2647 0014 00E100E0 .word -536813312 - 2648 .cfi_endproc - 2649 .LFE55: - 2650 .size CyEnableInts, .-CyEnableInts - 2651 .section .text.CyFlushCache,"ax",%progbits - 2652 .align 1 - 2653 .global CyFlushCache - 2654 .thumb - 2655 .thumb_func - 2656 .type CyFlushCache, %function - 2657 CyFlushCache: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 90 - - - 2658 .LFB56: -2220:.\Generated_Source\PSoC5/CyLib.c **** -2221:.\Generated_Source\PSoC5/CyLib.c **** #if(CY_PSOC5) -2222:.\Generated_Source\PSoC5/CyLib.c **** -2223:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2224:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyFlushCache -2225:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2226:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2227:.\Generated_Source\PSoC5/CyLib.c **** * Flushes the PSoC 5/5LP cache by invalidating all entries. -2228:.\Generated_Source\PSoC5/CyLib.c **** * -2229:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2230:.\Generated_Source\PSoC5/CyLib.c **** * None -2231:.\Generated_Source\PSoC5/CyLib.c **** * -2232:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2233:.\Generated_Source\PSoC5/CyLib.c **** * None -2234:.\Generated_Source\PSoC5/CyLib.c **** * -2235:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2236:.\Generated_Source\PSoC5/CyLib.c **** void CyFlushCache(void) -2237:.\Generated_Source\PSoC5/CyLib.c **** { - 2659 .loc 1 2237 0 - 2660 .cfi_startproc - 2661 @ args = 0, pretend = 0, frame = 0 - 2662 @ frame_needed = 0, uses_anonymous_args = 0 - 2663 0000 08B5 push {r3, lr} - 2664 .LCFI14: - 2665 .cfi_def_cfa_offset 8 - 2666 .cfi_offset 3, -8 - 2667 .cfi_offset 14, -4 -2238:.\Generated_Source\PSoC5/CyLib.c **** uint8 interruptState; -2239:.\Generated_Source\PSoC5/CyLib.c **** -2240:.\Generated_Source\PSoC5/CyLib.c **** /* Save current global interrupt enable and disable it */ -2241:.\Generated_Source\PSoC5/CyLib.c **** interruptState = CyEnterCriticalSection(); - 2668 .loc 1 2241 0 - 2669 0002 FFF7FEFF bl CyEnterCriticalSection - 2670 .LVL160: -2242:.\Generated_Source\PSoC5/CyLib.c **** -2243:.\Generated_Source\PSoC5/CyLib.c **** /* Fill instruction prefectch unit to insure data integrity */ -2244:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2671 .loc 1 2244 0 - 2672 @ 2244 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2673 0006 00BF NOP - 2674 - 2675 @ 0 "" 2 -2245:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2676 .loc 1 2245 0 - 2677 @ 2245 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2678 0008 00BF NOP - 2679 - 2680 @ 0 "" 2 -2246:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2681 .loc 1 2246 0 - 2682 @ 2246 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2683 000a 00BF NOP - 2684 - 2685 @ 0 "" 2 -2247:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2686 .loc 1 2247 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 91 - - - 2687 @ 2247 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2688 000c 00BF NOP - 2689 - 2690 @ 0 "" 2 -2248:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2691 .loc 1 2248 0 - 2692 @ 2248 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2693 000e 00BF NOP - 2694 - 2695 @ 0 "" 2 -2249:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2696 .loc 1 2249 0 - 2697 @ 2249 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2698 0010 00BF NOP - 2699 - 2700 @ 0 "" 2 -2250:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2701 .loc 1 2250 0 - 2702 @ 2250 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2703 0012 00BF NOP - 2704 - 2705 @ 0 "" 2 -2251:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2706 .loc 1 2251 0 - 2707 @ 2251 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2708 0014 00BF NOP - 2709 - 2710 @ 0 "" 2 -2252:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2711 .loc 1 2252 0 - 2712 @ 2252 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2713 0016 00BF NOP - 2714 - 2715 @ 0 "" 2 -2253:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2716 .loc 1 2253 0 - 2717 @ 2253 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2718 0018 00BF NOP - 2719 - 2720 @ 0 "" 2 -2254:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2721 .loc 1 2254 0 - 2722 @ 2254 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2723 001a 00BF NOP - 2724 - 2725 @ 0 "" 2 -2255:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2726 .loc 1 2255 0 - 2727 @ 2255 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2728 001c 00BF NOP - 2729 - 2730 @ 0 "" 2 -2256:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2731 .loc 1 2256 0 - 2732 @ 2256 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2733 001e 00BF NOP - 2734 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 92 - - - 2735 @ 0 "" 2 -2257:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2736 .loc 1 2257 0 - 2737 @ 2257 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2738 0020 00BF NOP - 2739 - 2740 @ 0 "" 2 -2258:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2741 .loc 1 2258 0 - 2742 @ 2258 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2743 0022 00BF NOP - 2744 - 2745 @ 0 "" 2 -2259:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2746 .loc 1 2259 0 - 2747 @ 2259 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2748 0024 00BF NOP - 2749 - 2750 @ 0 "" 2 -2260:.\Generated_Source\PSoC5/CyLib.c **** -2261:.\Generated_Source\PSoC5/CyLib.c **** /* All entries in the cache are invalidated on the next clock cycle. */ -2262:.\Generated_Source\PSoC5/CyLib.c **** CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; - 2751 .loc 1 2262 0 - 2752 .thumb - 2753 0026 0D4B ldr r3, .L292 - 2754 0028 1A88 ldrh r2, [r3, #0] - 2755 002a 91B2 uxth r1, r2 - 2756 002c 41F00402 orr r2, r1, #4 - 2757 0030 1A80 strh r2, [r3, #0] @ movhi -2263:.\Generated_Source\PSoC5/CyLib.c **** -2264:.\Generated_Source\PSoC5/CyLib.c **** -2265:.\Generated_Source\PSoC5/CyLib.c **** /*********************************************************************** -2266:.\Generated_Source\PSoC5/CyLib.c **** * The prefetch unit could/would be filled with the instructions that -2267:.\Generated_Source\PSoC5/CyLib.c **** * succeed the flush. Since a flush is desired then theoretically those -2268:.\Generated_Source\PSoC5/CyLib.c **** * instructions might be considered stale/invalid. -2269:.\Generated_Source\PSoC5/CyLib.c **** ***********************************************************************/ -2270:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2758 .loc 1 2270 0 - 2759 @ 2270 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2760 0032 00BF NOP - 2761 - 2762 @ 0 "" 2 -2271:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2763 .loc 1 2271 0 - 2764 @ 2271 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2765 0034 00BF NOP - 2766 - 2767 @ 0 "" 2 -2272:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2768 .loc 1 2272 0 - 2769 @ 2272 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2770 0036 00BF NOP - 2771 - 2772 @ 0 "" 2 -2273:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2773 .loc 1 2273 0 - 2774 @ 2273 ".\Generated_Source\PSoC5\CyLib.c" 1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 93 - - - 2775 0038 00BF NOP - 2776 - 2777 @ 0 "" 2 -2274:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2778 .loc 1 2274 0 - 2779 @ 2274 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2780 003a 00BF NOP - 2781 - 2782 @ 0 "" 2 -2275:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2783 .loc 1 2275 0 - 2784 @ 2275 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2785 003c 00BF NOP - 2786 - 2787 @ 0 "" 2 -2276:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2788 .loc 1 2276 0 - 2789 @ 2276 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2790 003e 00BF NOP - 2791 - 2792 @ 0 "" 2 -2277:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2793 .loc 1 2277 0 - 2794 @ 2277 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2795 0040 00BF NOP - 2796 - 2797 @ 0 "" 2 -2278:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2798 .loc 1 2278 0 - 2799 @ 2278 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2800 0042 00BF NOP - 2801 - 2802 @ 0 "" 2 -2279:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2803 .loc 1 2279 0 - 2804 @ 2279 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2805 0044 00BF NOP - 2806 - 2807 @ 0 "" 2 -2280:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2808 .loc 1 2280 0 - 2809 @ 2280 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2810 0046 00BF NOP - 2811 - 2812 @ 0 "" 2 -2281:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2813 .loc 1 2281 0 - 2814 @ 2281 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2815 0048 00BF NOP - 2816 - 2817 @ 0 "" 2 -2282:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2818 .loc 1 2282 0 - 2819 @ 2282 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2820 004a 00BF NOP - 2821 - 2822 @ 0 "" 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 94 - - -2283:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2823 .loc 1 2283 0 - 2824 @ 2283 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2825 004c 00BF NOP - 2826 - 2827 @ 0 "" 2 -2284:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2828 .loc 1 2284 0 - 2829 @ 2284 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2830 004e 00BF NOP - 2831 - 2832 @ 0 "" 2 -2285:.\Generated_Source\PSoC5/CyLib.c **** CY_NOP; - 2833 .loc 1 2285 0 - 2834 @ 2285 ".\Generated_Source\PSoC5\CyLib.c" 1 - 2835 0050 00BF NOP - 2836 - 2837 @ 0 "" 2 -2286:.\Generated_Source\PSoC5/CyLib.c **** -2287:.\Generated_Source\PSoC5/CyLib.c **** /* Restore global interrupt enable state */ -2288:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); -2289:.\Generated_Source\PSoC5/CyLib.c **** } - 2838 .loc 1 2289 0 - 2839 .thumb - 2840 0052 BDE80840 pop {r3, lr} -2288:.\Generated_Source\PSoC5/CyLib.c **** CyExitCriticalSection(interruptState); - 2841 .loc 1 2288 0 - 2842 0056 FFF7FEBF b CyExitCriticalSection - 2843 .LVL161: - 2844 .L293: - 2845 005a 00BF .align 2 - 2846 .L292: - 2847 005c 00480040 .word 1073760256 - 2848 .cfi_endproc - 2849 .LFE56: - 2850 .size CyFlushCache, .-CyFlushCache - 2851 .section .text.CyIntSetSysVector,"ax",%progbits - 2852 .align 1 - 2853 .global CyIntSetSysVector - 2854 .thumb - 2855 .thumb_func - 2856 .type CyIntSetSysVector, %function - 2857 CyIntSetSysVector: - 2858 .LFB57: -2290:.\Generated_Source\PSoC5/CyLib.c **** -2291:.\Generated_Source\PSoC5/CyLib.c **** -2292:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2293:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntSetSysVector -2294:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2295:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2296:.\Generated_Source\PSoC5/CyLib.c **** * Sets the interrupt vector of the specified system interrupt number. System -2297:.\Generated_Source\PSoC5/CyLib.c **** * interrupts are present only for the ARM platform. These interrupts are for -2298:.\Generated_Source\PSoC5/CyLib.c **** * SysTick, PendSV and others. -2299:.\Generated_Source\PSoC5/CyLib.c **** * -2300:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2301:.\Generated_Source\PSoC5/CyLib.c **** * number: Interrupt number, valid range [0-15]. -2302:.\Generated_Source\PSoC5/CyLib.c **** address: Pointer to an interrupt service routine. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 95 - - -2303:.\Generated_Source\PSoC5/CyLib.c **** * -2304:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2305:.\Generated_Source\PSoC5/CyLib.c **** * The old ISR vector at this location. -2306:.\Generated_Source\PSoC5/CyLib.c **** * -2307:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2308:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) -2309:.\Generated_Source\PSoC5/CyLib.c **** { - 2859 .loc 1 2309 0 - 2860 .cfi_startproc - 2861 @ args = 0, pretend = 0, frame = 0 - 2862 @ frame_needed = 0, uses_anonymous_args = 0 - 2863 @ link register save eliminated. - 2864 .LVL162: -2310:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress oldIsr; -2311:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; -2312:.\Generated_Source\PSoC5/CyLib.c **** -2313:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); -2314:.\Generated_Source\PSoC5/CyLib.c **** -2315:.\Generated_Source\PSoC5/CyLib.c **** /* Save old Interrupt service routine. */ -2316:.\Generated_Source\PSoC5/CyLib.c **** oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; - 2865 .loc 1 2316 0 - 2866 0000 044B ldr r3, .L295 - 2867 .LVL163: - 2868 0002 00F00F02 and r2, r0, #15 - 2869 0006 1B68 ldr r3, [r3, #0] - 2870 .LVL164: - 2871 0008 53F82200 ldr r0, [r3, r2, lsl #2] - 2872 .LVL165: -2317:.\Generated_Source\PSoC5/CyLib.c **** -2318:.\Generated_Source\PSoC5/CyLib.c **** /* Set new Interrupt service routine. */ -2319:.\Generated_Source\PSoC5/CyLib.c **** ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; - 2873 .loc 1 2319 0 - 2874 000c 43F82210 str r1, [r3, r2, lsl #2] -2320:.\Generated_Source\PSoC5/CyLib.c **** -2321:.\Generated_Source\PSoC5/CyLib.c **** return (oldIsr); -2322:.\Generated_Source\PSoC5/CyLib.c **** } - 2875 .loc 1 2322 0 - 2876 0010 7047 bx lr - 2877 .L296: - 2878 0012 00BF .align 2 - 2879 .L295: - 2880 0014 08ED00E0 .word -536810232 - 2881 .cfi_endproc - 2882 .LFE57: - 2883 .size CyIntSetSysVector, .-CyIntSetSysVector - 2884 .section .text.CyIntGetSysVector,"ax",%progbits - 2885 .align 1 - 2886 .global CyIntGetSysVector - 2887 .thumb - 2888 .thumb_func - 2889 .type CyIntGetSysVector, %function - 2890 CyIntGetSysVector: - 2891 .LFB58: -2323:.\Generated_Source\PSoC5/CyLib.c **** -2324:.\Generated_Source\PSoC5/CyLib.c **** -2325:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2326:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntGetSysVector - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 96 - - -2327:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2328:.\Generated_Source\PSoC5/CyLib.c **** * -2329:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2330:.\Generated_Source\PSoC5/CyLib.c **** * Gets the interrupt vector of the specified system interrupt number. System -2331:.\Generated_Source\PSoC5/CyLib.c **** * interrupts are present only for the ARM platform. These interrupts are for -2332:.\Generated_Source\PSoC5/CyLib.c **** * SysTick, PendSV and others. -2333:.\Generated_Source\PSoC5/CyLib.c **** * -2334:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2335:.\Generated_Source\PSoC5/CyLib.c **** * number: The interrupt number, valid range [0-15]. -2336:.\Generated_Source\PSoC5/CyLib.c **** * -2337:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2338:.\Generated_Source\PSoC5/CyLib.c **** * Address of the ISR in the interrupt vector table. -2339:.\Generated_Source\PSoC5/CyLib.c **** * -2340:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2341:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress CyIntGetSysVector(uint8 number) -2342:.\Generated_Source\PSoC5/CyLib.c **** { - 2892 .loc 1 2342 0 - 2893 .cfi_startproc - 2894 @ args = 0, pretend = 0, frame = 0 - 2895 @ frame_needed = 0, uses_anonymous_args = 0 - 2896 @ link register save eliminated. - 2897 .LVL166: -2343:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; -2344:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); -2345:.\Generated_Source\PSoC5/CyLib.c **** -2346:.\Generated_Source\PSoC5/CyLib.c **** return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; - 2898 .loc 1 2346 0 - 2899 0000 034B ldr r3, .L298 - 2900 .LVL167: - 2901 0002 00F00F00 and r0, r0, #15 - 2902 .LVL168: - 2903 0006 1968 ldr r1, [r3, #0] -2347:.\Generated_Source\PSoC5/CyLib.c **** } - 2904 .loc 1 2347 0 - 2905 0008 51F82000 ldr r0, [r1, r0, lsl #2] - 2906 000c 7047 bx lr - 2907 .L299: - 2908 000e 00BF .align 2 - 2909 .L298: - 2910 0010 08ED00E0 .word -536810232 - 2911 .cfi_endproc - 2912 .LFE58: - 2913 .size CyIntGetSysVector, .-CyIntGetSysVector - 2914 .section .text.CyIntSetVector,"ax",%progbits - 2915 .align 1 - 2916 .global CyIntSetVector - 2917 .thumb - 2918 .thumb_func - 2919 .type CyIntSetVector, %function - 2920 CyIntSetVector: - 2921 .LFB59: -2348:.\Generated_Source\PSoC5/CyLib.c **** -2349:.\Generated_Source\PSoC5/CyLib.c **** -2350:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2351:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntSetVector -2352:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2353:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 97 - - -2354:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2355:.\Generated_Source\PSoC5/CyLib.c **** * Sets the interrupt vector of the specified interrupt number. -2356:.\Generated_Source\PSoC5/CyLib.c **** * -2357:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2358:.\Generated_Source\PSoC5/CyLib.c **** * number: Valid range [0-31]. Interrupt number -2359:.\Generated_Source\PSoC5/CyLib.c **** * address: Pointer to an interrupt service routine -2360:.\Generated_Source\PSoC5/CyLib.c **** * -2361:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2362:.\Generated_Source\PSoC5/CyLib.c **** * Previous interrupt vector value. -2363:.\Generated_Source\PSoC5/CyLib.c **** * -2364:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2365:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress CyIntSetVector(uint8 number, cyisraddress address) -2366:.\Generated_Source\PSoC5/CyLib.c **** { - 2922 .loc 1 2366 0 - 2923 .cfi_startproc - 2924 @ args = 0, pretend = 0, frame = 0 - 2925 @ frame_needed = 0, uses_anonymous_args = 0 - 2926 @ link register save eliminated. - 2927 .LVL169: -2367:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress oldIsr; -2368:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; -2369:.\Generated_Source\PSoC5/CyLib.c **** -2370:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(number <= CY_INT_NUMBER_MAX); -2371:.\Generated_Source\PSoC5/CyLib.c **** -2372:.\Generated_Source\PSoC5/CyLib.c **** /* Save old Interrupt service routine. */ -2373:.\Generated_Source\PSoC5/CyLib.c **** oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]; - 2928 .loc 1 2373 0 - 2929 0000 054B ldr r3, .L301 - 2930 .LVL170: - 2931 0002 00F01F00 and r0, r0, #31 - 2932 .LVL171: - 2933 0006 1B68 ldr r3, [r3, #0] - 2934 .LVL172: - 2935 0008 00F11002 add r2, r0, #16 - 2936 000c 53F82200 ldr r0, [r3, r2, lsl #2] - 2937 .LVL173: -2374:.\Generated_Source\PSoC5/CyLib.c **** -2375:.\Generated_Source\PSoC5/CyLib.c **** /* Set new Interrupt service routine. */ -2376:.\Generated_Source\PSoC5/CyLib.c **** ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address; - 2938 .loc 1 2376 0 - 2939 0010 43F82210 str r1, [r3, r2, lsl #2] -2377:.\Generated_Source\PSoC5/CyLib.c **** -2378:.\Generated_Source\PSoC5/CyLib.c **** return (oldIsr); -2379:.\Generated_Source\PSoC5/CyLib.c **** } - 2940 .loc 1 2379 0 - 2941 0014 7047 bx lr - 2942 .L302: - 2943 0016 00BF .align 2 - 2944 .L301: - 2945 0018 08ED00E0 .word -536810232 - 2946 .cfi_endproc - 2947 .LFE59: - 2948 .size CyIntSetVector, .-CyIntSetVector - 2949 .section .text.CyIntGetVector,"ax",%progbits - 2950 .align 1 - 2951 .global CyIntGetVector - 2952 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 98 - - - 2953 .thumb_func - 2954 .type CyIntGetVector, %function - 2955 CyIntGetVector: - 2956 .LFB60: -2380:.\Generated_Source\PSoC5/CyLib.c **** -2381:.\Generated_Source\PSoC5/CyLib.c **** -2382:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2383:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntGetVector -2384:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2385:.\Generated_Source\PSoC5/CyLib.c **** * -2386:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2387:.\Generated_Source\PSoC5/CyLib.c **** * Gets the interrupt vector of the specified interrupt number. -2388:.\Generated_Source\PSoC5/CyLib.c **** * -2389:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2390:.\Generated_Source\PSoC5/CyLib.c **** * number: Valid range [0-31]. Interrupt number -2391:.\Generated_Source\PSoC5/CyLib.c **** * -2392:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2393:.\Generated_Source\PSoC5/CyLib.c **** * Address of the ISR in the interrupt vector table. -2394:.\Generated_Source\PSoC5/CyLib.c **** * -2395:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2396:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress CyIntGetVector(uint8 number) -2397:.\Generated_Source\PSoC5/CyLib.c **** { - 2957 .loc 1 2397 0 - 2958 .cfi_startproc - 2959 @ args = 0, pretend = 0, frame = 0 - 2960 @ frame_needed = 0, uses_anonymous_args = 0 - 2961 @ link register save eliminated. - 2962 .LVL174: -2398:.\Generated_Source\PSoC5/CyLib.c **** cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; -2399:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(number <= CY_INT_NUMBER_MAX); -2400:.\Generated_Source\PSoC5/CyLib.c **** -2401:.\Generated_Source\PSoC5/CyLib.c **** return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); - 2963 .loc 1 2401 0 - 2964 0000 034B ldr r3, .L304 - 2965 .LVL175: - 2966 0002 00F01F00 and r0, r0, #31 - 2967 .LVL176: - 2968 0006 1968 ldr r1, [r3, #0] - 2969 0008 1030 adds r0, r0, #16 -2402:.\Generated_Source\PSoC5/CyLib.c **** } - 2970 .loc 1 2402 0 - 2971 000a 51F82000 ldr r0, [r1, r0, lsl #2] - 2972 000e 7047 bx lr - 2973 .L305: - 2974 .align 2 - 2975 .L304: - 2976 0010 08ED00E0 .word -536810232 - 2977 .cfi_endproc - 2978 .LFE60: - 2979 .size CyIntGetVector, .-CyIntGetVector - 2980 .section .text.CyIntSetPriority,"ax",%progbits - 2981 .align 1 - 2982 .global CyIntSetPriority - 2983 .thumb - 2984 .thumb_func - 2985 .type CyIntSetPriority, %function - 2986 CyIntSetPriority: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 99 - - - 2987 .LFB61: -2403:.\Generated_Source\PSoC5/CyLib.c **** -2404:.\Generated_Source\PSoC5/CyLib.c **** -2405:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2406:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntSetPriority -2407:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2408:.\Generated_Source\PSoC5/CyLib.c **** * -2409:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2410:.\Generated_Source\PSoC5/CyLib.c **** * Sets the Priority of the Interrupt. -2411:.\Generated_Source\PSoC5/CyLib.c **** * -2412:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2413:.\Generated_Source\PSoC5/CyLib.c **** * priority: Priority of the interrupt. 0 - 7, 0 being the highest. -2414:.\Generated_Source\PSoC5/CyLib.c **** * number: The number of the interrupt, 0 - 31. -2415:.\Generated_Source\PSoC5/CyLib.c **** * -2416:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2417:.\Generated_Source\PSoC5/CyLib.c **** * None -2418:.\Generated_Source\PSoC5/CyLib.c **** * -2419:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2420:.\Generated_Source\PSoC5/CyLib.c **** void CyIntSetPriority(uint8 number, uint8 priority) -2421:.\Generated_Source\PSoC5/CyLib.c **** { - 2988 .loc 1 2421 0 - 2989 .cfi_startproc - 2990 @ args = 0, pretend = 0, frame = 0 - 2991 @ frame_needed = 0, uses_anonymous_args = 0 - 2992 @ link register save eliminated. - 2993 .LVL177: -2422:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(priority <= CY_INT_PRIORITY_MAX); -2423:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(number <= CY_INT_NUMBER_MAX); -2424:.\Generated_Source\PSoC5/CyLib.c **** CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; - 2994 .loc 1 2424 0 - 2995 0000 00F01F00 and r0, r0, #31 - 2996 .LVL178: - 2997 0004 00F16043 add r3, r0, #-536870912 - 2998 0008 4901 lsls r1, r1, #5 - 2999 .LVL179: - 3000 000a 03F56442 add r2, r3, #58368 - 3001 000e C8B2 uxtb r0, r1 - 3002 0010 1070 strb r0, [r2, #0] - 3003 0012 7047 bx lr - 3004 .cfi_endproc - 3005 .LFE61: - 3006 .size CyIntSetPriority, .-CyIntSetPriority - 3007 .section .text.CyIntGetPriority,"ax",%progbits - 3008 .align 1 - 3009 .global CyIntGetPriority - 3010 .thumb - 3011 .thumb_func - 3012 .type CyIntGetPriority, %function - 3013 CyIntGetPriority: - 3014 .LFB62: -2425:.\Generated_Source\PSoC5/CyLib.c **** } -2426:.\Generated_Source\PSoC5/CyLib.c **** -2427:.\Generated_Source\PSoC5/CyLib.c **** -2428:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2429:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntGetPriority -2430:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2431:.\Generated_Source\PSoC5/CyLib.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 100 - - -2432:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2433:.\Generated_Source\PSoC5/CyLib.c **** * Gets the Priority of the Interrupt. -2434:.\Generated_Source\PSoC5/CyLib.c **** * -2435:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: -2436:.\Generated_Source\PSoC5/CyLib.c **** * number: The number of the interrupt, 0 - 31. -2437:.\Generated_Source\PSoC5/CyLib.c **** * -2438:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2439:.\Generated_Source\PSoC5/CyLib.c **** * Priority of the interrupt. 0 - 7, 0 being the highest. -2440:.\Generated_Source\PSoC5/CyLib.c **** * -2441:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2442:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyIntGetPriority(uint8 number) -2443:.\Generated_Source\PSoC5/CyLib.c **** { - 3015 .loc 1 2443 0 - 3016 .cfi_startproc - 3017 @ args = 0, pretend = 0, frame = 0 - 3018 @ frame_needed = 0, uses_anonymous_args = 0 - 3019 @ link register save eliminated. - 3020 .LVL180: -2444:.\Generated_Source\PSoC5/CyLib.c **** uint8 priority; -2445:.\Generated_Source\PSoC5/CyLib.c **** -2446:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(number <= CY_INT_NUMBER_MAX); -2447:.\Generated_Source\PSoC5/CyLib.c **** -2448:.\Generated_Source\PSoC5/CyLib.c **** priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; - 3021 .loc 1 2448 0 - 3022 0000 00F01F00 and r0, r0, #31 - 3023 .LVL181: - 3024 0004 00F16043 add r3, r0, #-536870912 - 3025 0008 03F56441 add r1, r3, #58368 - 3026 000c 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 3027 .LVL182: -2449:.\Generated_Source\PSoC5/CyLib.c **** -2450:.\Generated_Source\PSoC5/CyLib.c **** return (priority); -2451:.\Generated_Source\PSoC5/CyLib.c **** } - 3028 .loc 1 2451 0 - 3029 000e 5009 lsrs r0, r2, #5 - 3030 0010 7047 bx lr - 3031 .cfi_endproc - 3032 .LFE62: - 3033 .size CyIntGetPriority, .-CyIntGetPriority - 3034 .section .text.CyIntGetState,"ax",%progbits - 3035 .align 1 - 3036 .global CyIntGetState - 3037 .thumb - 3038 .thumb_func - 3039 .type CyIntGetState, %function - 3040 CyIntGetState: - 3041 .LFB63: -2452:.\Generated_Source\PSoC5/CyLib.c **** -2453:.\Generated_Source\PSoC5/CyLib.c **** -2454:.\Generated_Source\PSoC5/CyLib.c **** /******************************************************************************* -2455:.\Generated_Source\PSoC5/CyLib.c **** * Function Name: CyIntGetState -2456:.\Generated_Source\PSoC5/CyLib.c **** ******************************************************************************** -2457:.\Generated_Source\PSoC5/CyLib.c **** * -2458:.\Generated_Source\PSoC5/CyLib.c **** * Summary: -2459:.\Generated_Source\PSoC5/CyLib.c **** * Gets the enable state of the specified interrupt number. -2460:.\Generated_Source\PSoC5/CyLib.c **** * -2461:.\Generated_Source\PSoC5/CyLib.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 101 - - -2462:.\Generated_Source\PSoC5/CyLib.c **** * number: Valid range [0-31]. Interrupt number. -2463:.\Generated_Source\PSoC5/CyLib.c **** * -2464:.\Generated_Source\PSoC5/CyLib.c **** * Return: -2465:.\Generated_Source\PSoC5/CyLib.c **** * Enable status: 1 if enabled, 0 if disabled -2466:.\Generated_Source\PSoC5/CyLib.c **** * -2467:.\Generated_Source\PSoC5/CyLib.c **** *******************************************************************************/ -2468:.\Generated_Source\PSoC5/CyLib.c **** uint8 CyIntGetState(uint8 number) -2469:.\Generated_Source\PSoC5/CyLib.c **** { - 3042 .loc 1 2469 0 - 3043 .cfi_startproc - 3044 @ args = 0, pretend = 0, frame = 0 - 3045 @ frame_needed = 0, uses_anonymous_args = 0 - 3046 @ link register save eliminated. - 3047 .LVL183: -2470:.\Generated_Source\PSoC5/CyLib.c **** reg32 * stateReg; -2471:.\Generated_Source\PSoC5/CyLib.c **** -2472:.\Generated_Source\PSoC5/CyLib.c **** CYASSERT(number <= CY_INT_NUMBER_MAX); -2473:.\Generated_Source\PSoC5/CyLib.c **** -2474:.\Generated_Source\PSoC5/CyLib.c **** /* Get a pointer to the Interrupt enable register. */ -2475:.\Generated_Source\PSoC5/CyLib.c **** stateReg = CY_INT_ENABLE_PTR; -2476:.\Generated_Source\PSoC5/CyLib.c **** -2477:.\Generated_Source\PSoC5/CyLib.c **** /* Get the state of the interrupt. */ -2478:.\Generated_Source\PSoC5/CyLib.c **** return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8) - 3048 .loc 1 2478 0 - 3049 0000 044B ldr r3, .L309 - 3050 0002 00F01F00 and r0, r0, #31 - 3051 .LVL184: - 3052 0006 1968 ldr r1, [r3, #0] - 3053 0008 21FA00F2 lsr r2, r1, r0 -2479:.\Generated_Source\PSoC5/CyLib.c **** } - 3054 .loc 1 2479 0 - 3055 000c 02F00100 and r0, r2, #1 - 3056 0010 7047 bx lr - 3057 .L310: - 3058 0012 00BF .align 2 - 3059 .L309: - 3060 0014 00E100E0 .word -536813312 - 3061 .cfi_endproc - 3062 .LFE63: - 3063 .size CyIntGetState, .-CyIntGetState - 3064 .global cydelay_32k_ms - 3065 .global cydelay_freq_mhz - 3066 .global cydelay_freq_khz - 3067 .global cydelay_freq_hz - 3068 .global CyResetStatus - 3069 .data - 3070 .align 2 - 3071 .set .LANCHOR0,. + 0 - 3072 .type cydelay_32k_ms, %object - 3073 .size cydelay_32k_ms, 4 - 3074 cydelay_32k_ms: - 3075 0000 0000007D .word 2097152000 - 3076 .type cydelay_freq_khz, %object - 3077 .size cydelay_freq_khz, 4 - 3078 cydelay_freq_khz: - 3079 0004 00FA0000 .word 64000 - 3080 .type cydelay_freq_mhz, %object - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 102 - - - 3081 .size cydelay_freq_mhz, 1 - 3082 cydelay_freq_mhz: - 3083 0008 40 .byte 64 - 3084 0009 000000 .space 3 - 3085 .type cydelay_freq_hz, %object - 3086 .size cydelay_freq_hz, 4 - 3087 cydelay_freq_hz: - 3088 000c 0090D003 .word 64000000 - 3089 .section .noinit,"aw",%progbits - 3090 .type CyResetStatus, %object - 3091 .size CyResetStatus, 1 - 3092 CyResetStatus: - 3093 0000 00 .space 1 - 3094 .text - 3095 .Letext0: - 3096 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 3097 .file 3 ".\\Generated_Source\\PSoC5\\CyLib.h" - 3098 .file 4 ".\\Generated_Source\\PSoC5\\cyPm.h" - 3099 .section .debug_info,"",%progbits - 3100 .Ldebug_info0: - 3101 0000 BC0F0000 .4byte 0xfbc - 3102 0004 0200 .2byte 0x2 - 3103 0006 00000000 .4byte .Ldebug_abbrev0 - 3104 000a 04 .byte 0x4 - 3105 000b 01 .uleb128 0x1 - 3106 000c 52050000 .4byte .LASF134 - 3107 0010 01 .byte 0x1 - 3108 0011 82040000 .4byte .LASF135 - 3109 0015 A0030000 .4byte .LASF136 - 3110 0019 00000000 .4byte .Ldebug_ranges0+0 - 3111 001d 00000000 .4byte 0 - 3112 0021 00000000 .4byte 0 - 3113 0025 00000000 .4byte .Ldebug_line0 - 3114 0029 02 .uleb128 0x2 - 3115 002a 01 .byte 0x1 - 3116 002b 06 .byte 0x6 - 3117 002c 25010000 .4byte .LASF0 - 3118 0030 02 .uleb128 0x2 - 3119 0031 01 .byte 0x1 - 3120 0032 08 .byte 0x8 - 3121 0033 C5050000 .4byte .LASF1 - 3122 0037 02 .uleb128 0x2 - 3123 0038 02 .byte 0x2 - 3124 0039 05 .byte 0x5 - 3125 003a E1050000 .4byte .LASF2 - 3126 003e 02 .uleb128 0x2 - 3127 003f 02 .byte 0x2 - 3128 0040 07 .byte 0x7 - 3129 0041 C7020000 .4byte .LASF3 - 3130 0045 03 .uleb128 0x3 - 3131 0046 04 .byte 0x4 - 3132 0047 05 .byte 0x5 - 3133 0048 696E7400 .ascii "int\000" - 3134 004c 02 .uleb128 0x2 - 3135 004d 04 .byte 0x4 - 3136 004e 07 .byte 0x7 - 3137 004f 1F020000 .4byte .LASF4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 103 - - - 3138 0053 02 .uleb128 0x2 - 3139 0054 08 .byte 0x8 - 3140 0055 05 .byte 0x5 - 3141 0056 17010000 .4byte .LASF5 - 3142 005a 02 .uleb128 0x2 - 3143 005b 08 .byte 0x8 - 3144 005c 07 .byte 0x7 - 3145 005d A4000000 .4byte .LASF6 - 3146 0061 02 .uleb128 0x2 - 3147 0062 04 .byte 0x4 - 3148 0063 05 .byte 0x5 - 3149 0064 6A010000 .4byte .LASF7 - 3150 0068 02 .uleb128 0x2 - 3151 0069 04 .byte 0x4 - 3152 006a 07 .byte 0x7 - 3153 006b 0E040000 .4byte .LASF8 - 3154 006f 02 .uleb128 0x2 - 3155 0070 04 .byte 0x4 - 3156 0071 07 .byte 0x7 - 3157 0072 59020000 .4byte .LASF9 - 3158 0076 04 .uleb128 0x4 - 3159 0077 01 .byte 0x1 - 3160 0078 05 .uleb128 0x5 - 3161 0079 04 .byte 0x4 - 3162 007a 76000000 .4byte 0x76 - 3163 007e 02 .uleb128 0x2 - 3164 007f 01 .byte 0x1 - 3165 0080 08 .byte 0x8 - 3166 0081 85060000 .4byte .LASF10 - 3167 0085 06 .uleb128 0x6 - 3168 0086 8D010000 .4byte .LASF11 - 3169 008a 02 .byte 0x2 - 3170 008b 5B .byte 0x5b - 3171 008c 30000000 .4byte 0x30 - 3172 0090 06 .uleb128 0x6 - 3173 0091 15000000 .4byte .LASF12 - 3174 0095 02 .byte 0x2 - 3175 0096 5C .byte 0x5c - 3176 0097 3E000000 .4byte 0x3e - 3177 009b 06 .uleb128 0x6 - 3178 009c DC010000 .4byte .LASF13 - 3179 00a0 02 .byte 0x2 - 3180 00a1 5D .byte 0x5d - 3181 00a2 6F000000 .4byte 0x6f - 3182 00a6 02 .uleb128 0x2 - 3183 00a7 04 .byte 0x4 - 3184 00a8 04 .byte 0x4 - 3185 00a9 C2040000 .4byte .LASF14 - 3186 00ad 02 .uleb128 0x2 - 3187 00ae 08 .byte 0x8 - 3188 00af 04 .byte 0x4 - 3189 00b0 AD010000 .4byte .LASF15 - 3190 00b4 06 .uleb128 0x6 - 3191 00b5 A6070000 .4byte .LASF16 - 3192 00b9 02 .byte 0x2 - 3193 00ba E8 .byte 0xe8 - 3194 00bb 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 104 - - - 3195 00bf 06 .uleb128 0x6 - 3196 00c0 9B050000 .4byte .LASF17 - 3197 00c4 02 .byte 0x2 - 3198 00c5 F0 .byte 0xf0 - 3199 00c6 CA000000 .4byte 0xca - 3200 00ca 07 .uleb128 0x7 - 3201 00cb 85000000 .4byte 0x85 - 3202 00cf 06 .uleb128 0x6 - 3203 00d0 87010000 .4byte .LASF18 - 3204 00d4 02 .byte 0x2 - 3205 00d5 F1 .byte 0xf1 - 3206 00d6 DA000000 .4byte 0xda - 3207 00da 07 .uleb128 0x7 - 3208 00db 90000000 .4byte 0x90 - 3209 00df 06 .uleb128 0x6 - 3210 00e0 DE030000 .4byte .LASF19 - 3211 00e4 02 .byte 0x2 - 3212 00e5 F2 .byte 0xf2 - 3213 00e6 EA000000 .4byte 0xea - 3214 00ea 07 .uleb128 0x7 - 3215 00eb 9B000000 .4byte 0x9b - 3216 00ef 08 .uleb128 0x8 - 3217 00f0 8F060000 .4byte .LASF20 - 3218 00f4 02 .byte 0x2 - 3219 00f5 0201 .2byte 0x102 - 3220 00f7 78000000 .4byte 0x78 - 3221 00fb 09 .uleb128 0x9 - 3222 00fc 01 .byte 0x1 - 3223 00fd A3040000 .4byte .LASF131 - 3224 0101 01 .byte 0x1 - 3225 0102 0B03 .2byte 0x30b - 3226 0104 01 .byte 0x1 - 3227 0105 01 .byte 0x1 - 3228 0106 17010000 .4byte 0x117 - 3229 010a 0A .uleb128 0xa - 3230 010b 9E070000 .4byte .LASF24 - 3231 010f 01 .byte 0x1 - 3232 0110 0B03 .2byte 0x30b - 3233 0112 85000000 .4byte 0x85 - 3234 0116 00 .byte 0 - 3235 0117 0B .uleb128 0xb - 3236 0118 01 .byte 0x1 - 3237 0119 7A070000 .4byte .LASF129 - 3238 011d 01 .byte 0x1 - 3239 011e E004 .2byte 0x4e0 - 3240 0120 01 .byte 0x1 - 3241 0121 85000000 .4byte 0x85 - 3242 0125 01 .byte 0x1 - 3243 0126 0C .uleb128 0xc - 3244 0127 46020000 .4byte .LASF137 - 3245 012b 01 .byte 0x1 - 3246 012c 6E01 .2byte 0x16e - 3247 012e 01 .byte 0x1 - 3248 012f 85000000 .4byte 0x85 - 3249 0133 01 .byte 0x1 - 3250 0134 45010000 .4byte 0x145 - 3251 0138 0D .uleb128 0xd - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 105 - - - 3252 0139 27060000 .4byte .LASF138 - 3253 013d 01 .byte 0x1 - 3254 013e 7001 .2byte 0x170 - 3255 0140 85000000 .4byte 0x85 - 3256 0144 00 .byte 0 - 3257 0145 0E .uleb128 0xe - 3258 0146 D9000000 .4byte .LASF21 - 3259 014a 01 .byte 0x1 - 3260 014b 8D01 .2byte 0x18d - 3261 014d 01 .byte 0x1 - 3262 014e 00000000 .4byte .LFB7 - 3263 0152 B8000000 .4byte .LFE7 - 3264 0156 02 .byte 0x2 - 3265 0157 7D .byte 0x7d - 3266 0158 00 .sleb128 0 - 3267 0159 01 .byte 0x1 - 3268 015a A1010000 .4byte 0x1a1 - 3269 015e 0F .uleb128 0xf - 3270 015f 31010000 .4byte .LASF23 - 3271 0163 01 .byte 0x1 - 3272 0164 8D01 .2byte 0x18d - 3273 0166 85000000 .4byte 0x85 - 3274 016a 00000000 .4byte .LLST0 - 3275 016e 10 .uleb128 0x10 - 3276 016f 69040000 .4byte .LASF37 - 3277 0173 01 .byte 0x1 - 3278 0174 8F01 .2byte 0x18f - 3279 0176 85000000 .4byte 0x85 - 3280 017a 01 .byte 0x1 - 3281 017b 53 .byte 0x53 - 3282 017c 11 .uleb128 0x11 - 3283 017d 26010000 .4byte 0x126 - 3284 0181 00000000 .4byte .LBB10 - 3285 0185 2A000000 .4byte .LBE10 - 3286 0189 01 .byte 0x1 - 3287 018a 8F01 .2byte 0x18f - 3288 018c 12 .uleb128 0x12 - 3289 018d 00000000 .4byte .LBB11 - 3290 0191 2A000000 .4byte .LBE11 - 3291 0195 13 .uleb128 0x13 - 3292 0196 38010000 .4byte 0x138 - 3293 019a 3A000000 .4byte .LLST1 - 3294 019e 00 .byte 0 - 3295 019f 00 .byte 0 - 3296 01a0 00 .byte 0 - 3297 01a1 0E .uleb128 0xe - 3298 01a2 71030000 .4byte .LASF22 - 3299 01a6 01 .byte 0x1 - 3300 01a7 2103 .2byte 0x321 - 3301 01a9 01 .byte 0x1 - 3302 01aa 00000000 .4byte .LFB14 - 3303 01ae 3C000000 .4byte .LFE14 - 3304 01b2 02 .byte 0x2 - 3305 01b3 7D .byte 0x7d - 3306 01b4 00 .sleb128 0 - 3307 01b5 01 .byte 0x1 - 3308 01b6 CB010000 .4byte 0x1cb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 106 - - - 3309 01ba 0F .uleb128 0xf - 3310 01bb 9E070000 .4byte .LASF24 - 3311 01bf 01 .byte 0x1 - 3312 01c0 2103 .2byte 0x321 - 3313 01c2 90000000 .4byte 0x90 - 3314 01c6 5A000000 .4byte .LLST2 - 3315 01ca 00 .byte 0 - 3316 01cb 14 .uleb128 0x14 - 3317 01cc 01 .byte 0x1 - 3318 01cd 37040000 .4byte .LASF31 - 3319 01d1 01 .byte 0x1 - 3320 01d2 99 .byte 0x99 - 3321 01d3 01 .byte 0x1 - 3322 01d4 00000000 .4byte .LFB1 - 3323 01d8 10000000 .4byte .LFE1 - 3324 01dc 02 .byte 0x2 - 3325 01dd 7D .byte 0x7d - 3326 01de 00 .sleb128 0 - 3327 01df 01 .byte 0x1 - 3328 01e0 15 .uleb128 0x15 - 3329 01e1 01 .byte 0x1 - 3330 01e2 B4010000 .4byte .LASF28 - 3331 01e6 01 .byte 0x1 - 3332 01e7 BF .byte 0xbf - 3333 01e8 01 .byte 0x1 - 3334 01e9 00000000 .4byte .LFB2 - 3335 01ed 34000000 .4byte .LFE2 - 3336 01f1 02 .byte 0x2 - 3337 01f2 7D .byte 0x7d - 3338 01f3 00 .sleb128 0 - 3339 01f4 01 .byte 0x1 - 3340 01f5 27020000 .4byte 0x227 - 3341 01f9 16 .uleb128 0x16 - 3342 01fa 67070000 .4byte .LASF25 - 3343 01fe 01 .byte 0x1 - 3344 01ff BF .byte 0xbf - 3345 0200 85000000 .4byte 0x85 - 3346 0204 7B000000 .4byte .LLST3 - 3347 0208 16 .uleb128 0x16 - 3348 0209 D8060000 .4byte .LASF26 - 3349 020d 01 .byte 0x1 - 3350 020e BF .byte 0xbf - 3351 020f 85000000 .4byte 0x85 - 3352 0213 A8000000 .4byte .LLST4 - 3353 0217 16 .uleb128 0x16 - 3354 0218 BA040000 .4byte .LASF27 - 3355 021c 01 .byte 0x1 - 3356 021d BF .byte 0xbf - 3357 021e 85000000 .4byte 0x85 - 3358 0222 C9000000 .4byte .LLST5 - 3359 0226 00 .byte 0 - 3360 0227 15 .uleb128 0x15 - 3361 0228 01 .byte 0x1 - 3362 0229 73010000 .4byte .LASF29 - 3363 022d 01 .byte 0x1 - 3364 022e F6 .byte 0xf6 - 3365 022f 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 107 - - - 3366 0230 00000000 .4byte .LFB3 - 3367 0234 14000000 .4byte .LFE3 - 3368 0238 02 .byte 0x2 - 3369 0239 7D .byte 0x7d - 3370 023a 00 .sleb128 0 - 3371 023b 01 .byte 0x1 - 3372 023c 50020000 .4byte 0x250 - 3373 0240 16 .uleb128 0x16 - 3374 0241 07040000 .4byte .LASF30 - 3375 0245 01 .byte 0x1 - 3376 0246 F6 .byte 0xf6 - 3377 0247 85000000 .4byte 0x85 - 3378 024b EA000000 .4byte .LLST6 - 3379 024f 00 .byte 0 - 3380 0250 17 .uleb128 0x17 - 3381 0251 01 .byte 0x1 - 3382 0252 BC020000 .4byte .LASF32 - 3383 0256 01 .byte 0x1 - 3384 0257 5901 .2byte 0x159 - 3385 0259 01 .byte 0x1 - 3386 025a 00000000 .4byte .LFB5 - 3387 025e 18000000 .4byte .LFE5 - 3388 0262 02 .byte 0x2 - 3389 0263 7D .byte 0x7d - 3390 0264 00 .sleb128 0 - 3391 0265 01 .byte 0x1 - 3392 0266 18 .uleb128 0x18 - 3393 0267 01 .byte 0x1 - 3394 0268 2C020000 .4byte .LASF33 - 3395 026c 01 .byte 0x1 - 3396 026d 8702 .2byte 0x287 - 3397 026f 01 .byte 0x1 - 3398 0270 00000000 .4byte .LFB9 - 3399 0274 40000000 .4byte .LFE9 - 3400 0278 02 .byte 0x2 - 3401 0279 7D .byte 0x7d - 3402 027a 00 .sleb128 0 - 3403 027b 01 .byte 0x1 - 3404 027c 91020000 .4byte 0x291 - 3405 0280 0F .uleb128 0xf - 3406 0281 07040000 .4byte .LASF30 - 3407 0285 01 .byte 0x1 - 3408 0286 8702 .2byte 0x287 - 3409 0288 85000000 .4byte 0x85 - 3410 028c 0B010000 .4byte .LLST7 - 3411 0290 00 .byte 0 - 3412 0291 17 .uleb128 0x17 - 3413 0292 01 .byte 0x1 - 3414 0293 6F000000 .4byte .LASF34 - 3415 0297 01 .byte 0x1 - 3416 0298 B002 .2byte 0x2b0 - 3417 029a 01 .byte 0x1 - 3418 029b 00000000 .4byte .LFB10 - 3419 029f 10000000 .4byte .LFE10 - 3420 02a3 02 .byte 0x2 - 3421 02a4 7D .byte 0x7d - 3422 02a5 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 108 - - - 3423 02a6 01 .byte 0x1 - 3424 02a7 17 .uleb128 0x17 - 3425 02a8 01 .byte 0x1 - 3426 02a9 9C060000 .4byte .LASF35 - 3427 02ad 01 .byte 0x1 - 3428 02ae C502 .2byte 0x2c5 - 3429 02b0 01 .byte 0x1 - 3430 02b1 00000000 .4byte .LFB11 - 3431 02b5 10000000 .4byte .LFE11 - 3432 02b9 02 .byte 0x2 - 3433 02ba 7D .byte 0x7d - 3434 02bb 00 .sleb128 0 - 3435 02bc 01 .byte 0x1 - 3436 02bd 19 .uleb128 0x19 - 3437 02be 01 .byte 0x1 - 3438 02bf 6C070000 .4byte .LASF36 - 3439 02c3 01 .byte 0x1 - 3440 02c4 EC01 .2byte 0x1ec - 3441 02c6 01 .byte 0x1 - 3442 02c7 00000000 .4byte .LFB8 - 3443 02cb D8000000 .4byte .LFE8 - 3444 02cf 5E010000 .4byte .LLST8 - 3445 02d3 01 .byte 0x1 - 3446 02d4 3E030000 .4byte 0x33e - 3447 02d8 0F .uleb128 0xf - 3448 02d9 31010000 .4byte .LASF23 - 3449 02dd 01 .byte 0x1 - 3450 02de EC01 .2byte 0x1ec - 3451 02e0 85000000 .4byte 0x85 - 3452 02e4 7E010000 .4byte .LLST9 - 3453 02e8 1A .uleb128 0x1a - 3454 02e9 0C070000 .4byte .LASF38 - 3455 02ed 01 .byte 0x1 - 3456 02ee EE01 .2byte 0x1ee - 3457 02f0 85000000 .4byte 0x85 - 3458 02f4 9F010000 .4byte .LLST10 - 3459 02f8 10 .uleb128 0x10 - 3460 02f9 75060000 .4byte .LASF39 - 3461 02fd 01 .byte 0x1 - 3462 02fe EF01 .2byte 0x1ef - 3463 0300 85000000 .4byte 0x85 - 3464 0304 01 .byte 0x1 - 3465 0305 56 .byte 0x56 - 3466 0306 1B .uleb128 0x1b - 3467 0307 34000000 .4byte .LVL28 - 3468 030b 45010000 .4byte 0x145 - 3469 030f 1A030000 .4byte 0x31a - 3470 0313 1C .uleb128 0x1c - 3471 0314 01 .byte 0x1 - 3472 0315 50 .byte 0x50 - 3473 0316 02 .byte 0x2 - 3474 0317 74 .byte 0x74 - 3475 0318 00 .sleb128 0 - 3476 0319 00 .byte 0 - 3477 031a 1D .uleb128 0x1d - 3478 031b BE000000 .4byte .LVL29 - 3479 031f 91020000 .4byte 0x291 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 109 - - - 3480 0323 1D .uleb128 0x1d - 3481 0324 C4000000 .4byte .LVL30 - 3482 0328 A7020000 .4byte 0x2a7 - 3483 032c 1E .uleb128 0x1e - 3484 032d D2000000 .4byte .LVL31 - 3485 0331 01 .byte 0x1 - 3486 0332 45010000 .4byte 0x145 - 3487 0336 1C .uleb128 0x1c - 3488 0337 01 .byte 0x1 - 3489 0338 50 .byte 0x50 - 3490 0339 02 .byte 0x2 - 3491 033a 74 .byte 0x74 - 3492 033b 00 .sleb128 0 - 3493 033c 00 .byte 0 - 3494 033d 00 .byte 0 - 3495 033e 18 .uleb128 0x18 - 3496 033f 01 .byte 0x1 - 3497 0340 08030000 .4byte .LASF40 - 3498 0344 01 .byte 0x1 - 3499 0345 E802 .2byte 0x2e8 - 3500 0347 01 .byte 0x1 - 3501 0348 00000000 .4byte .LFB12 - 3502 034c 18000000 .4byte .LFE12 - 3503 0350 02 .byte 0x2 - 3504 0351 7D .byte 0x7d - 3505 0352 00 .sleb128 0 - 3506 0353 01 .byte 0x1 - 3507 0354 69030000 .4byte 0x369 - 3508 0358 0F .uleb128 0xf - 3509 0359 07040000 .4byte .LASF30 - 3510 035d 01 .byte 0x1 - 3511 035e E802 .2byte 0x2e8 - 3512 0360 85000000 .4byte 0x85 - 3513 0364 C9010000 .4byte .LLST11 - 3514 0368 00 .byte 0 - 3515 0369 1F .uleb128 0x1f - 3516 036a FB000000 .4byte 0xfb - 3517 036e 00000000 .4byte .LFB13 - 3518 0372 0C000000 .4byte .LFE13 - 3519 0376 02 .byte 0x2 - 3520 0377 7D .byte 0x7d - 3521 0378 00 .sleb128 0 - 3522 0379 01 .byte 0x1 - 3523 037a 86030000 .4byte 0x386 - 3524 037e 20 .uleb128 0x20 - 3525 037f 0A010000 .4byte 0x10a - 3526 0383 01 .byte 0x1 - 3527 0384 50 .byte 0x50 - 3528 0385 00 .byte 0 - 3529 0386 19 .uleb128 0x19 - 3530 0387 01 .byte 0x1 - 3531 0388 20070000 .4byte .LASF41 - 3532 038c 01 .byte 0x1 - 3533 038d 5003 .2byte 0x350 - 3534 038f 01 .byte 0x1 - 3535 0390 00000000 .4byte .LFB15 - 3536 0394 6C000000 .4byte .LFE15 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 110 - - - 3537 0398 EA010000 .4byte .LLST12 - 3538 039c 01 .byte 0x1 - 3539 039d 74040000 .4byte 0x474 - 3540 03a1 0F .uleb128 0xf - 3541 03a2 9E070000 .4byte .LASF24 - 3542 03a6 01 .byte 0x1 - 3543 03a7 5003 .2byte 0x350 - 3544 03a9 90000000 .4byte 0x90 - 3545 03ad 0A020000 .4byte .LLST13 - 3546 03b1 1A .uleb128 0x1a - 3547 03b2 45050000 .4byte .LASF42 - 3548 03b6 01 .byte 0x1 - 3549 03b7 5203 .2byte 0x352 - 3550 03b9 85000000 .4byte 0x85 - 3551 03bd 2B020000 .4byte .LLST14 - 3552 03c1 1A .uleb128 0x1a - 3553 03c2 3C020000 .4byte .LASF43 - 3554 03c6 01 .byte 0x1 - 3555 03c7 5303 .2byte 0x353 - 3556 03c9 90000000 .4byte 0x90 - 3557 03cd 49020000 .4byte .LLST15 - 3558 03d1 1A .uleb128 0x1a - 3559 03d2 42010000 .4byte .LASF44 - 3560 03d6 01 .byte 0x1 - 3561 03d7 5403 .2byte 0x354 - 3562 03d9 85000000 .4byte 0x85 - 3563 03dd 93020000 .4byte .LLST16 - 3564 03e1 21 .uleb128 0x21 - 3565 03e2 FB000000 .4byte 0xfb - 3566 03e6 24000000 .4byte .LBB12 - 3567 03ea 2A000000 .4byte .LBE12 - 3568 03ee 01 .byte 0x1 - 3569 03ef 6403 .2byte 0x364 - 3570 03f1 FF030000 .4byte 0x3ff - 3571 03f5 22 .uleb128 0x22 - 3572 03f6 0A010000 .4byte 0x10a - 3573 03fa B1020000 .4byte .LLST17 - 3574 03fe 00 .byte 0 - 3575 03ff 21 .uleb128 0x21 - 3576 0400 FB000000 .4byte 0xfb - 3577 0404 4A000000 .4byte .LBB14 - 3578 0408 50000000 .4byte .LBE14 - 3579 040c 01 .byte 0x1 - 3580 040d 7403 .2byte 0x374 - 3581 040f 1D040000 .4byte 0x41d - 3582 0413 22 .uleb128 0x22 - 3583 0414 0A010000 .4byte 0x10a - 3584 0418 C5020000 .4byte .LLST18 - 3585 041c 00 .byte 0 - 3586 041d 1D .uleb128 0x1d - 3587 041e 08000000 .4byte .LVL36 - 3588 0422 610F0000 .4byte 0xf61 - 3589 0426 1B .uleb128 0x1b - 3590 0427 3A000000 .4byte .LVL46 - 3591 042b A1010000 .4byte 0x1a1 - 3592 042f 3A040000 .4byte 0x43a - 3593 0433 1C .uleb128 0x1c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 111 - - - 3594 0434 01 .byte 0x1 - 3595 0435 50 .byte 0x50 - 3596 0436 02 .byte 0x2 - 3597 0437 74 .byte 0x74 - 3598 0438 00 .sleb128 0 - 3599 0439 00 .byte 0 - 3600 043a 1B .uleb128 0x1b - 3601 043b 42000000 .4byte .LVL48 - 3602 043f A1010000 .4byte 0x1a1 - 3603 0443 4E040000 .4byte 0x44e - 3604 0447 1C .uleb128 0x1c - 3605 0448 01 .byte 0x1 - 3606 0449 50 .byte 0x50 - 3607 044a 02 .byte 0x2 - 3608 044b 74 .byte 0x74 - 3609 044c 00 .sleb128 0 - 3610 044d 00 .byte 0 - 3611 044e 1B .uleb128 0x1b - 3612 044f 56000000 .4byte .LVL51 - 3613 0453 A1010000 .4byte 0x1a1 - 3614 0457 62040000 .4byte 0x462 - 3615 045b 1C .uleb128 0x1c - 3616 045c 01 .byte 0x1 - 3617 045d 50 .byte 0x50 - 3618 045e 02 .byte 0x2 - 3619 045f 74 .byte 0x74 - 3620 0460 00 .sleb128 0 - 3621 0461 00 .byte 0 - 3622 0462 1E .uleb128 0x1e - 3623 0463 60000000 .4byte .LVL52 - 3624 0467 01 .byte 0x1 - 3625 0468 6F0F0000 .4byte 0xf6f - 3626 046c 1C .uleb128 0x1c - 3627 046d 01 .byte 0x1 - 3628 046e 50 .byte 0x50 - 3629 046f 02 .byte 0x2 - 3630 0470 76 .byte 0x76 - 3631 0471 00 .sleb128 0 - 3632 0472 00 .byte 0 - 3633 0473 00 .byte 0 - 3634 0474 18 .uleb128 0x18 - 3635 0475 01 .byte 0x1 - 3636 0476 EA060000 .4byte .LASF45 - 3637 047a 01 .byte 0x1 - 3638 047b B403 .2byte 0x3b4 - 3639 047d 01 .byte 0x1 - 3640 047e 00000000 .4byte .LFB16 - 3641 0482 18000000 .4byte .LFE16 - 3642 0486 02 .byte 0x2 - 3643 0487 7D .byte 0x7d - 3644 0488 00 .sleb128 0 - 3645 0489 01 .byte 0x1 - 3646 048a 9F040000 .4byte 0x49f - 3647 048e 0F .uleb128 0xf - 3648 048f 07040000 .4byte .LASF30 - 3649 0493 01 .byte 0x1 - 3650 0494 B403 .2byte 0x3b4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 112 - - - 3651 0496 85000000 .4byte 0x85 - 3652 049a D8020000 .4byte .LLST19 - 3653 049e 00 .byte 0 - 3654 049f 17 .uleb128 0x17 - 3655 04a0 01 .byte 0x1 - 3656 04a1 51010000 .4byte .LASF46 - 3657 04a5 01 .byte 0x1 - 3658 04a6 CD03 .2byte 0x3cd - 3659 04a8 01 .byte 0x1 - 3660 04a9 00000000 .4byte .LFB17 - 3661 04ad 10000000 .4byte .LFE17 - 3662 04b1 02 .byte 0x2 - 3663 04b2 7D .byte 0x7d - 3664 04b3 00 .sleb128 0 - 3665 04b4 01 .byte 0x1 - 3666 04b5 17 .uleb128 0x17 - 3667 04b6 01 .byte 0x1 - 3668 04b7 C4010000 .4byte .LASF47 - 3669 04bb 01 .byte 0x1 - 3670 04bc E903 .2byte 0x3e9 - 3671 04be 01 .byte 0x1 - 3672 04bf 00000000 .4byte .LFB18 - 3673 04c3 10000000 .4byte .LFE18 - 3674 04c7 02 .byte 0x2 - 3675 04c8 7D .byte 0x7d - 3676 04c9 00 .sleb128 0 - 3677 04ca 01 .byte 0x1 - 3678 04cb 17 .uleb128 0x17 - 3679 04cc 01 .byte 0x1 - 3680 04cd 59040000 .4byte .LASF48 - 3681 04d1 01 .byte 0x1 - 3682 04d2 FE03 .2byte 0x3fe - 3683 04d4 01 .byte 0x1 - 3684 04d5 00000000 .4byte .LFB19 - 3685 04d9 10000000 .4byte .LFE19 - 3686 04dd 02 .byte 0x2 - 3687 04de 7D .byte 0x7d - 3688 04df 00 .sleb128 0 - 3689 04e0 01 .byte 0x1 - 3690 04e1 17 .uleb128 0x17 - 3691 04e2 01 .byte 0x1 - 3692 04e3 59000000 .4byte .LASF49 - 3693 04e7 01 .byte 0x1 - 3694 04e8 1204 .2byte 0x412 - 3695 04ea 01 .byte 0x1 - 3696 04eb 00000000 .4byte .LFB20 - 3697 04ef 10000000 .4byte .LFE20 - 3698 04f3 02 .byte 0x2 - 3699 04f4 7D .byte 0x7d - 3700 04f5 00 .sleb128 0 - 3701 04f6 01 .byte 0x1 - 3702 04f7 19 .uleb128 0x19 - 3703 04f8 01 .byte 0x1 - 3704 04f9 4D000000 .4byte .LASF50 - 3705 04fd 01 .byte 0x1 - 3706 04fe 2801 .2byte 0x128 - 3707 0500 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 113 - - - 3708 0501 00000000 .4byte .LFB4 - 3709 0505 50000000 .4byte .LFE4 - 3710 0509 F9020000 .4byte .LLST20 - 3711 050d 01 .byte 0x1 - 3712 050e 82050000 .4byte 0x582 - 3713 0512 0F .uleb128 0xf - 3714 0513 5F010000 .4byte .LASF51 - 3715 0517 01 .byte 0x1 - 3716 0518 2801 .2byte 0x128 - 3717 051a 85000000 .4byte 0x85 - 3718 051e 19030000 .4byte .LLST21 - 3719 0522 1A .uleb128 0x1a - 3720 0523 68060000 .4byte .LASF52 - 3721 0527 01 .byte 0x1 - 3722 0528 2A01 .2byte 0x12a - 3723 052a 85000000 .4byte 0x85 - 3724 052e 3A030000 .4byte .LLST22 - 3725 0532 1A .uleb128 0x1a - 3726 0533 B7070000 .4byte .LASF53 - 3727 0537 01 .byte 0x1 - 3728 0538 2B01 .2byte 0x12b - 3729 053a 85000000 .4byte 0x85 - 3730 053e 4D030000 .4byte .LLST23 - 3731 0542 1A .uleb128 0x1a - 3732 0543 25000000 .4byte .LASF54 - 3733 0547 01 .byte 0x1 - 3734 0548 2C01 .2byte 0x12c - 3735 054a 85000000 .4byte 0x85 - 3736 054e 60030000 .4byte .LLST24 - 3737 0552 1B .uleb128 0x1b - 3738 0553 30000000 .4byte .LVL60 - 3739 0557 830F0000 .4byte 0xf83 - 3740 055b 65050000 .4byte 0x565 - 3741 055f 1C .uleb128 0x1c - 3742 0560 01 .byte 0x1 - 3743 0561 50 .byte 0x50 - 3744 0562 01 .byte 0x1 - 3745 0563 30 .byte 0x30 - 3746 0564 00 .byte 0 - 3747 0565 1B .uleb128 0x1b - 3748 0566 36000000 .4byte .LVL61 - 3749 056a 970F0000 .4byte 0xf97 - 3750 056e 78050000 .4byte 0x578 - 3751 0572 1C .uleb128 0x1c - 3752 0573 01 .byte 0x1 - 3753 0574 50 .byte 0x50 - 3754 0575 01 .byte 0x1 - 3755 0576 31 .byte 0x31 - 3756 0577 00 .byte 0 - 3757 0578 1D .uleb128 0x1d - 3758 0579 40000000 .4byte .LVL62 - 3759 057d E1040000 .4byte 0x4e1 - 3760 0581 00 .byte 0 - 3761 0582 23 .uleb128 0x23 - 3762 0583 01 .byte 0x1 - 3763 0584 93010000 .4byte .LASF62 - 3764 0588 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 114 - - - 3765 0589 59 .byte 0x59 - 3766 058a 01 .byte 0x1 - 3767 058b B4000000 .4byte 0xb4 - 3768 058f 00000000 .4byte .LFB0 - 3769 0593 68000000 .4byte .LFE0 - 3770 0597 7E030000 .4byte .LLST25 - 3771 059b 01 .byte 0x1 - 3772 059c 1B060000 .4byte 0x61b - 3773 05a0 16 .uleb128 0x16 - 3774 05a1 5F010000 .4byte .LASF51 - 3775 05a5 01 .byte 0x1 - 3776 05a6 59 .byte 0x59 - 3777 05a7 85000000 .4byte 0x85 - 3778 05ab 9E030000 .4byte .LLST26 - 3779 05af 24 .uleb128 0x24 - 3780 05b0 50070000 .4byte .LASF55 - 3781 05b4 01 .byte 0x1 - 3782 05b5 5B .byte 0x5b - 3783 05b6 B4000000 .4byte 0xb4 - 3784 05ba D8030000 .4byte .LLST27 - 3785 05be 24 .uleb128 0x24 - 3786 05bf EB050000 .4byte .LASF56 - 3787 05c3 01 .byte 0x1 - 3788 05c4 5D .byte 0x5d - 3789 05c5 85000000 .4byte 0x85 - 3790 05c9 1A040000 .4byte .LLST28 - 3791 05cd 24 .uleb128 0x24 - 3792 05ce BB000000 .4byte .LASF57 - 3793 05d2 01 .byte 0x1 - 3794 05d3 5E .byte 0x5e - 3795 05d4 85000000 .4byte 0x85 - 3796 05d8 38040000 .4byte .LLST29 - 3797 05dc 24 .uleb128 0x24 - 3798 05dd D3050000 .4byte .LASF58 - 3799 05e1 01 .byte 0x1 - 3800 05e2 5F .byte 0x5f - 3801 05e3 85000000 .4byte 0x85 - 3802 05e7 4B040000 .4byte .LLST30 - 3803 05eb 1B .uleb128 0x1b - 3804 05ec 26000000 .4byte .LVL69 - 3805 05f0 830F0000 .4byte 0xf83 - 3806 05f4 FE050000 .4byte 0x5fe - 3807 05f8 1C .uleb128 0x1c - 3808 05f9 01 .byte 0x1 - 3809 05fa 50 .byte 0x50 - 3810 05fb 01 .byte 0x1 - 3811 05fc 48 .byte 0x48 - 3812 05fd 00 .byte 0 - 3813 05fe 1B .uleb128 0x1b - 3814 05ff 2C000000 .4byte .LVL70 - 3815 0603 970F0000 .4byte 0xf97 - 3816 0607 11060000 .4byte 0x611 - 3817 060b 1C .uleb128 0x1c - 3818 060c 01 .byte 0x1 - 3819 060d 50 .byte 0x50 - 3820 060e 01 .byte 0x1 - 3821 060f 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 115 - - - 3822 0610 00 .byte 0 - 3823 0611 1D .uleb128 0x1d - 3824 0612 4C000000 .4byte .LVL72 - 3825 0616 E1040000 .4byte 0x4e1 - 3826 061a 00 .byte 0 - 3827 061b 17 .uleb128 0x17 - 3828 061c 01 .byte 0x1 - 3829 061d F8040000 .4byte .LASF59 - 3830 0621 01 .byte 0x1 - 3831 0622 2904 .2byte 0x429 - 3832 0624 01 .byte 0x1 - 3833 0625 00000000 .4byte .LFB21 - 3834 0629 10000000 .4byte .LFE21 - 3835 062d 02 .byte 0x2 - 3836 062e 7D .byte 0x7d - 3837 062f 00 .sleb128 0 - 3838 0630 01 .byte 0x1 - 3839 0631 17 .uleb128 0x17 - 3840 0632 01 .byte 0x1 - 3841 0633 24050000 .4byte .LASF60 - 3842 0637 01 .byte 0x1 - 3843 0638 4104 .2byte 0x441 - 3844 063a 01 .byte 0x1 - 3845 063b 00000000 .4byte .LFB22 - 3846 063f 10000000 .4byte .LFE22 - 3847 0643 02 .byte 0x2 - 3848 0644 7D .byte 0x7d - 3849 0645 00 .sleb128 0 - 3850 0646 01 .byte 0x1 - 3851 0647 18 .uleb128 0x18 - 3852 0648 01 .byte 0x1 - 3853 0649 57070000 .4byte .LASF61 - 3854 064d 01 .byte 0x1 - 3855 064e 5904 .2byte 0x459 - 3856 0650 01 .byte 0x1 - 3857 0651 00000000 .4byte .LFB23 - 3858 0655 18000000 .4byte .LFE23 - 3859 0659 02 .byte 0x2 - 3860 065a 7D .byte 0x7d - 3861 065b 00 .sleb128 0 - 3862 065c 01 .byte 0x1 - 3863 065d 72060000 .4byte 0x672 - 3864 0661 0F .uleb128 0xf - 3865 0662 07040000 .4byte .LASF30 - 3866 0666 01 .byte 0x1 - 3867 0667 5904 .2byte 0x459 - 3868 0669 85000000 .4byte 0x85 - 3869 066d 5E040000 .4byte .LLST31 - 3870 0671 00 .byte 0 - 3871 0672 25 .uleb128 0x25 - 3872 0673 01 .byte 0x1 - 3873 0674 A9020000 .4byte .LASF63 - 3874 0678 01 .byte 0x1 - 3875 0679 7104 .2byte 0x471 - 3876 067b 01 .byte 0x1 - 3877 067c 85000000 .4byte 0x85 - 3878 0680 00000000 .4byte .LFB24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 116 - - - 3879 0684 1C000000 .4byte .LFE24 - 3880 0688 02 .byte 0x2 - 3881 0689 7D .byte 0x7d - 3882 068a 00 .sleb128 0 - 3883 068b 01 .byte 0x1 - 3884 068c AF060000 .4byte 0x6af - 3885 0690 0F .uleb128 0xf - 3886 0691 8A060000 .4byte .LASF64 - 3887 0695 01 .byte 0x1 - 3888 0696 7104 .2byte 0x471 - 3889 0698 85000000 .4byte 0x85 - 3890 069c 7F040000 .4byte .LLST32 - 3891 06a0 10 .uleb128 0x10 - 3892 06a1 64010000 .4byte .LASF65 - 3893 06a5 01 .byte 0x1 - 3894 06a6 7304 .2byte 0x473 - 3895 06a8 85000000 .4byte 0x85 - 3896 06ac 01 .byte 0x1 - 3897 06ad 53 .byte 0x53 - 3898 06ae 00 .byte 0 - 3899 06af 17 .uleb128 0x17 - 3900 06b0 01 .byte 0x1 - 3901 06b1 97020000 .4byte .LASF66 - 3902 06b5 01 .byte 0x1 - 3903 06b6 C104 .2byte 0x4c1 - 3904 06b8 01 .byte 0x1 - 3905 06b9 00000000 .4byte .LFB26 - 3906 06bd 34000000 .4byte .LFE26 - 3907 06c1 02 .byte 0x2 - 3908 06c2 7D .byte 0x7d - 3909 06c3 00 .sleb128 0 - 3910 06c4 01 .byte 0x1 - 3911 06c5 26 .uleb128 0x26 - 3912 06c6 17010000 .4byte 0x117 - 3913 06ca 00000000 .4byte .LFB27 - 3914 06ce 10000000 .4byte .LFE27 - 3915 06d2 02 .byte 0x2 - 3916 06d3 7D .byte 0x7d - 3917 06d4 00 .sleb128 0 - 3918 06d5 01 .byte 0x1 - 3919 06d6 27 .uleb128 0x27 - 3920 06d7 01 .byte 0x1 - 3921 06d8 D1030000 .4byte .LASF67 - 3922 06dc 01 .byte 0x1 - 3923 06dd 3A05 .2byte 0x53a - 3924 06df 01 .byte 0x1 - 3925 06e0 B4000000 .4byte 0xb4 - 3926 06e4 00000000 .4byte .LFB29 - 3927 06e8 88000000 .4byte .LFE29 - 3928 06ec A0040000 .4byte .LLST33 - 3929 06f0 01 .byte 0x1 - 3930 06f1 95070000 .4byte 0x795 - 3931 06f5 0F .uleb128 0xf - 3932 06f6 5F010000 .4byte .LASF51 - 3933 06fa 01 .byte 0x1 - 3934 06fb 3A05 .2byte 0x53a - 3935 06fd 85000000 .4byte 0x85 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 117 - - - 3936 0701 C0040000 .4byte .LLST34 - 3937 0705 1A .uleb128 0x1a - 3938 0706 50070000 .4byte .LASF55 - 3939 070a 01 .byte 0x1 - 3940 070b 3C05 .2byte 0x53c - 3941 070d B4000000 .4byte 0xb4 - 3942 0711 F6040000 .4byte .LLST35 - 3943 0715 1A .uleb128 0x1a - 3944 0716 6B020000 .4byte .LASF68 - 3945 071a 01 .byte 0x1 - 3946 071b 3D05 .2byte 0x53d - 3947 071d CA000000 .4byte 0xca - 3948 0721 38050000 .4byte .LLST36 - 3949 0725 1A .uleb128 0x1a - 3950 0726 0F000000 .4byte .LASF69 - 3951 072a 01 .byte 0x1 - 3952 072b 3E05 .2byte 0x53e - 3953 072d CA000000 .4byte 0xca - 3954 0731 A6050000 .4byte .LLST37 - 3955 0735 1A .uleb128 0x1a - 3956 0736 EB050000 .4byte .LASF56 - 3957 073a 01 .byte 0x1 - 3958 073b 3F05 .2byte 0x53f - 3959 073d 85000000 .4byte 0x85 - 3960 0741 CF050000 .4byte .LLST38 - 3961 0745 1A .uleb128 0x1a - 3962 0746 0B010000 .4byte .LASF70 - 3963 074a 01 .byte 0x1 - 3964 074b 4005 .2byte 0x540 - 3965 074d 85000000 .4byte 0x85 - 3966 0751 E2050000 .4byte .LLST39 - 3967 0755 1A .uleb128 0x1a - 3968 0756 92070000 .4byte .LASF71 - 3969 075a 01 .byte 0x1 - 3970 075b 4105 .2byte 0x541 - 3971 075d 85000000 .4byte 0x85 - 3972 0761 F5050000 .4byte .LLST40 - 3973 0765 1B .uleb128 0x1b - 3974 0766 24000000 .4byte .LVL86 - 3975 076a 830F0000 .4byte 0xf83 - 3976 076e 78070000 .4byte 0x778 - 3977 0772 1C .uleb128 0x1c - 3978 0773 01 .byte 0x1 - 3979 0774 50 .byte 0x50 - 3980 0775 01 .byte 0x1 - 3981 0776 48 .byte 0x48 - 3982 0777 00 .byte 0 - 3983 0778 1B .uleb128 0x1b - 3984 0779 40000000 .4byte .LVL92 - 3985 077d 970F0000 .4byte 0xf97 - 3986 0781 8B070000 .4byte 0x78b - 3987 0785 1C .uleb128 0x1c - 3988 0786 01 .byte 0x1 - 3989 0787 50 .byte 0x50 - 3990 0788 01 .byte 0x1 - 3991 0789 31 .byte 0x31 - 3992 078a 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 118 - - - 3993 078b 1D .uleb128 0x1d - 3994 078c 72000000 .4byte .LVL100 - 3995 0790 E1040000 .4byte 0x4e1 - 3996 0794 00 .byte 0 - 3997 0795 17 .uleb128 0x17 - 3998 0796 01 .byte 0x1 - 3999 0797 F6070000 .4byte .LASF72 - 4000 079b 01 .byte 0x1 - 4001 079c 8A05 .2byte 0x58a - 4002 079e 01 .byte 0x1 - 4003 079f 00000000 .4byte .LFB30 - 4004 07a3 10000000 .4byte .LFE30 - 4005 07a7 02 .byte 0x2 - 4006 07a8 7D .byte 0x7d - 4007 07a9 00 .sleb128 0 - 4008 07aa 01 .byte 0x1 - 4009 07ab 17 .uleb128 0x17 - 4010 07ac 01 .byte 0x1 - 4011 07ad FA050000 .4byte .LASF73 - 4012 07b1 01 .byte 0x1 - 4013 07b2 A005 .2byte 0x5a0 - 4014 07b4 01 .byte 0x1 - 4015 07b5 00000000 .4byte .LFB31 - 4016 07b9 10000000 .4byte .LFE31 - 4017 07bd 02 .byte 0x2 - 4018 07be 7D .byte 0x7d - 4019 07bf 00 .sleb128 0 - 4020 07c0 01 .byte 0x1 - 4021 07c1 17 .uleb128 0x17 - 4022 07c2 01 .byte 0x1 - 4023 07c3 35000000 .4byte .LASF74 - 4024 07c7 01 .byte 0x1 - 4025 07c8 B605 .2byte 0x5b6 - 4026 07ca 01 .byte 0x1 - 4027 07cb 00000000 .4byte .LFB32 - 4028 07cf 10000000 .4byte .LFE32 - 4029 07d3 02 .byte 0x2 - 4030 07d4 7D .byte 0x7d - 4031 07d5 00 .sleb128 0 - 4032 07d6 01 .byte 0x1 - 4033 07d7 28 .uleb128 0x28 - 4034 07d8 01 .byte 0x1 - 4035 07d9 E4030000 .4byte .LASF139 - 4036 07dd 01 .byte 0x1 - 4037 07de CE05 .2byte 0x5ce - 4038 07e0 01 .byte 0x1 - 4039 07e1 85000000 .4byte 0x85 - 4040 07e5 00000000 .4byte .LFB33 - 4041 07e9 0C000000 .4byte .LFE33 - 4042 07ed 02 .byte 0x2 - 4043 07ee 7D .byte 0x7d - 4044 07ef 00 .sleb128 0 - 4045 07f0 01 .byte 0x1 - 4046 07f1 17 .uleb128 0x17 - 4047 07f2 01 .byte 0x1 - 4048 07f3 45030000 .4byte .LASF75 - 4049 07f7 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 119 - - - 4050 07f8 E905 .2byte 0x5e9 - 4051 07fa 01 .byte 0x1 - 4052 07fb 00000000 .4byte .LFB34 - 4053 07ff 10000000 .4byte .LFE34 - 4054 0803 02 .byte 0x2 - 4055 0804 7D .byte 0x7d - 4056 0805 00 .sleb128 0 - 4057 0806 01 .byte 0x1 - 4058 0807 17 .uleb128 0x17 - 4059 0808 01 .byte 0x1 - 4060 0809 31060000 .4byte .LASF76 - 4061 080d 01 .byte 0x1 - 4062 080e FF05 .2byte 0x5ff - 4063 0810 01 .byte 0x1 - 4064 0811 00000000 .4byte .LFB35 - 4065 0815 10000000 .4byte .LFE35 - 4066 0819 02 .byte 0x2 - 4067 081a 7D .byte 0x7d - 4068 081b 00 .sleb128 0 - 4069 081c 01 .byte 0x1 - 4070 081d 18 .uleb128 0x18 - 4071 081e 01 .byte 0x1 - 4072 081f 17040000 .4byte .LASF77 - 4073 0823 01 .byte 0x1 - 4074 0824 1906 .2byte 0x619 - 4075 0826 01 .byte 0x1 - 4076 0827 00000000 .4byte .LFB36 - 4077 082b 18000000 .4byte .LFE36 - 4078 082f 02 .byte 0x2 - 4079 0830 7D .byte 0x7d - 4080 0831 00 .sleb128 0 - 4081 0832 01 .byte 0x1 - 4082 0833 48080000 .4byte 0x848 - 4083 0837 0F .uleb128 0xf - 4084 0838 AF070000 .4byte .LASF78 - 4085 083c 01 .byte 0x1 - 4086 083d 1906 .2byte 0x619 - 4087 083f 85000000 .4byte 0x85 - 4088 0843 08060000 .4byte .LLST41 - 4089 0847 00 .byte 0 - 4090 0848 18 .uleb128 0x18 - 4091 0849 01 .byte 0x1 - 4092 084a 54060000 .4byte .LASF79 - 4093 084e 01 .byte 0x1 - 4094 084f 3106 .2byte 0x631 - 4095 0851 01 .byte 0x1 - 4096 0852 00000000 .4byte .LFB37 - 4097 0856 18000000 .4byte .LFE37 - 4098 085a 02 .byte 0x2 - 4099 085b 7D .byte 0x7d - 4100 085c 00 .sleb128 0 - 4101 085d 01 .byte 0x1 - 4102 085e 73080000 .4byte 0x873 - 4103 0862 0F .uleb128 0xf - 4104 0863 AF070000 .4byte .LASF78 - 4105 0867 01 .byte 0x1 - 4106 0868 3106 .2byte 0x631 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 120 - - - 4107 086a 85000000 .4byte 0x85 - 4108 086e 29060000 .4byte .LLST42 - 4109 0872 00 .byte 0 - 4110 0873 18 .uleb128 0x18 - 4111 0874 01 .byte 0x1 - 4112 0875 B1050000 .4byte .LASF80 - 4113 0879 01 .byte 0x1 - 4114 087a 4806 .2byte 0x648 - 4115 087c 01 .byte 0x1 - 4116 087d 00000000 .4byte .LFB38 - 4117 0881 1C000000 .4byte .LFE38 - 4118 0885 02 .byte 0x2 - 4119 0886 7D .byte 0x7d - 4120 0887 00 .sleb128 0 - 4121 0888 01 .byte 0x1 - 4122 0889 9E080000 .4byte 0x89e - 4123 088d 0F .uleb128 0xf - 4124 088e AF070000 .4byte .LASF78 - 4125 0892 01 .byte 0x1 - 4126 0893 4806 .2byte 0x648 - 4127 0895 85000000 .4byte 0x85 - 4128 0899 4A060000 .4byte .LLST43 - 4129 089d 00 .byte 0 - 4130 089e 18 .uleb128 0x18 - 4131 089f 01 .byte 0x1 - 4132 08a0 AA050000 .4byte .LASF81 - 4133 08a4 01 .byte 0x1 - 4134 08a5 5D06 .2byte 0x65d - 4135 08a7 01 .byte 0x1 - 4136 08a8 00000000 .4byte .LFB39 - 4137 08ac 04000000 .4byte .LFE39 - 4138 08b0 02 .byte 0x2 - 4139 08b1 7D .byte 0x7d - 4140 08b2 00 .sleb128 0 - 4141 08b3 01 .byte 0x1 - 4142 08b4 C7080000 .4byte 0x8c7 - 4143 08b8 29 .uleb128 0x29 - 4144 08b9 4D060000 .4byte .LASF82 - 4145 08bd 01 .byte 0x1 - 4146 08be 5D06 .2byte 0x65d - 4147 08c0 85000000 .4byte 0x85 - 4148 08c4 01 .byte 0x1 - 4149 08c5 50 .byte 0x50 - 4150 08c6 00 .byte 0 - 4151 08c7 17 .uleb128 0x17 - 4152 08c8 01 .byte 0x1 - 4153 08c9 C9000000 .4byte .LASF83 - 4154 08cd 01 .byte 0x1 - 4155 08ce 7C06 .2byte 0x67c - 4156 08d0 01 .byte 0x1 - 4157 08d1 00000000 .4byte .LFB40 - 4158 08d5 10000000 .4byte .LFE40 - 4159 08d9 02 .byte 0x2 - 4160 08da 7D .byte 0x7d - 4161 08db 00 .sleb128 0 - 4162 08dc 01 .byte 0x1 - 4163 08dd 19 .uleb128 0x19 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 121 - - - 4164 08de 01 .byte 0x1 - 4165 08df 18070000 .4byte .LASF84 - 4166 08e3 01 .byte 0x1 - 4167 08e4 9606 .2byte 0x696 - 4168 08e6 01 .byte 0x1 - 4169 08e7 00000000 .4byte .LFB41 - 4170 08eb 28000000 .4byte .LFE41 - 4171 08ef 6B060000 .4byte .LLST44 - 4172 08f3 01 .byte 0x1 - 4173 08f4 1C090000 .4byte 0x91c - 4174 08f8 0F .uleb128 0xf - 4175 08f9 17050000 .4byte .LASF85 - 4176 08fd 01 .byte 0x1 - 4177 08fe 9606 .2byte 0x696 - 4178 0900 9B000000 .4byte 0x9b - 4179 0904 8B060000 .4byte .LLST45 - 4180 0908 1D .uleb128 0x1d - 4181 0909 12000000 .4byte .LVL113 - 4182 090d AF0F0000 .4byte 0xfaf - 4183 0911 2A .uleb128 0x2a - 4184 0912 24000000 .4byte .LVL115 - 4185 0916 01 .byte 0x1 - 4186 0917 AF0F0000 .4byte 0xfaf - 4187 091b 00 .byte 0 - 4188 091c 18 .uleb128 0x18 - 4189 091d 01 .byte 0x1 - 4190 091e A3010000 .4byte .LASF86 - 4191 0922 01 .byte 0x1 - 4192 0923 C706 .2byte 0x6c7 - 4193 0925 01 .byte 0x1 - 4194 0926 00000000 .4byte .LFB42 - 4195 092a 10000000 .4byte .LFE42 - 4196 092e 02 .byte 0x2 - 4197 092f 7D .byte 0x7d - 4198 0930 00 .sleb128 0 - 4199 0931 01 .byte 0x1 - 4200 0932 51090000 .4byte 0x951 - 4201 0936 0F .uleb128 0xf - 4202 0937 C4070000 .4byte .LASF87 - 4203 093b 01 .byte 0x1 - 4204 093c C706 .2byte 0x6c7 - 4205 093e 90000000 .4byte 0x90 - 4206 0942 A9060000 .4byte .LLST46 - 4207 0946 2A .uleb128 0x2a - 4208 0947 0A000000 .4byte .LVL118 - 4209 094b 01 .byte 0x1 - 4210 094c AF0F0000 .4byte 0xfaf - 4211 0950 00 .byte 0 - 4212 0951 27 .uleb128 0x27 - 4213 0952 01 .byte 0x1 - 4214 0953 C8040000 .4byte .LASF88 - 4215 0957 01 .byte 0x1 - 4216 0958 F804 .2byte 0x4f8 - 4217 095a 01 .byte 0x1 - 4218 095b 85000000 .4byte 0x85 - 4219 095f 00000000 .4byte .LFB28 - 4220 0963 6C000000 .4byte .LFE28 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 122 - - - 4221 0967 CA060000 .4byte .LLST47 - 4222 096b 01 .byte 0x1 - 4223 096c C4090000 .4byte 0x9c4 - 4224 0970 0F .uleb128 0xf - 4225 0971 8A060000 .4byte .LASF64 - 4226 0975 01 .byte 0x1 - 4227 0976 F804 .2byte 0x4f8 - 4228 0978 85000000 .4byte 0x85 - 4229 097c EA060000 .4byte .LLST48 - 4230 0980 10 .uleb128 0x10 - 4231 0981 64010000 .4byte .LASF65 - 4232 0985 01 .byte 0x1 - 4233 0986 FA04 .2byte 0x4fa - 4234 0988 85000000 .4byte 0x85 - 4235 098c 01 .byte 0x1 - 4236 098d 56 .byte 0x56 - 4237 098e 1B .uleb128 0x1b - 4238 098f 20000000 .4byte .LVL122 - 4239 0993 1C090000 .4byte 0x91c - 4240 0997 A1090000 .4byte 0x9a1 - 4241 099b 1C .uleb128 0x1c - 4242 099c 01 .byte 0x1 - 4243 099d 50 .byte 0x50 - 4244 099e 01 .byte 0x1 - 4245 099f 3A .byte 0x3a - 4246 09a0 00 .byte 0 - 4247 09a1 1B .uleb128 0x1b - 4248 09a2 32000000 .4byte .LVL123 - 4249 09a6 1C090000 .4byte 0x91c - 4250 09aa B4090000 .4byte 0x9b4 - 4251 09ae 1C .uleb128 0x1c - 4252 09af 01 .byte 0x1 - 4253 09b0 50 .byte 0x50 - 4254 09b1 01 .byte 0x1 - 4255 09b2 44 .byte 0x44 - 4256 09b3 00 .byte 0 - 4257 09b4 2B .uleb128 0x2b - 4258 09b5 44000000 .4byte .LVL126 - 4259 09b9 1C090000 .4byte 0x91c - 4260 09bd 1C .uleb128 0x1c - 4261 09be 01 .byte 0x1 - 4262 09bf 50 .byte 0x50 - 4263 09c0 01 .byte 0x1 - 4264 09c1 3A .byte 0x3a - 4265 09c2 00 .byte 0 - 4266 09c3 00 .byte 0 - 4267 09c4 19 .uleb128 0x19 - 4268 09c5 01 .byte 0x1 - 4269 09c6 91000000 .4byte .LASF89 - 4270 09ca 01 .byte 0x1 - 4271 09cb 9504 .2byte 0x495 - 4272 09cd 01 .byte 0x1 - 4273 09ce 00000000 .4byte .LFB25 - 4274 09d2 70000000 .4byte .LFE25 - 4275 09d6 30070000 .4byte .LLST49 - 4276 09da 01 .byte 0x1 - 4277 09db 200A0000 .4byte 0xa20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 123 - - - 4278 09df 2C .uleb128 0x2c - 4279 09e0 6900 .ascii "i\000" - 4280 09e2 01 .byte 0x1 - 4281 09e3 9704 .2byte 0x497 - 4282 09e5 DA000000 .4byte 0xda - 4283 09e9 50070000 .4byte .LLST50 - 4284 09ed 2D .uleb128 0x2d - 4285 09ee 17010000 .4byte 0x117 - 4286 09f2 38000000 .4byte .LBB16 - 4287 09f6 3C000000 .4byte .LBE16 - 4288 09fa 01 .byte 0x1 - 4289 09fb A704 .2byte 0x4a7 - 4290 09fd 1B .uleb128 0x1b - 4291 09fe 4A000000 .4byte .LVL129 - 4292 0a02 51090000 .4byte 0x951 - 4293 0a06 100A0000 .4byte 0xa10 - 4294 0a0a 1C .uleb128 0x1c - 4295 0a0b 01 .byte 0x1 - 4296 0a0c 50 .byte 0x50 - 4297 0a0d 01 .byte 0x1 - 4298 0a0e 30 .byte 0x30 - 4299 0a0f 00 .byte 0 - 4300 0a10 2B .uleb128 0x2b - 4301 0a11 52000000 .4byte .LVL130 - 4302 0a15 1C090000 .4byte 0x91c - 4303 0a19 1C .uleb128 0x1c - 4304 0a1a 01 .byte 0x1 - 4305 0a1b 50 .byte 0x50 - 4306 0a1c 01 .byte 0x1 - 4307 0a1d 31 .byte 0x31 - 4308 0a1e 00 .byte 0 - 4309 0a1f 00 .byte 0 - 4310 0a20 18 .uleb128 0x18 - 4311 0a21 01 .byte 0x1 - 4312 0a22 36010000 .4byte .LASF90 - 4313 0a26 01 .byte 0x1 - 4314 0a27 DD06 .2byte 0x6dd - 4315 0a29 01 .byte 0x1 - 4316 0a2a 00000000 .4byte .LFB43 - 4317 0a2e 40000000 .4byte .LFE43 - 4318 0a32 02 .byte 0x2 - 4319 0a33 7D .byte 0x7d - 4320 0a34 00 .sleb128 0 - 4321 0a35 01 .byte 0x1 - 4322 0a36 4B0A0000 .4byte 0xa4b - 4323 0a3a 0F .uleb128 0xf - 4324 0a3b 31010000 .4byte .LASF23 - 4325 0a3f 01 .byte 0x1 - 4326 0a40 DD06 .2byte 0x6dd - 4327 0a42 9B000000 .4byte 0x9b - 4328 0a46 86070000 .4byte .LLST51 - 4329 0a4a 00 .byte 0 - 4330 0a4b 18 .uleb128 0x18 - 4331 0a4c 01 .byte 0x1 - 4332 0a4d DA020000 .4byte .LASF91 - 4333 0a51 01 .byte 0x1 - 4334 0a52 1C07 .2byte 0x71c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 124 - - - 4335 0a54 01 .byte 0x1 - 4336 0a55 00000000 .4byte .LFB44 - 4337 0a59 40000000 .4byte .LFE44 - 4338 0a5d 02 .byte 0x2 - 4339 0a5e 7D .byte 0x7d - 4340 0a5f 00 .sleb128 0 - 4341 0a60 01 .byte 0x1 - 4342 0a61 860A0000 .4byte 0xa86 - 4343 0a65 0F .uleb128 0xf - 4344 0a66 29040000 .4byte .LASF92 - 4345 0a6a 01 .byte 0x1 - 4346 0a6b 1C07 .2byte 0x71c - 4347 0a6d 85000000 .4byte 0x85 - 4348 0a71 A7070000 .4byte .LLST52 - 4349 0a75 0F .uleb128 0xf - 4350 0a76 7E060000 .4byte .LASF93 - 4351 0a7a 01 .byte 0x1 - 4352 0a7b 1C07 .2byte 0x71c - 4353 0a7d 85000000 .4byte 0x85 - 4354 0a81 C8070000 .4byte .LLST53 - 4355 0a85 00 .byte 0 - 4356 0a86 17 .uleb128 0x17 - 4357 0a87 01 .byte 0x1 - 4358 0a88 D1010000 .4byte .LASF94 - 4359 0a8c 01 .byte 0x1 - 4360 0a8d 3C07 .2byte 0x73c - 4361 0a8f 01 .byte 0x1 - 4362 0a90 00000000 .4byte .LFB45 - 4363 0a94 0C000000 .4byte .LFE45 - 4364 0a98 02 .byte 0x2 - 4365 0a99 7D .byte 0x7d - 4366 0a9a 00 .sleb128 0 - 4367 0a9b 01 .byte 0x1 - 4368 0a9c 19 .uleb128 0x19 - 4369 0a9d 01 .byte 0x1 - 4370 0a9e E4070000 .4byte .LASF95 - 4371 0aa2 01 .byte 0x1 - 4372 0aa3 5807 .2byte 0x758 - 4373 0aa5 01 .byte 0x1 - 4374 0aa6 00000000 .4byte .LFB46 - 4375 0aaa 68000000 .4byte .LFE46 - 4376 0aae E9070000 .4byte .LLST54 - 4377 0ab2 01 .byte 0x1 - 4378 0ab3 E70A0000 .4byte 0xae7 - 4379 0ab7 0F .uleb128 0xf - 4380 0ab8 F6010000 .4byte .LASF96 - 4381 0abc 01 .byte 0x1 - 4382 0abd 5807 .2byte 0x758 - 4383 0abf 85000000 .4byte 0x85 - 4384 0ac3 09080000 .4byte .LLST55 - 4385 0ac7 0F .uleb128 0xf - 4386 0ac8 A0050000 .4byte .LASF97 - 4387 0acc 01 .byte 0x1 - 4388 0acd 5807 .2byte 0x758 - 4389 0acf 85000000 .4byte 0x85 - 4390 0ad3 2A080000 .4byte .LLST56 - 4391 0ad7 2B .uleb128 0x2b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 125 - - - 4392 0ad8 30000000 .4byte .LVL142 - 4393 0adc 1C090000 .4byte 0x91c - 4394 0ae0 1C .uleb128 0x1c - 4395 0ae1 01 .byte 0x1 - 4396 0ae2 50 .byte 0x50 - 4397 0ae3 01 .byte 0x1 - 4398 0ae4 31 .byte 0x31 - 4399 0ae5 00 .byte 0 - 4400 0ae6 00 .byte 0 - 4401 0ae7 19 .uleb128 0x19 - 4402 0ae8 01 .byte 0x1 - 4403 0ae9 73020000 .4byte .LASF98 - 4404 0aed 01 .byte 0x1 - 4405 0aee 8A07 .2byte 0x78a - 4406 0af0 01 .byte 0x1 - 4407 0af1 00000000 .4byte .LFB47 - 4408 0af5 68000000 .4byte .LFE47 - 4409 0af9 4B080000 .4byte .LLST57 - 4410 0afd 01 .byte 0x1 - 4411 0afe 320B0000 .4byte 0xb32 - 4412 0b02 0F .uleb128 0xf - 4413 0b03 F6010000 .4byte .LASF96 - 4414 0b07 01 .byte 0x1 - 4415 0b08 8A07 .2byte 0x78a - 4416 0b0a 85000000 .4byte 0x85 - 4417 0b0e 6B080000 .4byte .LLST58 - 4418 0b12 0F .uleb128 0xf - 4419 0b13 A0050000 .4byte .LASF97 - 4420 0b17 01 .byte 0x1 - 4421 0b18 8A07 .2byte 0x78a - 4422 0b1a 85000000 .4byte 0x85 - 4423 0b1e 8C080000 .4byte .LLST59 - 4424 0b22 2B .uleb128 0x2b - 4425 0b23 32000000 .4byte .LVL146 - 4426 0b27 1C090000 .4byte 0x91c - 4427 0b2b 1C .uleb128 0x1c - 4428 0b2c 01 .byte 0x1 - 4429 0b2d 50 .byte 0x50 - 4430 0b2e 01 .byte 0x1 - 4431 0b2f 31 .byte 0x31 - 4432 0b30 00 .byte 0 - 4433 0b31 00 .byte 0 - 4434 0b32 17 .uleb128 0x17 - 4435 0b33 01 .byte 0x1 - 4436 0b34 B1060000 .4byte .LASF99 - 4437 0b38 01 .byte 0x1 - 4438 0b39 B507 .2byte 0x7b5 - 4439 0b3b 01 .byte 0x1 - 4440 0b3c 00000000 .4byte .LFB48 - 4441 0b40 24000000 .4byte .LFE48 - 4442 0b44 02 .byte 0x2 - 4443 0b45 7D .byte 0x7d - 4444 0b46 00 .sleb128 0 - 4445 0b47 01 .byte 0x1 - 4446 0b48 17 .uleb128 0x17 - 4447 0b49 01 .byte 0x1 - 4448 0b4a C4060000 .4byte .LASF100 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 126 - - - 4449 0b4e 01 .byte 0x1 - 4450 0b4f D107 .2byte 0x7d1 - 4451 0b51 01 .byte 0x1 - 4452 0b52 00000000 .4byte .LFB49 - 4453 0b56 24000000 .4byte .LFE49 - 4454 0b5a 02 .byte 0x2 - 4455 0b5b 7D .byte 0x7d - 4456 0b5c 00 .sleb128 0 - 4457 0b5d 01 .byte 0x1 - 4458 0b5e 19 .uleb128 0x19 - 4459 0b5f 01 .byte 0x1 - 4460 0b60 D1070000 .4byte .LASF101 - 4461 0b64 01 .byte 0x1 - 4462 0b65 ED07 .2byte 0x7ed - 4463 0b67 01 .byte 0x1 - 4464 0b68 00000000 .4byte .LFB50 - 4465 0b6c 44000000 .4byte .LFE50 - 4466 0b70 AD080000 .4byte .LLST60 - 4467 0b74 01 .byte 0x1 - 4468 0b75 8A0B0000 .4byte 0xb8a - 4469 0b79 2B .uleb128 0x2b - 4470 0b7a 24000000 .4byte .LVL147 - 4471 0b7e 1C090000 .4byte 0x91c - 4472 0b82 1C .uleb128 0x1c - 4473 0b83 01 .byte 0x1 - 4474 0b84 50 .byte 0x50 - 4475 0b85 02 .byte 0x2 - 4476 0b86 74 .byte 0x74 - 4477 0b87 00 .sleb128 0 - 4478 0b88 00 .byte 0 - 4479 0b89 00 .byte 0 - 4480 0b8a 17 .uleb128 0x17 - 4481 0b8b 01 .byte 0x1 - 4482 0b8c F4020000 .4byte .LASF102 - 4483 0b90 01 .byte 0x1 - 4484 0b91 0E08 .2byte 0x80e - 4485 0b93 01 .byte 0x1 - 4486 0b94 00000000 .4byte .LFB51 - 4487 0b98 10000000 .4byte .LFE51 - 4488 0b9c 02 .byte 0x2 - 4489 0b9d 7D .byte 0x7d - 4490 0b9e 00 .sleb128 0 - 4491 0b9f 01 .byte 0x1 - 4492 0ba0 25 .uleb128 0x25 - 4493 0ba1 01 .byte 0x1 - 4494 0ba2 86020000 .4byte .LASF103 - 4495 0ba6 01 .byte 0x1 - 4496 0ba7 2808 .2byte 0x828 - 4497 0ba9 01 .byte 0x1 - 4498 0baa 85000000 .4byte 0x85 - 4499 0bae 00000000 .4byte .LFB52 - 4500 0bb2 14000000 .4byte .LFE52 - 4501 0bb6 02 .byte 0x2 - 4502 0bb7 7D .byte 0x7d - 4503 0bb8 00 .sleb128 0 - 4504 0bb9 01 .byte 0x1 - 4505 0bba DD0B0000 .4byte 0xbdd - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 127 - - - 4506 0bbe 0F .uleb128 0xf - 4507 0bbf F1010000 .4byte .LASF104 - 4508 0bc3 01 .byte 0x1 - 4509 0bc4 2808 .2byte 0x828 - 4510 0bc6 85000000 .4byte 0x85 - 4511 0bca CD080000 .4byte .LLST61 - 4512 0bce 10 .uleb128 0x10 - 4513 0bcf 50070000 .4byte .LASF55 - 4514 0bd3 01 .byte 0x1 - 4515 0bd4 2A08 .2byte 0x82a - 4516 0bd6 85000000 .4byte 0x85 - 4517 0bda 01 .byte 0x1 - 4518 0bdb 52 .byte 0x52 - 4519 0bdc 00 .byte 0 - 4520 0bdd 27 .uleb128 0x27 - 4521 0bde 01 .byte 0x1 - 4522 0bdf 46040000 .4byte .LASF105 - 4523 0be3 01 .byte 0x1 - 4524 0be4 4508 .2byte 0x845 - 4525 0be6 01 .byte 0x1 - 4526 0be7 85000000 .4byte 0x85 - 4527 0beb 00000000 .4byte .LFB53 - 4528 0bef 18000000 .4byte .LFE53 - 4529 0bf3 EE080000 .4byte .LLST62 - 4530 0bf7 01 .byte 0x1 - 4531 0bf8 2D0C0000 .4byte 0xc2d - 4532 0bfc 1A .uleb128 0x1a - 4533 0bfd 42010000 .4byte .LASF44 - 4534 0c01 01 .byte 0x1 - 4535 0c02 4708 .2byte 0x847 - 4536 0c04 85000000 .4byte 0x85 - 4537 0c08 0E090000 .4byte .LLST63 - 4538 0c0c 10 .uleb128 0x10 - 4539 0c0d 43070000 .4byte .LASF106 - 4540 0c11 01 .byte 0x1 - 4541 0c12 4808 .2byte 0x848 - 4542 0c14 85000000 .4byte 0x85 - 4543 0c18 01 .byte 0x1 - 4544 0c19 54 .byte 0x54 - 4545 0c1a 1D .uleb128 0x1d - 4546 0c1b 06000000 .4byte .LVL151 - 4547 0c1f 610F0000 .4byte 0xf61 - 4548 0c23 1D .uleb128 0x1d - 4549 0c24 0E000000 .4byte .LVL153 - 4550 0c28 6F0F0000 .4byte 0xf6f - 4551 0c2c 00 .byte 0 - 4552 0c2d 27 .uleb128 0x27 - 4553 0c2e 01 .byte 0x1 - 4554 0c2f 83000000 .4byte .LASF107 - 4555 0c33 01 .byte 0x1 - 4556 0c34 6008 .2byte 0x860 - 4557 0c36 01 .byte 0x1 - 4558 0c37 9B000000 .4byte 0x9b - 4559 0c3b 00000000 .4byte .LFB54 - 4560 0c3f 1C000000 .4byte .LFE54 - 4561 0c43 21090000 .4byte .LLST64 - 4562 0c47 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 128 - - - 4563 0c48 7D0C0000 .4byte 0xc7d - 4564 0c4c 10 .uleb128 0x10 - 4565 0c4d 1C000000 .4byte .LASF108 - 4566 0c51 01 .byte 0x1 - 4567 0c52 6208 .2byte 0x862 - 4568 0c54 9B000000 .4byte 0x9b - 4569 0c58 01 .byte 0x1 - 4570 0c59 54 .byte 0x54 - 4571 0c5a 1A .uleb128 0x1a - 4572 0c5b 42010000 .4byte .LASF44 - 4573 0c5f 01 .byte 0x1 - 4574 0c60 6308 .2byte 0x863 - 4575 0c62 85000000 .4byte 0x85 - 4576 0c66 41090000 .4byte .LLST65 - 4577 0c6a 1D .uleb128 0x1d - 4578 0c6b 06000000 .4byte .LVL154 - 4579 0c6f 610F0000 .4byte 0xf61 - 4580 0c73 1D .uleb128 0x1d - 4581 0c74 14000000 .4byte .LVL156 - 4582 0c78 6F0F0000 .4byte 0xf6f - 4583 0c7c 00 .byte 0 - 4584 0c7d 19 .uleb128 0x19 - 4585 0c7e 01 .byte 0x1 - 4586 0c7f DD060000 .4byte .LASF109 - 4587 0c83 01 .byte 0x1 - 4588 0c84 9408 .2byte 0x894 - 4589 0c86 01 .byte 0x1 - 4590 0c87 00000000 .4byte .LFB55 - 4591 0c8b 18000000 .4byte .LFE55 - 4592 0c8f 54090000 .4byte .LLST66 - 4593 0c93 01 .byte 0x1 - 4594 0c94 CC0C0000 .4byte 0xccc - 4595 0c98 0F .uleb128 0xf - 4596 0c99 F1010000 .4byte .LASF104 - 4597 0c9d 01 .byte 0x1 - 4598 0c9e 9408 .2byte 0x894 - 4599 0ca0 9B000000 .4byte 0x9b - 4600 0ca4 74090000 .4byte .LLST67 - 4601 0ca8 1A .uleb128 0x1a - 4602 0ca9 42010000 .4byte .LASF44 - 4603 0cad 01 .byte 0x1 - 4604 0cae 9708 .2byte 0x897 - 4605 0cb0 85000000 .4byte 0x85 - 4606 0cb4 92090000 .4byte .LLST68 - 4607 0cb8 1D .uleb128 0x1d - 4608 0cb9 08000000 .4byte .LVL158 - 4609 0cbd 610F0000 .4byte 0xf61 - 4610 0cc1 2A .uleb128 0x2a - 4611 0cc2 14000000 .4byte .LVL159 - 4612 0cc6 01 .byte 0x1 - 4613 0cc7 6F0F0000 .4byte 0xf6f - 4614 0ccb 00 .byte 0 - 4615 0ccc 19 .uleb128 0x19 - 4616 0ccd 01 .byte 0x1 - 4617 0cce 11060000 .4byte .LASF110 - 4618 0cd2 01 .byte 0x1 - 4619 0cd3 BC08 .2byte 0x8bc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 129 - - - 4620 0cd5 01 .byte 0x1 - 4621 0cd6 00000000 .4byte .LFB56 - 4622 0cda 60000000 .4byte .LFE56 - 4623 0cde A5090000 .4byte .LLST69 - 4624 0ce2 01 .byte 0x1 - 4625 0ce3 0B0D0000 .4byte 0xd0b - 4626 0ce7 1A .uleb128 0x1a - 4627 0ce8 42010000 .4byte .LASF44 - 4628 0cec 01 .byte 0x1 - 4629 0ced BE08 .2byte 0x8be - 4630 0cef 85000000 .4byte 0x85 - 4631 0cf3 C5090000 .4byte .LLST70 - 4632 0cf7 1D .uleb128 0x1d - 4633 0cf8 06000000 .4byte .LVL160 - 4634 0cfc 610F0000 .4byte 0xf61 - 4635 0d00 2A .uleb128 0x2a - 4636 0d01 5A000000 .4byte .LVL161 - 4637 0d05 01 .byte 0x1 - 4638 0d06 6F0F0000 .4byte 0xf6f - 4639 0d0a 00 .byte 0 - 4640 0d0b 25 .uleb128 0x25 - 4641 0d0c 01 .byte 0x1 - 4642 0d0d 8E030000 .4byte .LASF111 - 4643 0d11 01 .byte 0x1 - 4644 0d12 0409 .2byte 0x904 - 4645 0d14 01 .byte 0x1 - 4646 0d15 EF000000 .4byte 0xef - 4647 0d19 00000000 .4byte .LFB57 - 4648 0d1d 18000000 .4byte .LFE57 - 4649 0d21 02 .byte 0x2 - 4650 0d22 7D .byte 0x7d - 4651 0d23 00 .sleb128 0 - 4652 0d24 01 .byte 0x1 - 4653 0d25 660D0000 .4byte 0xd66 - 4654 0d29 0F .uleb128 0xf - 4655 0d2a 1E030000 .4byte .LASF112 - 4656 0d2e 01 .byte 0x1 - 4657 0d2f 0409 .2byte 0x904 - 4658 0d31 85000000 .4byte 0x85 - 4659 0d35 D8090000 .4byte .LLST71 - 4660 0d39 29 .uleb128 0x29 - 4661 0d3a 2F040000 .4byte .LASF113 - 4662 0d3e 01 .byte 0x1 - 4663 0d3f 0409 .2byte 0x904 - 4664 0d41 EF000000 .4byte 0xef - 4665 0d45 01 .byte 0x1 - 4666 0d46 51 .byte 0x51 - 4667 0d47 10 .uleb128 0x10 - 4668 0d48 68000000 .4byte .LASF114 - 4669 0d4c 01 .byte 0x1 - 4670 0d4d 0609 .2byte 0x906 - 4671 0d4f EF000000 .4byte 0xef - 4672 0d53 01 .byte 0x1 - 4673 0d54 50 .byte 0x50 - 4674 0d55 1A .uleb128 0x1a - 4675 0d56 00000000 .4byte .LASF115 - 4676 0d5a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 130 - - - 4677 0d5b 0709 .2byte 0x907 - 4678 0d5d 660D0000 .4byte 0xd66 - 4679 0d61 F9090000 .4byte .LLST72 - 4680 0d65 00 .byte 0 - 4681 0d66 05 .uleb128 0x5 - 4682 0d67 04 .byte 0x4 - 4683 0d68 EF000000 .4byte 0xef - 4684 0d6c 25 .uleb128 0x25 - 4685 0d6d 01 .byte 0x1 - 4686 0d6e 0D020000 .4byte .LASF116 - 4687 0d72 01 .byte 0x1 - 4688 0d73 2509 .2byte 0x925 - 4689 0d75 01 .byte 0x1 - 4690 0d76 EF000000 .4byte 0xef - 4691 0d7a 00000000 .4byte .LFB58 - 4692 0d7e 14000000 .4byte .LFE58 - 4693 0d82 02 .byte 0x2 - 4694 0d83 7D .byte 0x7d - 4695 0d84 00 .sleb128 0 - 4696 0d85 01 .byte 0x1 - 4697 0d86 AB0D0000 .4byte 0xdab - 4698 0d8a 0F .uleb128 0xf - 4699 0d8b 1E030000 .4byte .LASF112 - 4700 0d8f 01 .byte 0x1 - 4701 0d90 2509 .2byte 0x925 - 4702 0d92 85000000 .4byte 0x85 - 4703 0d96 280A0000 .4byte .LLST73 - 4704 0d9a 1A .uleb128 0x1a - 4705 0d9b 00000000 .4byte .LASF115 - 4706 0d9f 01 .byte 0x1 - 4707 0da0 2709 .2byte 0x927 - 4708 0da2 660D0000 .4byte 0xd66 - 4709 0da6 490A0000 .4byte .LLST74 - 4710 0daa 00 .byte 0 - 4711 0dab 25 .uleb128 0x25 - 4712 0dac 01 .byte 0x1 - 4713 0dad E5020000 .4byte .LASF117 - 4714 0db1 01 .byte 0x1 - 4715 0db2 3D09 .2byte 0x93d - 4716 0db4 01 .byte 0x1 - 4717 0db5 EF000000 .4byte 0xef - 4718 0db9 00000000 .4byte .LFB59 - 4719 0dbd 1C000000 .4byte .LFE59 - 4720 0dc1 02 .byte 0x2 - 4721 0dc2 7D .byte 0x7d - 4722 0dc3 00 .sleb128 0 - 4723 0dc4 01 .byte 0x1 - 4724 0dc5 060E0000 .4byte 0xe06 - 4725 0dc9 0F .uleb128 0xf - 4726 0dca 1E030000 .4byte .LASF112 - 4727 0dce 01 .byte 0x1 - 4728 0dcf 3D09 .2byte 0x93d - 4729 0dd1 85000000 .4byte 0x85 - 4730 0dd5 6D0A0000 .4byte .LLST75 - 4731 0dd9 29 .uleb128 0x29 - 4732 0dda 2F040000 .4byte .LASF113 - 4733 0dde 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 131 - - - 4734 0ddf 3D09 .2byte 0x93d - 4735 0de1 EF000000 .4byte 0xef - 4736 0de5 01 .byte 0x1 - 4737 0de6 51 .byte 0x51 - 4738 0de7 10 .uleb128 0x10 - 4739 0de8 68000000 .4byte .LASF114 - 4740 0dec 01 .byte 0x1 - 4741 0ded 3F09 .2byte 0x93f - 4742 0def EF000000 .4byte 0xef - 4743 0df3 01 .byte 0x1 - 4744 0df4 50 .byte 0x50 - 4745 0df5 1A .uleb128 0x1a - 4746 0df6 00000000 .4byte .LASF115 - 4747 0dfa 01 .byte 0x1 - 4748 0dfb 4009 .2byte 0x940 - 4749 0dfd 660D0000 .4byte 0xd66 - 4750 0e01 8E0A0000 .4byte .LLST76 - 4751 0e05 00 .byte 0 - 4752 0e06 25 .uleb128 0x25 - 4753 0e07 01 .byte 0x1 - 4754 0e08 08050000 .4byte .LASF118 - 4755 0e0c 01 .byte 0x1 - 4756 0e0d 5C09 .2byte 0x95c - 4757 0e0f 01 .byte 0x1 - 4758 0e10 EF000000 .4byte 0xef - 4759 0e14 00000000 .4byte .LFB60 - 4760 0e18 14000000 .4byte .LFE60 - 4761 0e1c 02 .byte 0x2 - 4762 0e1d 7D .byte 0x7d - 4763 0e1e 00 .sleb128 0 - 4764 0e1f 01 .byte 0x1 - 4765 0e20 450E0000 .4byte 0xe45 - 4766 0e24 0F .uleb128 0xf - 4767 0e25 1E030000 .4byte .LASF112 - 4768 0e29 01 .byte 0x1 - 4769 0e2a 5C09 .2byte 0x95c - 4770 0e2c 85000000 .4byte 0x85 - 4771 0e30 BD0A0000 .4byte .LLST77 - 4772 0e34 1A .uleb128 0x1a - 4773 0e35 00000000 .4byte .LASF115 - 4774 0e39 01 .byte 0x1 - 4775 0e3a 5E09 .2byte 0x95e - 4776 0e3c 660D0000 .4byte 0xd66 - 4777 0e40 DE0A0000 .4byte .LLST78 - 4778 0e44 00 .byte 0 - 4779 0e45 18 .uleb128 0x18 - 4780 0e46 01 .byte 0x1 - 4781 0e47 60030000 .4byte .LASF119 - 4782 0e4b 01 .byte 0x1 - 4783 0e4c 7409 .2byte 0x974 - 4784 0e4e 01 .byte 0x1 - 4785 0e4f 00000000 .4byte .LFB61 - 4786 0e53 14000000 .4byte .LFE61 - 4787 0e57 02 .byte 0x2 - 4788 0e58 7D .byte 0x7d - 4789 0e59 00 .sleb128 0 - 4790 0e5a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 132 - - - 4791 0e5b 800E0000 .4byte 0xe80 - 4792 0e5f 0F .uleb128 0xf - 4793 0e60 1E030000 .4byte .LASF112 - 4794 0e64 01 .byte 0x1 - 4795 0e65 7409 .2byte 0x974 - 4796 0e67 85000000 .4byte 0x85 - 4797 0e6b 020B0000 .4byte .LLST79 - 4798 0e6f 0F .uleb128 0xf - 4799 0e70 3C030000 .4byte .LASF120 - 4800 0e74 01 .byte 0x1 - 4801 0e75 7409 .2byte 0x974 - 4802 0e77 85000000 .4byte 0x85 - 4803 0e7b 230B0000 .4byte .LLST80 - 4804 0e7f 00 .byte 0 - 4805 0e80 25 .uleb128 0x25 - 4806 0e81 01 .byte 0x1 - 4807 0e82 FC010000 .4byte .LASF121 - 4808 0e86 01 .byte 0x1 - 4809 0e87 8A09 .2byte 0x98a - 4810 0e89 01 .byte 0x1 - 4811 0e8a 85000000 .4byte 0x85 - 4812 0e8e 00000000 .4byte .LFB62 - 4813 0e92 12000000 .4byte .LFE62 - 4814 0e96 02 .byte 0x2 - 4815 0e97 7D .byte 0x7d - 4816 0e98 00 .sleb128 0 - 4817 0e99 01 .byte 0x1 - 4818 0e9a C10E0000 .4byte 0xec1 - 4819 0e9e 0F .uleb128 0xf - 4820 0e9f 1E030000 .4byte .LASF112 - 4821 0ea3 01 .byte 0x1 - 4822 0ea4 8A09 .2byte 0x98a - 4823 0ea6 85000000 .4byte 0x85 - 4824 0eaa 440B0000 .4byte .LLST81 - 4825 0eae 10 .uleb128 0x10 - 4826 0eaf 3C030000 .4byte .LASF120 - 4827 0eb3 01 .byte 0x1 - 4828 0eb4 8C09 .2byte 0x98c - 4829 0eb6 85000000 .4byte 0x85 - 4830 0eba 05 .byte 0x5 - 4831 0ebb 72 .byte 0x72 - 4832 0ebc 00 .sleb128 0 - 4833 0ebd 35 .byte 0x35 - 4834 0ebe 25 .byte 0x25 - 4835 0ebf 9F .byte 0x9f - 4836 0ec0 00 .byte 0 - 4837 0ec1 25 .uleb128 0x25 - 4838 0ec2 01 .byte 0x1 - 4839 0ec3 FD000000 .4byte .LASF122 - 4840 0ec7 01 .byte 0x1 - 4841 0ec8 A409 .2byte 0x9a4 - 4842 0eca 01 .byte 0x1 - 4843 0ecb 85000000 .4byte 0x85 - 4844 0ecf 00000000 .4byte .LFB63 - 4845 0ed3 18000000 .4byte .LFE63 - 4846 0ed7 02 .byte 0x2 - 4847 0ed8 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 133 - - - 4848 0ed9 00 .sleb128 0 - 4849 0eda 01 .byte 0x1 - 4850 0edb 010F0000 .4byte 0xf01 - 4851 0edf 0F .uleb128 0xf - 4852 0ee0 1E030000 .4byte .LASF112 - 4853 0ee4 01 .byte 0x1 - 4854 0ee5 A409 .2byte 0x9a4 - 4855 0ee7 85000000 .4byte 0x85 - 4856 0eeb 650B0000 .4byte .LLST82 - 4857 0eef 2E .uleb128 0x2e - 4858 0ef0 1E060000 .4byte .LASF123 - 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.uleb128 0x11 - 5305 0155 01 .uleb128 0x1 - 5306 0156 12 .uleb128 0x12 - 5307 0157 01 .uleb128 0x1 - 5308 0158 40 .uleb128 0x40 - 5309 0159 0A .uleb128 0xa - 5310 015a 9742 .uleb128 0x2117 - 5311 015c 0C .uleb128 0xc - 5312 015d 00 .byte 0 - 5313 015e 00 .byte 0 - 5314 015f 18 .uleb128 0x18 - 5315 0160 2E .uleb128 0x2e - 5316 0161 01 .byte 0x1 - 5317 0162 3F .uleb128 0x3f - 5318 0163 0C .uleb128 0xc - 5319 0164 03 .uleb128 0x3 - 5320 0165 0E .uleb128 0xe - 5321 0166 3A .uleb128 0x3a - 5322 0167 0B .uleb128 0xb - 5323 0168 3B .uleb128 0x3b - 5324 0169 05 .uleb128 0x5 - 5325 016a 27 .uleb128 0x27 - 5326 016b 0C .uleb128 0xc - 5327 016c 11 .uleb128 0x11 - 5328 016d 01 .uleb128 0x1 - 5329 016e 12 .uleb128 0x12 - 5330 016f 01 .uleb128 0x1 - 5331 0170 40 .uleb128 0x40 - 5332 0171 0A .uleb128 0xa - 5333 0172 9742 .uleb128 0x2117 - 5334 0174 0C .uleb128 0xc - 5335 0175 01 .uleb128 0x1 - 5336 0176 13 .uleb128 0x13 - 5337 0177 00 .byte 0 - 5338 0178 00 .byte 0 - 5339 0179 19 .uleb128 0x19 - 5340 017a 2E .uleb128 0x2e - 5341 017b 01 .byte 0x1 - 5342 017c 3F .uleb128 0x3f - 5343 017d 0C .uleb128 0xc - 5344 017e 03 .uleb128 0x3 - 5345 017f 0E .uleb128 0xe - 5346 0180 3A .uleb128 0x3a - 5347 0181 0B .uleb128 0xb - 5348 0182 3B .uleb128 0x3b - 5349 0183 05 .uleb128 0x5 - 5350 0184 27 .uleb128 0x27 - 5351 0185 0C .uleb128 0xc - 5352 0186 11 .uleb128 0x11 - 5353 0187 01 .uleb128 0x1 - 5354 0188 12 .uleb128 0x12 - 5355 0189 01 .uleb128 0x1 - 5356 018a 40 .uleb128 0x40 - 5357 018b 06 .uleb128 0x6 - 5358 018c 9742 .uleb128 0x2117 - 5359 018e 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 142 - - - 5360 018f 01 .uleb128 0x1 - 5361 0190 13 .uleb128 0x13 - 5362 0191 00 .byte 0 - 5363 0192 00 .byte 0 - 5364 0193 1A .uleb128 0x1a - 5365 0194 34 .uleb128 0x34 - 5366 0195 00 .byte 0 - 5367 0196 03 .uleb128 0x3 - 5368 0197 0E .uleb128 0xe - 5369 0198 3A .uleb128 0x3a - 5370 0199 0B .uleb128 0xb - 5371 019a 3B .uleb128 0x3b - 5372 019b 05 .uleb128 0x5 - 5373 019c 49 .uleb128 0x49 - 5374 019d 13 .uleb128 0x13 - 5375 019e 02 .uleb128 0x2 - 5376 019f 06 .uleb128 0x6 - 5377 01a0 00 .byte 0 - 5378 01a1 00 .byte 0 - 5379 01a2 1B .uleb128 0x1b - 5380 01a3 898201 .uleb128 0x4109 - 5381 01a6 01 .byte 0x1 - 5382 01a7 11 .uleb128 0x11 - 5383 01a8 01 .uleb128 0x1 - 5384 01a9 31 .uleb128 0x31 - 5385 01aa 13 .uleb128 0x13 - 5386 01ab 01 .uleb128 0x1 - 5387 01ac 13 .uleb128 0x13 - 5388 01ad 00 .byte 0 - 5389 01ae 00 .byte 0 - 5390 01af 1C .uleb128 0x1c - 5391 01b0 8A8201 .uleb128 0x410a - 5392 01b3 00 .byte 0 - 5393 01b4 02 .uleb128 0x2 - 5394 01b5 0A .uleb128 0xa - 5395 01b6 9142 .uleb128 0x2111 - 5396 01b8 0A .uleb128 0xa - 5397 01b9 00 .byte 0 - 5398 01ba 00 .byte 0 - 5399 01bb 1D .uleb128 0x1d - 5400 01bc 898201 .uleb128 0x4109 - 5401 01bf 00 .byte 0 - 5402 01c0 11 .uleb128 0x11 - 5403 01c1 01 .uleb128 0x1 - 5404 01c2 31 .uleb128 0x31 - 5405 01c3 13 .uleb128 0x13 - 5406 01c4 00 .byte 0 - 5407 01c5 00 .byte 0 - 5408 01c6 1E .uleb128 0x1e - 5409 01c7 898201 .uleb128 0x4109 - 5410 01ca 01 .byte 0x1 - 5411 01cb 11 .uleb128 0x11 - 5412 01cc 01 .uleb128 0x1 - 5413 01cd 9542 .uleb128 0x2115 - 5414 01cf 0C .uleb128 0xc - 5415 01d0 31 .uleb128 0x31 - 5416 01d1 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 143 - - - 5417 01d2 00 .byte 0 - 5418 01d3 00 .byte 0 - 5419 01d4 1F .uleb128 0x1f - 5420 01d5 2E .uleb128 0x2e - 5421 01d6 01 .byte 0x1 - 5422 01d7 31 .uleb128 0x31 - 5423 01d8 13 .uleb128 0x13 - 5424 01d9 11 .uleb128 0x11 - 5425 01da 01 .uleb128 0x1 - 5426 01db 12 .uleb128 0x12 - 5427 01dc 01 .uleb128 0x1 - 5428 01dd 40 .uleb128 0x40 - 5429 01de 0A .uleb128 0xa - 5430 01df 9742 .uleb128 0x2117 - 5431 01e1 0C .uleb128 0xc - 5432 01e2 01 .uleb128 0x1 - 5433 01e3 13 .uleb128 0x13 - 5434 01e4 00 .byte 0 - 5435 01e5 00 .byte 0 - 5436 01e6 20 .uleb128 0x20 - 5437 01e7 05 .uleb128 0x5 - 5438 01e8 00 .byte 0 - 5439 01e9 31 .uleb128 0x31 - 5440 01ea 13 .uleb128 0x13 - 5441 01eb 02 .uleb128 0x2 - 5442 01ec 0A .uleb128 0xa - 5443 01ed 00 .byte 0 - 5444 01ee 00 .byte 0 - 5445 01ef 21 .uleb128 0x21 - 5446 01f0 1D .uleb128 0x1d - 5447 01f1 01 .byte 0x1 - 5448 01f2 31 .uleb128 0x31 - 5449 01f3 13 .uleb128 0x13 - 5450 01f4 11 .uleb128 0x11 - 5451 01f5 01 .uleb128 0x1 - 5452 01f6 12 .uleb128 0x12 - 5453 01f7 01 .uleb128 0x1 - 5454 01f8 58 .uleb128 0x58 - 5455 01f9 0B .uleb128 0xb - 5456 01fa 59 .uleb128 0x59 - 5457 01fb 05 .uleb128 0x5 - 5458 01fc 01 .uleb128 0x1 - 5459 01fd 13 .uleb128 0x13 - 5460 01fe 00 .byte 0 - 5461 01ff 00 .byte 0 - 5462 0200 22 .uleb128 0x22 - 5463 0201 05 .uleb128 0x5 - 5464 0202 00 .byte 0 - 5465 0203 31 .uleb128 0x31 - 5466 0204 13 .uleb128 0x13 - 5467 0205 02 .uleb128 0x2 - 5468 0206 06 .uleb128 0x6 - 5469 0207 00 .byte 0 - 5470 0208 00 .byte 0 - 5471 0209 23 .uleb128 0x23 - 5472 020a 2E .uleb128 0x2e - 5473 020b 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 144 - - - 5474 020c 3F .uleb128 0x3f - 5475 020d 0C .uleb128 0xc - 5476 020e 03 .uleb128 0x3 - 5477 020f 0E .uleb128 0xe - 5478 0210 3A .uleb128 0x3a - 5479 0211 0B .uleb128 0xb - 5480 0212 3B .uleb128 0x3b - 5481 0213 0B .uleb128 0xb - 5482 0214 27 .uleb128 0x27 - 5483 0215 0C .uleb128 0xc - 5484 0216 49 .uleb128 0x49 - 5485 0217 13 .uleb128 0x13 - 5486 0218 11 .uleb128 0x11 - 5487 0219 01 .uleb128 0x1 - 5488 021a 12 .uleb128 0x12 - 5489 021b 01 .uleb128 0x1 - 5490 021c 40 .uleb128 0x40 - 5491 021d 06 .uleb128 0x6 - 5492 021e 9742 .uleb128 0x2117 - 5493 0220 0C .uleb128 0xc - 5494 0221 01 .uleb128 0x1 - 5495 0222 13 .uleb128 0x13 - 5496 0223 00 .byte 0 - 5497 0224 00 .byte 0 - 5498 0225 24 .uleb128 0x24 - 5499 0226 34 .uleb128 0x34 - 5500 0227 00 .byte 0 - 5501 0228 03 .uleb128 0x3 - 5502 0229 0E .uleb128 0xe - 5503 022a 3A .uleb128 0x3a - 5504 022b 0B .uleb128 0xb - 5505 022c 3B .uleb128 0x3b - 5506 022d 0B .uleb128 0xb - 5507 022e 49 .uleb128 0x49 - 5508 022f 13 .uleb128 0x13 - 5509 0230 02 .uleb128 0x2 - 5510 0231 06 .uleb128 0x6 - 5511 0232 00 .byte 0 - 5512 0233 00 .byte 0 - 5513 0234 25 .uleb128 0x25 - 5514 0235 2E .uleb128 0x2e - 5515 0236 01 .byte 0x1 - 5516 0237 3F .uleb128 0x3f - 5517 0238 0C .uleb128 0xc - 5518 0239 03 .uleb128 0x3 - 5519 023a 0E .uleb128 0xe - 5520 023b 3A .uleb128 0x3a - 5521 023c 0B .uleb128 0xb - 5522 023d 3B .uleb128 0x3b - 5523 023e 05 .uleb128 0x5 - 5524 023f 27 .uleb128 0x27 - 5525 0240 0C .uleb128 0xc - 5526 0241 49 .uleb128 0x49 - 5527 0242 13 .uleb128 0x13 - 5528 0243 11 .uleb128 0x11 - 5529 0244 01 .uleb128 0x1 - 5530 0245 12 .uleb128 0x12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 145 - - - 5531 0246 01 .uleb128 0x1 - 5532 0247 40 .uleb128 0x40 - 5533 0248 0A .uleb128 0xa - 5534 0249 9742 .uleb128 0x2117 - 5535 024b 0C .uleb128 0xc - 5536 024c 01 .uleb128 0x1 - 5537 024d 13 .uleb128 0x13 - 5538 024e 00 .byte 0 - 5539 024f 00 .byte 0 - 5540 0250 26 .uleb128 0x26 - 5541 0251 2E .uleb128 0x2e - 5542 0252 00 .byte 0 - 5543 0253 31 .uleb128 0x31 - 5544 0254 13 .uleb128 0x13 - 5545 0255 11 .uleb128 0x11 - 5546 0256 01 .uleb128 0x1 - 5547 0257 12 .uleb128 0x12 - 5548 0258 01 .uleb128 0x1 - 5549 0259 40 .uleb128 0x40 - 5550 025a 0A .uleb128 0xa - 5551 025b 9742 .uleb128 0x2117 - 5552 025d 0C .uleb128 0xc - 5553 025e 00 .byte 0 - 5554 025f 00 .byte 0 - 5555 0260 27 .uleb128 0x27 - 5556 0261 2E .uleb128 0x2e - 5557 0262 01 .byte 0x1 - 5558 0263 3F .uleb128 0x3f - 5559 0264 0C .uleb128 0xc - 5560 0265 03 .uleb128 0x3 - 5561 0266 0E .uleb128 0xe - 5562 0267 3A .uleb128 0x3a - 5563 0268 0B .uleb128 0xb - 5564 0269 3B .uleb128 0x3b - 5565 026a 05 .uleb128 0x5 - 5566 026b 27 .uleb128 0x27 - 5567 026c 0C .uleb128 0xc - 5568 026d 49 .uleb128 0x49 - 5569 026e 13 .uleb128 0x13 - 5570 026f 11 .uleb128 0x11 - 5571 0270 01 .uleb128 0x1 - 5572 0271 12 .uleb128 0x12 - 5573 0272 01 .uleb128 0x1 - 5574 0273 40 .uleb128 0x40 - 5575 0274 06 .uleb128 0x6 - 5576 0275 9742 .uleb128 0x2117 - 5577 0277 0C .uleb128 0xc - 5578 0278 01 .uleb128 0x1 - 5579 0279 13 .uleb128 0x13 - 5580 027a 00 .byte 0 - 5581 027b 00 .byte 0 - 5582 027c 28 .uleb128 0x28 - 5583 027d 2E .uleb128 0x2e - 5584 027e 00 .byte 0 - 5585 027f 3F .uleb128 0x3f - 5586 0280 0C .uleb128 0xc - 5587 0281 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 146 - - - 5588 0282 0E .uleb128 0xe - 5589 0283 3A .uleb128 0x3a - 5590 0284 0B .uleb128 0xb - 5591 0285 3B .uleb128 0x3b - 5592 0286 05 .uleb128 0x5 - 5593 0287 27 .uleb128 0x27 - 5594 0288 0C .uleb128 0xc - 5595 0289 49 .uleb128 0x49 - 5596 028a 13 .uleb128 0x13 - 5597 028b 11 .uleb128 0x11 - 5598 028c 01 .uleb128 0x1 - 5599 028d 12 .uleb128 0x12 - 5600 028e 01 .uleb128 0x1 - 5601 028f 40 .uleb128 0x40 - 5602 0290 0A .uleb128 0xa - 5603 0291 9742 .uleb128 0x2117 - 5604 0293 0C .uleb128 0xc - 5605 0294 00 .byte 0 - 5606 0295 00 .byte 0 - 5607 0296 29 .uleb128 0x29 - 5608 0297 05 .uleb128 0x5 - 5609 0298 00 .byte 0 - 5610 0299 03 .uleb128 0x3 - 5611 029a 0E .uleb128 0xe - 5612 029b 3A .uleb128 0x3a - 5613 029c 0B .uleb128 0xb - 5614 029d 3B .uleb128 0x3b - 5615 029e 05 .uleb128 0x5 - 5616 029f 49 .uleb128 0x49 - 5617 02a0 13 .uleb128 0x13 - 5618 02a1 02 .uleb128 0x2 - 5619 02a2 0A .uleb128 0xa - 5620 02a3 00 .byte 0 - 5621 02a4 00 .byte 0 - 5622 02a5 2A .uleb128 0x2a - 5623 02a6 898201 .uleb128 0x4109 - 5624 02a9 00 .byte 0 - 5625 02aa 11 .uleb128 0x11 - 5626 02ab 01 .uleb128 0x1 - 5627 02ac 9542 .uleb128 0x2115 - 5628 02ae 0C .uleb128 0xc - 5629 02af 31 .uleb128 0x31 - 5630 02b0 13 .uleb128 0x13 - 5631 02b1 00 .byte 0 - 5632 02b2 00 .byte 0 - 5633 02b3 2B .uleb128 0x2b - 5634 02b4 898201 .uleb128 0x4109 - 5635 02b7 01 .byte 0x1 - 5636 02b8 11 .uleb128 0x11 - 5637 02b9 01 .uleb128 0x1 - 5638 02ba 31 .uleb128 0x31 - 5639 02bb 13 .uleb128 0x13 - 5640 02bc 00 .byte 0 - 5641 02bd 00 .byte 0 - 5642 02be 2C .uleb128 0x2c - 5643 02bf 34 .uleb128 0x34 - 5644 02c0 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 147 - - - 5645 02c1 03 .uleb128 0x3 - 5646 02c2 08 .uleb128 0x8 - 5647 02c3 3A .uleb128 0x3a - 5648 02c4 0B .uleb128 0xb - 5649 02c5 3B .uleb128 0x3b - 5650 02c6 05 .uleb128 0x5 - 5651 02c7 49 .uleb128 0x49 - 5652 02c8 13 .uleb128 0x13 - 5653 02c9 02 .uleb128 0x2 - 5654 02ca 06 .uleb128 0x6 - 5655 02cb 00 .byte 0 - 5656 02cc 00 .byte 0 - 5657 02cd 2D .uleb128 0x2d - 5658 02ce 1D .uleb128 0x1d - 5659 02cf 00 .byte 0 - 5660 02d0 31 .uleb128 0x31 - 5661 02d1 13 .uleb128 0x13 - 5662 02d2 11 .uleb128 0x11 - 5663 02d3 01 .uleb128 0x1 - 5664 02d4 12 .uleb128 0x12 - 5665 02d5 01 .uleb128 0x1 - 5666 02d6 58 .uleb128 0x58 - 5667 02d7 0B .uleb128 0xb - 5668 02d8 59 .uleb128 0x59 - 5669 02d9 05 .uleb128 0x5 - 5670 02da 00 .byte 0 - 5671 02db 00 .byte 0 - 5672 02dc 2E .uleb128 0x2e - 5673 02dd 34 .uleb128 0x34 - 5674 02de 00 .byte 0 - 5675 02df 03 .uleb128 0x3 - 5676 02e0 0E .uleb128 0xe - 5677 02e1 3A .uleb128 0x3a - 5678 02e2 0B .uleb128 0xb - 5679 02e3 3B .uleb128 0x3b - 5680 02e4 05 .uleb128 0x5 - 5681 02e5 49 .uleb128 0x49 - 5682 02e6 13 .uleb128 0x13 - 5683 02e7 1C .uleb128 0x1c - 5684 02e8 0D .uleb128 0xd - 5685 02e9 00 .byte 0 - 5686 02ea 00 .byte 0 - 5687 02eb 2F .uleb128 0x2f - 5688 02ec 34 .uleb128 0x34 - 5689 02ed 00 .byte 0 - 5690 02ee 03 .uleb128 0x3 - 5691 02ef 0E .uleb128 0xe - 5692 02f0 3A .uleb128 0x3a - 5693 02f1 0B .uleb128 0xb - 5694 02f2 3B .uleb128 0x3b - 5695 02f3 0B .uleb128 0xb - 5696 02f4 49 .uleb128 0x49 - 5697 02f5 13 .uleb128 0x13 - 5698 02f6 3F .uleb128 0x3f - 5699 02f7 0C .uleb128 0xc - 5700 02f8 02 .uleb128 0x2 - 5701 02f9 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 148 - - - 5702 02fa 00 .byte 0 - 5703 02fb 00 .byte 0 - 5704 02fc 30 .uleb128 0x30 - 5705 02fd 2E .uleb128 0x2e - 5706 02fe 00 .byte 0 - 5707 02ff 3F .uleb128 0x3f - 5708 0300 0C .uleb128 0xc - 5709 0301 03 .uleb128 0x3 - 5710 0302 0E .uleb128 0xe - 5711 0303 3A .uleb128 0x3a - 5712 0304 0B .uleb128 0xb - 5713 0305 3B .uleb128 0x3b - 5714 0306 0B .uleb128 0xb - 5715 0307 27 .uleb128 0x27 - 5716 0308 0C .uleb128 0xc - 5717 0309 49 .uleb128 0x49 - 5718 030a 13 .uleb128 0x13 - 5719 030b 3C .uleb128 0x3c - 5720 030c 0C .uleb128 0xc - 5721 030d 00 .byte 0 - 5722 030e 00 .byte 0 - 5723 030f 31 .uleb128 0x31 - 5724 0310 2E .uleb128 0x2e - 5725 0311 01 .byte 0x1 - 5726 0312 3F .uleb128 0x3f - 5727 0313 0C .uleb128 0xc - 5728 0314 03 .uleb128 0x3 - 5729 0315 0E .uleb128 0xe - 5730 0316 3A .uleb128 0x3a - 5731 0317 0B .uleb128 0xb - 5732 0318 3B .uleb128 0x3b - 5733 0319 0B .uleb128 0xb - 5734 031a 27 .uleb128 0x27 - 5735 031b 0C .uleb128 0xc - 5736 031c 3C .uleb128 0x3c - 5737 031d 0C .uleb128 0xc - 5738 031e 01 .uleb128 0x1 - 5739 031f 13 .uleb128 0x13 - 5740 0320 00 .byte 0 - 5741 0321 00 .byte 0 - 5742 0322 32 .uleb128 0x32 - 5743 0323 05 .uleb128 0x5 - 5744 0324 00 .byte 0 - 5745 0325 49 .uleb128 0x49 - 5746 0326 13 .uleb128 0x13 - 5747 0327 00 .byte 0 - 5748 0328 00 .byte 0 - 5749 0329 33 .uleb128 0x33 - 5750 032a 2E .uleb128 0x2e - 5751 032b 01 .byte 0x1 - 5752 032c 3F .uleb128 0x3f - 5753 032d 0C .uleb128 0xc - 5754 032e 03 .uleb128 0x3 - 5755 032f 0E .uleb128 0xe - 5756 0330 3A .uleb128 0x3a - 5757 0331 0B .uleb128 0xb - 5758 0332 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 149 - - - 5759 0333 0B .uleb128 0xb - 5760 0334 27 .uleb128 0x27 - 5761 0335 0C .uleb128 0xc - 5762 0336 49 .uleb128 0x49 - 5763 0337 13 .uleb128 0x13 - 5764 0338 3C .uleb128 0x3c - 5765 0339 0C .uleb128 0xc - 5766 033a 01 .uleb128 0x1 - 5767 033b 13 .uleb128 0x13 - 5768 033c 00 .byte 0 - 5769 033d 00 .byte 0 - 5770 033e 34 .uleb128 0x34 - 5771 033f 2E .uleb128 0x2e - 5772 0340 01 .byte 0x1 - 5773 0341 3F .uleb128 0x3f - 5774 0342 0C .uleb128 0xc - 5775 0343 03 .uleb128 0x3 - 5776 0344 0E .uleb128 0xe - 5777 0345 3A .uleb128 0x3a - 5778 0346 0B .uleb128 0xb - 5779 0347 3B .uleb128 0x3b - 5780 0348 0B .uleb128 0xb - 5781 0349 27 .uleb128 0x27 - 5782 034a 0C .uleb128 0xc - 5783 034b 3C .uleb128 0x3c - 5784 034c 0C .uleb128 0xc - 5785 034d 00 .byte 0 - 5786 034e 00 .byte 0 - 5787 034f 00 .byte 0 - 5788 .section .debug_loc,"",%progbits - 5789 .Ldebug_loc0: - 5790 .LLST0: - 5791 0000 00000000 .4byte .LVL0 - 5792 0004 5E000000 .4byte .LVL2 - 5793 0008 0100 .2byte 0x1 - 5794 000a 50 .byte 0x50 - 5795 000b 5E000000 .4byte .LVL2 - 5796 000f 72000000 .4byte .LVL3 - 5797 0013 0400 .2byte 0x4 - 5798 0015 F3 .byte 0xf3 - 5799 0016 01 .uleb128 0x1 - 5800 0017 50 .byte 0x50 - 5801 0018 9F .byte 0x9f - 5802 0019 72000000 .4byte .LVL3 - 5803 001d 80000000 .4byte .LVL4 - 5804 0021 0100 .2byte 0x1 - 5805 0023 50 .byte 0x50 - 5806 0024 80000000 .4byte .LVL4 - 5807 0028 B8000000 .4byte .LFE7 - 5808 002c 0400 .2byte 0x4 - 5809 002e F3 .byte 0xf3 - 5810 002f 01 .uleb128 0x1 - 5811 0030 50 .byte 0x50 - 5812 0031 9F .byte 0x9f - 5813 0032 00000000 .4byte 0 - 5814 0036 00000000 .4byte 0 - 5815 .LLST1: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 150 - - - 5816 003a 00000000 .4byte .LVL0 - 5817 003e 2A000000 .4byte .LVL1 - 5818 0042 0200 .2byte 0x2 - 5819 0044 30 .byte 0x30 - 5820 0045 9F .byte 0x9f - 5821 0046 72000000 .4byte .LVL3 - 5822 004a 80000000 .4byte .LVL4 - 5823 004e 0200 .2byte 0x2 - 5824 0050 31 .byte 0x31 - 5825 0051 9F .byte 0x9f - 5826 0052 00000000 .4byte 0 - 5827 0056 00000000 .4byte 0 - 5828 .LLST2: - 5829 005a 00000000 .4byte .LVL5 - 5830 005e 1C000000 .4byte .LVL6 - 5831 0062 0100 .2byte 0x1 - 5832 0064 50 .byte 0x50 - 5833 0065 1C000000 .4byte .LVL6 - 5834 0069 3C000000 .4byte .LFE14 - 5835 006d 0400 .2byte 0x4 - 5836 006f F3 .byte 0xf3 - 5837 0070 01 .uleb128 0x1 - 5838 0071 50 .byte 0x50 - 5839 0072 9F .byte 0x9f - 5840 0073 00000000 .4byte 0 - 5841 0077 00000000 .4byte 0 - 5842 .LLST3: - 5843 007b 00000000 .4byte .LVL7 - 5844 007f 18000000 .4byte .LVL9 - 5845 0083 0100 .2byte 0x1 - 5846 0085 50 .byte 0x50 - 5847 0086 18000000 .4byte .LVL9 - 5848 008a 2E000000 .4byte .LVL11 - 5849 008e 0200 .2byte 0x2 - 5850 0090 73 .byte 0x73 - 5851 0091 00 .sleb128 0 - 5852 0092 2E000000 .4byte .LVL11 - 5853 0096 34000000 .4byte .LFE2 - 5854 009a 0400 .2byte 0x4 - 5855 009c F3 .byte 0xf3 - 5856 009d 01 .uleb128 0x1 - 5857 009e 50 .byte 0x50 - 5858 009f 9F .byte 0x9f - 5859 00a0 00000000 .4byte 0 - 5860 00a4 00000000 .4byte 0 - 5861 .LLST4: - 5862 00a8 00000000 .4byte .LVL7 - 5863 00ac 14000000 .4byte .LVL8 - 5864 00b0 0100 .2byte 0x1 - 5865 00b2 51 .byte 0x51 - 5866 00b3 14000000 .4byte .LVL8 - 5867 00b7 34000000 .4byte .LFE2 - 5868 00bb 0400 .2byte 0x4 - 5869 00bd F3 .byte 0xf3 - 5870 00be 01 .uleb128 0x1 - 5871 00bf 51 .byte 0x51 - 5872 00c0 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 151 - - - 5873 00c1 00000000 .4byte 0 - 5874 00c5 00000000 .4byte 0 - 5875 .LLST5: - 5876 00c9 00000000 .4byte .LVL7 - 5877 00cd 20000000 .4byte .LVL10 - 5878 00d1 0100 .2byte 0x1 - 5879 00d3 52 .byte 0x52 - 5880 00d4 20000000 .4byte .LVL10 - 5881 00d8 34000000 .4byte .LFE2 - 5882 00dc 0400 .2byte 0x4 - 5883 00de F3 .byte 0xf3 - 5884 00df 01 .uleb128 0x1 - 5885 00e0 52 .byte 0x52 - 5886 00e1 9F .byte 0x9f - 5887 00e2 00000000 .4byte 0 - 5888 00e6 00000000 .4byte 0 - 5889 .LLST6: - 5890 00ea 00000000 .4byte .LVL12 - 5891 00ee 10000000 .4byte .LVL13 - 5892 00f2 0100 .2byte 0x1 - 5893 00f4 50 .byte 0x50 - 5894 00f5 10000000 .4byte .LVL13 - 5895 00f9 14000000 .4byte .LFE3 - 5896 00fd 0400 .2byte 0x4 - 5897 00ff F3 .byte 0xf3 - 5898 0100 01 .uleb128 0x1 - 5899 0101 50 .byte 0x50 - 5900 0102 9F .byte 0x9f - 5901 0103 00000000 .4byte 0 - 5902 0107 00000000 .4byte 0 - 5903 .LLST7: - 5904 010b 00000000 .4byte .LVL14 - 5905 010f 14000000 .4byte .LVL15 - 5906 0113 0100 .2byte 0x1 - 5907 0115 50 .byte 0x50 - 5908 0116 14000000 .4byte .LVL15 - 5909 011a 16000000 .4byte .LVL16 - 5910 011e 0400 .2byte 0x4 - 5911 0120 F3 .byte 0xf3 - 5912 0121 01 .uleb128 0x1 - 5913 0122 50 .byte 0x50 - 5914 0123 9F .byte 0x9f - 5915 0124 16000000 .4byte .LVL16 - 5916 0128 20000000 .4byte .LVL17 - 5917 012c 0100 .2byte 0x1 - 5918 012e 50 .byte 0x50 - 5919 012f 20000000 .4byte .LVL17 - 5920 0133 30000000 .4byte .LVL18 - 5921 0137 0400 .2byte 0x4 - 5922 0139 F3 .byte 0xf3 - 5923 013a 01 .uleb128 0x1 - 5924 013b 50 .byte 0x50 - 5925 013c 9F .byte 0x9f - 5926 013d 30000000 .4byte .LVL18 - 5927 0141 34000000 .4byte .LVL19 - 5928 0145 0100 .2byte 0x1 - 5929 0147 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 152 - - - 5930 0148 34000000 .4byte .LVL19 - 5931 014c 40000000 .4byte .LFE9 - 5932 0150 0400 .2byte 0x4 - 5933 0152 F3 .byte 0xf3 - 5934 0153 01 .uleb128 0x1 - 5935 0154 50 .byte 0x50 - 5936 0155 9F .byte 0x9f - 5937 0156 00000000 .4byte 0 - 5938 015a 00000000 .4byte 0 - 5939 .LLST8: - 5940 015e 00000000 .4byte .LFB8 - 5941 0162 02000000 .4byte .LCFI0 - 5942 0166 0200 .2byte 0x2 - 5943 0168 7D .byte 0x7d - 5944 0169 00 .sleb128 0 - 5945 016a 02000000 .4byte .LCFI0 - 5946 016e D8000000 .4byte .LFE8 - 5947 0172 0200 .2byte 0x2 - 5948 0174 7D .byte 0x7d - 5949 0175 10 .sleb128 16 - 5950 0176 00000000 .4byte 0 - 5951 017a 00000000 .4byte 0 - 5952 .LLST9: - 5953 017e 00000000 .4byte .LVL20 - 5954 0182 30000000 .4byte .LVL27 - 5955 0186 0100 .2byte 0x1 - 5956 0188 50 .byte 0x50 - 5957 0189 30000000 .4byte .LVL27 - 5958 018d D8000000 .4byte .LFE8 - 5959 0191 0400 .2byte 0x4 - 5960 0193 F3 .byte 0xf3 - 5961 0194 01 .uleb128 0x1 - 5962 0195 50 .byte 0x50 - 5963 0196 9F .byte 0x9f - 5964 0197 00000000 .4byte 0 - 5965 019b 00000000 .4byte 0 - 5966 .LLST10: - 5967 019f 14000000 .4byte .LVL21 - 5968 01a3 22000000 .4byte .LVL22 - 5969 01a7 0100 .2byte 0x1 - 5970 01a9 55 .byte 0x55 - 5971 01aa 24000000 .4byte .LVL23 - 5972 01ae 26000000 .4byte .LVL24 - 5973 01b2 0200 .2byte 0x2 - 5974 01b4 33 .byte 0x33 - 5975 01b5 9F .byte 0x9f - 5976 01b6 2C000000 .4byte .LVL25 - 5977 01ba 2E000000 .4byte .LVL26 - 5978 01be 0100 .2byte 0x1 - 5979 01c0 55 .byte 0x55 - 5980 01c1 00000000 .4byte 0 - 5981 01c5 00000000 .4byte 0 - 5982 .LLST11: - 5983 01c9 00000000 .4byte .LVL32 - 5984 01cd 06000000 .4byte .LVL33 - 5985 01d1 0100 .2byte 0x1 - 5986 01d3 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 153 - - - 5987 01d4 06000000 .4byte .LVL33 - 5988 01d8 18000000 .4byte .LFE12 - 5989 01dc 0400 .2byte 0x4 - 5990 01de F3 .byte 0xf3 - 5991 01df 01 .uleb128 0x1 - 5992 01e0 50 .byte 0x50 - 5993 01e1 9F .byte 0x9f - 5994 01e2 00000000 .4byte 0 - 5995 01e6 00000000 .4byte 0 - 5996 .LLST12: - 5997 01ea 00000000 .4byte .LFB15 - 5998 01ee 02000000 .4byte .LCFI1 - 5999 01f2 0200 .2byte 0x2 - 6000 01f4 7D .byte 0x7d - 6001 01f5 00 .sleb128 0 - 6002 01f6 02000000 .4byte .LCFI1 - 6003 01fa 6C000000 .4byte .LFE15 - 6004 01fe 0200 .2byte 0x2 - 6005 0200 7D .byte 0x7d - 6006 0201 18 .sleb128 24 - 6007 0202 00000000 .4byte 0 - 6008 0206 00000000 .4byte 0 - 6009 .LLST13: - 6010 020a 00000000 .4byte .LVL35 - 6011 020e 07000000 .4byte .LVL36-1 - 6012 0212 0100 .2byte 0x1 - 6013 0214 50 .byte 0x50 - 6014 0215 07000000 .4byte .LVL36-1 - 6015 0219 6C000000 .4byte .LFE15 - 6016 021d 0400 .2byte 0x4 - 6017 021f F3 .byte 0xf3 - 6018 0220 01 .uleb128 0x1 - 6019 0221 50 .byte 0x50 - 6020 0222 9F .byte 0x9f - 6021 0223 00000000 .4byte 0 - 6022 0227 00000000 .4byte 0 - 6023 .LLST14: - 6024 022b 22000000 .4byte .LVL41 - 6025 022f 2E000000 .4byte .LVL45 - 6026 0233 0100 .2byte 0x1 - 6027 0235 53 .byte 0x53 - 6028 0236 3C000000 .4byte .LVL47 - 6029 023a 41000000 .4byte .LVL48-1 - 6030 023e 0100 .2byte 0x1 - 6031 0240 53 .byte 0x53 - 6032 0241 00000000 .4byte 0 - 6033 0245 00000000 .4byte 0 - 6034 .LLST15: - 6035 0249 10000000 .4byte .LVL39 - 6036 024d 12000000 .4byte .LVL40 - 6037 0251 0800 .2byte 0x8 - 6038 0253 72 .byte 0x72 - 6039 0254 00 .sleb128 0 - 6040 0255 08 .byte 0x8 - 6041 0256 FF .byte 0xff - 6042 0257 1A .byte 0x1a - 6043 0258 38 .byte 0x38 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 154 - - - 6044 0259 24 .byte 0x24 - 6045 025a 9F .byte 0x9f - 6046 025b 12000000 .4byte .LVL40 - 6047 025f 26000000 .4byte .LVL43 - 6048 0263 0E00 .2byte 0xe - 6049 0265 72 .byte 0x72 - 6050 0266 00 .sleb128 0 - 6051 0267 08 .byte 0x8 - 6052 0268 FF .byte 0xff - 6053 0269 1A .byte 0x1a - 6054 026a 38 .byte 0x38 - 6055 026b 24 .byte 0x24 - 6056 026c 71 .byte 0x71 - 6057 026d 00 .sleb128 0 - 6058 026e 08 .byte 0x8 - 6059 026f FF .byte 0xff - 6060 0270 1A .byte 0x1a - 6061 0271 21 .byte 0x21 - 6062 0272 9F .byte 0x9f - 6063 0273 50000000 .4byte .LVL50 - 6064 0277 55000000 .4byte .LVL51-1 - 6065 027b 0E00 .2byte 0xe - 6066 027d 72 .byte 0x72 - 6067 027e 00 .sleb128 0 - 6068 027f 08 .byte 0x8 - 6069 0280 FF .byte 0xff - 6070 0281 1A .byte 0x1a - 6071 0282 38 .byte 0x38 - 6072 0283 24 .byte 0x24 - 6073 0284 71 .byte 0x71 - 6074 0285 00 .sleb128 0 - 6075 0286 08 .byte 0x8 - 6076 0287 FF .byte 0xff - 6077 0288 1A .byte 0x1a - 6078 0289 21 .byte 0x21 - 6079 028a 9F .byte 0x9f - 6080 028b 00000000 .4byte 0 - 6081 028f 00000000 .4byte 0 - 6082 .LLST16: - 6083 0293 0C000000 .4byte .LVL37 - 6084 0297 0E000000 .4byte .LVL38 - 6085 029b 0100 .2byte 0x1 - 6086 029d 50 .byte 0x50 - 6087 029e 0E000000 .4byte .LVL38 - 6088 02a2 6C000000 .4byte .LFE15 - 6089 02a6 0100 .2byte 0x1 - 6090 02a8 56 .byte 0x56 - 6091 02a9 00000000 .4byte 0 - 6092 02ad 00000000 .4byte 0 - 6093 .LLST17: - 6094 02b1 24000000 .4byte .LVL42 - 6095 02b5 28000000 .4byte .LVL44 - 6096 02b9 0200 .2byte 0x2 - 6097 02bb 37 .byte 0x37 - 6098 02bc 9F .byte 0x9f - 6099 02bd 00000000 .4byte 0 - 6100 02c1 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 155 - - - 6101 .LLST18: - 6102 02c5 4A000000 .4byte .LVL49 - 6103 02c9 50000000 .4byte .LVL50 - 6104 02cd 0100 .2byte 0x1 - 6105 02cf 57 .byte 0x57 - 6106 02d0 00000000 .4byte 0 - 6107 02d4 00000000 .4byte 0 - 6108 .LLST19: - 6109 02d8 00000000 .4byte .LVL53 - 6110 02dc 06000000 .4byte .LVL54 - 6111 02e0 0100 .2byte 0x1 - 6112 02e2 50 .byte 0x50 - 6113 02e3 06000000 .4byte .LVL54 - 6114 02e7 18000000 .4byte .LFE16 - 6115 02eb 0400 .2byte 0x4 - 6116 02ed F3 .byte 0xf3 - 6117 02ee 01 .uleb128 0x1 - 6118 02ef 50 .byte 0x50 - 6119 02f0 9F .byte 0x9f - 6120 02f1 00000000 .4byte 0 - 6121 02f5 00000000 .4byte 0 - 6122 .LLST20: - 6123 02f9 00000000 .4byte .LFB4 - 6124 02fd 02000000 .4byte .LCFI2 - 6125 0301 0200 .2byte 0x2 - 6126 0303 7D .byte 0x7d - 6127 0304 00 .sleb128 0 - 6128 0305 02000000 .4byte .LCFI2 - 6129 0309 50000000 .4byte .LFE4 - 6130 030d 0200 .2byte 0x2 - 6131 030f 7D .byte 0x7d - 6132 0310 10 .sleb128 16 - 6133 0311 00000000 .4byte 0 - 6134 0315 00000000 .4byte 0 - 6135 .LLST21: - 6136 0319 00000000 .4byte .LVL55 - 6137 031d 24000000 .4byte .LVL56 - 6138 0321 0100 .2byte 0x1 - 6139 0323 50 .byte 0x50 - 6140 0324 24000000 .4byte .LVL56 - 6141 0328 50000000 .4byte .LFE4 - 6142 032c 0400 .2byte 0x4 - 6143 032e F3 .byte 0xf3 - 6144 032f 01 .uleb128 0x1 - 6145 0330 50 .byte 0x50 - 6146 0331 9F .byte 0x9f - 6147 0332 00000000 .4byte 0 - 6148 0336 00000000 .4byte 0 - 6149 .LLST22: - 6150 033a 2C000000 .4byte .LVL59 - 6151 033e 46000000 .4byte .LVL63 - 6152 0342 0100 .2byte 0x1 - 6153 0344 54 .byte 0x54 - 6154 0345 00000000 .4byte 0 - 6155 0349 00000000 .4byte 0 - 6156 .LLST23: - 6157 034d 26000000 .4byte .LVL57 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 156 - - - 6158 0351 46000000 .4byte .LVL63 - 6159 0355 0100 .2byte 0x1 - 6160 0357 55 .byte 0x55 - 6161 0358 00000000 .4byte 0 - 6162 035c 00000000 .4byte 0 - 6163 .LLST24: - 6164 0360 26000000 .4byte .LVL57 - 6165 0364 28000000 .4byte .LVL58 - 6166 0368 0100 .2byte 0x1 - 6167 036a 50 .byte 0x50 - 6168 036b 28000000 .4byte .LVL58 - 6169 036f 46000000 .4byte .LVL63 - 6170 0373 0100 .2byte 0x1 - 6171 0375 56 .byte 0x56 - 6172 0376 00000000 .4byte 0 - 6173 037a 00000000 .4byte 0 - 6174 .LLST25: - 6175 037e 00000000 .4byte .LFB0 - 6176 0382 02000000 .4byte .LCFI3 - 6177 0386 0200 .2byte 0x2 - 6178 0388 7D .byte 0x7d - 6179 0389 00 .sleb128 0 - 6180 038a 02000000 .4byte .LCFI3 - 6181 038e 68000000 .4byte .LFE0 - 6182 0392 0200 .2byte 0x2 - 6183 0394 7D .byte 0x7d - 6184 0395 18 .sleb128 24 - 6185 0396 00000000 .4byte 0 - 6186 039a 00000000 .4byte 0 - 6187 .LLST26: - 6188 039e 00000000 .4byte .LVL64 - 6189 03a2 1A000000 .4byte .LVL65 - 6190 03a6 0100 .2byte 0x1 - 6191 03a8 50 .byte 0x50 - 6192 03a9 1A000000 .4byte .LVL65 - 6193 03ad 54000000 .4byte .LVL73 - 6194 03b1 0400 .2byte 0x4 - 6195 03b3 F3 .byte 0xf3 - 6196 03b4 01 .uleb128 0x1 - 6197 03b5 50 .byte 0x50 - 6198 03b6 9F .byte 0x9f - 6199 03b7 54000000 .4byte .LVL73 - 6200 03bb 56000000 .4byte .LVL74 - 6201 03bf 0100 .2byte 0x1 - 6202 03c1 50 .byte 0x50 - 6203 03c2 56000000 .4byte .LVL74 - 6204 03c6 68000000 .4byte .LFE0 - 6205 03ca 0400 .2byte 0x4 - 6206 03cc F3 .byte 0xf3 - 6207 03cd 01 .uleb128 0x1 - 6208 03ce 50 .byte 0x50 - 6209 03cf 9F .byte 0x9f - 6210 03d0 00000000 .4byte 0 - 6211 03d4 00000000 .4byte 0 - 6212 .LLST27: - 6213 03d8 00000000 .4byte .LVL64 - 6214 03dc 26000000 .4byte .LVL69 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 157 - - - 6215 03e0 0200 .2byte 0x2 - 6216 03e2 30 .byte 0x30 - 6217 03e3 9F .byte 0x9f - 6218 03e4 26000000 .4byte .LVL69 - 6219 03e8 46000000 .4byte .LVL71 - 6220 03ec 0200 .2byte 0x2 - 6221 03ee 40 .byte 0x40 - 6222 03ef 9F .byte 0x9f - 6223 03f0 46000000 .4byte .LVL71 - 6224 03f4 54000000 .4byte .LVL73 - 6225 03f8 0100 .2byte 0x1 - 6226 03fa 54 .byte 0x54 - 6227 03fb 54000000 .4byte .LVL73 - 6228 03ff 56000000 .4byte .LVL74 - 6229 0403 0200 .2byte 0x2 - 6230 0405 30 .byte 0x30 - 6231 0406 9F .byte 0x9f - 6232 0407 56000000 .4byte .LVL74 - 6233 040b 68000000 .4byte .LFE0 - 6234 040f 0100 .2byte 0x1 - 6235 0411 54 .byte 0x54 - 6236 0412 00000000 .4byte 0 - 6237 0416 00000000 .4byte 0 - 6238 .LLST28: - 6239 041a 1C000000 .4byte .LVL66 - 6240 041e 1E000000 .4byte .LVL67 - 6241 0422 0100 .2byte 0x1 - 6242 0424 50 .byte 0x50 - 6243 0425 1E000000 .4byte .LVL67 - 6244 0429 54000000 .4byte .LVL73 - 6245 042d 0100 .2byte 0x1 - 6246 042f 57 .byte 0x57 - 6247 0430 00000000 .4byte 0 - 6248 0434 00000000 .4byte 0 - 6249 .LLST29: - 6250 0438 1C000000 .4byte .LVL66 - 6251 043c 54000000 .4byte .LVL73 - 6252 0440 0100 .2byte 0x1 - 6253 0442 56 .byte 0x56 - 6254 0443 00000000 .4byte 0 - 6255 0447 00000000 .4byte 0 - 6256 .LLST30: - 6257 044b 22000000 .4byte .LVL68 - 6258 044f 54000000 .4byte .LVL73 - 6259 0453 0100 .2byte 0x1 - 6260 0455 55 .byte 0x55 - 6261 0456 00000000 .4byte 0 - 6262 045a 00000000 .4byte 0 - 6263 .LLST31: - 6264 045e 00000000 .4byte .LVL75 - 6265 0462 08000000 .4byte .LVL76 - 6266 0466 0100 .2byte 0x1 - 6267 0468 50 .byte 0x50 - 6268 0469 08000000 .4byte .LVL76 - 6269 046d 18000000 .4byte .LFE23 - 6270 0471 0400 .2byte 0x4 - 6271 0473 F3 .byte 0xf3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 158 - - - 6272 0474 01 .uleb128 0x1 - 6273 0475 50 .byte 0x50 - 6274 0476 9F .byte 0x9f - 6275 0477 00000000 .4byte 0 - 6276 047b 00000000 .4byte 0 - 6277 .LLST32: - 6278 047f 00000000 .4byte .LVL77 - 6279 0483 16000000 .4byte .LVL79 - 6280 0487 0100 .2byte 0x1 - 6281 0489 50 .byte 0x50 - 6282 048a 16000000 .4byte .LVL79 - 6283 048e 1C000000 .4byte .LFE24 - 6284 0492 0400 .2byte 0x4 - 6285 0494 F3 .byte 0xf3 - 6286 0495 01 .uleb128 0x1 - 6287 0496 50 .byte 0x50 - 6288 0497 9F .byte 0x9f - 6289 0498 00000000 .4byte 0 - 6290 049c 00000000 .4byte 0 - 6291 .LLST33: - 6292 04a0 00000000 .4byte .LFB29 - 6293 04a4 02000000 .4byte .LCFI4 - 6294 04a8 0200 .2byte 0x2 - 6295 04aa 7D .byte 0x7d - 6296 04ab 00 .sleb128 0 - 6297 04ac 02000000 .4byte .LCFI4 - 6298 04b0 88000000 .4byte .LFE29 - 6299 04b4 0200 .2byte 0x2 - 6300 04b6 7D .byte 0x7d - 6301 04b7 20 .sleb128 32 - 6302 04b8 00000000 .4byte 0 - 6303 04bc 00000000 .4byte 0 - 6304 .LLST34: - 6305 04c0 00000000 .4byte .LVL80 - 6306 04c4 14000000 .4byte .LVL82 - 6307 04c8 0100 .2byte 0x1 - 6308 04ca 50 .byte 0x50 - 6309 04cb 14000000 .4byte .LVL82 - 6310 04cf 7A000000 .4byte .LVL101 - 6311 04d3 0200 .2byte 0x2 - 6312 04d5 91 .byte 0x91 - 6313 04d6 66 .sleb128 -26 - 6314 04d7 7A000000 .4byte .LVL101 - 6315 04db 7C000000 .4byte .LVL102 - 6316 04df 0100 .2byte 0x1 - 6317 04e1 50 .byte 0x50 - 6318 04e2 7C000000 .4byte .LVL102 - 6319 04e6 88000000 .4byte .LFE29 - 6320 04ea 0200 .2byte 0x2 - 6321 04ec 91 .byte 0x91 - 6322 04ed 66 .sleb128 -26 - 6323 04ee 00000000 .4byte 0 - 6324 04f2 00000000 .4byte 0 - 6325 .LLST35: - 6326 04f6 00000000 .4byte .LVL80 - 6327 04fa 24000000 .4byte .LVL86 - 6328 04fe 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 159 - - - 6329 0500 30 .byte 0x30 - 6330 0501 9F .byte 0x9f - 6331 0502 24000000 .4byte .LVL86 - 6332 0506 66000000 .4byte .LVL98 - 6333 050a 0200 .2byte 0x2 - 6334 050c 40 .byte 0x40 - 6335 050d 9F .byte 0x9f - 6336 050e 66000000 .4byte .LVL98 - 6337 0512 7A000000 .4byte .LVL101 - 6338 0516 0100 .2byte 0x1 - 6339 0518 54 .byte 0x54 - 6340 0519 7A000000 .4byte .LVL101 - 6341 051d 7C000000 .4byte .LVL102 - 6342 0521 0200 .2byte 0x2 - 6343 0523 30 .byte 0x30 - 6344 0524 9F .byte 0x9f - 6345 0525 7C000000 .4byte .LVL102 - 6346 0529 88000000 .4byte .LFE29 - 6347 052d 0100 .2byte 0x1 - 6348 052f 54 .byte 0x54 - 6349 0530 00000000 .4byte 0 - 6350 0534 00000000 .4byte 0 - 6351 .LLST36: - 6352 0538 08000000 .4byte .LVL81 - 6353 053c 28000000 .4byte .LVL87 - 6354 0540 0200 .2byte 0x2 - 6355 0542 91 .byte 0x91 - 6356 0543 66 .sleb128 -26 - 6357 0544 28000000 .4byte .LVL87 - 6358 0548 2E000000 .4byte .LVL88 - 6359 054c 0100 .2byte 0x1 - 6360 054e 50 .byte 0x50 - 6361 054f 5A000000 .4byte .LVL95 - 6362 0553 5E000000 .4byte .LVL96 - 6363 0557 0100 .2byte 0x1 - 6364 0559 51 .byte 0x51 - 6365 055a 5E000000 .4byte .LVL96 - 6366 055e 64000000 .4byte .LVL97 - 6367 0562 0100 .2byte 0x1 - 6368 0564 54 .byte 0x54 - 6369 0565 64000000 .4byte .LVL97 - 6370 0569 71000000 .4byte .LVL100-1 - 6371 056d 0100 .2byte 0x1 - 6372 056f 50 .byte 0x50 - 6373 0570 72000000 .4byte .LVL100 - 6374 0574 7A000000 .4byte .LVL101 - 6375 0578 0100 .2byte 0x1 - 6376 057a 50 .byte 0x50 - 6377 057b 7A000000 .4byte .LVL101 - 6378 057f 7C000000 .4byte .LVL102 - 6379 0583 0200 .2byte 0x2 - 6380 0585 91 .byte 0x91 - 6381 0586 66 .sleb128 -26 - 6382 0587 7C000000 .4byte .LVL102 - 6383 058b 7E000000 .4byte .LVL103 - 6384 058f 0100 .2byte 0x1 - 6385 0591 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 160 - - - 6386 0592 7E000000 .4byte .LVL103 - 6387 0596 88000000 .4byte .LFE29 - 6388 059a 0200 .2byte 0x2 - 6389 059c 91 .byte 0x91 - 6390 059d 66 .sleb128 -26 - 6391 059e 00000000 .4byte 0 - 6392 05a2 00000000 .4byte 0 - 6393 .LLST37: - 6394 05a6 30000000 .4byte .LVL89 - 6395 05aa 38000000 .4byte .LVL90 - 6396 05ae 0100 .2byte 0x1 - 6397 05b0 50 .byte 0x50 - 6398 05b1 38000000 .4byte .LVL90 - 6399 05b5 3A000000 .4byte .LVL91 - 6400 05b9 0100 .2byte 0x1 - 6401 05bb 54 .byte 0x54 - 6402 05bc 48000000 .4byte .LVL93 - 6403 05c0 4C000000 .4byte .LVL94 - 6404 05c4 0100 .2byte 0x1 - 6405 05c6 52 .byte 0x52 - 6406 05c7 00000000 .4byte 0 - 6407 05cb 00000000 .4byte 0 - 6408 .LLST38: - 6409 05cf 18000000 .4byte .LVL83 - 6410 05d3 6A000000 .4byte .LVL99 - 6411 05d7 0100 .2byte 0x1 - 6412 05d9 57 .byte 0x57 - 6413 05da 00000000 .4byte 0 - 6414 05de 00000000 .4byte 0 - 6415 .LLST39: - 6416 05e2 1C000000 .4byte .LVL84 - 6417 05e6 7A000000 .4byte .LVL101 - 6418 05ea 0100 .2byte 0x1 - 6419 05ec 56 .byte 0x56 - 6420 05ed 00000000 .4byte 0 - 6421 05f1 00000000 .4byte 0 - 6422 .LLST40: - 6423 05f5 20000000 .4byte .LVL85 - 6424 05f9 7A000000 .4byte .LVL101 - 6425 05fd 0100 .2byte 0x1 - 6426 05ff 55 .byte 0x55 - 6427 0600 00000000 .4byte 0 - 6428 0604 00000000 .4byte 0 - 6429 .LLST41: - 6430 0608 00000000 .4byte .LVL104 - 6431 060c 06000000 .4byte .LVL105 - 6432 0610 0100 .2byte 0x1 - 6433 0612 50 .byte 0x50 - 6434 0613 06000000 .4byte .LVL105 - 6435 0617 18000000 .4byte .LFE36 - 6436 061b 0400 .2byte 0x4 - 6437 061d F3 .byte 0xf3 - 6438 061e 01 .uleb128 0x1 - 6439 061f 50 .byte 0x50 - 6440 0620 9F .byte 0x9f - 6441 0621 00000000 .4byte 0 - 6442 0625 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 161 - - - 6443 .LLST42: - 6444 0629 00000000 .4byte .LVL106 - 6445 062d 06000000 .4byte .LVL107 - 6446 0631 0100 .2byte 0x1 - 6447 0633 50 .byte 0x50 - 6448 0634 06000000 .4byte .LVL107 - 6449 0638 18000000 .4byte .LFE37 - 6450 063c 0400 .2byte 0x4 - 6451 063e F3 .byte 0xf3 - 6452 063f 01 .uleb128 0x1 - 6453 0640 50 .byte 0x50 - 6454 0641 9F .byte 0x9f - 6455 0642 00000000 .4byte 0 - 6456 0646 00000000 .4byte 0 - 6457 .LLST43: - 6458 064a 00000000 .4byte .LVL108 - 6459 064e 04000000 .4byte .LVL109 - 6460 0652 0100 .2byte 0x1 - 6461 0654 50 .byte 0x50 - 6462 0655 04000000 .4byte .LVL109 - 6463 0659 1C000000 .4byte .LFE38 - 6464 065d 0400 .2byte 0x4 - 6465 065f F3 .byte 0xf3 - 6466 0660 01 .uleb128 0x1 - 6467 0661 50 .byte 0x50 - 6468 0662 9F .byte 0x9f - 6469 0663 00000000 .4byte 0 - 6470 0667 00000000 .4byte 0 - 6471 .LLST44: - 6472 066b 00000000 .4byte .LFB41 - 6473 066f 02000000 .4byte .LCFI5 - 6474 0673 0200 .2byte 0x2 - 6475 0675 7D .byte 0x7d - 6476 0676 00 .sleb128 0 - 6477 0677 02000000 .4byte .LCFI5 - 6478 067b 28000000 .4byte .LFE41 - 6479 067f 0200 .2byte 0x2 - 6480 0681 7D .byte 0x7d - 6481 0682 08 .sleb128 8 - 6482 0683 00000000 .4byte 0 - 6483 0687 00000000 .4byte 0 - 6484 .LLST45: - 6485 068b 00000000 .4byte .LVL111 - 6486 068f 04000000 .4byte .LVL112 - 6487 0693 0100 .2byte 0x1 - 6488 0695 50 .byte 0x50 - 6489 0696 04000000 .4byte .LVL112 - 6490 069a 28000000 .4byte .LFE41 - 6491 069e 0100 .2byte 0x1 - 6492 06a0 54 .byte 0x54 - 6493 06a1 00000000 .4byte 0 - 6494 06a5 00000000 .4byte 0 - 6495 .LLST46: - 6496 06a9 00000000 .4byte .LVL116 - 6497 06ad 06000000 .4byte .LVL117 - 6498 06b1 0100 .2byte 0x1 - 6499 06b3 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 162 - - - 6500 06b4 06000000 .4byte .LVL117 - 6501 06b8 10000000 .4byte .LFE42 - 6502 06bc 0400 .2byte 0x4 - 6503 06be F3 .byte 0xf3 - 6504 06bf 01 .uleb128 0x1 - 6505 06c0 50 .byte 0x50 - 6506 06c1 9F .byte 0x9f - 6507 06c2 00000000 .4byte 0 - 6508 06c6 00000000 .4byte 0 - 6509 .LLST47: - 6510 06ca 00000000 .4byte .LFB28 - 6511 06ce 02000000 .4byte .LCFI6 - 6512 06d2 0200 .2byte 0x2 - 6513 06d4 7D .byte 0x7d - 6514 06d5 00 .sleb128 0 - 6515 06d6 02000000 .4byte .LCFI6 - 6516 06da 6C000000 .4byte .LFE28 - 6517 06de 0200 .2byte 0x2 - 6518 06e0 7D .byte 0x7d - 6519 06e1 10 .sleb128 16 - 6520 06e2 00000000 .4byte 0 - 6521 06e6 00000000 .4byte 0 - 6522 .LLST48: - 6523 06ea 00000000 .4byte .LVL119 - 6524 06ee 1C000000 .4byte .LVL121 - 6525 06f2 0100 .2byte 0x1 - 6526 06f4 50 .byte 0x50 - 6527 06f5 1C000000 .4byte .LVL121 - 6528 06f9 1F000000 .4byte .LVL122-1 - 6529 06fd 0200 .2byte 0x2 - 6530 06ff 71 .byte 0x71 - 6531 0700 00 .sleb128 0 - 6532 0701 1F000000 .4byte .LVL122-1 - 6533 0705 3A000000 .4byte .LVL124 - 6534 0709 0400 .2byte 0x4 - 6535 070b F3 .byte 0xf3 - 6536 070c 01 .uleb128 0x1 - 6537 070d 50 .byte 0x50 - 6538 070e 9F .byte 0x9f - 6539 070f 3A000000 .4byte .LVL124 - 6540 0713 40000000 .4byte .LVL125 - 6541 0717 0100 .2byte 0x1 - 6542 0719 50 .byte 0x50 - 6543 071a 40000000 .4byte .LVL125 - 6544 071e 6C000000 .4byte .LFE28 - 6545 0722 0400 .2byte 0x4 - 6546 0724 F3 .byte 0xf3 - 6547 0725 01 .uleb128 0x1 - 6548 0726 50 .byte 0x50 - 6549 0727 9F .byte 0x9f - 6550 0728 00000000 .4byte 0 - 6551 072c 00000000 .4byte 0 - 6552 .LLST49: - 6553 0730 00000000 .4byte .LFB25 - 6554 0734 02000000 .4byte .LCFI7 - 6555 0738 0200 .2byte 0x2 - 6556 073a 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 163 - - - 6557 073b 00 .sleb128 0 - 6558 073c 02000000 .4byte .LCFI7 - 6559 0740 70000000 .4byte .LFE25 - 6560 0744 0200 .2byte 0x2 - 6561 0746 7D .byte 0x7d - 6562 0747 10 .sleb128 16 - 6563 0748 00000000 .4byte 0 - 6564 074c 00000000 .4byte 0 - 6565 .LLST50: - 6566 0750 2C000000 .4byte .LVL127 - 6567 0754 34000000 .4byte .LVL128 - 6568 0758 0100 .2byte 0x1 - 6569 075a 53 .byte 0x53 - 6570 075b 34000000 .4byte .LVL128 - 6571 075f 56000000 .4byte .LVL131 - 6572 0763 0200 .2byte 0x2 - 6573 0765 91 .byte 0x91 - 6574 0766 76 .sleb128 -10 - 6575 0767 56000000 .4byte .LVL131 - 6576 076b 5A000000 .4byte .LVL132 - 6577 076f 0100 .2byte 0x1 - 6578 0771 52 .byte 0x52 - 6579 0772 5C000000 .4byte .LVL133 - 6580 0776 70000000 .4byte .LFE25 - 6581 077a 0200 .2byte 0x2 - 6582 077c 91 .byte 0x91 - 6583 077d 76 .sleb128 -10 - 6584 077e 00000000 .4byte 0 - 6585 0782 00000000 .4byte 0 - 6586 .LLST51: - 6587 0786 00000000 .4byte .LVL134 - 6588 078a 12000000 .4byte .LVL135 - 6589 078e 0100 .2byte 0x1 - 6590 0790 50 .byte 0x50 - 6591 0791 12000000 .4byte .LVL135 - 6592 0795 40000000 .4byte .LFE43 - 6593 0799 0400 .2byte 0x4 - 6594 079b F3 .byte 0xf3 - 6595 079c 01 .uleb128 0x1 - 6596 079d 50 .byte 0x50 - 6597 079e 9F .byte 0x9f - 6598 079f 00000000 .4byte 0 - 6599 07a3 00000000 .4byte 0 - 6600 .LLST52: - 6601 07a7 00000000 .4byte .LVL136 - 6602 07ab 06000000 .4byte .LVL137 - 6603 07af 0100 .2byte 0x1 - 6604 07b1 50 .byte 0x50 - 6605 07b2 06000000 .4byte .LVL137 - 6606 07b6 40000000 .4byte .LFE44 - 6607 07ba 0400 .2byte 0x4 - 6608 07bc F3 .byte 0xf3 - 6609 07bd 01 .uleb128 0x1 - 6610 07be 50 .byte 0x50 - 6611 07bf 9F .byte 0x9f - 6612 07c0 00000000 .4byte 0 - 6613 07c4 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 164 - - - 6614 .LLST53: - 6615 07c8 00000000 .4byte .LVL136 - 6616 07cc 0A000000 .4byte .LVL138 - 6617 07d0 0100 .2byte 0x1 - 6618 07d2 51 .byte 0x51 - 6619 07d3 0A000000 .4byte .LVL138 - 6620 07d7 40000000 .4byte .LFE44 - 6621 07db 0400 .2byte 0x4 - 6622 07dd F3 .byte 0xf3 - 6623 07de 01 .uleb128 0x1 - 6624 07df 51 .byte 0x51 - 6625 07e0 9F .byte 0x9f - 6626 07e1 00000000 .4byte 0 - 6627 07e5 00000000 .4byte 0 - 6628 .LLST54: - 6629 07e9 00000000 .4byte .LFB46 - 6630 07ed 02000000 .4byte .LCFI8 - 6631 07f1 0200 .2byte 0x2 - 6632 07f3 7D .byte 0x7d - 6633 07f4 00 .sleb128 0 - 6634 07f5 02000000 .4byte .LCFI8 - 6635 07f9 68000000 .4byte .LFE46 - 6636 07fd 0200 .2byte 0x2 - 6637 07ff 7D .byte 0x7d - 6638 0800 10 .sleb128 16 - 6639 0801 00000000 .4byte 0 - 6640 0805 00000000 .4byte 0 - 6641 .LLST55: - 6642 0809 00000000 .4byte .LVL139 - 6643 080d 0E000000 .4byte .LVL140 - 6644 0811 0100 .2byte 0x1 - 6645 0813 50 .byte 0x50 - 6646 0814 0E000000 .4byte .LVL140 - 6647 0818 68000000 .4byte .LFE46 - 6648 081c 0400 .2byte 0x4 - 6649 081e F3 .byte 0xf3 - 6650 081f 01 .uleb128 0x1 - 6651 0820 50 .byte 0x50 - 6652 0821 9F .byte 0x9f - 6653 0822 00000000 .4byte 0 - 6654 0826 00000000 .4byte 0 - 6655 .LLST56: - 6656 082a 00000000 .4byte .LVL139 - 6657 082e 12000000 .4byte .LVL141 - 6658 0832 0100 .2byte 0x1 - 6659 0834 51 .byte 0x51 - 6660 0835 12000000 .4byte .LVL141 - 6661 0839 68000000 .4byte .LFE46 - 6662 083d 0400 .2byte 0x4 - 6663 083f F3 .byte 0xf3 - 6664 0840 01 .uleb128 0x1 - 6665 0841 51 .byte 0x51 - 6666 0842 9F .byte 0x9f - 6667 0843 00000000 .4byte 0 - 6668 0847 00000000 .4byte 0 - 6669 .LLST57: - 6670 084b 00000000 .4byte .LFB47 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 165 - - - 6671 084f 02000000 .4byte .LCFI9 - 6672 0853 0200 .2byte 0x2 - 6673 0855 7D .byte 0x7d - 6674 0856 00 .sleb128 0 - 6675 0857 02000000 .4byte .LCFI9 - 6676 085b 68000000 .4byte .LFE47 - 6677 085f 0200 .2byte 0x2 - 6678 0861 7D .byte 0x7d - 6679 0862 10 .sleb128 16 - 6680 0863 00000000 .4byte 0 - 6681 0867 00000000 .4byte 0 - 6682 .LLST58: - 6683 086b 00000000 .4byte .LVL143 - 6684 086f 0E000000 .4byte .LVL144 - 6685 0873 0100 .2byte 0x1 - 6686 0875 50 .byte 0x50 - 6687 0876 0E000000 .4byte .LVL144 - 6688 087a 68000000 .4byte .LFE47 - 6689 087e 0400 .2byte 0x4 - 6690 0880 F3 .byte 0xf3 - 6691 0881 01 .uleb128 0x1 - 6692 0882 50 .byte 0x50 - 6693 0883 9F .byte 0x9f - 6694 0884 00000000 .4byte 0 - 6695 0888 00000000 .4byte 0 - 6696 .LLST59: - 6697 088c 00000000 .4byte .LVL143 - 6698 0890 20000000 .4byte .LVL145 - 6699 0894 0100 .2byte 0x1 - 6700 0896 51 .byte 0x51 - 6701 0897 20000000 .4byte .LVL145 - 6702 089b 68000000 .4byte .LFE47 - 6703 089f 0400 .2byte 0x4 - 6704 08a1 F3 .byte 0xf3 - 6705 08a2 01 .uleb128 0x1 - 6706 08a3 51 .byte 0x51 - 6707 08a4 9F .byte 0x9f - 6708 08a5 00000000 .4byte 0 - 6709 08a9 00000000 .4byte 0 - 6710 .LLST60: - 6711 08ad 00000000 .4byte .LFB50 - 6712 08b1 02000000 .4byte .LCFI10 - 6713 08b5 0200 .2byte 0x2 - 6714 08b7 7D .byte 0x7d - 6715 08b8 00 .sleb128 0 - 6716 08b9 02000000 .4byte .LCFI10 - 6717 08bd 44000000 .4byte .LFE50 - 6718 08c1 0200 .2byte 0x2 - 6719 08c3 7D .byte 0x7d - 6720 08c4 08 .sleb128 8 - 6721 08c5 00000000 .4byte 0 - 6722 08c9 00000000 .4byte 0 - 6723 .LLST61: - 6724 08cd 00000000 .4byte .LVL148 - 6725 08d1 0A000000 .4byte .LVL150 - 6726 08d5 0100 .2byte 0x1 - 6727 08d7 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 166 - - - 6728 08d8 0A000000 .4byte .LVL150 - 6729 08dc 14000000 .4byte .LFE52 - 6730 08e0 0400 .2byte 0x4 - 6731 08e2 F3 .byte 0xf3 - 6732 08e3 01 .uleb128 0x1 - 6733 08e4 50 .byte 0x50 - 6734 08e5 9F .byte 0x9f - 6735 08e6 00000000 .4byte 0 - 6736 08ea 00000000 .4byte 0 - 6737 .LLST62: - 6738 08ee 00000000 .4byte .LFB53 - 6739 08f2 02000000 .4byte .LCFI11 - 6740 08f6 0200 .2byte 0x2 - 6741 08f8 7D .byte 0x7d - 6742 08f9 00 .sleb128 0 - 6743 08fa 02000000 .4byte .LCFI11 - 6744 08fe 18000000 .4byte .LFE53 - 6745 0902 0200 .2byte 0x2 - 6746 0904 7D .byte 0x7d - 6747 0905 08 .sleb128 8 - 6748 0906 00000000 .4byte 0 - 6749 090a 00000000 .4byte 0 - 6750 .LLST63: - 6751 090e 06000000 .4byte .LVL151 - 6752 0912 0D000000 .4byte .LVL153-1 - 6753 0916 0100 .2byte 0x1 - 6754 0918 50 .byte 0x50 - 6755 0919 00000000 .4byte 0 - 6756 091d 00000000 .4byte 0 - 6757 .LLST64: - 6758 0921 00000000 .4byte .LFB54 - 6759 0925 02000000 .4byte .LCFI12 - 6760 0929 0200 .2byte 0x2 - 6761 092b 7D .byte 0x7d - 6762 092c 00 .sleb128 0 - 6763 092d 02000000 .4byte .LCFI12 - 6764 0931 1C000000 .4byte .LFE54 - 6765 0935 0200 .2byte 0x2 - 6766 0937 7D .byte 0x7d - 6767 0938 08 .sleb128 8 - 6768 0939 00000000 .4byte 0 - 6769 093d 00000000 .4byte 0 - 6770 .LLST65: - 6771 0941 06000000 .4byte .LVL154 - 6772 0945 13000000 .4byte .LVL156-1 - 6773 0949 0100 .2byte 0x1 - 6774 094b 50 .byte 0x50 - 6775 094c 00000000 .4byte 0 - 6776 0950 00000000 .4byte 0 - 6777 .LLST66: - 6778 0954 00000000 .4byte .LFB55 - 6779 0958 02000000 .4byte .LCFI13 - 6780 095c 0200 .2byte 0x2 - 6781 095e 7D .byte 0x7d - 6782 095f 00 .sleb128 0 - 6783 0960 02000000 .4byte .LCFI13 - 6784 0964 18000000 .4byte .LFE55 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 167 - - - 6785 0968 0200 .2byte 0x2 - 6786 096a 7D .byte 0x7d - 6787 096b 08 .sleb128 8 - 6788 096c 00000000 .4byte 0 - 6789 0970 00000000 .4byte 0 - 6790 .LLST67: - 6791 0974 00000000 .4byte .LVL157 - 6792 0978 07000000 .4byte .LVL158-1 - 6793 097c 0100 .2byte 0x1 - 6794 097e 50 .byte 0x50 - 6795 097f 07000000 .4byte .LVL158-1 - 6796 0983 18000000 .4byte .LFE55 - 6797 0987 0100 .2byte 0x1 - 6798 0989 54 .byte 0x54 - 6799 098a 00000000 .4byte 0 - 6800 098e 00000000 .4byte 0 - 6801 .LLST68: - 6802 0992 08000000 .4byte .LVL158 - 6803 0996 13000000 .4byte .LVL159-1 - 6804 099a 0100 .2byte 0x1 - 6805 099c 50 .byte 0x50 - 6806 099d 00000000 .4byte 0 - 6807 09a1 00000000 .4byte 0 - 6808 .LLST69: - 6809 09a5 00000000 .4byte .LFB56 - 6810 09a9 02000000 .4byte .LCFI14 - 6811 09ad 0200 .2byte 0x2 - 6812 09af 7D .byte 0x7d - 6813 09b0 00 .sleb128 0 - 6814 09b1 02000000 .4byte .LCFI14 - 6815 09b5 60000000 .4byte .LFE56 - 6816 09b9 0200 .2byte 0x2 - 6817 09bb 7D .byte 0x7d - 6818 09bc 08 .sleb128 8 - 6819 09bd 00000000 .4byte 0 - 6820 09c1 00000000 .4byte 0 - 6821 .LLST70: - 6822 09c5 06000000 .4byte .LVL160 - 6823 09c9 59000000 .4byte .LVL161-1 - 6824 09cd 0100 .2byte 0x1 - 6825 09cf 50 .byte 0x50 - 6826 09d0 00000000 .4byte 0 - 6827 09d4 00000000 .4byte 0 - 6828 .LLST71: - 6829 09d8 00000000 .4byte .LVL162 - 6830 09dc 0C000000 .4byte .LVL165 - 6831 09e0 0100 .2byte 0x1 - 6832 09e2 50 .byte 0x50 - 6833 09e3 0C000000 .4byte .LVL165 - 6834 09e7 18000000 .4byte .LFE57 - 6835 09eb 0400 .2byte 0x4 - 6836 09ed F3 .byte 0xf3 - 6837 09ee 01 .uleb128 0x1 - 6838 09ef 50 .byte 0x50 - 6839 09f0 9F .byte 0x9f - 6840 09f1 00000000 .4byte 0 - 6841 09f5 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 168 - - - 6842 .LLST72: - 6843 09f9 00000000 .4byte .LVL162 - 6844 09fd 02000000 .4byte .LVL163 - 6845 0a01 0600 .2byte 0x6 - 6846 0a03 11 .byte 0x11 - 6847 0a04 88DA8380 .sleb128 -536810232 - 6847 7E - 6848 0a09 02000000 .4byte .LVL163 - 6849 0a0d 08000000 .4byte .LVL164 - 6850 0a11 0200 .2byte 0x2 - 6851 0a13 73 .byte 0x73 - 6852 0a14 00 .sleb128 0 - 6853 0a15 08000000 .4byte .LVL164 - 6854 0a19 18000000 .4byte .LFE57 - 6855 0a1d 0100 .2byte 0x1 - 6856 0a1f 53 .byte 0x53 - 6857 0a20 00000000 .4byte 0 - 6858 0a24 00000000 .4byte 0 - 6859 .LLST73: - 6860 0a28 00000000 .4byte .LVL166 - 6861 0a2c 06000000 .4byte .LVL168 - 6862 0a30 0100 .2byte 0x1 - 6863 0a32 50 .byte 0x50 - 6864 0a33 06000000 .4byte .LVL168 - 6865 0a37 14000000 .4byte .LFE58 - 6866 0a3b 0400 .2byte 0x4 - 6867 0a3d F3 .byte 0xf3 - 6868 0a3e 01 .uleb128 0x1 - 6869 0a3f 50 .byte 0x50 - 6870 0a40 9F .byte 0x9f - 6871 0a41 00000000 .4byte 0 - 6872 0a45 00000000 .4byte 0 - 6873 .LLST74: - 6874 0a49 00000000 .4byte .LVL166 - 6875 0a4d 02000000 .4byte .LVL167 - 6876 0a51 0600 .2byte 0x6 - 6877 0a53 11 .byte 0x11 - 6878 0a54 88DA8380 .sleb128 -536810232 - 6878 7E - 6879 0a59 02000000 .4byte .LVL167 - 6880 0a5d 14000000 .4byte .LFE58 - 6881 0a61 0200 .2byte 0x2 - 6882 0a63 73 .byte 0x73 - 6883 0a64 00 .sleb128 0 - 6884 0a65 00000000 .4byte 0 - 6885 0a69 00000000 .4byte 0 - 6886 .LLST75: - 6887 0a6d 00000000 .4byte .LVL169 - 6888 0a71 06000000 .4byte .LVL171 - 6889 0a75 0100 .2byte 0x1 - 6890 0a77 50 .byte 0x50 - 6891 0a78 06000000 .4byte .LVL171 - 6892 0a7c 1C000000 .4byte .LFE59 - 6893 0a80 0400 .2byte 0x4 - 6894 0a82 F3 .byte 0xf3 - 6895 0a83 01 .uleb128 0x1 - 6896 0a84 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 169 - - - 6897 0a85 9F .byte 0x9f - 6898 0a86 00000000 .4byte 0 - 6899 0a8a 00000000 .4byte 0 - 6900 .LLST76: - 6901 0a8e 00000000 .4byte .LVL169 - 6902 0a92 02000000 .4byte .LVL170 - 6903 0a96 0600 .2byte 0x6 - 6904 0a98 11 .byte 0x11 - 6905 0a99 88DA8380 .sleb128 -536810232 - 6905 7E - 6906 0a9e 02000000 .4byte .LVL170 - 6907 0aa2 08000000 .4byte .LVL172 - 6908 0aa6 0200 .2byte 0x2 - 6909 0aa8 73 .byte 0x73 - 6910 0aa9 00 .sleb128 0 - 6911 0aaa 08000000 .4byte .LVL172 - 6912 0aae 1C000000 .4byte .LFE59 - 6913 0ab2 0100 .2byte 0x1 - 6914 0ab4 53 .byte 0x53 - 6915 0ab5 00000000 .4byte 0 - 6916 0ab9 00000000 .4byte 0 - 6917 .LLST77: - 6918 0abd 00000000 .4byte .LVL174 - 6919 0ac1 06000000 .4byte .LVL176 - 6920 0ac5 0100 .2byte 0x1 - 6921 0ac7 50 .byte 0x50 - 6922 0ac8 06000000 .4byte .LVL176 - 6923 0acc 14000000 .4byte .LFE60 - 6924 0ad0 0400 .2byte 0x4 - 6925 0ad2 F3 .byte 0xf3 - 6926 0ad3 01 .uleb128 0x1 - 6927 0ad4 50 .byte 0x50 - 6928 0ad5 9F .byte 0x9f - 6929 0ad6 00000000 .4byte 0 - 6930 0ada 00000000 .4byte 0 - 6931 .LLST78: - 6932 0ade 00000000 .4byte .LVL174 - 6933 0ae2 02000000 .4byte .LVL175 - 6934 0ae6 0600 .2byte 0x6 - 6935 0ae8 11 .byte 0x11 - 6936 0ae9 88DA8380 .sleb128 -536810232 - 6936 7E - 6937 0aee 02000000 .4byte .LVL175 - 6938 0af2 14000000 .4byte .LFE60 - 6939 0af6 0200 .2byte 0x2 - 6940 0af8 73 .byte 0x73 - 6941 0af9 00 .sleb128 0 - 6942 0afa 00000000 .4byte 0 - 6943 0afe 00000000 .4byte 0 - 6944 .LLST79: - 6945 0b02 00000000 .4byte .LVL177 - 6946 0b06 04000000 .4byte .LVL178 - 6947 0b0a 0100 .2byte 0x1 - 6948 0b0c 50 .byte 0x50 - 6949 0b0d 04000000 .4byte .LVL178 - 6950 0b11 14000000 .4byte .LFE61 - 6951 0b15 0400 .2byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 170 - - - 6952 0b17 F3 .byte 0xf3 - 6953 0b18 01 .uleb128 0x1 - 6954 0b19 50 .byte 0x50 - 6955 0b1a 9F .byte 0x9f - 6956 0b1b 00000000 .4byte 0 - 6957 0b1f 00000000 .4byte 0 - 6958 .LLST80: - 6959 0b23 00000000 .4byte .LVL177 - 6960 0b27 0A000000 .4byte .LVL179 - 6961 0b2b 0100 .2byte 0x1 - 6962 0b2d 51 .byte 0x51 - 6963 0b2e 0A000000 .4byte .LVL179 - 6964 0b32 14000000 .4byte .LFE61 - 6965 0b36 0400 .2byte 0x4 - 6966 0b38 F3 .byte 0xf3 - 6967 0b39 01 .uleb128 0x1 - 6968 0b3a 51 .byte 0x51 - 6969 0b3b 9F .byte 0x9f - 6970 0b3c 00000000 .4byte 0 - 6971 0b40 00000000 .4byte 0 - 6972 .LLST81: - 6973 0b44 00000000 .4byte .LVL180 - 6974 0b48 04000000 .4byte .LVL181 - 6975 0b4c 0100 .2byte 0x1 - 6976 0b4e 50 .byte 0x50 - 6977 0b4f 04000000 .4byte .LVL181 - 6978 0b53 12000000 .4byte .LFE62 - 6979 0b57 0400 .2byte 0x4 - 6980 0b59 F3 .byte 0xf3 - 6981 0b5a 01 .uleb128 0x1 - 6982 0b5b 50 .byte 0x50 - 6983 0b5c 9F .byte 0x9f - 6984 0b5d 00000000 .4byte 0 - 6985 0b61 00000000 .4byte 0 - 6986 .LLST82: - 6987 0b65 00000000 .4byte .LVL183 - 6988 0b69 06000000 .4byte .LVL184 - 6989 0b6d 0100 .2byte 0x1 - 6990 0b6f 50 .byte 0x50 - 6991 0b70 06000000 .4byte .LVL184 - 6992 0b74 18000000 .4byte .LFE63 - 6993 0b78 0400 .2byte 0x4 - 6994 0b7a F3 .byte 0xf3 - 6995 0b7b 01 .uleb128 0x1 - 6996 0b7c 50 .byte 0x50 - 6997 0b7d 9F .byte 0x9f - 6998 0b7e 00000000 .4byte 0 - 6999 0b82 00000000 .4byte 0 - 7000 .section .debug_aranges,"",%progbits - 7001 0000 0C020000 .4byte 0x20c - 7002 0004 0200 .2byte 0x2 - 7003 0006 00000000 .4byte .Ldebug_info0 - 7004 000a 04 .byte 0x4 - 7005 000b 00 .byte 0 - 7006 000c 0000 .2byte 0 - 7007 000e 0000 .2byte 0 - 7008 0010 00000000 .4byte .LFB7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 171 - - - 7009 0014 B8000000 .4byte .LFE7-.LFB7 - 7010 0018 00000000 .4byte .LFB14 - 7011 001c 3C000000 .4byte .LFE14-.LFB14 - 7012 0020 00000000 .4byte .LFB1 - 7013 0024 10000000 .4byte .LFE1-.LFB1 - 7014 0028 00000000 .4byte .LFB2 - 7015 002c 34000000 .4byte .LFE2-.LFB2 - 7016 0030 00000000 .4byte .LFB3 - 7017 0034 14000000 .4byte .LFE3-.LFB3 - 7018 0038 00000000 .4byte .LFB5 - 7019 003c 18000000 .4byte .LFE5-.LFB5 - 7020 0040 00000000 .4byte .LFB9 - 7021 0044 40000000 .4byte .LFE9-.LFB9 - 7022 0048 00000000 .4byte .LFB10 - 7023 004c 10000000 .4byte .LFE10-.LFB10 - 7024 0050 00000000 .4byte .LFB11 - 7025 0054 10000000 .4byte .LFE11-.LFB11 - 7026 0058 00000000 .4byte .LFB8 - 7027 005c D8000000 .4byte .LFE8-.LFB8 - 7028 0060 00000000 .4byte .LFB12 - 7029 0064 18000000 .4byte .LFE12-.LFB12 - 7030 0068 00000000 .4byte .LFB13 - 7031 006c 0C000000 .4byte .LFE13-.LFB13 - 7032 0070 00000000 .4byte .LFB15 - 7033 0074 6C000000 .4byte .LFE15-.LFB15 - 7034 0078 00000000 .4byte .LFB16 - 7035 007c 18000000 .4byte .LFE16-.LFB16 - 7036 0080 00000000 .4byte .LFB17 - 7037 0084 10000000 .4byte .LFE17-.LFB17 - 7038 0088 00000000 .4byte .LFB18 - 7039 008c 10000000 .4byte .LFE18-.LFB18 - 7040 0090 00000000 .4byte .LFB19 - 7041 0094 10000000 .4byte .LFE19-.LFB19 - 7042 0098 00000000 .4byte .LFB20 - 7043 009c 10000000 .4byte .LFE20-.LFB20 - 7044 00a0 00000000 .4byte .LFB4 - 7045 00a4 50000000 .4byte .LFE4-.LFB4 - 7046 00a8 00000000 .4byte .LFB0 - 7047 00ac 68000000 .4byte .LFE0-.LFB0 - 7048 00b0 00000000 .4byte .LFB21 - 7049 00b4 10000000 .4byte .LFE21-.LFB21 - 7050 00b8 00000000 .4byte .LFB22 - 7051 00bc 10000000 .4byte .LFE22-.LFB22 - 7052 00c0 00000000 .4byte .LFB23 - 7053 00c4 18000000 .4byte .LFE23-.LFB23 - 7054 00c8 00000000 .4byte .LFB24 - 7055 00cc 1C000000 .4byte .LFE24-.LFB24 - 7056 00d0 00000000 .4byte .LFB26 - 7057 00d4 34000000 .4byte .LFE26-.LFB26 - 7058 00d8 00000000 .4byte .LFB27 - 7059 00dc 10000000 .4byte .LFE27-.LFB27 - 7060 00e0 00000000 .4byte .LFB29 - 7061 00e4 88000000 .4byte .LFE29-.LFB29 - 7062 00e8 00000000 .4byte .LFB30 - 7063 00ec 10000000 .4byte .LFE30-.LFB30 - 7064 00f0 00000000 .4byte .LFB31 - 7065 00f4 10000000 .4byte .LFE31-.LFB31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 172 - - - 7066 00f8 00000000 .4byte .LFB32 - 7067 00fc 10000000 .4byte .LFE32-.LFB32 - 7068 0100 00000000 .4byte .LFB33 - 7069 0104 0C000000 .4byte .LFE33-.LFB33 - 7070 0108 00000000 .4byte .LFB34 - 7071 010c 10000000 .4byte .LFE34-.LFB34 - 7072 0110 00000000 .4byte .LFB35 - 7073 0114 10000000 .4byte .LFE35-.LFB35 - 7074 0118 00000000 .4byte .LFB36 - 7075 011c 18000000 .4byte .LFE36-.LFB36 - 7076 0120 00000000 .4byte .LFB37 - 7077 0124 18000000 .4byte .LFE37-.LFB37 - 7078 0128 00000000 .4byte .LFB38 - 7079 012c 1C000000 .4byte .LFE38-.LFB38 - 7080 0130 00000000 .4byte .LFB39 - 7081 0134 04000000 .4byte .LFE39-.LFB39 - 7082 0138 00000000 .4byte .LFB40 - 7083 013c 10000000 .4byte .LFE40-.LFB40 - 7084 0140 00000000 .4byte .LFB41 - 7085 0144 28000000 .4byte .LFE41-.LFB41 - 7086 0148 00000000 .4byte .LFB42 - 7087 014c 10000000 .4byte .LFE42-.LFB42 - 7088 0150 00000000 .4byte .LFB28 - 7089 0154 6C000000 .4byte .LFE28-.LFB28 - 7090 0158 00000000 .4byte .LFB25 - 7091 015c 70000000 .4byte .LFE25-.LFB25 - 7092 0160 00000000 .4byte .LFB43 - 7093 0164 40000000 .4byte .LFE43-.LFB43 - 7094 0168 00000000 .4byte .LFB44 - 7095 016c 40000000 .4byte .LFE44-.LFB44 - 7096 0170 00000000 .4byte .LFB45 - 7097 0174 0C000000 .4byte .LFE45-.LFB45 - 7098 0178 00000000 .4byte .LFB46 - 7099 017c 68000000 .4byte .LFE46-.LFB46 - 7100 0180 00000000 .4byte .LFB47 - 7101 0184 68000000 .4byte .LFE47-.LFB47 - 7102 0188 00000000 .4byte .LFB48 - 7103 018c 24000000 .4byte .LFE48-.LFB48 - 7104 0190 00000000 .4byte .LFB49 - 7105 0194 24000000 .4byte .LFE49-.LFB49 - 7106 0198 00000000 .4byte .LFB50 - 7107 019c 44000000 .4byte .LFE50-.LFB50 - 7108 01a0 00000000 .4byte .LFB51 - 7109 01a4 10000000 .4byte .LFE51-.LFB51 - 7110 01a8 00000000 .4byte .LFB52 - 7111 01ac 14000000 .4byte .LFE52-.LFB52 - 7112 01b0 00000000 .4byte .LFB53 - 7113 01b4 18000000 .4byte .LFE53-.LFB53 - 7114 01b8 00000000 .4byte .LFB54 - 7115 01bc 1C000000 .4byte .LFE54-.LFB54 - 7116 01c0 00000000 .4byte .LFB55 - 7117 01c4 18000000 .4byte .LFE55-.LFB55 - 7118 01c8 00000000 .4byte .LFB56 - 7119 01cc 60000000 .4byte .LFE56-.LFB56 - 7120 01d0 00000000 .4byte .LFB57 - 7121 01d4 18000000 .4byte .LFE57-.LFB57 - 7122 01d8 00000000 .4byte .LFB58 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 173 - - - 7123 01dc 14000000 .4byte .LFE58-.LFB58 - 7124 01e0 00000000 .4byte .LFB59 - 7125 01e4 1C000000 .4byte .LFE59-.LFB59 - 7126 01e8 00000000 .4byte .LFB60 - 7127 01ec 14000000 .4byte .LFE60-.LFB60 - 7128 01f0 00000000 .4byte .LFB61 - 7129 01f4 14000000 .4byte .LFE61-.LFB61 - 7130 01f8 00000000 .4byte .LFB62 - 7131 01fc 12000000 .4byte .LFE62-.LFB62 - 7132 0200 00000000 .4byte .LFB63 - 7133 0204 18000000 .4byte .LFE63-.LFB63 - 7134 0208 00000000 .4byte 0 - 7135 020c 00000000 .4byte 0 - 7136 .section .debug_ranges,"",%progbits - 7137 .Ldebug_ranges0: - 7138 0000 00000000 .4byte .LFB7 - 7139 0004 B8000000 .4byte .LFE7 - 7140 0008 00000000 .4byte .LFB14 - 7141 000c 3C000000 .4byte .LFE14 - 7142 0010 00000000 .4byte .LFB1 - 7143 0014 10000000 .4byte .LFE1 - 7144 0018 00000000 .4byte .LFB2 - 7145 001c 34000000 .4byte .LFE2 - 7146 0020 00000000 .4byte .LFB3 - 7147 0024 14000000 .4byte .LFE3 - 7148 0028 00000000 .4byte .LFB5 - 7149 002c 18000000 .4byte .LFE5 - 7150 0030 00000000 .4byte .LFB9 - 7151 0034 40000000 .4byte .LFE9 - 7152 0038 00000000 .4byte .LFB10 - 7153 003c 10000000 .4byte .LFE10 - 7154 0040 00000000 .4byte .LFB11 - 7155 0044 10000000 .4byte .LFE11 - 7156 0048 00000000 .4byte .LFB8 - 7157 004c D8000000 .4byte .LFE8 - 7158 0050 00000000 .4byte .LFB12 - 7159 0054 18000000 .4byte .LFE12 - 7160 0058 00000000 .4byte .LFB13 - 7161 005c 0C000000 .4byte .LFE13 - 7162 0060 00000000 .4byte .LFB15 - 7163 0064 6C000000 .4byte .LFE15 - 7164 0068 00000000 .4byte .LFB16 - 7165 006c 18000000 .4byte .LFE16 - 7166 0070 00000000 .4byte .LFB17 - 7167 0074 10000000 .4byte .LFE17 - 7168 0078 00000000 .4byte .LFB18 - 7169 007c 10000000 .4byte .LFE18 - 7170 0080 00000000 .4byte .LFB19 - 7171 0084 10000000 .4byte .LFE19 - 7172 0088 00000000 .4byte .LFB20 - 7173 008c 10000000 .4byte .LFE20 - 7174 0090 00000000 .4byte .LFB4 - 7175 0094 50000000 .4byte .LFE4 - 7176 0098 00000000 .4byte .LFB0 - 7177 009c 68000000 .4byte .LFE0 - 7178 00a0 00000000 .4byte .LFB21 - 7179 00a4 10000000 .4byte .LFE21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 174 - - - 7180 00a8 00000000 .4byte .LFB22 - 7181 00ac 10000000 .4byte .LFE22 - 7182 00b0 00000000 .4byte .LFB23 - 7183 00b4 18000000 .4byte .LFE23 - 7184 00b8 00000000 .4byte .LFB24 - 7185 00bc 1C000000 .4byte .LFE24 - 7186 00c0 00000000 .4byte .LFB26 - 7187 00c4 34000000 .4byte .LFE26 - 7188 00c8 00000000 .4byte .LFB27 - 7189 00cc 10000000 .4byte .LFE27 - 7190 00d0 00000000 .4byte .LFB29 - 7191 00d4 88000000 .4byte .LFE29 - 7192 00d8 00000000 .4byte .LFB30 - 7193 00dc 10000000 .4byte .LFE30 - 7194 00e0 00000000 .4byte .LFB31 - 7195 00e4 10000000 .4byte .LFE31 - 7196 00e8 00000000 .4byte .LFB32 - 7197 00ec 10000000 .4byte .LFE32 - 7198 00f0 00000000 .4byte .LFB33 - 7199 00f4 0C000000 .4byte .LFE33 - 7200 00f8 00000000 .4byte .LFB34 - 7201 00fc 10000000 .4byte .LFE34 - 7202 0100 00000000 .4byte .LFB35 - 7203 0104 10000000 .4byte .LFE35 - 7204 0108 00000000 .4byte .LFB36 - 7205 010c 18000000 .4byte .LFE36 - 7206 0110 00000000 .4byte .LFB37 - 7207 0114 18000000 .4byte .LFE37 - 7208 0118 00000000 .4byte .LFB38 - 7209 011c 1C000000 .4byte .LFE38 - 7210 0120 00000000 .4byte .LFB39 - 7211 0124 04000000 .4byte .LFE39 - 7212 0128 00000000 .4byte .LFB40 - 7213 012c 10000000 .4byte .LFE40 - 7214 0130 00000000 .4byte .LFB41 - 7215 0134 28000000 .4byte .LFE41 - 7216 0138 00000000 .4byte .LFB42 - 7217 013c 10000000 .4byte .LFE42 - 7218 0140 00000000 .4byte .LFB28 - 7219 0144 6C000000 .4byte .LFE28 - 7220 0148 00000000 .4byte .LFB25 - 7221 014c 70000000 .4byte .LFE25 - 7222 0150 00000000 .4byte .LFB43 - 7223 0154 40000000 .4byte .LFE43 - 7224 0158 00000000 .4byte .LFB44 - 7225 015c 40000000 .4byte .LFE44 - 7226 0160 00000000 .4byte .LFB45 - 7227 0164 0C000000 .4byte .LFE45 - 7228 0168 00000000 .4byte .LFB46 - 7229 016c 68000000 .4byte .LFE46 - 7230 0170 00000000 .4byte .LFB47 - 7231 0174 68000000 .4byte .LFE47 - 7232 0178 00000000 .4byte .LFB48 - 7233 017c 24000000 .4byte .LFE48 - 7234 0180 00000000 .4byte .LFB49 - 7235 0184 24000000 .4byte .LFE49 - 7236 0188 00000000 .4byte .LFB50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 175 - - - 7237 018c 44000000 .4byte .LFE50 - 7238 0190 00000000 .4byte .LFB51 - 7239 0194 10000000 .4byte .LFE51 - 7240 0198 00000000 .4byte .LFB52 - 7241 019c 14000000 .4byte .LFE52 - 7242 01a0 00000000 .4byte .LFB53 - 7243 01a4 18000000 .4byte .LFE53 - 7244 01a8 00000000 .4byte .LFB54 - 7245 01ac 1C000000 .4byte .LFE54 - 7246 01b0 00000000 .4byte .LFB55 - 7247 01b4 18000000 .4byte .LFE55 - 7248 01b8 00000000 .4byte .LFB56 - 7249 01bc 60000000 .4byte .LFE56 - 7250 01c0 00000000 .4byte .LFB57 - 7251 01c4 18000000 .4byte .LFE57 - 7252 01c8 00000000 .4byte .LFB58 - 7253 01cc 14000000 .4byte .LFE58 - 7254 01d0 00000000 .4byte .LFB59 - 7255 01d4 1C000000 .4byte .LFE59 - 7256 01d8 00000000 .4byte .LFB60 - 7257 01dc 14000000 .4byte .LFE60 - 7258 01e0 00000000 .4byte .LFB61 - 7259 01e4 14000000 .4byte .LFE61 - 7260 01e8 00000000 .4byte .LFB62 - 7261 01ec 12000000 .4byte .LFE62 - 7262 01f0 00000000 .4byte .LFB63 - 7263 01f4 18000000 .4byte .LFE63 - 7264 01f8 00000000 .4byte 0 - 7265 01fc 00000000 .4byte 0 - 7266 .section .debug_line,"",%progbits - 7267 .Ldebug_line0: - 7268 0000 64060000 .section .debug_str,"MS",%progbits,1 - 7268 02005900 - 7268 00000201 - 7268 FB0E0D00 - 7268 01010101 - 7269 .LASF115: - 7270 0000 72616D56 .ascii "ramVectorTable\000" - 7270 6563746F - 7270 72546162 - 7270 6C6500 - 7271 .LASF69: - 7272 000f 636F756E .ascii "count\000" - 7272 7400 - 7273 .LASF12: - 7274 0015 75696E74 .ascii "uint16\000" - 7274 313600 - 7275 .LASF108: - 7276 001c 696E7453 .ascii "intState\000" - 7276 74617465 - 7276 00 - 7277 .LASF54: - 7278 0025 696C6F31 .ascii "ilo100KhzEnable\000" - 7278 30304B68 - 7278 7A456E61 - 7278 626C6500 - 7279 .LASF74: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 176 - - - 7280 0035 43795854 .ascii "CyXTAL_DisableErrStatus\000" - 7280 414C5F44 - 7280 69736162 - 7280 6C654572 - 7280 72537461 - 7281 .LASF50: - 7282 004d 4379494D .ascii "CyIMO_Start\000" - 7282 4F5F5374 - 7282 61727400 - 7283 .LASF49: - 7284 0059 4379494C .ascii "CyILO_Stop100K\000" - 7284 4F5F5374 - 7284 6F703130 - 7284 304B00 - 7285 .LASF114: - 7286 0068 6F6C6449 .ascii "oldIsr\000" - 7286 737200 - 7287 .LASF34: - 7288 006f 4379494D .ascii "CyIMO_EnableDoubler\000" - 7288 4F5F456E - 7288 61626C65 - 7288 446F7562 - 7288 6C657200 - 7289 .LASF107: - 7290 0083 43794469 .ascii "CyDisableInts\000" - 7290 7361626C - 7290 65496E74 - 7290 7300 - 7291 .LASF89: - 7292 0091 43795854 .ascii "CyXTAL_32KHZ_Start\000" - 7292 414C5F33 - 7292 324B485A - 7292 5F537461 - 7292 727400 - 7293 .LASF6: - 7294 00a4 6C6F6E67 .ascii "long long unsigned int\000" - 7294 206C6F6E - 7294 6720756E - 7294 7369676E - 7294 65642069 - 7295 .LASF57: - 7296 00bb 706D5477 .ascii "pmTwCfg0State\000" - 7296 43666730 - 7296 53746174 - 7296 6500 - 7297 .LASF83: - 7298 00c9 4379536F .ascii "CySoftwareReset\000" - 7298 66747761 - 7298 72655265 - 7298 73657400 - 7299 .LASF21: - 7300 00d9 4379494D .ascii "CyIMO_SetTrimValue\000" - 7300 4F5F5365 - 7300 74547269 - 7300 6D56616C - 7300 756500 - 7301 .LASF127: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 177 - - - 7302 00ec 63796465 .ascii "cydelay_freq_mhz\000" - 7302 6C61795F - 7302 66726571 - 7302 5F6D687A - 7302 00 - 7303 .LASF122: - 7304 00fd 4379496E .ascii "CyIntGetState\000" - 7304 74476574 - 7304 53746174 - 7304 6500 - 7305 .LASF70: - 7306 010b 706D5477 .ascii "pmTwCfg0Tmp\000" - 7306 43666730 - 7306 546D7000 - 7307 .LASF5: - 7308 0117 6C6F6E67 .ascii "long long int\000" - 7308 206C6F6E - 7308 6720696E - 7308 7400 - 7309 .LASF0: - 7310 0125 7369676E .ascii "signed char\000" - 7310 65642063 - 7310 68617200 - 7311 .LASF23: - 7312 0131 66726571 .ascii "freq\000" - 7312 00 - 7313 .LASF90: - 7314 0136 43794465 .ascii "CyDelayFreq\000" - 7314 6C617946 - 7314 72657100 - 7315 .LASF44: - 7316 0142 696E7465 .ascii "interruptState\000" - 7316 72727570 - 7316 74537461 - 7316 746500 - 7317 .LASF46: - 7318 0151 4379494C .ascii "CyILO_Start1K\000" - 7318 4F5F5374 - 7318 61727431 - 7318 4B00 - 7319 .LASF51: - 7320 015f 77616974 .ascii "wait\000" - 7320 00 - 7321 .LASF65: - 7322 0164 73746174 .ascii "state\000" - 7322 6500 - 7323 .LASF7: - 7324 016a 6C6F6E67 .ascii "long int\000" - 7324 20696E74 - 7324 00 - 7325 .LASF29: - 7326 0173 4379504C .ascii "CyPLL_OUT_SetSource\000" - 7326 4C5F4F55 - 7326 545F5365 - 7326 74536F75 - 7326 72636500 - 7327 .LASF18: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 178 - - - 7328 0187 72656731 .ascii "reg16\000" - 7328 3600 - 7329 .LASF11: - 7330 018d 75696E74 .ascii "uint8\000" - 7330 3800 - 7331 .LASF62: - 7332 0193 4379504C .ascii "CyPLL_OUT_Start\000" - 7332 4C5F4F55 - 7332 545F5374 - 7332 61727400 - 7333 .LASF86: - 7334 01a3 43794465 .ascii "CyDelayUs\000" - 7334 6C617955 - 7334 7300 - 7335 .LASF15: - 7336 01ad 646F7562 .ascii "double\000" - 7336 6C6500 - 7337 .LASF28: - 7338 01b4 4379504C .ascii "CyPLL_OUT_SetPQ\000" - 7338 4C5F4F55 - 7338 545F5365 - 7338 74505100 - 7339 .LASF47: - 7340 01c4 4379494C .ascii "CyILO_Stop1K\000" - 7340 4F5F5374 - 7340 6F70314B - 7340 00 - 7341 .LASF94: - 7342 01d1 43795764 .ascii "CyWdtClear\000" - 7342 74436C65 - 7342 617200 - 7343 .LASF13: - 7344 01dc 75696E74 .ascii "uint32\000" - 7344 333200 - 7345 .LASF141: - 7346 01e3 43794465 .ascii "CyDelayCycles\000" - 7346 6C617943 - 7346 79636C65 - 7346 7300 - 7347 .LASF104: - 7348 01f1 6D61736B .ascii "mask\000" - 7348 00 - 7349 .LASF96: - 7350 01f6 72657365 .ascii "reset\000" - 7350 7400 - 7351 .LASF121: - 7352 01fc 4379496E .ascii "CyIntGetPriority\000" - 7352 74476574 - 7352 5072696F - 7352 72697479 - 7352 00 - 7353 .LASF116: - 7354 020d 4379496E .ascii "CyIntGetSysVector\000" - 7354 74476574 - 7354 53797356 - 7354 6563746F - 7354 7200 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccqtVW5G.s page 179 - - - 7355 .LASF4: - 7356 021f 756E7369 .ascii "unsigned int\000" - 7356 676E6564 - 7356 20696E74 - 7356 00 - 7357 .LASF33: - 7358 022c 4379494D .ascii "CyIMO_SetSource\000" - 7358 4F5F5365 - 7358 74536F75 - 7358 72636500 - 7359 .LASF43: - 7360 023c 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100755 index 0e416d9..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.lst +++ /dev/null @@ -1,3235 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "CySpc.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.CySpcStart,"ax",%progbits - 19 .align 1 - 20 .global CySpcStart - 21 .thumb - 22 .thumb_func - 23 .type CySpcStart, %function - 24 CySpcStart: - 25 .LFB0: - 26 .file 1 ".\\Generated_Source\\PSoC5\\CySpc.c" - 1:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/CySpc.c **** * File Name: CySpc.c - 3:.\Generated_Source\PSoC5/CySpc.c **** * Version 4.0 - 4:.\Generated_Source\PSoC5/CySpc.c **** * - 5:.\Generated_Source\PSoC5/CySpc.c **** * Description: - 6:.\Generated_Source\PSoC5/CySpc.c **** * Provides an API for the System Performance Component. - 7:.\Generated_Source\PSoC5/CySpc.c **** * The SPC functions are not meant to be called directly by the user - 8:.\Generated_Source\PSoC5/CySpc.c **** * application. - 9:.\Generated_Source\PSoC5/CySpc.c **** * - 10:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/CySpc.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/CySpc.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/CySpc.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/CySpc.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/CySpc.c **** - 17:.\Generated_Source\PSoC5/CySpc.c **** #include "CySpc.h" - 18:.\Generated_Source\PSoC5/CySpc.c **** - 19:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_KEY_ONE (0xB6u) - 20:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) - 21:.\Generated_Source\PSoC5/CySpc.c **** - 22:.\Generated_Source\PSoC5/CySpc.c **** /* Command Codes */ - 23:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_LD_BYTE (0x00u) - 24:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) - 25:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_LD_ROW (0x02u) - 26:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_RD_BYTE (0x03u) - 27:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) - 28:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_WR_ROW (0x05u) - 29:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_WR_USER_NVL (0x06u) - 30:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_PRG_ROW (0x07u) - 31:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_ER_SECTOR (0x08u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 2 - - - 32:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_ER_ALL (0x09u) - 33:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_RD_HIDDEN (0x0Au) - 34:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_PRG_PROTECT (0x0Bu) - 35:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_CHECKSUM (0x0Cu) - 36:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) - 37:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_GET_TEMP (0x0Eu) - 38:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_GET_ADC (0x0Fu) - 39:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) - 40:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_SETUP_TS (0x11u) - 41:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_DISABLE_TS (0x12u) - 42:.\Generated_Source\PSoC5/CySpc.c **** #define CY_SPC_CMD_ER_ROW (0x13u) - 43:.\Generated_Source\PSoC5/CySpc.c **** - 44:.\Generated_Source\PSoC5/CySpc.c **** /* Enable bit in Active and Alternate Active mode templates */ - 45:.\Generated_Source\PSoC5/CySpc.c **** #define PM_SPC_PM_EN (0x08u) - 46:.\Generated_Source\PSoC5/CySpc.c **** - 47:.\Generated_Source\PSoC5/CySpc.c **** /* Gate calls to the SPC. */ - 48:.\Generated_Source\PSoC5/CySpc.c **** uint8 SpcLockState = CY_SPC_UNLOCKED; - 49:.\Generated_Source\PSoC5/CySpc.c **** - 50:.\Generated_Source\PSoC5/CySpc.c **** - 51:.\Generated_Source\PSoC5/CySpc.c **** #if(CY_PSOC5) - 52:.\Generated_Source\PSoC5/CySpc.c **** - 53:.\Generated_Source\PSoC5/CySpc.c **** /*************************************************************************** - 54:.\Generated_Source\PSoC5/CySpc.c **** * The wait-state pipeline must be enabled prior to accessing the SPC - 55:.\Generated_Source\PSoC5/CySpc.c **** * register interface regardless of CPU frequency. The CySpcLock() saves - 56:.\Generated_Source\PSoC5/CySpc.c **** * current wait-state pipeline state and enables it. The CySpcUnlock() - 57:.\Generated_Source\PSoC5/CySpc.c **** * function, which must be called after SPC transaction, restores original - 58:.\Generated_Source\PSoC5/CySpc.c **** * state. - 59:.\Generated_Source\PSoC5/CySpc.c **** ***************************************************************************/ - 60:.\Generated_Source\PSoC5/CySpc.c **** static uint32 spcWaitPipeBypass = 0u; - 61:.\Generated_Source\PSoC5/CySpc.c **** - 62:.\Generated_Source\PSoC5/CySpc.c **** #endif /* (CY_PSOC5) */ - 63:.\Generated_Source\PSoC5/CySpc.c **** - 64:.\Generated_Source\PSoC5/CySpc.c **** - 65:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 66:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcStart - 67:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 68:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 69:.\Generated_Source\PSoC5/CySpc.c **** * Starts the SPC. - 70:.\Generated_Source\PSoC5/CySpc.c **** * - 71:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 72:.\Generated_Source\PSoC5/CySpc.c **** * None - 73:.\Generated_Source\PSoC5/CySpc.c **** * - 74:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 75:.\Generated_Source\PSoC5/CySpc.c **** * None - 76:.\Generated_Source\PSoC5/CySpc.c **** * - 77:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 78:.\Generated_Source\PSoC5/CySpc.c **** void CySpcStart(void) - 79:.\Generated_Source\PSoC5/CySpc.c **** { - 27 .loc 1 79 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 0000 08B5 push {r3, lr} - 32 .LCFI0: - 33 .cfi_def_cfa_offset 8 - 34 .cfi_offset 3, -8 - 35 .cfi_offset 14, -4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 3 - - - 80:.\Generated_Source\PSoC5/CySpc.c **** /* Save current global interrupt enable and disable it */ - 81:.\Generated_Source\PSoC5/CySpc.c **** uint8 interruptState = CyEnterCriticalSection(); - 36 .loc 1 81 0 - 37 0002 FFF7FEFF bl CyEnterCriticalSection - 38 .LVL0: - 82:.\Generated_Source\PSoC5/CySpc.c **** - 83:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; - 39 .loc 1 83 0 - 40 0006 064B ldr r3, .L2 - 41 0008 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 42 000a 42F00801 orr r1, r2, #8 - 43 000e 1970 strb r1, [r3, #0] - 84:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; - 44 .loc 1 84 0 - 45 0010 1A7C ldrb r2, [r3, #16] @ zero_extendqisi2 - 46 0012 42F00801 orr r1, r2, #8 - 47 0016 1974 strb r1, [r3, #16] - 85:.\Generated_Source\PSoC5/CySpc.c **** - 86:.\Generated_Source\PSoC5/CySpc.c **** /* Restore global interrupt enable state */ - 87:.\Generated_Source\PSoC5/CySpc.c **** CyExitCriticalSection(interruptState); - 88:.\Generated_Source\PSoC5/CySpc.c **** } - 48 .loc 1 88 0 - 49 0018 BDE80840 pop {r3, lr} - 87:.\Generated_Source\PSoC5/CySpc.c **** CyExitCriticalSection(interruptState); - 50 .loc 1 87 0 - 51 001c FFF7FEBF b CyExitCriticalSection - 52 .LVL1: - 53 .L3: - 54 .align 2 - 55 .L2: - 56 0020 A0430040 .word 1073759136 - 57 .cfi_endproc - 58 .LFE0: - 59 .size CySpcStart, .-CySpcStart - 60 .section .text.CySpcStop,"ax",%progbits - 61 .align 1 - 62 .global CySpcStop - 63 .thumb - 64 .thumb_func - 65 .type CySpcStop, %function - 66 CySpcStop: - 67 .LFB1: - 89:.\Generated_Source\PSoC5/CySpc.c **** - 90:.\Generated_Source\PSoC5/CySpc.c **** - 91:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 92:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcStop - 93:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 94:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 95:.\Generated_Source\PSoC5/CySpc.c **** * Stops the SPC. - 96:.\Generated_Source\PSoC5/CySpc.c **** * - 97:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 98:.\Generated_Source\PSoC5/CySpc.c **** * None - 99:.\Generated_Source\PSoC5/CySpc.c **** * - 100:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 101:.\Generated_Source\PSoC5/CySpc.c **** * None - 102:.\Generated_Source\PSoC5/CySpc.c **** * - 103:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 4 - - - 104:.\Generated_Source\PSoC5/CySpc.c **** void CySpcStop(void) - 105:.\Generated_Source\PSoC5/CySpc.c **** { - 68 .loc 1 105 0 - 69 .cfi_startproc - 70 @ args = 0, pretend = 0, frame = 0 - 71 @ frame_needed = 0, uses_anonymous_args = 0 - 72 0000 08B5 push {r3, lr} - 73 .LCFI1: - 74 .cfi_def_cfa_offset 8 - 75 .cfi_offset 3, -8 - 76 .cfi_offset 14, -4 - 106:.\Generated_Source\PSoC5/CySpc.c **** /* Save current global interrupt enable and disable it */ - 107:.\Generated_Source\PSoC5/CySpc.c **** uint8 interruptState = CyEnterCriticalSection(); - 77 .loc 1 107 0 - 78 0002 FFF7FEFF bl CyEnterCriticalSection - 79 .LVL2: - 108:.\Generated_Source\PSoC5/CySpc.c **** - 109:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); - 80 .loc 1 109 0 - 81 0006 064B ldr r3, .L5 - 82 0008 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 83 000a 02F0F701 and r1, r2, #247 - 84 000e 1970 strb r1, [r3, #0] - 110:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); - 85 .loc 1 110 0 - 86 0010 1A7C ldrb r2, [r3, #16] @ zero_extendqisi2 - 87 0012 02F0F701 and r1, r2, #247 - 88 0016 1974 strb r1, [r3, #16] - 111:.\Generated_Source\PSoC5/CySpc.c **** - 112:.\Generated_Source\PSoC5/CySpc.c **** /* Restore global interrupt enable state */ - 113:.\Generated_Source\PSoC5/CySpc.c **** CyExitCriticalSection(interruptState); - 114:.\Generated_Source\PSoC5/CySpc.c **** } - 89 .loc 1 114 0 - 90 0018 BDE80840 pop {r3, lr} - 113:.\Generated_Source\PSoC5/CySpc.c **** CyExitCriticalSection(interruptState); - 91 .loc 1 113 0 - 92 001c FFF7FEBF b CyExitCriticalSection - 93 .LVL3: - 94 .L6: - 95 .align 2 - 96 .L5: - 97 0020 A0430040 .word 1073759136 - 98 .cfi_endproc - 99 .LFE1: - 100 .size CySpcStop, .-CySpcStop - 101 .section .text.CySpcReadData,"ax",%progbits - 102 .align 1 - 103 .global CySpcReadData - 104 .thumb - 105 .thumb_func - 106 .type CySpcReadData, %function - 107 CySpcReadData: - 108 .LFB2: - 115:.\Generated_Source\PSoC5/CySpc.c **** - 116:.\Generated_Source\PSoC5/CySpc.c **** - 117:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 118:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcReadData - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 5 - - - 119:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 120:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 121:.\Generated_Source\PSoC5/CySpc.c **** * Reads data from the SPC. - 122:.\Generated_Source\PSoC5/CySpc.c **** * - 123:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 124:.\Generated_Source\PSoC5/CySpc.c **** * uint8 buffer: - 125:.\Generated_Source\PSoC5/CySpc.c **** * Address to store data read. - 126:.\Generated_Source\PSoC5/CySpc.c **** * - 127:.\Generated_Source\PSoC5/CySpc.c **** * uint8 size: - 128:.\Generated_Source\PSoC5/CySpc.c **** * Number of bytes to read from the SPC. - 129:.\Generated_Source\PSoC5/CySpc.c **** * - 130:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 131:.\Generated_Source\PSoC5/CySpc.c **** * uint8: - 132:.\Generated_Source\PSoC5/CySpc.c **** * The number of bytes read from the SPC. - 133:.\Generated_Source\PSoC5/CySpc.c **** * - 134:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 135:.\Generated_Source\PSoC5/CySpc.c **** uint8 CySpcReadData(uint8 buffer[], uint8 size) - 136:.\Generated_Source\PSoC5/CySpc.c **** { - 109 .loc 1 136 0 - 110 .cfi_startproc - 111 @ args = 0, pretend = 0, frame = 0 - 112 @ frame_needed = 0, uses_anonymous_args = 0 - 113 .LVL4: - 114 0000 70B5 push {r4, r5, r6, lr} - 115 .LCFI2: - 116 .cfi_def_cfa_offset 16 - 117 .cfi_offset 4, -16 - 118 .cfi_offset 5, -12 - 119 .cfi_offset 6, -8 - 120 .cfi_offset 14, -4 - 121 .loc 1 136 0 - 122 0002 0646 mov r6, r0 - 123 0004 0D46 mov r5, r1 - 137:.\Generated_Source\PSoC5/CySpc.c **** uint8 i; - 138:.\Generated_Source\PSoC5/CySpc.c **** - 139:.\Generated_Source\PSoC5/CySpc.c **** for(i = 0u; i < size; i++) - 124 .loc 1 139 0 - 125 0006 0024 movs r4, #0 - 126 .LVL5: - 127 .L8: - 128 .loc 1 139 0 is_stmt 0 discriminator 1 - 129 0008 E3B2 uxtb r3, r4 - 130 000a AB42 cmp r3, r5 - 131 000c 0CD2 bcs .L13 - 132 .L11: - 140:.\Generated_Source\PSoC5/CySpc.c **** { - 141:.\Generated_Source\PSoC5/CySpc.c **** while(!CY_SPC_DATA_READY) - 133 .loc 1 141 0 is_stmt 1 discriminator 1 - 134 000e 0748 ldr r0, .L15 - 135 0010 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 136 0012 CB07 lsls r3, r1, #31 - 137 0014 03D4 bmi .L14 - 138 .L9: - 142:.\Generated_Source\PSoC5/CySpc.c **** { - 143:.\Generated_Source\PSoC5/CySpc.c **** CyDelayUs(1u); - 139 .loc 1 143 0 - 140 0016 0120 movs r0, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 6 - - - 141 0018 FFF7FEFF bl CyDelayUs - 142 .LVL6: - 143 001c F7E7 b .L11 - 144 .L14: - 144:.\Generated_Source\PSoC5/CySpc.c **** } - 145:.\Generated_Source\PSoC5/CySpc.c **** buffer[i] = CY_SPC_CPU_DATA_REG; - 145 .loc 1 145 0 - 146 001e 044A ldr r2, .L15+4 - 147 0020 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 148 0022 3355 strb r3, [r6, r4] - 149 0024 0134 adds r4, r4, #1 - 150 0026 EFE7 b .L8 - 151 .L13: - 146:.\Generated_Source\PSoC5/CySpc.c **** } - 147:.\Generated_Source\PSoC5/CySpc.c **** - 148:.\Generated_Source\PSoC5/CySpc.c **** return(i); - 149:.\Generated_Source\PSoC5/CySpc.c **** } - 152 .loc 1 149 0 - 153 0028 2846 mov r0, r5 - 154 002a 70BD pop {r4, r5, r6, pc} - 155 .L16: - 156 .align 2 - 157 .L15: - 158 002c 22470040 .word 1073760034 - 159 0030 20470040 .word 1073760032 - 160 .cfi_endproc - 161 .LFE2: - 162 .size CySpcReadData, .-CySpcReadData - 163 .section .text.CySpcLoadMultiByte,"ax",%progbits - 164 .align 1 - 165 .global CySpcLoadMultiByte - 166 .thumb - 167 .thumb_func - 168 .type CySpcLoadMultiByte, %function - 169 CySpcLoadMultiByte: - 170 .LFB3: - 150:.\Generated_Source\PSoC5/CySpc.c **** - 151:.\Generated_Source\PSoC5/CySpc.c **** - 152:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 153:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcLoadMultiByte - 154:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 155:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 156:.\Generated_Source\PSoC5/CySpc.c **** * Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. - 157:.\Generated_Source\PSoC5/CySpc.c **** * - 158:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 159:.\Generated_Source\PSoC5/CySpc.c **** * uint8 array: - 160:.\Generated_Source\PSoC5/CySpc.c **** * Id of the array. - 161:.\Generated_Source\PSoC5/CySpc.c **** * - 162:.\Generated_Source\PSoC5/CySpc.c **** * uint16 address: - 163:.\Generated_Source\PSoC5/CySpc.c **** * Flash/eeprom addrress - 164:.\Generated_Source\PSoC5/CySpc.c **** * - 165:.\Generated_Source\PSoC5/CySpc.c **** * uint8* buffer: - 166:.\Generated_Source\PSoC5/CySpc.c **** * Data to load to the row latch - 167:.\Generated_Source\PSoC5/CySpc.c **** * - 168:.\Generated_Source\PSoC5/CySpc.c **** * uint16 number: - 169:.\Generated_Source\PSoC5/CySpc.c **** * Number bytes to load. - 170:.\Generated_Source\PSoC5/CySpc.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 7 - - - 171:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 172:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_STARTED - 173:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_CANCELED - 174:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_LOCKED - 175:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_BAD_PARAM - 176:.\Generated_Source\PSoC5/CySpc.c **** * - 177:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 178:.\Generated_Source\PSoC5/CySpc.c **** cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ - 179:.\Generated_Source\PSoC5/CySpc.c **** - 180:.\Generated_Source\PSoC5/CySpc.c **** { - 171 .loc 1 180 0 - 172 .cfi_startproc - 173 @ args = 0, pretend = 0, frame = 0 - 174 @ frame_needed = 0, uses_anonymous_args = 0 - 175 .LVL7: - 181:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 182:.\Generated_Source\PSoC5/CySpc.c **** uint8 i; - 183:.\Generated_Source\PSoC5/CySpc.c **** - 184:.\Generated_Source\PSoC5/CySpc.c **** /*************************************************************************** - 185:.\Generated_Source\PSoC5/CySpc.c **** * Check if number is correct for array. Number must be less than - 186:.\Generated_Source\PSoC5/CySpc.c **** * 32 for Flash or less than 16 for EEPROM. - 187:.\Generated_Source\PSoC5/CySpc.c **** ***************************************************************************/ - 188:.\Generated_Source\PSoC5/CySpc.c **** if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || - 176 .loc 1 188 0 - 177 0000 3E28 cmp r0, #62 - 180:.\Generated_Source\PSoC5/CySpc.c **** { - 178 .loc 1 180 0 - 179 0002 70B5 push {r4, r5, r6, lr} - 180 .LCFI3: - 181 .cfi_def_cfa_offset 16 - 182 .cfi_offset 4, -16 - 183 .cfi_offset 5, -12 - 184 .cfi_offset 6, -8 - 185 .cfi_offset 14, -4 - 186 .loc 1 188 0 - 187 0004 01D8 bhi .L18 - 188 .loc 1 188 0 is_stmt 0 discriminator 1 - 189 0006 1F2B cmp r3, #31 - 190 0008 02E0 b .L28 - 191 .L18: - 192 .loc 1 188 0 discriminator 2 - 193 000a 3F28 cmp r0, #63 - 194 000c 27D0 beq .L24 - 189:.\Generated_Source\PSoC5/CySpc.c **** ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) - 195 .loc 1 189 0 is_stmt 1 - 196 000e 0F2B cmp r3, #15 - 197 .L28: - 198 0010 25D8 bhi .L24 - 190:.\Generated_Source\PSoC5/CySpc.c **** { - 191:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_IDLE) - 199 .loc 1 191 0 - 200 0012 164D ldr r5, .L30 - 201 0014 2C78 ldrb r4, [r5, #0] @ zero_extendqisi2 - 202 0016 04F00204 and r4, r4, #2 - 203 001a E4B2 uxtb r4, r4 - 204 001c 0CB3 cbz r4, .L25 - 192:.\Generated_Source\PSoC5/CySpc.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 8 - - - 193:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - 205 .loc 1 193 0 - 206 001e 144C ldr r4, .L30+4 - 207 0020 B626 movs r6, #182 - 208 0022 2670 strb r6, [r4, #0] - 194:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); - 209 .loc 1 194 0 - 210 0024 D426 movs r6, #212 - 211 0026 2670 strb r6, [r4, #0] - 195:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; - 212 .loc 1 195 0 - 213 0028 0126 movs r6, #1 - 214 002a 2670 strb r6, [r4, #0] - 196:.\Generated_Source\PSoC5/CySpc.c **** - 197:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_BUSY) - 215 .loc 1 197 0 - 216 002c 2D78 ldrb r5, [r5, #0] @ zero_extendqisi2 - 217 002e 05F00205 and r5, r5, #2 - 218 0032 EDB2 uxtb r5, r5 - 219 0034 BDB9 cbnz r5, .L26 - 198:.\Generated_Source\PSoC5/CySpc.c **** { - 199:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = array; - 220 .loc 1 199 0 - 221 0036 2070 strb r0, [r4, #0] - 200:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = 1u & HI8(address); - 222 .loc 1 200 0 - 223 0038 C1F30020 ubfx r0, r1, #8, #1 - 224 .LVL8: - 225 003c 2070 strb r0, [r4, #0] - 201:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = LO8(address); - 226 .loc 1 201 0 - 227 003e C9B2 uxtb r1, r1 - 228 .LVL9: - 202:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); - 229 .loc 1 202 0 - 230 0040 581E subs r0, r3, #1 - 201:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = LO8(address); - 231 .loc 1 201 0 - 232 0042 2170 strb r1, [r4, #0] - 233 .loc 1 202 0 - 234 0044 C1B2 uxtb r1, r0 - 235 0046 2170 strb r1, [r4, #0] - 236 .LVL10: - 203:.\Generated_Source\PSoC5/CySpc.c **** - 204:.\Generated_Source\PSoC5/CySpc.c **** for(i = 0u; i < size; i++) - 237 .loc 1 204 0 - 238 0048 2946 mov r1, r5 - 239 .LVL11: - 240 .L21: - 241 .loc 1 204 0 is_stmt 0 discriminator 1 - 242 004a C8B2 uxtb r0, r1 - 243 004c 9842 cmp r0, r3 - 244 004e 04D2 bcs .L29 - 245 .L22: - 205:.\Generated_Source\PSoC5/CySpc.c **** { - 206:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = buffer[i]; - 246 .loc 1 206 0 is_stmt 1 discriminator 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 9 - - - 247 0050 545C ldrb r4, [r2, r1] @ zero_extendqisi2 - 248 0052 0748 ldr r0, .L30+4 - 249 .LVL12: - 250 0054 0131 adds r1, r1, #1 - 251 0056 0470 strb r4, [r0, #0] - 252 0058 F7E7 b .L21 - 253 .LVL13: - 254 .L29: - 181:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 255 .loc 1 181 0 - 256 005a 0720 movs r0, #7 - 257 005c 70BD pop {r4, r5, r6, pc} - 258 .LVL14: - 259 .L24: - 207:.\Generated_Source\PSoC5/CySpc.c **** } - 208:.\Generated_Source\PSoC5/CySpc.c **** } - 209:.\Generated_Source\PSoC5/CySpc.c **** else - 210:.\Generated_Source\PSoC5/CySpc.c **** { - 211:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 212:.\Generated_Source\PSoC5/CySpc.c **** } - 213:.\Generated_Source\PSoC5/CySpc.c **** } - 214:.\Generated_Source\PSoC5/CySpc.c **** else - 215:.\Generated_Source\PSoC5/CySpc.c **** { - 216:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_LOCKED; - 217:.\Generated_Source\PSoC5/CySpc.c **** } - 218:.\Generated_Source\PSoC5/CySpc.c **** } - 219:.\Generated_Source\PSoC5/CySpc.c **** else - 220:.\Generated_Source\PSoC5/CySpc.c **** { - 221:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_BAD_PARAM; - 260 .loc 1 221 0 - 261 005e 0120 movs r0, #1 - 262 .LVL15: - 263 0060 70BD pop {r4, r5, r6, pc} - 264 .LVL16: - 265 .L25: - 216:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_LOCKED; - 266 .loc 1 216 0 - 267 0062 0420 movs r0, #4 - 268 .LVL17: - 269 0064 70BD pop {r4, r5, r6, pc} - 270 .LVL18: - 271 .L26: - 211:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 272 .loc 1 211 0 - 273 0066 0920 movs r0, #9 - 274 .LVL19: - 222:.\Generated_Source\PSoC5/CySpc.c **** } - 223:.\Generated_Source\PSoC5/CySpc.c **** - 224:.\Generated_Source\PSoC5/CySpc.c **** return(status); - 225:.\Generated_Source\PSoC5/CySpc.c **** } - 275 .loc 1 225 0 - 276 0068 70BD pop {r4, r5, r6, pc} - 277 .L31: - 278 006a 00BF .align 2 - 279 .L30: - 280 006c 22470040 .word 1073760034 - 281 0070 20470040 .word 1073760032 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 10 - - - 282 .cfi_endproc - 283 .LFE3: - 284 .size CySpcLoadMultiByte, .-CySpcLoadMultiByte - 285 .section .text.CySpcLoadRow,"ax",%progbits - 286 .align 1 - 287 .global CySpcLoadRow - 288 .thumb - 289 .thumb_func - 290 .type CySpcLoadRow, %function - 291 CySpcLoadRow: - 292 .LFB4: - 226:.\Generated_Source\PSoC5/CySpc.c **** - 227:.\Generated_Source\PSoC5/CySpc.c **** - 228:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 229:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcLoadRow - 230:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 231:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 232:.\Generated_Source\PSoC5/CySpc.c **** * Loads a row of data into the row latch of a Flash/EEPROM array. - 233:.\Generated_Source\PSoC5/CySpc.c **** * - 234:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 235:.\Generated_Source\PSoC5/CySpc.c **** * uint8 array: - 236:.\Generated_Source\PSoC5/CySpc.c **** * Id of the array. - 237:.\Generated_Source\PSoC5/CySpc.c **** * - 238:.\Generated_Source\PSoC5/CySpc.c **** * uint8* buffer: - 239:.\Generated_Source\PSoC5/CySpc.c **** * Data to be loaded to the row latch - 240:.\Generated_Source\PSoC5/CySpc.c **** * - 241:.\Generated_Source\PSoC5/CySpc.c **** * uint8 size: - 242:.\Generated_Source\PSoC5/CySpc.c **** * The number of data bytes that the SPC expects to be written. Depends on the - 243:.\Generated_Source\PSoC5/CySpc.c **** * type of the array and, if the array is Flash, whether ECC is being enabled - 244:.\Generated_Source\PSoC5/CySpc.c **** * or not. There are following values: flash row latch size with ECC enabled, - 245:.\Generated_Source\PSoC5/CySpc.c **** * flash row latch size with ECC disabled and EEPROM row latch size. - 246:.\Generated_Source\PSoC5/CySpc.c **** * - 247:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 248:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_STARTED - 249:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_CANCELED - 250:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_LOCKED - 251:.\Generated_Source\PSoC5/CySpc.c **** * - 252:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 253:.\Generated_Source\PSoC5/CySpc.c **** cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) - 254:.\Generated_Source\PSoC5/CySpc.c **** { - 293 .loc 1 254 0 - 294 .cfi_startproc - 295 @ args = 0, pretend = 0, frame = 0 - 296 @ frame_needed = 0, uses_anonymous_args = 0 - 297 .LVL20: - 298 0000 30B5 push {r4, r5, lr} - 299 .LCFI4: - 300 .cfi_def_cfa_offset 12 - 301 .cfi_offset 4, -12 - 302 .cfi_offset 5, -8 - 303 .cfi_offset 14, -4 - 255:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 256:.\Generated_Source\PSoC5/CySpc.c **** uint16 i; - 257:.\Generated_Source\PSoC5/CySpc.c **** - 258:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the SPC is ready to accept command */ - 259:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_IDLE) - 304 .loc 1 259 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 11 - - - 305 0002 104B ldr r3, .L39 - 306 0004 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 307 0006 04F00204 and r4, r4, #2 - 308 000a E4B2 uxtb r4, r4 - 309 000c ACB1 cbz r4, .L36 - 260:.\Generated_Source\PSoC5/CySpc.c **** { - 261:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - 310 .loc 1 261 0 - 311 000e 0E4C ldr r4, .L39+4 - 312 0010 B625 movs r5, #182 - 313 0012 2570 strb r5, [r4, #0] - 262:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); - 314 .loc 1 262 0 - 315 0014 D525 movs r5, #213 - 316 0016 2570 strb r5, [r4, #0] - 263:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; - 317 .loc 1 263 0 - 318 0018 0225 movs r5, #2 - 319 001a 2570 strb r5, [r4, #0] - 264:.\Generated_Source\PSoC5/CySpc.c **** - 265:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the command was accepted */ - 266:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_BUSY) - 320 .loc 1 266 0 - 321 001c 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 322 001e 2B40 ands r3, r3, r5 - 323 0020 DBB2 uxtb r3, r3 - 324 0022 63B9 cbnz r3, .L37 - 267:.\Generated_Source\PSoC5/CySpc.c **** { - 268:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = array; - 325 .loc 1 268 0 - 326 0024 2070 strb r0, [r4, #0] - 327 .LVL21: - 328 .L34: - 269:.\Generated_Source\PSoC5/CySpc.c **** - 270:.\Generated_Source\PSoC5/CySpc.c **** for(i = 0u; i < size; i++) - 329 .loc 1 270 0 discriminator 1 - 330 0026 98B2 uxth r0, r3 - 331 0028 9042 cmp r0, r2 - 332 002a 04D2 bcs .L38 - 333 .L35: - 271:.\Generated_Source\PSoC5/CySpc.c **** { - 272:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = buffer[i]; - 334 .loc 1 272 0 discriminator 2 - 335 002c CC5C ldrb r4, [r1, r3] @ zero_extendqisi2 - 336 002e 0648 ldr r0, .L39+4 - 337 .LVL22: - 338 0030 0133 adds r3, r3, #1 - 339 0032 0470 strb r4, [r0, #0] - 340 0034 F7E7 b .L34 - 341 .LVL23: - 342 .L38: - 255:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 343 .loc 1 255 0 - 344 0036 0720 movs r0, #7 - 345 0038 30BD pop {r4, r5, pc} - 346 .LVL24: - 347 .L36: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 12 - - - 273:.\Generated_Source\PSoC5/CySpc.c **** } - 274:.\Generated_Source\PSoC5/CySpc.c **** } - 275:.\Generated_Source\PSoC5/CySpc.c **** else - 276:.\Generated_Source\PSoC5/CySpc.c **** { - 277:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 278:.\Generated_Source\PSoC5/CySpc.c **** } - 279:.\Generated_Source\PSoC5/CySpc.c **** } - 280:.\Generated_Source\PSoC5/CySpc.c **** else - 281:.\Generated_Source\PSoC5/CySpc.c **** { - 282:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_LOCKED; - 348 .loc 1 282 0 - 349 003a 0420 movs r0, #4 - 350 .LVL25: - 351 003c 30BD pop {r4, r5, pc} - 352 .LVL26: - 353 .L37: - 277:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 354 .loc 1 277 0 - 355 003e 0920 movs r0, #9 - 356 .LVL27: - 283:.\Generated_Source\PSoC5/CySpc.c **** } - 284:.\Generated_Source\PSoC5/CySpc.c **** - 285:.\Generated_Source\PSoC5/CySpc.c **** return(status); - 286:.\Generated_Source\PSoC5/CySpc.c **** } - 357 .loc 1 286 0 - 358 0040 30BD pop {r4, r5, pc} - 359 .L40: - 360 0042 00BF .align 2 - 361 .L39: - 362 0044 22470040 .word 1073760034 - 363 0048 20470040 .word 1073760032 - 364 .cfi_endproc - 365 .LFE4: - 366 .size CySpcLoadRow, .-CySpcLoadRow - 367 .section .text.CySpcWriteRow,"ax",%progbits - 368 .align 1 - 369 .global CySpcWriteRow - 370 .thumb - 371 .thumb_func - 372 .type CySpcWriteRow, %function - 373 CySpcWriteRow: - 374 .LFB5: - 287:.\Generated_Source\PSoC5/CySpc.c **** - 288:.\Generated_Source\PSoC5/CySpc.c **** - 289:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 290:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcWriteRow - 291:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 292:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 293:.\Generated_Source\PSoC5/CySpc.c **** * Erases then programs a row in Flash/EEPROM with data in row latch. - 294:.\Generated_Source\PSoC5/CySpc.c **** * - 295:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 296:.\Generated_Source\PSoC5/CySpc.c **** * uint8 array: - 297:.\Generated_Source\PSoC5/CySpc.c **** * Id of the array. - 298:.\Generated_Source\PSoC5/CySpc.c **** * - 299:.\Generated_Source\PSoC5/CySpc.c **** * uint16 address: - 300:.\Generated_Source\PSoC5/CySpc.c **** * flash/eeprom addrress - 301:.\Generated_Source\PSoC5/CySpc.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 13 - - - 302:.\Generated_Source\PSoC5/CySpc.c **** * uint8 tempPolarity: - 303:.\Generated_Source\PSoC5/CySpc.c **** * temperature polarity. - 304:.\Generated_Source\PSoC5/CySpc.c **** * 1: the Temp Magnitude is interpreted as a positive value - 305:.\Generated_Source\PSoC5/CySpc.c **** * 0: the Temp Magnitude is interpreted as a negative value - 306:.\Generated_Source\PSoC5/CySpc.c **** * - 307:.\Generated_Source\PSoC5/CySpc.c **** * uint8 tempMagnitude: - 308:.\Generated_Source\PSoC5/CySpc.c **** * temperature magnitude. - 309:.\Generated_Source\PSoC5/CySpc.c **** * - 310:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 311:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_STARTED - 312:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_CANCELED - 313:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_LOCKED - 314:.\Generated_Source\PSoC5/CySpc.c **** * - 315:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 316:.\Generated_Source\PSoC5/CySpc.c **** cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ - 317:.\Generated_Source\PSoC5/CySpc.c **** - 318:.\Generated_Source\PSoC5/CySpc.c **** { - 375 .loc 1 318 0 - 376 .cfi_startproc - 377 @ args = 0, pretend = 0, frame = 0 - 378 @ frame_needed = 0, uses_anonymous_args = 0 - 379 .LVL28: - 380 0000 70B5 push {r4, r5, r6, lr} - 381 .LCFI5: - 382 .cfi_def_cfa_offset 16 - 383 .cfi_offset 4, -16 - 384 .cfi_offset 5, -12 - 385 .cfi_offset 6, -8 - 386 .cfi_offset 14, -4 - 319:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 320:.\Generated_Source\PSoC5/CySpc.c **** - 321:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the SPC is ready to accept command */ - 322:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_IDLE) - 387 .loc 1 322 0 - 388 0002 0F4D ldr r5, .L45 - 389 0004 2C78 ldrb r4, [r5, #0] @ zero_extendqisi2 - 390 0006 04F00204 and r4, r4, #2 - 391 000a E4B2 uxtb r4, r4 - 392 000c A4B1 cbz r4, .L43 - 323:.\Generated_Source\PSoC5/CySpc.c **** { - 324:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - 393 .loc 1 324 0 - 394 000e 0D4C ldr r4, .L45+4 - 395 0010 B626 movs r6, #182 - 396 0012 2670 strb r6, [r4, #0] - 325:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); - 397 .loc 1 325 0 - 398 0014 D826 movs r6, #216 - 399 0016 2670 strb r6, [r4, #0] - 326:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; - 400 .loc 1 326 0 - 401 0018 0526 movs r6, #5 - 402 001a 2670 strb r6, [r4, #0] - 327:.\Generated_Source\PSoC5/CySpc.c **** - 328:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the command was accepted */ - 329:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_BUSY) - 403 .loc 1 329 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 14 - - - 404 001c 2D78 ldrb r5, [r5, #0] @ zero_extendqisi2 - 405 001e 05F00205 and r5, r5, #2 - 406 0022 EDB2 uxtb r5, r5 - 407 0024 55B9 cbnz r5, .L44 - 330:.\Generated_Source\PSoC5/CySpc.c **** { - 331:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = array; - 408 .loc 1 331 0 - 409 0026 2070 strb r0, [r4, #0] - 332:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = HI8(address); - 410 .loc 1 332 0 - 411 0028 080A lsrs r0, r1, #8 - 412 .LVL29: - 333:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = LO8(address); - 413 .loc 1 333 0 - 414 002a C9B2 uxtb r1, r1 - 415 .LVL30: - 332:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = HI8(address); - 416 .loc 1 332 0 - 417 002c 2070 strb r0, [r4, #0] - 418 .loc 1 333 0 - 419 002e 2170 strb r1, [r4, #0] - 319:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 420 .loc 1 319 0 - 421 0030 0720 movs r0, #7 - 334:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = tempPolarity; - 422 .loc 1 334 0 - 423 0032 2270 strb r2, [r4, #0] - 335:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = tempMagnitude; - 424 .loc 1 335 0 - 425 0034 2370 strb r3, [r4, #0] - 426 0036 70BD pop {r4, r5, r6, pc} - 427 .LVL31: - 428 .L43: - 336:.\Generated_Source\PSoC5/CySpc.c **** } - 337:.\Generated_Source\PSoC5/CySpc.c **** else - 338:.\Generated_Source\PSoC5/CySpc.c **** { - 339:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 340:.\Generated_Source\PSoC5/CySpc.c **** } - 341:.\Generated_Source\PSoC5/CySpc.c **** } - 342:.\Generated_Source\PSoC5/CySpc.c **** else - 343:.\Generated_Source\PSoC5/CySpc.c **** { - 344:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_LOCKED; - 429 .loc 1 344 0 - 430 0038 0420 movs r0, #4 - 431 .LVL32: - 432 003a 70BD pop {r4, r5, r6, pc} - 433 .LVL33: - 434 .L44: - 339:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 435 .loc 1 339 0 - 436 003c 0920 movs r0, #9 - 437 .LVL34: - 345:.\Generated_Source\PSoC5/CySpc.c **** } - 346:.\Generated_Source\PSoC5/CySpc.c **** - 347:.\Generated_Source\PSoC5/CySpc.c **** return(status); - 348:.\Generated_Source\PSoC5/CySpc.c **** } - 438 .loc 1 348 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 15 - - - 439 003e 70BD pop {r4, r5, r6, pc} - 440 .L46: - 441 .align 2 - 442 .L45: - 443 0040 22470040 .word 1073760034 - 444 0044 20470040 .word 1073760032 - 445 .cfi_endproc - 446 .LFE5: - 447 .size CySpcWriteRow, .-CySpcWriteRow - 448 .section .text.CySpcEraseSector,"ax",%progbits - 449 .align 1 - 450 .global CySpcEraseSector - 451 .thumb - 452 .thumb_func - 453 .type CySpcEraseSector, %function - 454 CySpcEraseSector: - 455 .LFB6: - 349:.\Generated_Source\PSoC5/CySpc.c **** - 350:.\Generated_Source\PSoC5/CySpc.c **** - 351:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 352:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcEraseSector - 353:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 354:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 355:.\Generated_Source\PSoC5/CySpc.c **** * Erases all data in the addressed sector (block of 64 rows). - 356:.\Generated_Source\PSoC5/CySpc.c **** * - 357:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 358:.\Generated_Source\PSoC5/CySpc.c **** * uint8 array: - 359:.\Generated_Source\PSoC5/CySpc.c **** * Id of the array. - 360:.\Generated_Source\PSoC5/CySpc.c **** * - 361:.\Generated_Source\PSoC5/CySpc.c **** * uint8 sectorNumber: - 362:.\Generated_Source\PSoC5/CySpc.c **** * Zero based sector number within Flash/EEPROM array - 363:.\Generated_Source\PSoC5/CySpc.c **** * - 364:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 365:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_STARTED - 366:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_CANCELED - 367:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_LOCKED - 368:.\Generated_Source\PSoC5/CySpc.c **** * - 369:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 370:.\Generated_Source\PSoC5/CySpc.c **** cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) - 371:.\Generated_Source\PSoC5/CySpc.c **** { - 456 .loc 1 371 0 - 457 .cfi_startproc - 458 @ args = 0, pretend = 0, frame = 0 - 459 @ frame_needed = 0, uses_anonymous_args = 0 - 460 .LVL35: - 461 0000 10B5 push {r4, lr} - 462 .LCFI6: - 463 .cfi_def_cfa_offset 8 - 464 .cfi_offset 4, -8 - 465 .cfi_offset 14, -4 - 372:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 373:.\Generated_Source\PSoC5/CySpc.c **** - 374:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the SPC is ready to accept command */ - 375:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_IDLE) - 466 .loc 1 375 0 - 467 0002 0D4A ldr r2, .L51 - 468 0004 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 16 - - - 469 0006 03F00203 and r3, r3, #2 - 470 000a DBB2 uxtb r3, r3 - 471 000c 7BB1 cbz r3, .L49 - 376:.\Generated_Source\PSoC5/CySpc.c **** { - 377:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - 472 .loc 1 377 0 - 473 000e 0B4B ldr r3, .L51+4 - 474 0010 B624 movs r4, #182 - 475 0012 1C70 strb r4, [r3, #0] - 378:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); - 476 .loc 1 378 0 - 477 0014 DB24 movs r4, #219 - 478 0016 1C70 strb r4, [r3, #0] - 379:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; - 479 .loc 1 379 0 - 480 0018 0824 movs r4, #8 - 481 001a 1C70 strb r4, [r3, #0] - 380:.\Generated_Source\PSoC5/CySpc.c **** - 381:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the command was accepted */ - 382:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_BUSY) - 482 .loc 1 382 0 - 483 001c 1278 ldrb r2, [r2, #0] @ zero_extendqisi2 - 484 001e 02F00202 and r2, r2, #2 - 485 0022 D2B2 uxtb r2, r2 - 486 0024 2AB9 cbnz r2, .L50 - 383:.\Generated_Source\PSoC5/CySpc.c **** { - 384:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = array; - 487 .loc 1 384 0 - 488 0026 1870 strb r0, [r3, #0] - 385:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = sectorNumber; - 489 .loc 1 385 0 - 490 0028 1970 strb r1, [r3, #0] - 372:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 491 .loc 1 372 0 - 492 002a 0720 movs r0, #7 - 493 .LVL36: - 494 002c 10BD pop {r4, pc} - 495 .LVL37: - 496 .L49: - 386:.\Generated_Source\PSoC5/CySpc.c **** } - 387:.\Generated_Source\PSoC5/CySpc.c **** else - 388:.\Generated_Source\PSoC5/CySpc.c **** { - 389:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 390:.\Generated_Source\PSoC5/CySpc.c **** } - 391:.\Generated_Source\PSoC5/CySpc.c **** } - 392:.\Generated_Source\PSoC5/CySpc.c **** else - 393:.\Generated_Source\PSoC5/CySpc.c **** { - 394:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_LOCKED; - 497 .loc 1 394 0 - 498 002e 0420 movs r0, #4 - 499 .LVL38: - 500 0030 10BD pop {r4, pc} - 501 .LVL39: - 502 .L50: - 389:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 503 .loc 1 389 0 - 504 0032 0920 movs r0, #9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 17 - - - 505 .LVL40: - 395:.\Generated_Source\PSoC5/CySpc.c **** } - 396:.\Generated_Source\PSoC5/CySpc.c **** - 397:.\Generated_Source\PSoC5/CySpc.c **** return(status); - 398:.\Generated_Source\PSoC5/CySpc.c **** } - 506 .loc 1 398 0 - 507 0034 10BD pop {r4, pc} - 508 .L52: - 509 0036 00BF .align 2 - 510 .L51: - 511 0038 22470040 .word 1073760034 - 512 003c 20470040 .word 1073760032 - 513 .cfi_endproc - 514 .LFE6: - 515 .size CySpcEraseSector, .-CySpcEraseSector - 516 .section .text.CySpcGetTemp,"ax",%progbits - 517 .align 1 - 518 .global CySpcGetTemp - 519 .thumb - 520 .thumb_func - 521 .type CySpcGetTemp, %function - 522 CySpcGetTemp: - 523 .LFB7: - 399:.\Generated_Source\PSoC5/CySpc.c **** - 400:.\Generated_Source\PSoC5/CySpc.c **** - 401:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 402:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcGetTemp - 403:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 404:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 405:.\Generated_Source\PSoC5/CySpc.c **** * Returns the internal die temperature - 406:.\Generated_Source\PSoC5/CySpc.c **** * - 407:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 408:.\Generated_Source\PSoC5/CySpc.c **** * uint8 numSamples: - 409:.\Generated_Source\PSoC5/CySpc.c **** * Number of samples. Valid values are 1-5, resulting in 2 - 32 samples - 410:.\Generated_Source\PSoC5/CySpc.c **** * respectively. - 411:.\Generated_Source\PSoC5/CySpc.c **** * - 412:.\Generated_Source\PSoC5/CySpc.c **** * uint16 timerPeriod: - 413:.\Generated_Source\PSoC5/CySpc.c **** * Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits - 414:.\Generated_Source\PSoC5/CySpc.c **** * of 16 bit values are ignored. - 415:.\Generated_Source\PSoC5/CySpc.c **** * - 416:.\Generated_Source\PSoC5/CySpc.c **** * uint8 clkDivSelect: - 417:.\Generated_Source\PSoC5/CySpc.c **** * ADC ACLK clock divide value. Valid values are 2 - 225. - 418:.\Generated_Source\PSoC5/CySpc.c **** * - 419:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 420:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_STARTED - 421:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_CANCELED - 422:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_LOCKED - 423:.\Generated_Source\PSoC5/CySpc.c **** * - 424:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 425:.\Generated_Source\PSoC5/CySpc.c **** cystatus CySpcGetTemp(uint8 numSamples) - 426:.\Generated_Source\PSoC5/CySpc.c **** { - 524 .loc 1 426 0 - 525 .cfi_startproc - 526 @ args = 0, pretend = 0, frame = 0 - 527 @ frame_needed = 0, uses_anonymous_args = 0 - 528 @ link register save eliminated. - 529 .LVL41: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 18 - - - 427:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 428:.\Generated_Source\PSoC5/CySpc.c **** - 429:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the SPC is ready to accept command */ - 430:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_IDLE) - 530 .loc 1 430 0 - 531 0000 0C4A ldr r2, .L57 - 532 0002 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 533 0004 03F00201 and r1, r3, #2 - 534 0008 CBB2 uxtb r3, r1 - 535 000a 73B1 cbz r3, .L55 - 431:.\Generated_Source\PSoC5/CySpc.c **** { - 432:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - 536 .loc 1 432 0 - 537 000c 0A4B ldr r3, .L57+4 - 538 000e B621 movs r1, #182 - 539 0010 1970 strb r1, [r3, #0] - 433:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); - 540 .loc 1 433 0 - 541 0012 E121 movs r1, #225 - 542 0014 1970 strb r1, [r3, #0] - 434:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; - 543 .loc 1 434 0 - 544 0016 0E21 movs r1, #14 - 545 0018 1970 strb r1, [r3, #0] - 435:.\Generated_Source\PSoC5/CySpc.c **** - 436:.\Generated_Source\PSoC5/CySpc.c **** /* Make sure the command was accepted */ - 437:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_BUSY) - 546 .loc 1 437 0 - 547 001a 1278 ldrb r2, [r2, #0] @ zero_extendqisi2 - 548 001c 02F00201 and r1, r2, #2 - 549 0020 CAB2 uxtb r2, r1 - 550 0022 22B9 cbnz r2, .L56 - 438:.\Generated_Source\PSoC5/CySpc.c **** { - 439:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_DATA_REG = numSamples; - 551 .loc 1 439 0 - 552 0024 1870 strb r0, [r3, #0] - 427:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_STARTED; - 553 .loc 1 427 0 - 554 0026 0720 movs r0, #7 - 555 .LVL42: - 556 0028 7047 bx lr - 557 .LVL43: - 558 .L55: - 440:.\Generated_Source\PSoC5/CySpc.c **** } - 441:.\Generated_Source\PSoC5/CySpc.c **** else - 442:.\Generated_Source\PSoC5/CySpc.c **** { - 443:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 444:.\Generated_Source\PSoC5/CySpc.c **** } - 445:.\Generated_Source\PSoC5/CySpc.c **** } - 446:.\Generated_Source\PSoC5/CySpc.c **** else - 447:.\Generated_Source\PSoC5/CySpc.c **** { - 448:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_LOCKED; - 559 .loc 1 448 0 - 560 002a 0420 movs r0, #4 - 561 .LVL44: - 562 002c 7047 bx lr - 563 .LVL45: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 19 - - - 564 .L56: - 443:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_CANCELED; - 565 .loc 1 443 0 - 566 002e 0920 movs r0, #9 - 567 .LVL46: - 449:.\Generated_Source\PSoC5/CySpc.c **** } - 450:.\Generated_Source\PSoC5/CySpc.c **** - 451:.\Generated_Source\PSoC5/CySpc.c **** return(status); - 452:.\Generated_Source\PSoC5/CySpc.c **** } - 568 .loc 1 452 0 - 569 0030 7047 bx lr - 570 .L58: - 571 0032 00BF .align 2 - 572 .L57: - 573 0034 22470040 .word 1073760034 - 574 0038 20470040 .word 1073760032 - 575 .cfi_endproc - 576 .LFE7: - 577 .size CySpcGetTemp, .-CySpcGetTemp - 578 .section .text.CySpcLock,"ax",%progbits - 579 .align 1 - 580 .global CySpcLock - 581 .thumb - 582 .thumb_func - 583 .type CySpcLock, %function - 584 CySpcLock: - 585 .LFB8: - 453:.\Generated_Source\PSoC5/CySpc.c **** - 454:.\Generated_Source\PSoC5/CySpc.c **** - 455:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 456:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcLock - 457:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - 458:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 459:.\Generated_Source\PSoC5/CySpc.c **** * Locks the SPC so it can not be used by someone else: - 460:.\Generated_Source\PSoC5/CySpc.c **** * - Saves wait-pipeline enable state and enable pipeline (PSoC5) - 461:.\Generated_Source\PSoC5/CySpc.c **** * - 462:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 463:.\Generated_Source\PSoC5/CySpc.c **** * Note - 464:.\Generated_Source\PSoC5/CySpc.c **** * - 465:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 466:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_SUCCESS - if the resource was free. - 467:.\Generated_Source\PSoC5/CySpc.c **** * CYRET_LOCKED - if the SPC is in use. - 468:.\Generated_Source\PSoC5/CySpc.c **** * - 469:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 470:.\Generated_Source\PSoC5/CySpc.c **** cystatus CySpcLock(void) - 471:.\Generated_Source\PSoC5/CySpc.c **** { - 586 .loc 1 471 0 - 587 .cfi_startproc - 588 @ args = 0, pretend = 0, frame = 0 - 589 @ frame_needed = 0, uses_anonymous_args = 0 - 590 .LVL47: - 591 0000 38B5 push {r3, r4, r5, lr} - 592 .LCFI7: - 593 .cfi_def_cfa_offset 16 - 594 .cfi_offset 3, -16 - 595 .cfi_offset 4, -12 - 596 .cfi_offset 5, -8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 20 - - - 597 .cfi_offset 14, -4 - 472:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_LOCKED; - 473:.\Generated_Source\PSoC5/CySpc.c **** uint8 interruptState; - 474:.\Generated_Source\PSoC5/CySpc.c **** - 475:.\Generated_Source\PSoC5/CySpc.c **** /* Enter critical section */ - 476:.\Generated_Source\PSoC5/CySpc.c **** interruptState = CyEnterCriticalSection(); - 598 .loc 1 476 0 - 599 0002 FFF7FEFF bl CyEnterCriticalSection - 600 .LVL48: - 477:.\Generated_Source\PSoC5/CySpc.c **** - 478:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_UNLOCKED == SpcLockState) - 601 .loc 1 478 0 - 602 0006 0C4B ldr r3, .L63 - 603 0008 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 604 000a 79B9 cbnz r1, .L61 - 479:.\Generated_Source\PSoC5/CySpc.c **** { - 480:.\Generated_Source\PSoC5/CySpc.c **** SpcLockState = CY_SPC_LOCKED; - 605 .loc 1 480 0 - 606 000c 0125 movs r5, #1 - 481:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_SUCCESS; - 482:.\Generated_Source\PSoC5/CySpc.c **** - 483:.\Generated_Source\PSoC5/CySpc.c **** #if(CY_PSOC5) - 484:.\Generated_Source\PSoC5/CySpc.c **** - 485:.\Generated_Source\PSoC5/CySpc.c **** if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) - 607 .loc 1 485 0 - 608 000e 0B4A ldr r2, .L63+4 - 480:.\Generated_Source\PSoC5/CySpc.c **** SpcLockState = CY_SPC_LOCKED; - 609 .loc 1 480 0 - 610 0010 1D70 strb r5, [r3, #0] - 611 .LVL49: - 612 .loc 1 485 0 - 613 0012 1468 ldr r4, [r2, #0] - 614 0014 2C40 ands r4, r4, r5 - 615 0016 0AD0 beq .L60 - 486:.\Generated_Source\PSoC5/CySpc.c **** { - 487:.\Generated_Source\PSoC5/CySpc.c **** /* Enable pipeline registers */ - 488:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); - 616 .loc 1 488 0 - 617 0018 1468 ldr r4, [r2, #0] - 618 001a 24F00104 bic r4, r4, #1 - 619 001e 1460 str r4, [r2, #0] - 489:.\Generated_Source\PSoC5/CySpc.c **** - 490:.\Generated_Source\PSoC5/CySpc.c **** /* At least 2 NOP instructions are recommended */ - 491:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; - 620 .loc 1 491 0 - 621 @ 491 ".\Generated_Source\PSoC5\CySpc.c" 1 - 622 0020 00BF NOP - 623 - 624 @ 0 "" 2 - 492:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; - 625 .loc 1 492 0 - 626 @ 492 ".\Generated_Source\PSoC5\CySpc.c" 1 - 627 0022 00BF NOP - 628 - 629 @ 0 "" 2 - 493:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; - 630 .loc 1 493 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 21 - - - 631 @ 493 ".\Generated_Source\PSoC5\CySpc.c" 1 - 632 0024 00BF NOP - 633 - 634 @ 0 "" 2 - 494:.\Generated_Source\PSoC5/CySpc.c **** - 495:.\Generated_Source\PSoC5/CySpc.c **** spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; - 635 .loc 1 495 0 - 636 .thumb - 637 0026 5D60 str r5, [r3, #4] - 481:.\Generated_Source\PSoC5/CySpc.c **** status = CYRET_SUCCESS; - 638 .loc 1 481 0 - 639 0028 0C46 mov r4, r1 - 640 002a 00E0 b .L60 - 641 .LVL50: - 642 .L61: - 472:.\Generated_Source\PSoC5/CySpc.c **** cystatus status = CYRET_LOCKED; - 643 .loc 1 472 0 - 644 002c 0424 movs r4, #4 - 645 .LVL51: - 646 .L60: - 496:.\Generated_Source\PSoC5/CySpc.c **** } - 497:.\Generated_Source\PSoC5/CySpc.c **** - 498:.\Generated_Source\PSoC5/CySpc.c **** #endif /* (CY_PSOC5) */ - 499:.\Generated_Source\PSoC5/CySpc.c **** } - 500:.\Generated_Source\PSoC5/CySpc.c **** - 501:.\Generated_Source\PSoC5/CySpc.c **** /* Exit critical section */ - 502:.\Generated_Source\PSoC5/CySpc.c **** CyExitCriticalSection(interruptState); - 647 .loc 1 502 0 - 648 002e FFF7FEFF bl CyExitCriticalSection - 649 .LVL52: - 503:.\Generated_Source\PSoC5/CySpc.c **** - 504:.\Generated_Source\PSoC5/CySpc.c **** return(status); - 505:.\Generated_Source\PSoC5/CySpc.c **** } - 650 .loc 1 505 0 - 651 0032 2046 mov r0, r4 - 652 0034 38BD pop {r3, r4, r5, pc} - 653 .L64: - 654 0036 00BF .align 2 - 655 .L63: - 656 0038 00000000 .word .LANCHOR0 - 657 003c 04000840 .word 1074266116 - 658 .cfi_endproc - 659 .LFE8: - 660 .size CySpcLock, .-CySpcLock - 661 .section .text.CySpcUnlock,"ax",%progbits - 662 .align 1 - 663 .global CySpcUnlock - 664 .thumb - 665 .thumb_func - 666 .type CySpcUnlock, %function - 667 CySpcUnlock: - 668 .LFB9: - 506:.\Generated_Source\PSoC5/CySpc.c **** - 507:.\Generated_Source\PSoC5/CySpc.c **** - 508:.\Generated_Source\PSoC5/CySpc.c **** /******************************************************************************* - 509:.\Generated_Source\PSoC5/CySpc.c **** * Function Name: CySpcUnlock - 510:.\Generated_Source\PSoC5/CySpc.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 22 - - - 511:.\Generated_Source\PSoC5/CySpc.c **** * Summary: - 512:.\Generated_Source\PSoC5/CySpc.c **** * Unlocks the SPC so it can be used by someone else: - 513:.\Generated_Source\PSoC5/CySpc.c **** * - Restores wait-pipeline enable state (PSoC5) - 514:.\Generated_Source\PSoC5/CySpc.c **** * - 515:.\Generated_Source\PSoC5/CySpc.c **** * Parameters: - 516:.\Generated_Source\PSoC5/CySpc.c **** * None - 517:.\Generated_Source\PSoC5/CySpc.c **** * - 518:.\Generated_Source\PSoC5/CySpc.c **** * Return: - 519:.\Generated_Source\PSoC5/CySpc.c **** * None - 520:.\Generated_Source\PSoC5/CySpc.c **** * - 521:.\Generated_Source\PSoC5/CySpc.c **** *******************************************************************************/ - 522:.\Generated_Source\PSoC5/CySpc.c **** void CySpcUnlock(void) - 523:.\Generated_Source\PSoC5/CySpc.c **** { - 669 .loc 1 523 0 - 670 .cfi_startproc - 671 @ args = 0, pretend = 0, frame = 0 - 672 @ frame_needed = 0, uses_anonymous_args = 0 - 673 0000 10B5 push {r4, lr} - 674 .LCFI8: - 675 .cfi_def_cfa_offset 8 - 676 .cfi_offset 4, -8 - 677 .cfi_offset 14, -4 - 524:.\Generated_Source\PSoC5/CySpc.c **** uint8 interruptState; - 525:.\Generated_Source\PSoC5/CySpc.c **** - 526:.\Generated_Source\PSoC5/CySpc.c **** /* Enter critical section */ - 527:.\Generated_Source\PSoC5/CySpc.c **** interruptState = CyEnterCriticalSection(); - 678 .loc 1 527 0 - 679 0002 FFF7FEFF bl CyEnterCriticalSection - 680 .LVL53: - 528:.\Generated_Source\PSoC5/CySpc.c **** - 529:.\Generated_Source\PSoC5/CySpc.c **** /* Release the SPC object */ - 530:.\Generated_Source\PSoC5/CySpc.c **** SpcLockState = CY_SPC_UNLOCKED; - 681 .loc 1 530 0 - 682 0006 094B ldr r3, .L67 - 683 0008 0022 movs r2, #0 - 531:.\Generated_Source\PSoC5/CySpc.c **** - 532:.\Generated_Source\PSoC5/CySpc.c **** #if(CY_PSOC5) - 533:.\Generated_Source\PSoC5/CySpc.c **** - 534:.\Generated_Source\PSoC5/CySpc.c **** if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) - 684 .loc 1 534 0 - 685 000a 5968 ldr r1, [r3, #4] - 530:.\Generated_Source\PSoC5/CySpc.c **** SpcLockState = CY_SPC_UNLOCKED; - 686 .loc 1 530 0 - 687 000c 1A70 strb r2, [r3, #0] - 688 .loc 1 534 0 - 689 000e 0129 cmp r1, #1 - 690 0010 08D1 bne .L66 - 535:.\Generated_Source\PSoC5/CySpc.c **** { - 536:.\Generated_Source\PSoC5/CySpc.c **** /* Force to bypass pipeline registers */ - 537:.\Generated_Source\PSoC5/CySpc.c **** CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; - 691 .loc 1 537 0 - 692 0012 0749 ldr r1, .L67+4 - 693 0014 0C68 ldr r4, [r1, #0] - 694 0016 44F00104 orr r4, r4, #1 - 695 001a 0C60 str r4, [r1, #0] - 538:.\Generated_Source\PSoC5/CySpc.c **** - 539:.\Generated_Source\PSoC5/CySpc.c **** /* At least 2 NOP instructions are recommended */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 23 - - - 540:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; - 696 .loc 1 540 0 - 697 @ 540 ".\Generated_Source\PSoC5\CySpc.c" 1 - 698 001c 00BF NOP - 699 - 700 @ 0 "" 2 - 541:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; - 701 .loc 1 541 0 - 702 @ 541 ".\Generated_Source\PSoC5\CySpc.c" 1 - 703 001e 00BF NOP - 704 - 705 @ 0 "" 2 - 542:.\Generated_Source\PSoC5/CySpc.c **** CY_NOP; - 706 .loc 1 542 0 - 707 @ 542 ".\Generated_Source\PSoC5\CySpc.c" 1 - 708 0020 00BF NOP - 709 - 710 @ 0 "" 2 - 543:.\Generated_Source\PSoC5/CySpc.c **** - 544:.\Generated_Source\PSoC5/CySpc.c **** spcWaitPipeBypass = 0u; - 711 .loc 1 544 0 - 712 .thumb - 713 0022 5A60 str r2, [r3, #4] - 714 .L66: - 545:.\Generated_Source\PSoC5/CySpc.c **** } - 546:.\Generated_Source\PSoC5/CySpc.c **** - 547:.\Generated_Source\PSoC5/CySpc.c **** #endif /* (CY_PSOC5) */ - 548:.\Generated_Source\PSoC5/CySpc.c **** - 549:.\Generated_Source\PSoC5/CySpc.c **** /* Exit critical section */ - 550:.\Generated_Source\PSoC5/CySpc.c **** CyExitCriticalSection(interruptState); - 551:.\Generated_Source\PSoC5/CySpc.c **** } - 715 .loc 1 551 0 - 716 0024 BDE81040 pop {r4, lr} - 550:.\Generated_Source\PSoC5/CySpc.c **** CyExitCriticalSection(interruptState); - 717 .loc 1 550 0 - 718 0028 FFF7FEBF b CyExitCriticalSection - 719 .LVL54: - 720 .L68: - 721 .align 2 - 722 .L67: - 723 002c 00000000 .word .LANCHOR0 - 724 0030 04000840 .word 1074266116 - 725 .cfi_endproc - 726 .LFE9: - 727 .size CySpcUnlock, .-CySpcUnlock - 728 .global SpcLockState - 729 .bss - 730 .align 2 - 731 .set .LANCHOR0,. + 0 - 732 .type SpcLockState, %object - 733 .size SpcLockState, 1 - 734 SpcLockState: - 735 0000 00 .space 1 - 736 0001 000000 .space 3 - 737 .type spcWaitPipeBypass, %object - 738 .size spcWaitPipeBypass, 4 - 739 spcWaitPipeBypass: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 24 - - - 740 0004 00000000 .space 4 - 741 .text - 742 .Letext0: - 743 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 744 .file 3 ".\\Generated_Source\\PSoC5\\CyLib.h" - 745 .section .debug_info,"",%progbits - 746 .Ldebug_info0: - 747 0000 6B040000 .4byte 0x46b - 748 0004 0200 .2byte 0x2 - 749 0006 00000000 .4byte .Ldebug_abbrev0 - 750 000a 04 .byte 0x4 - 751 000b 01 .uleb128 0x1 - 752 000c 57020000 .4byte .LASF40 - 753 0010 01 .byte 0x1 - 754 0011 45000000 .4byte .LASF41 - 755 0015 CA000000 .4byte .LASF42 - 756 0019 00000000 .4byte .Ldebug_ranges0+0 - 757 001d 00000000 .4byte 0 - 758 0021 00000000 .4byte 0 - 759 0025 00000000 .4byte .Ldebug_line0 - 760 0029 02 .uleb128 0x2 - 761 002a 01 .byte 0x1 - 762 002b 06 .byte 0x6 - 763 002c 4B020000 .4byte .LASF0 - 764 0030 02 .uleb128 0x2 - 765 0031 01 .byte 0x1 - 766 0032 08 .byte 0x8 - 767 0033 21010000 .4byte .LASF1 - 768 0037 02 .uleb128 0x2 - 769 0038 02 .byte 0x2 - 770 0039 05 .byte 0x5 - 771 003a FC010000 .4byte .LASF2 - 772 003e 02 .uleb128 0x2 - 773 003f 02 .byte 0x2 - 774 0040 07 .byte 0x7 - 775 0041 66000000 .4byte .LASF3 - 776 0045 02 .uleb128 0x2 - 777 0046 04 .byte 0x4 - 778 0047 05 .byte 0x5 - 779 0048 30020000 .4byte .LASF4 - 780 004c 02 .uleb128 0x2 - 781 004d 04 .byte 0x4 - 782 004e 07 .byte 0x7 - 783 004f B8000000 .4byte .LASF5 - 784 0053 02 .uleb128 0x2 - 785 0054 08 .byte 0x8 - 786 0055 05 .byte 0x5 - 787 0056 DF010000 .4byte .LASF6 - 788 005a 02 .uleb128 0x2 - 789 005b 08 .byte 0x8 - 790 005c 07 .byte 0x7 - 791 005d 87010000 .4byte .LASF7 - 792 0061 03 .uleb128 0x3 - 793 0062 04 .byte 0x4 - 794 0063 05 .byte 0x5 - 795 0064 696E7400 .ascii "int\000" - 796 0068 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 25 - - - 797 0069 04 .byte 0x4 - 798 006a 07 .byte 0x7 - 799 006b 72010000 .4byte .LASF8 - 800 006f 04 .uleb128 0x4 - 801 0070 FB000000 .4byte .LASF9 - 802 0074 02 .byte 0x2 - 803 0075 5B .byte 0x5b - 804 0076 30000000 .4byte 0x30 - 805 007a 04 .uleb128 0x4 - 806 007b 43010000 .4byte .LASF10 - 807 007f 02 .byte 0x2 - 808 0080 5C .byte 0x5c - 809 0081 3E000000 .4byte 0x3e - 810 0085 04 .uleb128 0x4 - 811 0086 54010000 .4byte .LASF11 - 812 008a 02 .byte 0x2 - 813 008b 5D .byte 0x5d - 814 008c 4C000000 .4byte 0x4c - 815 0090 02 .uleb128 0x2 - 816 0091 04 .byte 0x4 - 817 0092 04 .byte 0x4 - 818 0093 8E000000 .4byte .LASF12 - 819 0097 02 .uleb128 0x2 - 820 0098 08 .byte 0x8 - 821 0099 04 .byte 0x4 - 822 009a 2F010000 .4byte .LASF13 - 823 009e 02 .uleb128 0x2 - 824 009f 01 .byte 0x1 - 825 00a0 08 .byte 0x8 - 826 00a1 F7010000 .4byte .LASF14 - 827 00a5 04 .uleb128 0x4 - 828 00a6 13000000 .4byte .LASF15 - 829 00aa 02 .byte 0x2 - 830 00ab E8 .byte 0xe8 - 831 00ac 4C000000 .4byte 0x4c - 832 00b0 04 .uleb128 0x4 - 833 00b1 A4000000 .4byte .LASF16 - 834 00b5 02 .byte 0x2 - 835 00b6 F0 .byte 0xf0 - 836 00b7 BB000000 .4byte 0xbb - 837 00bb 05 .uleb128 0x5 - 838 00bc 6F000000 .4byte 0x6f - 839 00c0 04 .uleb128 0x4 - 840 00c1 1C000000 .4byte .LASF17 - 841 00c5 02 .byte 0x2 - 842 00c6 F2 .byte 0xf2 - 843 00c7 CB000000 .4byte 0xcb - 844 00cb 05 .uleb128 0x5 - 845 00cc 85000000 .4byte 0x85 - 846 00d0 02 .uleb128 0x2 - 847 00d1 04 .byte 0x4 - 848 00d2 07 .byte 0x7 - 849 00d3 B9010000 .4byte .LASF18 - 850 00d7 06 .uleb128 0x6 - 851 00d8 01 .byte 0x1 - 852 00d9 22000000 .4byte .LASF19 - 853 00dd 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 26 - - - 854 00de 4E .byte 0x4e - 855 00df 01 .byte 0x1 - 856 00e0 00000000 .4byte .LFB0 - 857 00e4 24000000 .4byte .LFE0 - 858 00e8 00000000 .4byte .LLST0 - 859 00ec 01 .byte 0x1 - 860 00ed 14010000 .4byte 0x114 - 861 00f1 07 .uleb128 0x7 - 862 00f2 A9000000 .4byte .LASF21 - 863 00f6 01 .byte 0x1 - 864 00f7 51 .byte 0x51 - 865 00f8 6F000000 .4byte 0x6f - 866 00fc 20000000 .4byte .LLST1 - 867 0100 08 .uleb128 0x8 - 868 0101 06000000 .4byte .LVL0 - 869 0105 3C040000 .4byte 0x43c - 870 0109 09 .uleb128 0x9 - 871 010a 20000000 .4byte .LVL1 - 872 010e 01 .byte 0x1 - 873 010f 4A040000 .4byte 0x44a - 874 0113 00 .byte 0 - 875 0114 06 .uleb128 0x6 - 876 0115 01 .byte 0x1 - 877 0116 3B000000 .4byte .LASF20 - 878 011a 01 .byte 0x1 - 879 011b 68 .byte 0x68 - 880 011c 01 .byte 0x1 - 881 011d 00000000 .4byte .LFB1 - 882 0121 24000000 .4byte .LFE1 - 883 0125 33000000 .4byte .LLST2 - 884 0129 01 .byte 0x1 - 885 012a 51010000 .4byte 0x151 - 886 012e 07 .uleb128 0x7 - 887 012f A9000000 .4byte .LASF21 - 888 0133 01 .byte 0x1 - 889 0134 6B .byte 0x6b - 890 0135 6F000000 .4byte 0x6f - 891 0139 53000000 .4byte .LLST3 - 892 013d 08 .uleb128 0x8 - 893 013e 06000000 .4byte .LVL2 - 894 0142 3C040000 .4byte 0x43c - 895 0146 09 .uleb128 0x9 - 896 0147 20000000 .4byte .LVL3 - 897 014b 01 .byte 0x1 - 898 014c 4A040000 .4byte 0x44a - 899 0150 00 .byte 0 - 900 0151 0A .uleb128 0xa - 901 0152 01 .byte 0x1 - 902 0153 79000000 .4byte .LASF24 - 903 0157 01 .byte 0x1 - 904 0158 87 .byte 0x87 - 905 0159 01 .byte 0x1 - 906 015a 6F000000 .4byte 0x6f - 907 015e 00000000 .4byte .LFB2 - 908 0162 34000000 .4byte .LFE2 - 909 0166 66000000 .4byte .LLST4 - 910 016a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 27 - - - 911 016b AA010000 .4byte 0x1aa - 912 016f 0B .uleb128 0xb - 913 0170 06020000 .4byte .LASF22 - 914 0174 01 .byte 0x1 - 915 0175 87 .byte 0x87 - 916 0176 AA010000 .4byte 0x1aa - 917 017a 86000000 .4byte .LLST5 - 918 017e 0B .uleb128 0xb - 919 017f 9F000000 .4byte .LASF23 - 920 0183 01 .byte 0x1 - 921 0184 87 .byte 0x87 - 922 0185 6F000000 .4byte 0x6f - 923 0189 A4000000 .4byte .LLST6 - 924 018d 0C .uleb128 0xc - 925 018e 6900 .ascii "i\000" - 926 0190 01 .byte 0x1 - 927 0191 89 .byte 0x89 - 928 0192 6F000000 .4byte 0x6f - 929 0196 C5000000 .4byte .LLST7 - 930 019a 0D .uleb128 0xd - 931 019b 1C000000 .4byte .LVL6 - 932 019f 5E040000 .4byte 0x45e - 933 01a3 0E .uleb128 0xe - 934 01a4 01 .byte 0x1 - 935 01a5 50 .byte 0x50 - 936 01a6 01 .byte 0x1 - 937 01a7 31 .byte 0x31 - 938 01a8 00 .byte 0 - 939 01a9 00 .byte 0 - 940 01aa 0F .uleb128 0xf - 941 01ab 04 .byte 0x4 - 942 01ac 6F000000 .4byte 0x6f - 943 01b0 0A .uleb128 0xa - 944 01b1 01 .byte 0x1 - 945 01b2 00000000 .4byte .LASF25 - 946 01b6 01 .byte 0x1 - 947 01b7 B2 .byte 0xb2 - 948 01b8 01 .byte 0x1 - 949 01b9 A5000000 .4byte 0xa5 - 950 01bd 00000000 .4byte .LFB3 - 951 01c1 74000000 .4byte .LFE3 - 952 01c5 D9000000 .4byte .LLST8 - 953 01c9 01 .byte 0x1 - 954 01ca 23020000 .4byte 0x223 - 955 01ce 0B .uleb128 0xb - 956 01cf 1B010000 .4byte .LASF26 - 957 01d3 01 .byte 0x1 - 958 01d4 B2 .byte 0xb2 - 959 01d5 6F000000 .4byte 0x6f - 960 01d9 F9000000 .4byte .LLST9 - 961 01dd 0B .uleb128 0xb - 962 01de 7F010000 .4byte .LASF27 - 963 01e2 01 .byte 0x1 - 964 01e3 B2 .byte 0xb2 - 965 01e4 7A000000 .4byte 0x7a - 966 01e8 8D010000 .4byte .LLST10 - 967 01ec 10 .uleb128 0x10 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 28 - - - 968 01ed 06020000 .4byte .LASF22 - 969 01f1 01 .byte 0x1 - 970 01f2 B2 .byte 0xb2 - 971 01f3 23020000 .4byte 0x223 - 972 01f7 01 .byte 0x1 - 973 01f8 52 .byte 0x52 - 974 01f9 10 .uleb128 0x10 - 975 01fa 9F000000 .4byte .LASF23 - 976 01fe 01 .byte 0x1 - 977 01ff B2 .byte 0xb2 - 978 0200 6F000000 .4byte 0x6f - 979 0204 01 .byte 0x1 - 980 0205 53 .byte 0x53 - 981 0206 07 .uleb128 0x7 - 982 0207 87000000 .4byte .LASF28 - 983 020b 01 .byte 0x1 - 984 020c B5 .byte 0xb5 - 985 020d A5000000 .4byte 0xa5 - 986 0211 B9010000 .4byte .LLST11 - 987 0215 0C .uleb128 0xc - 988 0216 6900 .ascii "i\000" - 989 0218 01 .byte 0x1 - 990 0219 B6 .byte 0xb6 - 991 021a 6F000000 .4byte 0x6f - 992 021e D8010000 .4byte .LLST12 - 993 0222 00 .byte 0 - 994 0223 0F .uleb128 0xf - 995 0224 04 .byte 0x4 - 996 0225 29020000 .4byte 0x229 - 997 0229 11 .uleb128 0x11 - 998 022a 6F000000 .4byte 0x6f - 999 022e 0A .uleb128 0xa - 1000 022f 01 .byte 0x1 - 1001 0230 AC010000 .4byte .LASF29 - 1002 0234 01 .byte 0x1 - 1003 0235 FD .byte 0xfd - 1004 0236 01 .byte 0x1 - 1005 0237 A5000000 .4byte 0xa5 - 1006 023b 00000000 .4byte .LFB4 - 1007 023f 4C000000 .4byte .LFE4 - 1008 0243 EC010000 .4byte .LLST13 - 1009 0247 01 .byte 0x1 - 1010 0248 8F020000 .4byte 0x28f - 1011 024c 0B .uleb128 0xb - 1012 024d 1B010000 .4byte .LASF26 - 1013 0251 01 .byte 0x1 - 1014 0252 FD .byte 0xfd - 1015 0253 6F000000 .4byte 0x6f - 1016 0257 0C020000 .4byte .LLST14 - 1017 025b 10 .uleb128 0x10 - 1018 025c 06020000 .4byte .LASF22 - 1019 0260 01 .byte 0x1 - 1020 0261 FD .byte 0xfd - 1021 0262 23020000 .4byte 0x223 - 1022 0266 01 .byte 0x1 - 1023 0267 51 .byte 0x51 - 1024 0268 10 .uleb128 0x10 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 29 - - - 1025 0269 9F000000 .4byte .LASF23 - 1026 026d 01 .byte 0x1 - 1027 026e FD .byte 0xfd - 1028 026f 7A000000 .4byte 0x7a - 1029 0273 01 .byte 0x1 - 1030 0274 52 .byte 0x52 - 1031 0275 07 .uleb128 0x7 - 1032 0276 87000000 .4byte .LASF28 - 1033 027a 01 .byte 0x1 - 1034 027b FF .byte 0xff - 1035 027c A5000000 .4byte 0xa5 - 1036 0280 7B020000 .4byte .LLST15 - 1037 0284 12 .uleb128 0x12 - 1038 0285 6900 .ascii "i\000" - 1039 0287 01 .byte 0x1 - 1040 0288 0001 .2byte 0x100 - 1041 028a 7A000000 .4byte 0x7a - 1042 028e 00 .byte 0 - 1043 028f 13 .uleb128 0x13 - 1044 0290 01 .byte 0x1 - 1045 0291 2D000000 .4byte .LASF30 - 1046 0295 01 .byte 0x1 - 1047 0296 3C01 .2byte 0x13c - 1048 0298 01 .byte 0x1 - 1049 0299 A5000000 .4byte 0xa5 - 1050 029d 00000000 .4byte .LFB5 - 1051 02a1 48000000 .4byte .LFE5 - 1052 02a5 9A020000 .4byte .LLST16 - 1053 02a9 01 .byte 0x1 - 1054 02aa FB020000 .4byte 0x2fb - 1055 02ae 14 .uleb128 0x14 - 1056 02af 1B010000 .4byte .LASF26 - 1057 02b3 01 .byte 0x1 - 1058 02b4 3C01 .2byte 0x13c - 1059 02b6 6F000000 .4byte 0x6f - 1060 02ba BA020000 .4byte .LLST17 - 1061 02be 14 .uleb128 0x14 - 1062 02bf 7F010000 .4byte .LASF27 - 1063 02c3 01 .byte 0x1 - 1064 02c4 3C01 .2byte 0x13c - 1065 02c6 7A000000 .4byte 0x7a - 1066 02ca 0B030000 .4byte .LLST18 - 1067 02ce 15 .uleb128 0x15 - 1068 02cf 0E010000 .4byte .LASF31 - 1069 02d3 01 .byte 0x1 - 1070 02d4 3C01 .2byte 0x13c - 1071 02d6 6F000000 .4byte 0x6f - 1072 02da 01 .byte 0x1 - 1073 02db 52 .byte 0x52 - 1074 02dc 15 .uleb128 0x15 - 1075 02dd 9E010000 .4byte .LASF32 - 1076 02e1 01 .byte 0x1 - 1077 02e2 3C01 .2byte 0x13c - 1078 02e4 6F000000 .4byte 0x6f - 1079 02e8 01 .byte 0x1 - 1080 02e9 53 .byte 0x53 - 1081 02ea 16 .uleb128 0x16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 30 - - - 1082 02eb 87000000 .4byte .LASF28 - 1083 02ef 01 .byte 0x1 - 1084 02f0 3F01 .2byte 0x13f - 1085 02f2 A5000000 .4byte 0xa5 - 1086 02f6 37030000 .4byte .LLST19 - 1087 02fa 00 .byte 0 - 1088 02fb 13 .uleb128 0x13 - 1089 02fc 01 .byte 0x1 - 1090 02fd CE010000 .4byte .LASF33 - 1091 0301 01 .byte 0x1 - 1092 0302 7201 .2byte 0x172 - 1093 0304 01 .byte 0x1 - 1094 0305 A5000000 .4byte 0xa5 - 1095 0309 00000000 .4byte .LFB6 - 1096 030d 40000000 .4byte .LFE6 - 1097 0311 56030000 .4byte .LLST20 - 1098 0315 01 .byte 0x1 - 1099 0316 49030000 .4byte 0x349 - 1100 031a 14 .uleb128 0x14 - 1101 031b 1B010000 .4byte .LASF26 - 1102 031f 01 .byte 0x1 - 1103 0320 7201 .2byte 0x172 - 1104 0322 6F000000 .4byte 0x6f - 1105 0326 76030000 .4byte .LLST21 - 1106 032a 15 .uleb128 0x15 - 1107 032b 0D020000 .4byte .LASF34 - 1108 032f 01 .byte 0x1 - 1109 0330 7201 .2byte 0x172 - 1110 0332 6F000000 .4byte 0x6f - 1111 0336 01 .byte 0x1 - 1112 0337 51 .byte 0x51 - 1113 0338 16 .uleb128 0x16 - 1114 0339 87000000 .4byte .LASF28 - 1115 033d 01 .byte 0x1 - 1116 033e 7401 .2byte 0x174 - 1117 0340 A5000000 .4byte 0xa5 - 1118 0344 C7030000 .4byte .LLST22 - 1119 0348 00 .byte 0 - 1120 0349 17 .uleb128 0x17 - 1121 034a 01 .byte 0x1 - 1122 034b 36010000 .4byte .LASF35 - 1123 034f 01 .byte 0x1 - 1124 0350 A901 .2byte 0x1a9 - 1125 0352 01 .byte 0x1 - 1126 0353 A5000000 .4byte 0xa5 - 1127 0357 00000000 .4byte .LFB7 - 1128 035b 3C000000 .4byte .LFE7 - 1129 035f 02 .byte 0x2 - 1130 0360 7D .byte 0x7d - 1131 0361 00 .sleb128 0 - 1132 0362 01 .byte 0x1 - 1133 0363 88030000 .4byte 0x388 - 1134 0367 14 .uleb128 0x14 - 1135 0368 94000000 .4byte .LASF36 - 1136 036c 01 .byte 0x1 - 1137 036d A901 .2byte 0x1a9 - 1138 036f 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 31 - - - 1139 0373 E6030000 .4byte .LLST23 - 1140 0377 16 .uleb128 0x16 - 1141 0378 87000000 .4byte .LASF28 - 1142 037c 01 .byte 0x1 - 1143 037d AB01 .2byte 0x1ab - 1144 037f A5000000 .4byte 0xa5 - 1145 0383 37040000 .4byte .LLST24 - 1146 0387 00 .byte 0 - 1147 0388 13 .uleb128 0x13 - 1148 0389 01 .byte 0x1 - 1149 038a 4A010000 .4byte .LASF37 - 1150 038e 01 .byte 0x1 - 1151 038f D601 .2byte 0x1d6 - 1152 0391 01 .byte 0x1 - 1153 0392 A5000000 .4byte 0xa5 - 1154 0396 00000000 .4byte .LFB8 - 1155 039a 40000000 .4byte .LFE8 - 1156 039e 56040000 .4byte .LLST25 - 1157 03a2 01 .byte 0x1 - 1158 03a3 DA030000 .4byte 0x3da - 1159 03a7 16 .uleb128 0x16 - 1160 03a8 87000000 .4byte .LASF28 - 1161 03ac 01 .byte 0x1 - 1162 03ad D801 .2byte 0x1d8 - 1163 03af A5000000 .4byte 0xa5 - 1164 03b3 76040000 .4byte .LLST26 - 1165 03b7 16 .uleb128 0x16 - 1166 03b8 A9000000 .4byte .LASF21 - 1167 03bc 01 .byte 0x1 - 1168 03bd D901 .2byte 0x1d9 - 1169 03bf 6F000000 .4byte 0x6f - 1170 03c3 AD040000 .4byte .LLST27 - 1171 03c7 08 .uleb128 0x8 - 1172 03c8 06000000 .4byte .LVL48 - 1173 03cc 3C040000 .4byte 0x43c - 1174 03d0 08 .uleb128 0x8 - 1175 03d1 32000000 .4byte .LVL52 - 1176 03d5 4A040000 .4byte 0x44a - 1177 03d9 00 .byte 0 - 1178 03da 18 .uleb128 0x18 - 1179 03db 01 .byte 0x1 - 1180 03dc C2010000 .4byte .LASF38 - 1181 03e0 01 .byte 0x1 - 1182 03e1 0A02 .2byte 0x20a - 1183 03e3 01 .byte 0x1 - 1184 03e4 00000000 .4byte .LFB9 - 1185 03e8 34000000 .4byte .LFE9 - 1186 03ec C0040000 .4byte .LLST28 - 1187 03f0 01 .byte 0x1 - 1188 03f1 19040000 .4byte 0x419 - 1189 03f5 16 .uleb128 0x16 - 1190 03f6 A9000000 .4byte .LASF21 - 1191 03fa 01 .byte 0x1 - 1192 03fb 0C02 .2byte 0x20c - 1193 03fd 6F000000 .4byte 0x6f - 1194 0401 E0040000 .4byte .LLST29 - 1195 0405 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 32 - - - 1196 0406 06000000 .4byte .LVL53 - 1197 040a 3C040000 .4byte 0x43c - 1198 040e 09 .uleb128 0x9 - 1199 040f 2C000000 .4byte .LVL54 - 1200 0413 01 .byte 0x1 - 1201 0414 4A040000 .4byte 0x44a - 1202 0418 00 .byte 0 - 1203 0419 19 .uleb128 0x19 - 1204 041a 39020000 .4byte .LASF39 - 1205 041e 01 .byte 0x1 - 1206 041f 3C .byte 0x3c - 1207 0420 85000000 .4byte 0x85 - 1208 0424 05 .byte 0x5 - 1209 0425 03 .byte 0x3 - 1210 0426 04000000 .4byte spcWaitPipeBypass - 1211 042a 1A .uleb128 0x1a - 1212 042b 01010000 .4byte .LASF43 - 1213 042f 01 .byte 0x1 - 1214 0430 30 .byte 0x30 - 1215 0431 6F000000 .4byte 0x6f - 1216 0435 01 .byte 0x1 - 1217 0436 05 .byte 0x5 - 1218 0437 03 .byte 0x3 - 1219 0438 00000000 .4byte SpcLockState - 1220 043c 1B .uleb128 0x1b - 1221 043d 01 .byte 0x1 - 1222 043e 5B010000 .4byte .LASF44 - 1223 0442 03 .byte 0x3 - 1224 0443 7E .byte 0x7e - 1225 0444 01 .byte 0x1 - 1226 0445 6F000000 .4byte 0x6f - 1227 0449 01 .byte 0x1 - 1228 044a 1C .uleb128 0x1c - 1229 044b 01 .byte 0x1 - 1230 044c 1A020000 .4byte .LASF45 - 1231 0450 03 .byte 0x3 - 1232 0451 7F .byte 0x7f - 1233 0452 01 .byte 0x1 - 1234 0453 01 .byte 0x1 - 1235 0454 5E040000 .4byte 0x45e - 1236 0458 1D .uleb128 0x1d - 1237 0459 6F000000 .4byte 0x6f - 1238 045d 00 .byte 0 - 1239 045e 1E .uleb128 0x1e - 1240 045f 01 .byte 0x1 - 1241 0460 ED010000 .4byte .LASF46 - 1242 0464 03 .byte 0x3 - 1243 0465 78 .byte 0x78 - 1244 0466 01 .byte 0x1 - 1245 0467 01 .byte 0x1 - 1246 0468 1D .uleb128 0x1d - 1247 0469 7A000000 .4byte 0x7a - 1248 046d 00 .byte 0 - 1249 046e 00 .byte 0 - 1250 .section .debug_abbrev,"",%progbits - 1251 .Ldebug_abbrev0: - 1252 0000 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 33 - - - 1253 0001 11 .uleb128 0x11 - 1254 0002 01 .byte 0x1 - 1255 0003 25 .uleb128 0x25 - 1256 0004 0E .uleb128 0xe - 1257 0005 13 .uleb128 0x13 - 1258 0006 0B .uleb128 0xb - 1259 0007 03 .uleb128 0x3 - 1260 0008 0E .uleb128 0xe - 1261 0009 1B .uleb128 0x1b - 1262 000a 0E .uleb128 0xe - 1263 000b 55 .uleb128 0x55 - 1264 000c 06 .uleb128 0x6 - 1265 000d 11 .uleb128 0x11 - 1266 000e 01 .uleb128 0x1 - 1267 000f 52 .uleb128 0x52 - 1268 0010 01 .uleb128 0x1 - 1269 0011 10 .uleb128 0x10 - 1270 0012 06 .uleb128 0x6 - 1271 0013 00 .byte 0 - 1272 0014 00 .byte 0 - 1273 0015 02 .uleb128 0x2 - 1274 0016 24 .uleb128 0x24 - 1275 0017 00 .byte 0 - 1276 0018 0B .uleb128 0xb - 1277 0019 0B .uleb128 0xb - 1278 001a 3E .uleb128 0x3e - 1279 001b 0B .uleb128 0xb - 1280 001c 03 .uleb128 0x3 - 1281 001d 0E .uleb128 0xe - 1282 001e 00 .byte 0 - 1283 001f 00 .byte 0 - 1284 0020 03 .uleb128 0x3 - 1285 0021 24 .uleb128 0x24 - 1286 0022 00 .byte 0 - 1287 0023 0B .uleb128 0xb - 1288 0024 0B .uleb128 0xb - 1289 0025 3E .uleb128 0x3e - 1290 0026 0B .uleb128 0xb - 1291 0027 03 .uleb128 0x3 - 1292 0028 08 .uleb128 0x8 - 1293 0029 00 .byte 0 - 1294 002a 00 .byte 0 - 1295 002b 04 .uleb128 0x4 - 1296 002c 16 .uleb128 0x16 - 1297 002d 00 .byte 0 - 1298 002e 03 .uleb128 0x3 - 1299 002f 0E .uleb128 0xe - 1300 0030 3A .uleb128 0x3a - 1301 0031 0B .uleb128 0xb - 1302 0032 3B .uleb128 0x3b - 1303 0033 0B .uleb128 0xb - 1304 0034 49 .uleb128 0x49 - 1305 0035 13 .uleb128 0x13 - 1306 0036 00 .byte 0 - 1307 0037 00 .byte 0 - 1308 0038 05 .uleb128 0x5 - 1309 0039 35 .uleb128 0x35 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 34 - - - 1310 003a 00 .byte 0 - 1311 003b 49 .uleb128 0x49 - 1312 003c 13 .uleb128 0x13 - 1313 003d 00 .byte 0 - 1314 003e 00 .byte 0 - 1315 003f 06 .uleb128 0x6 - 1316 0040 2E .uleb128 0x2e - 1317 0041 01 .byte 0x1 - 1318 0042 3F .uleb128 0x3f - 1319 0043 0C .uleb128 0xc - 1320 0044 03 .uleb128 0x3 - 1321 0045 0E .uleb128 0xe - 1322 0046 3A .uleb128 0x3a - 1323 0047 0B .uleb128 0xb - 1324 0048 3B .uleb128 0x3b - 1325 0049 0B .uleb128 0xb - 1326 004a 27 .uleb128 0x27 - 1327 004b 0C .uleb128 0xc - 1328 004c 11 .uleb128 0x11 - 1329 004d 01 .uleb128 0x1 - 1330 004e 12 .uleb128 0x12 - 1331 004f 01 .uleb128 0x1 - 1332 0050 40 .uleb128 0x40 - 1333 0051 06 .uleb128 0x6 - 1334 0052 9742 .uleb128 0x2117 - 1335 0054 0C .uleb128 0xc - 1336 0055 01 .uleb128 0x1 - 1337 0056 13 .uleb128 0x13 - 1338 0057 00 .byte 0 - 1339 0058 00 .byte 0 - 1340 0059 07 .uleb128 0x7 - 1341 005a 34 .uleb128 0x34 - 1342 005b 00 .byte 0 - 1343 005c 03 .uleb128 0x3 - 1344 005d 0E .uleb128 0xe - 1345 005e 3A .uleb128 0x3a - 1346 005f 0B .uleb128 0xb - 1347 0060 3B .uleb128 0x3b - 1348 0061 0B .uleb128 0xb - 1349 0062 49 .uleb128 0x49 - 1350 0063 13 .uleb128 0x13 - 1351 0064 02 .uleb128 0x2 - 1352 0065 06 .uleb128 0x6 - 1353 0066 00 .byte 0 - 1354 0067 00 .byte 0 - 1355 0068 08 .uleb128 0x8 - 1356 0069 898201 .uleb128 0x4109 - 1357 006c 00 .byte 0 - 1358 006d 11 .uleb128 0x11 - 1359 006e 01 .uleb128 0x1 - 1360 006f 31 .uleb128 0x31 - 1361 0070 13 .uleb128 0x13 - 1362 0071 00 .byte 0 - 1363 0072 00 .byte 0 - 1364 0073 09 .uleb128 0x9 - 1365 0074 898201 .uleb128 0x4109 - 1366 0077 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 35 - - - 1367 0078 11 .uleb128 0x11 - 1368 0079 01 .uleb128 0x1 - 1369 007a 9542 .uleb128 0x2115 - 1370 007c 0C .uleb128 0xc - 1371 007d 31 .uleb128 0x31 - 1372 007e 13 .uleb128 0x13 - 1373 007f 00 .byte 0 - 1374 0080 00 .byte 0 - 1375 0081 0A .uleb128 0xa - 1376 0082 2E .uleb128 0x2e - 1377 0083 01 .byte 0x1 - 1378 0084 3F .uleb128 0x3f - 1379 0085 0C .uleb128 0xc - 1380 0086 03 .uleb128 0x3 - 1381 0087 0E .uleb128 0xe - 1382 0088 3A .uleb128 0x3a - 1383 0089 0B .uleb128 0xb - 1384 008a 3B .uleb128 0x3b - 1385 008b 0B .uleb128 0xb - 1386 008c 27 .uleb128 0x27 - 1387 008d 0C .uleb128 0xc - 1388 008e 49 .uleb128 0x49 - 1389 008f 13 .uleb128 0x13 - 1390 0090 11 .uleb128 0x11 - 1391 0091 01 .uleb128 0x1 - 1392 0092 12 .uleb128 0x12 - 1393 0093 01 .uleb128 0x1 - 1394 0094 40 .uleb128 0x40 - 1395 0095 06 .uleb128 0x6 - 1396 0096 9742 .uleb128 0x2117 - 1397 0098 0C .uleb128 0xc - 1398 0099 01 .uleb128 0x1 - 1399 009a 13 .uleb128 0x13 - 1400 009b 00 .byte 0 - 1401 009c 00 .byte 0 - 1402 009d 0B .uleb128 0xb - 1403 009e 05 .uleb128 0x5 - 1404 009f 00 .byte 0 - 1405 00a0 03 .uleb128 0x3 - 1406 00a1 0E .uleb128 0xe - 1407 00a2 3A .uleb128 0x3a - 1408 00a3 0B .uleb128 0xb - 1409 00a4 3B .uleb128 0x3b - 1410 00a5 0B .uleb128 0xb - 1411 00a6 49 .uleb128 0x49 - 1412 00a7 13 .uleb128 0x13 - 1413 00a8 02 .uleb128 0x2 - 1414 00a9 06 .uleb128 0x6 - 1415 00aa 00 .byte 0 - 1416 00ab 00 .byte 0 - 1417 00ac 0C .uleb128 0xc - 1418 00ad 34 .uleb128 0x34 - 1419 00ae 00 .byte 0 - 1420 00af 03 .uleb128 0x3 - 1421 00b0 08 .uleb128 0x8 - 1422 00b1 3A .uleb128 0x3a - 1423 00b2 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 36 - - - 1424 00b3 3B .uleb128 0x3b - 1425 00b4 0B .uleb128 0xb - 1426 00b5 49 .uleb128 0x49 - 1427 00b6 13 .uleb128 0x13 - 1428 00b7 02 .uleb128 0x2 - 1429 00b8 06 .uleb128 0x6 - 1430 00b9 00 .byte 0 - 1431 00ba 00 .byte 0 - 1432 00bb 0D .uleb128 0xd - 1433 00bc 898201 .uleb128 0x4109 - 1434 00bf 01 .byte 0x1 - 1435 00c0 11 .uleb128 0x11 - 1436 00c1 01 .uleb128 0x1 - 1437 00c2 31 .uleb128 0x31 - 1438 00c3 13 .uleb128 0x13 - 1439 00c4 00 .byte 0 - 1440 00c5 00 .byte 0 - 1441 00c6 0E .uleb128 0xe - 1442 00c7 8A8201 .uleb128 0x410a - 1443 00ca 00 .byte 0 - 1444 00cb 02 .uleb128 0x2 - 1445 00cc 0A .uleb128 0xa - 1446 00cd 9142 .uleb128 0x2111 - 1447 00cf 0A .uleb128 0xa - 1448 00d0 00 .byte 0 - 1449 00d1 00 .byte 0 - 1450 00d2 0F .uleb128 0xf - 1451 00d3 0F .uleb128 0xf - 1452 00d4 00 .byte 0 - 1453 00d5 0B .uleb128 0xb - 1454 00d6 0B .uleb128 0xb - 1455 00d7 49 .uleb128 0x49 - 1456 00d8 13 .uleb128 0x13 - 1457 00d9 00 .byte 0 - 1458 00da 00 .byte 0 - 1459 00db 10 .uleb128 0x10 - 1460 00dc 05 .uleb128 0x5 - 1461 00dd 00 .byte 0 - 1462 00de 03 .uleb128 0x3 - 1463 00df 0E .uleb128 0xe - 1464 00e0 3A .uleb128 0x3a - 1465 00e1 0B .uleb128 0xb - 1466 00e2 3B .uleb128 0x3b - 1467 00e3 0B .uleb128 0xb - 1468 00e4 49 .uleb128 0x49 - 1469 00e5 13 .uleb128 0x13 - 1470 00e6 02 .uleb128 0x2 - 1471 00e7 0A .uleb128 0xa - 1472 00e8 00 .byte 0 - 1473 00e9 00 .byte 0 - 1474 00ea 11 .uleb128 0x11 - 1475 00eb 26 .uleb128 0x26 - 1476 00ec 00 .byte 0 - 1477 00ed 49 .uleb128 0x49 - 1478 00ee 13 .uleb128 0x13 - 1479 00ef 00 .byte 0 - 1480 00f0 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 37 - - - 1481 00f1 12 .uleb128 0x12 - 1482 00f2 34 .uleb128 0x34 - 1483 00f3 00 .byte 0 - 1484 00f4 03 .uleb128 0x3 - 1485 00f5 08 .uleb128 0x8 - 1486 00f6 3A .uleb128 0x3a - 1487 00f7 0B .uleb128 0xb - 1488 00f8 3B .uleb128 0x3b - 1489 00f9 05 .uleb128 0x5 - 1490 00fa 49 .uleb128 0x49 - 1491 00fb 13 .uleb128 0x13 - 1492 00fc 00 .byte 0 - 1493 00fd 00 .byte 0 - 1494 00fe 13 .uleb128 0x13 - 1495 00ff 2E .uleb128 0x2e - 1496 0100 01 .byte 0x1 - 1497 0101 3F .uleb128 0x3f - 1498 0102 0C .uleb128 0xc - 1499 0103 03 .uleb128 0x3 - 1500 0104 0E .uleb128 0xe - 1501 0105 3A .uleb128 0x3a - 1502 0106 0B .uleb128 0xb - 1503 0107 3B .uleb128 0x3b - 1504 0108 05 .uleb128 0x5 - 1505 0109 27 .uleb128 0x27 - 1506 010a 0C .uleb128 0xc - 1507 010b 49 .uleb128 0x49 - 1508 010c 13 .uleb128 0x13 - 1509 010d 11 .uleb128 0x11 - 1510 010e 01 .uleb128 0x1 - 1511 010f 12 .uleb128 0x12 - 1512 0110 01 .uleb128 0x1 - 1513 0111 40 .uleb128 0x40 - 1514 0112 06 .uleb128 0x6 - 1515 0113 9742 .uleb128 0x2117 - 1516 0115 0C .uleb128 0xc - 1517 0116 01 .uleb128 0x1 - 1518 0117 13 .uleb128 0x13 - 1519 0118 00 .byte 0 - 1520 0119 00 .byte 0 - 1521 011a 14 .uleb128 0x14 - 1522 011b 05 .uleb128 0x5 - 1523 011c 00 .byte 0 - 1524 011d 03 .uleb128 0x3 - 1525 011e 0E .uleb128 0xe - 1526 011f 3A .uleb128 0x3a - 1527 0120 0B .uleb128 0xb - 1528 0121 3B .uleb128 0x3b - 1529 0122 05 .uleb128 0x5 - 1530 0123 49 .uleb128 0x49 - 1531 0124 13 .uleb128 0x13 - 1532 0125 02 .uleb128 0x2 - 1533 0126 06 .uleb128 0x6 - 1534 0127 00 .byte 0 - 1535 0128 00 .byte 0 - 1536 0129 15 .uleb128 0x15 - 1537 012a 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 38 - - - 1538 012b 00 .byte 0 - 1539 012c 03 .uleb128 0x3 - 1540 012d 0E .uleb128 0xe - 1541 012e 3A .uleb128 0x3a - 1542 012f 0B .uleb128 0xb - 1543 0130 3B .uleb128 0x3b - 1544 0131 05 .uleb128 0x5 - 1545 0132 49 .uleb128 0x49 - 1546 0133 13 .uleb128 0x13 - 1547 0134 02 .uleb128 0x2 - 1548 0135 0A .uleb128 0xa - 1549 0136 00 .byte 0 - 1550 0137 00 .byte 0 - 1551 0138 16 .uleb128 0x16 - 1552 0139 34 .uleb128 0x34 - 1553 013a 00 .byte 0 - 1554 013b 03 .uleb128 0x3 - 1555 013c 0E .uleb128 0xe - 1556 013d 3A .uleb128 0x3a - 1557 013e 0B .uleb128 0xb - 1558 013f 3B .uleb128 0x3b - 1559 0140 05 .uleb128 0x5 - 1560 0141 49 .uleb128 0x49 - 1561 0142 13 .uleb128 0x13 - 1562 0143 02 .uleb128 0x2 - 1563 0144 06 .uleb128 0x6 - 1564 0145 00 .byte 0 - 1565 0146 00 .byte 0 - 1566 0147 17 .uleb128 0x17 - 1567 0148 2E .uleb128 0x2e - 1568 0149 01 .byte 0x1 - 1569 014a 3F .uleb128 0x3f - 1570 014b 0C .uleb128 0xc - 1571 014c 03 .uleb128 0x3 - 1572 014d 0E .uleb128 0xe - 1573 014e 3A .uleb128 0x3a - 1574 014f 0B .uleb128 0xb - 1575 0150 3B .uleb128 0x3b - 1576 0151 05 .uleb128 0x5 - 1577 0152 27 .uleb128 0x27 - 1578 0153 0C .uleb128 0xc - 1579 0154 49 .uleb128 0x49 - 1580 0155 13 .uleb128 0x13 - 1581 0156 11 .uleb128 0x11 - 1582 0157 01 .uleb128 0x1 - 1583 0158 12 .uleb128 0x12 - 1584 0159 01 .uleb128 0x1 - 1585 015a 40 .uleb128 0x40 - 1586 015b 0A .uleb128 0xa - 1587 015c 9742 .uleb128 0x2117 - 1588 015e 0C .uleb128 0xc - 1589 015f 01 .uleb128 0x1 - 1590 0160 13 .uleb128 0x13 - 1591 0161 00 .byte 0 - 1592 0162 00 .byte 0 - 1593 0163 18 .uleb128 0x18 - 1594 0164 2E .uleb128 0x2e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 39 - - - 1595 0165 01 .byte 0x1 - 1596 0166 3F .uleb128 0x3f - 1597 0167 0C .uleb128 0xc - 1598 0168 03 .uleb128 0x3 - 1599 0169 0E .uleb128 0xe - 1600 016a 3A .uleb128 0x3a - 1601 016b 0B .uleb128 0xb - 1602 016c 3B .uleb128 0x3b - 1603 016d 05 .uleb128 0x5 - 1604 016e 27 .uleb128 0x27 - 1605 016f 0C .uleb128 0xc - 1606 0170 11 .uleb128 0x11 - 1607 0171 01 .uleb128 0x1 - 1608 0172 12 .uleb128 0x12 - 1609 0173 01 .uleb128 0x1 - 1610 0174 40 .uleb128 0x40 - 1611 0175 06 .uleb128 0x6 - 1612 0176 9742 .uleb128 0x2117 - 1613 0178 0C .uleb128 0xc - 1614 0179 01 .uleb128 0x1 - 1615 017a 13 .uleb128 0x13 - 1616 017b 00 .byte 0 - 1617 017c 00 .byte 0 - 1618 017d 19 .uleb128 0x19 - 1619 017e 34 .uleb128 0x34 - 1620 017f 00 .byte 0 - 1621 0180 03 .uleb128 0x3 - 1622 0181 0E .uleb128 0xe - 1623 0182 3A .uleb128 0x3a - 1624 0183 0B .uleb128 0xb - 1625 0184 3B .uleb128 0x3b - 1626 0185 0B .uleb128 0xb - 1627 0186 49 .uleb128 0x49 - 1628 0187 13 .uleb128 0x13 - 1629 0188 02 .uleb128 0x2 - 1630 0189 0A .uleb128 0xa - 1631 018a 00 .byte 0 - 1632 018b 00 .byte 0 - 1633 018c 1A .uleb128 0x1a - 1634 018d 34 .uleb128 0x34 - 1635 018e 00 .byte 0 - 1636 018f 03 .uleb128 0x3 - 1637 0190 0E .uleb128 0xe - 1638 0191 3A .uleb128 0x3a - 1639 0192 0B .uleb128 0xb - 1640 0193 3B .uleb128 0x3b - 1641 0194 0B .uleb128 0xb - 1642 0195 49 .uleb128 0x49 - 1643 0196 13 .uleb128 0x13 - 1644 0197 3F .uleb128 0x3f - 1645 0198 0C .uleb128 0xc - 1646 0199 02 .uleb128 0x2 - 1647 019a 0A .uleb128 0xa - 1648 019b 00 .byte 0 - 1649 019c 00 .byte 0 - 1650 019d 1B .uleb128 0x1b - 1651 019e 2E .uleb128 0x2e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 40 - - - 1652 019f 00 .byte 0 - 1653 01a0 3F .uleb128 0x3f - 1654 01a1 0C .uleb128 0xc - 1655 01a2 03 .uleb128 0x3 - 1656 01a3 0E .uleb128 0xe - 1657 01a4 3A .uleb128 0x3a - 1658 01a5 0B .uleb128 0xb - 1659 01a6 3B .uleb128 0x3b - 1660 01a7 0B .uleb128 0xb - 1661 01a8 27 .uleb128 0x27 - 1662 01a9 0C .uleb128 0xc - 1663 01aa 49 .uleb128 0x49 - 1664 01ab 13 .uleb128 0x13 - 1665 01ac 3C .uleb128 0x3c - 1666 01ad 0C .uleb128 0xc - 1667 01ae 00 .byte 0 - 1668 01af 00 .byte 0 - 1669 01b0 1C .uleb128 0x1c - 1670 01b1 2E .uleb128 0x2e - 1671 01b2 01 .byte 0x1 - 1672 01b3 3F .uleb128 0x3f - 1673 01b4 0C .uleb128 0xc - 1674 01b5 03 .uleb128 0x3 - 1675 01b6 0E .uleb128 0xe - 1676 01b7 3A .uleb128 0x3a - 1677 01b8 0B .uleb128 0xb - 1678 01b9 3B .uleb128 0x3b - 1679 01ba 0B .uleb128 0xb - 1680 01bb 27 .uleb128 0x27 - 1681 01bc 0C .uleb128 0xc - 1682 01bd 3C .uleb128 0x3c - 1683 01be 0C .uleb128 0xc - 1684 01bf 01 .uleb128 0x1 - 1685 01c0 13 .uleb128 0x13 - 1686 01c1 00 .byte 0 - 1687 01c2 00 .byte 0 - 1688 01c3 1D .uleb128 0x1d - 1689 01c4 05 .uleb128 0x5 - 1690 01c5 00 .byte 0 - 1691 01c6 49 .uleb128 0x49 - 1692 01c7 13 .uleb128 0x13 - 1693 01c8 00 .byte 0 - 1694 01c9 00 .byte 0 - 1695 01ca 1E .uleb128 0x1e - 1696 01cb 2E .uleb128 0x2e - 1697 01cc 01 .byte 0x1 - 1698 01cd 3F .uleb128 0x3f - 1699 01ce 0C .uleb128 0xc - 1700 01cf 03 .uleb128 0x3 - 1701 01d0 0E .uleb128 0xe - 1702 01d1 3A .uleb128 0x3a - 1703 01d2 0B .uleb128 0xb - 1704 01d3 3B .uleb128 0x3b - 1705 01d4 0B .uleb128 0xb - 1706 01d5 27 .uleb128 0x27 - 1707 01d6 0C .uleb128 0xc - 1708 01d7 3C .uleb128 0x3c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 41 - - - 1709 01d8 0C .uleb128 0xc - 1710 01d9 00 .byte 0 - 1711 01da 00 .byte 0 - 1712 01db 00 .byte 0 - 1713 .section .debug_loc,"",%progbits - 1714 .Ldebug_loc0: - 1715 .LLST0: - 1716 0000 00000000 .4byte .LFB0 - 1717 0004 02000000 .4byte .LCFI0 - 1718 0008 0200 .2byte 0x2 - 1719 000a 7D .byte 0x7d - 1720 000b 00 .sleb128 0 - 1721 000c 02000000 .4byte .LCFI0 - 1722 0010 24000000 .4byte .LFE0 - 1723 0014 0200 .2byte 0x2 - 1724 0016 7D .byte 0x7d - 1725 0017 08 .sleb128 8 - 1726 0018 00000000 .4byte 0 - 1727 001c 00000000 .4byte 0 - 1728 .LLST1: - 1729 0020 06000000 .4byte .LVL0 - 1730 0024 1F000000 .4byte .LVL1-1 - 1731 0028 0100 .2byte 0x1 - 1732 002a 50 .byte 0x50 - 1733 002b 00000000 .4byte 0 - 1734 002f 00000000 .4byte 0 - 1735 .LLST2: - 1736 0033 00000000 .4byte .LFB1 - 1737 0037 02000000 .4byte .LCFI1 - 1738 003b 0200 .2byte 0x2 - 1739 003d 7D .byte 0x7d - 1740 003e 00 .sleb128 0 - 1741 003f 02000000 .4byte .LCFI1 - 1742 0043 24000000 .4byte .LFE1 - 1743 0047 0200 .2byte 0x2 - 1744 0049 7D .byte 0x7d - 1745 004a 08 .sleb128 8 - 1746 004b 00000000 .4byte 0 - 1747 004f 00000000 .4byte 0 - 1748 .LLST3: - 1749 0053 06000000 .4byte .LVL2 - 1750 0057 1F000000 .4byte .LVL3-1 - 1751 005b 0100 .2byte 0x1 - 1752 005d 50 .byte 0x50 - 1753 005e 00000000 .4byte 0 - 1754 0062 00000000 .4byte 0 - 1755 .LLST4: - 1756 0066 00000000 .4byte .LFB2 - 1757 006a 02000000 .4byte .LCFI2 - 1758 006e 0200 .2byte 0x2 - 1759 0070 7D .byte 0x7d - 1760 0071 00 .sleb128 0 - 1761 0072 02000000 .4byte .LCFI2 - 1762 0076 34000000 .4byte .LFE2 - 1763 007a 0200 .2byte 0x2 - 1764 007c 7D .byte 0x7d - 1765 007d 10 .sleb128 16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 42 - - - 1766 007e 00000000 .4byte 0 - 1767 0082 00000000 .4byte 0 - 1768 .LLST5: - 1769 0086 00000000 .4byte .LVL4 - 1770 008a 08000000 .4byte .LVL5 - 1771 008e 0100 .2byte 0x1 - 1772 0090 50 .byte 0x50 - 1773 0091 08000000 .4byte .LVL5 - 1774 0095 34000000 .4byte .LFE2 - 1775 0099 0100 .2byte 0x1 - 1776 009b 56 .byte 0x56 - 1777 009c 00000000 .4byte 0 - 1778 00a0 00000000 .4byte 0 - 1779 .LLST6: - 1780 00a4 00000000 .4byte .LVL4 - 1781 00a8 08000000 .4byte .LVL5 - 1782 00ac 0100 .2byte 0x1 - 1783 00ae 51 .byte 0x51 - 1784 00af 08000000 .4byte .LVL5 - 1785 00b3 34000000 .4byte .LFE2 - 1786 00b7 0400 .2byte 0x4 - 1787 00b9 F3 .byte 0xf3 - 1788 00ba 01 .uleb128 0x1 - 1789 00bb 51 .byte 0x51 - 1790 00bc 9F .byte 0x9f - 1791 00bd 00000000 .4byte 0 - 1792 00c1 00000000 .4byte 0 - 1793 .LLST7: - 1794 00c5 00000000 .4byte .LVL4 - 1795 00c9 08000000 .4byte .LVL5 - 1796 00cd 0200 .2byte 0x2 - 1797 00cf 30 .byte 0x30 - 1798 00d0 9F .byte 0x9f - 1799 00d1 00000000 .4byte 0 - 1800 00d5 00000000 .4byte 0 - 1801 .LLST8: - 1802 00d9 00000000 .4byte .LFB3 - 1803 00dd 04000000 .4byte .LCFI3 - 1804 00e1 0200 .2byte 0x2 - 1805 00e3 7D .byte 0x7d - 1806 00e4 00 .sleb128 0 - 1807 00e5 04000000 .4byte .LCFI3 - 1808 00e9 74000000 .4byte .LFE3 - 1809 00ed 0200 .2byte 0x2 - 1810 00ef 7D .byte 0x7d - 1811 00f0 10 .sleb128 16 - 1812 00f1 00000000 .4byte 0 - 1813 00f5 00000000 .4byte 0 - 1814 .LLST9: - 1815 00f9 00000000 .4byte .LVL7 - 1816 00fd 3C000000 .4byte .LVL8 - 1817 0101 0100 .2byte 0x1 - 1818 0103 50 .byte 0x50 - 1819 0104 3C000000 .4byte .LVL8 - 1820 0108 4A000000 .4byte .LVL11 - 1821 010c 0200 .2byte 0x2 - 1822 010e 74 .byte 0x74 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 43 - - - 1823 010f 00 .sleb128 0 - 1824 0110 4A000000 .4byte .LVL11 - 1825 0114 54000000 .4byte .LVL12 - 1826 0118 0500 .2byte 0x5 - 1827 011a 0C .byte 0xc - 1828 011b 20470040 .4byte 0x40004720 - 1829 011f 54000000 .4byte .LVL12 - 1830 0123 5A000000 .4byte .LVL13 - 1831 0127 0200 .2byte 0x2 - 1832 0129 70 .byte 0x70 - 1833 012a 00 .sleb128 0 - 1834 012b 5A000000 .4byte .LVL13 - 1835 012f 5E000000 .4byte .LVL14 - 1836 0133 0500 .2byte 0x5 - 1837 0135 0C .byte 0xc - 1838 0136 20470040 .4byte 0x40004720 - 1839 013a 5E000000 .4byte .LVL14 - 1840 013e 60000000 .4byte .LVL15 - 1841 0142 0100 .2byte 0x1 - 1842 0144 50 .byte 0x50 - 1843 0145 60000000 .4byte .LVL15 - 1844 0149 62000000 .4byte .LVL16 - 1845 014d 0400 .2byte 0x4 - 1846 014f F3 .byte 0xf3 - 1847 0150 01 .uleb128 0x1 - 1848 0151 50 .byte 0x50 - 1849 0152 9F .byte 0x9f - 1850 0153 62000000 .4byte .LVL16 - 1851 0157 64000000 .4byte .LVL17 - 1852 015b 0100 .2byte 0x1 - 1853 015d 50 .byte 0x50 - 1854 015e 64000000 .4byte .LVL17 - 1855 0162 66000000 .4byte .LVL18 - 1856 0166 0400 .2byte 0x4 - 1857 0168 F3 .byte 0xf3 - 1858 0169 01 .uleb128 0x1 - 1859 016a 50 .byte 0x50 - 1860 016b 9F .byte 0x9f - 1861 016c 66000000 .4byte .LVL18 - 1862 0170 68000000 .4byte .LVL19 - 1863 0174 0100 .2byte 0x1 - 1864 0176 50 .byte 0x50 - 1865 0177 68000000 .4byte .LVL19 - 1866 017b 74000000 .4byte .LFE3 - 1867 017f 0400 .2byte 0x4 - 1868 0181 F3 .byte 0xf3 - 1869 0182 01 .uleb128 0x1 - 1870 0183 50 .byte 0x50 - 1871 0184 9F .byte 0x9f - 1872 0185 00000000 .4byte 0 - 1873 0189 00000000 .4byte 0 - 1874 .LLST10: - 1875 018d 00000000 .4byte .LVL7 - 1876 0191 40000000 .4byte .LVL9 - 1877 0195 0100 .2byte 0x1 - 1878 0197 51 .byte 0x51 - 1879 0198 40000000 .4byte .LVL9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 44 - - - 1880 019c 5E000000 .4byte .LVL14 - 1881 01a0 0400 .2byte 0x4 - 1882 01a2 F3 .byte 0xf3 - 1883 01a3 01 .uleb128 0x1 - 1884 01a4 51 .byte 0x51 - 1885 01a5 9F .byte 0x9f - 1886 01a6 5E000000 .4byte .LVL14 - 1887 01aa 74000000 .4byte .LFE3 - 1888 01ae 0100 .2byte 0x1 - 1889 01b0 51 .byte 0x51 - 1890 01b1 00000000 .4byte 0 - 1891 01b5 00000000 .4byte 0 - 1892 .LLST11: - 1893 01b9 00000000 .4byte .LVL7 - 1894 01bd 68000000 .4byte .LVL19 - 1895 01c1 0200 .2byte 0x2 - 1896 01c3 37 .byte 0x37 - 1897 01c4 9F .byte 0x9f - 1898 01c5 68000000 .4byte .LVL19 - 1899 01c9 74000000 .4byte .LFE3 - 1900 01cd 0100 .2byte 0x1 - 1901 01cf 50 .byte 0x50 - 1902 01d0 00000000 .4byte 0 - 1903 01d4 00000000 .4byte 0 - 1904 .LLST12: - 1905 01d8 48000000 .4byte .LVL10 - 1906 01dc 4A000000 .4byte .LVL11 - 1907 01e0 0200 .2byte 0x2 - 1908 01e2 30 .byte 0x30 - 1909 01e3 9F .byte 0x9f - 1910 01e4 00000000 .4byte 0 - 1911 01e8 00000000 .4byte 0 - 1912 .LLST13: - 1913 01ec 00000000 .4byte .LFB4 - 1914 01f0 02000000 .4byte .LCFI4 - 1915 01f4 0200 .2byte 0x2 - 1916 01f6 7D .byte 0x7d - 1917 01f7 00 .sleb128 0 - 1918 01f8 02000000 .4byte .LCFI4 - 1919 01fc 4C000000 .4byte .LFE4 - 1920 0200 0200 .2byte 0x2 - 1921 0202 7D .byte 0x7d - 1922 0203 0C .sleb128 12 - 1923 0204 00000000 .4byte 0 - 1924 0208 00000000 .4byte 0 - 1925 .LLST14: - 1926 020c 00000000 .4byte .LVL20 - 1927 0210 26000000 .4byte .LVL21 - 1928 0214 0100 .2byte 0x1 - 1929 0216 50 .byte 0x50 - 1930 0217 26000000 .4byte .LVL21 - 1931 021b 30000000 .4byte .LVL22 - 1932 021f 0500 .2byte 0x5 - 1933 0221 0C .byte 0xc - 1934 0222 20470040 .4byte 0x40004720 - 1935 0226 30000000 .4byte .LVL22 - 1936 022a 36000000 .4byte .LVL23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 45 - - - 1937 022e 0200 .2byte 0x2 - 1938 0230 70 .byte 0x70 - 1939 0231 00 .sleb128 0 - 1940 0232 36000000 .4byte .LVL23 - 1941 0236 3A000000 .4byte .LVL24 - 1942 023a 0500 .2byte 0x5 - 1943 023c 0C .byte 0xc - 1944 023d 20470040 .4byte 0x40004720 - 1945 0241 3A000000 .4byte .LVL24 - 1946 0245 3C000000 .4byte .LVL25 - 1947 0249 0100 .2byte 0x1 - 1948 024b 50 .byte 0x50 - 1949 024c 3C000000 .4byte .LVL25 - 1950 0250 3E000000 .4byte .LVL26 - 1951 0254 0400 .2byte 0x4 - 1952 0256 F3 .byte 0xf3 - 1953 0257 01 .uleb128 0x1 - 1954 0258 50 .byte 0x50 - 1955 0259 9F .byte 0x9f - 1956 025a 3E000000 .4byte .LVL26 - 1957 025e 40000000 .4byte .LVL27 - 1958 0262 0100 .2byte 0x1 - 1959 0264 50 .byte 0x50 - 1960 0265 40000000 .4byte .LVL27 - 1961 0269 4C000000 .4byte .LFE4 - 1962 026d 0400 .2byte 0x4 - 1963 026f F3 .byte 0xf3 - 1964 0270 01 .uleb128 0x1 - 1965 0271 50 .byte 0x50 - 1966 0272 9F .byte 0x9f - 1967 0273 00000000 .4byte 0 - 1968 0277 00000000 .4byte 0 - 1969 .LLST15: - 1970 027b 00000000 .4byte .LVL20 - 1971 027f 40000000 .4byte .LVL27 - 1972 0283 0200 .2byte 0x2 - 1973 0285 37 .byte 0x37 - 1974 0286 9F .byte 0x9f - 1975 0287 40000000 .4byte .LVL27 - 1976 028b 4C000000 .4byte .LFE4 - 1977 028f 0100 .2byte 0x1 - 1978 0291 50 .byte 0x50 - 1979 0292 00000000 .4byte 0 - 1980 0296 00000000 .4byte 0 - 1981 .LLST16: - 1982 029a 00000000 .4byte .LFB5 - 1983 029e 02000000 .4byte .LCFI5 - 1984 02a2 0200 .2byte 0x2 - 1985 02a4 7D .byte 0x7d - 1986 02a5 00 .sleb128 0 - 1987 02a6 02000000 .4byte .LCFI5 - 1988 02aa 48000000 .4byte .LFE5 - 1989 02ae 0200 .2byte 0x2 - 1990 02b0 7D .byte 0x7d - 1991 02b1 10 .sleb128 16 - 1992 02b2 00000000 .4byte 0 - 1993 02b6 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 46 - - - 1994 .LLST17: - 1995 02ba 00000000 .4byte .LVL28 - 1996 02be 2A000000 .4byte .LVL29 - 1997 02c2 0100 .2byte 0x1 - 1998 02c4 50 .byte 0x50 - 1999 02c5 2A000000 .4byte .LVL29 - 2000 02c9 38000000 .4byte .LVL31 - 2001 02cd 0200 .2byte 0x2 - 2002 02cf 74 .byte 0x74 - 2003 02d0 00 .sleb128 0 - 2004 02d1 38000000 .4byte .LVL31 - 2005 02d5 3A000000 .4byte .LVL32 - 2006 02d9 0100 .2byte 0x1 - 2007 02db 50 .byte 0x50 - 2008 02dc 3A000000 .4byte .LVL32 - 2009 02e0 3C000000 .4byte .LVL33 - 2010 02e4 0400 .2byte 0x4 - 2011 02e6 F3 .byte 0xf3 - 2012 02e7 01 .uleb128 0x1 - 2013 02e8 50 .byte 0x50 - 2014 02e9 9F .byte 0x9f - 2015 02ea 3C000000 .4byte .LVL33 - 2016 02ee 3E000000 .4byte .LVL34 - 2017 02f2 0100 .2byte 0x1 - 2018 02f4 50 .byte 0x50 - 2019 02f5 3E000000 .4byte .LVL34 - 2020 02f9 48000000 .4byte .LFE5 - 2021 02fd 0400 .2byte 0x4 - 2022 02ff F3 .byte 0xf3 - 2023 0300 01 .uleb128 0x1 - 2024 0301 50 .byte 0x50 - 2025 0302 9F .byte 0x9f - 2026 0303 00000000 .4byte 0 - 2027 0307 00000000 .4byte 0 - 2028 .LLST18: - 2029 030b 00000000 .4byte .LVL28 - 2030 030f 2C000000 .4byte .LVL30 - 2031 0313 0100 .2byte 0x1 - 2032 0315 51 .byte 0x51 - 2033 0316 2C000000 .4byte .LVL30 - 2034 031a 38000000 .4byte .LVL31 - 2035 031e 0400 .2byte 0x4 - 2036 0320 F3 .byte 0xf3 - 2037 0321 01 .uleb128 0x1 - 2038 0322 51 .byte 0x51 - 2039 0323 9F .byte 0x9f - 2040 0324 38000000 .4byte .LVL31 - 2041 0328 48000000 .4byte .LFE5 - 2042 032c 0100 .2byte 0x1 - 2043 032e 51 .byte 0x51 - 2044 032f 00000000 .4byte 0 - 2045 0333 00000000 .4byte 0 - 2046 .LLST19: - 2047 0337 00000000 .4byte .LVL28 - 2048 033b 3E000000 .4byte .LVL34 - 2049 033f 0200 .2byte 0x2 - 2050 0341 37 .byte 0x37 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 47 - - - 2051 0342 9F .byte 0x9f - 2052 0343 3E000000 .4byte .LVL34 - 2053 0347 48000000 .4byte .LFE5 - 2054 034b 0100 .2byte 0x1 - 2055 034d 50 .byte 0x50 - 2056 034e 00000000 .4byte 0 - 2057 0352 00000000 .4byte 0 - 2058 .LLST20: - 2059 0356 00000000 .4byte .LFB6 - 2060 035a 02000000 .4byte .LCFI6 - 2061 035e 0200 .2byte 0x2 - 2062 0360 7D .byte 0x7d - 2063 0361 00 .sleb128 0 - 2064 0362 02000000 .4byte .LCFI6 - 2065 0366 40000000 .4byte .LFE6 - 2066 036a 0200 .2byte 0x2 - 2067 036c 7D .byte 0x7d - 2068 036d 08 .sleb128 8 - 2069 036e 00000000 .4byte 0 - 2070 0372 00000000 .4byte 0 - 2071 .LLST21: - 2072 0376 00000000 .4byte .LVL35 - 2073 037a 2C000000 .4byte .LVL36 - 2074 037e 0100 .2byte 0x1 - 2075 0380 50 .byte 0x50 - 2076 0381 2C000000 .4byte .LVL36 - 2077 0385 2E000000 .4byte .LVL37 - 2078 0389 0200 .2byte 0x2 - 2079 038b 73 .byte 0x73 - 2080 038c 00 .sleb128 0 - 2081 038d 2E000000 .4byte .LVL37 - 2082 0391 30000000 .4byte .LVL38 - 2083 0395 0100 .2byte 0x1 - 2084 0397 50 .byte 0x50 - 2085 0398 30000000 .4byte .LVL38 - 2086 039c 32000000 .4byte .LVL39 - 2087 03a0 0400 .2byte 0x4 - 2088 03a2 F3 .byte 0xf3 - 2089 03a3 01 .uleb128 0x1 - 2090 03a4 50 .byte 0x50 - 2091 03a5 9F .byte 0x9f - 2092 03a6 32000000 .4byte .LVL39 - 2093 03aa 34000000 .4byte .LVL40 - 2094 03ae 0100 .2byte 0x1 - 2095 03b0 50 .byte 0x50 - 2096 03b1 34000000 .4byte .LVL40 - 2097 03b5 40000000 .4byte .LFE6 - 2098 03b9 0400 .2byte 0x4 - 2099 03bb F3 .byte 0xf3 - 2100 03bc 01 .uleb128 0x1 - 2101 03bd 50 .byte 0x50 - 2102 03be 9F .byte 0x9f - 2103 03bf 00000000 .4byte 0 - 2104 03c3 00000000 .4byte 0 - 2105 .LLST22: - 2106 03c7 00000000 .4byte .LVL35 - 2107 03cb 34000000 .4byte .LVL40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 48 - - - 2108 03cf 0200 .2byte 0x2 - 2109 03d1 37 .byte 0x37 - 2110 03d2 9F .byte 0x9f - 2111 03d3 34000000 .4byte .LVL40 - 2112 03d7 40000000 .4byte .LFE6 - 2113 03db 0100 .2byte 0x1 - 2114 03dd 50 .byte 0x50 - 2115 03de 00000000 .4byte 0 - 2116 03e2 00000000 .4byte 0 - 2117 .LLST23: - 2118 03e6 00000000 .4byte .LVL41 - 2119 03ea 28000000 .4byte .LVL42 - 2120 03ee 0100 .2byte 0x1 - 2121 03f0 50 .byte 0x50 - 2122 03f1 28000000 .4byte .LVL42 - 2123 03f5 2A000000 .4byte .LVL43 - 2124 03f9 0200 .2byte 0x2 - 2125 03fb 73 .byte 0x73 - 2126 03fc 00 .sleb128 0 - 2127 03fd 2A000000 .4byte .LVL43 - 2128 0401 2C000000 .4byte .LVL44 - 2129 0405 0100 .2byte 0x1 - 2130 0407 50 .byte 0x50 - 2131 0408 2C000000 .4byte .LVL44 - 2132 040c 2E000000 .4byte .LVL45 - 2133 0410 0400 .2byte 0x4 - 2134 0412 F3 .byte 0xf3 - 2135 0413 01 .uleb128 0x1 - 2136 0414 50 .byte 0x50 - 2137 0415 9F .byte 0x9f - 2138 0416 2E000000 .4byte .LVL45 - 2139 041a 30000000 .4byte .LVL46 - 2140 041e 0100 .2byte 0x1 - 2141 0420 50 .byte 0x50 - 2142 0421 30000000 .4byte .LVL46 - 2143 0425 3C000000 .4byte .LFE7 - 2144 0429 0400 .2byte 0x4 - 2145 042b F3 .byte 0xf3 - 2146 042c 01 .uleb128 0x1 - 2147 042d 50 .byte 0x50 - 2148 042e 9F .byte 0x9f - 2149 042f 00000000 .4byte 0 - 2150 0433 00000000 .4byte 0 - 2151 .LLST24: - 2152 0437 00000000 .4byte .LVL41 - 2153 043b 30000000 .4byte .LVL46 - 2154 043f 0200 .2byte 0x2 - 2155 0441 37 .byte 0x37 - 2156 0442 9F .byte 0x9f - 2157 0443 30000000 .4byte .LVL46 - 2158 0447 3C000000 .4byte .LFE7 - 2159 044b 0100 .2byte 0x1 - 2160 044d 50 .byte 0x50 - 2161 044e 00000000 .4byte 0 - 2162 0452 00000000 .4byte 0 - 2163 .LLST25: - 2164 0456 00000000 .4byte .LFB8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 49 - - - 2165 045a 02000000 .4byte .LCFI7 - 2166 045e 0200 .2byte 0x2 - 2167 0460 7D .byte 0x7d - 2168 0461 00 .sleb128 0 - 2169 0462 02000000 .4byte .LCFI7 - 2170 0466 40000000 .4byte .LFE8 - 2171 046a 0200 .2byte 0x2 - 2172 046c 7D .byte 0x7d - 2173 046d 10 .sleb128 16 - 2174 046e 00000000 .4byte 0 - 2175 0472 00000000 .4byte 0 - 2176 .LLST26: - 2177 0476 00000000 .4byte .LVL47 - 2178 047a 12000000 .4byte .LVL49 - 2179 047e 0200 .2byte 0x2 - 2180 0480 34 .byte 0x34 - 2181 0481 9F .byte 0x9f - 2182 0482 12000000 .4byte .LVL49 - 2183 0486 2C000000 .4byte .LVL50 - 2184 048a 0200 .2byte 0x2 - 2185 048c 30 .byte 0x30 - 2186 048d 9F .byte 0x9f - 2187 048e 2C000000 .4byte .LVL50 - 2188 0492 2E000000 .4byte .LVL51 - 2189 0496 0200 .2byte 0x2 - 2190 0498 34 .byte 0x34 - 2191 0499 9F .byte 0x9f - 2192 049a 2E000000 .4byte .LVL51 - 2193 049e 40000000 .4byte .LFE8 - 2194 04a2 0100 .2byte 0x1 - 2195 04a4 54 .byte 0x54 - 2196 04a5 00000000 .4byte 0 - 2197 04a9 00000000 .4byte 0 - 2198 .LLST27: - 2199 04ad 06000000 .4byte .LVL48 - 2200 04b1 31000000 .4byte .LVL52-1 - 2201 04b5 0100 .2byte 0x1 - 2202 04b7 50 .byte 0x50 - 2203 04b8 00000000 .4byte 0 - 2204 04bc 00000000 .4byte 0 - 2205 .LLST28: - 2206 04c0 00000000 .4byte .LFB9 - 2207 04c4 02000000 .4byte .LCFI8 - 2208 04c8 0200 .2byte 0x2 - 2209 04ca 7D .byte 0x7d - 2210 04cb 00 .sleb128 0 - 2211 04cc 02000000 .4byte .LCFI8 - 2212 04d0 34000000 .4byte .LFE9 - 2213 04d4 0200 .2byte 0x2 - 2214 04d6 7D .byte 0x7d - 2215 04d7 08 .sleb128 8 - 2216 04d8 00000000 .4byte 0 - 2217 04dc 00000000 .4byte 0 - 2218 .LLST29: - 2219 04e0 06000000 .4byte .LVL53 - 2220 04e4 2B000000 .4byte .LVL54-1 - 2221 04e8 0100 .2byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 50 - - - 2222 04ea 50 .byte 0x50 - 2223 04eb 00000000 .4byte 0 - 2224 04ef 00000000 .4byte 0 - 2225 .section .debug_aranges,"",%progbits - 2226 0000 64000000 .4byte 0x64 - 2227 0004 0200 .2byte 0x2 - 2228 0006 00000000 .4byte .Ldebug_info0 - 2229 000a 04 .byte 0x4 - 2230 000b 00 .byte 0 - 2231 000c 0000 .2byte 0 - 2232 000e 0000 .2byte 0 - 2233 0010 00000000 .4byte .LFB0 - 2234 0014 24000000 .4byte .LFE0-.LFB0 - 2235 0018 00000000 .4byte .LFB1 - 2236 001c 24000000 .4byte .LFE1-.LFB1 - 2237 0020 00000000 .4byte .LFB2 - 2238 0024 34000000 .4byte .LFE2-.LFB2 - 2239 0028 00000000 .4byte .LFB3 - 2240 002c 74000000 .4byte .LFE3-.LFB3 - 2241 0030 00000000 .4byte .LFB4 - 2242 0034 4C000000 .4byte .LFE4-.LFB4 - 2243 0038 00000000 .4byte .LFB5 - 2244 003c 48000000 .4byte .LFE5-.LFB5 - 2245 0040 00000000 .4byte .LFB6 - 2246 0044 40000000 .4byte .LFE6-.LFB6 - 2247 0048 00000000 .4byte .LFB7 - 2248 004c 3C000000 .4byte .LFE7-.LFB7 - 2249 0050 00000000 .4byte .LFB8 - 2250 0054 40000000 .4byte .LFE8-.LFB8 - 2251 0058 00000000 .4byte .LFB9 - 2252 005c 34000000 .4byte .LFE9-.LFB9 - 2253 0060 00000000 .4byte 0 - 2254 0064 00000000 .4byte 0 - 2255 .section .debug_ranges,"",%progbits - 2256 .Ldebug_ranges0: - 2257 0000 00000000 .4byte .LFB0 - 2258 0004 24000000 .4byte .LFE0 - 2259 0008 00000000 .4byte .LFB1 - 2260 000c 24000000 .4byte .LFE1 - 2261 0010 00000000 .4byte .LFB2 - 2262 0014 34000000 .4byte .LFE2 - 2263 0018 00000000 .4byte .LFB3 - 2264 001c 74000000 .4byte .LFE3 - 2265 0020 00000000 .4byte .LFB4 - 2266 0024 4C000000 .4byte .LFE4 - 2267 0028 00000000 .4byte .LFB5 - 2268 002c 48000000 .4byte .LFE5 - 2269 0030 00000000 .4byte .LFB6 - 2270 0034 40000000 .4byte .LFE6 - 2271 0038 00000000 .4byte .LFB7 - 2272 003c 3C000000 .4byte .LFE7 - 2273 0040 00000000 .4byte .LFB8 - 2274 0044 40000000 .4byte .LFE8 - 2275 0048 00000000 .4byte .LFB9 - 2276 004c 34000000 .4byte .LFE9 - 2277 0050 00000000 .4byte 0 - 2278 0054 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 51 - - - 2279 .section .debug_line,"",%progbits - 2280 .Ldebug_line0: - 2281 0000 B9010000 .section .debug_str,"MS",%progbits,1 - 2281 02004F00 - 2281 00000201 - 2281 FB0E0D00 - 2281 01010101 - 2282 .LASF25: - 2283 0000 43795370 .ascii "CySpcLoadMultiByte\000" - 2283 634C6F61 - 2283 644D756C - 2283 74694279 - 2283 746500 - 2284 .LASF15: - 2285 0013 63797374 .ascii "cystatus\000" - 2285 61747573 - 2285 00 - 2286 .LASF17: - 2287 001c 72656733 .ascii "reg32\000" - 2287 3200 - 2288 .LASF19: - 2289 0022 43795370 .ascii "CySpcStart\000" - 2289 63537461 - 2289 727400 - 2290 .LASF30: - 2291 002d 43795370 .ascii "CySpcWriteRow\000" - 2291 63577269 - 2291 7465526F - 2291 7700 - 2292 .LASF20: - 2293 003b 43795370 .ascii "CySpcStop\000" - 2293 6353746F - 2293 7000 - 2294 .LASF41: - 2295 0045 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\CySpc.c\000" - 2295 6E657261 - 2295 7465645F - 2295 536F7572 - 2295 63655C50 - 2296 .LASF3: - 2297 0066 73686F72 .ascii "short unsigned int\000" - 2297 7420756E - 2297 7369676E - 2297 65642069 - 2297 6E7400 - 2298 .LASF24: - 2299 0079 43795370 .ascii "CySpcReadData\000" - 2299 63526561 - 2299 64446174 - 2299 6100 - 2300 .LASF28: - 2301 0087 73746174 .ascii "status\000" - 2301 757300 - 2302 .LASF12: - 2303 008e 666C6F61 .ascii "float\000" - 2303 7400 - 2304 .LASF36: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 52 - - - 2305 0094 6E756D53 .ascii "numSamples\000" - 2305 616D706C - 2305 657300 - 2306 .LASF23: - 2307 009f 73697A65 .ascii "size\000" - 2307 00 - 2308 .LASF16: - 2309 00a4 72656738 .ascii "reg8\000" - 2309 00 - 2310 .LASF21: - 2311 00a9 696E7465 .ascii "interruptState\000" - 2311 72727570 - 2311 74537461 - 2311 746500 - 2312 .LASF5: - 2313 00b8 6C6F6E67 .ascii "long unsigned int\000" - 2313 20756E73 - 2313 69676E65 - 2313 6420696E - 2313 7400 - 2314 .LASF42: - 2315 00ca 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 2315 43534932 - 2315 53445C73 - 2315 6F667477 - 2315 6172655C - 2316 00f9 6E00 .ascii "n\000" - 2317 .LASF9: - 2318 00fb 75696E74 .ascii "uint8\000" - 2318 3800 - 2319 .LASF43: - 2320 0101 5370634C .ascii "SpcLockState\000" - 2320 6F636B53 - 2320 74617465 - 2320 00 - 2321 .LASF31: - 2322 010e 74656D70 .ascii "tempPolarity\000" - 2322 506F6C61 - 2322 72697479 - 2322 00 - 2323 .LASF26: - 2324 011b 61727261 .ascii "array\000" - 2324 7900 - 2325 .LASF1: - 2326 0121 756E7369 .ascii "unsigned char\000" - 2326 676E6564 - 2326 20636861 - 2326 7200 - 2327 .LASF13: - 2328 012f 646F7562 .ascii "double\000" - 2328 6C6500 - 2329 .LASF35: - 2330 0136 43795370 .ascii "CySpcGetTemp\000" - 2330 63476574 - 2330 54656D70 - 2330 00 - 2331 .LASF10: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 53 - - - 2332 0143 75696E74 .ascii "uint16\000" - 2332 313600 - 2333 .LASF37: - 2334 014a 43795370 .ascii "CySpcLock\000" - 2334 634C6F63 - 2334 6B00 - 2335 .LASF11: - 2336 0154 75696E74 .ascii "uint32\000" - 2336 333200 - 2337 .LASF44: - 2338 015b 4379456E .ascii "CyEnterCriticalSection\000" - 2338 74657243 - 2338 72697469 - 2338 63616C53 - 2338 65637469 - 2339 .LASF8: - 2340 0172 756E7369 .ascii "unsigned int\000" - 2340 676E6564 - 2340 20696E74 - 2340 00 - 2341 .LASF27: - 2342 017f 61646472 .ascii "address\000" - 2342 65737300 - 2343 .LASF7: - 2344 0187 6C6F6E67 .ascii "long long unsigned int\000" - 2344 206C6F6E - 2344 6720756E - 2344 7369676E - 2344 65642069 - 2345 .LASF32: - 2346 019e 74656D70 .ascii "tempMagnitude\000" - 2346 4D61676E - 2346 69747564 - 2346 6500 - 2347 .LASF29: - 2348 01ac 43795370 .ascii "CySpcLoadRow\000" - 2348 634C6F61 - 2348 64526F77 - 2348 00 - 2349 .LASF18: - 2350 01b9 73697A65 .ascii "sizetype\000" - 2350 74797065 - 2350 00 - 2351 .LASF38: - 2352 01c2 43795370 .ascii "CySpcUnlock\000" - 2352 63556E6C - 2352 6F636B00 - 2353 .LASF33: - 2354 01ce 43795370 .ascii "CySpcEraseSector\000" - 2354 63457261 - 2354 73655365 - 2354 63746F72 - 2354 00 - 2355 .LASF6: - 2356 01df 6C6F6E67 .ascii "long long int\000" - 2356 206C6F6E - 2356 6720696E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNS4VrE.s page 54 - - - 2356 7400 - 2357 .LASF46: - 2358 01ed 43794465 .ascii "CyDelayUs\000" - 2358 6C617955 - 2358 7300 - 2359 .LASF14: - 2360 01f7 63686172 .ascii "char\000" - 2360 00 - 2361 .LASF2: - 2362 01fc 73686F72 .ascii "short int\000" - 2362 7420696E - 2362 7400 - 2363 .LASF22: - 2364 0206 62756666 .ascii "buffer\000" - 2364 657200 - 2365 .LASF34: - 2366 020d 73656374 .ascii "sectorNumber\000" - 2366 6F724E75 - 2366 6D626572 - 2366 00 - 2367 .LASF45: - 2368 021a 43794578 .ascii "CyExitCriticalSection\000" - 2368 69744372 - 2368 69746963 - 2368 616C5365 - 2368 6374696F - 2369 .LASF4: - 2370 0230 6C6F6E67 .ascii "long int\000" - 2370 20696E74 - 2370 00 - 2371 .LASF39: - 2372 0239 73706357 .ascii "spcWaitPipeBypass\000" - 2372 61697450 - 2372 69706542 - 2372 79706173 - 2372 7300 - 2373 .LASF0: - 2374 024b 7369676E .ascii "signed char\000" - 2374 65642063 - 2374 68617200 - 2375 .LASF40: - 2376 0257 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 2376 4320342E - 2376 372E3320 - 2376 32303133 - 2376 30333132 - 2377 028a 616E6368 .ascii "anch revision 196615]\000" - 2377 20726576 - 2377 6973696F - 2377 6E203139 - 2377 36363135 - 2378 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/CySpc.o deleted file mode 100755 index cf97e1cffa42d3be22c5cb83835bd3fbe0b04fdc..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 11440 zcmb_idvsjIeV*C7E3KuKEcqd0`N5TuY#G~&WEFSC#z;cT4K%9x>LL|B`N;?W z{YlBz+L4xXVLdZdd$Ympsk7l2Bu_oqs$zMaz_|~Mj==(*)X9>K6&qFkzm9#YCGu+N zCOz_Esq>n4>HULuf?KAJEZeP@|LUE_jj2=f+EmO%UDKF4sZU?HC~#(NTP-l%S zioG$`g9!JHeHs2<>MGf!mwEo0;HwF~ntZ-eCnx9fedt7m$@esJ4f*oj4R7JH=f~Vs zU8>Zbm%1pG&&uXhb+Q8E_(E zle(dN%be7-{>8Dfm#6jDpVPr<2h>yiyY@h2qdF6;=iPKSu0m{1p`Z%Ks*L@lt!myi z{k18*F#JmC=1Bi~*ha*5?}1ZitIS-oHrEH03Ya+<)O*m-8$i5Z7=@RBF4+osK!@uv zj{||w?+ldoK`jsrHBlBUeS%at^v{%qOOF7YU}#_{OIaFJ@M9|MYr-|yN~NwfZ0=(7 z+IGr z^MazMfh>KPtsS&=QNty;ti~WrBBi&W1>-B&?#~%7Be^4Id_9djQ71Ak)1%ZrqN&8f z70yA@kHA5B3CH*dn|Fd&ew2bERAs*+14`dT;#t%R_Ut<3Q>i<2vr?0Tl$4pI^qBr8 z2$n4B>!|u7crKp>u^yx1N2uku8uCUozlc_q2|h+ey|c=MHmbU_^awqiq)(0>^LU(2 zPJ=+;g|MjhqCZNH=X23{OMXGtmvYh1Q!xV43wPdx+u?;f&s6kIFWe^#cM}w+Ae_<^ zsi}GiHCF3fgiWCDhm!snmuaSdtIgPcm$d2NYGYgOC^fy3xp;EDbNT~5s1Ip9+STS&~f=F-1#fz0Tu@2LB1+(yIy~FdCHQv5YZ!`1?dV4tUZ8f-oTa^A2 zI{R}F5OQpO2HG?KmX{3Y+*G}V=0C}s$H2V`BK?m!{nJMOFqk!F7Qb%%eH(OcCWe>7 z%*^5o^xxBCSpZjW7CudHGjrCF0JAycx1O{Z9B&cKyo}vleFqpJ2Rf>jPcz*_8y#Yg z)hxXaEa#6+7J9a>g@tpg)||9+sHf)YUs7X4>pAB3DqXD`DyNn^m9r{$msIPWx(e$r zP_N3%*MJFCX@;?~Ym`%YdHEIPo3Z*smnuR@RIiPA+y#+pJw?Y#{-PzKAt_y+(+so`x;OAIB_@ob`Ze`j(y-IM6*=uEa=s#NP}XR0UKL#>|C>}V>HiT0Cd z9c>@z_L^AjW>}mbC_S&~n(a#hLHM@JvlB6oXze!R_^wM_b6wNk-h~HY-s&-}Yn>6d zF{cxVmR!=*f8`}jd+V;OyRfb)FDO~#9K70Tj4oX0RJsLD&THKOlje3R&%-6K#z|i7 z%!)2_CKYO)3g~)j?yZAwC+#|u-8yHIrx)_2^$ON_|o84(j^mrL*gs_d#dD64NJhAKH`g-fhE!*@2eP zYy$TqlZ|JGGb)`pxNNC+r#iFobk=L`Ne^TbJCiq9K{BQOx7*xh?{cO;na;YyLz#ht zLy2CO?{Y@8GZF7yAJ4{>MC=<(#2!Ql<&y5{kEc~{a=3di;U(Xe$nJu^@zcD*3i00FbRv`Sx--5{%x7Et;Lt#JxL2a`UUBp}GF&%a+}%Ti zjBEyVLpq*GFj_M0^XrZI`ov&-bazIX&Ukl)g6`qIzC>DOjM4VtL){=+M>mWNWQ(&m zInpGP>e&+?$aV~*5-p>tIQk$r*SK!mzT0hemq%Adm$^%unwK>#YhLO$rW1n+`r6tm-9)`QY81sZ8!Fj*zHd24jTJy`P3-(?YE5?c{p~vlZRXfHQ}Xg6k56cZ*&X4Fh14TSpqlVj?=pH_}e_*IDiT;{) zyt^Bd-|LCT!HV{iajcMo*b;sA<2i!^Lka5lZ;YzkWtUP+c%0{r+wS?H?QK zZ+DTuP4LHj7@KJQ9YWjh?{7eJ&D&!A-3f+YuO0-~zAaYoFTwEZr9f=5N_J_51rwol+lS(lS5%S0;Dgs-b6X=yOJ? zQg8Ygws}#J-uvj>`xC^y5PJT&BMnM*guJ-?`G+PPm!(DiepcbV+(TrFjTxtiN?d{#?A>JP0L@OD(GPx2MS8G59-Woj}hvJB$214S#&Q zqCY-&tiK-d$9;jN2aEhc+&f$7k9DX>&%w?5v{e!v>fL|~ZfDAhvd~**3DG0@dGTjO z$Dy~F4x}(Y7XEDEzi(C8m>vY5{is8={oq`*dmozWwP{M-=ksTqL|^w*7Y5@D3^5(d zt1`V-41I=Q>!ah-xpDECJs9W3ZOd&@I~>zU(f zN6BM2*oFOL#a+2j-|o^@KU}0AHu@N1DO?fx;;6DB{W7CJm{Tdswb*b}d69m((O;j_ zD$lh%{Ya61#OTLzTI@}}II5yZzryIR%Bf)S`ii3}i}WjvetzG>V)7LSJ7(c{PA>A# z9W`GZRb8ZCZS?cw>Ct`*yC?Hb>T&lUi^5kNHQh&Xe7zs8Ez>DDF;dQ*BVU|?6DQ?! zO@5s3Ua7MUgN|8Yd6r}TW$dS2qro{}k2(eOG2d5j9ku4w&APJBcTc}W^*~O0-h(OF zf&F_5^SVjoStBn~_Xyo?=yLTnp*I;iq8=7HX6Op_U7`6*or3%SeW7E9o~&LG+KXSU z-U7|SoT_<0?7Me;R@L`T@Ve$ZQsY%`Xo5G@iQfRl4ySI@%AK`aNA1g{;TN8_bFADy z4svH~Bl4fF4a1(R#n8Un${D)grQO>X%bLCC!(6<-ai8?le6E$@pH7w^B@I2UH~dp6 z$LAa%-3X)~?mB___#u*r=MeX5B4;ykCUK#+2M6#RHTK~1xj{Mq;Y(a6$a_utQ-b_O zfizxo4PGzEhY!=tw%}PJ4&d(*;s19+ zYfK{Q@pock4H5D=#4w&;f(=C2n_t->zf9;gB5xDqGoAL=5zF!0gkT>L_B@MHexuO* zL6-DgLVs28Yed+OiJa$$0Jgqo1fM0s-w#Fpy3qe5^jV?#dm{b+mtZL-2I*=d?B@!a z?-9Vif;4XaTESM4ZzDp^ZyspZCG>#cVZqOc{9d8|ia1TFZwP)<xI8n=siSi#rp*Ng`Xk9 z--yt+34OQFUnS1LPws*bi2S(79~1fsq5nbX=ZLU-Met3LzfE+NIxF}KBI5s+i2i7< zVbCQ+=uH-^C9=On)I~zCB3_A~UxaQKJRpc=VCFqYgJ%6>9dKXgdT<5n1!jX zxK^-Luv2i4U>~tusXr1-3mz6U>mBmDg}zttD}oOR9vA$M;A4W%3O+Ar)<4$CTcm;i zCiw4y9|@ip402sSFDzIk$WLF$=Q|0J?=Zwgf@U88eYwzP9{|mF3F>VYH2VQ)z7vpd z_64BX7l4DpH~Ru;p3SLulOVrCA$_kP&&#C0E_h6kU&xSeexU%`{le@Mpr04{X+gfH zQJ){9aJ`=s(%^s|D`3%(-wW5G8C&j`LN_#cA55&TGy zU(qoBWWgH2TETk3MnQf_L;WiRTLs$$uOebU+bh^D*e7^c@J7MU3f>|3MZtRo?-TsG z;4#5R1WyQ_6y&!#jQ^tGj|6`z$d7TjPrfVoYr)?Lo)MLzQTG!gmOef_UVbDtq1zBykZp4l%EXFvBF_&4Vu_K;f1u4cq2Gf-r-+F61);x8MBL*-KT1UW=Y)QVh& - 21:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS.h" - 22:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_pvt.h" - 23:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_hid.h" - 24:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA1_REMOVE == 0u) - 25:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep1_dma.h" - 26:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA1_REMOVE */ - 27:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA2_REMOVE == 0u) - 28:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep2_dma.h" - 29:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA2_REMOVE */ - 30:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA3_REMOVE == 0u) - 31:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep3_dma.h" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 2 - - - 32:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA3_REMOVE */ - 33:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA4_REMOVE == 0u) - 34:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep4_dma.h" - 35:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA4_REMOVE */ - 36:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA5_REMOVE == 0u) - 37:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep5_dma.h" - 38:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA5_REMOVE */ - 39:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA6_REMOVE == 0u) - 40:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep6_dma.h" - 41:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA6_REMOVE */ - 42:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA7_REMOVE == 0u) - 43:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep7_dma.h" - 44:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA7_REMOVE */ - 45:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA8_REMOVE == 0u) - 46:.\Generated_Source\PSoC5/USBFS.c **** #include "USBFS_ep8_dma.h" - 47:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA8_REMOVE */ - 48:.\Generated_Source\PSoC5/USBFS.c **** - 49:.\Generated_Source\PSoC5/USBFS.c **** - 50:.\Generated_Source\PSoC5/USBFS.c **** /*************************************** - 51:.\Generated_Source\PSoC5/USBFS.c **** * Global data allocation - 52:.\Generated_Source\PSoC5/USBFS.c **** ***************************************/ - 53:.\Generated_Source\PSoC5/USBFS.c **** - 54:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_initVar = 0u; - 55:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_MANUAL) - 56:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_DmaChan[USBFS_MAX_EP]; - 57:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_DmaTd[USBFS_MAX_EP]; - 58:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM */ - 59:.\Generated_Source\PSoC5/USBFS.c **** - 60:.\Generated_Source\PSoC5/USBFS.c **** - 61:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 62:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_Start - 63:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 64:.\Generated_Source\PSoC5/USBFS.c **** * - 65:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 66:.\Generated_Source\PSoC5/USBFS.c **** * This function initialize the USB SIE, arbiter and the - 67:.\Generated_Source\PSoC5/USBFS.c **** * endpoint APIs, including setting the D+ Pullup - 68:.\Generated_Source\PSoC5/USBFS.c **** * - 69:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 70:.\Generated_Source\PSoC5/USBFS.c **** * device: Contains the device number of the desired device descriptor. - 71:.\Generated_Source\PSoC5/USBFS.c **** * The device number can be found in the Device Descriptor Tab of - 72:.\Generated_Source\PSoC5/USBFS.c **** * "Configure" dialog, under the settings of desired Device Descriptor, - 73:.\Generated_Source\PSoC5/USBFS.c **** * in the "Device Number" field. - 74:.\Generated_Source\PSoC5/USBFS.c **** * mode: The operating voltage. This determines whether the voltage regulator - 75:.\Generated_Source\PSoC5/USBFS.c **** * is enabled for 5V operation or if pass through mode is used for 3.3V - 76:.\Generated_Source\PSoC5/USBFS.c **** * operation. Symbolic names and their associated values are given in the - 77:.\Generated_Source\PSoC5/USBFS.c **** * following table. - 78:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_3V_OPERATION - Disable voltage regulator and pass-thru - 79:.\Generated_Source\PSoC5/USBFS.c **** * Vcc for pull-up - 80:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_5V_OPERATION - Enable voltage regulator and use - 81:.\Generated_Source\PSoC5/USBFS.c **** * regulator for pull-up - 82:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage - 83:.\Generated_Source\PSoC5/USBFS.c **** * regulator depend on Vddd Voltage configuration in DWR. - 84:.\Generated_Source\PSoC5/USBFS.c **** * - 85:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 86:.\Generated_Source\PSoC5/USBFS.c **** * None. - 87:.\Generated_Source\PSoC5/USBFS.c **** * - 88:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 3 - - - 89:.\Generated_Source\PSoC5/USBFS.c **** * The USBFS_intiVar variable is used to indicate initial - 90:.\Generated_Source\PSoC5/USBFS.c **** * configuration of this component. The variable is initialized to zero (0u) - 91:.\Generated_Source\PSoC5/USBFS.c **** * and set to one (1u) the first time USBFS_Start() is called. - 92:.\Generated_Source\PSoC5/USBFS.c **** * This allows for component Re-Start without unnecessary re-initialization - 93:.\Generated_Source\PSoC5/USBFS.c **** * in all subsequent calls to the USBFS_Start() routine. - 94:.\Generated_Source\PSoC5/USBFS.c **** * If re-initialization of the component is required the variable should be set - 95:.\Generated_Source\PSoC5/USBFS.c **** * to zero before call of UART_Start() routine, or the user may call - 96:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_Init() and USBFS_InitComponent() as done - 97:.\Generated_Source\PSoC5/USBFS.c **** * in the USBFS_Start() routine. - 98:.\Generated_Source\PSoC5/USBFS.c **** * - 99:.\Generated_Source\PSoC5/USBFS.c **** * Side Effects: - 100:.\Generated_Source\PSoC5/USBFS.c **** * This function will reset all communication states to default. - 101:.\Generated_Source\PSoC5/USBFS.c **** * - 102:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: - 103:.\Generated_Source\PSoC5/USBFS.c **** * No. - 104:.\Generated_Source\PSoC5/USBFS.c **** * - 105:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 106:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_Start(uint8 device, uint8 mode) - 107:.\Generated_Source\PSoC5/USBFS.c **** { - 108:.\Generated_Source\PSoC5/USBFS.c **** /* If not Initialized then initialize all required hardware and software */ - 109:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_initVar == 0u) - 110:.\Generated_Source\PSoC5/USBFS.c **** { - 111:.\Generated_Source\PSoC5/USBFS.c **** USBFS_Init(); - 112:.\Generated_Source\PSoC5/USBFS.c **** USBFS_initVar = 1u; - 113:.\Generated_Source\PSoC5/USBFS.c **** } - 114:.\Generated_Source\PSoC5/USBFS.c **** USBFS_InitComponent(device, mode); - 115:.\Generated_Source\PSoC5/USBFS.c **** } - 116:.\Generated_Source\PSoC5/USBFS.c **** - 117:.\Generated_Source\PSoC5/USBFS.c **** - 118:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 119:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_Init - 120:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 121:.\Generated_Source\PSoC5/USBFS.c **** * - 122:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 123:.\Generated_Source\PSoC5/USBFS.c **** * Initialize component's hardware. Usually called in USBFS_Start(). - 124:.\Generated_Source\PSoC5/USBFS.c **** * - 125:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 126:.\Generated_Source\PSoC5/USBFS.c **** * None. - 127:.\Generated_Source\PSoC5/USBFS.c **** * - 128:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 129:.\Generated_Source\PSoC5/USBFS.c **** * None. - 130:.\Generated_Source\PSoC5/USBFS.c **** * - 131:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: - 132:.\Generated_Source\PSoC5/USBFS.c **** * No. - 133:.\Generated_Source\PSoC5/USBFS.c **** * - 134:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 135:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_Init(void) - 136:.\Generated_Source\PSoC5/USBFS.c **** { - 27 .loc 1 136 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 32 .LCFI0: - 33 .cfi_def_cfa_offset 24 - 34 .cfi_offset 3, -24 - 35 .cfi_offset 4, -20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 4 - - - 36 .cfi_offset 5, -16 - 37 .cfi_offset 6, -12 - 38 .cfi_offset 7, -8 - 39 .cfi_offset 14, -4 - 137:.\Generated_Source\PSoC5/USBFS.c **** uint8 enableInterrupts; - 138:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_MANUAL) - 139:.\Generated_Source\PSoC5/USBFS.c **** uint16 i; - 140:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - 141:.\Generated_Source\PSoC5/USBFS.c **** - 142:.\Generated_Source\PSoC5/USBFS.c **** enableInterrupts = CyEnterCriticalSection(); - 40 .loc 1 142 0 - 41 0002 FFF7FEFF bl CyEnterCriticalSection - 42 .LVL0: - 143:.\Generated_Source\PSoC5/USBFS.c **** - 144:.\Generated_Source\PSoC5/USBFS.c **** /* Enable USB block */ - 145:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; - 43 .loc 1 145 0 - 44 0006 384B ldr r3, .L2 - 142:.\Generated_Source\PSoC5/USBFS.c **** enableInterrupts = CyEnterCriticalSection(); - 45 .loc 1 142 0 - 46 0008 0746 mov r7, r0 - 47 .LVL1: - 48 .loc 1 145 0 - 49 000a 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 146:.\Generated_Source\PSoC5/USBFS.c **** /* Enable USB block for Standby Power Mode */ - 147:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; - 148:.\Generated_Source\PSoC5/USBFS.c **** - 149:.\Generated_Source\PSoC5/USBFS.c **** /* Enable core clock */ - 150:.\Generated_Source\PSoC5/USBFS.c **** USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; - 50 .loc 1 150 0 - 51 000c 0125 movs r5, #1 - 145:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; - 52 .loc 1 145 0 - 53 000e 42F00100 orr r0, r2, #1 - 54 .LVL2: - 55 0012 1870 strb r0, [r3, #0] - 147:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; - 56 .loc 1 147 0 - 57 0014 197C ldrb r1, [r3, #16] @ zero_extendqisi2 - 151:.\Generated_Source\PSoC5/USBFS.c **** - 152:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - 58 .loc 1 152 0 - 59 0016 0226 movs r6, #2 - 147:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; - 60 .loc 1 147 0 - 61 0018 41F00104 orr r4, r1, #1 - 62 001c 1C74 strb r4, [r3, #16] - 150:.\Generated_Source\PSoC5/USBFS.c **** USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; - 63 .loc 1 150 0 - 64 001e 334B ldr r3, .L2+4 - 153:.\Generated_Source\PSoC5/USBFS.c **** - 154:.\Generated_Source\PSoC5/USBFS.c **** /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */ - 155:.\Generated_Source\PSoC5/USBFS.c **** /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ - 156:.\Generated_Source\PSoC5/USBFS.c **** USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN)); - 157:.\Generated_Source\PSoC5/USBFS.c **** CyDelayUs(0u); /*~50ns delay */ - 158:.\Generated_Source\PSoC5/USBFS.c **** /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) - 159:.\Generated_Source\PSoC5/USBFS.c **** * high. This will have been set low by the power manger out of reset. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 5 - - - 160:.\Generated_Source\PSoC5/USBFS.c **** * Also confirm USBIO pull-up disabled - 161:.\Generated_Source\PSoC5/USBFS.c **** */ - 162:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N | - 65 .loc 1 162 0 - 66 0020 334C ldr r4, .L2+8 - 150:.\Generated_Source\PSoC5/USBFS.c **** USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; - 67 .loc 1 150 0 - 68 0022 1D70 strb r5, [r3, #0] - 152:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - 69 .loc 1 152 0 - 70 0024 03F8946C strb r6, [r3, #-148] - 156:.\Generated_Source\PSoC5/USBFS.c **** USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN)); - 71 .loc 1 156 0 - 72 0028 13F88D2C ldrb r2, [r3, #-141] @ zero_extendqisi2 - 73 002c 02F07F00 and r0, r2, #127 - 74 0030 03F88D0C strb r0, [r3, #-141] - 157:.\Generated_Source\PSoC5/USBFS.c **** CyDelayUs(0u); /*~50ns delay */ - 75 .loc 1 157 0 - 76 0034 0020 movs r0, #0 - 77 0036 FFF7FEFF bl CyDelayUs - 78 .LVL3: - 79 .loc 1 162 0 - 80 003a 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 163:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_PD_PULLUP_N))); - 164:.\Generated_Source\PSoC5/USBFS.c **** - 165:.\Generated_Source\PSoC5/USBFS.c **** /* Select iomode to USB mode*/ - 166:.\Generated_Source\PSoC5/USBFS.c **** USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE)); - 81 .loc 1 166 0 - 82 003c 2D48 ldr r0, .L2+12 - 162:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N | - 83 .loc 1 162 0 - 84 003e 01F0F903 and r3, r1, #249 - 85 0042 2370 strb r3, [r4, #0] - 86 .loc 1 166 0 - 87 0044 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 88 0046 02F0DF01 and r1, r2, #223 - 89 004a 0170 strb r1, [r0, #0] - 167:.\Generated_Source\PSoC5/USBFS.c **** - 168:.\Generated_Source\PSoC5/USBFS.c **** /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ - 169:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; - 90 .loc 1 169 0 - 91 004c 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 170:.\Generated_Source\PSoC5/USBFS.c **** /* The reference will be available 1 us after the regulator is enabled */ - 171:.\Generated_Source\PSoC5/USBFS.c **** CyDelayUs(1u); - 92 .loc 1 171 0 - 93 004e 2846 mov r0, r5 - 169:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; - 94 .loc 1 169 0 - 95 0050 2B43 orrs r3, r3, r5 - 96 0052 2370 strb r3, [r4, #0] - 97 .loc 1 171 0 - 98 0054 FFF7FEFF bl CyDelayUs - 99 .LVL4: - 172:.\Generated_Source\PSoC5/USBFS.c **** /* OR 40us after power restored */ - 173:.\Generated_Source\PSoC5/USBFS.c **** CyDelayUs(40u); - 100 .loc 1 173 0 - 101 0058 2820 movs r0, #40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 6 - - - 102 005a FFF7FEFF bl CyDelayUs - 103 .LVL5: - 174:.\Generated_Source\PSoC5/USBFS.c **** /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). * - 175:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK)); - 104 .loc 1 175 0 - 105 005e 2648 ldr r0, .L2+16 - 106 0060 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 107 0062 02F07F01 and r1, r2, #127 - 108 0066 0170 strb r1, [r0, #0] - 176:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK)); - 109 .loc 1 176 0 - 110 0068 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 111 006a 03F0BF02 and r2, r3, #191 - 112 006e 0270 strb r2, [r0, #0] - 177:.\Generated_Source\PSoC5/USBFS.c **** - 178:.\Generated_Source\PSoC5/USBFS.c **** /* Enable USBIO */ - 179:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; - 113 .loc 1 179 0 - 114 0070 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 115 0072 3043 orrs r0, r0, r6 - 116 0074 2070 strb r0, [r4, #0] - 180:.\Generated_Source\PSoC5/USBFS.c **** CyDelayUs(2u); - 117 .loc 1 180 0 - 118 0076 3046 mov r0, r6 - 119 0078 FFF7FEFF bl CyDelayUs - 120 .LVL6: - 181:.\Generated_Source\PSoC5/USBFS.c **** /* Set the USBIO pull-up enable */ - 182:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; - 121 .loc 1 182 0 - 122 007c 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 183:.\Generated_Source\PSoC5/USBFS.c **** - 184:.\Generated_Source\PSoC5/USBFS.c **** /* Write WAx */ - 185:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); - 123 .loc 1 185 0 - 124 007e 1F4A ldr r2, .L2+20 - 182:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; - 125 .loc 1 182 0 - 126 0080 41F00403 orr r3, r1, #4 - 127 0084 2370 strb r3, [r4, #0] - 128 .loc 1 185 0 - 129 0086 0024 movs r4, #0 - 130 0088 1470 strb r4, [r2, #0] - 186:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); - 187:.\Generated_Source\PSoC5/USBFS.c **** - 188:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_MANUAL) - 189:.\Generated_Source\PSoC5/USBFS.c **** /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not - 190:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < USBFS_MAX_EP; i++) - 191:.\Generated_Source\PSoC5/USBFS.c **** { - 192:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaTd[i] = DMA_INVALID_TD; - 193:.\Generated_Source\PSoC5/USBFS.c **** } - 194:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - 195:.\Generated_Source\PSoC5/USBFS.c **** - 196:.\Generated_Source\PSoC5/USBFS.c **** CyExitCriticalSection(enableInterrupts); - 131 .loc 1 196 0 - 132 008a 3846 mov r0, r7 - 186:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); - 133 .loc 1 186 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 7 - - - 134 008c 5470 strb r4, [r2, #1] - 135 .loc 1 196 0 - 136 008e FFF7FEFF bl CyExitCriticalSection - 137 .LVL7: - 197:.\Generated_Source\PSoC5/USBFS.c **** - 198:.\Generated_Source\PSoC5/USBFS.c **** - 199:.\Generated_Source\PSoC5/USBFS.c **** /* Set the bus reset Interrupt. */ - 200:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); - 138 .loc 1 200 0 - 139 0092 1720 movs r0, #23 - 140 0094 1A49 ldr r1, .L2+24 - 141 0096 FFF7FEFF bl CyIntSetVector - 142 .LVL8: - 201:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); - 143 .loc 1 201 0 - 144 009a 1720 movs r0, #23 - 145 009c 0721 movs r1, #7 - 146 009e FFF7FEFF bl CyIntSetPriority - 147 .LVL9: - 202:.\Generated_Source\PSoC5/USBFS.c **** - 203:.\Generated_Source\PSoC5/USBFS.c **** /* Set the SOF Interrupt. */ - 204:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_SOF_ISR_REMOVE == 0u) - 205:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); - 148 .loc 1 205 0 - 149 00a2 1520 movs r0, #21 - 150 00a4 1749 ldr r1, .L2+28 - 151 00a6 FFF7FEFF bl CyIntSetVector - 152 .LVL10: - 206:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); - 153 .loc 1 206 0 - 154 00aa 1520 movs r0, #21 - 155 00ac 0721 movs r1, #7 - 156 00ae FFF7FEFF bl CyIntSetPriority - 157 .LVL11: - 207:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_SOF_ISR_REMOVE */ - 208:.\Generated_Source\PSoC5/USBFS.c **** - 209:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Control Endpoint Interrupt. */ - 210:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); - 158 .loc 1 210 0 - 159 00b2 1820 movs r0, #24 - 160 00b4 1449 ldr r1, .L2+32 - 161 00b6 FFF7FEFF bl CyIntSetVector - 162 .LVL12: - 211:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); - 163 .loc 1 211 0 - 164 00ba 1820 movs r0, #24 - 165 00bc 0721 movs r1, #7 - 166 00be FFF7FEFF bl CyIntSetPriority - 167 .LVL13: - 212:.\Generated_Source\PSoC5/USBFS.c **** - 213:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 1 Interrupt. */ - 214:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP1_ISR_REMOVE == 0u) - 215:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); - 168 .loc 1 215 0 - 169 00c2 2046 mov r0, r4 - 170 00c4 1149 ldr r1, .L2+36 - 171 00c6 FFF7FEFF bl CyIntSetVector - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 8 - - - 172 .LVL14: - 216:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); - 173 .loc 1 216 0 - 174 00ca 2046 mov r0, r4 - 175 00cc 0721 movs r1, #7 - 176 00ce FFF7FEFF bl CyIntSetPriority - 177 .LVL15: - 217:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP1_ISR_REMOVE */ - 218:.\Generated_Source\PSoC5/USBFS.c **** - 219:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 2 Interrupt. */ - 220:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP2_ISR_REMOVE == 0u) - 221:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); - 178 .loc 1 221 0 - 179 00d2 2846 mov r0, r5 - 180 00d4 0E49 ldr r1, .L2+40 - 181 00d6 FFF7FEFF bl CyIntSetVector - 182 .LVL16: - 222:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); - 183 .loc 1 222 0 - 184 00da 2846 mov r0, r5 - 185 00dc 0721 movs r1, #7 - 223:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP2_ISR_REMOVE */ - 224:.\Generated_Source\PSoC5/USBFS.c **** - 225:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 3 Interrupt. */ - 226:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP3_ISR_REMOVE == 0u) - 227:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); - 228:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); - 229:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP3_ISR_REMOVE */ - 230:.\Generated_Source\PSoC5/USBFS.c **** - 231:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 4 Interrupt. */ - 232:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP4_ISR_REMOVE == 0u) - 233:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); - 234:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); - 235:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP4_ISR_REMOVE */ - 236:.\Generated_Source\PSoC5/USBFS.c **** - 237:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 5 Interrupt. */ - 238:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP5_ISR_REMOVE == 0u) - 239:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); - 240:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); - 241:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP5_ISR_REMOVE */ - 242:.\Generated_Source\PSoC5/USBFS.c **** - 243:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 6 Interrupt. */ - 244:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP6_ISR_REMOVE == 0u) - 245:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); - 246:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); - 247:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP6_ISR_REMOVE */ - 248:.\Generated_Source\PSoC5/USBFS.c **** - 249:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 7 Interrupt. */ - 250:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP7_ISR_REMOVE == 0u) - 251:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); - 252:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); - 253:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP7_ISR_REMOVE */ - 254:.\Generated_Source\PSoC5/USBFS.c **** - 255:.\Generated_Source\PSoC5/USBFS.c **** /* Set the Data Endpoint 8 Interrupt. */ - 256:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP8_ISR_REMOVE == 0u) - 257:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); - 258:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 9 - - - 259:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP8_ISR_REMOVE */ - 260:.\Generated_Source\PSoC5/USBFS.c **** - 261:.\Generated_Source\PSoC5/USBFS.c **** #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) - 262:.\Generated_Source\PSoC5/USBFS.c **** /* Set the ARB Interrupt. */ - 263:.\Generated_Source\PSoC5/USBFS.c **** (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); - 264:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); - 265:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - 266:.\Generated_Source\PSoC5/USBFS.c **** - 267:.\Generated_Source\PSoC5/USBFS.c **** } - 186 .loc 1 267 0 - 187 00de BDE8F840 pop {r3, r4, r5, r6, r7, lr} - 222:.\Generated_Source\PSoC5/USBFS.c **** CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); - 188 .loc 1 222 0 - 189 00e2 FFF7FEBF b CyIntSetPriority - 190 .LVL17: - 191 .L3: - 192 00e6 00BF .align 2 - 193 .L2: - 194 00e8 A5430040 .word 1073759141 - 195 00ec 9D600040 .word 1073766557 - 196 00f0 94430040 .word 1073759124 - 197 00f4 12600040 .word 1073766418 - 198 00f8 F8510040 .word 1073762808 - 199 00fc 84600040 .word 1073766532 - 200 0100 00000000 .word USBFS_BUS_RESET_ISR - 201 0104 00000000 .word USBFS_SOF_ISR - 202 0108 00000000 .word USBFS_EP_0_ISR - 203 010c 00000000 .word USBFS_EP_1_ISR - 204 0110 00000000 .word USBFS_EP_2_ISR - 205 .cfi_endproc - 206 .LFE1: - 207 .size USBFS_Init, .-USBFS_Init - 208 .section .text.USBFS_InitComponent,"ax",%progbits - 209 .align 1 - 210 .global USBFS_InitComponent - 211 .thumb - 212 .thumb_func - 213 .type USBFS_InitComponent, %function - 214 USBFS_InitComponent: - 215 .LFB2: - 268:.\Generated_Source\PSoC5/USBFS.c **** - 269:.\Generated_Source\PSoC5/USBFS.c **** - 270:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 271:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_InitComponent - 272:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 273:.\Generated_Source\PSoC5/USBFS.c **** * - 274:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 275:.\Generated_Source\PSoC5/USBFS.c **** * Initialize the component, except for the HW which is done one time in - 276:.\Generated_Source\PSoC5/USBFS.c **** * the Start function. This function pulls up D+. - 277:.\Generated_Source\PSoC5/USBFS.c **** * - 278:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 279:.\Generated_Source\PSoC5/USBFS.c **** * device: Contains the device number of the desired device descriptor. - 280:.\Generated_Source\PSoC5/USBFS.c **** * The device number can be found in the Device Descriptor Tab of - 281:.\Generated_Source\PSoC5/USBFS.c **** * "Configure" dialog, under the settings of desired Device Descriptor, - 282:.\Generated_Source\PSoC5/USBFS.c **** * in the "Device Number" field. - 283:.\Generated_Source\PSoC5/USBFS.c **** * mode: The operating voltage. This determines whether the voltage regulator - 284:.\Generated_Source\PSoC5/USBFS.c **** * is enabled for 5V operation or if pass through mode is used for 3.3V - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 10 - - - 285:.\Generated_Source\PSoC5/USBFS.c **** * operation. Symbolic names and their associated values are given in the - 286:.\Generated_Source\PSoC5/USBFS.c **** * following table. - 287:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_3V_OPERATION - Disable voltage regulator and pass-thru - 288:.\Generated_Source\PSoC5/USBFS.c **** * Vcc for pull-up - 289:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_5V_OPERATION - Enable voltage regulator and use - 290:.\Generated_Source\PSoC5/USBFS.c **** * regulator for pull-up - 291:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage - 292:.\Generated_Source\PSoC5/USBFS.c **** * regulator depend on Vddd Voltage configuration in DWR. - 293:.\Generated_Source\PSoC5/USBFS.c **** * - 294:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 295:.\Generated_Source\PSoC5/USBFS.c **** * None. - 296:.\Generated_Source\PSoC5/USBFS.c **** * - 297:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: - 298:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_device: Contains the device number of the desired device - 299:.\Generated_Source\PSoC5/USBFS.c **** * descriptor. The device number can be found in the Device Descriptor Tab - 300:.\Generated_Source\PSoC5/USBFS.c **** * of "Configure" dialog, under the settings of desired Device Descriptor, - 301:.\Generated_Source\PSoC5/USBFS.c **** * in the "Device Number" field. - 302:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_transferState: This variable used by the communication - 303:.\Generated_Source\PSoC5/USBFS.c **** * functions to handle current transfer state. Initialized to - 304:.\Generated_Source\PSoC5/USBFS.c **** * TRANS_STATE_IDLE in this API. - 305:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_configuration: Contains current configuration number - 306:.\Generated_Source\PSoC5/USBFS.c **** * which is set by the Host using SET_CONFIGURATION request. - 307:.\Generated_Source\PSoC5/USBFS.c **** * Initialized to zero in this API. - 308:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceAddress: Contains current device address. This - 309:.\Generated_Source\PSoC5/USBFS.c **** * variable is initialized to zero in this API. Host starts to communicate - 310:.\Generated_Source\PSoC5/USBFS.c **** * to device with address 0 and then set it to whatever value using - 311:.\Generated_Source\PSoC5/USBFS.c **** * SET_ADDRESS request. - 312:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceStatus: initialized to 0. - 313:.\Generated_Source\PSoC5/USBFS.c **** * This is two bit variable which contain power status in first bit - 314:.\Generated_Source\PSoC5/USBFS.c **** * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote - 315:.\Generated_Source\PSoC5/USBFS.c **** * wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. - 316:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_lastPacketSize initialized to 0; - 317:.\Generated_Source\PSoC5/USBFS.c **** * - 318:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: - 319:.\Generated_Source\PSoC5/USBFS.c **** * No. - 320:.\Generated_Source\PSoC5/USBFS.c **** * - 321:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 322:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_InitComponent(uint8 device, uint8 mode) - 323:.\Generated_Source\PSoC5/USBFS.c **** { - 216 .loc 1 323 0 - 217 .cfi_startproc - 218 @ args = 0, pretend = 0, frame = 0 - 219 @ frame_needed = 0, uses_anonymous_args = 0 - 220 .LVL18: - 324:.\Generated_Source\PSoC5/USBFS.c **** /* Initialize _hidProtocol variable to comply with - 325:.\Generated_Source\PSoC5/USBFS.c **** * HID 7.2.6 Set_Protocol Request: - 326:.\Generated_Source\PSoC5/USBFS.c **** * "When initialized, all devices default to report protocol." - 327:.\Generated_Source\PSoC5/USBFS.c **** */ - 328:.\Generated_Source\PSoC5/USBFS.c **** #if defined(USBFS_ENABLE_HID_CLASS) - 329:.\Generated_Source\PSoC5/USBFS.c **** uint8 i; - 330:.\Generated_Source\PSoC5/USBFS.c **** - 331:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - 332:.\Generated_Source\PSoC5/USBFS.c **** { - 333:.\Generated_Source\PSoC5/USBFS.c **** USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; - 221 .loc 1 333 0 - 222 0000 184B ldr r3, .L11 - 223 0002 0122 movs r2, #1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 11 - - - 323:.\Generated_Source\PSoC5/USBFS.c **** { - 224 .loc 1 323 0 - 225 0004 10B5 push {r4, lr} - 226 .LCFI1: - 227 .cfi_def_cfa_offset 8 - 228 .cfi_offset 4, -8 - 229 .cfi_offset 14, -4 - 230 .loc 1 333 0 - 231 0006 1A70 strb r2, [r3, #0] - 232 .LVL19: - 334:.\Generated_Source\PSoC5/USBFS.c **** } - 335:.\Generated_Source\PSoC5/USBFS.c **** #endif /* USBFS_ENABLE_HID_CLASS */ - 336:.\Generated_Source\PSoC5/USBFS.c **** - 337:.\Generated_Source\PSoC5/USBFS.c **** /* Enable Interrupts. */ - 338:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_BUS_RESET_VECT_NUM); - 233 .loc 1 338 0 - 234 0008 174B ldr r3, .L11+4 - 235 000a 4FF40004 mov r4, #8388608 - 236 000e 1C60 str r4, [r3, #0] - 339:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_0_VECT_NUM); - 237 .loc 1 339 0 - 238 0010 4FF08074 mov r4, #16777216 - 239 0014 1C60 str r4, [r3, #0] - 340:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP1_ISR_REMOVE == 0u) - 341:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_1_VECT_NUM); - 240 .loc 1 341 0 - 241 0016 1A60 str r2, [r3, #0] - 342:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP1_ISR_REMOVE */ - 343:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP2_ISR_REMOVE == 0u) - 344:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_2_VECT_NUM); - 242 .loc 1 344 0 - 243 0018 0222 movs r2, #2 - 244 001a 1A60 str r2, [r3, #0] - 345:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP2_ISR_REMOVE */ - 346:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP3_ISR_REMOVE == 0u) - 347:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_3_VECT_NUM); - 348:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP3_ISR_REMOVE */ - 349:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP4_ISR_REMOVE == 0u) - 350:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_4_VECT_NUM); - 351:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP4_ISR_REMOVE */ - 352:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP5_ISR_REMOVE == 0u) - 353:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_5_VECT_NUM); - 354:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP5_ISR_REMOVE */ - 355:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP6_ISR_REMOVE == 0u) - 356:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_6_VECT_NUM); - 357:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP6_ISR_REMOVE */ - 358:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP7_ISR_REMOVE == 0u) - 359:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_7_VECT_NUM); - 360:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP7_ISR_REMOVE */ - 361:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP8_ISR_REMOVE == 0u) - 362:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_EP_8_VECT_NUM); - 363:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP8_ISR_REMOVE */ - 364:.\Generated_Source\PSoC5/USBFS.c **** #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) - 365:.\Generated_Source\PSoC5/USBFS.c **** /* usb arb interrupt enable */ - 366:.\Generated_Source\PSoC5/USBFS.c **** USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; - 367:.\Generated_Source\PSoC5/USBFS.c **** CyIntEnable(USBFS_ARB_VECT_NUM); - 368:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 12 - - - 369:.\Generated_Source\PSoC5/USBFS.c **** - 370:.\Generated_Source\PSoC5/USBFS.c **** /* Arbiter configuration for DMA transfers */ - 371:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_MANUAL) - 372:.\Generated_Source\PSoC5/USBFS.c **** - 373:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - 374:.\Generated_Source\PSoC5/USBFS.c **** USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; - 375:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - 376:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - 377:.\Generated_Source\PSoC5/USBFS.c **** /*Set cfg cmplt this rises DMA request when the full configuration is done */ - 378:.\Generated_Source\PSoC5/USBFS.c **** USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - 379:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - 380:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - 381:.\Generated_Source\PSoC5/USBFS.c **** - 382:.\Generated_Source\PSoC5/USBFS.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 245 .loc 1 382 0 - 246 001c 134B ldr r3, .L11+8 - 247 001e 0024 movs r4, #0 - 248 0020 1C70 strb r4, [r3, #0] - 249 0022 134B ldr r3, .L11+12 - 383:.\Generated_Source\PSoC5/USBFS.c **** - 384:.\Generated_Source\PSoC5/USBFS.c **** /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/ - 385:.\Generated_Source\PSoC5/USBFS.c **** switch(mode) - 250 .loc 1 385 0 - 251 0024 01B1 cbz r1, .L9 - 252 0026 0322 movs r2, #3 - 253 .L9: - 386:.\Generated_Source\PSoC5/USBFS.c **** { - 387:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_3V_OPERATION: - 388:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - 389:.\Generated_Source\PSoC5/USBFS.c **** break; - 390:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_5V_OPERATION: - 391:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; - 392:.\Generated_Source\PSoC5/USBFS.c **** break; - 393:.\Generated_Source\PSoC5/USBFS.c **** default: /*USBFS_DWR_VDDD_OPERATION */ - 394:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_VDDD_MV < USBFS_3500MV) - 395:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - 396:.\Generated_Source\PSoC5/USBFS.c **** #else - 397:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; - 398:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_VDDD_MV < USBFS_3500MV */ - 399:.\Generated_Source\PSoC5/USBFS.c **** break; - 400:.\Generated_Source\PSoC5/USBFS.c **** } - 401:.\Generated_Source\PSoC5/USBFS.c **** - 402:.\Generated_Source\PSoC5/USBFS.c **** /* Record the descriptor selection */ - 403:.\Generated_Source\PSoC5/USBFS.c **** USBFS_device = device; - 254 .loc 1 403 0 - 255 0028 1249 ldr r1, .L11+16 - 256 .LVL20: - 397:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; - 257 .loc 1 397 0 - 258 002a 1A70 strb r2, [r3, #0] - 404:.\Generated_Source\PSoC5/USBFS.c **** - 405:.\Generated_Source\PSoC5/USBFS.c **** /* Clear all of the component data */ - 406:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; - 259 .loc 1 406 0 - 260 002c 124B ldr r3, .L11+20 - 403:.\Generated_Source\PSoC5/USBFS.c **** USBFS_device = device; - 261 .loc 1 403 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 13 - - - 262 002e 0870 strb r0, [r1, #0] - 407:.\Generated_Source\PSoC5/USBFS.c **** USBFS_interfaceNumber = 0u; - 263 .loc 1 407 0 - 264 0030 124A ldr r2, .L11+24 - 406:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; - 265 .loc 1 406 0 - 266 0032 0020 movs r0, #0 - 267 .LVL21: - 408:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; - 268 .loc 1 408 0 - 269 0034 1249 ldr r1, .L11+28 - 270 .LVL22: - 406:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; - 271 .loc 1 406 0 - 272 0036 1870 strb r0, [r3, #0] - 409:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceAddress = 0u; - 273 .loc 1 409 0 - 274 0038 124B ldr r3, .L11+32 - 407:.\Generated_Source\PSoC5/USBFS.c **** USBFS_interfaceNumber = 0u; - 275 .loc 1 407 0 - 276 003a 1070 strb r0, [r2, #0] - 408:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; - 277 .loc 1 408 0 - 278 003c 0870 strb r0, [r1, #0] - 410:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus = 0u; - 279 .loc 1 410 0 - 280 003e 124A ldr r2, .L11+36 - 411:.\Generated_Source\PSoC5/USBFS.c **** - 412:.\Generated_Source\PSoC5/USBFS.c **** USBFS_lastPacketSize = 0u; - 281 .loc 1 412 0 - 282 0040 1249 ldr r1, .L11+40 - 409:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceAddress = 0u; - 283 .loc 1 409 0 - 284 0042 1870 strb r0, [r3, #0] - 413:.\Generated_Source\PSoC5/USBFS.c **** - 414:.\Generated_Source\PSoC5/USBFS.c **** /* ACK Setup, Stall IN/OUT */ - 415:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - 285 .loc 1 415 0 - 286 0044 124B ldr r3, .L11+44 - 410:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus = 0u; - 287 .loc 1 410 0 - 288 0046 1070 strb r0, [r2, #0] - 412:.\Generated_Source\PSoC5/USBFS.c **** USBFS_lastPacketSize = 0u; - 289 .loc 1 412 0 - 290 0048 0870 strb r0, [r1, #0] - 416:.\Generated_Source\PSoC5/USBFS.c **** - 417:.\Generated_Source\PSoC5/USBFS.c **** /* Enable the SIE with an address 0 */ - 418:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); - 291 .loc 1 418 0 - 292 004a 8022 movs r2, #128 - 415:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - 293 .loc 1 415 0 - 294 004c 0320 movs r0, #3 - 295 004e 1870 strb r0, [r3, #0] - 419:.\Generated_Source\PSoC5/USBFS.c **** - 420:.\Generated_Source\PSoC5/USBFS.c **** /* Workaround for PSOC5LP */ - 421:.\Generated_Source\PSoC5/USBFS.c **** CyDelayCycles(1u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 14 - - - 296 .loc 1 421 0 - 297 0050 0120 movs r0, #1 - 418:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); - 298 .loc 1 418 0 - 299 0052 03F8202C strb r2, [r3, #-32] - 300 .loc 1 421 0 - 301 0056 FFF7FEFF bl CyDelayCycles - 302 .LVL23: - 422:.\Generated_Source\PSoC5/USBFS.c **** - 423:.\Generated_Source\PSoC5/USBFS.c **** /* Finally, Enable d+ pullup and select iomode to USB mode*/ - 424:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); - 303 .loc 1 424 0 - 304 005a 0E48 ldr r0, .L11+48 - 305 005c 0421 movs r1, #4 - 306 005e 0170 strb r1, [r0, #0] - 307 0060 10BD pop {r4, pc} - 308 .L12: - 309 0062 00BF .align 2 - 310 .L11: - 311 0064 00000000 .word USBFS_hidProtocol - 312 0068 00E100E0 .word -536813312 - 313 006c 00000000 .word USBFS_transferState - 314 0070 09600040 .word 1073766409 - 315 0074 00000000 .word USBFS_device - 316 0078 00000000 .word USBFS_configuration - 317 007c 00000000 .word USBFS_interfaceNumber - 318 0080 00000000 .word USBFS_configurationChanged - 319 0084 00000000 .word USBFS_deviceAddress - 320 0088 00000000 .word USBFS_deviceStatus - 321 008c 00000000 .word USBFS_lastPacketSize - 322 0090 28600040 .word 1073766440 - 323 0094 12600040 .word 1073766418 - 324 .cfi_endproc - 325 .LFE2: - 326 .size USBFS_InitComponent, .-USBFS_InitComponent - 327 .section .text.USBFS_Start,"ax",%progbits - 328 .align 1 - 329 .global USBFS_Start - 330 .thumb - 331 .thumb_func - 332 .type USBFS_Start, %function - 333 USBFS_Start: - 334 .LFB0: - 107:.\Generated_Source\PSoC5/USBFS.c **** { - 335 .loc 1 107 0 - 336 .cfi_startproc - 337 @ args = 0, pretend = 0, frame = 0 - 338 @ frame_needed = 0, uses_anonymous_args = 0 - 339 .LVL24: - 340 0000 70B5 push {r4, r5, r6, lr} - 341 .LCFI2: - 342 .cfi_def_cfa_offset 16 - 343 .cfi_offset 4, -16 - 344 .cfi_offset 5, -12 - 345 .cfi_offset 6, -8 - 346 .cfi_offset 14, -4 - 109:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_initVar == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 15 - - - 347 .loc 1 109 0 - 348 0002 074C ldr r4, .L15 - 107:.\Generated_Source\PSoC5/USBFS.c **** { - 349 .loc 1 107 0 - 350 0004 0646 mov r6, r0 - 109:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_initVar == 0u) - 351 .loc 1 109 0 - 352 0006 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 107:.\Generated_Source\PSoC5/USBFS.c **** { - 353 .loc 1 107 0 - 354 0008 0D46 mov r5, r1 - 109:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_initVar == 0u) - 355 .loc 1 109 0 - 356 000a 1BB9 cbnz r3, .L14 - 111:.\Generated_Source\PSoC5/USBFS.c **** USBFS_Init(); - 357 .loc 1 111 0 - 358 000c FFF7FEFF bl USBFS_Init - 359 .LVL25: - 112:.\Generated_Source\PSoC5/USBFS.c **** USBFS_initVar = 1u; - 360 .loc 1 112 0 - 361 0010 0120 movs r0, #1 - 362 0012 2070 strb r0, [r4, #0] - 363 .L14: - 114:.\Generated_Source\PSoC5/USBFS.c **** USBFS_InitComponent(device, mode); - 364 .loc 1 114 0 - 365 0014 3046 mov r0, r6 - 366 0016 2946 mov r1, r5 - 115:.\Generated_Source\PSoC5/USBFS.c **** } - 367 .loc 1 115 0 - 368 0018 BDE87040 pop {r4, r5, r6, lr} - 114:.\Generated_Source\PSoC5/USBFS.c **** USBFS_InitComponent(device, mode); - 369 .loc 1 114 0 - 370 001c FFF7FEBF b USBFS_InitComponent - 371 .LVL26: - 372 .L16: - 373 .align 2 - 374 .L15: - 375 0020 00000000 .word .LANCHOR0 - 376 .cfi_endproc - 377 .LFE0: - 378 .size USBFS_Start, .-USBFS_Start - 379 .section .text.USBFS_ReInitComponent,"ax",%progbits - 380 .align 1 - 381 .global USBFS_ReInitComponent - 382 .thumb - 383 .thumb_func - 384 .type USBFS_ReInitComponent, %function - 385 USBFS_ReInitComponent: - 386 .LFB3: - 425:.\Generated_Source\PSoC5/USBFS.c **** } - 426:.\Generated_Source\PSoC5/USBFS.c **** - 427:.\Generated_Source\PSoC5/USBFS.c **** - 428:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 429:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_ReInitComponent - 430:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 431:.\Generated_Source\PSoC5/USBFS.c **** * - 432:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 16 - - - 433:.\Generated_Source\PSoC5/USBFS.c **** * This function reinitialize the component configuration and is - 434:.\Generated_Source\PSoC5/USBFS.c **** * intend to be called from the Reset interrupt. - 435:.\Generated_Source\PSoC5/USBFS.c **** * - 436:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 437:.\Generated_Source\PSoC5/USBFS.c **** * None. - 438:.\Generated_Source\PSoC5/USBFS.c **** * - 439:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 440:.\Generated_Source\PSoC5/USBFS.c **** * None. - 441:.\Generated_Source\PSoC5/USBFS.c **** * - 442:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: - 443:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_device: Contains the device number of the desired device - 444:.\Generated_Source\PSoC5/USBFS.c **** * descriptor. The device number can be found in the Device Descriptor Tab - 445:.\Generated_Source\PSoC5/USBFS.c **** * of "Configure" dialog, under the settings of desired Device Descriptor, - 446:.\Generated_Source\PSoC5/USBFS.c **** * in the "Device Number" field. - 447:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_transferState: This variable used by the communication - 448:.\Generated_Source\PSoC5/USBFS.c **** * functions to handle current transfer state. Initialized to - 449:.\Generated_Source\PSoC5/USBFS.c **** * TRANS_STATE_IDLE in this API. - 450:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_configuration: Contains current configuration number - 451:.\Generated_Source\PSoC5/USBFS.c **** * which is set by the Host using SET_CONFIGURATION request. - 452:.\Generated_Source\PSoC5/USBFS.c **** * Initialized to zero in this API. - 453:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceAddress: Contains current device address. This - 454:.\Generated_Source\PSoC5/USBFS.c **** * variable is initialized to zero in this API. Host starts to communicate - 455:.\Generated_Source\PSoC5/USBFS.c **** * to device with address 0 and then set it to whatever value using - 456:.\Generated_Source\PSoC5/USBFS.c **** * SET_ADDRESS request. - 457:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceStatus: initialized to 0. - 458:.\Generated_Source\PSoC5/USBFS.c **** * This is two bit variable which contain power status in first bit - 459:.\Generated_Source\PSoC5/USBFS.c **** * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote - 460:.\Generated_Source\PSoC5/USBFS.c **** * wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. - 461:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_lastPacketSize initialized to 0; - 462:.\Generated_Source\PSoC5/USBFS.c **** * - 463:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: - 464:.\Generated_Source\PSoC5/USBFS.c **** * No. - 465:.\Generated_Source\PSoC5/USBFS.c **** * - 466:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 467:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_ReInitComponent(void) - 468:.\Generated_Source\PSoC5/USBFS.c **** { - 387 .loc 1 468 0 - 388 .cfi_startproc - 389 @ args = 0, pretend = 0, frame = 0 - 390 @ frame_needed = 0, uses_anonymous_args = 0 - 391 @ link register save eliminated. - 392 .LVL27: - 469:.\Generated_Source\PSoC5/USBFS.c **** /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol - 470:.\Generated_Source\PSoC5/USBFS.c **** * Request: "When initialized, all devices default to report protocol." - 471:.\Generated_Source\PSoC5/USBFS.c **** */ - 472:.\Generated_Source\PSoC5/USBFS.c **** #if defined(USBFS_ENABLE_HID_CLASS) - 473:.\Generated_Source\PSoC5/USBFS.c **** uint8 i; - 474:.\Generated_Source\PSoC5/USBFS.c **** - 475:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - 476:.\Generated_Source\PSoC5/USBFS.c **** { - 477:.\Generated_Source\PSoC5/USBFS.c **** USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; - 393 .loc 1 477 0 - 394 0000 0C4B ldr r3, .L18 - 395 0002 0122 movs r2, #1 - 478:.\Generated_Source\PSoC5/USBFS.c **** } - 479:.\Generated_Source\PSoC5/USBFS.c **** #endif /* USBFS_ENABLE_HID_CLASS */ - 480:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 17 - - - 481:.\Generated_Source\PSoC5/USBFS.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 396 .loc 1 481 0 - 397 0004 0C49 ldr r1, .L18+4 - 477:.\Generated_Source\PSoC5/USBFS.c **** USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; - 398 .loc 1 477 0 - 399 0006 1A70 strb r2, [r3, #0] - 400 .LVL28: - 401 .loc 1 481 0 - 402 0008 0020 movs r0, #0 - 482:.\Generated_Source\PSoC5/USBFS.c **** - 483:.\Generated_Source\PSoC5/USBFS.c **** /* Clear all of the component data */ - 484:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; - 403 .loc 1 484 0 - 404 000a 0C4A ldr r2, .L18+8 - 485:.\Generated_Source\PSoC5/USBFS.c **** USBFS_interfaceNumber = 0u; - 405 .loc 1 485 0 - 406 000c 0C4B ldr r3, .L18+12 - 481:.\Generated_Source\PSoC5/USBFS.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 407 .loc 1 481 0 - 408 000e 0870 strb r0, [r1, #0] - 486:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; - 409 .loc 1 486 0 - 410 0010 0C49 ldr r1, .L18+16 - 484:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; - 411 .loc 1 484 0 - 412 0012 1070 strb r0, [r2, #0] - 485:.\Generated_Source\PSoC5/USBFS.c **** USBFS_interfaceNumber = 0u; - 413 .loc 1 485 0 - 414 0014 1870 strb r0, [r3, #0] - 487:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceAddress = 0u; - 415 .loc 1 487 0 - 416 0016 0C4A ldr r2, .L18+20 - 488:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus = 0u; - 417 .loc 1 488 0 - 418 0018 0C4B ldr r3, .L18+24 - 486:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; - 419 .loc 1 486 0 - 420 001a 0870 strb r0, [r1, #0] - 489:.\Generated_Source\PSoC5/USBFS.c **** - 490:.\Generated_Source\PSoC5/USBFS.c **** USBFS_lastPacketSize = 0u; - 421 .loc 1 490 0 - 422 001c 0C49 ldr r1, .L18+28 - 487:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceAddress = 0u; - 423 .loc 1 487 0 - 424 001e 1070 strb r0, [r2, #0] - 488:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus = 0u; - 425 .loc 1 488 0 - 426 0020 1870 strb r0, [r3, #0] - 491:.\Generated_Source\PSoC5/USBFS.c **** - 492:.\Generated_Source\PSoC5/USBFS.c **** - 493:.\Generated_Source\PSoC5/USBFS.c **** /* ACK Setup, Stall IN/OUT */ - 494:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - 427 .loc 1 494 0 - 428 0022 0C4B ldr r3, .L18+32 - 490:.\Generated_Source\PSoC5/USBFS.c **** USBFS_lastPacketSize = 0u; - 429 .loc 1 490 0 - 430 0024 0870 strb r0, [r1, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 18 - - - 495:.\Generated_Source\PSoC5/USBFS.c **** - 496:.\Generated_Source\PSoC5/USBFS.c **** /* Enable the SIE with an address 0 */ - 497:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); - 431 .loc 1 497 0 - 432 0026 8022 movs r2, #128 - 494:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - 433 .loc 1 494 0 - 434 0028 0320 movs r0, #3 - 435 002a 1870 strb r0, [r3, #0] - 436 .loc 1 497 0 - 437 002c 03F8202C strb r2, [r3, #-32] - 438 0030 7047 bx lr - 439 .L19: - 440 0032 00BF .align 2 - 441 .L18: - 442 0034 00000000 .word USBFS_hidProtocol - 443 0038 00000000 .word USBFS_transferState - 444 003c 00000000 .word USBFS_configuration - 445 0040 00000000 .word USBFS_interfaceNumber - 446 0044 00000000 .word USBFS_configurationChanged - 447 0048 00000000 .word USBFS_deviceAddress - 448 004c 00000000 .word USBFS_deviceStatus - 449 0050 00000000 .word USBFS_lastPacketSize - 450 0054 28600040 .word 1073766440 - 451 .cfi_endproc - 452 .LFE3: - 453 .size USBFS_ReInitComponent, .-USBFS_ReInitComponent - 454 .section .text.USBFS_Stop,"ax",%progbits - 455 .align 1 - 456 .global USBFS_Stop - 457 .thumb - 458 .thumb_func - 459 .type USBFS_Stop, %function - 460 USBFS_Stop: - 461 .LFB4: - 498:.\Generated_Source\PSoC5/USBFS.c **** - 499:.\Generated_Source\PSoC5/USBFS.c **** } - 500:.\Generated_Source\PSoC5/USBFS.c **** - 501:.\Generated_Source\PSoC5/USBFS.c **** - 502:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 503:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_Stop - 504:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 505:.\Generated_Source\PSoC5/USBFS.c **** * - 506:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 507:.\Generated_Source\PSoC5/USBFS.c **** * This function shuts down the USB function including to release - 508:.\Generated_Source\PSoC5/USBFS.c **** * the D+ Pullup and disabling the SIE. - 509:.\Generated_Source\PSoC5/USBFS.c **** * - 510:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 511:.\Generated_Source\PSoC5/USBFS.c **** * None. - 512:.\Generated_Source\PSoC5/USBFS.c **** * - 513:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 514:.\Generated_Source\PSoC5/USBFS.c **** * None. - 515:.\Generated_Source\PSoC5/USBFS.c **** * - 516:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: - 517:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_configuration: Contains current configuration number - 518:.\Generated_Source\PSoC5/USBFS.c **** * which is set by the Host using SET_CONFIGURATION request. - 519:.\Generated_Source\PSoC5/USBFS.c **** * Initialized to zero in this API. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 19 - - - 520:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceAddress: Contains current device address. This - 521:.\Generated_Source\PSoC5/USBFS.c **** * variable is initialized to zero in this API. Host starts to communicate - 522:.\Generated_Source\PSoC5/USBFS.c **** * to device with address 0 and then set it to whatever value using - 523:.\Generated_Source\PSoC5/USBFS.c **** * SET_ADDRESS request. - 524:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceStatus: initialized to 0. - 525:.\Generated_Source\PSoC5/USBFS.c **** * This is two bit variable which contain power status in first bit - 526:.\Generated_Source\PSoC5/USBFS.c **** * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote - 527:.\Generated_Source\PSoC5/USBFS.c **** * wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. - 528:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_configurationChanged: This variable is set to one after - 529:.\Generated_Source\PSoC5/USBFS.c **** * SET_CONFIGURATION request and cleared in this function. - 530:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_intiVar variable is set to zero - 531:.\Generated_Source\PSoC5/USBFS.c **** * - 532:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 533:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_Stop(void) - 534:.\Generated_Source\PSoC5/USBFS.c **** { - 462 .loc 1 534 0 - 463 .cfi_startproc - 464 @ args = 0, pretend = 0, frame = 0 - 465 @ frame_needed = 0, uses_anonymous_args = 0 - 466 @ link register save eliminated. - 535:.\Generated_Source\PSoC5/USBFS.c **** - 536:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_MANUAL) - 537:.\Generated_Source\PSoC5/USBFS.c **** USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ - 538:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - 539:.\Generated_Source\PSoC5/USBFS.c **** - 540:.\Generated_Source\PSoC5/USBFS.c **** /* Disable the SIE */ - 541:.\Generated_Source\PSoC5/USBFS.c **** USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE); - 467 .loc 1 541 0 - 468 0000 154B ldr r3, .L21 - 469 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 470 0004 02F07F00 and r0, r2, #127 - 471 0008 1870 strb r0, [r3, #0] - 542:.\Generated_Source\PSoC5/USBFS.c **** /* Disable the d+ pullup */ - 543:.\Generated_Source\PSoC5/USBFS.c **** USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN); - 472 .loc 1 543 0 - 473 000a 997A ldrb r1, [r3, #10] @ zero_extendqisi2 - 474 000c 01F0FB02 and r2, r1, #251 - 475 0010 9A72 strb r2, [r3, #10] - 544:.\Generated_Source\PSoC5/USBFS.c **** /* Disable USB in ACT PM */ - 545:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB); - 476 .loc 1 545 0 - 477 0012 124B ldr r3, .L21+4 - 478 0014 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 479 0016 00F0FE01 and r1, r0, #254 - 480 001a 1970 strb r1, [r3, #0] - 546:.\Generated_Source\PSoC5/USBFS.c **** /* Disable USB block for Standby Power Mode */ - 547:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); - 481 .loc 1 547 0 - 482 001c 1A7C ldrb r2, [r3, #16] @ zero_extendqisi2 - 548:.\Generated_Source\PSoC5/USBFS.c **** - 549:.\Generated_Source\PSoC5/USBFS.c **** /* Disable the reset and EP interrupts */ - 550:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_BUS_RESET_VECT_NUM); - 483 .loc 1 550 0 - 484 001e 4FF40001 mov r1, #8388608 - 547:.\Generated_Source\PSoC5/USBFS.c **** USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); - 485 .loc 1 547 0 - 486 0022 02F0FE00 and r0, r2, #254 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 20 - - - 487 0026 1874 strb r0, [r3, #16] - 488 .loc 1 550 0 - 489 0028 0D4B ldr r3, .L21+8 - 551:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_0_VECT_NUM); - 490 .loc 1 551 0 - 491 002a 4FF08072 mov r2, #16777216 - 550:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_BUS_RESET_VECT_NUM); - 492 .loc 1 550 0 - 493 002e 1960 str r1, [r3, #0] - 552:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP1_ISR_REMOVE == 0u) - 553:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_1_VECT_NUM); - 494 .loc 1 553 0 - 495 0030 0120 movs r0, #1 - 554:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP1_ISR_REMOVE */ - 555:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP2_ISR_REMOVE == 0u) - 556:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_2_VECT_NUM); - 496 .loc 1 556 0 - 497 0032 0221 movs r1, #2 - 551:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_0_VECT_NUM); - 498 .loc 1 551 0 - 499 0034 1A60 str r2, [r3, #0] - 553:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_1_VECT_NUM); - 500 .loc 1 553 0 - 501 0036 1860 str r0, [r3, #0] - 557:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP2_ISR_REMOVE */ - 558:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP3_ISR_REMOVE == 0u) - 559:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_3_VECT_NUM); - 560:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP3_ISR_REMOVE */ - 561:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP4_ISR_REMOVE == 0u) - 562:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_4_VECT_NUM); - 563:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP4_ISR_REMOVE */ - 564:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP5_ISR_REMOVE == 0u) - 565:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_5_VECT_NUM); - 566:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP5_ISR_REMOVE */ - 567:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP6_ISR_REMOVE == 0u) - 568:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_6_VECT_NUM); - 569:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP6_ISR_REMOVE */ - 570:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP7_ISR_REMOVE == 0u) - 571:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_7_VECT_NUM); - 572:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP7_ISR_REMOVE */ - 573:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP8_ISR_REMOVE == 0u) - 574:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_8_VECT_NUM); - 575:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP8_ISR_REMOVE */ - 576:.\Generated_Source\PSoC5/USBFS.c **** - 577:.\Generated_Source\PSoC5/USBFS.c **** /* Clear all of the component data */ - 578:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; - 502 .loc 1 578 0 - 503 0038 0A4A ldr r2, .L21+12 - 556:.\Generated_Source\PSoC5/USBFS.c **** CyIntDisable(USBFS_EP_2_VECT_NUM); - 504 .loc 1 556 0 - 505 003a 1960 str r1, [r3, #0] - 579:.\Generated_Source\PSoC5/USBFS.c **** USBFS_interfaceNumber = 0u; - 506 .loc 1 579 0 - 507 003c 0A48 ldr r0, .L21+16 - 580:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; - 508 .loc 1 580 0 - 509 003e 0B49 ldr r1, .L21+20 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 21 - - - 578:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configuration = 0u; - 510 .loc 1 578 0 - 511 0040 0023 movs r3, #0 - 512 0042 1370 strb r3, [r2, #0] - 579:.\Generated_Source\PSoC5/USBFS.c **** USBFS_interfaceNumber = 0u; - 513 .loc 1 579 0 - 514 0044 0370 strb r3, [r0, #0] - 581:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceAddress = 0u; - 515 .loc 1 581 0 - 516 0046 0A4A ldr r2, .L21+24 - 580:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; - 517 .loc 1 580 0 - 518 0048 0B70 strb r3, [r1, #0] - 582:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus = 0u; - 519 .loc 1 582 0 - 520 004a 0A48 ldr r0, .L21+28 - 583:.\Generated_Source\PSoC5/USBFS.c **** USBFS_initVar = 0u; - 521 .loc 1 583 0 - 522 004c 0A49 ldr r1, .L21+32 - 581:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceAddress = 0u; - 523 .loc 1 581 0 - 524 004e 1370 strb r3, [r2, #0] - 525 .loc 1 583 0 - 526 0050 0B70 strb r3, [r1, #0] - 582:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus = 0u; - 527 .loc 1 582 0 - 528 0052 0370 strb r3, [r0, #0] - 529 .loc 1 583 0 - 530 0054 7047 bx lr - 531 .L22: - 532 0056 00BF .align 2 - 533 .L21: - 534 0058 08600040 .word 1073766408 - 535 005c A5430040 .word 1073759141 - 536 0060 80E100E0 .word -536813184 - 537 0064 00000000 .word USBFS_configuration - 538 0068 00000000 .word USBFS_interfaceNumber - 539 006c 00000000 .word USBFS_configurationChanged - 540 0070 00000000 .word USBFS_deviceAddress - 541 0074 00000000 .word USBFS_deviceStatus - 542 0078 00000000 .word .LANCHOR0 - 543 .cfi_endproc - 544 .LFE4: - 545 .size USBFS_Stop, .-USBFS_Stop - 546 .section .text.USBFS_CheckActivity,"ax",%progbits - 547 .align 1 - 548 .global USBFS_CheckActivity - 549 .thumb - 550 .thumb_func - 551 .type USBFS_CheckActivity, %function - 552 USBFS_CheckActivity: - 553 .LFB5: - 584:.\Generated_Source\PSoC5/USBFS.c **** - 585:.\Generated_Source\PSoC5/USBFS.c **** } - 586:.\Generated_Source\PSoC5/USBFS.c **** - 587:.\Generated_Source\PSoC5/USBFS.c **** - 588:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 22 - - - 589:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_CheckActivity - 590:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 591:.\Generated_Source\PSoC5/USBFS.c **** * - 592:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 593:.\Generated_Source\PSoC5/USBFS.c **** * Returns the activity status of the bus. Clears the status hardware to - 594:.\Generated_Source\PSoC5/USBFS.c **** * provide fresh activity status on the next call of this routine. - 595:.\Generated_Source\PSoC5/USBFS.c **** * - 596:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 597:.\Generated_Source\PSoC5/USBFS.c **** * None. - 598:.\Generated_Source\PSoC5/USBFS.c **** * - 599:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 600:.\Generated_Source\PSoC5/USBFS.c **** * 1 - If bus activity was detected since the last call to this function - 601:.\Generated_Source\PSoC5/USBFS.c **** * 0 - If bus activity not was detected since the last call to this function - 602:.\Generated_Source\PSoC5/USBFS.c **** * - 603:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 604:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_CheckActivity(void) - 605:.\Generated_Source\PSoC5/USBFS.c **** { - 554 .loc 1 605 0 - 555 .cfi_startproc - 556 @ args = 0, pretend = 0, frame = 0 - 557 @ frame_needed = 0, uses_anonymous_args = 0 - 558 @ link register save eliminated. - 606:.\Generated_Source\PSoC5/USBFS.c **** uint8 r; - 607:.\Generated_Source\PSoC5/USBFS.c **** - 608:.\Generated_Source\PSoC5/USBFS.c **** r = CY_GET_REG8(USBFS_CR1_PTR); - 559 .loc 1 608 0 - 560 0000 034B ldr r3, .L24 - 561 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 562 .LVL29: - 609:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY)))); - 563 .loc 1 609 0 - 564 0004 00F0FB02 and r2, r0, #251 - 565 0008 1A70 strb r2, [r3, #0] - 610:.\Generated_Source\PSoC5/USBFS.c **** - 611:.\Generated_Source\PSoC5/USBFS.c **** return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT); - 612:.\Generated_Source\PSoC5/USBFS.c **** } - 566 .loc 1 612 0 - 567 000a C0F38000 ubfx r0, r0, #2, #1 - 568 .LVL30: - 569 000e 7047 bx lr - 570 .L25: - 571 .align 2 - 572 .L24: - 573 0010 09600040 .word 1073766409 - 574 .cfi_endproc - 575 .LFE5: - 576 .size USBFS_CheckActivity, .-USBFS_CheckActivity - 577 .section .text.USBFS_GetConfiguration,"ax",%progbits - 578 .align 1 - 579 .global USBFS_GetConfiguration - 580 .thumb - 581 .thumb_func - 582 .type USBFS_GetConfiguration, %function - 583 USBFS_GetConfiguration: - 584 .LFB6: - 613:.\Generated_Source\PSoC5/USBFS.c **** - 614:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 23 - - - 615:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 616:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_GetConfiguration - 617:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 618:.\Generated_Source\PSoC5/USBFS.c **** * - 619:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 620:.\Generated_Source\PSoC5/USBFS.c **** * Returns the current configuration setting - 621:.\Generated_Source\PSoC5/USBFS.c **** * - 622:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 623:.\Generated_Source\PSoC5/USBFS.c **** * None. - 624:.\Generated_Source\PSoC5/USBFS.c **** * - 625:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 626:.\Generated_Source\PSoC5/USBFS.c **** * configuration. - 627:.\Generated_Source\PSoC5/USBFS.c **** * - 628:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 629:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_GetConfiguration(void) - 630:.\Generated_Source\PSoC5/USBFS.c **** { - 585 .loc 1 630 0 - 586 .cfi_startproc - 587 @ args = 0, pretend = 0, frame = 0 - 588 @ frame_needed = 0, uses_anonymous_args = 0 - 589 @ link register save eliminated. - 631:.\Generated_Source\PSoC5/USBFS.c **** return(USBFS_configuration); - 590 .loc 1 631 0 - 591 0000 014B ldr r3, .L27 - 592 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 632:.\Generated_Source\PSoC5/USBFS.c **** } - 593 .loc 1 632 0 - 594 0004 7047 bx lr - 595 .L28: - 596 0006 00BF .align 2 - 597 .L27: - 598 0008 00000000 .word USBFS_configuration - 599 .cfi_endproc - 600 .LFE6: - 601 .size USBFS_GetConfiguration, .-USBFS_GetConfiguration - 602 .section .text.USBFS_IsConfigurationChanged,"ax",%progbits - 603 .align 1 - 604 .global USBFS_IsConfigurationChanged - 605 .thumb - 606 .thumb_func - 607 .type USBFS_IsConfigurationChanged, %function - 608 USBFS_IsConfigurationChanged: - 609 .LFB7: - 633:.\Generated_Source\PSoC5/USBFS.c **** - 634:.\Generated_Source\PSoC5/USBFS.c **** - 635:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 636:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_IsConfigurationChanged - 637:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 638:.\Generated_Source\PSoC5/USBFS.c **** * - 639:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 640:.\Generated_Source\PSoC5/USBFS.c **** * Returns the clear on read configuration state. It is usefull when PC send - 641:.\Generated_Source\PSoC5/USBFS.c **** * double SET_CONFIGURATION request with same configuration number. - 642:.\Generated_Source\PSoC5/USBFS.c **** * - 643:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 644:.\Generated_Source\PSoC5/USBFS.c **** * None. - 645:.\Generated_Source\PSoC5/USBFS.c **** * - 646:.\Generated_Source\PSoC5/USBFS.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 24 - - - 647:.\Generated_Source\PSoC5/USBFS.c **** * Not zero value when new configuration has been changed, otherwise zero is - 648:.\Generated_Source\PSoC5/USBFS.c **** * returned. - 649:.\Generated_Source\PSoC5/USBFS.c **** * - 650:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: - 651:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_configurationChanged: This variable is set to one after - 652:.\Generated_Source\PSoC5/USBFS.c **** * SET_CONFIGURATION request and cleared in this function. - 653:.\Generated_Source\PSoC5/USBFS.c **** * - 654:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 655:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_IsConfigurationChanged(void) - 656:.\Generated_Source\PSoC5/USBFS.c **** { - 610 .loc 1 656 0 - 611 .cfi_startproc - 612 @ args = 0, pretend = 0, frame = 0 - 613 @ frame_needed = 0, uses_anonymous_args = 0 - 614 @ link register save eliminated. - 615 .LVL31: - 657:.\Generated_Source\PSoC5/USBFS.c **** uint8 res = 0u; - 658:.\Generated_Source\PSoC5/USBFS.c **** - 659:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_configurationChanged != 0u) - 616 .loc 1 659 0 - 617 0000 034B ldr r3, .L32 - 618 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 619 0004 10B1 cbz r0, .L30 - 660:.\Generated_Source\PSoC5/USBFS.c **** { - 661:.\Generated_Source\PSoC5/USBFS.c **** res = USBFS_configurationChanged; - 662:.\Generated_Source\PSoC5/USBFS.c **** USBFS_configurationChanged = 0u; - 620 .loc 1 662 0 - 621 0006 0022 movs r2, #0 - 661:.\Generated_Source\PSoC5/USBFS.c **** res = USBFS_configurationChanged; - 622 .loc 1 661 0 - 623 0008 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 624 .LVL32: - 625 .loc 1 662 0 - 626 000a 1A70 strb r2, [r3, #0] - 627 .LVL33: - 628 .L30: - 663:.\Generated_Source\PSoC5/USBFS.c **** } - 664:.\Generated_Source\PSoC5/USBFS.c **** - 665:.\Generated_Source\PSoC5/USBFS.c **** return(res); - 666:.\Generated_Source\PSoC5/USBFS.c **** } - 629 .loc 1 666 0 - 630 000c 7047 bx lr - 631 .L33: - 632 000e 00BF .align 2 - 633 .L32: - 634 0010 00000000 .word USBFS_configurationChanged - 635 .cfi_endproc - 636 .LFE7: - 637 .size USBFS_IsConfigurationChanged, .-USBFS_IsConfigurationChanged - 638 .section .text.USBFS_GetInterfaceSetting,"ax",%progbits - 639 .align 1 - 640 .global USBFS_GetInterfaceSetting - 641 .thumb - 642 .thumb_func - 643 .type USBFS_GetInterfaceSetting, %function - 644 USBFS_GetInterfaceSetting: - 645 .LFB8: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 25 - - - 667:.\Generated_Source\PSoC5/USBFS.c **** - 668:.\Generated_Source\PSoC5/USBFS.c **** - 669:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 670:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_GetInterfaceSetting - 671:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 672:.\Generated_Source\PSoC5/USBFS.c **** * - 673:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 674:.\Generated_Source\PSoC5/USBFS.c **** * Returns the alternate setting from current interface - 675:.\Generated_Source\PSoC5/USBFS.c **** * - 676:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 677:.\Generated_Source\PSoC5/USBFS.c **** * uint8 interfaceNumber, interface number - 678:.\Generated_Source\PSoC5/USBFS.c **** * - 679:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 680:.\Generated_Source\PSoC5/USBFS.c **** * Alternate setting. - 681:.\Generated_Source\PSoC5/USBFS.c **** * - 682:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 683:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) - 684:.\Generated_Source\PSoC5/USBFS.c **** - 685:.\Generated_Source\PSoC5/USBFS.c **** { - 646 .loc 1 685 0 - 647 .cfi_startproc - 648 @ args = 0, pretend = 0, frame = 0 - 649 @ frame_needed = 0, uses_anonymous_args = 0 - 650 @ link register save eliminated. - 651 .LVL34: - 686:.\Generated_Source\PSoC5/USBFS.c **** return(USBFS_interfaceSetting[interfaceNumber]); - 652 .loc 1 686 0 - 653 0000 014B ldr r3, .L35 - 654 0002 185C ldrb r0, [r3, r0] @ zero_extendqisi2 - 655 .LVL35: - 687:.\Generated_Source\PSoC5/USBFS.c **** } - 656 .loc 1 687 0 - 657 0004 7047 bx lr - 658 .L36: - 659 0006 00BF .align 2 - 660 .L35: - 661 0008 00000000 .word USBFS_interfaceSetting - 662 .cfi_endproc - 663 .LFE8: - 664 .size USBFS_GetInterfaceSetting, .-USBFS_GetInterfaceSetting - 665 .section .text.USBFS_GetEPState,"ax",%progbits - 666 .align 1 - 667 .global USBFS_GetEPState - 668 .thumb - 669 .thumb_func - 670 .type USBFS_GetEPState, %function - 671 USBFS_GetEPState: - 672 .LFB9: - 688:.\Generated_Source\PSoC5/USBFS.c **** - 689:.\Generated_Source\PSoC5/USBFS.c **** - 690:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 691:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_GetEPState - 692:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 693:.\Generated_Source\PSoC5/USBFS.c **** * - 694:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 695:.\Generated_Source\PSoC5/USBFS.c **** * Returned the state of the requested endpoint. - 696:.\Generated_Source\PSoC5/USBFS.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 26 - - - 697:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 698:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Endpoint Number - 699:.\Generated_Source\PSoC5/USBFS.c **** * - 700:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 701:.\Generated_Source\PSoC5/USBFS.c **** * State of the requested endpoint. - 702:.\Generated_Source\PSoC5/USBFS.c **** * - 703:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 704:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_GetEPState(uint8 epNumber) - 705:.\Generated_Source\PSoC5/USBFS.c **** { - 673 .loc 1 705 0 - 674 .cfi_startproc - 675 @ args = 0, pretend = 0, frame = 0 - 676 @ frame_needed = 0, uses_anonymous_args = 0 - 677 @ link register save eliminated. - 678 .LVL36: - 706:.\Generated_Source\PSoC5/USBFS.c **** return(USBFS_EP[epNumber].apiEpState); - 679 .loc 1 706 0 - 680 0000 024B ldr r3, .L38 - 681 0002 0C22 movs r2, #12 - 682 0004 02FB0030 mla r0, r2, r0, r3 - 683 .LVL37: - 684 0008 4078 ldrb r0, [r0, #1] @ zero_extendqisi2 - 707:.\Generated_Source\PSoC5/USBFS.c **** } - 685 .loc 1 707 0 - 686 000a 7047 bx lr - 687 .L39: - 688 .align 2 - 689 .L38: - 690 000c 00000000 .word USBFS_EP - 691 .cfi_endproc - 692 .LFE9: - 693 .size USBFS_GetEPState, .-USBFS_GetEPState - 694 .section .text.USBFS_GetEPCount,"ax",%progbits - 695 .align 1 - 696 .global USBFS_GetEPCount - 697 .thumb - 698 .thumb_func - 699 .type USBFS_GetEPCount, %function - 700 USBFS_GetEPCount: - 701 .LFB10: - 708:.\Generated_Source\PSoC5/USBFS.c **** - 709:.\Generated_Source\PSoC5/USBFS.c **** - 710:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 711:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_GetEPCount - 712:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 713:.\Generated_Source\PSoC5/USBFS.c **** * - 714:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 715:.\Generated_Source\PSoC5/USBFS.c **** * This function supports Data Endpoints only(EP1-EP8). - 716:.\Generated_Source\PSoC5/USBFS.c **** * Returns the transfer count for the requested endpoint. The value from - 717:.\Generated_Source\PSoC5/USBFS.c **** * the count registers includes 2 counts for the two byte checksum of the - 718:.\Generated_Source\PSoC5/USBFS.c **** * packet. This function subtracts the two counts. - 719:.\Generated_Source\PSoC5/USBFS.c **** * - 720:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 721:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Data Endpoint Number. - 722:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. - 723:.\Generated_Source\PSoC5/USBFS.c **** * - 724:.\Generated_Source\PSoC5/USBFS.c **** * Return: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 27 - - - 725:.\Generated_Source\PSoC5/USBFS.c **** * Returns the current byte count from the specified endpoint or 0 for an - 726:.\Generated_Source\PSoC5/USBFS.c **** * invalid endpoint. - 727:.\Generated_Source\PSoC5/USBFS.c **** * - 728:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 729:.\Generated_Source\PSoC5/USBFS.c **** uint16 USBFS_GetEPCount(uint8 epNumber) - 730:.\Generated_Source\PSoC5/USBFS.c **** { - 702 .loc 1 730 0 - 703 .cfi_startproc - 704 @ args = 0, pretend = 0, frame = 0 - 705 @ frame_needed = 0, uses_anonymous_args = 0 - 706 @ link register save eliminated. - 707 .LVL38: - 731:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri; - 732:.\Generated_Source\PSoC5/USBFS.c **** uint16 result = 0u; - 733:.\Generated_Source\PSoC5/USBFS.c **** - 734:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - 708 .loc 1 734 0 - 709 0000 0138 subs r0, r0, #1 - 710 .LVL39: - 711 0002 C3B2 uxtb r3, r0 - 712 0004 072B cmp r3, #7 - 713 0006 0CD8 bhi .L42 - 714 .LVL40: - 735:.\Generated_Source\PSoC5/USBFS.c **** { - 736:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 715 .loc 1 736 0 - 716 0008 1901 lsls r1, r3, #4 - 737:.\Generated_Source\PSoC5/USBFS.c **** - 738:.\Generated_Source\PSoC5/USBFS.c **** result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & - 717 .loc 1 738 0 - 718 000a 074A ldr r2, .L43 - 719 000c CBB2 uxtb r3, r1 - 720 .LVL41: - 721 000e 985C ldrb r0, [r3, r2] @ zero_extendqisi2 - 722 .LVL42: - 739:.\Generated_Source\PSoC5/USBFS.c **** USBFS_EPX_CNT0_MASK); - 740:.\Generated_Source\PSoC5/USBFS.c **** result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri)); - 723 .loc 1 740 0 - 724 0010 511C adds r1, r2, #1 - 725 0012 5B5C ldrb r3, [r3, r1] @ zero_extendqisi2 - 726 0014 00F00F02 and r2, r0, #15 - 727 0018 43EA0220 orr r0, r3, r2, lsl #8 - 728 .LVL43: - 741:.\Generated_Source\PSoC5/USBFS.c **** result -= USBFS_EPX_CNTX_CRC_COUNT; - 729 .loc 1 741 0 - 730 001c 811E subs r1, r0, #2 - 731 001e 88B2 uxth r0, r1 - 732 .LVL44: - 733 0020 7047 bx lr - 734 .LVL45: - 735 .L42: - 732:.\Generated_Source\PSoC5/USBFS.c **** uint16 result = 0u; - 736 .loc 1 732 0 - 737 0022 0020 movs r0, #0 - 738 .LVL46: - 742:.\Generated_Source\PSoC5/USBFS.c **** } - 743:.\Generated_Source\PSoC5/USBFS.c **** return(result); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 28 - - - 744:.\Generated_Source\PSoC5/USBFS.c **** } - 739 .loc 1 744 0 - 740 0024 7047 bx lr - 741 .L44: - 742 0026 00BF .align 2 - 743 .L43: - 744 0028 0C600040 .word 1073766412 - 745 .cfi_endproc - 746 .LFE10: - 747 .size USBFS_GetEPCount, .-USBFS_GetEPCount - 748 .section .text.USBFS_LoadInEP,"ax",%progbits - 749 .align 1 - 750 .global USBFS_LoadInEP - 751 .thumb - 752 .thumb_func - 753 .type USBFS_LoadInEP, %function - 754 USBFS_LoadInEP: - 755 .LFB11: - 745:.\Generated_Source\PSoC5/USBFS.c **** - 746:.\Generated_Source\PSoC5/USBFS.c **** - 747:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_MANUAL) - 748:.\Generated_Source\PSoC5/USBFS.c **** - 749:.\Generated_Source\PSoC5/USBFS.c **** - 750:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 751:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_InitEP_DMA - 752:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 753:.\Generated_Source\PSoC5/USBFS.c **** * - 754:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 755:.\Generated_Source\PSoC5/USBFS.c **** * This function allocates and initializes a DMA channel to be used by the - 756:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data - 757:.\Generated_Source\PSoC5/USBFS.c **** * transfer. - 758:.\Generated_Source\PSoC5/USBFS.c **** * - 759:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 760:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Contains the data endpoint number. - 761:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. - 762:.\Generated_Source\PSoC5/USBFS.c **** * *pData: Pointer to a data array that is related to the EP transfers. - 763:.\Generated_Source\PSoC5/USBFS.c **** * - 764:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 765:.\Generated_Source\PSoC5/USBFS.c **** * None. - 766:.\Generated_Source\PSoC5/USBFS.c **** * - 767:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: - 768:.\Generated_Source\PSoC5/USBFS.c **** * No. - 769:.\Generated_Source\PSoC5/USBFS.c **** * - 770:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 771:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) - 772:.\Generated_Source\PSoC5/USBFS.c **** - 773:.\Generated_Source\PSoC5/USBFS.c **** { - 774:.\Generated_Source\PSoC5/USBFS.c **** uint16 src; - 775:.\Generated_Source\PSoC5/USBFS.c **** uint16 dst; - 776:.\Generated_Source\PSoC5/USBFS.c **** #if (CY_PSOC3) /* PSoC 3 */ - 777:.\Generated_Source\PSoC5/USBFS.c **** src = HI16(CYDEV_SRAM_BASE); - 778:.\Generated_Source\PSoC5/USBFS.c **** dst = HI16(CYDEV_PERIPH_BASE); - 779:.\Generated_Source\PSoC5/USBFS.c **** pData = pData; - 780:.\Generated_Source\PSoC5/USBFS.c **** #else /* PSoC 5 */ - 781:.\Generated_Source\PSoC5/USBFS.c **** if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u ) - 782:.\Generated_Source\PSoC5/USBFS.c **** { /* for the IN EP source is the SRAM memory buffer */ - 783:.\Generated_Source\PSoC5/USBFS.c **** src = HI16(pData); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 29 - - - 784:.\Generated_Source\PSoC5/USBFS.c **** dst = HI16(CYDEV_PERIPH_BASE); - 785:.\Generated_Source\PSoC5/USBFS.c **** } - 786:.\Generated_Source\PSoC5/USBFS.c **** else - 787:.\Generated_Source\PSoC5/USBFS.c **** { /* for the OUT EP source is the SIE register */ - 788:.\Generated_Source\PSoC5/USBFS.c **** src = HI16(CYDEV_PERIPH_BASE); - 789:.\Generated_Source\PSoC5/USBFS.c **** dst = HI16(pData); - 790:.\Generated_Source\PSoC5/USBFS.c **** } - 791:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End C51 */ - 792:.\Generated_Source\PSoC5/USBFS.c **** switch(epNumber) - 793:.\Generated_Source\PSoC5/USBFS.c **** { - 794:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP1: - 795:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA1_REMOVE == 0u) - 796:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize( - 797:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 798:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA1_REMOVE */ - 799:.\Generated_Source\PSoC5/USBFS.c **** break; - 800:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP2: - 801:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA2_REMOVE == 0u) - 802:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize( - 803:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 804:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA2_REMOVE */ - 805:.\Generated_Source\PSoC5/USBFS.c **** break; - 806:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP3: - 807:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA3_REMOVE == 0u) - 808:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize( - 809:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 810:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA3_REMOVE */ - 811:.\Generated_Source\PSoC5/USBFS.c **** break; - 812:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP4: - 813:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA4_REMOVE == 0u) - 814:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize( - 815:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 816:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA4_REMOVE */ - 817:.\Generated_Source\PSoC5/USBFS.c **** break; - 818:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP5: - 819:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA5_REMOVE == 0u) - 820:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize( - 821:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 822:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA5_REMOVE */ - 823:.\Generated_Source\PSoC5/USBFS.c **** break; - 824:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP6: - 825:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA6_REMOVE == 0u) - 826:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize( - 827:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 828:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA6_REMOVE */ - 829:.\Generated_Source\PSoC5/USBFS.c **** break; - 830:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP7: - 831:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA7_REMOVE == 0u) - 832:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize( - 833:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 834:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA7_REMOVE */ - 835:.\Generated_Source\PSoC5/USBFS.c **** break; - 836:.\Generated_Source\PSoC5/USBFS.c **** case USBFS_EP8: - 837:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_DMA8_REMOVE == 0u) - 838:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize( - 839:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - 840:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_DMA8_REMOVE */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 30 - - - 841:.\Generated_Source\PSoC5/USBFS.c **** break; - 842:.\Generated_Source\PSoC5/USBFS.c **** default: - 843:.\Generated_Source\PSoC5/USBFS.c **** /* Do not support EP0 DMA transfers */ - 844:.\Generated_Source\PSoC5/USBFS.c **** break; - 845:.\Generated_Source\PSoC5/USBFS.c **** } - 846:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - 847:.\Generated_Source\PSoC5/USBFS.c **** { - 848:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); - 849:.\Generated_Source\PSoC5/USBFS.c **** } - 850:.\Generated_Source\PSoC5/USBFS.c **** } - 851:.\Generated_Source\PSoC5/USBFS.c **** - 852:.\Generated_Source\PSoC5/USBFS.c **** - 853:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 854:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_Stop_DMA - 855:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 856:.\Generated_Source\PSoC5/USBFS.c **** * - 857:.\Generated_Source\PSoC5/USBFS.c **** * Summary: Stops and free DMA - 858:.\Generated_Source\PSoC5/USBFS.c **** * - 859:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - 860:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Contains the data endpoint number or - 861:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_MAX_EP to stop all DMAs - 862:.\Generated_Source\PSoC5/USBFS.c **** * - 863:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 864:.\Generated_Source\PSoC5/USBFS.c **** * None. - 865:.\Generated_Source\PSoC5/USBFS.c **** * - 866:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: - 867:.\Generated_Source\PSoC5/USBFS.c **** * No. - 868:.\Generated_Source\PSoC5/USBFS.c **** * - 869:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 870:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_Stop_DMA(uint8 epNumber) - 871:.\Generated_Source\PSoC5/USBFS.c **** { - 872:.\Generated_Source\PSoC5/USBFS.c **** uint8 i; - 873:.\Generated_Source\PSoC5/USBFS.c **** i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; - 874:.\Generated_Source\PSoC5/USBFS.c **** do - 875:.\Generated_Source\PSoC5/USBFS.c **** { - 876:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_DmaTd[i] != DMA_INVALID_TD) - 877:.\Generated_Source\PSoC5/USBFS.c **** { - 878:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChDisable(USBFS_DmaChan[i]); - 879:.\Generated_Source\PSoC5/USBFS.c **** CyDmaTdFree(USBFS_DmaTd[i]); - 880:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaTd[i] = DMA_INVALID_TD; - 881:.\Generated_Source\PSoC5/USBFS.c **** } - 882:.\Generated_Source\PSoC5/USBFS.c **** i++; - 883:.\Generated_Source\PSoC5/USBFS.c **** }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); - 884:.\Generated_Source\PSoC5/USBFS.c **** } - 885:.\Generated_Source\PSoC5/USBFS.c **** - 886:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - 887:.\Generated_Source\PSoC5/USBFS.c **** - 888:.\Generated_Source\PSoC5/USBFS.c **** - 889:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* - 890:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_LoadInEP - 891:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** - 892:.\Generated_Source\PSoC5/USBFS.c **** * - 893:.\Generated_Source\PSoC5/USBFS.c **** * Summary: - 894:.\Generated_Source\PSoC5/USBFS.c **** * Loads and enables the specified USB data endpoint for an IN interrupt or bulk - 895:.\Generated_Source\PSoC5/USBFS.c **** * transfer. - 896:.\Generated_Source\PSoC5/USBFS.c **** * - 897:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 31 - - - 898:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Contains the data endpoint number. - 899:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. - 900:.\Generated_Source\PSoC5/USBFS.c **** * *pData: A pointer to a data array from which the data for the endpoint space - 901:.\Generated_Source\PSoC5/USBFS.c **** * is loaded. - 902:.\Generated_Source\PSoC5/USBFS.c **** * length: The number of bytes to transfer from the array and then send as a - 903:.\Generated_Source\PSoC5/USBFS.c **** * result of an IN request. Valid values are between 0 and 512. - 904:.\Generated_Source\PSoC5/USBFS.c **** * - 905:.\Generated_Source\PSoC5/USBFS.c **** * Return: - 906:.\Generated_Source\PSoC5/USBFS.c **** * None. - 907:.\Generated_Source\PSoC5/USBFS.c **** * - 908:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: - 909:.\Generated_Source\PSoC5/USBFS.c **** * No. - 910:.\Generated_Source\PSoC5/USBFS.c **** * - 911:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ - 912:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) - 913:.\Generated_Source\PSoC5/USBFS.c **** - 914:.\Generated_Source\PSoC5/USBFS.c **** { - 756 .loc 1 914 0 - 757 .cfi_startproc - 758 @ args = 0, pretend = 0, frame = 0 - 759 @ frame_needed = 0, uses_anonymous_args = 0 - 760 .LVL47: - 915:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri; - 916:.\Generated_Source\PSoC5/USBFS.c **** reg8 *p; - 917:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_MANUAL) - 918:.\Generated_Source\PSoC5/USBFS.c **** uint16 i; - 919:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ - 920:.\Generated_Source\PSoC5/USBFS.c **** - 921:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - 761 .loc 1 921 0 - 762 0000 431E subs r3, r0, #1 - 763 0002 DBB2 uxtb r3, r3 - 764 0004 072B cmp r3, #7 - 914:.\Generated_Source\PSoC5/USBFS.c **** { - 765 .loc 1 914 0 - 766 0006 F0B5 push {r4, r5, r6, r7, lr} - 767 .LCFI3: - 768 .cfi_def_cfa_offset 20 - 769 .cfi_offset 4, -20 - 770 .cfi_offset 5, -16 - 771 .cfi_offset 6, -12 - 772 .cfi_offset 7, -8 - 773 .cfi_offset 14, -4 - 774 .loc 1 921 0 - 775 0008 2FD8 bhi .L45 - 776 .LVL48: - 922:.\Generated_Source\PSoC5/USBFS.c **** { - 923:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 924:.\Generated_Source\PSoC5/USBFS.c **** p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); - 925:.\Generated_Source\PSoC5/USBFS.c **** - 926:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - 927:.\Generated_Source\PSoC5/USBFS.c **** /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes - 928:.\Generated_Source\PSoC5/USBFS.c **** if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) - 777 .loc 1 928 0 - 778 000a 184E ldr r6, .L52 - 923:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 779 .loc 1 923 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 32 - - - 780 000c 1C01 lsls r4, r3, #4 - 781 .loc 1 928 0 - 782 000e 0C27 movs r7, #12 - 924:.\Generated_Source\PSoC5/USBFS.c **** p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); - 783 .loc 1 924 0 - 784 0010 E3B2 uxtb r3, r4 - 785 .LVL49: - 786 .loc 1 928 0 - 787 0012 07FB0064 mla r4, r7, r0, r6 - 788 0016 E788 ldrh r7, [r4, #6] - 924:.\Generated_Source\PSoC5/USBFS.c **** p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); - 789 .loc 1 924 0 - 790 0018 154D ldr r5, .L52+4 - 791 .loc 1 928 0 - 792 001a BFB2 uxth r7, r7 - 793 001c C7F50077 rsb r7, r7, #512 - 794 0020 BA42 cmp r2, r7 - 924:.\Generated_Source\PSoC5/USBFS.c **** p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); - 795 .loc 1 924 0 - 796 0022 1D44 add r5, r3, r5 - 797 .LVL50: - 798 .loc 1 928 0 - 799 0024 03D9 bls .L47 - 929:.\Generated_Source\PSoC5/USBFS.c **** { - 930:.\Generated_Source\PSoC5/USBFS.c **** length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; - 800 .loc 1 930 0 - 801 0026 E288 ldrh r2, [r4, #6] - 802 .LVL51: - 803 0028 C2F50074 rsb r4, r2, #512 - 804 002c A2B2 uxth r2, r4 - 805 .LVL52: - 806 .L47: - 931:.\Generated_Source\PSoC5/USBFS.c **** } - 932:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - 933:.\Generated_Source\PSoC5/USBFS.c **** - 934:.\Generated_Source\PSoC5/USBFS.c **** /* Set the count and data toggle */ - 935:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), - 807 .loc 1 935 0 - 808 002e 0C24 movs r4, #12 - 809 0030 04FB0066 mla r6, r4, r0, r6 - 810 0034 F478 ldrb r4, [r6, #3] @ zero_extendqisi2 - 811 0036 44EA1226 orr r6, r4, r2, lsr #8 - 812 003a 0E4C ldr r4, .L52+8 - 813 003c 1E55 strb r6, [r3, r4] - 936:.\Generated_Source\PSoC5/USBFS.c **** (length >> 8u) | (USBFS_EP[epNumber].epToggle)); - 937:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu); - 814 .loc 1 937 0 - 815 003e D6B2 uxtb r6, r2 - 816 0040 0134 adds r4, r4, #1 - 817 0042 1E55 strb r6, [r3, r4] - 938:.\Generated_Source\PSoC5/USBFS.c **** - 939:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_MANUAL) - 940:.\Generated_Source\PSoC5/USBFS.c **** if(pData != NULL) - 818 .loc 1 940 0 - 819 0044 49B9 cbnz r1, .L51 - 820 .L50: - 941:.\Generated_Source\PSoC5/USBFS.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 33 - - - 942:.\Generated_Source\PSoC5/USBFS.c **** /* Copy the data using the arbiter data register */ - 943:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < length; i++) - 944:.\Generated_Source\PSoC5/USBFS.c **** { - 945:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(p, pData[i]); - 946:.\Generated_Source\PSoC5/USBFS.c **** } - 947:.\Generated_Source\PSoC5/USBFS.c **** } - 948:.\Generated_Source\PSoC5/USBFS.c **** USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - 821 .loc 1 948 0 - 822 0046 094A ldr r2, .L52 - 823 .LVL53: - 824 0048 0C21 movs r1, #12 - 825 .LVL54: - 826 004a 01FB0020 mla r0, r1, r0, r2 - 827 .LVL55: - 828 004e 0021 movs r1, #0 - 829 0050 4170 strb r1, [r0, #1] - 949:.\Generated_Source\PSoC5/USBFS.c **** /* Write the Mode register */ - 950:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - 830 .loc 1 950 0 - 831 0052 4079 ldrb r0, [r0, #5] @ zero_extendqisi2 - 832 0054 084A ldr r2, .L52+12 - 833 0056 9854 strb r0, [r3, r2] - 834 0058 F0BD pop {r4, r5, r6, r7, pc} - 835 .LVL56: - 836 .L51: - 940:.\Generated_Source\PSoC5/USBFS.c **** if(pData != NULL) - 837 .loc 1 940 0 - 838 005a 0024 movs r4, #0 - 839 .L48: - 943:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < length; i++) - 840 .loc 1 943 0 discriminator 1 - 841 005c A6B2 uxth r6, r4 - 842 005e 9642 cmp r6, r2 - 843 0060 F1D2 bcs .L50 - 844 .L49: - 945:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(p, pData[i]); - 845 .loc 1 945 0 discriminator 2 - 846 0062 0E5D ldrb r6, [r1, r4] @ zero_extendqisi2 - 847 0064 0134 adds r4, r4, #1 - 848 0066 2E70 strb r6, [r5, #0] - 849 0068 F8E7 b .L48 - 850 .LVL57: - 851 .L45: - 852 006a F0BD pop {r4, r5, r6, r7, pc} - 853 .L53: - 854 .align 2 - 855 .L52: - 856 006c 00000000 .word USBFS_EP - 857 0070 88600040 .word 1073766536 - 858 0074 0C600040 .word 1073766412 - 859 0078 0E600040 .word 1073766414 - 860 .cfi_endproc - 861 .LFE11: - 862 .size USBFS_LoadInEP, .-USBFS_LoadInEP - 863 .section .text.USBFS_EnableOutEP,"ax",%progbits - 864 .align 1 - 865 .global USBFS_EnableOutEP - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 34 - - - 866 .thumb - 867 .thumb_func - 868 .type USBFS_EnableOutEP, %function - 869 USBFS_EnableOutEP: - 870 .LFB13: - 951:.\Generated_Source\PSoC5/USBFS.c **** #else - 952:.\Generated_Source\PSoC5/USBFS.c **** /* Init DMA if it was not initialized */ - 953:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) - 954:.\Generated_Source\PSoC5/USBFS.c **** { - 955:.\Generated_Source\PSoC5/USBFS.c **** USBFS_InitEP_DMA(epNumber, pData); - 956:.\Generated_Source\PSoC5/USBFS.c **** } - 957:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ - 958:.\Generated_Source\PSoC5/USBFS.c **** - 959:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - 960:.\Generated_Source\PSoC5/USBFS.c **** USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - 961:.\Generated_Source\PSoC5/USBFS.c **** if((pData != NULL) && (length > 0u)) - 962:.\Generated_Source\PSoC5/USBFS.c **** { - 963:.\Generated_Source\PSoC5/USBFS.c **** /* Enable DMA in mode2 for transferring data */ - 964:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - 965:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, - 966:.\Generated_Source\PSoC5/USBFS.c **** TD_TERMIN_EN | TD_ - 967:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32) - 968:.\Generated_Source\PSoC5/USBFS.c **** /* Enable the DMA */ - 969:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); - 970:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - 971:.\Generated_Source\PSoC5/USBFS.c **** /* Generate DMA request */ - 972:.\Generated_Source\PSoC5/USBFS.c **** * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; - 973:.\Generated_Source\PSoC5/USBFS.c **** * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); - 974:.\Generated_Source\PSoC5/USBFS.c **** /* Mode register will be written in arb ISR after DMA transfer complete */ - 975:.\Generated_Source\PSoC5/USBFS.c **** } - 976:.\Generated_Source\PSoC5/USBFS.c **** else - 977:.\Generated_Source\PSoC5/USBFS.c **** { - 978:.\Generated_Source\PSoC5/USBFS.c **** /* When zero-length packet - write the Mode register directly */ - 979:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - 980:.\Generated_Source\PSoC5/USBFS.c **** } - 981:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - 982:.\Generated_Source\PSoC5/USBFS.c **** - 983:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - 984:.\Generated_Source\PSoC5/USBFS.c **** if(pData != NULL) - 985:.\Generated_Source\PSoC5/USBFS.c **** { - 986:.\Generated_Source\PSoC5/USBFS.c **** /* Enable DMA in mode3 for transferring data */ - 987:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - 988:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, - 989:.\Generated_Source\PSoC5/USBFS.c **** USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR - 990:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32) - 991:.\Generated_Source\PSoC5/USBFS.c **** /* Clear Any potential pending DMA requests before starting the DMA channel to tran - 992:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); - 993:.\Generated_Source\PSoC5/USBFS.c **** /* Enable the DMA */ - 994:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); - 995:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - 996:.\Generated_Source\PSoC5/USBFS.c **** } - 997:.\Generated_Source\PSoC5/USBFS.c **** else - 998:.\Generated_Source\PSoC5/USBFS.c **** { - 999:.\Generated_Source\PSoC5/USBFS.c **** USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; -1000:.\Generated_Source\PSoC5/USBFS.c **** if(length > 0u) -1001:.\Generated_Source\PSoC5/USBFS.c **** { -1002:.\Generated_Source\PSoC5/USBFS.c **** /* Set Data ready status, This will generate DMA request */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 35 - - -1003:.\Generated_Source\PSoC5/USBFS.c **** * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; -1004:.\Generated_Source\PSoC5/USBFS.c **** /* Mode register will be written in arb ISR(In Buffer Full) after first DMA tra -1005:.\Generated_Source\PSoC5/USBFS.c **** } -1006:.\Generated_Source\PSoC5/USBFS.c **** else -1007:.\Generated_Source\PSoC5/USBFS.c **** { -1008:.\Generated_Source\PSoC5/USBFS.c **** /* When zero-length packet - write the Mode register directly */ -1009:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); -1010:.\Generated_Source\PSoC5/USBFS.c **** } -1011:.\Generated_Source\PSoC5/USBFS.c **** } -1012:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ -1013:.\Generated_Source\PSoC5/USBFS.c **** -1014:.\Generated_Source\PSoC5/USBFS.c **** } -1015:.\Generated_Source\PSoC5/USBFS.c **** } -1016:.\Generated_Source\PSoC5/USBFS.c **** -1017:.\Generated_Source\PSoC5/USBFS.c **** -1018:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1019:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_ReadOutEP -1020:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1021:.\Generated_Source\PSoC5/USBFS.c **** * -1022:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1023:.\Generated_Source\PSoC5/USBFS.c **** * Read data from an endpoint. The application must call -1024:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_GetEPState to see if an event is pending. -1025:.\Generated_Source\PSoC5/USBFS.c **** * -1026:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1027:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Contains the data endpoint number. -1028:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. -1029:.\Generated_Source\PSoC5/USBFS.c **** * pData: A pointer to a data array from which the data for the endpoint space -1030:.\Generated_Source\PSoC5/USBFS.c **** * is loaded. -1031:.\Generated_Source\PSoC5/USBFS.c **** * length: The number of bytes to transfer from the USB Out endpoint and loads -1032:.\Generated_Source\PSoC5/USBFS.c **** * it into data array. Valid values are between 0 and 1023. The function -1033:.\Generated_Source\PSoC5/USBFS.c **** * moves fewer than the requested number of bytes if the host sends -1034:.\Generated_Source\PSoC5/USBFS.c **** * fewer bytes than requested. -1035:.\Generated_Source\PSoC5/USBFS.c **** * -1036:.\Generated_Source\PSoC5/USBFS.c **** * Returns: -1037:.\Generated_Source\PSoC5/USBFS.c **** * Number of bytes received, 0 for an invalid endpoint. -1038:.\Generated_Source\PSoC5/USBFS.c **** * -1039:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: -1040:.\Generated_Source\PSoC5/USBFS.c **** * No. -1041:.\Generated_Source\PSoC5/USBFS.c **** * -1042:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1043:.\Generated_Source\PSoC5/USBFS.c **** uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) -1044:.\Generated_Source\PSoC5/USBFS.c **** -1045:.\Generated_Source\PSoC5/USBFS.c **** { -1046:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri; -1047:.\Generated_Source\PSoC5/USBFS.c **** reg8 *p; -1048:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_MANUAL) -1049:.\Generated_Source\PSoC5/USBFS.c **** uint16 i; -1050:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ -1051:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) -1052:.\Generated_Source\PSoC5/USBFS.c **** uint16 xferCount; -1053:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ -1054:.\Generated_Source\PSoC5/USBFS.c **** -1055:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) -1056:.\Generated_Source\PSoC5/USBFS.c **** { -1057:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); -1058:.\Generated_Source\PSoC5/USBFS.c **** p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); -1059:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 36 - - -1060:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) -1061:.\Generated_Source\PSoC5/USBFS.c **** /* Determine which is smaller the requested data or the available data */ -1062:.\Generated_Source\PSoC5/USBFS.c **** xferCount = USBFS_GetEPCount(epNumber); -1063:.\Generated_Source\PSoC5/USBFS.c **** if (length > xferCount) -1064:.\Generated_Source\PSoC5/USBFS.c **** { -1065:.\Generated_Source\PSoC5/USBFS.c **** length = xferCount; -1066:.\Generated_Source\PSoC5/USBFS.c **** } -1067:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ -1068:.\Generated_Source\PSoC5/USBFS.c **** -1069:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_MANUAL) -1070:.\Generated_Source\PSoC5/USBFS.c **** /* Copy the data using the arbiter data register */ -1071:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < length; i++) -1072:.\Generated_Source\PSoC5/USBFS.c **** { -1073:.\Generated_Source\PSoC5/USBFS.c **** pData[i] = CY_GET_REG8(p); -1074:.\Generated_Source\PSoC5/USBFS.c **** } -1075:.\Generated_Source\PSoC5/USBFS.c **** -1076:.\Generated_Source\PSoC5/USBFS.c **** /* (re)arming of OUT endpoint */ -1077:.\Generated_Source\PSoC5/USBFS.c **** USBFS_EnableOutEP(epNumber); -1078:.\Generated_Source\PSoC5/USBFS.c **** #else -1079:.\Generated_Source\PSoC5/USBFS.c **** /*Init DMA if it was not initialized */ -1080:.\Generated_Source\PSoC5/USBFS.c **** if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) -1081:.\Generated_Source\PSoC5/USBFS.c **** { -1082:.\Generated_Source\PSoC5/USBFS.c **** USBFS_InitEP_DMA(epNumber, pData); -1083:.\Generated_Source\PSoC5/USBFS.c **** } -1084:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ -1085:.\Generated_Source\PSoC5/USBFS.c **** -1086:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) -1087:.\Generated_Source\PSoC5/USBFS.c **** /* Enable DMA in mode2 for transferring data */ -1088:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); -1089:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, -1090:.\Generated_Source\PSoC5/USBFS.c **** TD_TERMIN_EN | TD_I -1091:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); -1092:.\Generated_Source\PSoC5/USBFS.c **** /* Enable the DMA */ -1093:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); -1094:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); -1095:.\Generated_Source\PSoC5/USBFS.c **** -1096:.\Generated_Source\PSoC5/USBFS.c **** /* Generate DMA request */ -1097:.\Generated_Source\PSoC5/USBFS.c **** * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; -1098:.\Generated_Source\PSoC5/USBFS.c **** * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); -1099:.\Generated_Source\PSoC5/USBFS.c **** /* Out EP will be (re)armed in arb ISR after transfer complete */ -1100:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ -1101:.\Generated_Source\PSoC5/USBFS.c **** -1102:.\Generated_Source\PSoC5/USBFS.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) -1103:.\Generated_Source\PSoC5/USBFS.c **** /* Enable DMA in mode3 for transferring data */ -1104:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); -1105:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], -1106:.\Generated_Source\PSoC5/USBFS.c **** TD_TERMIN_EN | TD_I -1107:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); -1108:.\Generated_Source\PSoC5/USBFS.c **** -1109:.\Generated_Source\PSoC5/USBFS.c **** /* Clear Any potential pending DMA requests before starting the DMA channel to transfer -1110:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); -1111:.\Generated_Source\PSoC5/USBFS.c **** /* Enable the DMA */ -1112:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); -1113:.\Generated_Source\PSoC5/USBFS.c **** (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); -1114:.\Generated_Source\PSoC5/USBFS.c **** /* Out EP will be (re)armed in arb ISR after transfer complete */ -1115:.\Generated_Source\PSoC5/USBFS.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ -1116:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 37 - - -1117:.\Generated_Source\PSoC5/USBFS.c **** } -1118:.\Generated_Source\PSoC5/USBFS.c **** else -1119:.\Generated_Source\PSoC5/USBFS.c **** { -1120:.\Generated_Source\PSoC5/USBFS.c **** length = 0u; -1121:.\Generated_Source\PSoC5/USBFS.c **** } -1122:.\Generated_Source\PSoC5/USBFS.c **** -1123:.\Generated_Source\PSoC5/USBFS.c **** return(length); -1124:.\Generated_Source\PSoC5/USBFS.c **** } -1125:.\Generated_Source\PSoC5/USBFS.c **** -1126:.\Generated_Source\PSoC5/USBFS.c **** -1127:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1128:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_EnableOutEP -1129:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1130:.\Generated_Source\PSoC5/USBFS.c **** * -1131:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1132:.\Generated_Source\PSoC5/USBFS.c **** * This function enables an OUT endpoint. It should not be -1133:.\Generated_Source\PSoC5/USBFS.c **** * called for an IN endpoint. -1134:.\Generated_Source\PSoC5/USBFS.c **** * -1135:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1136:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Endpoint Number -1137:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. -1138:.\Generated_Source\PSoC5/USBFS.c **** * -1139:.\Generated_Source\PSoC5/USBFS.c **** * Return: -1140:.\Generated_Source\PSoC5/USBFS.c **** * None. -1141:.\Generated_Source\PSoC5/USBFS.c **** * -1142:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: -1143:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING -1144:.\Generated_Source\PSoC5/USBFS.c **** * -1145:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: -1146:.\Generated_Source\PSoC5/USBFS.c **** * No. -1147:.\Generated_Source\PSoC5/USBFS.c **** * -1148:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1149:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_EnableOutEP(uint8 epNumber) -1150:.\Generated_Source\PSoC5/USBFS.c **** { - 871 .loc 1 1150 0 - 872 .cfi_startproc - 873 @ args = 0, pretend = 0, frame = 0 - 874 @ frame_needed = 0, uses_anonymous_args = 0 - 875 @ link register save eliminated. - 876 .LVL58: -1151:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri; -1152:.\Generated_Source\PSoC5/USBFS.c **** -1153:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - 877 .loc 1 1153 0 - 878 0000 431E subs r3, r0, #1 - 879 0002 DBB2 uxtb r3, r3 - 880 0004 072B cmp r3, #7 - 881 0006 0AD8 bhi .L54 - 882 .LVL59: -1154:.\Generated_Source\PSoC5/USBFS.c **** { -1155:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); -1156:.\Generated_Source\PSoC5/USBFS.c **** USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - 883 .loc 1 1156 0 - 884 0008 054A ldr r2, .L56 - 885 000a 0C21 movs r1, #12 - 886 000c 01FB0020 mla r0, r1, r0, r2 - 887 .LVL60: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 38 - - - 888 0010 0021 movs r1, #0 - 889 0012 4170 strb r1, [r0, #1] -1155:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 890 .loc 1 1155 0 - 891 0014 1B01 lsls r3, r3, #4 - 892 .LVL61: -1157:.\Generated_Source\PSoC5/USBFS.c **** /* Write the Mode register */ -1158:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - 893 .loc 1 1158 0 - 894 0016 4079 ldrb r0, [r0, #5] @ zero_extendqisi2 - 895 0018 024A ldr r2, .L56+4 - 896 001a DBB2 uxtb r3, r3 - 897 001c 9854 strb r0, [r3, r2] - 898 .L54: - 899 001e 7047 bx lr - 900 .L57: - 901 .align 2 - 902 .L56: - 903 0020 00000000 .word USBFS_EP - 904 0024 0E600040 .word 1073766414 - 905 .cfi_endproc - 906 .LFE13: - 907 .size USBFS_EnableOutEP, .-USBFS_EnableOutEP - 908 .section .text.USBFS_ReadOutEP,"ax",%progbits - 909 .align 1 - 910 .global USBFS_ReadOutEP - 911 .thumb - 912 .thumb_func - 913 .type USBFS_ReadOutEP, %function - 914 USBFS_ReadOutEP: - 915 .LFB12: -1045:.\Generated_Source\PSoC5/USBFS.c **** { - 916 .loc 1 1045 0 - 917 .cfi_startproc - 918 @ args = 0, pretend = 0, frame = 0 - 919 @ frame_needed = 0, uses_anonymous_args = 0 - 920 .LVL62: - 921 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 922 .LCFI4: - 923 .cfi_def_cfa_offset 24 - 924 .cfi_offset 3, -24 - 925 .cfi_offset 4, -20 - 926 .cfi_offset 5, -16 - 927 .cfi_offset 6, -12 - 928 .cfi_offset 7, -8 - 929 .cfi_offset 14, -4 -1055:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) - 930 .loc 1 1055 0 - 931 0002 431E subs r3, r0, #1 -1045:.\Generated_Source\PSoC5/USBFS.c **** { - 932 .loc 1 1045 0 - 933 0004 0D46 mov r5, r1 -1055:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) - 934 .loc 1 1055 0 - 935 0006 D9B2 uxtb r1, r3 - 936 .LVL63: - 937 0008 0729 cmp r1, #7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 39 - - -1045:.\Generated_Source\PSoC5/USBFS.c **** { - 938 .loc 1 1045 0 - 939 000a 0746 mov r7, r0 - 940 000c 1446 mov r4, r2 -1055:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) - 941 .loc 1 1055 0 - 942 000e 16D8 bhi .L62 -1055:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) - 943 .loc 1 1055 0 is_stmt 0 discriminator 1 - 944 0010 BDB1 cbz r5, .L63 - 945 .LVL64: -1057:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 946 .loc 1 1057 0 is_stmt 1 - 947 0012 0A01 lsls r2, r1, #4 - 948 .LVL65: -1058:.\Generated_Source\PSoC5/USBFS.c **** p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); - 949 .loc 1 1058 0 - 950 0014 0C4E ldr r6, .L65 - 951 0016 D3B2 uxtb r3, r2 - 952 0018 9E19 adds r6, r3, r6 - 953 .LVL66: -1062:.\Generated_Source\PSoC5/USBFS.c **** xferCount = USBFS_GetEPCount(epNumber); - 954 .loc 1 1062 0 - 955 001a FFF7FEFF bl USBFS_GetEPCount - 956 .LVL67: - 957 001e A042 cmp r0, r4 - 958 0020 28BF it cs - 959 0022 2046 movcs r0, r4 - 960 .LVL68: - 961 0024 84B2 uxth r4, r0 - 962 .LVL69: -1071:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < length; i++) - 963 .loc 1 1071 0 - 964 0026 0022 movs r2, #0 - 965 .LVL70: - 966 .L60: -1071:.\Generated_Source\PSoC5/USBFS.c **** for (i = 0u; i < length; i++) - 967 .loc 1 1071 0 is_stmt 0 discriminator 1 - 968 0028 90B2 uxth r0, r2 - 969 002a A042 cmp r0, r4 - 970 002c 03D2 bcs .L64 - 971 .L61: -1073:.\Generated_Source\PSoC5/USBFS.c **** pData[i] = CY_GET_REG8(p); - 972 .loc 1 1073 0 is_stmt 1 discriminator 2 - 973 002e 3178 ldrb r1, [r6, #0] @ zero_extendqisi2 - 974 0030 A954 strb r1, [r5, r2] - 975 0032 0132 adds r2, r2, #1 - 976 0034 F8E7 b .L60 - 977 .L64: -1077:.\Generated_Source\PSoC5/USBFS.c **** USBFS_EnableOutEP(epNumber); - 978 .loc 1 1077 0 - 979 0036 3846 mov r0, r7 - 980 0038 FFF7FEFF bl USBFS_EnableOutEP - 981 .LVL71: - 982 003c 02E0 b .L59 - 983 .LVL72: - 984 .L62: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 40 - - -1120:.\Generated_Source\PSoC5/USBFS.c **** length = 0u; - 985 .loc 1 1120 0 - 986 003e 0024 movs r4, #0 - 987 0040 00E0 b .L59 - 988 .L63: - 989 0042 2C46 mov r4, r5 - 990 .LVL73: - 991 .L59: -1124:.\Generated_Source\PSoC5/USBFS.c **** } - 992 .loc 1 1124 0 - 993 0044 2046 mov r0, r4 - 994 0046 F8BD pop {r3, r4, r5, r6, r7, pc} - 995 .L66: - 996 .align 2 - 997 .L65: - 998 0048 88600040 .word 1073766536 - 999 .cfi_endproc - 1000 .LFE12: - 1001 .size USBFS_ReadOutEP, .-USBFS_ReadOutEP - 1002 .section .text.USBFS_DisableOutEP,"ax",%progbits - 1003 .align 1 - 1004 .global USBFS_DisableOutEP - 1005 .thumb - 1006 .thumb_func - 1007 .type USBFS_DisableOutEP, %function - 1008 USBFS_DisableOutEP: - 1009 .LFB14: -1159:.\Generated_Source\PSoC5/USBFS.c **** } -1160:.\Generated_Source\PSoC5/USBFS.c **** } -1161:.\Generated_Source\PSoC5/USBFS.c **** -1162:.\Generated_Source\PSoC5/USBFS.c **** -1163:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1164:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_DisableOutEP -1165:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1166:.\Generated_Source\PSoC5/USBFS.c **** * -1167:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1168:.\Generated_Source\PSoC5/USBFS.c **** * This function disables an OUT endpoint. It should not be -1169:.\Generated_Source\PSoC5/USBFS.c **** * called for an IN endpoint. -1170:.\Generated_Source\PSoC5/USBFS.c **** * -1171:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1172:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Endpoint Number -1173:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. -1174:.\Generated_Source\PSoC5/USBFS.c **** * -1175:.\Generated_Source\PSoC5/USBFS.c **** * Return: -1176:.\Generated_Source\PSoC5/USBFS.c **** * None. -1177:.\Generated_Source\PSoC5/USBFS.c **** * -1178:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1179:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_DisableOutEP(uint8 epNumber) -1180:.\Generated_Source\PSoC5/USBFS.c **** { - 1010 .loc 1 1180 0 - 1011 .cfi_startproc - 1012 @ args = 0, pretend = 0, frame = 0 - 1013 @ frame_needed = 0, uses_anonymous_args = 0 - 1014 @ link register save eliminated. - 1015 .LVL74: -1181:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri ; -1182:.\Generated_Source\PSoC5/USBFS.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 41 - - -1183:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - 1016 .loc 1 1183 0 - 1017 0000 0138 subs r0, r0, #1 - 1018 .LVL75: - 1019 0002 C1B2 uxtb r1, r0 - 1020 0004 0729 cmp r1, #7 - 1021 0006 04D8 bhi .L67 - 1022 .LVL76: -1184:.\Generated_Source\PSoC5/USBFS.c **** { -1185:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 1023 .loc 1 1185 0 - 1024 0008 0A01 lsls r2, r1, #4 -1186:.\Generated_Source\PSoC5/USBFS.c **** /* Write the Mode register */ -1187:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); - 1025 .loc 1 1187 0 - 1026 000a 024B ldr r3, .L69 - 1027 000c D0B2 uxtb r0, r2 - 1028 000e 0821 movs r1, #8 - 1029 .LVL77: - 1030 0010 C154 strb r1, [r0, r3] - 1031 .L67: - 1032 0012 7047 bx lr - 1033 .L70: - 1034 .align 2 - 1035 .L69: - 1036 0014 0E600040 .word 1073766414 - 1037 .cfi_endproc - 1038 .LFE14: - 1039 .size USBFS_DisableOutEP, .-USBFS_DisableOutEP - 1040 .section .text.USBFS_Force,"ax",%progbits - 1041 .align 1 - 1042 .global USBFS_Force - 1043 .thumb - 1044 .thumb_func - 1045 .type USBFS_Force, %function - 1046 USBFS_Force: - 1047 .LFB15: -1188:.\Generated_Source\PSoC5/USBFS.c **** } -1189:.\Generated_Source\PSoC5/USBFS.c **** } -1190:.\Generated_Source\PSoC5/USBFS.c **** -1191:.\Generated_Source\PSoC5/USBFS.c **** -1192:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1193:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_Force -1194:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1195:.\Generated_Source\PSoC5/USBFS.c **** * -1196:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1197:.\Generated_Source\PSoC5/USBFS.c **** * Forces the bus state -1198:.\Generated_Source\PSoC5/USBFS.c **** * -1199:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1200:.\Generated_Source\PSoC5/USBFS.c **** * bState -1201:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_FORCE_J -1202:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_FORCE_K -1203:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_FORCE_SE0 -1204:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_FORCE_NONE -1205:.\Generated_Source\PSoC5/USBFS.c **** * -1206:.\Generated_Source\PSoC5/USBFS.c **** * Return: -1207:.\Generated_Source\PSoC5/USBFS.c **** * None. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 42 - - -1208:.\Generated_Source\PSoC5/USBFS.c **** * -1209:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1210:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_Force(uint8 bState) -1211:.\Generated_Source\PSoC5/USBFS.c **** { - 1048 .loc 1 1211 0 - 1049 .cfi_startproc - 1050 @ args = 0, pretend = 0, frame = 0 - 1051 @ frame_needed = 0, uses_anonymous_args = 0 - 1052 @ link register save eliminated. - 1053 .LVL78: -1212:.\Generated_Source\PSoC5/USBFS.c **** CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState); - 1054 .loc 1 1212 0 - 1055 0000 014B ldr r3, .L72 - 1056 0002 1870 strb r0, [r3, #0] - 1057 0004 7047 bx lr - 1058 .L73: - 1059 0006 00BF .align 2 - 1060 .L72: - 1061 0008 10600040 .word 1073766416 - 1062 .cfi_endproc - 1063 .LFE15: - 1064 .size USBFS_Force, .-USBFS_Force - 1065 .section .text.USBFS_GetEPAckState,"ax",%progbits - 1066 .align 1 - 1067 .global USBFS_GetEPAckState - 1068 .thumb - 1069 .thumb_func - 1070 .type USBFS_GetEPAckState, %function - 1071 USBFS_GetEPAckState: - 1072 .LFB16: -1213:.\Generated_Source\PSoC5/USBFS.c **** } -1214:.\Generated_Source\PSoC5/USBFS.c **** -1215:.\Generated_Source\PSoC5/USBFS.c **** -1216:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1217:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_GetEPAckState -1218:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1219:.\Generated_Source\PSoC5/USBFS.c **** * -1220:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1221:.\Generated_Source\PSoC5/USBFS.c **** * Returns the ACK of the CR0 Register (ACKD) -1222:.\Generated_Source\PSoC5/USBFS.c **** * -1223:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1224:.\Generated_Source\PSoC5/USBFS.c **** * epNumber: Endpoint Number -1225:.\Generated_Source\PSoC5/USBFS.c **** * Valid values are between 1 and 8. -1226:.\Generated_Source\PSoC5/USBFS.c **** * -1227:.\Generated_Source\PSoC5/USBFS.c **** * Returns -1228:.\Generated_Source\PSoC5/USBFS.c **** * 0 if nothing has been ACKD, non-=zero something has been ACKD -1229:.\Generated_Source\PSoC5/USBFS.c **** * -1230:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1231:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_GetEPAckState(uint8 epNumber) -1232:.\Generated_Source\PSoC5/USBFS.c **** { - 1073 .loc 1 1232 0 - 1074 .cfi_startproc - 1075 @ args = 0, pretend = 0, frame = 0 - 1076 @ frame_needed = 0, uses_anonymous_args = 0 - 1077 @ link register save eliminated. - 1078 .LVL79: -1233:.\Generated_Source\PSoC5/USBFS.c **** uint8 ri; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 43 - - -1234:.\Generated_Source\PSoC5/USBFS.c **** uint8 cr = 0u; -1235:.\Generated_Source\PSoC5/USBFS.c **** -1236:.\Generated_Source\PSoC5/USBFS.c **** if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - 1079 .loc 1 1236 0 - 1080 0000 0138 subs r0, r0, #1 - 1081 .LVL80: - 1082 0002 C1B2 uxtb r1, r0 - 1083 0004 0729 cmp r1, #7 - 1084 0006 07D8 bhi .L76 - 1085 .LVL81: -1237:.\Generated_Source\PSoC5/USBFS.c **** { -1238:.\Generated_Source\PSoC5/USBFS.c **** ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 1086 .loc 1 1238 0 - 1087 0008 0A01 lsls r2, r1, #4 -1239:.\Generated_Source\PSoC5/USBFS.c **** cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD; - 1088 .loc 1 1239 0 - 1089 000a 044B ldr r3, .L77 - 1090 000c D0B2 uxtb r0, r2 - 1091 000e C15C ldrb r1, [r0, r3] @ zero_extendqisi2 - 1092 .LVL82: - 1093 0010 01F01002 and r2, r1, #16 - 1094 0014 D0B2 uxtb r0, r2 - 1095 .LVL83: - 1096 0016 7047 bx lr - 1097 .LVL84: - 1098 .L76: -1234:.\Generated_Source\PSoC5/USBFS.c **** uint8 cr = 0u; - 1099 .loc 1 1234 0 - 1100 0018 0020 movs r0, #0 - 1101 .LVL85: -1240:.\Generated_Source\PSoC5/USBFS.c **** } -1241:.\Generated_Source\PSoC5/USBFS.c **** -1242:.\Generated_Source\PSoC5/USBFS.c **** return(cr); -1243:.\Generated_Source\PSoC5/USBFS.c **** } - 1102 .loc 1 1243 0 - 1103 001a 7047 bx lr - 1104 .L78: - 1105 .align 2 - 1106 .L77: - 1107 001c 0E600040 .word 1073766414 - 1108 .cfi_endproc - 1109 .LFE16: - 1110 .size USBFS_GetEPAckState, .-USBFS_GetEPAckState - 1111 .section .text.USBFS_SetPowerStatus,"ax",%progbits - 1112 .align 1 - 1113 .global USBFS_SetPowerStatus - 1114 .thumb - 1115 .thumb_func - 1116 .type USBFS_SetPowerStatus, %function - 1117 USBFS_SetPowerStatus: - 1118 .LFB17: -1244:.\Generated_Source\PSoC5/USBFS.c **** -1245:.\Generated_Source\PSoC5/USBFS.c **** -1246:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1247:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_SetPowerStatus -1248:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1249:.\Generated_Source\PSoC5/USBFS.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 44 - - -1250:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1251:.\Generated_Source\PSoC5/USBFS.c **** * Sets the device power status for reporting in the Get Device Status -1252:.\Generated_Source\PSoC5/USBFS.c **** * request -1253:.\Generated_Source\PSoC5/USBFS.c **** * -1254:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1255:.\Generated_Source\PSoC5/USBFS.c **** * powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered, -1256:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered -1257:.\Generated_Source\PSoC5/USBFS.c **** * -1258:.\Generated_Source\PSoC5/USBFS.c **** * Return: -1259:.\Generated_Source\PSoC5/USBFS.c **** * None. -1260:.\Generated_Source\PSoC5/USBFS.c **** * -1261:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: -1262:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceStatus - set power status -1263:.\Generated_Source\PSoC5/USBFS.c **** * -1264:.\Generated_Source\PSoC5/USBFS.c **** * Reentrant: -1265:.\Generated_Source\PSoC5/USBFS.c **** * No. -1266:.\Generated_Source\PSoC5/USBFS.c **** * -1267:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1268:.\Generated_Source\PSoC5/USBFS.c **** void USBFS_SetPowerStatus(uint8 powerStatus) -1269:.\Generated_Source\PSoC5/USBFS.c **** { - 1119 .loc 1 1269 0 - 1120 .cfi_startproc - 1121 @ args = 0, pretend = 0, frame = 0 - 1122 @ frame_needed = 0, uses_anonymous_args = 0 - 1123 @ link register save eliminated. - 1124 .LVL86: - 1125 0000 044B ldr r3, .L83 -1270:.\Generated_Source\PSoC5/USBFS.c **** if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) -1271:.\Generated_Source\PSoC5/USBFS.c **** { -1272:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; - 1126 .loc 1 1272 0 - 1127 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 -1270:.\Generated_Source\PSoC5/USBFS.c **** if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) - 1128 .loc 1 1270 0 - 1129 0004 10B1 cbz r0, .L80 - 1130 .loc 1 1272 0 - 1131 0006 42F00100 orr r0, r2, #1 - 1132 .LVL87: - 1133 000a 01E0 b .L82 - 1134 .LVL88: - 1135 .L80: -1273:.\Generated_Source\PSoC5/USBFS.c **** } -1274:.\Generated_Source\PSoC5/USBFS.c **** else -1275:.\Generated_Source\PSoC5/USBFS.c **** { -1276:.\Generated_Source\PSoC5/USBFS.c **** USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED)); - 1136 .loc 1 1276 0 - 1137 000c 02F0FE00 and r0, r2, #254 - 1138 .LVL89: - 1139 .L82: - 1140 0010 1870 strb r0, [r3, #0] - 1141 0012 7047 bx lr - 1142 .L84: - 1143 .align 2 - 1144 .L83: - 1145 0014 00000000 .word USBFS_deviceStatus - 1146 .cfi_endproc - 1147 .LFE17: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 45 - - - 1148 .size USBFS_SetPowerStatus, .-USBFS_SetPowerStatus - 1149 .section .text.USBFS_RWUEnabled,"ax",%progbits - 1150 .align 1 - 1151 .global USBFS_RWUEnabled - 1152 .thumb - 1153 .thumb_func - 1154 .type USBFS_RWUEnabled, %function - 1155 USBFS_RWUEnabled: - 1156 .LFB18: -1277:.\Generated_Source\PSoC5/USBFS.c **** } -1278:.\Generated_Source\PSoC5/USBFS.c **** } -1279:.\Generated_Source\PSoC5/USBFS.c **** -1280:.\Generated_Source\PSoC5/USBFS.c **** -1281:.\Generated_Source\PSoC5/USBFS.c **** #if (USBFS_MON_VBUS == 1u) -1282:.\Generated_Source\PSoC5/USBFS.c **** -1283:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1284:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_VBusPresent -1285:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1286:.\Generated_Source\PSoC5/USBFS.c **** * -1287:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1288:.\Generated_Source\PSoC5/USBFS.c **** * Determines VBUS presence for Self Powered Devices. -1289:.\Generated_Source\PSoC5/USBFS.c **** * -1290:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1291:.\Generated_Source\PSoC5/USBFS.c **** * None. -1292:.\Generated_Source\PSoC5/USBFS.c **** * -1293:.\Generated_Source\PSoC5/USBFS.c **** * Return: -1294:.\Generated_Source\PSoC5/USBFS.c **** * 1 if VBUS is present, otherwise 0. -1295:.\Generated_Source\PSoC5/USBFS.c **** * -1296:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1297:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_VBusPresent(void) -1298:.\Generated_Source\PSoC5/USBFS.c **** { -1299:.\Generated_Source\PSoC5/USBFS.c **** return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u); -1300:.\Generated_Source\PSoC5/USBFS.c **** } -1301:.\Generated_Source\PSoC5/USBFS.c **** -1302:.\Generated_Source\PSoC5/USBFS.c **** #endif /* USBFS_MON_VBUS */ -1303:.\Generated_Source\PSoC5/USBFS.c **** -1304:.\Generated_Source\PSoC5/USBFS.c **** -1305:.\Generated_Source\PSoC5/USBFS.c **** /******************************************************************************* -1306:.\Generated_Source\PSoC5/USBFS.c **** * Function Name: USBFS_RWUEnabled -1307:.\Generated_Source\PSoC5/USBFS.c **** ******************************************************************************** -1308:.\Generated_Source\PSoC5/USBFS.c **** * -1309:.\Generated_Source\PSoC5/USBFS.c **** * Summary: -1310:.\Generated_Source\PSoC5/USBFS.c **** * Returns TRUE if Remote Wake Up is enabled, otherwise FALSE -1311:.\Generated_Source\PSoC5/USBFS.c **** * -1312:.\Generated_Source\PSoC5/USBFS.c **** * Parameters: -1313:.\Generated_Source\PSoC5/USBFS.c **** * None. -1314:.\Generated_Source\PSoC5/USBFS.c **** * -1315:.\Generated_Source\PSoC5/USBFS.c **** * Return: -1316:.\Generated_Source\PSoC5/USBFS.c **** * TRUE - Remote Wake Up Enabled -1317:.\Generated_Source\PSoC5/USBFS.c **** * FALSE - Remote Wake Up Disabled -1318:.\Generated_Source\PSoC5/USBFS.c **** * -1319:.\Generated_Source\PSoC5/USBFS.c **** * Global variables: -1320:.\Generated_Source\PSoC5/USBFS.c **** * USBFS_deviceStatus - checked to determine remote status -1321:.\Generated_Source\PSoC5/USBFS.c **** * -1322:.\Generated_Source\PSoC5/USBFS.c **** *******************************************************************************/ -1323:.\Generated_Source\PSoC5/USBFS.c **** uint8 USBFS_RWUEnabled(void) -1324:.\Generated_Source\PSoC5/USBFS.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 46 - - - 1157 .loc 1 1324 0 - 1158 .cfi_startproc - 1159 @ args = 0, pretend = 0, frame = 0 - 1160 @ frame_needed = 0, uses_anonymous_args = 0 - 1161 @ link register save eliminated. - 1162 .LVL90: -1325:.\Generated_Source\PSoC5/USBFS.c **** uint8 result = USBFS_FALSE; -1326:.\Generated_Source\PSoC5/USBFS.c **** if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u) - 1163 .loc 1 1326 0 - 1164 0000 024B ldr r3, .L86 - 1165 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1166 .LVL91: -1327:.\Generated_Source\PSoC5/USBFS.c **** { -1328:.\Generated_Source\PSoC5/USBFS.c **** result = USBFS_TRUE; -1329:.\Generated_Source\PSoC5/USBFS.c **** } -1330:.\Generated_Source\PSoC5/USBFS.c **** -1331:.\Generated_Source\PSoC5/USBFS.c **** return(result); -1332:.\Generated_Source\PSoC5/USBFS.c **** } - 1167 .loc 1 1332 0 - 1168 0004 C0F34000 ubfx r0, r0, #1, #1 - 1169 .LVL92: - 1170 0008 7047 bx lr - 1171 .L87: - 1172 000a 00BF .align 2 - 1173 .L86: - 1174 000c 00000000 .word USBFS_deviceStatus - 1175 .cfi_endproc - 1176 .LFE18: - 1177 .size USBFS_RWUEnabled, .-USBFS_RWUEnabled - 1178 .global USBFS_initVar - 1179 .bss - 1180 .set .LANCHOR0,. + 0 - 1181 .type USBFS_initVar, %object - 1182 .size USBFS_initVar, 1 - 1183 USBFS_initVar: - 1184 0000 00 .space 1 - 1185 .text - 1186 .Letext0: - 1187 .file 2 "./Generated_Source/PSoC5/cytypes.h" - 1188 .file 3 ".\\Generated_Source\\PSoC5\\USBFS.h" - 1189 .file 4 ".\\Generated_Source\\PSoC5\\USBFS_pvt.h" - 1190 .file 5 "./Generated_Source/PSoC5/CyLib.h" - 1191 .section .debug_info,"",%progbits - 1192 .Ldebug_info0: - 1193 0000 BF080000 .4byte 0x8bf - 1194 0004 0200 .2byte 0x2 - 1195 0006 00000000 .4byte .Ldebug_abbrev0 - 1196 000a 04 .byte 0x4 - 1197 000b 01 .uleb128 0x1 - 1198 000c F6020000 .4byte .LASF72 - 1199 0010 01 .byte 0x1 - 1200 0011 B3000000 .4byte .LASF73 - 1201 0015 61020000 .4byte .LASF74 - 1202 0019 00000000 .4byte .Ldebug_ranges0+0 - 1203 001d 00000000 .4byte 0 - 1204 0021 00000000 .4byte 0 - 1205 0025 00000000 .4byte .Ldebug_line0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 47 - - - 1206 0029 02 .uleb128 0x2 - 1207 002a 01 .byte 0x1 - 1208 002b 06 .byte 0x6 - 1209 002c A7000000 .4byte .LASF0 - 1210 0030 02 .uleb128 0x2 - 1211 0031 01 .byte 0x1 - 1212 0032 08 .byte 0x8 - 1213 0033 58030000 .4byte .LASF1 - 1214 0037 02 .uleb128 0x2 - 1215 0038 02 .byte 0x2 - 1216 0039 05 .byte 0x5 - 1217 003a 66030000 .4byte .LASF2 - 1218 003e 02 .uleb128 0x2 - 1219 003f 02 .byte 0x2 - 1220 0040 07 .byte 0x7 - 1221 0041 1A020000 .4byte .LASF3 - 1222 0045 02 .uleb128 0x2 - 1223 0046 04 .byte 0x4 - 1224 0047 05 .byte 0x5 - 1225 0048 4C010000 .4byte .LASF4 - 1226 004c 02 .uleb128 0x2 - 1227 004d 04 .byte 0x4 - 1228 004e 07 .byte 0x7 - 1229 004f F1010000 .4byte .LASF5 - 1230 0053 02 .uleb128 0x2 - 1231 0054 08 .byte 0x8 - 1232 0055 05 .byte 0x5 - 1233 0056 99000000 .4byte .LASF6 - 1234 005a 02 .uleb128 0x2 - 1235 005b 08 .byte 0x8 - 1236 005c 07 .byte 0x7 - 1237 005d 49000000 .4byte .LASF7 - 1238 0061 03 .uleb128 0x3 - 1239 0062 04 .byte 0x4 - 1240 0063 05 .byte 0x5 - 1241 0064 696E7400 .ascii "int\000" - 1242 0068 02 .uleb128 0x2 - 1243 0069 04 .byte 0x4 - 1244 006a 07 .byte 0x7 - 1245 006b E4010000 .4byte .LASF8 - 1246 006f 04 .uleb128 0x4 - 1247 0070 6C010000 .4byte .LASF9 - 1248 0074 02 .byte 0x2 - 1249 0075 5B .byte 0x5b - 1250 0076 30000000 .4byte 0x30 - 1251 007a 04 .uleb128 0x4 - 1252 007b 00000000 .4byte .LASF10 - 1253 007f 02 .byte 0x2 - 1254 0080 5C .byte 0x5c - 1255 0081 3E000000 .4byte 0x3e - 1256 0085 04 .uleb128 0x4 - 1257 0086 98010000 .4byte .LASF11 - 1258 008a 02 .byte 0x2 - 1259 008b 5D .byte 0x5d - 1260 008c 4C000000 .4byte 0x4c - 1261 0090 02 .uleb128 0x2 - 1262 0091 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 48 - - - 1263 0092 04 .byte 0x4 - 1264 0093 CE020000 .4byte .LASF12 - 1265 0097 02 .uleb128 0x2 - 1266 0098 08 .byte 0x8 - 1267 0099 04 .byte 0x4 - 1268 009a 85010000 .4byte .LASF13 - 1269 009e 02 .uleb128 0x2 - 1270 009f 01 .byte 0x1 - 1271 00a0 08 .byte 0x8 - 1272 00a1 DE030000 .4byte .LASF14 - 1273 00a5 04 .uleb128 0x4 - 1274 00a6 3F030000 .4byte .LASF15 - 1275 00aa 02 .byte 0x2 - 1276 00ab F0 .byte 0xf0 - 1277 00ac B0000000 .4byte 0xb0 - 1278 00b0 05 .uleb128 0x5 - 1279 00b1 6F000000 .4byte 0x6f - 1280 00b5 04 .uleb128 0x4 - 1281 00b6 92020000 .4byte .LASF16 - 1282 00ba 02 .byte 0x2 - 1283 00bb F2 .byte 0xf2 - 1284 00bc C0000000 .4byte 0xc0 - 1285 00c0 05 .uleb128 0x5 - 1286 00c1 85000000 .4byte 0x85 - 1287 00c5 06 .uleb128 0x6 - 1288 00c6 E8030000 .4byte .LASF17 - 1289 00ca 02 .byte 0x2 - 1290 00cb 0201 .2byte 0x102 - 1291 00cd D1000000 .4byte 0xd1 - 1292 00d1 07 .uleb128 0x7 - 1293 00d2 04 .byte 0x4 - 1294 00d3 D7000000 .4byte 0xd7 - 1295 00d7 08 .uleb128 0x8 - 1296 00d8 01 .byte 0x1 - 1297 00d9 02 .uleb128 0x2 - 1298 00da 04 .byte 0x4 - 1299 00db 07 .byte 0x7 - 1300 00dc A2020000 .4byte .LASF18 - 1301 00e0 09 .uleb128 0x9 - 1302 00e1 0C .byte 0xc - 1303 00e2 03 .byte 0x3 - 1304 00e3 79 .byte 0x79 - 1305 00e4 67010000 .4byte 0x167 - 1306 00e8 0A .uleb128 0xa - 1307 00e9 AB020000 .4byte .LASF19 - 1308 00ed 03 .byte 0x3 - 1309 00ee 7B .byte 0x7b - 1310 00ef 6F000000 .4byte 0x6f - 1311 00f3 02 .byte 0x2 - 1312 00f4 23 .byte 0x23 - 1313 00f5 00 .uleb128 0 - 1314 00f6 0A .uleb128 0xa - 1315 00f7 D4020000 .4byte .LASF20 - 1316 00fb 03 .byte 0x3 - 1317 00fc 7C .byte 0x7c - 1318 00fd 6F000000 .4byte 0x6f - 1319 0101 02 .byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 49 - - - 1320 0102 23 .byte 0x23 - 1321 0103 01 .uleb128 0x1 - 1322 0104 0A .uleb128 0xa - 1323 0105 98020000 .4byte .LASF21 - 1324 0109 03 .byte 0x3 - 1325 010a 7D .byte 0x7d - 1326 010b 6F000000 .4byte 0x6f - 1327 010f 02 .byte 0x2 - 1328 0110 23 .byte 0x23 - 1329 0111 02 .uleb128 0x2 - 1330 0112 0A .uleb128 0xa - 1331 0113 72010000 .4byte .LASF22 - 1332 0117 03 .byte 0x3 - 1333 0118 7E .byte 0x7e - 1334 0119 6F000000 .4byte 0x6f - 1335 011d 02 .byte 0x2 - 1336 011e 23 .byte 0x23 - 1337 011f 03 .uleb128 0x3 - 1338 0120 0A .uleb128 0xa - 1339 0121 74000000 .4byte .LASF23 - 1340 0125 03 .byte 0x3 - 1341 0126 7F .byte 0x7f - 1342 0127 6F000000 .4byte 0x6f - 1343 012b 02 .byte 0x2 - 1344 012c 23 .byte 0x23 - 1345 012d 04 .uleb128 0x4 - 1346 012e 0A .uleb128 0xa - 1347 012f CD010000 .4byte .LASF24 - 1348 0133 03 .byte 0x3 - 1349 0134 80 .byte 0x80 - 1350 0135 6F000000 .4byte 0x6f - 1351 0139 02 .byte 0x2 - 1352 013a 23 .byte 0x23 - 1353 013b 05 .uleb128 0x5 - 1354 013c 0A .uleb128 0xa - 1355 013d 0C040000 .4byte .LASF25 - 1356 0141 03 .byte 0x3 - 1357 0142 81 .byte 0x81 - 1358 0143 7A000000 .4byte 0x7a - 1359 0147 02 .byte 0x2 - 1360 0148 23 .byte 0x23 - 1361 0149 06 .uleb128 0x6 - 1362 014a 0A .uleb128 0xa - 1363 014b F5030000 .4byte .LASF26 - 1364 014f 03 .byte 0x3 - 1365 0150 82 .byte 0x82 - 1366 0151 7A000000 .4byte 0x7a - 1367 0155 02 .byte 0x2 - 1368 0156 23 .byte 0x23 - 1369 0157 08 .uleb128 0x8 - 1370 0158 0A .uleb128 0xa - 1371 0159 3C020000 .4byte .LASF27 - 1372 015d 03 .byte 0x3 - 1373 015e 83 .byte 0x83 - 1374 015f 6F000000 .4byte 0x6f - 1375 0163 02 .byte 0x2 - 1376 0164 23 .byte 0x23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 50 - - - 1377 0165 0A .uleb128 0xa - 1378 0166 00 .byte 0 - 1379 0167 04 .uleb128 0x4 - 1380 0168 AE030000 .4byte .LASF28 - 1381 016c 03 .byte 0x3 - 1382 016d 84 .byte 0x84 - 1383 016e E0000000 .4byte 0xe0 - 1384 0172 0B .uleb128 0xb - 1385 0173 01 .byte 0x1 - 1386 0174 C3020000 .4byte .LASF29 - 1387 0178 01 .byte 0x1 - 1388 0179 87 .byte 0x87 - 1389 017a 01 .byte 0x1 - 1390 017b 00000000 .4byte .LFB1 - 1391 017f 14010000 .4byte .LFE1 - 1392 0183 00000000 .4byte .LLST0 - 1393 0187 01 .byte 0x1 - 1394 0188 E0020000 .4byte 0x2e0 - 1395 018c 0C .uleb128 0xc - 1396 018d 51040000 .4byte .LASF33 - 1397 0191 01 .byte 0x1 - 1398 0192 89 .byte 0x89 - 1399 0193 6F000000 .4byte 0x6f - 1400 0197 20000000 .4byte .LLST1 - 1401 019b 0D .uleb128 0xd - 1402 019c 06000000 .4byte .LVL0 - 1403 01a0 46080000 .4byte 0x846 - 1404 01a4 0E .uleb128 0xe - 1405 01a5 3A000000 .4byte .LVL3 - 1406 01a9 54080000 .4byte 0x854 - 1407 01ad B7010000 .4byte 0x1b7 - 1408 01b1 0F .uleb128 0xf - 1409 01b2 01 .byte 0x1 - 1410 01b3 50 .byte 0x50 - 1411 01b4 01 .byte 0x1 - 1412 01b5 30 .byte 0x30 - 1413 01b6 00 .byte 0 - 1414 01b7 0E .uleb128 0xe - 1415 01b8 58000000 .4byte .LVL4 - 1416 01bc 54080000 .4byte 0x854 - 1417 01c0 CB010000 .4byte 0x1cb - 1418 01c4 0F .uleb128 0xf - 1419 01c5 01 .byte 0x1 - 1420 01c6 50 .byte 0x50 - 1421 01c7 02 .byte 0x2 - 1422 01c8 75 .byte 0x75 - 1423 01c9 00 .sleb128 0 - 1424 01ca 00 .byte 0 - 1425 01cb 0E .uleb128 0xe - 1426 01cc 5E000000 .4byte .LVL5 - 1427 01d0 54080000 .4byte 0x854 - 1428 01d4 DF010000 .4byte 0x1df - 1429 01d8 0F .uleb128 0xf - 1430 01d9 01 .byte 0x1 - 1431 01da 50 .byte 0x50 - 1432 01db 02 .byte 0x2 - 1433 01dc 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 51 - - - 1434 01dd 28 .byte 0x28 - 1435 01de 00 .byte 0 - 1436 01df 0E .uleb128 0xe - 1437 01e0 7C000000 .4byte .LVL6 - 1438 01e4 54080000 .4byte 0x854 - 1439 01e8 F3010000 .4byte 0x1f3 - 1440 01ec 0F .uleb128 0xf - 1441 01ed 01 .byte 0x1 - 1442 01ee 50 .byte 0x50 - 1443 01ef 02 .byte 0x2 - 1444 01f0 76 .byte 0x76 - 1445 01f1 00 .sleb128 0 - 1446 01f2 00 .byte 0 - 1447 01f3 0E .uleb128 0xe - 1448 01f4 92000000 .4byte .LVL7 - 1449 01f8 68080000 .4byte 0x868 - 1450 01fc 07020000 .4byte 0x207 - 1451 0200 0F .uleb128 0xf - 1452 0201 01 .byte 0x1 - 1453 0202 50 .byte 0x50 - 1454 0203 02 .byte 0x2 - 1455 0204 77 .byte 0x77 - 1456 0205 00 .sleb128 0 - 1457 0206 00 .byte 0 - 1458 0207 0E .uleb128 0xe - 1459 0208 9A000000 .4byte .LVL8 - 1460 020c 7C080000 .4byte 0x87c - 1461 0210 1A020000 .4byte 0x21a - 1462 0214 0F .uleb128 0xf - 1463 0215 01 .byte 0x1 - 1464 0216 50 .byte 0x50 - 1465 0217 01 .byte 0x1 - 1466 0218 47 .byte 0x47 - 1467 0219 00 .byte 0 - 1468 021a 0E .uleb128 0xe - 1469 021b A2000000 .4byte .LVL9 - 1470 021f 99080000 .4byte 0x899 - 1471 0223 32020000 .4byte 0x232 - 1472 0227 0F .uleb128 0xf - 1473 0228 01 .byte 0x1 - 1474 0229 51 .byte 0x51 - 1475 022a 01 .byte 0x1 - 1476 022b 37 .byte 0x37 - 1477 022c 0F .uleb128 0xf - 1478 022d 01 .byte 0x1 - 1479 022e 50 .byte 0x50 - 1480 022f 01 .byte 0x1 - 1481 0230 47 .byte 0x47 - 1482 0231 00 .byte 0 - 1483 0232 0E .uleb128 0xe - 1484 0233 AA000000 .4byte .LVL10 - 1485 0237 7C080000 .4byte 0x87c - 1486 023b 45020000 .4byte 0x245 - 1487 023f 0F .uleb128 0xf - 1488 0240 01 .byte 0x1 - 1489 0241 50 .byte 0x50 - 1490 0242 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 52 - - - 1491 0243 45 .byte 0x45 - 1492 0244 00 .byte 0 - 1493 0245 0E .uleb128 0xe - 1494 0246 B2000000 .4byte .LVL11 - 1495 024a 99080000 .4byte 0x899 - 1496 024e 5D020000 .4byte 0x25d - 1497 0252 0F .uleb128 0xf - 1498 0253 01 .byte 0x1 - 1499 0254 51 .byte 0x51 - 1500 0255 01 .byte 0x1 - 1501 0256 37 .byte 0x37 - 1502 0257 0F .uleb128 0xf - 1503 0258 01 .byte 0x1 - 1504 0259 50 .byte 0x50 - 1505 025a 01 .byte 0x1 - 1506 025b 45 .byte 0x45 - 1507 025c 00 .byte 0 - 1508 025d 0E .uleb128 0xe - 1509 025e BA000000 .4byte .LVL12 - 1510 0262 7C080000 .4byte 0x87c - 1511 0266 70020000 .4byte 0x270 - 1512 026a 0F .uleb128 0xf - 1513 026b 01 .byte 0x1 - 1514 026c 50 .byte 0x50 - 1515 026d 01 .byte 0x1 - 1516 026e 48 .byte 0x48 - 1517 026f 00 .byte 0 - 1518 0270 0E .uleb128 0xe - 1519 0271 C2000000 .4byte .LVL13 - 1520 0275 99080000 .4byte 0x899 - 1521 0279 88020000 .4byte 0x288 - 1522 027d 0F .uleb128 0xf - 1523 027e 01 .byte 0x1 - 1524 027f 51 .byte 0x51 - 1525 0280 01 .byte 0x1 - 1526 0281 37 .byte 0x37 - 1527 0282 0F .uleb128 0xf - 1528 0283 01 .byte 0x1 - 1529 0284 50 .byte 0x50 - 1530 0285 01 .byte 0x1 - 1531 0286 48 .byte 0x48 - 1532 0287 00 .byte 0 - 1533 0288 0E .uleb128 0xe - 1534 0289 CA000000 .4byte .LVL14 - 1535 028d 7C080000 .4byte 0x87c - 1536 0291 9C020000 .4byte 0x29c - 1537 0295 0F .uleb128 0xf - 1538 0296 01 .byte 0x1 - 1539 0297 50 .byte 0x50 - 1540 0298 02 .byte 0x2 - 1541 0299 74 .byte 0x74 - 1542 029a 00 .sleb128 0 - 1543 029b 00 .byte 0 - 1544 029c 0E .uleb128 0xe - 1545 029d D2000000 .4byte .LVL15 - 1546 02a1 99080000 .4byte 0x899 - 1547 02a5 B5020000 .4byte 0x2b5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 53 - - - 1548 02a9 0F .uleb128 0xf - 1549 02aa 01 .byte 0x1 - 1550 02ab 51 .byte 0x51 - 1551 02ac 01 .byte 0x1 - 1552 02ad 37 .byte 0x37 - 1553 02ae 0F .uleb128 0xf - 1554 02af 01 .byte 0x1 - 1555 02b0 50 .byte 0x50 - 1556 02b1 02 .byte 0x2 - 1557 02b2 74 .byte 0x74 - 1558 02b3 00 .sleb128 0 - 1559 02b4 00 .byte 0 - 1560 02b5 0E .uleb128 0xe - 1561 02b6 DA000000 .4byte .LVL16 - 1562 02ba 7C080000 .4byte 0x87c - 1563 02be C9020000 .4byte 0x2c9 - 1564 02c2 0F .uleb128 0xf - 1565 02c3 01 .byte 0x1 - 1566 02c4 50 .byte 0x50 - 1567 02c5 02 .byte 0x2 - 1568 02c6 75 .byte 0x75 - 1569 02c7 00 .sleb128 0 - 1570 02c8 00 .byte 0 - 1571 02c9 10 .uleb128 0x10 - 1572 02ca E6000000 .4byte .LVL17 - 1573 02ce 01 .byte 0x1 - 1574 02cf 99080000 .4byte 0x899 - 1575 02d3 0F .uleb128 0xf - 1576 02d4 01 .byte 0x1 - 1577 02d5 51 .byte 0x51 - 1578 02d6 01 .byte 0x1 - 1579 02d7 37 .byte 0x37 - 1580 02d8 0F .uleb128 0xf - 1581 02d9 01 .byte 0x1 - 1582 02da 50 .byte 0x50 - 1583 02db 02 .byte 0x2 - 1584 02dc 75 .byte 0x75 - 1585 02dd 00 .sleb128 0 - 1586 02de 00 .byte 0 - 1587 02df 00 .byte 0 - 1588 02e0 11 .uleb128 0x11 - 1589 02e1 01 .byte 0x1 - 1590 02e2 9F010000 .4byte .LASF30 - 1591 02e6 01 .byte 0x1 - 1592 02e7 4201 .2byte 0x142 - 1593 02e9 01 .byte 0x1 - 1594 02ea 00000000 .4byte .LFB2 - 1595 02ee 98000000 .4byte .LFE2 - 1596 02f2 3E000000 .4byte .LLST2 - 1597 02f6 01 .byte 0x1 - 1598 02f7 39030000 .4byte 0x339 - 1599 02fb 12 .uleb128 0x12 - 1600 02fc 92000000 .4byte .LASF31 - 1601 0300 01 .byte 0x1 - 1602 0301 4201 .2byte 0x142 - 1603 0303 6F000000 .4byte 0x6f - 1604 0307 5E000000 .4byte .LLST3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 54 - - - 1605 030b 12 .uleb128 0x12 - 1606 030c E3030000 .4byte .LASF32 - 1607 0310 01 .byte 0x1 - 1608 0311 4201 .2byte 0x142 - 1609 0313 6F000000 .4byte 0x6f - 1610 0317 8B000000 .4byte .LLST4 - 1611 031b 13 .uleb128 0x13 - 1612 031c 6900 .ascii "i\000" - 1613 031e 01 .byte 0x1 - 1614 031f 4901 .2byte 0x149 - 1615 0321 6F000000 .4byte 0x6f - 1616 0325 AC000000 .4byte .LLST5 - 1617 0329 14 .uleb128 0x14 - 1618 032a 5A000000 .4byte .LVL23 - 1619 032e B2080000 .4byte 0x8b2 - 1620 0332 0F .uleb128 0xf - 1621 0333 01 .byte 0x1 - 1622 0334 50 .byte 0x50 - 1623 0335 01 .byte 0x1 - 1624 0336 31 .byte 0x31 - 1625 0337 00 .byte 0 - 1626 0338 00 .byte 0 - 1627 0339 0B .uleb128 0xb - 1628 033a 01 .byte 0x1 - 1629 033b 00040000 .4byte .LASF34 - 1630 033f 01 .byte 0x1 - 1631 0340 6A .byte 0x6a - 1632 0341 01 .byte 0x1 - 1633 0342 00000000 .4byte .LFB0 - 1634 0346 24000000 .4byte .LFE0 - 1635 034a CC000000 .4byte .LLST6 - 1636 034e 01 .byte 0x1 - 1637 034f 92030000 .4byte 0x392 - 1638 0353 15 .uleb128 0x15 - 1639 0354 92000000 .4byte .LASF31 - 1640 0358 01 .byte 0x1 - 1641 0359 6A .byte 0x6a - 1642 035a 6F000000 .4byte 0x6f - 1643 035e EC000000 .4byte .LLST7 - 1644 0362 15 .uleb128 0x15 - 1645 0363 E3030000 .4byte .LASF32 - 1646 0367 01 .byte 0x1 - 1647 0368 6A .byte 0x6a - 1648 0369 6F000000 .4byte 0x6f - 1649 036d 0D010000 .4byte .LLST8 - 1650 0371 0D .uleb128 0xd - 1651 0372 10000000 .4byte .LVL25 - 1652 0376 72010000 .4byte 0x172 - 1653 037a 10 .uleb128 0x10 - 1654 037b 20000000 .4byte .LVL26 - 1655 037f 01 .byte 0x1 - 1656 0380 E0020000 .4byte 0x2e0 - 1657 0384 0F .uleb128 0xf - 1658 0385 01 .byte 0x1 - 1659 0386 51 .byte 0x51 - 1660 0387 02 .byte 0x2 - 1661 0388 75 .byte 0x75 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 55 - - - 1662 0389 00 .sleb128 0 - 1663 038a 0F .uleb128 0xf - 1664 038b 01 .byte 0x1 - 1665 038c 50 .byte 0x50 - 1666 038d 02 .byte 0x2 - 1667 038e 76 .byte 0x76 - 1668 038f 00 .sleb128 0 - 1669 0390 00 .byte 0 - 1670 0391 00 .byte 0 - 1671 0392 16 .uleb128 0x16 - 1672 0393 01 .byte 0x1 - 1673 0394 3B040000 .4byte .LASF35 - 1674 0398 01 .byte 0x1 - 1675 0399 D301 .2byte 0x1d3 - 1676 039b 01 .byte 0x1 - 1677 039c 00000000 .4byte .LFB3 - 1678 03a0 58000000 .4byte .LFE3 - 1679 03a4 02 .byte 0x2 - 1680 03a5 7D .byte 0x7d - 1681 03a6 00 .sleb128 0 - 1682 03a7 01 .byte 0x1 - 1683 03a8 BB030000 .4byte 0x3bb - 1684 03ac 13 .uleb128 0x13 - 1685 03ad 6900 .ascii "i\000" - 1686 03af 01 .byte 0x1 - 1687 03b0 D901 .2byte 0x1d9 - 1688 03b2 6F000000 .4byte 0x6f - 1689 03b6 2E010000 .4byte .LLST9 - 1690 03ba 00 .byte 0 - 1691 03bb 17 .uleb128 0x17 - 1692 03bc 01 .byte 0x1 - 1693 03bd 41010000 .4byte .LASF75 - 1694 03c1 01 .byte 0x1 - 1695 03c2 1502 .2byte 0x215 - 1696 03c4 01 .byte 0x1 - 1697 03c5 00000000 .4byte .LFB4 - 1698 03c9 7C000000 .4byte .LFE4 - 1699 03cd 02 .byte 0x2 - 1700 03ce 7D .byte 0x7d - 1701 03cf 00 .sleb128 0 - 1702 03d0 01 .byte 0x1 - 1703 03d1 18 .uleb128 0x18 - 1704 03d2 01 .byte 0x1 - 1705 03d3 62040000 .4byte .LASF36 - 1706 03d7 01 .byte 0x1 - 1707 03d8 5C02 .2byte 0x25c - 1708 03da 01 .byte 0x1 - 1709 03db 6F000000 .4byte 0x6f - 1710 03df 00000000 .4byte .LFB5 - 1711 03e3 14000000 .4byte .LFE5 - 1712 03e7 02 .byte 0x2 - 1713 03e8 7D .byte 0x7d - 1714 03e9 00 .sleb128 0 - 1715 03ea 01 .byte 0x1 - 1716 03eb FE030000 .4byte 0x3fe - 1717 03ef 13 .uleb128 0x13 - 1718 03f0 7200 .ascii "r\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 56 - - - 1719 03f2 01 .byte 0x1 - 1720 03f3 5E02 .2byte 0x25e - 1721 03f5 6F000000 .4byte 0x6f - 1722 03f9 4E010000 .4byte .LLST10 - 1723 03fd 00 .byte 0 - 1724 03fe 19 .uleb128 0x19 - 1725 03ff 01 .byte 0x1 - 1726 0400 55010000 .4byte .LASF76 - 1727 0404 01 .byte 0x1 - 1728 0405 7502 .2byte 0x275 - 1729 0407 01 .byte 0x1 - 1730 0408 6F000000 .4byte 0x6f - 1731 040c 00000000 .4byte .LFB6 - 1732 0410 0C000000 .4byte .LFE6 - 1733 0414 02 .byte 0x2 - 1734 0415 7D .byte 0x7d - 1735 0416 00 .sleb128 0 - 1736 0417 01 .byte 0x1 - 1737 0418 18 .uleb128 0x18 - 1738 0419 01 .byte 0x1 - 1739 041a D4000000 .4byte .LASF37 - 1740 041e 01 .byte 0x1 - 1741 041f 8F02 .2byte 0x28f - 1742 0421 01 .byte 0x1 - 1743 0422 6F000000 .4byte 0x6f - 1744 0426 00000000 .4byte .LFB7 - 1745 042a 14000000 .4byte .LFE7 - 1746 042e 02 .byte 0x2 - 1747 042f 7D .byte 0x7d - 1748 0430 00 .sleb128 0 - 1749 0431 01 .byte 0x1 - 1750 0432 47040000 .4byte 0x447 - 1751 0436 13 .uleb128 0x13 - 1752 0437 72657300 .ascii "res\000" - 1753 043b 01 .byte 0x1 - 1754 043c 9102 .2byte 0x291 - 1755 043e 6F000000 .4byte 0x6f - 1756 0442 61010000 .4byte .LLST11 - 1757 0446 00 .byte 0 - 1758 0447 18 .uleb128 0x18 - 1759 0448 01 .byte 0x1 - 1760 0449 A2040000 .4byte .LASF38 - 1761 044d 01 .byte 0x1 - 1762 044e AB02 .2byte 0x2ab - 1763 0450 01 .byte 0x1 - 1764 0451 6F000000 .4byte 0x6f - 1765 0455 00000000 .4byte .LFB8 - 1766 0459 0C000000 .4byte .LFE8 - 1767 045d 02 .byte 0x2 - 1768 045e 7D .byte 0x7d - 1769 045f 00 .sleb128 0 - 1770 0460 01 .byte 0x1 - 1771 0461 76040000 .4byte 0x476 - 1772 0465 12 .uleb128 0x12 - 1773 0466 79000000 .4byte .LASF39 - 1774 046a 01 .byte 0x1 - 1775 046b AB02 .2byte 0x2ab - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 57 - - - 1776 046d 6F000000 .4byte 0x6f - 1777 0471 80010000 .4byte .LLST12 - 1778 0475 00 .byte 0 - 1779 0476 18 .uleb128 0x18 - 1780 0477 01 .byte 0x1 - 1781 0478 2A040000 .4byte .LASF40 - 1782 047c 01 .byte 0x1 - 1783 047d C002 .2byte 0x2c0 - 1784 047f 01 .byte 0x1 - 1785 0480 6F000000 .4byte 0x6f - 1786 0484 00000000 .4byte .LFB9 - 1787 0488 10000000 .4byte .LFE9 - 1788 048c 02 .byte 0x2 - 1789 048d 7D .byte 0x7d - 1790 048e 00 .sleb128 0 - 1791 048f 01 .byte 0x1 - 1792 0490 A5040000 .4byte 0x4a5 - 1793 0494 12 .uleb128 0x12 - 1794 0495 89000000 .4byte .LASF41 - 1795 0499 01 .byte 0x1 - 1796 049a C002 .2byte 0x2c0 - 1797 049c 6F000000 .4byte 0x6f - 1798 04a0 A1010000 .4byte .LLST13 - 1799 04a4 00 .byte 0 - 1800 04a5 18 .uleb128 0x18 - 1801 04a6 01 .byte 0x1 - 1802 04a7 BC040000 .4byte .LASF42 - 1803 04ab 01 .byte 0x1 - 1804 04ac D902 .2byte 0x2d9 - 1805 04ae 01 .byte 0x1 - 1806 04af 7A000000 .4byte 0x7a - 1807 04b3 00000000 .4byte .LFB10 - 1808 04b7 2C000000 .4byte .LFE10 - 1809 04bb 02 .byte 0x2 - 1810 04bc 7D .byte 0x7d - 1811 04bd 00 .sleb128 0 - 1812 04be 01 .byte 0x1 - 1813 04bf F3040000 .4byte 0x4f3 - 1814 04c3 12 .uleb128 0x12 - 1815 04c4 89000000 .4byte .LASF41 - 1816 04c8 01 .byte 0x1 - 1817 04c9 D902 .2byte 0x2d9 - 1818 04cb 6F000000 .4byte 0x6f - 1819 04cf C2010000 .4byte .LLST14 - 1820 04d3 13 .uleb128 0x13 - 1821 04d4 726900 .ascii "ri\000" - 1822 04d7 01 .byte 0x1 - 1823 04d8 DB02 .2byte 0x2db - 1824 04da 6F000000 .4byte 0x6f - 1825 04de E3010000 .4byte .LLST15 - 1826 04e2 1A .uleb128 0x1a - 1827 04e3 CD040000 .4byte .LASF43 - 1828 04e7 01 .byte 0x1 - 1829 04e8 DC02 .2byte 0x2dc - 1830 04ea 7A000000 .4byte 0x7a - 1831 04ee 09020000 .4byte .LLST16 - 1832 04f2 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 58 - - - 1833 04f3 11 .uleb128 0x11 - 1834 04f4 01 .byte 0x1 - 1835 04f5 93040000 .4byte .LASF44 - 1836 04f9 01 .byte 0x1 - 1837 04fa 9003 .2byte 0x390 - 1838 04fc 01 .byte 0x1 - 1839 04fd 00000000 .4byte .LFB11 - 1840 0501 7C000000 .4byte .LFE11 - 1841 0505 5C020000 .4byte .LLST17 - 1842 0509 01 .byte 0x1 - 1843 050a 66050000 .4byte 0x566 - 1844 050e 12 .uleb128 0x12 - 1845 050f 89000000 .4byte .LASF41 - 1846 0513 01 .byte 0x1 - 1847 0514 9003 .2byte 0x390 - 1848 0516 6F000000 .4byte 0x6f - 1849 051a 7C020000 .4byte .LLST18 - 1850 051e 12 .uleb128 0x12 - 1851 051f B3010000 .4byte .LASF45 - 1852 0523 01 .byte 0x1 - 1853 0524 9003 .2byte 0x390 - 1854 0526 66050000 .4byte 0x566 - 1855 052a A8020000 .4byte .LLST19 - 1856 052e 12 .uleb128 0x12 - 1857 052f D7030000 .4byte .LASF46 - 1858 0533 01 .byte 0x1 - 1859 0534 9003 .2byte 0x390 - 1860 0536 7A000000 .4byte 0x7a - 1861 053a D4020000 .4byte .LLST20 - 1862 053e 13 .uleb128 0x13 - 1863 053f 726900 .ascii "ri\000" - 1864 0542 01 .byte 0x1 - 1865 0543 9303 .2byte 0x393 - 1866 0545 6F000000 .4byte 0x6f - 1867 0549 0B030000 .4byte .LLST21 - 1868 054d 13 .uleb128 0x13 - 1869 054e 7000 .ascii "p\000" - 1870 0550 01 .byte 0x1 - 1871 0551 9403 .2byte 0x394 - 1872 0553 71050000 .4byte 0x571 - 1873 0557 40030000 .4byte .LLST22 - 1874 055b 1B .uleb128 0x1b - 1875 055c 6900 .ascii "i\000" - 1876 055e 01 .byte 0x1 - 1877 055f 9603 .2byte 0x396 - 1878 0561 7A000000 .4byte 0x7a - 1879 0565 00 .byte 0 - 1880 0566 07 .uleb128 0x7 - 1881 0567 04 .byte 0x4 - 1882 0568 6C050000 .4byte 0x56c - 1883 056c 1C .uleb128 0x1c - 1884 056d 6F000000 .4byte 0x6f - 1885 0571 07 .uleb128 0x7 - 1886 0572 04 .byte 0x4 - 1887 0573 A5000000 .4byte 0xa5 - 1888 0577 16 .uleb128 0x16 - 1889 0578 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 59 - - - 1890 0579 70030000 .4byte .LASF47 - 1891 057d 01 .byte 0x1 - 1892 057e 7D04 .2byte 0x47d - 1893 0580 01 .byte 0x1 - 1894 0581 00000000 .4byte .LFB13 - 1895 0585 28000000 .4byte .LFE13 - 1896 0589 02 .byte 0x2 - 1897 058a 7D .byte 0x7d - 1898 058b 00 .sleb128 0 - 1899 058c 01 .byte 0x1 - 1900 058d B1050000 .4byte 0x5b1 - 1901 0591 12 .uleb128 0x12 - 1902 0592 89000000 .4byte .LASF41 - 1903 0596 01 .byte 0x1 - 1904 0597 7D04 .2byte 0x47d - 1905 0599 6F000000 .4byte 0x6f - 1906 059d 53030000 .4byte .LLST23 - 1907 05a1 13 .uleb128 0x13 - 1908 05a2 726900 .ascii "ri\000" - 1909 05a5 01 .byte 0x1 - 1910 05a6 7F04 .2byte 0x47f - 1911 05a8 6F000000 .4byte 0x6f - 1912 05ac 74030000 .4byte .LLST24 - 1913 05b0 00 .byte 0 - 1914 05b1 1D .uleb128 0x1d - 1915 05b2 01 .byte 0x1 - 1916 05b3 D4010000 .4byte .LASF48 - 1917 05b7 01 .byte 0x1 - 1918 05b8 1304 .2byte 0x413 - 1919 05ba 01 .byte 0x1 - 1920 05bb 7A000000 .4byte 0x7a - 1921 05bf 00000000 .4byte .LFB12 - 1922 05c3 4C000000 .4byte .LFE12 - 1923 05c7 8B030000 .4byte .LLST25 - 1924 05cb 01 .byte 0x1 - 1925 05cc 60060000 .4byte 0x660 - 1926 05d0 12 .uleb128 0x12 - 1927 05d1 89000000 .4byte .LASF41 - 1928 05d5 01 .byte 0x1 - 1929 05d6 1304 .2byte 0x413 - 1930 05d8 6F000000 .4byte 0x6f - 1931 05dc AB030000 .4byte .LLST26 - 1932 05e0 12 .uleb128 0x12 - 1933 05e1 B3010000 .4byte .LASF45 - 1934 05e5 01 .byte 0x1 - 1935 05e6 1304 .2byte 0x413 - 1936 05e8 60060000 .4byte 0x660 - 1937 05ec E5030000 .4byte .LLST27 - 1938 05f0 12 .uleb128 0x12 - 1939 05f1 D7030000 .4byte .LASF46 - 1940 05f5 01 .byte 0x1 - 1941 05f6 1304 .2byte 0x413 - 1942 05f8 7A000000 .4byte 0x7a - 1943 05fc 03040000 .4byte .LLST28 - 1944 0600 13 .uleb128 0x13 - 1945 0601 726900 .ascii "ri\000" - 1946 0604 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 60 - - - 1947 0605 1604 .2byte 0x416 - 1948 0607 6F000000 .4byte 0x6f - 1949 060b 50040000 .4byte .LLST29 - 1950 060f 13 .uleb128 0x13 - 1951 0610 7000 .ascii "p\000" - 1952 0612 01 .byte 0x1 - 1953 0613 1704 .2byte 0x417 - 1954 0615 71050000 .4byte 0x571 - 1955 0619 76040000 .4byte .LLST30 - 1956 061d 13 .uleb128 0x13 - 1957 061e 6900 .ascii "i\000" - 1958 0620 01 .byte 0x1 - 1959 0621 1904 .2byte 0x419 - 1960 0623 7A000000 .4byte 0x7a - 1961 0627 89040000 .4byte .LLST31 - 1962 062b 1A .uleb128 0x1a - 1963 062c 76040000 .4byte .LASF49 - 1964 0630 01 .byte 0x1 - 1965 0631 1C04 .2byte 0x41c - 1966 0633 7A000000 .4byte 0x7a - 1967 0637 9D040000 .4byte .LLST32 - 1968 063b 0E .uleb128 0xe - 1969 063c 1E000000 .4byte .LVL67 - 1970 0640 A5040000 .4byte 0x4a5 - 1971 0644 4F060000 .4byte 0x64f - 1972 0648 0F .uleb128 0xf - 1973 0649 01 .byte 0x1 - 1974 064a 50 .byte 0x50 - 1975 064b 02 .byte 0x2 - 1976 064c 77 .byte 0x77 - 1977 064d 00 .sleb128 0 - 1978 064e 00 .byte 0 - 1979 064f 14 .uleb128 0x14 - 1980 0650 3C000000 .4byte .LVL71 - 1981 0654 77050000 .4byte 0x577 - 1982 0658 0F .uleb128 0xf - 1983 0659 01 .byte 0x1 - 1984 065a 50 .byte 0x50 - 1985 065b 02 .byte 0x2 - 1986 065c 77 .byte 0x77 - 1987 065d 00 .sleb128 0 - 1988 065e 00 .byte 0 - 1989 065f 00 .byte 0 - 1990 0660 07 .uleb128 0x7 - 1991 0661 04 .byte 0x4 - 1992 0662 6F000000 .4byte 0x6f - 1993 0666 16 .uleb128 0x16 - 1994 0667 01 .byte 0x1 - 1995 0668 80040000 .4byte .LASF50 - 1996 066c 01 .byte 0x1 - 1997 066d 9B04 .2byte 0x49b - 1998 066f 01 .byte 0x1 - 1999 0670 00000000 .4byte .LFB14 - 2000 0674 18000000 .4byte .LFE14 - 2001 0678 02 .byte 0x2 - 2002 0679 7D .byte 0x7d - 2003 067a 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 61 - - - 2004 067b 01 .byte 0x1 - 2005 067c A0060000 .4byte 0x6a0 - 2006 0680 12 .uleb128 0x12 - 2007 0681 89000000 .4byte .LASF41 - 2008 0685 01 .byte 0x1 - 2009 0686 9B04 .2byte 0x49b - 2010 0688 6F000000 .4byte 0x6f - 2011 068c B0040000 .4byte .LLST33 - 2012 0690 13 .uleb128 0x13 - 2013 0691 726900 .ascii "ri\000" - 2014 0694 01 .byte 0x1 - 2015 0695 9D04 .2byte 0x49d - 2016 0697 6F000000 .4byte 0x6f - 2017 069b D1040000 .4byte .LLST34 - 2018 069f 00 .byte 0 - 2019 06a0 16 .uleb128 0x16 - 2020 06a1 01 .byte 0x1 - 2021 06a2 3D000000 .4byte .LASF51 - 2022 06a6 01 .byte 0x1 - 2023 06a7 BA04 .2byte 0x4ba - 2024 06a9 01 .byte 0x1 - 2025 06aa 00000000 .4byte .LFB15 - 2026 06ae 0C000000 .4byte .LFE15 - 2027 06b2 02 .byte 0x2 - 2028 06b3 7D .byte 0x7d - 2029 06b4 00 .sleb128 0 - 2030 06b5 01 .byte 0x1 - 2031 06b6 C9060000 .4byte 0x6c9 - 2032 06ba 1E .uleb128 0x1e - 2033 06bb D0030000 .4byte .LASF52 - 2034 06bf 01 .byte 0x1 - 2035 06c0 BA04 .2byte 0x4ba - 2036 06c2 6F000000 .4byte 0x6f - 2037 06c6 01 .byte 0x1 - 2038 06c7 50 .byte 0x50 - 2039 06c8 00 .byte 0 - 2040 06c9 18 .uleb128 0x18 - 2041 06ca 01 .byte 0x1 - 2042 06cb 60000000 .4byte .LASF53 - 2043 06cf 01 .byte 0x1 - 2044 06d0 CF04 .2byte 0x4cf - 2045 06d2 01 .byte 0x1 - 2046 06d3 6F000000 .4byte 0x6f - 2047 06d7 00000000 .4byte .LFB16 - 2048 06db 20000000 .4byte .LFE16 - 2049 06df 02 .byte 0x2 - 2050 06e0 7D .byte 0x7d - 2051 06e1 00 .sleb128 0 - 2052 06e2 01 .byte 0x1 - 2053 06e3 16070000 .4byte 0x716 - 2054 06e7 12 .uleb128 0x12 - 2055 06e8 89000000 .4byte .LASF41 - 2056 06ec 01 .byte 0x1 - 2057 06ed CF04 .2byte 0x4cf - 2058 06ef 6F000000 .4byte 0x6f - 2059 06f3 E8040000 .4byte .LLST35 - 2060 06f7 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 62 - - - 2061 06f8 726900 .ascii "ri\000" - 2062 06fb 01 .byte 0x1 - 2063 06fc D104 .2byte 0x4d1 - 2064 06fe 6F000000 .4byte 0x6f - 2065 0702 09050000 .4byte .LLST36 - 2066 0706 13 .uleb128 0x13 - 2067 0707 637200 .ascii "cr\000" - 2068 070a 01 .byte 0x1 - 2069 070b D204 .2byte 0x4d2 - 2070 070d 6F000000 .4byte 0x6f - 2071 0711 20050000 .4byte .LLST37 - 2072 0715 00 .byte 0 - 2073 0716 16 .uleb128 0x16 - 2074 0717 01 .byte 0x1 - 2075 0718 2C010000 .4byte .LASF54 - 2076 071c 01 .byte 0x1 - 2077 071d F404 .2byte 0x4f4 - 2078 071f 01 .byte 0x1 - 2079 0720 00000000 .4byte .LFB17 - 2080 0724 18000000 .4byte .LFE17 - 2081 0728 02 .byte 0x2 - 2082 0729 7D .byte 0x7d - 2083 072a 00 .sleb128 0 - 2084 072b 01 .byte 0x1 - 2085 072c 41070000 .4byte 0x741 - 2086 0730 12 .uleb128 0x12 - 2087 0731 8C010000 .4byte .LASF55 - 2088 0735 01 .byte 0x1 - 2089 0736 F404 .2byte 0x4f4 - 2090 0738 6F000000 .4byte 0x6f - 2091 073c 56050000 .4byte .LLST38 - 2092 0740 00 .byte 0 - 2093 0741 18 .uleb128 0x18 - 2094 0742 01 .byte 0x1 - 2095 0743 1B010000 .4byte .LASF56 - 2096 0747 01 .byte 0x1 - 2097 0748 2B05 .2byte 0x52b - 2098 074a 01 .byte 0x1 - 2099 074b 6F000000 .4byte 0x6f - 2100 074f 00000000 .4byte .LFB18 - 2101 0753 10000000 .4byte .LFE18 - 2102 0757 02 .byte 0x2 - 2103 0758 7D .byte 0x7d - 2104 0759 00 .sleb128 0 - 2105 075a 01 .byte 0x1 - 2106 075b 70070000 .4byte 0x770 - 2107 075f 1A .uleb128 0x1a - 2108 0760 CD040000 .4byte .LASF43 - 2109 0764 01 .byte 0x1 - 2110 0765 2D05 .2byte 0x52d - 2111 0767 6F000000 .4byte 0x6f - 2112 076b 90050000 .4byte .LLST39 - 2113 076f 00 .byte 0 - 2114 0770 1F .uleb128 0x1f - 2115 0771 1D000000 .4byte .LASF57 - 2116 0775 01 .byte 0x1 - 2117 0776 36 .byte 0x36 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 63 - - - 2118 0777 6F000000 .4byte 0x6f - 2119 077b 01 .byte 0x1 - 2120 077c 05 .byte 0x5 - 2121 077d 03 .byte 0x3 - 2122 077e 00000000 .4byte USBFS_initVar - 2123 0782 20 .uleb128 0x20 - 2124 0783 C3030000 .4byte .LASF58 - 2125 0787 03 .byte 0x3 - 2126 0788 1802 .2byte 0x218 - 2127 078a B0000000 .4byte 0xb0 - 2128 078e 01 .byte 0x1 - 2129 078f 01 .byte 0x1 - 2130 0790 20 .uleb128 0x20 - 2131 0791 44030000 .4byte .LASF59 - 2132 0795 03 .byte 0x3 - 2133 0796 1902 .2byte 0x219 - 2134 0798 B0000000 .4byte 0xb0 - 2135 079c 01 .byte 0x1 - 2136 079d 01 .byte 0x1 - 2137 079e 20 .uleb128 0x20 - 2138 079f B9010000 .4byte .LASF60 - 2139 07a3 03 .byte 0x3 - 2140 07a4 1A02 .2byte 0x21a - 2141 07a6 B0000000 .4byte 0xb0 - 2142 07aa 01 .byte 0x1 - 2143 07ab 01 .byte 0x1 - 2144 07ac 20 .uleb128 0x20 - 2145 07ad 46020000 .4byte .LASF61 - 2146 07b1 03 .byte 0x3 - 2147 07b2 1B02 .2byte 0x21b - 2148 07b4 B0000000 .4byte 0xb0 - 2149 07b8 01 .byte 0x1 - 2150 07b9 01 .byte 0x1 - 2151 07ba 20 .uleb128 0x20 - 2152 07bb 17040000 .4byte .LASF62 - 2153 07bf 03 .byte 0x3 - 2154 07c0 1C02 .2byte 0x21c - 2155 07c2 B0000000 .4byte 0xb0 - 2156 07c6 01 .byte 0x1 - 2157 07c7 01 .byte 0x1 - 2158 07c8 21 .uleb128 0x21 - 2159 07c9 6F000000 .4byte 0x6f - 2160 07cd D8070000 .4byte 0x7d8 - 2161 07d1 22 .uleb128 0x22 - 2162 07d2 D9000000 .4byte 0xd9 - 2163 07d6 00 .byte 0 - 2164 07d7 00 .byte 0 - 2165 07d8 20 .uleb128 0x20 - 2166 07d9 2B000000 .4byte .LASF63 - 2167 07dd 03 .byte 0x3 - 2168 07de 2002 .2byte 0x220 - 2169 07e0 E6070000 .4byte 0x7e6 - 2170 07e4 01 .byte 0x1 - 2171 07e5 01 .byte 0x1 - 2172 07e6 05 .uleb128 0x5 - 2173 07e7 C8070000 .4byte 0x7c8 - 2174 07eb 23 .uleb128 0x23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 64 - - - 2175 07ec 05010000 .4byte .LASF64 - 2176 07f0 04 .byte 0x4 - 2177 07f1 38 .byte 0x38 - 2178 07f2 B0000000 .4byte 0xb0 - 2179 07f6 01 .byte 0x1 - 2180 07f7 01 .byte 0x1 - 2181 07f8 23 .uleb128 0x23 - 2182 07f9 97030000 .4byte .LASF65 - 2183 07fd 04 .byte 0x4 - 2184 07fe 39 .byte 0x39 - 2185 07ff 05080000 .4byte 0x805 - 2186 0803 01 .byte 0x1 - 2187 0804 01 .byte 0x1 - 2188 0805 05 .uleb128 0x5 - 2189 0806 C8070000 .4byte 0x7c8 - 2190 080a 23 .uleb128 0x23 - 2191 080b F1000000 .4byte .LASF66 - 2192 080f 04 .byte 0x4 - 2193 0810 3B .byte 0x3b - 2194 0811 B0000000 .4byte 0xb0 - 2195 0815 01 .byte 0x1 - 2196 0816 01 .byte 0x1 - 2197 0817 21 .uleb128 0x21 - 2198 0818 67010000 .4byte 0x167 - 2199 081c 27080000 .4byte 0x827 - 2200 0820 22 .uleb128 0x22 - 2201 0821 D9000000 .4byte 0xd9 - 2202 0825 08 .byte 0x8 - 2203 0826 00 .byte 0 - 2204 0827 23 .uleb128 0x23 - 2205 0828 DF020000 .4byte .LASF67 - 2206 082c 04 .byte 0x4 - 2207 082d 3F .byte 0x3f - 2208 082e 34080000 .4byte 0x834 - 2209 0832 01 .byte 0x1 - 2210 0833 01 .byte 0x1 - 2211 0834 05 .uleb128 0x5 - 2212 0835 17080000 .4byte 0x817 - 2213 0839 23 .uleb128 0x23 - 2214 083a 82030000 .4byte .LASF68 - 2215 083e 04 .byte 0x4 - 2216 083f 48 .byte 0x48 - 2217 0840 B0000000 .4byte 0xb0 - 2218 0844 01 .byte 0x1 - 2219 0845 01 .byte 0x1 - 2220 0846 24 .uleb128 0x24 - 2221 0847 01 .byte 0x1 - 2222 0848 03020000 .4byte .LASF77 - 2223 084c 05 .byte 0x5 - 2224 084d 7E .byte 0x7e - 2225 084e 01 .byte 0x1 - 2226 084f 6F000000 .4byte 0x6f - 2227 0853 01 .byte 0x1 - 2228 0854 25 .uleb128 0x25 - 2229 0855 01 .byte 0x1 - 2230 0856 7B010000 .4byte .LASF69 - 2231 085a 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 65 - - - 2232 085b 78 .byte 0x78 - 2233 085c 01 .byte 0x1 - 2234 085d 01 .byte 0x1 - 2235 085e 68080000 .4byte 0x868 - 2236 0862 26 .uleb128 0x26 - 2237 0863 7A000000 .4byte 0x7a - 2238 0867 00 .byte 0 - 2239 0868 25 .uleb128 0x25 - 2240 0869 01 .byte 0x1 - 2241 086a 07000000 .4byte .LASF70 - 2242 086e 05 .byte 0x5 - 2243 086f 7F .byte 0x7f - 2244 0870 01 .byte 0x1 - 2245 0871 01 .byte 0x1 - 2246 0872 7C080000 .4byte 0x87c - 2247 0876 26 .uleb128 0x26 - 2248 0877 6F000000 .4byte 0x6f - 2249 087b 00 .byte 0 - 2250 087c 27 .uleb128 0x27 - 2251 087d 01 .byte 0x1 - 2252 087e 2D020000 .4byte .LASF78 - 2253 0882 05 .byte 0x5 - 2254 0883 89 .byte 0x89 - 2255 0884 01 .byte 0x1 - 2256 0885 C5000000 .4byte 0xc5 - 2257 0889 01 .byte 0x1 - 2258 088a 99080000 .4byte 0x899 - 2259 088e 26 .uleb128 0x26 - 2260 088f 6F000000 .4byte 0x6f - 2261 0893 26 .uleb128 0x26 - 2262 0894 C5000000 .4byte 0xc5 - 2263 0898 00 .byte 0 - 2264 0899 25 .uleb128 0x25 - 2265 089a 01 .byte 0x1 - 2266 089b B2020000 .4byte .LASF71 - 2267 089f 05 .byte 0x5 - 2268 08a0 8C .byte 0x8c - 2269 08a1 01 .byte 0x1 - 2270 08a2 01 .byte 0x1 - 2271 08a3 B2080000 .4byte 0x8b2 - 2272 08a7 26 .uleb128 0x26 - 2273 08a8 6F000000 .4byte 0x6f - 2274 08ac 26 .uleb128 0x26 - 2275 08ad 6F000000 .4byte 0x6f - 2276 08b1 00 .byte 0 - 2277 08b2 28 .uleb128 0x28 - 2278 08b3 01 .byte 0x1 - 2279 08b4 E8020000 .4byte .LASF79 - 2280 08b8 05 .byte 0x5 - 2281 08b9 7A .byte 0x7a - 2282 08ba 01 .byte 0x1 - 2283 08bb 01 .byte 0x1 - 2284 08bc 26 .uleb128 0x26 - 2285 08bd 85000000 .4byte 0x85 - 2286 08c1 00 .byte 0 - 2287 08c2 00 .byte 0 - 2288 .section .debug_abbrev,"",%progbits - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 66 - - - 2289 .Ldebug_abbrev0: - 2290 0000 01 .uleb128 0x1 - 2291 0001 11 .uleb128 0x11 - 2292 0002 01 .byte 0x1 - 2293 0003 25 .uleb128 0x25 - 2294 0004 0E .uleb128 0xe - 2295 0005 13 .uleb128 0x13 - 2296 0006 0B .uleb128 0xb - 2297 0007 03 .uleb128 0x3 - 2298 0008 0E .uleb128 0xe - 2299 0009 1B .uleb128 0x1b - 2300 000a 0E .uleb128 0xe - 2301 000b 55 .uleb128 0x55 - 2302 000c 06 .uleb128 0x6 - 2303 000d 11 .uleb128 0x11 - 2304 000e 01 .uleb128 0x1 - 2305 000f 52 .uleb128 0x52 - 2306 0010 01 .uleb128 0x1 - 2307 0011 10 .uleb128 0x10 - 2308 0012 06 .uleb128 0x6 - 2309 0013 00 .byte 0 - 2310 0014 00 .byte 0 - 2311 0015 02 .uleb128 0x2 - 2312 0016 24 .uleb128 0x24 - 2313 0017 00 .byte 0 - 2314 0018 0B .uleb128 0xb - 2315 0019 0B .uleb128 0xb - 2316 001a 3E .uleb128 0x3e - 2317 001b 0B .uleb128 0xb - 2318 001c 03 .uleb128 0x3 - 2319 001d 0E .uleb128 0xe - 2320 001e 00 .byte 0 - 2321 001f 00 .byte 0 - 2322 0020 03 .uleb128 0x3 - 2323 0021 24 .uleb128 0x24 - 2324 0022 00 .byte 0 - 2325 0023 0B .uleb128 0xb - 2326 0024 0B .uleb128 0xb - 2327 0025 3E .uleb128 0x3e - 2328 0026 0B .uleb128 0xb - 2329 0027 03 .uleb128 0x3 - 2330 0028 08 .uleb128 0x8 - 2331 0029 00 .byte 0 - 2332 002a 00 .byte 0 - 2333 002b 04 .uleb128 0x4 - 2334 002c 16 .uleb128 0x16 - 2335 002d 00 .byte 0 - 2336 002e 03 .uleb128 0x3 - 2337 002f 0E .uleb128 0xe - 2338 0030 3A .uleb128 0x3a - 2339 0031 0B .uleb128 0xb - 2340 0032 3B .uleb128 0x3b - 2341 0033 0B .uleb128 0xb - 2342 0034 49 .uleb128 0x49 - 2343 0035 13 .uleb128 0x13 - 2344 0036 00 .byte 0 - 2345 0037 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 67 - - - 2346 0038 05 .uleb128 0x5 - 2347 0039 35 .uleb128 0x35 - 2348 003a 00 .byte 0 - 2349 003b 49 .uleb128 0x49 - 2350 003c 13 .uleb128 0x13 - 2351 003d 00 .byte 0 - 2352 003e 00 .byte 0 - 2353 003f 06 .uleb128 0x6 - 2354 0040 16 .uleb128 0x16 - 2355 0041 00 .byte 0 - 2356 0042 03 .uleb128 0x3 - 2357 0043 0E .uleb128 0xe - 2358 0044 3A .uleb128 0x3a - 2359 0045 0B .uleb128 0xb - 2360 0046 3B .uleb128 0x3b - 2361 0047 05 .uleb128 0x5 - 2362 0048 49 .uleb128 0x49 - 2363 0049 13 .uleb128 0x13 - 2364 004a 00 .byte 0 - 2365 004b 00 .byte 0 - 2366 004c 07 .uleb128 0x7 - 2367 004d 0F .uleb128 0xf - 2368 004e 00 .byte 0 - 2369 004f 0B .uleb128 0xb - 2370 0050 0B .uleb128 0xb - 2371 0051 49 .uleb128 0x49 - 2372 0052 13 .uleb128 0x13 - 2373 0053 00 .byte 0 - 2374 0054 00 .byte 0 - 2375 0055 08 .uleb128 0x8 - 2376 0056 15 .uleb128 0x15 - 2377 0057 00 .byte 0 - 2378 0058 27 .uleb128 0x27 - 2379 0059 0C .uleb128 0xc - 2380 005a 00 .byte 0 - 2381 005b 00 .byte 0 - 2382 005c 09 .uleb128 0x9 - 2383 005d 13 .uleb128 0x13 - 2384 005e 01 .byte 0x1 - 2385 005f 0B .uleb128 0xb - 2386 0060 0B .uleb128 0xb - 2387 0061 3A .uleb128 0x3a - 2388 0062 0B .uleb128 0xb - 2389 0063 3B .uleb128 0x3b - 2390 0064 0B .uleb128 0xb - 2391 0065 01 .uleb128 0x1 - 2392 0066 13 .uleb128 0x13 - 2393 0067 00 .byte 0 - 2394 0068 00 .byte 0 - 2395 0069 0A .uleb128 0xa - 2396 006a 0D .uleb128 0xd - 2397 006b 00 .byte 0 - 2398 006c 03 .uleb128 0x3 - 2399 006d 0E .uleb128 0xe - 2400 006e 3A .uleb128 0x3a - 2401 006f 0B .uleb128 0xb - 2402 0070 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 68 - - - 2403 0071 0B .uleb128 0xb - 2404 0072 49 .uleb128 0x49 - 2405 0073 13 .uleb128 0x13 - 2406 0074 38 .uleb128 0x38 - 2407 0075 0A .uleb128 0xa - 2408 0076 00 .byte 0 - 2409 0077 00 .byte 0 - 2410 0078 0B .uleb128 0xb - 2411 0079 2E .uleb128 0x2e - 2412 007a 01 .byte 0x1 - 2413 007b 3F .uleb128 0x3f - 2414 007c 0C .uleb128 0xc - 2415 007d 03 .uleb128 0x3 - 2416 007e 0E .uleb128 0xe - 2417 007f 3A .uleb128 0x3a - 2418 0080 0B .uleb128 0xb - 2419 0081 3B .uleb128 0x3b - 2420 0082 0B .uleb128 0xb - 2421 0083 27 .uleb128 0x27 - 2422 0084 0C .uleb128 0xc - 2423 0085 11 .uleb128 0x11 - 2424 0086 01 .uleb128 0x1 - 2425 0087 12 .uleb128 0x12 - 2426 0088 01 .uleb128 0x1 - 2427 0089 40 .uleb128 0x40 - 2428 008a 06 .uleb128 0x6 - 2429 008b 9742 .uleb128 0x2117 - 2430 008d 0C .uleb128 0xc - 2431 008e 01 .uleb128 0x1 - 2432 008f 13 .uleb128 0x13 - 2433 0090 00 .byte 0 - 2434 0091 00 .byte 0 - 2435 0092 0C .uleb128 0xc - 2436 0093 34 .uleb128 0x34 - 2437 0094 00 .byte 0 - 2438 0095 03 .uleb128 0x3 - 2439 0096 0E .uleb128 0xe - 2440 0097 3A .uleb128 0x3a - 2441 0098 0B .uleb128 0xb - 2442 0099 3B .uleb128 0x3b - 2443 009a 0B .uleb128 0xb - 2444 009b 49 .uleb128 0x49 - 2445 009c 13 .uleb128 0x13 - 2446 009d 02 .uleb128 0x2 - 2447 009e 06 .uleb128 0x6 - 2448 009f 00 .byte 0 - 2449 00a0 00 .byte 0 - 2450 00a1 0D .uleb128 0xd - 2451 00a2 898201 .uleb128 0x4109 - 2452 00a5 00 .byte 0 - 2453 00a6 11 .uleb128 0x11 - 2454 00a7 01 .uleb128 0x1 - 2455 00a8 31 .uleb128 0x31 - 2456 00a9 13 .uleb128 0x13 - 2457 00aa 00 .byte 0 - 2458 00ab 00 .byte 0 - 2459 00ac 0E .uleb128 0xe - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 69 - - - 2460 00ad 898201 .uleb128 0x4109 - 2461 00b0 01 .byte 0x1 - 2462 00b1 11 .uleb128 0x11 - 2463 00b2 01 .uleb128 0x1 - 2464 00b3 31 .uleb128 0x31 - 2465 00b4 13 .uleb128 0x13 - 2466 00b5 01 .uleb128 0x1 - 2467 00b6 13 .uleb128 0x13 - 2468 00b7 00 .byte 0 - 2469 00b8 00 .byte 0 - 2470 00b9 0F .uleb128 0xf - 2471 00ba 8A8201 .uleb128 0x410a - 2472 00bd 00 .byte 0 - 2473 00be 02 .uleb128 0x2 - 2474 00bf 0A .uleb128 0xa - 2475 00c0 9142 .uleb128 0x2111 - 2476 00c2 0A .uleb128 0xa - 2477 00c3 00 .byte 0 - 2478 00c4 00 .byte 0 - 2479 00c5 10 .uleb128 0x10 - 2480 00c6 898201 .uleb128 0x4109 - 2481 00c9 01 .byte 0x1 - 2482 00ca 11 .uleb128 0x11 - 2483 00cb 01 .uleb128 0x1 - 2484 00cc 9542 .uleb128 0x2115 - 2485 00ce 0C .uleb128 0xc - 2486 00cf 31 .uleb128 0x31 - 2487 00d0 13 .uleb128 0x13 - 2488 00d1 00 .byte 0 - 2489 00d2 00 .byte 0 - 2490 00d3 11 .uleb128 0x11 - 2491 00d4 2E .uleb128 0x2e - 2492 00d5 01 .byte 0x1 - 2493 00d6 3F .uleb128 0x3f - 2494 00d7 0C .uleb128 0xc - 2495 00d8 03 .uleb128 0x3 - 2496 00d9 0E .uleb128 0xe - 2497 00da 3A .uleb128 0x3a - 2498 00db 0B .uleb128 0xb - 2499 00dc 3B .uleb128 0x3b - 2500 00dd 05 .uleb128 0x5 - 2501 00de 27 .uleb128 0x27 - 2502 00df 0C .uleb128 0xc - 2503 00e0 11 .uleb128 0x11 - 2504 00e1 01 .uleb128 0x1 - 2505 00e2 12 .uleb128 0x12 - 2506 00e3 01 .uleb128 0x1 - 2507 00e4 40 .uleb128 0x40 - 2508 00e5 06 .uleb128 0x6 - 2509 00e6 9742 .uleb128 0x2117 - 2510 00e8 0C .uleb128 0xc - 2511 00e9 01 .uleb128 0x1 - 2512 00ea 13 .uleb128 0x13 - 2513 00eb 00 .byte 0 - 2514 00ec 00 .byte 0 - 2515 00ed 12 .uleb128 0x12 - 2516 00ee 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 70 - - - 2517 00ef 00 .byte 0 - 2518 00f0 03 .uleb128 0x3 - 2519 00f1 0E .uleb128 0xe - 2520 00f2 3A .uleb128 0x3a - 2521 00f3 0B .uleb128 0xb - 2522 00f4 3B .uleb128 0x3b - 2523 00f5 05 .uleb128 0x5 - 2524 00f6 49 .uleb128 0x49 - 2525 00f7 13 .uleb128 0x13 - 2526 00f8 02 .uleb128 0x2 - 2527 00f9 06 .uleb128 0x6 - 2528 00fa 00 .byte 0 - 2529 00fb 00 .byte 0 - 2530 00fc 13 .uleb128 0x13 - 2531 00fd 34 .uleb128 0x34 - 2532 00fe 00 .byte 0 - 2533 00ff 03 .uleb128 0x3 - 2534 0100 08 .uleb128 0x8 - 2535 0101 3A .uleb128 0x3a - 2536 0102 0B .uleb128 0xb - 2537 0103 3B .uleb128 0x3b - 2538 0104 05 .uleb128 0x5 - 2539 0105 49 .uleb128 0x49 - 2540 0106 13 .uleb128 0x13 - 2541 0107 02 .uleb128 0x2 - 2542 0108 06 .uleb128 0x6 - 2543 0109 00 .byte 0 - 2544 010a 00 .byte 0 - 2545 010b 14 .uleb128 0x14 - 2546 010c 898201 .uleb128 0x4109 - 2547 010f 01 .byte 0x1 - 2548 0110 11 .uleb128 0x11 - 2549 0111 01 .uleb128 0x1 - 2550 0112 31 .uleb128 0x31 - 2551 0113 13 .uleb128 0x13 - 2552 0114 00 .byte 0 - 2553 0115 00 .byte 0 - 2554 0116 15 .uleb128 0x15 - 2555 0117 05 .uleb128 0x5 - 2556 0118 00 .byte 0 - 2557 0119 03 .uleb128 0x3 - 2558 011a 0E .uleb128 0xe - 2559 011b 3A .uleb128 0x3a - 2560 011c 0B .uleb128 0xb - 2561 011d 3B .uleb128 0x3b - 2562 011e 0B .uleb128 0xb - 2563 011f 49 .uleb128 0x49 - 2564 0120 13 .uleb128 0x13 - 2565 0121 02 .uleb128 0x2 - 2566 0122 06 .uleb128 0x6 - 2567 0123 00 .byte 0 - 2568 0124 00 .byte 0 - 2569 0125 16 .uleb128 0x16 - 2570 0126 2E .uleb128 0x2e - 2571 0127 01 .byte 0x1 - 2572 0128 3F .uleb128 0x3f - 2573 0129 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 71 - - - 2574 012a 03 .uleb128 0x3 - 2575 012b 0E .uleb128 0xe - 2576 012c 3A .uleb128 0x3a - 2577 012d 0B .uleb128 0xb - 2578 012e 3B .uleb128 0x3b - 2579 012f 05 .uleb128 0x5 - 2580 0130 27 .uleb128 0x27 - 2581 0131 0C .uleb128 0xc - 2582 0132 11 .uleb128 0x11 - 2583 0133 01 .uleb128 0x1 - 2584 0134 12 .uleb128 0x12 - 2585 0135 01 .uleb128 0x1 - 2586 0136 40 .uleb128 0x40 - 2587 0137 0A .uleb128 0xa - 2588 0138 9742 .uleb128 0x2117 - 2589 013a 0C .uleb128 0xc - 2590 013b 01 .uleb128 0x1 - 2591 013c 13 .uleb128 0x13 - 2592 013d 00 .byte 0 - 2593 013e 00 .byte 0 - 2594 013f 17 .uleb128 0x17 - 2595 0140 2E .uleb128 0x2e - 2596 0141 00 .byte 0 - 2597 0142 3F .uleb128 0x3f - 2598 0143 0C .uleb128 0xc - 2599 0144 03 .uleb128 0x3 - 2600 0145 0E .uleb128 0xe - 2601 0146 3A .uleb128 0x3a - 2602 0147 0B .uleb128 0xb - 2603 0148 3B .uleb128 0x3b - 2604 0149 05 .uleb128 0x5 - 2605 014a 27 .uleb128 0x27 - 2606 014b 0C .uleb128 0xc - 2607 014c 11 .uleb128 0x11 - 2608 014d 01 .uleb128 0x1 - 2609 014e 12 .uleb128 0x12 - 2610 014f 01 .uleb128 0x1 - 2611 0150 40 .uleb128 0x40 - 2612 0151 0A .uleb128 0xa - 2613 0152 9742 .uleb128 0x2117 - 2614 0154 0C .uleb128 0xc - 2615 0155 00 .byte 0 - 2616 0156 00 .byte 0 - 2617 0157 18 .uleb128 0x18 - 2618 0158 2E .uleb128 0x2e - 2619 0159 01 .byte 0x1 - 2620 015a 3F .uleb128 0x3f - 2621 015b 0C .uleb128 0xc - 2622 015c 03 .uleb128 0x3 - 2623 015d 0E .uleb128 0xe - 2624 015e 3A .uleb128 0x3a - 2625 015f 0B .uleb128 0xb - 2626 0160 3B .uleb128 0x3b - 2627 0161 05 .uleb128 0x5 - 2628 0162 27 .uleb128 0x27 - 2629 0163 0C .uleb128 0xc - 2630 0164 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 72 - - - 2631 0165 13 .uleb128 0x13 - 2632 0166 11 .uleb128 0x11 - 2633 0167 01 .uleb128 0x1 - 2634 0168 12 .uleb128 0x12 - 2635 0169 01 .uleb128 0x1 - 2636 016a 40 .uleb128 0x40 - 2637 016b 0A .uleb128 0xa - 2638 016c 9742 .uleb128 0x2117 - 2639 016e 0C .uleb128 0xc - 2640 016f 01 .uleb128 0x1 - 2641 0170 13 .uleb128 0x13 - 2642 0171 00 .byte 0 - 2643 0172 00 .byte 0 - 2644 0173 19 .uleb128 0x19 - 2645 0174 2E .uleb128 0x2e - 2646 0175 00 .byte 0 - 2647 0176 3F .uleb128 0x3f - 2648 0177 0C .uleb128 0xc - 2649 0178 03 .uleb128 0x3 - 2650 0179 0E .uleb128 0xe - 2651 017a 3A .uleb128 0x3a - 2652 017b 0B .uleb128 0xb - 2653 017c 3B .uleb128 0x3b - 2654 017d 05 .uleb128 0x5 - 2655 017e 27 .uleb128 0x27 - 2656 017f 0C .uleb128 0xc - 2657 0180 49 .uleb128 0x49 - 2658 0181 13 .uleb128 0x13 - 2659 0182 11 .uleb128 0x11 - 2660 0183 01 .uleb128 0x1 - 2661 0184 12 .uleb128 0x12 - 2662 0185 01 .uleb128 0x1 - 2663 0186 40 .uleb128 0x40 - 2664 0187 0A .uleb128 0xa - 2665 0188 9742 .uleb128 0x2117 - 2666 018a 0C .uleb128 0xc - 2667 018b 00 .byte 0 - 2668 018c 00 .byte 0 - 2669 018d 1A .uleb128 0x1a - 2670 018e 34 .uleb128 0x34 - 2671 018f 00 .byte 0 - 2672 0190 03 .uleb128 0x3 - 2673 0191 0E .uleb128 0xe - 2674 0192 3A .uleb128 0x3a - 2675 0193 0B .uleb128 0xb - 2676 0194 3B .uleb128 0x3b - 2677 0195 05 .uleb128 0x5 - 2678 0196 49 .uleb128 0x49 - 2679 0197 13 .uleb128 0x13 - 2680 0198 02 .uleb128 0x2 - 2681 0199 06 .uleb128 0x6 - 2682 019a 00 .byte 0 - 2683 019b 00 .byte 0 - 2684 019c 1B .uleb128 0x1b - 2685 019d 34 .uleb128 0x34 - 2686 019e 00 .byte 0 - 2687 019f 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 73 - - - 2688 01a0 08 .uleb128 0x8 - 2689 01a1 3A .uleb128 0x3a - 2690 01a2 0B .uleb128 0xb - 2691 01a3 3B .uleb128 0x3b - 2692 01a4 05 .uleb128 0x5 - 2693 01a5 49 .uleb128 0x49 - 2694 01a6 13 .uleb128 0x13 - 2695 01a7 00 .byte 0 - 2696 01a8 00 .byte 0 - 2697 01a9 1C .uleb128 0x1c - 2698 01aa 26 .uleb128 0x26 - 2699 01ab 00 .byte 0 - 2700 01ac 49 .uleb128 0x49 - 2701 01ad 13 .uleb128 0x13 - 2702 01ae 00 .byte 0 - 2703 01af 00 .byte 0 - 2704 01b0 1D .uleb128 0x1d - 2705 01b1 2E .uleb128 0x2e - 2706 01b2 01 .byte 0x1 - 2707 01b3 3F .uleb128 0x3f - 2708 01b4 0C .uleb128 0xc - 2709 01b5 03 .uleb128 0x3 - 2710 01b6 0E .uleb128 0xe - 2711 01b7 3A .uleb128 0x3a - 2712 01b8 0B .uleb128 0xb - 2713 01b9 3B .uleb128 0x3b - 2714 01ba 05 .uleb128 0x5 - 2715 01bb 27 .uleb128 0x27 - 2716 01bc 0C .uleb128 0xc - 2717 01bd 49 .uleb128 0x49 - 2718 01be 13 .uleb128 0x13 - 2719 01bf 11 .uleb128 0x11 - 2720 01c0 01 .uleb128 0x1 - 2721 01c1 12 .uleb128 0x12 - 2722 01c2 01 .uleb128 0x1 - 2723 01c3 40 .uleb128 0x40 - 2724 01c4 06 .uleb128 0x6 - 2725 01c5 9742 .uleb128 0x2117 - 2726 01c7 0C .uleb128 0xc - 2727 01c8 01 .uleb128 0x1 - 2728 01c9 13 .uleb128 0x13 - 2729 01ca 00 .byte 0 - 2730 01cb 00 .byte 0 - 2731 01cc 1E .uleb128 0x1e - 2732 01cd 05 .uleb128 0x5 - 2733 01ce 00 .byte 0 - 2734 01cf 03 .uleb128 0x3 - 2735 01d0 0E .uleb128 0xe - 2736 01d1 3A .uleb128 0x3a - 2737 01d2 0B .uleb128 0xb - 2738 01d3 3B .uleb128 0x3b - 2739 01d4 05 .uleb128 0x5 - 2740 01d5 49 .uleb128 0x49 - 2741 01d6 13 .uleb128 0x13 - 2742 01d7 02 .uleb128 0x2 - 2743 01d8 0A .uleb128 0xa - 2744 01d9 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 74 - - - 2745 01da 00 .byte 0 - 2746 01db 1F .uleb128 0x1f - 2747 01dc 34 .uleb128 0x34 - 2748 01dd 00 .byte 0 - 2749 01de 03 .uleb128 0x3 - 2750 01df 0E .uleb128 0xe - 2751 01e0 3A .uleb128 0x3a - 2752 01e1 0B .uleb128 0xb - 2753 01e2 3B .uleb128 0x3b - 2754 01e3 0B .uleb128 0xb - 2755 01e4 49 .uleb128 0x49 - 2756 01e5 13 .uleb128 0x13 - 2757 01e6 3F .uleb128 0x3f - 2758 01e7 0C .uleb128 0xc - 2759 01e8 02 .uleb128 0x2 - 2760 01e9 0A .uleb128 0xa - 2761 01ea 00 .byte 0 - 2762 01eb 00 .byte 0 - 2763 01ec 20 .uleb128 0x20 - 2764 01ed 34 .uleb128 0x34 - 2765 01ee 00 .byte 0 - 2766 01ef 03 .uleb128 0x3 - 2767 01f0 0E .uleb128 0xe - 2768 01f1 3A .uleb128 0x3a - 2769 01f2 0B .uleb128 0xb - 2770 01f3 3B .uleb128 0x3b - 2771 01f4 05 .uleb128 0x5 - 2772 01f5 49 .uleb128 0x49 - 2773 01f6 13 .uleb128 0x13 - 2774 01f7 3F .uleb128 0x3f - 2775 01f8 0C .uleb128 0xc - 2776 01f9 3C .uleb128 0x3c - 2777 01fa 0C .uleb128 0xc - 2778 01fb 00 .byte 0 - 2779 01fc 00 .byte 0 - 2780 01fd 21 .uleb128 0x21 - 2781 01fe 01 .uleb128 0x1 - 2782 01ff 01 .byte 0x1 - 2783 0200 49 .uleb128 0x49 - 2784 0201 13 .uleb128 0x13 - 2785 0202 01 .uleb128 0x1 - 2786 0203 13 .uleb128 0x13 - 2787 0204 00 .byte 0 - 2788 0205 00 .byte 0 - 2789 0206 22 .uleb128 0x22 - 2790 0207 21 .uleb128 0x21 - 2791 0208 00 .byte 0 - 2792 0209 49 .uleb128 0x49 - 2793 020a 13 .uleb128 0x13 - 2794 020b 2F .uleb128 0x2f - 2795 020c 0B .uleb128 0xb - 2796 020d 00 .byte 0 - 2797 020e 00 .byte 0 - 2798 020f 23 .uleb128 0x23 - 2799 0210 34 .uleb128 0x34 - 2800 0211 00 .byte 0 - 2801 0212 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 75 - - - 2802 0213 0E .uleb128 0xe - 2803 0214 3A .uleb128 0x3a - 2804 0215 0B .uleb128 0xb - 2805 0216 3B .uleb128 0x3b - 2806 0217 0B .uleb128 0xb - 2807 0218 49 .uleb128 0x49 - 2808 0219 13 .uleb128 0x13 - 2809 021a 3F .uleb128 0x3f - 2810 021b 0C .uleb128 0xc - 2811 021c 3C .uleb128 0x3c - 2812 021d 0C .uleb128 0xc - 2813 021e 00 .byte 0 - 2814 021f 00 .byte 0 - 2815 0220 24 .uleb128 0x24 - 2816 0221 2E .uleb128 0x2e - 2817 0222 00 .byte 0 - 2818 0223 3F .uleb128 0x3f - 2819 0224 0C .uleb128 0xc - 2820 0225 03 .uleb128 0x3 - 2821 0226 0E .uleb128 0xe - 2822 0227 3A .uleb128 0x3a - 2823 0228 0B .uleb128 0xb - 2824 0229 3B .uleb128 0x3b - 2825 022a 0B .uleb128 0xb - 2826 022b 27 .uleb128 0x27 - 2827 022c 0C .uleb128 0xc - 2828 022d 49 .uleb128 0x49 - 2829 022e 13 .uleb128 0x13 - 2830 022f 3C .uleb128 0x3c - 2831 0230 0C .uleb128 0xc - 2832 0231 00 .byte 0 - 2833 0232 00 .byte 0 - 2834 0233 25 .uleb128 0x25 - 2835 0234 2E .uleb128 0x2e - 2836 0235 01 .byte 0x1 - 2837 0236 3F .uleb128 0x3f - 2838 0237 0C .uleb128 0xc - 2839 0238 03 .uleb128 0x3 - 2840 0239 0E .uleb128 0xe - 2841 023a 3A .uleb128 0x3a - 2842 023b 0B .uleb128 0xb - 2843 023c 3B .uleb128 0x3b - 2844 023d 0B .uleb128 0xb - 2845 023e 27 .uleb128 0x27 - 2846 023f 0C .uleb128 0xc - 2847 0240 3C .uleb128 0x3c - 2848 0241 0C .uleb128 0xc - 2849 0242 01 .uleb128 0x1 - 2850 0243 13 .uleb128 0x13 - 2851 0244 00 .byte 0 - 2852 0245 00 .byte 0 - 2853 0246 26 .uleb128 0x26 - 2854 0247 05 .uleb128 0x5 - 2855 0248 00 .byte 0 - 2856 0249 49 .uleb128 0x49 - 2857 024a 13 .uleb128 0x13 - 2858 024b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 76 - - - 2859 024c 00 .byte 0 - 2860 024d 27 .uleb128 0x27 - 2861 024e 2E .uleb128 0x2e - 2862 024f 01 .byte 0x1 - 2863 0250 3F .uleb128 0x3f - 2864 0251 0C .uleb128 0xc - 2865 0252 03 .uleb128 0x3 - 2866 0253 0E .uleb128 0xe - 2867 0254 3A .uleb128 0x3a - 2868 0255 0B .uleb128 0xb - 2869 0256 3B .uleb128 0x3b - 2870 0257 0B .uleb128 0xb - 2871 0258 27 .uleb128 0x27 - 2872 0259 0C .uleb128 0xc - 2873 025a 49 .uleb128 0x49 - 2874 025b 13 .uleb128 0x13 - 2875 025c 3C .uleb128 0x3c - 2876 025d 0C .uleb128 0xc - 2877 025e 01 .uleb128 0x1 - 2878 025f 13 .uleb128 0x13 - 2879 0260 00 .byte 0 - 2880 0261 00 .byte 0 - 2881 0262 28 .uleb128 0x28 - 2882 0263 2E .uleb128 0x2e - 2883 0264 01 .byte 0x1 - 2884 0265 3F .uleb128 0x3f - 2885 0266 0C .uleb128 0xc - 2886 0267 03 .uleb128 0x3 - 2887 0268 0E .uleb128 0xe - 2888 0269 3A .uleb128 0x3a - 2889 026a 0B .uleb128 0xb - 2890 026b 3B .uleb128 0x3b - 2891 026c 0B .uleb128 0xb - 2892 026d 27 .uleb128 0x27 - 2893 026e 0C .uleb128 0xc - 2894 026f 3C .uleb128 0x3c - 2895 0270 0C .uleb128 0xc - 2896 0271 00 .byte 0 - 2897 0272 00 .byte 0 - 2898 0273 00 .byte 0 - 2899 .section .debug_loc,"",%progbits - 2900 .Ldebug_loc0: - 2901 .LLST0: - 2902 0000 00000000 .4byte .LFB1 - 2903 0004 02000000 .4byte .LCFI0 - 2904 0008 0200 .2byte 0x2 - 2905 000a 7D .byte 0x7d - 2906 000b 00 .sleb128 0 - 2907 000c 02000000 .4byte .LCFI0 - 2908 0010 14010000 .4byte .LFE1 - 2909 0014 0200 .2byte 0x2 - 2910 0016 7D .byte 0x7d - 2911 0017 18 .sleb128 24 - 2912 0018 00000000 .4byte 0 - 2913 001c 00000000 .4byte 0 - 2914 .LLST1: - 2915 0020 0A000000 .4byte .LVL1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 77 - - - 2916 0024 12000000 .4byte .LVL2 - 2917 0028 0100 .2byte 0x1 - 2918 002a 50 .byte 0x50 - 2919 002b 12000000 .4byte .LVL2 - 2920 002f 14010000 .4byte .LFE1 - 2921 0033 0100 .2byte 0x1 - 2922 0035 57 .byte 0x57 - 2923 0036 00000000 .4byte 0 - 2924 003a 00000000 .4byte 0 - 2925 .LLST2: - 2926 003e 00000000 .4byte .LFB2 - 2927 0042 06000000 .4byte .LCFI1 - 2928 0046 0200 .2byte 0x2 - 2929 0048 7D .byte 0x7d - 2930 0049 00 .sleb128 0 - 2931 004a 06000000 .4byte .LCFI1 - 2932 004e 98000000 .4byte .LFE2 - 2933 0052 0200 .2byte 0x2 - 2934 0054 7D .byte 0x7d - 2935 0055 08 .sleb128 8 - 2936 0056 00000000 .4byte 0 - 2937 005a 00000000 .4byte 0 - 2938 .LLST3: - 2939 005e 00000000 .4byte .LVL18 - 2940 0062 34000000 .4byte .LVL21 - 2941 0066 0100 .2byte 0x1 - 2942 0068 50 .byte 0x50 - 2943 0069 34000000 .4byte .LVL21 - 2944 006d 36000000 .4byte .LVL22 - 2945 0071 0200 .2byte 0x2 - 2946 0073 71 .byte 0x71 - 2947 0074 00 .sleb128 0 - 2948 0075 59000000 .4byte .LVL23-1 - 2949 0079 98000000 .4byte .LFE2 - 2950 007d 0400 .2byte 0x4 - 2951 007f F3 .byte 0xf3 - 2952 0080 01 .uleb128 0x1 - 2953 0081 50 .byte 0x50 - 2954 0082 9F .byte 0x9f - 2955 0083 00000000 .4byte 0 - 2956 0087 00000000 .4byte 0 - 2957 .LLST4: - 2958 008b 00000000 .4byte .LVL18 - 2959 008f 2A000000 .4byte .LVL20 - 2960 0093 0100 .2byte 0x1 - 2961 0095 51 .byte 0x51 - 2962 0096 2A000000 .4byte .LVL20 - 2963 009a 98000000 .4byte .LFE2 - 2964 009e 0400 .2byte 0x4 - 2965 00a0 F3 .byte 0xf3 - 2966 00a1 01 .uleb128 0x1 - 2967 00a2 51 .byte 0x51 - 2968 00a3 9F .byte 0x9f - 2969 00a4 00000000 .4byte 0 - 2970 00a8 00000000 .4byte 0 - 2971 .LLST5: - 2972 00ac 00000000 .4byte .LVL18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 78 - - - 2973 00b0 08000000 .4byte .LVL19 - 2974 00b4 0200 .2byte 0x2 - 2975 00b6 30 .byte 0x30 - 2976 00b7 9F .byte 0x9f - 2977 00b8 08000000 .4byte .LVL19 - 2978 00bc 98000000 .4byte .LFE2 - 2979 00c0 0200 .2byte 0x2 - 2980 00c2 31 .byte 0x31 - 2981 00c3 9F .byte 0x9f - 2982 00c4 00000000 .4byte 0 - 2983 00c8 00000000 .4byte 0 - 2984 .LLST6: - 2985 00cc 00000000 .4byte .LFB0 - 2986 00d0 02000000 .4byte .LCFI2 - 2987 00d4 0200 .2byte 0x2 - 2988 00d6 7D .byte 0x7d - 2989 00d7 00 .sleb128 0 - 2990 00d8 02000000 .4byte .LCFI2 - 2991 00dc 24000000 .4byte .LFE0 - 2992 00e0 0200 .2byte 0x2 - 2993 00e2 7D .byte 0x7d - 2994 00e3 10 .sleb128 16 - 2995 00e4 00000000 .4byte 0 - 2996 00e8 00000000 .4byte 0 - 2997 .LLST7: - 2998 00ec 00000000 .4byte .LVL24 - 2999 00f0 0F000000 .4byte .LVL25-1 - 3000 00f4 0100 .2byte 0x1 - 3001 00f6 50 .byte 0x50 - 3002 00f7 0F000000 .4byte .LVL25-1 - 3003 00fb 24000000 .4byte .LFE0 - 3004 00ff 0400 .2byte 0x4 - 3005 0101 F3 .byte 0xf3 - 3006 0102 01 .uleb128 0x1 - 3007 0103 50 .byte 0x50 - 3008 0104 9F .byte 0x9f - 3009 0105 00000000 .4byte 0 - 3010 0109 00000000 .4byte 0 - 3011 .LLST8: - 3012 010d 00000000 .4byte .LVL24 - 3013 0111 0F000000 .4byte .LVL25-1 - 3014 0115 0100 .2byte 0x1 - 3015 0117 51 .byte 0x51 - 3016 0118 0F000000 .4byte .LVL25-1 - 3017 011c 24000000 .4byte .LFE0 - 3018 0120 0400 .2byte 0x4 - 3019 0122 F3 .byte 0xf3 - 3020 0123 01 .uleb128 0x1 - 3021 0124 51 .byte 0x51 - 3022 0125 9F .byte 0x9f - 3023 0126 00000000 .4byte 0 - 3024 012a 00000000 .4byte 0 - 3025 .LLST9: - 3026 012e 00000000 .4byte .LVL27 - 3027 0132 08000000 .4byte .LVL28 - 3028 0136 0200 .2byte 0x2 - 3029 0138 30 .byte 0x30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 79 - - - 3030 0139 9F .byte 0x9f - 3031 013a 08000000 .4byte .LVL28 - 3032 013e 58000000 .4byte .LFE3 - 3033 0142 0200 .2byte 0x2 - 3034 0144 31 .byte 0x31 - 3035 0145 9F .byte 0x9f - 3036 0146 00000000 .4byte 0 - 3037 014a 00000000 .4byte 0 - 3038 .LLST10: - 3039 014e 04000000 .4byte .LVL29 - 3040 0152 0E000000 .4byte .LVL30 - 3041 0156 0100 .2byte 0x1 - 3042 0158 50 .byte 0x50 - 3043 0159 00000000 .4byte 0 - 3044 015d 00000000 .4byte 0 - 3045 .LLST11: - 3046 0161 00000000 .4byte .LVL31 - 3047 0165 0A000000 .4byte .LVL32 - 3048 0169 0200 .2byte 0x2 - 3049 016b 30 .byte 0x30 - 3050 016c 9F .byte 0x9f - 3051 016d 0A000000 .4byte .LVL32 - 3052 0171 14000000 .4byte .LFE7 - 3053 0175 0100 .2byte 0x1 - 3054 0177 50 .byte 0x50 - 3055 0178 00000000 .4byte 0 - 3056 017c 00000000 .4byte 0 - 3057 .LLST12: - 3058 0180 00000000 .4byte .LVL34 - 3059 0184 04000000 .4byte .LVL35 - 3060 0188 0100 .2byte 0x1 - 3061 018a 50 .byte 0x50 - 3062 018b 04000000 .4byte .LVL35 - 3063 018f 0C000000 .4byte .LFE8 - 3064 0193 0400 .2byte 0x4 - 3065 0195 F3 .byte 0xf3 - 3066 0196 01 .uleb128 0x1 - 3067 0197 50 .byte 0x50 - 3068 0198 9F .byte 0x9f - 3069 0199 00000000 .4byte 0 - 3070 019d 00000000 .4byte 0 - 3071 .LLST13: - 3072 01a1 00000000 .4byte .LVL36 - 3073 01a5 08000000 .4byte .LVL37 - 3074 01a9 0100 .2byte 0x1 - 3075 01ab 50 .byte 0x50 - 3076 01ac 08000000 .4byte .LVL37 - 3077 01b0 10000000 .4byte .LFE9 - 3078 01b4 0400 .2byte 0x4 - 3079 01b6 F3 .byte 0xf3 - 3080 01b7 01 .uleb128 0x1 - 3081 01b8 50 .byte 0x50 - 3082 01b9 9F .byte 0x9f - 3083 01ba 00000000 .4byte 0 - 3084 01be 00000000 .4byte 0 - 3085 .LLST14: - 3086 01c2 00000000 .4byte .LVL38 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 80 - - - 3087 01c6 02000000 .4byte .LVL39 - 3088 01ca 0100 .2byte 0x1 - 3089 01cc 50 .byte 0x50 - 3090 01cd 02000000 .4byte .LVL39 - 3091 01d1 2C000000 .4byte .LFE10 - 3092 01d5 0400 .2byte 0x4 - 3093 01d7 F3 .byte 0xf3 - 3094 01d8 01 .uleb128 0x1 - 3095 01d9 50 .byte 0x50 - 3096 01da 9F .byte 0x9f - 3097 01db 00000000 .4byte 0 - 3098 01df 00000000 .4byte 0 - 3099 .LLST15: - 3100 01e3 08000000 .4byte .LVL40 - 3101 01e7 0E000000 .4byte .LVL41 - 3102 01eb 0500 .2byte 0x5 - 3103 01ed 73 .byte 0x73 - 3104 01ee 00 .sleb128 0 - 3105 01ef 34 .byte 0x34 - 3106 01f0 24 .byte 0x24 - 3107 01f1 9F .byte 0x9f - 3108 01f2 0E000000 .4byte .LVL41 - 3109 01f6 10000000 .4byte .LVL42 - 3110 01fa 0500 .2byte 0x5 - 3111 01fc 70 .byte 0x70 - 3112 01fd 00 .sleb128 0 - 3113 01fe 34 .byte 0x34 - 3114 01ff 24 .byte 0x24 - 3115 0200 9F .byte 0x9f - 3116 0201 00000000 .4byte 0 - 3117 0205 00000000 .4byte 0 - 3118 .LLST16: - 3119 0209 00000000 .4byte .LVL38 - 3120 020d 10000000 .4byte .LVL42 - 3121 0211 0200 .2byte 0x2 - 3122 0213 30 .byte 0x30 - 3123 0214 9F .byte 0x9f - 3124 0215 10000000 .4byte .LVL42 - 3125 0219 1C000000 .4byte .LVL43 - 3126 021d 0800 .2byte 0x8 - 3127 021f 70 .byte 0x70 - 3128 0220 00 .sleb128 0 - 3129 0221 3F .byte 0x3f - 3130 0222 1A .byte 0x1a - 3131 0223 08 .byte 0x8 - 3132 0224 FF .byte 0xff - 3133 0225 1A .byte 0x1a - 3134 0226 9F .byte 0x9f - 3135 0227 1C000000 .4byte .LVL43 - 3136 022b 20000000 .4byte .LVL44 - 3137 022f 0100 .2byte 0x1 - 3138 0231 50 .byte 0x50 - 3139 0232 20000000 .4byte .LVL44 - 3140 0236 22000000 .4byte .LVL45 - 3141 023a 0100 .2byte 0x1 - 3142 023c 51 .byte 0x51 - 3143 023d 22000000 .4byte .LVL45 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 81 - - - 3144 0241 24000000 .4byte .LVL46 - 3145 0245 0200 .2byte 0x2 - 3146 0247 30 .byte 0x30 - 3147 0248 9F .byte 0x9f - 3148 0249 24000000 .4byte .LVL46 - 3149 024d 2C000000 .4byte .LFE10 - 3150 0251 0100 .2byte 0x1 - 3151 0253 50 .byte 0x50 - 3152 0254 00000000 .4byte 0 - 3153 0258 00000000 .4byte 0 - 3154 .LLST17: - 3155 025c 00000000 .4byte .LFB11 - 3156 0260 08000000 .4byte .LCFI3 - 3157 0264 0200 .2byte 0x2 - 3158 0266 7D .byte 0x7d - 3159 0267 00 .sleb128 0 - 3160 0268 08000000 .4byte .LCFI3 - 3161 026c 7C000000 .4byte .LFE11 - 3162 0270 0200 .2byte 0x2 - 3163 0272 7D .byte 0x7d - 3164 0273 14 .sleb128 20 - 3165 0274 00000000 .4byte 0 - 3166 0278 00000000 .4byte 0 - 3167 .LLST18: - 3168 027c 00000000 .4byte .LVL47 - 3169 0280 4E000000 .4byte .LVL55 - 3170 0284 0100 .2byte 0x1 - 3171 0286 50 .byte 0x50 - 3172 0287 4E000000 .4byte .LVL55 - 3173 028b 5A000000 .4byte .LVL56 - 3174 028f 0400 .2byte 0x4 - 3175 0291 F3 .byte 0xf3 - 3176 0292 01 .uleb128 0x1 - 3177 0293 50 .byte 0x50 - 3178 0294 9F .byte 0x9f - 3179 0295 5A000000 .4byte .LVL56 - 3180 0299 7C000000 .4byte .LFE11 - 3181 029d 0100 .2byte 0x1 - 3182 029f 50 .byte 0x50 - 3183 02a0 00000000 .4byte 0 - 3184 02a4 00000000 .4byte 0 - 3185 .LLST19: - 3186 02a8 00000000 .4byte .LVL47 - 3187 02ac 4A000000 .4byte .LVL54 - 3188 02b0 0100 .2byte 0x1 - 3189 02b2 51 .byte 0x51 - 3190 02b3 4A000000 .4byte .LVL54 - 3191 02b7 5A000000 .4byte .LVL56 - 3192 02bb 0400 .2byte 0x4 - 3193 02bd F3 .byte 0xf3 - 3194 02be 01 .uleb128 0x1 - 3195 02bf 51 .byte 0x51 - 3196 02c0 9F .byte 0x9f - 3197 02c1 5A000000 .4byte .LVL56 - 3198 02c5 7C000000 .4byte .LFE11 - 3199 02c9 0100 .2byte 0x1 - 3200 02cb 51 .byte 0x51 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 82 - - - 3201 02cc 00000000 .4byte 0 - 3202 02d0 00000000 .4byte 0 - 3203 .LLST20: - 3204 02d4 00000000 .4byte .LVL47 - 3205 02d8 28000000 .4byte .LVL51 - 3206 02dc 0100 .2byte 0x1 - 3207 02de 52 .byte 0x52 - 3208 02df 28000000 .4byte .LVL51 - 3209 02e3 2E000000 .4byte .LVL52 - 3210 02e7 0400 .2byte 0x4 - 3211 02e9 F3 .byte 0xf3 - 3212 02ea 01 .uleb128 0x1 - 3213 02eb 52 .byte 0x52 - 3214 02ec 9F .byte 0x9f - 3215 02ed 2E000000 .4byte .LVL52 - 3216 02f1 48000000 .4byte .LVL53 - 3217 02f5 0100 .2byte 0x1 - 3218 02f7 52 .byte 0x52 - 3219 02f8 5A000000 .4byte .LVL56 - 3220 02fc 7C000000 .4byte .LFE11 - 3221 0300 0100 .2byte 0x1 - 3222 0302 52 .byte 0x52 - 3223 0303 00000000 .4byte 0 - 3224 0307 00000000 .4byte 0 - 3225 .LLST21: - 3226 030b 0A000000 .4byte .LVL48 - 3227 030f 12000000 .4byte .LVL49 - 3228 0313 0500 .2byte 0x5 - 3229 0315 73 .byte 0x73 - 3230 0316 00 .sleb128 0 - 3231 0317 34 .byte 0x34 - 3232 0318 24 .byte 0x24 - 3233 0319 9F .byte 0x9f - 3234 031a 12000000 .4byte .LVL49 - 3235 031e 4E000000 .4byte .LVL55 - 3236 0322 0500 .2byte 0x5 - 3237 0324 70 .byte 0x70 - 3238 0325 7F .sleb128 -1 - 3239 0326 34 .byte 0x34 - 3240 0327 24 .byte 0x24 - 3241 0328 9F .byte 0x9f - 3242 0329 5A000000 .4byte .LVL56 - 3243 032d 6A000000 .4byte .LVL57 - 3244 0331 0500 .2byte 0x5 - 3245 0333 70 .byte 0x70 - 3246 0334 7F .sleb128 -1 - 3247 0335 34 .byte 0x34 - 3248 0336 24 .byte 0x24 - 3249 0337 9F .byte 0x9f - 3250 0338 00000000 .4byte 0 - 3251 033c 00000000 .4byte 0 - 3252 .LLST22: - 3253 0340 24000000 .4byte .LVL50 - 3254 0344 6A000000 .4byte .LVL57 - 3255 0348 0100 .2byte 0x1 - 3256 034a 55 .byte 0x55 - 3257 034b 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 83 - - - 3258 034f 00000000 .4byte 0 - 3259 .LLST23: - 3260 0353 00000000 .4byte .LVL58 - 3261 0357 10000000 .4byte .LVL60 - 3262 035b 0100 .2byte 0x1 - 3263 035d 50 .byte 0x50 - 3264 035e 10000000 .4byte .LVL60 - 3265 0362 28000000 .4byte .LFE13 - 3266 0366 0400 .2byte 0x4 - 3267 0368 F3 .byte 0xf3 - 3268 0369 01 .uleb128 0x1 - 3269 036a 50 .byte 0x50 - 3270 036b 9F .byte 0x9f - 3271 036c 00000000 .4byte 0 - 3272 0370 00000000 .4byte 0 - 3273 .LLST24: - 3274 0374 08000000 .4byte .LVL59 - 3275 0378 16000000 .4byte .LVL61 - 3276 037c 0500 .2byte 0x5 - 3277 037e 73 .byte 0x73 - 3278 037f 00 .sleb128 0 - 3279 0380 34 .byte 0x34 - 3280 0381 24 .byte 0x24 - 3281 0382 9F .byte 0x9f - 3282 0383 00000000 .4byte 0 - 3283 0387 00000000 .4byte 0 - 3284 .LLST25: - 3285 038b 00000000 .4byte .LFB12 - 3286 038f 02000000 .4byte .LCFI4 - 3287 0393 0200 .2byte 0x2 - 3288 0395 7D .byte 0x7d - 3289 0396 00 .sleb128 0 - 3290 0397 02000000 .4byte .LCFI4 - 3291 039b 4C000000 .4byte .LFE12 - 3292 039f 0200 .2byte 0x2 - 3293 03a1 7D .byte 0x7d - 3294 03a2 18 .sleb128 24 - 3295 03a3 00000000 .4byte 0 - 3296 03a7 00000000 .4byte 0 - 3297 .LLST26: - 3298 03ab 00000000 .4byte .LVL62 - 3299 03af 1D000000 .4byte .LVL67-1 - 3300 03b3 0100 .2byte 0x1 - 3301 03b5 50 .byte 0x50 - 3302 03b6 1D000000 .4byte .LVL67-1 - 3303 03ba 3E000000 .4byte .LVL72 - 3304 03be 0400 .2byte 0x4 - 3305 03c0 F3 .byte 0xf3 - 3306 03c1 01 .uleb128 0x1 - 3307 03c2 50 .byte 0x50 - 3308 03c3 9F .byte 0x9f - 3309 03c4 3E000000 .4byte .LVL72 - 3310 03c8 44000000 .4byte .LVL73 - 3311 03cc 0100 .2byte 0x1 - 3312 03ce 50 .byte 0x50 - 3313 03cf 44000000 .4byte .LVL73 - 3314 03d3 4C000000 .4byte .LFE12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 84 - - - 3315 03d7 0400 .2byte 0x4 - 3316 03d9 F3 .byte 0xf3 - 3317 03da 01 .uleb128 0x1 - 3318 03db 50 .byte 0x50 - 3319 03dc 9F .byte 0x9f - 3320 03dd 00000000 .4byte 0 - 3321 03e1 00000000 .4byte 0 - 3322 .LLST27: - 3323 03e5 00000000 .4byte .LVL62 - 3324 03e9 08000000 .4byte .LVL63 - 3325 03ed 0100 .2byte 0x1 - 3326 03ef 51 .byte 0x51 - 3327 03f0 08000000 .4byte .LVL63 - 3328 03f4 4C000000 .4byte .LFE12 - 3329 03f8 0100 .2byte 0x1 - 3330 03fa 55 .byte 0x55 - 3331 03fb 00000000 .4byte 0 - 3332 03ff 00000000 .4byte 0 - 3333 .LLST28: - 3334 0403 00000000 .4byte .LVL62 - 3335 0407 14000000 .4byte .LVL65 - 3336 040b 0100 .2byte 0x1 - 3337 040d 52 .byte 0x52 - 3338 040e 14000000 .4byte .LVL65 - 3339 0412 26000000 .4byte .LVL69 - 3340 0416 0400 .2byte 0x4 - 3341 0418 F3 .byte 0xf3 - 3342 0419 01 .uleb128 0x1 - 3343 041a 52 .byte 0x52 - 3344 041b 9F .byte 0x9f - 3345 041c 26000000 .4byte .LVL69 - 3346 0420 28000000 .4byte .LVL70 - 3347 0424 0100 .2byte 0x1 - 3348 0426 50 .byte 0x50 - 3349 0427 28000000 .4byte .LVL70 - 3350 042b 3E000000 .4byte .LVL72 - 3351 042f 0100 .2byte 0x1 - 3352 0431 54 .byte 0x54 - 3353 0432 3E000000 .4byte .LVL72 - 3354 0436 44000000 .4byte .LVL73 - 3355 043a 0100 .2byte 0x1 - 3356 043c 52 .byte 0x52 - 3357 043d 44000000 .4byte .LVL73 - 3358 0441 4C000000 .4byte .LFE12 - 3359 0445 0100 .2byte 0x1 - 3360 0447 54 .byte 0x54 - 3361 0448 00000000 .4byte 0 - 3362 044c 00000000 .4byte 0 - 3363 .LLST29: - 3364 0450 12000000 .4byte .LVL64 - 3365 0454 1D000000 .4byte .LVL67-1 - 3366 0458 0500 .2byte 0x5 - 3367 045a 71 .byte 0x71 - 3368 045b 00 .sleb128 0 - 3369 045c 34 .byte 0x34 - 3370 045d 24 .byte 0x24 - 3371 045e 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 85 - - - 3372 045f 1D000000 .4byte .LVL67-1 - 3373 0463 3E000000 .4byte .LVL72 - 3374 0467 0500 .2byte 0x5 - 3375 0469 77 .byte 0x77 - 3376 046a 7F .sleb128 -1 - 3377 046b 34 .byte 0x34 - 3378 046c 24 .byte 0x24 - 3379 046d 9F .byte 0x9f - 3380 046e 00000000 .4byte 0 - 3381 0472 00000000 .4byte 0 - 3382 .LLST30: - 3383 0476 1A000000 .4byte .LVL66 - 3384 047a 3E000000 .4byte .LVL72 - 3385 047e 0100 .2byte 0x1 - 3386 0480 56 .byte 0x56 - 3387 0481 00000000 .4byte 0 - 3388 0485 00000000 .4byte 0 - 3389 .LLST31: - 3390 0489 26000000 .4byte .LVL69 - 3391 048d 28000000 .4byte .LVL70 - 3392 0491 0200 .2byte 0x2 - 3393 0493 30 .byte 0x30 - 3394 0494 9F .byte 0x9f - 3395 0495 00000000 .4byte 0 - 3396 0499 00000000 .4byte 0 - 3397 .LLST32: - 3398 049d 1E000000 .4byte .LVL67 - 3399 04a1 24000000 .4byte .LVL68 - 3400 04a5 0100 .2byte 0x1 - 3401 04a7 50 .byte 0x50 - 3402 04a8 00000000 .4byte 0 - 3403 04ac 00000000 .4byte 0 - 3404 .LLST33: - 3405 04b0 00000000 .4byte .LVL74 - 3406 04b4 02000000 .4byte .LVL75 - 3407 04b8 0100 .2byte 0x1 - 3408 04ba 50 .byte 0x50 - 3409 04bb 02000000 .4byte .LVL75 - 3410 04bf 18000000 .4byte .LFE14 - 3411 04c3 0400 .2byte 0x4 - 3412 04c5 F3 .byte 0xf3 - 3413 04c6 01 .uleb128 0x1 - 3414 04c7 50 .byte 0x50 - 3415 04c8 9F .byte 0x9f - 3416 04c9 00000000 .4byte 0 - 3417 04cd 00000000 .4byte 0 - 3418 .LLST34: - 3419 04d1 08000000 .4byte .LVL76 - 3420 04d5 10000000 .4byte .LVL77 - 3421 04d9 0500 .2byte 0x5 - 3422 04db 71 .byte 0x71 - 3423 04dc 00 .sleb128 0 - 3424 04dd 34 .byte 0x34 - 3425 04de 24 .byte 0x24 - 3426 04df 9F .byte 0x9f - 3427 04e0 00000000 .4byte 0 - 3428 04e4 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 86 - - - 3429 .LLST35: - 3430 04e8 00000000 .4byte .LVL79 - 3431 04ec 02000000 .4byte .LVL80 - 3432 04f0 0100 .2byte 0x1 - 3433 04f2 50 .byte 0x50 - 3434 04f3 02000000 .4byte .LVL80 - 3435 04f7 20000000 .4byte .LFE16 - 3436 04fb 0400 .2byte 0x4 - 3437 04fd F3 .byte 0xf3 - 3438 04fe 01 .uleb128 0x1 - 3439 04ff 50 .byte 0x50 - 3440 0500 9F .byte 0x9f - 3441 0501 00000000 .4byte 0 - 3442 0505 00000000 .4byte 0 - 3443 .LLST36: - 3444 0509 08000000 .4byte .LVL81 - 3445 050d 10000000 .4byte .LVL82 - 3446 0511 0500 .2byte 0x5 - 3447 0513 71 .byte 0x71 - 3448 0514 00 .sleb128 0 - 3449 0515 34 .byte 0x34 - 3450 0516 24 .byte 0x24 - 3451 0517 9F .byte 0x9f - 3452 0518 00000000 .4byte 0 - 3453 051c 00000000 .4byte 0 - 3454 .LLST37: - 3455 0520 00000000 .4byte .LVL79 - 3456 0524 16000000 .4byte .LVL83 - 3457 0528 0200 .2byte 0x2 - 3458 052a 30 .byte 0x30 - 3459 052b 9F .byte 0x9f - 3460 052c 16000000 .4byte .LVL83 - 3461 0530 18000000 .4byte .LVL84 - 3462 0534 0100 .2byte 0x1 - 3463 0536 52 .byte 0x52 - 3464 0537 18000000 .4byte .LVL84 - 3465 053b 1A000000 .4byte .LVL85 - 3466 053f 0200 .2byte 0x2 - 3467 0541 30 .byte 0x30 - 3468 0542 9F .byte 0x9f - 3469 0543 1A000000 .4byte .LVL85 - 3470 0547 20000000 .4byte .LFE16 - 3471 054b 0100 .2byte 0x1 - 3472 054d 50 .byte 0x50 - 3473 054e 00000000 .4byte 0 - 3474 0552 00000000 .4byte 0 - 3475 .LLST38: - 3476 0556 00000000 .4byte .LVL86 - 3477 055a 0A000000 .4byte .LVL87 - 3478 055e 0100 .2byte 0x1 - 3479 0560 50 .byte 0x50 - 3480 0561 0A000000 .4byte .LVL87 - 3481 0565 0C000000 .4byte .LVL88 - 3482 0569 0400 .2byte 0x4 - 3483 056b F3 .byte 0xf3 - 3484 056c 01 .uleb128 0x1 - 3485 056d 50 .byte 0x50 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 87 - - - 3486 056e 9F .byte 0x9f - 3487 056f 0C000000 .4byte .LVL88 - 3488 0573 10000000 .4byte .LVL89 - 3489 0577 0100 .2byte 0x1 - 3490 0579 50 .byte 0x50 - 3491 057a 10000000 .4byte .LVL89 - 3492 057e 18000000 .4byte .LFE17 - 3493 0582 0400 .2byte 0x4 - 3494 0584 F3 .byte 0xf3 - 3495 0585 01 .uleb128 0x1 - 3496 0586 50 .byte 0x50 - 3497 0587 9F .byte 0x9f - 3498 0588 00000000 .4byte 0 - 3499 058c 00000000 .4byte 0 - 3500 .LLST39: - 3501 0590 00000000 .4byte .LVL90 - 3502 0594 04000000 .4byte .LVL91 - 3503 0598 0200 .2byte 0x2 - 3504 059a 30 .byte 0x30 - 3505 059b 9F .byte 0x9f - 3506 059c 04000000 .4byte .LVL91 - 3507 05a0 08000000 .4byte .LVL92 - 3508 05a4 0900 .2byte 0x9 - 3509 05a6 70 .byte 0x70 - 3510 05a7 00 .sleb128 0 - 3511 05a8 32 .byte 0x32 - 3512 05a9 1A .byte 0x1a - 3513 05aa 48 .byte 0x48 - 3514 05ab 24 .byte 0x24 - 3515 05ac 30 .byte 0x30 - 3516 05ad 2E .byte 0x2e - 3517 05ae 9F .byte 0x9f - 3518 05af 00000000 .4byte 0 - 3519 05b3 00000000 .4byte 0 - 3520 .section .debug_aranges,"",%progbits - 3521 0000 AC000000 .4byte 0xac - 3522 0004 0200 .2byte 0x2 - 3523 0006 00000000 .4byte .Ldebug_info0 - 3524 000a 04 .byte 0x4 - 3525 000b 00 .byte 0 - 3526 000c 0000 .2byte 0 - 3527 000e 0000 .2byte 0 - 3528 0010 00000000 .4byte .LFB1 - 3529 0014 14010000 .4byte .LFE1-.LFB1 - 3530 0018 00000000 .4byte .LFB2 - 3531 001c 98000000 .4byte .LFE2-.LFB2 - 3532 0020 00000000 .4byte .LFB0 - 3533 0024 24000000 .4byte .LFE0-.LFB0 - 3534 0028 00000000 .4byte .LFB3 - 3535 002c 58000000 .4byte .LFE3-.LFB3 - 3536 0030 00000000 .4byte .LFB4 - 3537 0034 7C000000 .4byte .LFE4-.LFB4 - 3538 0038 00000000 .4byte .LFB5 - 3539 003c 14000000 .4byte .LFE5-.LFB5 - 3540 0040 00000000 .4byte .LFB6 - 3541 0044 0C000000 .4byte .LFE6-.LFB6 - 3542 0048 00000000 .4byte .LFB7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 88 - - - 3543 004c 14000000 .4byte .LFE7-.LFB7 - 3544 0050 00000000 .4byte .LFB8 - 3545 0054 0C000000 .4byte .LFE8-.LFB8 - 3546 0058 00000000 .4byte .LFB9 - 3547 005c 10000000 .4byte .LFE9-.LFB9 - 3548 0060 00000000 .4byte .LFB10 - 3549 0064 2C000000 .4byte .LFE10-.LFB10 - 3550 0068 00000000 .4byte .LFB11 - 3551 006c 7C000000 .4byte .LFE11-.LFB11 - 3552 0070 00000000 .4byte .LFB13 - 3553 0074 28000000 .4byte .LFE13-.LFB13 - 3554 0078 00000000 .4byte .LFB12 - 3555 007c 4C000000 .4byte .LFE12-.LFB12 - 3556 0080 00000000 .4byte .LFB14 - 3557 0084 18000000 .4byte .LFE14-.LFB14 - 3558 0088 00000000 .4byte .LFB15 - 3559 008c 0C000000 .4byte .LFE15-.LFB15 - 3560 0090 00000000 .4byte .LFB16 - 3561 0094 20000000 .4byte .LFE16-.LFB16 - 3562 0098 00000000 .4byte .LFB17 - 3563 009c 18000000 .4byte .LFE17-.LFB17 - 3564 00a0 00000000 .4byte .LFB18 - 3565 00a4 10000000 .4byte .LFE18-.LFB18 - 3566 00a8 00000000 .4byte 0 - 3567 00ac 00000000 .4byte 0 - 3568 .section .debug_ranges,"",%progbits - 3569 .Ldebug_ranges0: - 3570 0000 00000000 .4byte .LFB1 - 3571 0004 14010000 .4byte .LFE1 - 3572 0008 00000000 .4byte .LFB2 - 3573 000c 98000000 .4byte .LFE2 - 3574 0010 00000000 .4byte .LFB0 - 3575 0014 24000000 .4byte .LFE0 - 3576 0018 00000000 .4byte .LFB3 - 3577 001c 58000000 .4byte .LFE3 - 3578 0020 00000000 .4byte .LFB4 - 3579 0024 7C000000 .4byte .LFE4 - 3580 0028 00000000 .4byte .LFB5 - 3581 002c 14000000 .4byte .LFE5 - 3582 0030 00000000 .4byte .LFB6 - 3583 0034 0C000000 .4byte .LFE6 - 3584 0038 00000000 .4byte .LFB7 - 3585 003c 14000000 .4byte .LFE7 - 3586 0040 00000000 .4byte .LFB8 - 3587 0044 0C000000 .4byte .LFE8 - 3588 0048 00000000 .4byte .LFB9 - 3589 004c 10000000 .4byte .LFE9 - 3590 0050 00000000 .4byte .LFB10 - 3591 0054 2C000000 .4byte .LFE10 - 3592 0058 00000000 .4byte .LFB11 - 3593 005c 7C000000 .4byte .LFE11 - 3594 0060 00000000 .4byte .LFB13 - 3595 0064 28000000 .4byte .LFE13 - 3596 0068 00000000 .4byte .LFB12 - 3597 006c 4C000000 .4byte .LFE12 - 3598 0070 00000000 .4byte .LFB14 - 3599 0074 18000000 .4byte .LFE14 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 89 - - - 3600 0078 00000000 .4byte .LFB15 - 3601 007c 0C000000 .4byte .LFE15 - 3602 0080 00000000 .4byte .LFB16 - 3603 0084 20000000 .4byte .LFE16 - 3604 0088 00000000 .4byte .LFB17 - 3605 008c 18000000 .4byte .LFE17 - 3606 0090 00000000 .4byte .LFB18 - 3607 0094 10000000 .4byte .LFE18 - 3608 0098 00000000 .4byte 0 - 3609 009c 00000000 .4byte 0 - 3610 .section .debug_line,"",%progbits - 3611 .Ldebug_line0: - 3612 0000 C8020000 .section .debug_str,"MS",%progbits,1 - 3612 02006900 - 3612 00000201 - 3612 FB0E0D00 - 3612 01010101 - 3613 .LASF10: - 3614 0000 75696E74 .ascii "uint16\000" - 3614 313600 - 3615 .LASF70: - 3616 0007 43794578 .ascii "CyExitCriticalSection\000" - 3616 69744372 - 3616 69746963 - 3616 616C5365 - 3616 6374696F - 3617 .LASF57: - 3618 001d 55534246 .ascii "USBFS_initVar\000" - 3618 535F696E - 3618 69745661 - 3618 7200 - 3619 .LASF63: - 3620 002b 55534246 .ascii "USBFS_hidProtocol\000" - 3620 535F6869 - 3620 6450726F - 3620 746F636F - 3620 6C00 - 3621 .LASF51: - 3622 003d 55534246 .ascii "USBFS_Force\000" - 3622 535F466F - 3622 72636500 - 3623 .LASF7: - 3624 0049 6C6F6E67 .ascii "long long unsigned int\000" - 3624 206C6F6E - 3624 6720756E - 3624 7369676E - 3624 65642069 - 3625 .LASF53: - 3626 0060 55534246 .ascii "USBFS_GetEPAckState\000" - 3626 535F4765 - 3626 74455041 - 3626 636B5374 - 3626 61746500 - 3627 .LASF23: - 3628 0074 61646472 .ascii "addr\000" - 3628 00 - 3629 .LASF39: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 90 - - - 3630 0079 696E7465 .ascii "interfaceNumber\000" - 3630 72666163 - 3630 654E756D - 3630 62657200 - 3631 .LASF41: - 3632 0089 65704E75 .ascii "epNumber\000" - 3632 6D626572 - 3632 00 - 3633 .LASF31: - 3634 0092 64657669 .ascii "device\000" - 3634 636500 - 3635 .LASF6: - 3636 0099 6C6F6E67 .ascii "long long int\000" - 3636 206C6F6E - 3636 6720696E - 3636 7400 - 3637 .LASF0: - 3638 00a7 7369676E .ascii "signed char\000" - 3638 65642063 - 3638 68617200 - 3639 .LASF73: - 3640 00b3 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS.c\000" - 3640 6E657261 - 3640 7465645F - 3640 536F7572 - 3640 63655C50 - 3641 .LASF37: - 3642 00d4 55534246 .ascii "USBFS_IsConfigurationChanged\000" - 3642 535F4973 - 3642 436F6E66 - 3642 69677572 - 3642 6174696F - 3643 .LASF66: - 3644 00f1 55534246 .ascii "USBFS_deviceAddress\000" - 3644 535F6465 - 3644 76696365 - 3644 41646472 - 3644 65737300 - 3645 .LASF64: - 3646 0105 55534246 .ascii "USBFS_interfaceNumber\000" - 3646 535F696E - 3646 74657266 - 3646 6163654E - 3646 756D6265 - 3647 .LASF56: - 3648 011b 55534246 .ascii "USBFS_RWUEnabled\000" - 3648 535F5257 - 3648 55456E61 - 3648 626C6564 - 3648 00 - 3649 .LASF54: - 3650 012c 55534246 .ascii "USBFS_SetPowerStatus\000" - 3650 535F5365 - 3650 74506F77 - 3650 65725374 - 3650 61747573 - 3651 .LASF75: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 91 - - - 3652 0141 55534246 .ascii "USBFS_Stop\000" - 3652 535F5374 - 3652 6F7000 - 3653 .LASF4: - 3654 014c 6C6F6E67 .ascii "long int\000" - 3654 20696E74 - 3654 00 - 3655 .LASF76: - 3656 0155 55534246 .ascii "USBFS_GetConfiguration\000" - 3656 535F4765 - 3656 74436F6E - 3656 66696775 - 3656 72617469 - 3657 .LASF9: - 3658 016c 75696E74 .ascii "uint8\000" - 3658 3800 - 3659 .LASF22: - 3660 0172 6570546F .ascii "epToggle\000" - 3660 67676C65 - 3660 00 - 3661 .LASF69: - 3662 017b 43794465 .ascii "CyDelayUs\000" - 3662 6C617955 - 3662 7300 - 3663 .LASF13: - 3664 0185 646F7562 .ascii "double\000" - 3664 6C6500 - 3665 .LASF55: - 3666 018c 706F7765 .ascii "powerStatus\000" - 3666 72537461 - 3666 74757300 - 3667 .LASF11: - 3668 0198 75696E74 .ascii "uint32\000" - 3668 333200 - 3669 .LASF30: - 3670 019f 55534246 .ascii "USBFS_InitComponent\000" - 3670 535F496E - 3670 6974436F - 3670 6D706F6E - 3670 656E7400 - 3671 .LASF45: - 3672 01b3 70446174 .ascii "pData\000" - 3672 6100 - 3673 .LASF60: - 3674 01b9 55534246 .ascii "USBFS_configuration\000" - 3674 535F636F - 3674 6E666967 - 3674 75726174 - 3674 696F6E00 - 3675 .LASF24: - 3676 01cd 65704D6F .ascii "epMode\000" - 3676 646500 - 3677 .LASF48: - 3678 01d4 55534246 .ascii "USBFS_ReadOutEP\000" - 3678 535F5265 - 3678 61644F75 - 3678 74455000 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 92 - - - 3679 .LASF8: - 3680 01e4 756E7369 .ascii "unsigned int\000" - 3680 676E6564 - 3680 20696E74 - 3680 00 - 3681 .LASF5: - 3682 01f1 6C6F6E67 .ascii "long unsigned int\000" - 3682 20756E73 - 3682 69676E65 - 3682 6420696E - 3682 7400 - 3683 .LASF77: - 3684 0203 4379456E .ascii "CyEnterCriticalSection\000" - 3684 74657243 - 3684 72697469 - 3684 63616C53 - 3684 65637469 - 3685 .LASF3: - 3686 021a 73686F72 .ascii "short unsigned int\000" - 3686 7420756E - 3686 7369676E - 3686 65642069 - 3686 6E7400 - 3687 .LASF78: - 3688 022d 4379496E .ascii "CyIntSetVector\000" - 3688 74536574 - 3688 56656374 - 3688 6F7200 - 3689 .LASF27: - 3690 023c 696E7465 .ascii "interface\000" - 3690 72666163 - 3690 6500 - 3691 .LASF61: - 3692 0246 55534246 .ascii "USBFS_configurationChanged\000" - 3692 535F636F - 3692 6E666967 - 3692 75726174 - 3692 696F6E43 - 3693 .LASF74: - 3694 0261 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 3694 43534932 - 3694 53445C73 - 3694 6F667477 - 3694 6172655C - 3695 0290 6E00 .ascii "n\000" - 3696 .LASF16: - 3697 0292 72656733 .ascii "reg32\000" - 3697 3200 - 3698 .LASF21: - 3699 0298 68774570 .ascii "hwEpState\000" - 3699 53746174 - 3699 6500 - 3700 .LASF18: - 3701 02a2 73697A65 .ascii "sizetype\000" - 3701 74797065 - 3701 00 - 3702 .LASF19: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 93 - - - 3703 02ab 61747472 .ascii "attrib\000" - 3703 696200 - 3704 .LASF71: - 3705 02b2 4379496E .ascii "CyIntSetPriority\000" - 3705 74536574 - 3705 5072696F - 3705 72697479 - 3705 00 - 3706 .LASF29: - 3707 02c3 55534246 .ascii "USBFS_Init\000" - 3707 535F496E - 3707 697400 - 3708 .LASF12: - 3709 02ce 666C6F61 .ascii "float\000" - 3709 7400 - 3710 .LASF20: - 3711 02d4 61706945 .ascii "apiEpState\000" - 3711 70537461 - 3711 746500 - 3712 .LASF67: - 3713 02df 55534246 .ascii "USBFS_EP\000" - 3713 535F4550 - 3713 00 - 3714 .LASF79: - 3715 02e8 43794465 .ascii "CyDelayCycles\000" - 3715 6C617943 - 3715 79636C65 - 3715 7300 - 3716 .LASF72: - 3717 02f6 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 3717 4320342E - 3717 372E3320 - 3717 32303133 - 3717 30333132 - 3718 0329 616E6368 .ascii "anch revision 196615]\000" - 3718 20726576 - 3718 6973696F - 3718 6E203139 - 3718 36363135 - 3719 .LASF15: - 3720 033f 72656738 .ascii "reg8\000" - 3720 00 - 3721 .LASF59: - 3722 0344 55534246 .ascii "USBFS_transferState\000" - 3722 535F7472 - 3722 616E7366 - 3722 65725374 - 3722 61746500 - 3723 .LASF1: - 3724 0358 756E7369 .ascii "unsigned char\000" - 3724 676E6564 - 3724 20636861 - 3724 7200 - 3725 .LASF2: - 3726 0366 73686F72 .ascii "short int\000" - 3726 7420696E - 3726 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 94 - - - 3727 .LASF47: - 3728 0370 55534246 .ascii "USBFS_EnableOutEP\000" - 3728 535F456E - 3728 61626C65 - 3728 4F757445 - 3728 5000 - 3729 .LASF68: - 3730 0382 55534246 .ascii "USBFS_lastPacketSize\000" - 3730 535F6C61 - 3730 73745061 - 3730 636B6574 - 3730 53697A65 - 3731 .LASF65: - 3732 0397 55534246 .ascii "USBFS_interfaceSetting\000" - 3732 535F696E - 3732 74657266 - 3732 61636553 - 3732 65747469 - 3733 .LASF28: - 3734 03ae 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 3734 4246535F - 3734 45505F43 - 3734 544C5F42 - 3734 4C4F434B - 3735 .LASF58: - 3736 03c3 55534246 .ascii "USBFS_device\000" - 3736 535F6465 - 3736 76696365 - 3736 00 - 3737 .LASF52: - 3738 03d0 62537461 .ascii "bState\000" - 3738 746500 - 3739 .LASF46: - 3740 03d7 6C656E67 .ascii "length\000" - 3740 746800 - 3741 .LASF14: - 3742 03de 63686172 .ascii "char\000" - 3742 00 - 3743 .LASF32: - 3744 03e3 6D6F6465 .ascii "mode\000" - 3744 00 - 3745 .LASF17: - 3746 03e8 63796973 .ascii "cyisraddress\000" - 3746 72616464 - 3746 72657373 - 3746 00 - 3747 .LASF26: - 3748 03f5 62756666 .ascii "bufferSize\000" - 3748 65725369 - 3748 7A6500 - 3749 .LASF34: - 3750 0400 55534246 .ascii "USBFS_Start\000" - 3750 535F5374 - 3750 61727400 - 3751 .LASF25: - 3752 040c 62756666 .ascii "buffOffset\000" - 3752 4F666673 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 95 - - - 3752 657400 - 3753 .LASF62: - 3754 0417 55534246 .ascii "USBFS_deviceStatus\000" - 3754 535F6465 - 3754 76696365 - 3754 53746174 - 3754 757300 - 3755 .LASF40: - 3756 042a 55534246 .ascii "USBFS_GetEPState\000" - 3756 535F4765 - 3756 74455053 - 3756 74617465 - 3756 00 - 3757 .LASF35: - 3758 043b 55534246 .ascii "USBFS_ReInitComponent\000" - 3758 535F5265 - 3758 496E6974 - 3758 436F6D70 - 3758 6F6E656E - 3759 .LASF33: - 3760 0451 656E6162 .ascii "enableInterrupts\000" - 3760 6C65496E - 3760 74657272 - 3760 75707473 - 3760 00 - 3761 .LASF36: - 3762 0462 55534246 .ascii "USBFS_CheckActivity\000" - 3762 535F4368 - 3762 65636B41 - 3762 63746976 - 3762 69747900 - 3763 .LASF49: - 3764 0476 78666572 .ascii "xferCount\000" - 3764 436F756E - 3764 7400 - 3765 .LASF50: - 3766 0480 55534246 .ascii "USBFS_DisableOutEP\000" - 3766 535F4469 - 3766 7361626C - 3766 654F7574 - 3766 455000 - 3767 .LASF44: - 3768 0493 55534246 .ascii "USBFS_LoadInEP\000" - 3768 535F4C6F - 3768 6164496E - 3768 455000 - 3769 .LASF38: - 3770 04a2 55534246 .ascii "USBFS_GetInterfaceSetting\000" - 3770 535F4765 - 3770 74496E74 - 3770 65726661 - 3770 63655365 - 3771 .LASF42: - 3772 04bc 55534246 .ascii "USBFS_GetEPCount\000" - 3772 535F4765 - 3772 74455043 - 3772 6F756E74 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccd5i1O6.s page 96 - - - 3772 00 - 3773 .LASF43: - 3774 04cd 72657375 .ascii "result\000" - 3774 6C7400 - 3775 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS.o deleted file mode 100755 index 753aea9bcbeed1db93101dc6000b4012ac250f1d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 18388 zcmd5^eRx&HnV&i5hJ0N@NC+e$gp&^-3WNlrQbouI34{a)1eDq+BF*_CvO-aqWk#i`8~(Tf5fQ-Qw0~%hui1_F?;8Uo-gED{ zhwyCw*gtl7&i&2%&Trm%=bbq-=g!IHme$TTt+n!!Ry8UmDfLj5DamLsP@~qWi`3bt z-v8Yn-(TC2*;YECmo!gnRU9ihWG!u))}gY*nvOM{i(>ZKdq)b-etd;BeT%Zsemtxk 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--git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst deleted file mode 100755 index df9af69..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.lst +++ /dev/null @@ -1,776 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "USBFS_Dm.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.USBFS_Dm_Write,"ax",%progbits - 19 .align 1 - 20 .global USBFS_Dm_Write - 21 .thumb - 22 .thumb_func - 23 .type USBFS_Dm_Write, %function - 24 USBFS_Dm_Write: - 25 .LFB0: - 26 .file 1 ".\\Generated_Source\\PSoC5\\USBFS_Dm.c" - 1:.\Generated_Source\PSoC5/USBFS_Dm.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/USBFS_Dm.c **** * File Name: USBFS_Dm.c - 3:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Version 1.90 - 4:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 5:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Description: - 6:.\Generated_Source\PSoC5/USBFS_Dm.c **** * This file contains API to enable firmware control of a Pins component. - 7:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 8:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Note: - 9:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 10:.\Generated_Source\PSoC5/USBFS_Dm.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/USBFS_Dm.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/USBFS_Dm.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/USBFS_Dm.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/USBFS_Dm.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 17:.\Generated_Source\PSoC5/USBFS_Dm.c **** #include "cytypes.h" - 18:.\Generated_Source\PSoC5/USBFS_Dm.c **** #include "USBFS_Dm.h" - 19:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 20:.\Generated_Source\PSoC5/USBFS_Dm.c **** /* APIs are not generated for P15[7:6] on PSoC 5 */ - 21:.\Generated_Source\PSoC5/USBFS_Dm.c **** #if !(CY_PSOC5A &&\ - 22:.\Generated_Source\PSoC5/USBFS_Dm.c **** USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) - 23:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 24:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 25:.\Generated_Source\PSoC5/USBFS_Dm.c **** /******************************************************************************* - 26:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Function Name: USBFS_Dm_Write - 27:.\Generated_Source\PSoC5/USBFS_Dm.c **** ******************************************************************************** - 28:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 29:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Summary: - 30:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Assign a new value to the digital port's data output register. - 31:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 2 - - - 32:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Parameters: - 33:.\Generated_Source\PSoC5/USBFS_Dm.c **** * prtValue: The value to be assigned to the Digital Port. - 34:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 35:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Return: - 36:.\Generated_Source\PSoC5/USBFS_Dm.c **** * None - 37:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 38:.\Generated_Source\PSoC5/USBFS_Dm.c **** *******************************************************************************/ - 39:.\Generated_Source\PSoC5/USBFS_Dm.c **** void USBFS_Dm_Write(uint8 value) - 40:.\Generated_Source\PSoC5/USBFS_Dm.c **** { - 27 .loc 1 40 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 32 .LVL0: - 41:.\Generated_Source\PSoC5/USBFS_Dm.c **** uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK)); - 33 .loc 1 41 0 - 34 0000 044B ldr r3, .L2 - 35 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 36 .LVL1: - 37 0004 02F07F01 and r1, r2, #127 - 42:.\Generated_Source\PSoC5/USBFS_Dm.c **** USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK); - 38 .loc 1 42 0 - 39 0008 41EAC010 orr r0, r1, r0, lsl #7 - 40 .LVL2: - 41 000c C2B2 uxtb r2, r0 - 42 .LVL3: - 43 000e 1A70 strb r2, [r3, #0] - 44 0010 7047 bx lr - 45 .L3: - 46 0012 00BF .align 2 - 47 .L2: - 48 0014 F0510040 .word 1073762800 - 49 .cfi_endproc - 50 .LFE0: - 51 .size USBFS_Dm_Write, .-USBFS_Dm_Write - 52 .section .text.USBFS_Dm_SetDriveMode,"ax",%progbits - 53 .align 1 - 54 .global USBFS_Dm_SetDriveMode - 55 .thumb - 56 .thumb_func - 57 .type USBFS_Dm_SetDriveMode, %function - 58 USBFS_Dm_SetDriveMode: - 59 .LFB1: - 43:.\Generated_Source\PSoC5/USBFS_Dm.c **** } - 44:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 45:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 46:.\Generated_Source\PSoC5/USBFS_Dm.c **** /******************************************************************************* - 47:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Function Name: USBFS_Dm_SetDriveMode - 48:.\Generated_Source\PSoC5/USBFS_Dm.c **** ******************************************************************************** - 49:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 50:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Summary: - 51:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Change the drive mode on the pins of the port. - 52:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 53:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Parameters: - 54:.\Generated_Source\PSoC5/USBFS_Dm.c **** * mode: Change the pins to this drive mode. - 55:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 3 - - - 56:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Return: - 57:.\Generated_Source\PSoC5/USBFS_Dm.c **** * None - 58:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 59:.\Generated_Source\PSoC5/USBFS_Dm.c **** *******************************************************************************/ - 60:.\Generated_Source\PSoC5/USBFS_Dm.c **** void USBFS_Dm_SetDriveMode(uint8 mode) - 61:.\Generated_Source\PSoC5/USBFS_Dm.c **** { - 60 .loc 1 61 0 - 61 .cfi_startproc - 62 @ args = 0, pretend = 0, frame = 0 - 63 @ frame_needed = 0, uses_anonymous_args = 0 - 64 @ link register save eliminated. - 65 .LVL4: - 62:.\Generated_Source\PSoC5/USBFS_Dm.c **** CyPins_SetPinDriveMode(USBFS_Dm_0, mode); - 66 .loc 1 62 0 - 67 0000 044B ldr r3, .L5 - 68 0002 00F00E00 and r0, r0, #14 - 69 .LVL5: - 70 0006 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 71 0008 22F00E01 bic r1, r2, #14 - 72 000c 40EA0102 orr r2, r0, r1 - 73 0010 1A70 strb r2, [r3, #0] - 74 0012 7047 bx lr - 75 .L6: - 76 .align 2 - 77 .L5: - 78 0014 7F500040 .word 1073762431 - 79 .cfi_endproc - 80 .LFE1: - 81 .size USBFS_Dm_SetDriveMode, .-USBFS_Dm_SetDriveMode - 82 .section .text.USBFS_Dm_Read,"ax",%progbits - 83 .align 1 - 84 .global USBFS_Dm_Read - 85 .thumb - 86 .thumb_func - 87 .type USBFS_Dm_Read, %function - 88 USBFS_Dm_Read: - 89 .LFB2: - 63:.\Generated_Source\PSoC5/USBFS_Dm.c **** } - 64:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 65:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 66:.\Generated_Source\PSoC5/USBFS_Dm.c **** /******************************************************************************* - 67:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Function Name: USBFS_Dm_Read - 68:.\Generated_Source\PSoC5/USBFS_Dm.c **** ******************************************************************************** - 69:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 70:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Summary: - 71:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Read the current value on the pins of the Digital Port in right justified - 72:.\Generated_Source\PSoC5/USBFS_Dm.c **** * form. - 73:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 74:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Parameters: - 75:.\Generated_Source\PSoC5/USBFS_Dm.c **** * None - 76:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 77:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Return: - 78:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Returns the current value of the Digital Port as a right justified number - 79:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 80:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Note: - 81:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Macro USBFS_Dm_ReadPS calls this function. - 82:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 4 - - - 83:.\Generated_Source\PSoC5/USBFS_Dm.c **** *******************************************************************************/ - 84:.\Generated_Source\PSoC5/USBFS_Dm.c **** uint8 USBFS_Dm_Read(void) - 85:.\Generated_Source\PSoC5/USBFS_Dm.c **** { - 90 .loc 1 85 0 - 91 .cfi_startproc - 92 @ args = 0, pretend = 0, frame = 0 - 93 @ frame_needed = 0, uses_anonymous_args = 0 - 94 @ link register save eliminated. - 86:.\Generated_Source\PSoC5/USBFS_Dm.c **** return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; - 95 .loc 1 86 0 - 96 0000 014B ldr r3, .L8 - 97 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 87:.\Generated_Source\PSoC5/USBFS_Dm.c **** } - 98 .loc 1 87 0 - 99 0004 C009 lsrs r0, r0, #7 - 100 0006 7047 bx lr - 101 .L9: - 102 .align 2 - 103 .L8: - 104 0008 F1510040 .word 1073762801 - 105 .cfi_endproc - 106 .LFE2: - 107 .size USBFS_Dm_Read, .-USBFS_Dm_Read - 108 .section .text.USBFS_Dm_ReadDataReg,"ax",%progbits - 109 .align 1 - 110 .global USBFS_Dm_ReadDataReg - 111 .thumb - 112 .thumb_func - 113 .type USBFS_Dm_ReadDataReg, %function - 114 USBFS_Dm_ReadDataReg: - 115 .LFB3: - 88:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 89:.\Generated_Source\PSoC5/USBFS_Dm.c **** - 90:.\Generated_Source\PSoC5/USBFS_Dm.c **** /******************************************************************************* - 91:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Function Name: USBFS_Dm_ReadDataReg - 92:.\Generated_Source\PSoC5/USBFS_Dm.c **** ******************************************************************************** - 93:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 94:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Summary: - 95:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Read the current value assigned to a Digital Port's data output register - 96:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 97:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Parameters: - 98:.\Generated_Source\PSoC5/USBFS_Dm.c **** * None - 99:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 100:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Return: - 101:.\Generated_Source\PSoC5/USBFS_Dm.c **** * Returns the current value assigned to the Digital Port's data output register - 102:.\Generated_Source\PSoC5/USBFS_Dm.c **** * - 103:.\Generated_Source\PSoC5/USBFS_Dm.c **** *******************************************************************************/ - 104:.\Generated_Source\PSoC5/USBFS_Dm.c **** uint8 USBFS_Dm_ReadDataReg(void) - 105:.\Generated_Source\PSoC5/USBFS_Dm.c **** { - 116 .loc 1 105 0 - 117 .cfi_startproc - 118 @ args = 0, pretend = 0, frame = 0 - 119 @ frame_needed = 0, uses_anonymous_args = 0 - 120 @ link register save eliminated. - 106:.\Generated_Source\PSoC5/USBFS_Dm.c **** return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; - 121 .loc 1 106 0 - 122 0000 014B ldr r3, .L11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 5 - - - 123 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 107:.\Generated_Source\PSoC5/USBFS_Dm.c **** } - 124 .loc 1 107 0 - 125 0004 C009 lsrs r0, r0, #7 - 126 0006 7047 bx lr - 127 .L12: - 128 .align 2 - 129 .L11: - 130 0008 F0510040 .word 1073762800 - 131 .cfi_endproc - 132 .LFE3: - 133 .size USBFS_Dm_ReadDataReg, .-USBFS_Dm_ReadDataReg - 134 .text - 135 .Letext0: - 136 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 137 .section .debug_info,"",%progbits - 138 .Ldebug_info0: - 139 0000 2F010000 .4byte 0x12f - 140 0004 0200 .2byte 0x2 - 141 0006 00000000 .4byte .Ldebug_abbrev0 - 142 000a 04 .byte 0x4 - 143 000b 01 .uleb128 0x1 - 144 000c 3F010000 .4byte .LASF20 - 145 0010 01 .byte 0x1 - 146 0011 BA000000 .4byte .LASF21 - 147 0015 76000000 .4byte .LASF22 - 148 0019 00000000 .4byte .Ldebug_ranges0+0 - 149 001d 00000000 .4byte 0 - 150 0021 00000000 .4byte 0 - 151 0025 00000000 .4byte .Ldebug_line0 - 152 0029 02 .uleb128 0x2 - 153 002a 01 .byte 0x1 - 154 002b 06 .byte 0x6 - 155 002c 91010000 .4byte .LASF0 - 156 0030 02 .uleb128 0x2 - 157 0031 01 .byte 0x1 - 158 0032 08 .byte 0x8 - 159 0033 51000000 .4byte .LASF1 - 160 0037 02 .uleb128 0x2 - 161 0038 02 .byte 0x2 - 162 0039 05 .byte 0x5 - 163 003a 2F010000 .4byte .LASF2 - 164 003e 02 .uleb128 0x2 - 165 003f 02 .byte 0x2 - 166 0040 07 .byte 0x7 - 167 0041 A7000000 .4byte .LASF3 - 168 0045 02 .uleb128 0x2 - 169 0046 04 .byte 0x4 - 170 0047 05 .byte 0x5 - 171 0048 88010000 .4byte .LASF4 - 172 004c 02 .uleb128 0x2 - 173 004d 04 .byte 0x4 - 174 004e 07 .byte 0x7 - 175 004f 64000000 .4byte .LASF5 - 176 0053 02 .uleb128 0x2 - 177 0054 08 .byte 0x8 - 178 0055 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 6 - - - 179 0056 1C010000 .4byte .LASF6 - 180 005a 02 .uleb128 0x2 - 181 005b 08 .byte 0x8 - 182 005c 07 .byte 0x7 - 183 005d 00010000 .4byte .LASF7 - 184 0061 03 .uleb128 0x3 - 185 0062 04 .byte 0x4 - 186 0063 05 .byte 0x5 - 187 0064 696E7400 .ascii "int\000" - 188 0068 02 .uleb128 0x2 - 189 0069 04 .byte 0x4 - 190 006a 07 .byte 0x7 - 191 006b F3000000 .4byte .LASF8 - 192 006f 04 .uleb128 0x4 - 193 0070 39010000 .4byte .LASF12 - 194 0074 02 .byte 0x2 - 195 0075 5B .byte 0x5b - 196 0076 30000000 .4byte 0x30 - 197 007a 02 .uleb128 0x2 - 198 007b 04 .byte 0x4 - 199 007c 04 .byte 0x4 - 200 007d 4B000000 .4byte .LASF9 - 201 0081 02 .uleb128 0x2 - 202 0082 08 .byte 0x8 - 203 0083 04 .byte 0x4 - 204 0084 2E000000 .4byte .LASF10 - 205 0088 02 .uleb128 0x2 - 206 0089 01 .byte 0x1 - 207 008a 08 .byte 0x8 - 208 008b 2A010000 .4byte .LASF11 - 209 008f 04 .uleb128 0x4 - 210 0090 5F000000 .4byte .LASF13 - 211 0094 02 .byte 0x2 - 212 0095 F0 .byte 0xf0 - 213 0096 9A000000 .4byte 0x9a - 214 009a 05 .uleb128 0x5 - 215 009b 6F000000 .4byte 0x6f - 216 009f 06 .uleb128 0x6 - 217 00a0 01 .byte 0x1 - 218 00a1 00000000 .4byte .LASF14 - 219 00a5 01 .byte 0x1 - 220 00a6 27 .byte 0x27 - 221 00a7 01 .byte 0x1 - 222 00a8 00000000 .4byte .LFB0 - 223 00ac 18000000 .4byte .LFE0 - 224 00b0 02 .byte 0x2 - 225 00b1 7D .byte 0x7d - 226 00b2 00 .sleb128 0 - 227 00b3 01 .byte 0x1 - 228 00b4 D7000000 .4byte 0xd7 - 229 00b8 07 .uleb128 0x7 - 230 00b9 1D000000 .4byte .LASF16 - 231 00bd 01 .byte 0x1 - 232 00be 27 .byte 0x27 - 233 00bf 6F000000 .4byte 0x6f - 234 00c3 00000000 .4byte .LLST0 - 235 00c7 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 7 - - - 236 00c8 23000000 .4byte .LASF23 - 237 00cc 01 .byte 0x1 - 238 00cd 29 .byte 0x29 - 239 00ce 6F000000 .4byte 0x6f - 240 00d2 21000000 .4byte .LLST1 - 241 00d6 00 .byte 0 - 242 00d7 06 .uleb128 0x6 - 243 00d8 01 .byte 0x1 - 244 00d9 35000000 .4byte .LASF15 - 245 00dd 01 .byte 0x1 - 246 00de 3C .byte 0x3c - 247 00df 01 .byte 0x1 - 248 00e0 00000000 .4byte .LFB1 - 249 00e4 18000000 .4byte .LFE1 - 250 00e8 02 .byte 0x2 - 251 00e9 7D .byte 0x7d - 252 00ea 00 .sleb128 0 - 253 00eb 01 .byte 0x1 - 254 00ec 00010000 .4byte 0x100 - 255 00f0 07 .uleb128 0x7 - 256 00f1 17010000 .4byte .LASF17 - 257 00f5 01 .byte 0x1 - 258 00f6 3C .byte 0x3c - 259 00f7 6F000000 .4byte 0x6f - 260 00fb 39000000 .4byte .LLST2 - 261 00ff 00 .byte 0 - 262 0100 09 .uleb128 0x9 - 263 0101 01 .byte 0x1 - 264 0102 0F000000 .4byte .LASF18 - 265 0106 01 .byte 0x1 - 266 0107 54 .byte 0x54 - 267 0108 01 .byte 0x1 - 268 0109 6F000000 .4byte 0x6f - 269 010d 00000000 .4byte .LFB2 - 270 0111 0C000000 .4byte .LFE2 - 271 0115 02 .byte 0x2 - 272 0116 7D .byte 0x7d - 273 0117 00 .sleb128 0 - 274 0118 01 .byte 0x1 - 275 0119 09 .uleb128 0x9 - 276 011a 01 .byte 0x1 - 277 011b DE000000 .4byte .LASF19 - 278 011f 01 .byte 0x1 - 279 0120 68 .byte 0x68 - 280 0121 01 .byte 0x1 - 281 0122 6F000000 .4byte 0x6f - 282 0126 00000000 .4byte .LFB3 - 283 012a 0C000000 .4byte .LFE3 - 284 012e 02 .byte 0x2 - 285 012f 7D .byte 0x7d - 286 0130 00 .sleb128 0 - 287 0131 01 .byte 0x1 - 288 0132 00 .byte 0 - 289 .section .debug_abbrev,"",%progbits - 290 .Ldebug_abbrev0: - 291 0000 01 .uleb128 0x1 - 292 0001 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 8 - - - 293 0002 01 .byte 0x1 - 294 0003 25 .uleb128 0x25 - 295 0004 0E .uleb128 0xe - 296 0005 13 .uleb128 0x13 - 297 0006 0B .uleb128 0xb - 298 0007 03 .uleb128 0x3 - 299 0008 0E .uleb128 0xe - 300 0009 1B .uleb128 0x1b - 301 000a 0E .uleb128 0xe - 302 000b 55 .uleb128 0x55 - 303 000c 06 .uleb128 0x6 - 304 000d 11 .uleb128 0x11 - 305 000e 01 .uleb128 0x1 - 306 000f 52 .uleb128 0x52 - 307 0010 01 .uleb128 0x1 - 308 0011 10 .uleb128 0x10 - 309 0012 06 .uleb128 0x6 - 310 0013 00 .byte 0 - 311 0014 00 .byte 0 - 312 0015 02 .uleb128 0x2 - 313 0016 24 .uleb128 0x24 - 314 0017 00 .byte 0 - 315 0018 0B .uleb128 0xb - 316 0019 0B .uleb128 0xb - 317 001a 3E .uleb128 0x3e - 318 001b 0B .uleb128 0xb - 319 001c 03 .uleb128 0x3 - 320 001d 0E .uleb128 0xe - 321 001e 00 .byte 0 - 322 001f 00 .byte 0 - 323 0020 03 .uleb128 0x3 - 324 0021 24 .uleb128 0x24 - 325 0022 00 .byte 0 - 326 0023 0B .uleb128 0xb - 327 0024 0B .uleb128 0xb - 328 0025 3E .uleb128 0x3e - 329 0026 0B .uleb128 0xb - 330 0027 03 .uleb128 0x3 - 331 0028 08 .uleb128 0x8 - 332 0029 00 .byte 0 - 333 002a 00 .byte 0 - 334 002b 04 .uleb128 0x4 - 335 002c 16 .uleb128 0x16 - 336 002d 00 .byte 0 - 337 002e 03 .uleb128 0x3 - 338 002f 0E .uleb128 0xe - 339 0030 3A .uleb128 0x3a - 340 0031 0B .uleb128 0xb - 341 0032 3B .uleb128 0x3b - 342 0033 0B .uleb128 0xb - 343 0034 49 .uleb128 0x49 - 344 0035 13 .uleb128 0x13 - 345 0036 00 .byte 0 - 346 0037 00 .byte 0 - 347 0038 05 .uleb128 0x5 - 348 0039 35 .uleb128 0x35 - 349 003a 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 9 - - - 350 003b 49 .uleb128 0x49 - 351 003c 13 .uleb128 0x13 - 352 003d 00 .byte 0 - 353 003e 00 .byte 0 - 354 003f 06 .uleb128 0x6 - 355 0040 2E .uleb128 0x2e - 356 0041 01 .byte 0x1 - 357 0042 3F .uleb128 0x3f - 358 0043 0C .uleb128 0xc - 359 0044 03 .uleb128 0x3 - 360 0045 0E .uleb128 0xe - 361 0046 3A .uleb128 0x3a - 362 0047 0B .uleb128 0xb - 363 0048 3B .uleb128 0x3b - 364 0049 0B .uleb128 0xb - 365 004a 27 .uleb128 0x27 - 366 004b 0C .uleb128 0xc - 367 004c 11 .uleb128 0x11 - 368 004d 01 .uleb128 0x1 - 369 004e 12 .uleb128 0x12 - 370 004f 01 .uleb128 0x1 - 371 0050 40 .uleb128 0x40 - 372 0051 0A .uleb128 0xa - 373 0052 9742 .uleb128 0x2117 - 374 0054 0C .uleb128 0xc - 375 0055 01 .uleb128 0x1 - 376 0056 13 .uleb128 0x13 - 377 0057 00 .byte 0 - 378 0058 00 .byte 0 - 379 0059 07 .uleb128 0x7 - 380 005a 05 .uleb128 0x5 - 381 005b 00 .byte 0 - 382 005c 03 .uleb128 0x3 - 383 005d 0E .uleb128 0xe - 384 005e 3A .uleb128 0x3a - 385 005f 0B .uleb128 0xb - 386 0060 3B .uleb128 0x3b - 387 0061 0B .uleb128 0xb - 388 0062 49 .uleb128 0x49 - 389 0063 13 .uleb128 0x13 - 390 0064 02 .uleb128 0x2 - 391 0065 06 .uleb128 0x6 - 392 0066 00 .byte 0 - 393 0067 00 .byte 0 - 394 0068 08 .uleb128 0x8 - 395 0069 34 .uleb128 0x34 - 396 006a 00 .byte 0 - 397 006b 03 .uleb128 0x3 - 398 006c 0E .uleb128 0xe - 399 006d 3A .uleb128 0x3a - 400 006e 0B .uleb128 0xb - 401 006f 3B .uleb128 0x3b - 402 0070 0B .uleb128 0xb - 403 0071 49 .uleb128 0x49 - 404 0072 13 .uleb128 0x13 - 405 0073 02 .uleb128 0x2 - 406 0074 06 .uleb128 0x6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 10 - - - 407 0075 00 .byte 0 - 408 0076 00 .byte 0 - 409 0077 09 .uleb128 0x9 - 410 0078 2E .uleb128 0x2e - 411 0079 00 .byte 0 - 412 007a 3F .uleb128 0x3f - 413 007b 0C .uleb128 0xc - 414 007c 03 .uleb128 0x3 - 415 007d 0E .uleb128 0xe - 416 007e 3A .uleb128 0x3a - 417 007f 0B .uleb128 0xb - 418 0080 3B .uleb128 0x3b - 419 0081 0B .uleb128 0xb - 420 0082 27 .uleb128 0x27 - 421 0083 0C .uleb128 0xc - 422 0084 49 .uleb128 0x49 - 423 0085 13 .uleb128 0x13 - 424 0086 11 .uleb128 0x11 - 425 0087 01 .uleb128 0x1 - 426 0088 12 .uleb128 0x12 - 427 0089 01 .uleb128 0x1 - 428 008a 40 .uleb128 0x40 - 429 008b 0A .uleb128 0xa - 430 008c 9742 .uleb128 0x2117 - 431 008e 0C .uleb128 0xc - 432 008f 00 .byte 0 - 433 0090 00 .byte 0 - 434 0091 00 .byte 0 - 435 .section .debug_loc,"",%progbits - 436 .Ldebug_loc0: - 437 .LLST0: - 438 0000 00000000 .4byte .LVL0 - 439 0004 0C000000 .4byte .LVL2 - 440 0008 0100 .2byte 0x1 - 441 000a 50 .byte 0x50 - 442 000b 0C000000 .4byte .LVL2 - 443 000f 18000000 .4byte .LFE0 - 444 0013 0400 .2byte 0x4 - 445 0015 F3 .byte 0xf3 - 446 0016 01 .uleb128 0x1 - 447 0017 50 .byte 0x50 - 448 0018 9F .byte 0x9f - 449 0019 00000000 .4byte 0 - 450 001d 00000000 .4byte 0 - 451 .LLST1: - 452 0021 04000000 .4byte .LVL1 - 453 0025 0E000000 .4byte .LVL3 - 454 0029 0600 .2byte 0x6 - 455 002b 72 .byte 0x72 - 456 002c 00 .sleb128 0 - 457 002d 08 .byte 0x8 - 458 002e 7F .byte 0x7f - 459 002f 1A .byte 0x1a - 460 0030 9F .byte 0x9f - 461 0031 00000000 .4byte 0 - 462 0035 00000000 .4byte 0 - 463 .LLST2: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 11 - - - 464 0039 00000000 .4byte .LVL4 - 465 003d 06000000 .4byte .LVL5 - 466 0041 0100 .2byte 0x1 - 467 0043 50 .byte 0x50 - 468 0044 06000000 .4byte .LVL5 - 469 0048 18000000 .4byte .LFE1 - 470 004c 0400 .2byte 0x4 - 471 004e F3 .byte 0xf3 - 472 004f 01 .uleb128 0x1 - 473 0050 50 .byte 0x50 - 474 0051 9F .byte 0x9f - 475 0052 00000000 .4byte 0 - 476 0056 00000000 .4byte 0 - 477 .section .debug_aranges,"",%progbits - 478 0000 34000000 .4byte 0x34 - 479 0004 0200 .2byte 0x2 - 480 0006 00000000 .4byte .Ldebug_info0 - 481 000a 04 .byte 0x4 - 482 000b 00 .byte 0 - 483 000c 0000 .2byte 0 - 484 000e 0000 .2byte 0 - 485 0010 00000000 .4byte .LFB0 - 486 0014 18000000 .4byte .LFE0-.LFB0 - 487 0018 00000000 .4byte .LFB1 - 488 001c 18000000 .4byte .LFE1-.LFB1 - 489 0020 00000000 .4byte .LFB2 - 490 0024 0C000000 .4byte .LFE2-.LFB2 - 491 0028 00000000 .4byte .LFB3 - 492 002c 0C000000 .4byte .LFE3-.LFB3 - 493 0030 00000000 .4byte 0 - 494 0034 00000000 .4byte 0 - 495 .section .debug_ranges,"",%progbits - 496 .Ldebug_ranges0: - 497 0000 00000000 .4byte .LFB0 - 498 0004 18000000 .4byte .LFE0 - 499 0008 00000000 .4byte .LFB1 - 500 000c 18000000 .4byte .LFE1 - 501 0010 00000000 .4byte .LFB2 - 502 0014 0C000000 .4byte .LFE2 - 503 0018 00000000 .4byte .LFB3 - 504 001c 0C000000 .4byte .LFE3 - 505 0020 00000000 .4byte 0 - 506 0024 00000000 .4byte 0 - 507 .section .debug_line,"",%progbits - 508 .Ldebug_line0: - 509 0000 92000000 .section .debug_str,"MS",%progbits,1 - 509 02004700 - 509 00000201 - 509 FB0E0D00 - 509 01010101 - 510 .LASF14: - 511 0000 55534246 .ascii "USBFS_Dm_Write\000" - 511 535F446D - 511 5F577269 - 511 746500 - 512 .LASF18: - 513 000f 55534246 .ascii "USBFS_Dm_Read\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 12 - - - 513 535F446D - 513 5F526561 - 513 6400 - 514 .LASF16: - 515 001d 76616C75 .ascii "value\000" - 515 6500 - 516 .LASF23: - 517 0023 73746174 .ascii "staticBits\000" - 517 69634269 - 517 747300 - 518 .LASF10: - 519 002e 646F7562 .ascii "double\000" - 519 6C6500 - 520 .LASF15: - 521 0035 55534246 .ascii "USBFS_Dm_SetDriveMode\000" - 521 535F446D - 521 5F536574 - 521 44726976 - 521 654D6F64 - 522 .LASF9: - 523 004b 666C6F61 .ascii "float\000" - 523 7400 - 524 .LASF1: - 525 0051 756E7369 .ascii "unsigned char\000" - 525 676E6564 - 525 20636861 - 525 7200 - 526 .LASF13: - 527 005f 72656738 .ascii "reg8\000" - 527 00 - 528 .LASF5: - 529 0064 6C6F6E67 .ascii "long unsigned int\000" - 529 20756E73 - 529 69676E65 - 529 6420696E - 529 7400 - 530 .LASF22: - 531 0076 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 531 43534932 - 531 53445C73 - 531 6F667477 - 531 6172655C - 532 00a5 6E00 .ascii "n\000" - 533 .LASF3: - 534 00a7 73686F72 .ascii "short unsigned int\000" - 534 7420756E - 534 7369676E - 534 65642069 - 534 6E7400 - 535 .LASF21: - 536 00ba 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_Dm.c\000" - 536 6E657261 - 536 7465645F - 536 536F7572 - 536 63655C50 - 537 .LASF19: - 538 00de 55534246 .ascii "USBFS_Dm_ReadDataReg\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccmaaXQv.s page 13 - - - 538 535F446D - 538 5F526561 - 538 64446174 - 538 61526567 - 539 .LASF8: - 540 00f3 756E7369 .ascii "unsigned int\000" - 540 676E6564 - 540 20696E74 - 540 00 - 541 .LASF7: - 542 0100 6C6F6E67 .ascii "long long unsigned int\000" - 542 206C6F6E - 542 6720756E - 542 7369676E - 542 65642069 - 543 .LASF17: - 544 0117 6D6F6465 .ascii "mode\000" - 544 00 - 545 .LASF6: - 546 011c 6C6F6E67 .ascii "long long int\000" - 546 206C6F6E - 546 6720696E - 546 7400 - 547 .LASF11: - 548 012a 63686172 .ascii "char\000" - 548 00 - 549 .LASF2: - 550 012f 73686F72 .ascii "short int\000" - 550 7420696E - 550 7400 - 551 .LASF12: - 552 0139 75696E74 .ascii "uint8\000" - 552 3800 - 553 .LASF20: - 554 013f 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 554 4320342E - 554 372E3320 - 554 32303133 - 554 30333132 - 555 0172 616E6368 .ascii "anch revision 196615]\000" - 555 20726576 - 555 6973696F - 555 6E203139 - 555 36363135 - 556 .LASF4: - 557 0188 6C6F6E67 .ascii "long int\000" - 557 20696E74 - 557 00 - 558 .LASF0: - 559 0191 7369676E .ascii "signed char\000" - 559 65642063 - 559 68617200 - 560 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dm.o deleted file mode 100755 index 0faf2149b36b0e88622eef82d857b28e3dec0563..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4132 zcmb_fTWl0n7(Qoax4WgK(w1vMvp|tzU?{X)MePj=0klw%L`s_3-D$hA-KjHEgaiT) zB%0_0_@IfG5T7*0XyO|tMxs9W;Db>TV`7XkJQyBK2~UOx{Jt~i?9MKrKKLgy-+%f3 z|J={)Uf6qRpOjJg6zL_ebHB+b{dzWD`_c* zAhS;(lp3c#|2E!fAFl@Z(5dwbmP5793;7c;^QiKZL&>hiOKzaKns$TSM#r9-Ja#9u z3@^Ed#9bsd%11~%CQYSgm~5m`{>s4AeE}g`<+_&kCc9;2%khR*c~mZHKuV`*YI+(@ zj99B#3}>mZTXr`+*>s>C1KK7C4UT-KIrgq^Zk27aZ^2sw%@UDJy27?lGTU2YHaeo3 zcc8tJiC$9JZz)CyoTrqyBS)@6QIf(NJrfNg5ZMbI6+eS$iHU^!6S?K|_J9@(Srmh8 zl43Bns_}o~y#cZ%hWVCvTNVl&11=fY$Qc{<%3k0`UU7WXp9>1!*vP0qh;=S{B(jf>P16A>9lv)FM48P+IJ%{R}M>)Wv`ek zOu2ywyvdzn+AmM$Dt;c36T8Po2S*QV9UU4A{fX#hH}EPB^k{s*_ajs*dVy0oTMWx0 zobrRHw#LIIZOjY_b7oXEoFO-Ik9w2U9B(*F-qO?Evt?_pEAXa0H}p2-PWB%?yxE({d&Qzx+|)b1V^cnG%Y~_2;GHgo zCBK~8vTOVHE!$4TZLw~0_Qdeu;O<-(8#(6t(_wDH4{|7(+pA0FMgqU!g`ppW8~%@8 z^l!zsay>U+60(asY!K7#o!NA_M>H(R9B#DQQj6shxy)WJSI7?eSZWP6A`inoh!obj zmga>uhl2+qd06Ug#*%TRJK@=x$ju8UjDi@ajE2rc!YN`Ug_93M;n3k!mO0+Ub`~g0*R~#&*Q}pt4ljEiGgpa0`?&kAYL6L|~`-PU|I0V*CM;toIFyqb!ADblNw-8=<1b?7udUlH<6U zn3tvCnsIPU=B%+qCl2V^L<2@8V#+FVk&6#U2VfN*)?0*!Z6@no#G*cEUx8L5rX4y{ z;`Y5{(5@LV>nD3cJJ}-bRLz-WMec>gm7->rVuvl#b^LT4ACsIA8@E{U%=1=beV)Hq z%qE77AltT<#pjl|MB6;e7L0X740WUS^SqI_TVub*{TiRs_`F7b3&?*_ zBM&d_^BON{d`;tJjqhvxkch4IvBqoK|1}Z+O}^Fk58D1&+rJU9*=}mQt^Ie2$m3nY zek>&7oVIFQsr`==@z;cZ{)iOzgQtS1jy90Hi1uoY>oo2nqWz~d4r$!4k-Oi*#lro? zeC`qQb3_#HB0iv9P!vzC8w`~XK6fAUR2}5;zG40`BI> USBFS_Dp_SHIFT; - 100 .loc 1 86 0 - 101 0000 024B ldr r3, .L8 - 102 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 87:.\Generated_Source\PSoC5/USBFS_Dp.c **** } - 103 .loc 1 87 0 - 104 0004 C0F38010 ubfx r0, r0, #6, #1 - 105 0008 7047 bx lr - 106 .L9: - 107 000a 00BF .align 2 - 108 .L8: - 109 000c F1510040 .word 1073762801 - 110 .cfi_endproc - 111 .LFE2: - 112 .size USBFS_Dp_Read, .-USBFS_Dp_Read - 113 .section .text.USBFS_Dp_ReadDataReg,"ax",%progbits - 114 .align 1 - 115 .global USBFS_Dp_ReadDataReg - 116 .thumb - 117 .thumb_func - 118 .type USBFS_Dp_ReadDataReg, %function - 119 USBFS_Dp_ReadDataReg: - 120 .LFB3: - 88:.\Generated_Source\PSoC5/USBFS_Dp.c **** - 89:.\Generated_Source\PSoC5/USBFS_Dp.c **** - 90:.\Generated_Source\PSoC5/USBFS_Dp.c **** /******************************************************************************* - 91:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Function Name: USBFS_Dp_ReadDataReg - 92:.\Generated_Source\PSoC5/USBFS_Dp.c **** ******************************************************************************** - 93:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - 94:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Summary: - 95:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Read the current value assigned to a Digital Port's data output register - 96:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - 97:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Parameters: - 98:.\Generated_Source\PSoC5/USBFS_Dp.c **** * None - 99:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - 100:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Return: - 101:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Returns the current value assigned to the Digital Port's data output register - 102:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - 103:.\Generated_Source\PSoC5/USBFS_Dp.c **** *******************************************************************************/ - 104:.\Generated_Source\PSoC5/USBFS_Dp.c **** uint8 USBFS_Dp_ReadDataReg(void) - 105:.\Generated_Source\PSoC5/USBFS_Dp.c **** { - 121 .loc 1 105 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 5 - - - 122 .cfi_startproc - 123 @ args = 0, pretend = 0, frame = 0 - 124 @ frame_needed = 0, uses_anonymous_args = 0 - 125 @ link register save eliminated. - 106:.\Generated_Source\PSoC5/USBFS_Dp.c **** return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; - 126 .loc 1 106 0 - 127 0000 024B ldr r3, .L11 - 128 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 107:.\Generated_Source\PSoC5/USBFS_Dp.c **** } - 129 .loc 1 107 0 - 130 0004 C0F38010 ubfx r0, r0, #6, #1 - 131 0008 7047 bx lr - 132 .L12: - 133 000a 00BF .align 2 - 134 .L11: - 135 000c F0510040 .word 1073762800 - 136 .cfi_endproc - 137 .LFE3: - 138 .size USBFS_Dp_ReadDataReg, .-USBFS_Dp_ReadDataReg - 139 .section .text.USBFS_Dp_ClearInterrupt,"ax",%progbits - 140 .align 1 - 141 .global USBFS_Dp_ClearInterrupt - 142 .thumb - 143 .thumb_func - 144 .type USBFS_Dp_ClearInterrupt, %function - 145 USBFS_Dp_ClearInterrupt: - 146 .LFB4: - 108:.\Generated_Source\PSoC5/USBFS_Dp.c **** - 109:.\Generated_Source\PSoC5/USBFS_Dp.c **** - 110:.\Generated_Source\PSoC5/USBFS_Dp.c **** /* If Interrupts Are Enabled for this Pins component */ - 111:.\Generated_Source\PSoC5/USBFS_Dp.c **** #if defined(USBFS_Dp_INTSTAT) - 112:.\Generated_Source\PSoC5/USBFS_Dp.c **** - 113:.\Generated_Source\PSoC5/USBFS_Dp.c **** /******************************************************************************* - 114:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Function Name: USBFS_Dp_ClearInterrupt - 115:.\Generated_Source\PSoC5/USBFS_Dp.c **** ******************************************************************************** - 116:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Summary: - 117:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Clears any active interrupts attached to port and returns the value of the - 118:.\Generated_Source\PSoC5/USBFS_Dp.c **** * interrupt status register. - 119:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - 120:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Parameters: - 121:.\Generated_Source\PSoC5/USBFS_Dp.c **** * None - 122:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - 123:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Return: - 124:.\Generated_Source\PSoC5/USBFS_Dp.c **** * Returns the value of the interrupt status register - 125:.\Generated_Source\PSoC5/USBFS_Dp.c **** * - 126:.\Generated_Source\PSoC5/USBFS_Dp.c **** *******************************************************************************/ - 127:.\Generated_Source\PSoC5/USBFS_Dp.c **** uint8 USBFS_Dp_ClearInterrupt(void) - 128:.\Generated_Source\PSoC5/USBFS_Dp.c **** { - 147 .loc 1 128 0 - 148 .cfi_startproc - 149 @ args = 0, pretend = 0, frame = 0 - 150 @ frame_needed = 0, uses_anonymous_args = 0 - 151 @ link register save eliminated. - 129:.\Generated_Source\PSoC5/USBFS_Dp.c **** return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; - 152 .loc 1 129 0 - 153 0000 024B ldr r3, .L14 - 154 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 6 - - - 130:.\Generated_Source\PSoC5/USBFS_Dp.c **** } - 155 .loc 1 130 0 - 156 0004 C0F38010 ubfx r0, r0, #6, #1 - 157 0008 7047 bx lr - 158 .L15: - 159 000a 00BF .align 2 - 160 .L14: - 161 000c 8F450040 .word 1073759631 - 162 .cfi_endproc - 163 .LFE4: - 164 .size USBFS_Dp_ClearInterrupt, .-USBFS_Dp_ClearInterrupt - 165 .text - 166 .Letext0: - 167 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 168 .section .debug_info,"",%progbits - 169 .Ldebug_info0: - 170 0000 48010000 .4byte 0x148 - 171 0004 0200 .2byte 0x2 - 172 0006 00000000 .4byte .Ldebug_abbrev0 - 173 000a 04 .byte 0x4 - 174 000b 01 .uleb128 0x1 - 175 000c 41010000 .4byte .LASF21 - 176 0010 01 .byte 0x1 - 177 0011 AD000000 .4byte .LASF22 - 178 0015 62000000 .4byte .LASF23 - 179 0019 00000000 .4byte .Ldebug_ranges0+0 - 180 001d 00000000 .4byte 0 - 181 0021 00000000 .4byte 0 - 182 0025 00000000 .4byte .Ldebug_line0 - 183 0029 02 .uleb128 0x2 - 184 002a 01 .byte 0x1 - 185 002b 06 .byte 0x6 - 186 002c A9010000 .4byte .LASF0 - 187 0030 02 .uleb128 0x2 - 188 0031 01 .byte 0x1 - 189 0032 08 .byte 0x8 - 190 0033 3D000000 .4byte .LASF1 - 191 0037 02 .uleb128 0x2 - 192 0038 02 .byte 0x2 - 193 0039 05 .byte 0x5 - 194 003a 31010000 .4byte .LASF2 - 195 003e 02 .uleb128 0x2 - 196 003f 02 .byte 0x2 - 197 0040 07 .byte 0x7 - 198 0041 93000000 .4byte .LASF3 - 199 0045 02 .uleb128 0x2 - 200 0046 04 .byte 0x4 - 201 0047 05 .byte 0x5 - 202 0048 8A010000 .4byte .LASF4 - 203 004c 02 .uleb128 0x2 - 204 004d 04 .byte 0x4 - 205 004e 07 .byte 0x7 - 206 004f 50000000 .4byte .LASF5 - 207 0053 02 .uleb128 0x2 - 208 0054 08 .byte 0x8 - 209 0055 05 .byte 0x5 - 210 0056 1E010000 .4byte .LASF6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 7 - - - 211 005a 02 .uleb128 0x2 - 212 005b 08 .byte 0x8 - 213 005c 07 .byte 0x7 - 214 005d ED000000 .4byte .LASF7 - 215 0061 03 .uleb128 0x3 - 216 0062 04 .byte 0x4 - 217 0063 05 .byte 0x5 - 218 0064 696E7400 .ascii "int\000" - 219 0068 02 .uleb128 0x2 - 220 0069 04 .byte 0x4 - 221 006a 07 .byte 0x7 - 222 006b E0000000 .4byte .LASF8 - 223 006f 04 .uleb128 0x4 - 224 0070 3B010000 .4byte .LASF12 - 225 0074 02 .byte 0x2 - 226 0075 5B .byte 0x5b - 227 0076 30000000 .4byte 0x30 - 228 007a 02 .uleb128 0x2 - 229 007b 04 .byte 0x4 - 230 007c 04 .byte 0x4 - 231 007d 1F000000 .4byte .LASF9 - 232 0081 02 .uleb128 0x2 - 233 0082 08 .byte 0x8 - 234 0083 04 .byte 0x4 - 235 0084 A6000000 .4byte .LASF10 - 236 0088 02 .uleb128 0x2 - 237 0089 01 .byte 0x1 - 238 008a 08 .byte 0x8 - 239 008b 2C010000 .4byte .LASF11 - 240 008f 04 .uleb128 0x4 - 241 0090 4B000000 .4byte .LASF13 - 242 0094 02 .byte 0x2 - 243 0095 F0 .byte 0xf0 - 244 0096 9A000000 .4byte 0x9a - 245 009a 05 .uleb128 0x5 - 246 009b 6F000000 .4byte 0x6f - 247 009f 06 .uleb128 0x6 - 248 00a0 01 .byte 0x1 - 249 00a1 D1000000 .4byte .LASF14 - 250 00a5 01 .byte 0x1 - 251 00a6 27 .byte 0x27 - 252 00a7 01 .byte 0x1 - 253 00a8 00000000 .4byte .LFB0 - 254 00ac 1C000000 .4byte .LFE0 - 255 00b0 02 .byte 0x2 - 256 00b1 7D .byte 0x7d - 257 00b2 00 .sleb128 0 - 258 00b3 01 .byte 0x1 - 259 00b4 D7000000 .4byte 0xd7 - 260 00b8 07 .uleb128 0x7 - 261 00b9 00000000 .4byte .LASF16 - 262 00bd 01 .byte 0x1 - 263 00be 27 .byte 0x27 - 264 00bf 6F000000 .4byte 0x6f - 265 00c3 00000000 .4byte .LLST0 - 266 00c7 08 .uleb128 0x8 - 267 00c8 14000000 .4byte .LASF24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 8 - - - 268 00cc 01 .byte 0x1 - 269 00cd 29 .byte 0x29 - 270 00ce 6F000000 .4byte 0x6f - 271 00d2 21000000 .4byte .LLST1 - 272 00d6 00 .byte 0 - 273 00d7 06 .uleb128 0x6 - 274 00d8 01 .byte 0x1 - 275 00d9 93010000 .4byte .LASF15 - 276 00dd 01 .byte 0x1 - 277 00de 3C .byte 0x3c - 278 00df 01 .byte 0x1 - 279 00e0 00000000 .4byte .LFB1 - 280 00e4 18000000 .4byte .LFE1 - 281 00e8 02 .byte 0x2 - 282 00e9 7D .byte 0x7d - 283 00ea 00 .sleb128 0 - 284 00eb 01 .byte 0x1 - 285 00ec 00010000 .4byte 0x100 - 286 00f0 07 .uleb128 0x7 - 287 00f1 19010000 .4byte .LASF17 - 288 00f5 01 .byte 0x1 - 289 00f6 3C .byte 0x3c - 290 00f7 6F000000 .4byte 0x6f - 291 00fb 39000000 .4byte .LLST2 - 292 00ff 00 .byte 0 - 293 0100 09 .uleb128 0x9 - 294 0101 01 .byte 0x1 - 295 0102 06000000 .4byte .LASF18 - 296 0106 01 .byte 0x1 - 297 0107 54 .byte 0x54 - 298 0108 01 .byte 0x1 - 299 0109 6F000000 .4byte 0x6f - 300 010d 00000000 .4byte .LFB2 - 301 0111 10000000 .4byte .LFE2 - 302 0115 02 .byte 0x2 - 303 0116 7D .byte 0x7d - 304 0117 00 .sleb128 0 - 305 0118 01 .byte 0x1 - 306 0119 09 .uleb128 0x9 - 307 011a 01 .byte 0x1 - 308 011b 04010000 .4byte .LASF19 - 309 011f 01 .byte 0x1 - 310 0120 68 .byte 0x68 - 311 0121 01 .byte 0x1 - 312 0122 6F000000 .4byte 0x6f - 313 0126 00000000 .4byte .LFB3 - 314 012a 10000000 .4byte .LFE3 - 315 012e 02 .byte 0x2 - 316 012f 7D .byte 0x7d - 317 0130 00 .sleb128 0 - 318 0131 01 .byte 0x1 - 319 0132 09 .uleb128 0x9 - 320 0133 01 .byte 0x1 - 321 0134 25000000 .4byte .LASF20 - 322 0138 01 .byte 0x1 - 323 0139 7F .byte 0x7f - 324 013a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 9 - - - 325 013b 6F000000 .4byte 0x6f - 326 013f 00000000 .4byte .LFB4 - 327 0143 10000000 .4byte .LFE4 - 328 0147 02 .byte 0x2 - 329 0148 7D .byte 0x7d - 330 0149 00 .sleb128 0 - 331 014a 01 .byte 0x1 - 332 014b 00 .byte 0 - 333 .section .debug_abbrev,"",%progbits - 334 .Ldebug_abbrev0: - 335 0000 01 .uleb128 0x1 - 336 0001 11 .uleb128 0x11 - 337 0002 01 .byte 0x1 - 338 0003 25 .uleb128 0x25 - 339 0004 0E .uleb128 0xe - 340 0005 13 .uleb128 0x13 - 341 0006 0B .uleb128 0xb - 342 0007 03 .uleb128 0x3 - 343 0008 0E .uleb128 0xe - 344 0009 1B .uleb128 0x1b - 345 000a 0E .uleb128 0xe - 346 000b 55 .uleb128 0x55 - 347 000c 06 .uleb128 0x6 - 348 000d 11 .uleb128 0x11 - 349 000e 01 .uleb128 0x1 - 350 000f 52 .uleb128 0x52 - 351 0010 01 .uleb128 0x1 - 352 0011 10 .uleb128 0x10 - 353 0012 06 .uleb128 0x6 - 354 0013 00 .byte 0 - 355 0014 00 .byte 0 - 356 0015 02 .uleb128 0x2 - 357 0016 24 .uleb128 0x24 - 358 0017 00 .byte 0 - 359 0018 0B .uleb128 0xb - 360 0019 0B .uleb128 0xb - 361 001a 3E .uleb128 0x3e - 362 001b 0B .uleb128 0xb - 363 001c 03 .uleb128 0x3 - 364 001d 0E .uleb128 0xe - 365 001e 00 .byte 0 - 366 001f 00 .byte 0 - 367 0020 03 .uleb128 0x3 - 368 0021 24 .uleb128 0x24 - 369 0022 00 .byte 0 - 370 0023 0B .uleb128 0xb - 371 0024 0B .uleb128 0xb - 372 0025 3E .uleb128 0x3e - 373 0026 0B .uleb128 0xb - 374 0027 03 .uleb128 0x3 - 375 0028 08 .uleb128 0x8 - 376 0029 00 .byte 0 - 377 002a 00 .byte 0 - 378 002b 04 .uleb128 0x4 - 379 002c 16 .uleb128 0x16 - 380 002d 00 .byte 0 - 381 002e 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 10 - - - 382 002f 0E .uleb128 0xe - 383 0030 3A .uleb128 0x3a - 384 0031 0B .uleb128 0xb - 385 0032 3B .uleb128 0x3b - 386 0033 0B .uleb128 0xb - 387 0034 49 .uleb128 0x49 - 388 0035 13 .uleb128 0x13 - 389 0036 00 .byte 0 - 390 0037 00 .byte 0 - 391 0038 05 .uleb128 0x5 - 392 0039 35 .uleb128 0x35 - 393 003a 00 .byte 0 - 394 003b 49 .uleb128 0x49 - 395 003c 13 .uleb128 0x13 - 396 003d 00 .byte 0 - 397 003e 00 .byte 0 - 398 003f 06 .uleb128 0x6 - 399 0040 2E .uleb128 0x2e - 400 0041 01 .byte 0x1 - 401 0042 3F .uleb128 0x3f - 402 0043 0C .uleb128 0xc - 403 0044 03 .uleb128 0x3 - 404 0045 0E .uleb128 0xe - 405 0046 3A .uleb128 0x3a - 406 0047 0B .uleb128 0xb - 407 0048 3B .uleb128 0x3b - 408 0049 0B .uleb128 0xb - 409 004a 27 .uleb128 0x27 - 410 004b 0C .uleb128 0xc - 411 004c 11 .uleb128 0x11 - 412 004d 01 .uleb128 0x1 - 413 004e 12 .uleb128 0x12 - 414 004f 01 .uleb128 0x1 - 415 0050 40 .uleb128 0x40 - 416 0051 0A .uleb128 0xa - 417 0052 9742 .uleb128 0x2117 - 418 0054 0C .uleb128 0xc - 419 0055 01 .uleb128 0x1 - 420 0056 13 .uleb128 0x13 - 421 0057 00 .byte 0 - 422 0058 00 .byte 0 - 423 0059 07 .uleb128 0x7 - 424 005a 05 .uleb128 0x5 - 425 005b 00 .byte 0 - 426 005c 03 .uleb128 0x3 - 427 005d 0E .uleb128 0xe - 428 005e 3A .uleb128 0x3a - 429 005f 0B .uleb128 0xb - 430 0060 3B .uleb128 0x3b - 431 0061 0B .uleb128 0xb - 432 0062 49 .uleb128 0x49 - 433 0063 13 .uleb128 0x13 - 434 0064 02 .uleb128 0x2 - 435 0065 06 .uleb128 0x6 - 436 0066 00 .byte 0 - 437 0067 00 .byte 0 - 438 0068 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 11 - - - 439 0069 34 .uleb128 0x34 - 440 006a 00 .byte 0 - 441 006b 03 .uleb128 0x3 - 442 006c 0E .uleb128 0xe - 443 006d 3A .uleb128 0x3a - 444 006e 0B .uleb128 0xb - 445 006f 3B .uleb128 0x3b - 446 0070 0B .uleb128 0xb - 447 0071 49 .uleb128 0x49 - 448 0072 13 .uleb128 0x13 - 449 0073 02 .uleb128 0x2 - 450 0074 06 .uleb128 0x6 - 451 0075 00 .byte 0 - 452 0076 00 .byte 0 - 453 0077 09 .uleb128 0x9 - 454 0078 2E .uleb128 0x2e - 455 0079 00 .byte 0 - 456 007a 3F .uleb128 0x3f - 457 007b 0C .uleb128 0xc - 458 007c 03 .uleb128 0x3 - 459 007d 0E .uleb128 0xe - 460 007e 3A .uleb128 0x3a - 461 007f 0B .uleb128 0xb - 462 0080 3B .uleb128 0x3b - 463 0081 0B .uleb128 0xb - 464 0082 27 .uleb128 0x27 - 465 0083 0C .uleb128 0xc - 466 0084 49 .uleb128 0x49 - 467 0085 13 .uleb128 0x13 - 468 0086 11 .uleb128 0x11 - 469 0087 01 .uleb128 0x1 - 470 0088 12 .uleb128 0x12 - 471 0089 01 .uleb128 0x1 - 472 008a 40 .uleb128 0x40 - 473 008b 0A .uleb128 0xa - 474 008c 9742 .uleb128 0x2117 - 475 008e 0C .uleb128 0xc - 476 008f 00 .byte 0 - 477 0090 00 .byte 0 - 478 0091 00 .byte 0 - 479 .section .debug_loc,"",%progbits - 480 .Ldebug_loc0: - 481 .LLST0: - 482 0000 00000000 .4byte .LVL0 - 483 0004 04000000 .4byte .LVL1 - 484 0008 0100 .2byte 0x1 - 485 000a 50 .byte 0x50 - 486 000b 04000000 .4byte .LVL1 - 487 000f 1C000000 .4byte .LFE0 - 488 0013 0400 .2byte 0x4 - 489 0015 F3 .byte 0xf3 - 490 0016 01 .uleb128 0x1 - 491 0017 50 .byte 0x50 - 492 0018 9F .byte 0x9f - 493 0019 00000000 .4byte 0 - 494 001d 00000000 .4byte 0 - 495 .LLST1: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 12 - - - 496 0021 06000000 .4byte .LVL2 - 497 0025 0E000000 .4byte .LVL3 - 498 0029 0600 .2byte 0x6 - 499 002b 72 .byte 0x72 - 500 002c 00 .sleb128 0 - 501 002d 09 .byte 0x9 - 502 002e BF .byte 0xbf - 503 002f 1A .byte 0x1a - 504 0030 9F .byte 0x9f - 505 0031 00000000 .4byte 0 - 506 0035 00000000 .4byte 0 - 507 .LLST2: - 508 0039 00000000 .4byte .LVL4 - 509 003d 06000000 .4byte .LVL5 - 510 0041 0100 .2byte 0x1 - 511 0043 50 .byte 0x50 - 512 0044 06000000 .4byte .LVL5 - 513 0048 18000000 .4byte .LFE1 - 514 004c 0400 .2byte 0x4 - 515 004e F3 .byte 0xf3 - 516 004f 01 .uleb128 0x1 - 517 0050 50 .byte 0x50 - 518 0051 9F .byte 0x9f - 519 0052 00000000 .4byte 0 - 520 0056 00000000 .4byte 0 - 521 .section .debug_aranges,"",%progbits - 522 0000 3C000000 .4byte 0x3c - 523 0004 0200 .2byte 0x2 - 524 0006 00000000 .4byte .Ldebug_info0 - 525 000a 04 .byte 0x4 - 526 000b 00 .byte 0 - 527 000c 0000 .2byte 0 - 528 000e 0000 .2byte 0 - 529 0010 00000000 .4byte .LFB0 - 530 0014 1C000000 .4byte .LFE0-.LFB0 - 531 0018 00000000 .4byte .LFB1 - 532 001c 18000000 .4byte .LFE1-.LFB1 - 533 0020 00000000 .4byte .LFB2 - 534 0024 10000000 .4byte .LFE2-.LFB2 - 535 0028 00000000 .4byte .LFB3 - 536 002c 10000000 .4byte .LFE3-.LFB3 - 537 0030 00000000 .4byte .LFB4 - 538 0034 10000000 .4byte .LFE4-.LFB4 - 539 0038 00000000 .4byte 0 - 540 003c 00000000 .4byte 0 - 541 .section .debug_ranges,"",%progbits - 542 .Ldebug_ranges0: - 543 0000 00000000 .4byte .LFB0 - 544 0004 1C000000 .4byte .LFE0 - 545 0008 00000000 .4byte .LFB1 - 546 000c 18000000 .4byte .LFE1 - 547 0010 00000000 .4byte .LFB2 - 548 0014 10000000 .4byte .LFE2 - 549 0018 00000000 .4byte .LFB3 - 550 001c 10000000 .4byte .LFE3 - 551 0020 00000000 .4byte .LFB4 - 552 0024 10000000 .4byte .LFE4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 13 - - - 553 0028 00000000 .4byte 0 - 554 002c 00000000 .4byte 0 - 555 .section .debug_line,"",%progbits - 556 .Ldebug_line0: - 557 0000 A8000000 .section .debug_str,"MS",%progbits,1 - 557 02004700 - 557 00000201 - 557 FB0E0D00 - 557 01010101 - 558 .LASF16: - 559 0000 76616C75 .ascii "value\000" - 559 6500 - 560 .LASF18: - 561 0006 55534246 .ascii "USBFS_Dp_Read\000" - 561 535F4470 - 561 5F526561 - 561 6400 - 562 .LASF24: - 563 0014 73746174 .ascii "staticBits\000" - 563 69634269 - 563 747300 - 564 .LASF9: - 565 001f 666C6F61 .ascii "float\000" - 565 7400 - 566 .LASF20: - 567 0025 55534246 .ascii "USBFS_Dp_ClearInterrupt\000" - 567 535F4470 - 567 5F436C65 - 567 6172496E - 567 74657272 - 568 .LASF1: - 569 003d 756E7369 .ascii "unsigned char\000" - 569 676E6564 - 569 20636861 - 569 7200 - 570 .LASF13: - 571 004b 72656738 .ascii "reg8\000" - 571 00 - 572 .LASF5: - 573 0050 6C6F6E67 .ascii "long unsigned int\000" - 573 20756E73 - 573 69676E65 - 573 6420696E - 573 7400 - 574 .LASF23: - 575 0062 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 575 43534932 - 575 53445C73 - 575 6F667477 - 575 6172655C - 576 0091 6E00 .ascii "n\000" - 577 .LASF3: - 578 0093 73686F72 .ascii "short unsigned int\000" - 578 7420756E - 578 7369676E - 578 65642069 - 578 6E7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 14 - - - 579 .LASF10: - 580 00a6 646F7562 .ascii "double\000" - 580 6C6500 - 581 .LASF22: - 582 00ad 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_Dp.c\000" - 582 6E657261 - 582 7465645F - 582 536F7572 - 582 63655C50 - 583 .LASF14: - 584 00d1 55534246 .ascii "USBFS_Dp_Write\000" - 584 535F4470 - 584 5F577269 - 584 746500 - 585 .LASF8: - 586 00e0 756E7369 .ascii "unsigned int\000" - 586 676E6564 - 586 20696E74 - 586 00 - 587 .LASF7: - 588 00ed 6C6F6E67 .ascii "long long unsigned int\000" - 588 206C6F6E - 588 6720756E - 588 7369676E - 588 65642069 - 589 .LASF19: - 590 0104 55534246 .ascii "USBFS_Dp_ReadDataReg\000" - 590 535F4470 - 590 5F526561 - 590 64446174 - 590 61526567 - 591 .LASF17: - 592 0119 6D6F6465 .ascii "mode\000" - 592 00 - 593 .LASF6: - 594 011e 6C6F6E67 .ascii "long long int\000" - 594 206C6F6E - 594 6720696E - 594 7400 - 595 .LASF11: - 596 012c 63686172 .ascii "char\000" - 596 00 - 597 .LASF2: - 598 0131 73686F72 .ascii "short int\000" - 598 7420696E - 598 7400 - 599 .LASF12: - 600 013b 75696E74 .ascii "uint8\000" - 600 3800 - 601 .LASF21: - 602 0141 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 602 4320342E - 602 372E3320 - 602 32303133 - 602 30333132 - 603 0174 616E6368 .ascii "anch revision 196615]\000" - 603 20726576 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccENAnU1.s page 15 - - - 603 6973696F - 603 6E203139 - 603 36363135 - 604 .LASF4: - 605 018a 6C6F6E67 .ascii "long int\000" - 605 20696E74 - 605 00 - 606 .LASF15: - 607 0193 55534246 .ascii "USBFS_Dp_SetDriveMode\000" - 607 535F4470 - 607 5F536574 - 607 44726976 - 607 654D6F64 - 608 .LASF0: - 609 01a9 7369676E .ascii "signed char\000" - 609 65642063 - 609 68617200 - 610 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_Dp.o deleted file mode 100755 index 00aec8596344368822d1b7262cd1932c559320e6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4496 zcmb_fO>7)z8GgT+UGKVfOl+r#OIh)WMWpr{~6Jr*fE&o|#UJG*Jr z9(bjl=lyxU_j|wJnSJ&0wHK69VnxY>v@MYj3p$dY(J&#Om&203`kETuk-f5V_U<~f z_Z=D8+FFpidtZ}s?yBq!$mq^9djqO`Upb?Qe7_=P=jzDLA3l0*KY0(p%i3(0wSRnB z%8Mw%(S7FBEOhm27**})d^oD-U2;|NO9(hleu|b;c#~Ex|07ztLWNc_{}ioa;oq>_ zT)xqa8G9dA?m0$YnuO})a!(VAxpxSvcmg2|3;N#A@yv&K^r*k!sm2i!%n4$zi26HF zPnQ}ehf+L%hdNGkjCPND6HU}b-EIU9w&R2s4r@P&=Sl2UJ$R~{%4XURljL5NBXj)| z0>{|m)kgxN2Gy~F;XZfZ$iS_hL3KmzM{eh+^!0riPE3VSix}rYaR)B+J=b?-7$ZF+ zgdR^l-=BEL`v=vKDnIeFOZ^IwLOx|XNLifeFnc{|x4SZ&wnUYb9DYhF1WsU1K2num zLeav(qcZ7{NP6#%rhW$X#7Kp}8SHF$5gxN|pe4fe6tXFtN=i2--lQDrpM`%1JVzGz zR38uQ6PzWkEtkk!UI>~&9;Tk#{>FBYcD`~W@axiw z{kT!P)QDTMx)J(uJ3O}$_|cVS97NIfRxI1iR%5Lh)JwH>Kawa|J0}}qbFGy6d756l zu)H+4bmjEY{BkQ?jlb(hLF&MuS1yHNj9%(N=1t343gY>waXYxqQnE8G3v+W9N)zn*W*Ba?N~>X1LPw>`rlV3N3Tr{D z6-KS&|Bu>cPh%7MfnRNin&5t%!x9BMC$CRS&l82~z0OeXfO=9La!1r*HL9MzPn=jV0?nlZkMi5*Fo{HAG~@{-CkR1G*?3urggts#Ws*kbR(=~O&@z@ zEkO0{_K$it8ciIHBqN3|UM<|*46ukP4R{P1r1RNe`2y8E?vH$wW2L7c@e%d5b)cQxaDrBGhR zFUwnpZSQ=>E$=&Byq(AJ-ss}}@G-pK7#={&TXytnfr+(T9@uLK1twyb{$ z2Wr|HK=LRvCSPJ<4}kYAYXDgvWfHvXILa7@otHz1+i}31o;9|+gM72LGuT!o+OtgF zH7tG^4xWF00y7`yn|)#&sl0(jjZ&+fFXPgx?T1EA9z4v(-L#6t>vmMa{<1yN&UL&a zm=VV%bMEad*?jpfeqQtWJ)Q^_Eh8>&JMR6q^k{zDXK%xV;o?ib9iy+%#ZUe?*?cZe zawoso#pg+Hi`%i%9DiRs2+i%v=IWEyrnnt99r@hpZE@v*?w{+M2zO9hTMQGpXZqI3kGKmE*ku* z!LJ+SyNLX68{9JZioqWkeBIzr48Cpf4iQ`SJ%hh9{y!2Airh2yUyc0_W4}+t)P7*_ zf$@J#L^}ryz`FJkvBd@r9x?te5OLnWXpnam`OgzES#t)FPS?j%$U3=Oi9DmkF@whp zo+qL%{ihu`Z|p^bJZ%mREB6N5b5D_9A|m+&5p_)xxoAZ2Z2zEYzFt=tIuF|M{Ik8z zhxXjN%u^yF&ryRniOAO=qWvxr?OrE>{|h4cIvC+tO& MNB0B!8z$fX0HO8*OaK4? diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst deleted file mode 100755 index 8c0639f..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.lst +++ /dev/null @@ -1,239 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "USBFS_audio.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .Letext0: - 19 .section .debug_info,"",%progbits - 20 .Ldebug_info0: - 21 0000 7C000000 .4byte 0x7c - 22 0004 0200 .2byte 0x2 - 23 0006 00000000 .4byte .Ldebug_abbrev0 - 24 000a 04 .byte 0x4 - 25 000b 01 .uleb128 0x1 - 26 000c 1B000000 .4byte .LASF13 - 27 0010 01 .byte 0x1 - 28 0011 8D000000 .4byte .LASF14 - 29 0015 06010000 .4byte .LASF15 - 30 0019 00000000 .4byte .Ldebug_line0 - 31 001d 02 .uleb128 0x2 - 32 001e 01 .byte 0x1 - 33 001f 06 .byte 0x6 - 34 0020 EA000000 .4byte .LASF0 - 35 0024 02 .uleb128 0x2 - 36 0025 01 .byte 0x1 - 37 0026 08 .byte 0x8 - 38 0027 B4000000 .4byte .LASF1 - 39 002b 02 .uleb128 0x2 - 40 002c 02 .byte 0x2 - 41 002d 05 .byte 0x5 - 42 002e FC000000 .4byte .LASF2 - 43 0032 02 .uleb128 0x2 - 44 0033 02 .byte 0x2 - 45 0034 07 .byte 0x7 - 46 0035 D7000000 .4byte .LASF3 - 47 0039 02 .uleb128 0x2 - 48 003a 04 .byte 0x4 - 49 003b 05 .byte 0x5 - 50 003c C7000000 .4byte .LASF4 - 51 0040 02 .uleb128 0x2 - 52 0041 04 .byte 0x4 - 53 0042 07 .byte 0x7 - 54 0043 64000000 .4byte .LASF5 - 55 0047 02 .uleb128 0x2 - 56 0048 08 .byte 0x8 - 57 0049 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 2 - - - 58 004a 00000000 .4byte .LASF6 - 59 004e 02 .uleb128 0x2 - 60 004f 08 .byte 0x8 - 61 0050 07 .byte 0x7 - 62 0051 76000000 .4byte .LASF7 - 63 0055 03 .uleb128 0x3 - 64 0056 04 .byte 0x4 - 65 0057 05 .byte 0x5 - 66 0058 696E7400 .ascii "int\000" - 67 005c 02 .uleb128 0x2 - 68 005d 04 .byte 0x4 - 69 005e 07 .byte 0x7 - 70 005f 0E000000 .4byte .LASF8 - 71 0063 02 .uleb128 0x2 - 72 0064 04 .byte 0x4 - 73 0065 04 .byte 0x4 - 74 0066 F6000000 .4byte .LASF9 - 75 006a 02 .uleb128 0x2 - 76 006b 08 .byte 0x8 - 77 006c 04 .byte 0x4 - 78 006d D0000000 .4byte .LASF10 - 79 0071 02 .uleb128 0x2 - 80 0072 01 .byte 0x1 - 81 0073 08 .byte 0x8 - 82 0074 C2000000 .4byte .LASF11 - 83 0078 02 .uleb128 0x2 - 84 0079 04 .byte 0x4 - 85 007a 07 .byte 0x7 - 86 007b 37010000 .4byte .LASF12 - 87 007f 00 .byte 0 - 88 .section .debug_abbrev,"",%progbits - 89 .Ldebug_abbrev0: - 90 0000 01 .uleb128 0x1 - 91 0001 11 .uleb128 0x11 - 92 0002 01 .byte 0x1 - 93 0003 25 .uleb128 0x25 - 94 0004 0E .uleb128 0xe - 95 0005 13 .uleb128 0x13 - 96 0006 0B .uleb128 0xb - 97 0007 03 .uleb128 0x3 - 98 0008 0E .uleb128 0xe - 99 0009 1B .uleb128 0x1b - 100 000a 0E .uleb128 0xe - 101 000b 10 .uleb128 0x10 - 102 000c 06 .uleb128 0x6 - 103 000d 00 .byte 0 - 104 000e 00 .byte 0 - 105 000f 02 .uleb128 0x2 - 106 0010 24 .uleb128 0x24 - 107 0011 00 .byte 0 - 108 0012 0B .uleb128 0xb - 109 0013 0B .uleb128 0xb - 110 0014 3E .uleb128 0x3e - 111 0015 0B .uleb128 0xb - 112 0016 03 .uleb128 0x3 - 113 0017 0E .uleb128 0xe - 114 0018 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 3 - - - 115 0019 00 .byte 0 - 116 001a 03 .uleb128 0x3 - 117 001b 24 .uleb128 0x24 - 118 001c 00 .byte 0 - 119 001d 0B .uleb128 0xb - 120 001e 0B .uleb128 0xb - 121 001f 3E .uleb128 0x3e - 122 0020 0B .uleb128 0xb - 123 0021 03 .uleb128 0x3 - 124 0022 08 .uleb128 0x8 - 125 0023 00 .byte 0 - 126 0024 00 .byte 0 - 127 0025 00 .byte 0 - 128 .section .debug_aranges,"",%progbits - 129 0000 14000000 .4byte 0x14 - 130 0004 0200 .2byte 0x2 - 131 0006 00000000 .4byte .Ldebug_info0 - 132 000a 04 .byte 0x4 - 133 000b 00 .byte 0 - 134 000c 0000 .2byte 0 - 135 000e 0000 .2byte 0 - 136 0010 00000000 .4byte 0 - 137 0014 00000000 .4byte 0 - 138 .section .debug_line,"",%progbits - 139 .Ldebug_line0: - 140 0000 19000000 .section .debug_str,"MS",%progbits,1 - 140 02001300 - 140 00000201 - 140 FB0E0D00 - 140 01010101 - 141 .LASF6: - 142 0000 6C6F6E67 .ascii "long long int\000" - 142 206C6F6E - 142 6720696E - 142 7400 - 143 .LASF8: - 144 000e 756E7369 .ascii "unsigned int\000" - 144 676E6564 - 144 20696E74 - 144 00 - 145 .LASF13: - 146 001b 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 146 4320342E - 146 372E3320 - 146 32303133 - 146 30333132 - 147 004e 616E6368 .ascii "anch revision 196615]\000" - 147 20726576 - 147 6973696F - 147 6E203139 - 147 36363135 - 148 .LASF5: - 149 0064 6C6F6E67 .ascii "long unsigned int\000" - 149 20756E73 - 149 69676E65 - 149 6420696E - 149 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccNAvcMf.s page 4 - - - 150 .LASF7: - 151 0076 6C6F6E67 .ascii "long long unsigned int\000" - 151 206C6F6E - 151 6720756E - 151 7369676E - 151 65642069 - 152 .LASF14: - 153 008d 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_audio.c\000" - 153 6E657261 - 153 7465645F - 153 536F7572 - 153 63655C50 - 154 .LASF1: - 155 00b4 756E7369 .ascii "unsigned char\000" - 155 676E6564 - 155 20636861 - 155 7200 - 156 .LASF11: - 157 00c2 63686172 .ascii "char\000" - 157 00 - 158 .LASF4: - 159 00c7 6C6F6E67 .ascii "long int\000" - 159 20696E74 - 159 00 - 160 .LASF10: - 161 00d0 646F7562 .ascii "double\000" - 161 6C6500 - 162 .LASF3: - 163 00d7 73686F72 .ascii "short unsigned int\000" - 163 7420756E - 163 7369676E - 163 65642069 - 163 6E7400 - 164 .LASF0: - 165 00ea 7369676E .ascii "signed char\000" - 165 65642063 - 165 68617200 - 166 .LASF9: - 167 00f6 666C6F61 .ascii "float\000" - 167 7400 - 168 .LASF2: - 169 00fc 73686F72 .ascii "short int\000" - 169 7420696E - 169 7400 - 170 .LASF15: - 171 0106 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 171 43534932 - 171 53445C73 - 171 6F667477 - 171 6172655C - 172 0135 6E00 .ascii "n\000" - 173 .LASF12: - 174 0137 73697A65 .ascii "sizetype\000" - 174 74797065 - 174 00 - 175 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_audio.o deleted file mode 100755 index a597323319500c5613238c8992cd3b847a7a6f62..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1896 zcmb_d%We}%6usqc$AN$eF9CxF^&nu3M4BW{h(MzeU?3Vqco{Scj7+z?oU~+jL3bO- zJT&|O5+B0{L~Lfu4v9}-2S{u{f^(~@?3fKKxKhp{c3gp<)t4ClR%W zN1ze8y0_f{kP_|YUVN->C+uENig}58Dp~b($BP*xS-hIa$YW*s>TR##E%-}*-J74C ztIyWw=Dk`fdosx6aqrH#n=2<}Ka^1-s+!cTFplDkNM_>R;If7qac+-19G>|E0tqNBvZe$9%Tt- z@n14uzb}cF8;vtwjcavFsb1!FRqCNK-bGUx?|P~_GRst&9sd!dc4-4|M^?n|Nz&tH*%`yzl$&Z3OAV179 z@^QX?B*VdKJ5IU^F3p25#IbJn1~}|hi2+4GFHWT8n4A2L>h~o|>!TQckmqR}4syhQ zujqG%VBB{t#d|agpt$Kozku^~E}kvX*KzD)`4x>{$+zNW5o5=I>iM29F=Blupl`88 z;7cs@8IT_{zdvrA?>96%29)?Cag2!(>$?iwa(2B&+t0*^^<9R(Iq$tnk%#kw4)fjx zw_`x*9oo-Kj96a`ojLEDWe1eA)(M>{x7?tOyM_aJ0GkyX_b&{n@qKIGKwRA_Ks)u$ zB5vq;k2wCUTCs7A_N=uJb>0Bkfwm2e>pYFdHL+(4N*jpd7%O%@t6SV`cj@hCYiD$Z zt1Ya~_)6g4oRQo@+IztJ2o*Lx4R#Io4f4I USBFS_BTLDR_SIZEOF_WRITE_BUFFER) - 206:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 207:.\Generated_Source\PSoC5/USBFS_boot.c **** size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER; - 208:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 209:.\Generated_Source\PSoC5/USBFS_boot.c **** /* Start a timer to wait on. */ - 210:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_CyBtLdrStarttimer(time, timeOut); - 225 .loc 1 210 0 - 226 0006 0A22 movs r2, #10 - 227 .LVL19: - 228 0008 5343 muls r3, r2, r3 - 229 .LVL20: - 230 000a 284C ldr r4, .L43 - 201:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 231 .loc 1 201 0 - 232 000c 8046 mov r8, r0 - 233 .loc 1 210 0 - 234 000e 6380 strh r3, [r4, #2] @ movhi - 211:.\Generated_Source\PSoC5/USBFS_boot.c **** - 212:.\Generated_Source\PSoC5/USBFS_boot.c **** /* Wait on enumeration in first time */ - 213:.\Generated_Source\PSoC5/USBFS_boot.c **** if(USBFS_started) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 9 - - - 235 .loc 1 213 0 - 236 0010 2478 ldrb r4, [r4, #0] @ zero_extendqisi2 - 201:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 237 .loc 1 201 0 - 238 0012 0F46 mov r7, r1 - 239 .LVL21: - 240 .loc 1 213 0 - 241 0014 D4B1 cbz r4, .L40 - 242 .L28: - 243 0016 0024 movs r4, #0 - 244 .LVL22: - 245 .L16: - 214:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 215:.\Generated_Source\PSoC5/USBFS_boot.c **** /* Wait for Device to enumerate */ - 216:.\Generated_Source\PSoC5/USBFS_boot.c **** while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time)) - 246 .loc 1 216 0 discriminator 1 - 247 0018 FFF7FEFF bl USBFS_GetConfiguration - 248 .LVL23: - 249 001c 58B9 cbnz r0, .L18 - 250 .loc 1 216 0 is_stmt 0 discriminator 2 - 251 001e 234B ldr r3, .L43 - 252 0020 661C adds r6, r4, #1 - 253 0022 5888 ldrh r0, [r3, #2] - 254 0024 B6B2 uxth r6, r6 - 255 .LVL24: - 256 0026 A042 cmp r0, r4 - 257 0028 04D9 bls .L41 - 258 .L19: - 217:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 218:.\Generated_Source\PSoC5/USBFS_boot.c **** CyDelay(1u); /* 1ms delay */ - 259 .loc 1 218 0 is_stmt 1 - 260 002a 0120 movs r0, #1 - 261 002c FFF7FEFF bl CyDelay - 262 .LVL25: - 216:.\Generated_Source\PSoC5/USBFS_boot.c **** while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time)) - 263 .loc 1 216 0 - 264 0030 3446 mov r4, r6 - 265 0032 F1E7 b .L16 - 266 .L41: - 267 0034 3446 mov r4, r6 - 268 .LVL26: - 269 .L18: - 219:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 220:.\Generated_Source\PSoC5/USBFS_boot.c **** /* Enable first OUT, if enumeration complete */ - 221:.\Generated_Source\PSoC5/USBFS_boot.c **** if(USBFS_GetConfiguration()) - 270 .loc 1 221 0 - 271 0036 FFF7FEFF bl USBFS_GetConfiguration - 272 .LVL27: - 273 003a E0B1 cbz r0, .L35 - 222:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 223:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */ - 274 .loc 1 223 0 - 275 003c FFF7FEFF bl USBFS_IsConfigurationChanged - 276 .LVL28: - 224:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_CyBtldrCommReset(); - 277 .loc 1 224 0 - 278 0040 FFF7FEFF bl USBFS_CyBtldrCommReset - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 10 - - - 279 .LVL29: - 225:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_started = 0u; - 280 .loc 1 225 0 - 281 0044 194A ldr r2, .L43 - 282 0046 0021 movs r1, #0 - 283 0048 1170 strb r1, [r2, #0] - 284 004a 14E0 b .L35 - 285 .LVL30: - 286 .L40: - 226:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 227:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 228:.\Generated_Source\PSoC5/USBFS_boot.c **** else /* Check for configuration changes, has been done by Host */ - 229:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 230:.\Generated_Source\PSoC5/USBFS_boot.c **** if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or - 287 .loc 1 230 0 - 288 004c FFF7FEFF bl USBFS_IsConfigurationChanged - 289 .LVL31: - 290 0050 08B9 cbnz r0, .L22 - 291 .L23: - 210:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_CyBtLdrStarttimer(time, timeOut); - 292 .loc 1 210 0 - 293 0052 0024 movs r4, #0 - 294 0054 0FE0 b .L35 - 295 .L22: - 231:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 232:.\Generated_Source\PSoC5/USBFS_boot.c **** if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */ - 296 .loc 1 232 0 - 297 0056 FFF7FEFF bl USBFS_GetConfiguration - 298 .LVL32: - 299 005a 0028 cmp r0, #0 - 300 005c F9D0 beq .L23 - 233:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 234:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_CyBtldrCommReset(); - 301 .loc 1 234 0 - 302 005e FFF7FEFF bl USBFS_CyBtldrCommReset - 303 .LVL33: - 304 0062 08E0 b .L35 - 305 .LVL34: - 306 .L42: - 235:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 236:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 237:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 238:.\Generated_Source\PSoC5/USBFS_boot.c **** /* Wait on next packet */ - 239:.\Generated_Source\PSoC5/USBFS_boot.c **** while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ - 307 .loc 1 239 0 discriminator 2 - 308 0064 114B ldr r3, .L43 - 240:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_CyBtLdrChecktimer(time)) - 309 .loc 1 240 0 discriminator 2 - 310 0066 661C adds r6, r4, #1 - 239:.\Generated_Source\PSoC5/USBFS_boot.c **** while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ - 311 .loc 1 239 0 discriminator 2 - 312 0068 5988 ldrh r1, [r3, #2] - 313 .loc 1 240 0 discriminator 2 - 314 006a B6B2 uxth r6, r6 - 315 .LVL35: - 239:.\Generated_Source\PSoC5/USBFS_boot.c **** while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ - 316 .loc 1 239 0 discriminator 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 11 - - - 317 006c A142 cmp r1, r4 - 318 006e 09D9 bls .L24 - 319 .L25: - 241:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 242:.\Generated_Source\PSoC5/USBFS_boot.c **** CyDelay(1u); /* 1ms delay */ - 320 .loc 1 242 0 - 321 0070 FFF7FEFF bl CyDelay - 322 .LVL36: - 240:.\Generated_Source\PSoC5/USBFS_boot.c **** USBFS_CyBtLdrChecktimer(time)) - 323 .loc 1 240 0 - 324 0074 3446 mov r4, r6 - 325 .LVL37: - 326 .L35: - 239:.\Generated_Source\PSoC5/USBFS_boot.c **** while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ - 327 .loc 1 239 0 discriminator 1 - 328 0076 0120 movs r0, #1 - 329 0078 FFF7FEFF bl USBFS_GetEPState - 330 .LVL38: - 331 007c 0128 cmp r0, #1 - 332 .loc 1 242 0 discriminator 1 - 333 007e 4FF00100 mov r0, #1 - 239:.\Generated_Source\PSoC5/USBFS_boot.c **** while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ - 334 .loc 1 239 0 discriminator 1 - 335 0082 EFD1 bne .L42 - 336 .LVL39: - 337 .L24: - 243:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 244:.\Generated_Source\PSoC5/USBFS_boot.c **** - 245:.\Generated_Source\PSoC5/USBFS_boot.c **** /* OUT EP has completed */ - 246:.\Generated_Source\PSoC5/USBFS_boot.c **** if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL) - 338 .loc 1 246 0 - 339 0084 FFF7FEFF bl USBFS_GetEPState - 340 .LVL40: - 341 0088 0128 cmp r0, #1 - 342 008a 0AD1 bne .L26 - 247:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 248:.\Generated_Source\PSoC5/USBFS_boot.c **** *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size); - 343 .loc 1 248 0 - 344 008c 4146 mov r1, r8 - 345 008e 402F cmp r7, #64 - 346 0090 34BF ite cc - 347 0092 3A46 movcc r2, r7 - 348 0094 4022 movcs r2, #64 - 349 0096 FFF7FEFF bl USBFS_ReadOutEP - 350 .LVL41: - 351 009a 2880 strh r0, [r5, #0] @ movhi - 352 .LVL42: - 249:.\Generated_Source\PSoC5/USBFS_boot.c **** status = CYRET_SUCCESS; - 353 .loc 1 249 0 - 354 009c 0020 movs r0, #0 - 355 009e BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 356 .LVL43: - 357 .L26: - 250:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 251:.\Generated_Source\PSoC5/USBFS_boot.c **** else - 252:.\Generated_Source\PSoC5/USBFS_boot.c **** { - 253:.\Generated_Source\PSoC5/USBFS_boot.c **** *count = 0u; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 12 - - - 358 .loc 1 253 0 - 359 00a2 0020 movs r0, #0 - 360 00a4 2880 strh r0, [r5, #0] @ movhi - 361 .LVL44: - 254:.\Generated_Source\PSoC5/USBFS_boot.c **** status = CYRET_TIMEOUT; - 362 .loc 1 254 0 - 363 00a6 1020 movs r0, #16 - 364 .LVL45: - 255:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 256:.\Generated_Source\PSoC5/USBFS_boot.c **** return(status); - 257:.\Generated_Source\PSoC5/USBFS_boot.c **** } - 365 .loc 1 257 0 - 366 00a8 BDE8F081 pop {r4, r5, r6, r7, r8, pc} - 367 .L44: - 368 .align 2 - 369 .L43: - 370 00ac 00000000 .word .LANCHOR0 - 371 .cfi_endproc - 372 .LFE4: - 373 .size USBFS_CyBtldrCommRead, .-USBFS_CyBtldrCommRead - 374 .bss - 375 .align 1 - 376 .set .LANCHOR0,. + 0 - 377 .type USBFS_started, %object - 378 .size USBFS_started, 1 - 379 USBFS_started: - 380 0000 00 .space 1 - 381 0001 00 .space 1 - 382 .type USBFS_universalTime, %object - 383 .size USBFS_universalTime, 2 - 384 USBFS_universalTime: - 385 0002 0000 .space 2 - 386 .text - 387 .Letext0: - 388 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 389 .file 3 ".\\Generated_Source\\PSoC5\\USBFS.h" - 390 .file 4 ".\\Generated_Source\\PSoC5\\CyLib.h" - 391 .section .debug_info,"",%progbits - 392 .Ldebug_info0: - 393 0000 0B040000 .4byte 0x40b - 394 0004 0200 .2byte 0x2 - 395 0006 00000000 .4byte .Ldebug_abbrev0 - 396 000a 04 .byte 0x4 - 397 000b 01 .uleb128 0x1 - 398 000c B7010000 .4byte .LASF37 - 399 0010 01 .byte 0x1 - 400 0011 66020000 .4byte .LASF38 - 401 0015 91000000 .4byte .LASF39 - 402 0019 00000000 .4byte .Ldebug_ranges0+0 - 403 001d 00000000 .4byte 0 - 404 0021 00000000 .4byte 0 - 405 0025 00000000 .4byte .Ldebug_line0 - 406 0029 02 .uleb128 0x2 - 407 002a 01 .byte 0x1 - 408 002b 06 .byte 0x6 - 409 002c 30020000 .4byte .LASF0 - 410 0030 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 13 - - - 411 0031 01 .byte 0x1 - 412 0032 08 .byte 0x8 - 413 0033 C8000000 .4byte .LASF1 - 414 0037 02 .uleb128 0x2 - 415 0038 02 .byte 0x2 - 416 0039 05 .byte 0x5 - 417 003a AD010000 .4byte .LASF2 - 418 003e 02 .uleb128 0x2 - 419 003f 02 .byte 0x2 - 420 0040 07 .byte 0x7 - 421 0041 16000000 .4byte .LASF3 - 422 0045 02 .uleb128 0x2 - 423 0046 04 .byte 0x4 - 424 0047 05 .byte 0x5 - 425 0048 11020000 .4byte .LASF4 - 426 004c 02 .uleb128 0x2 - 427 004d 04 .byte 0x4 - 428 004e 07 .byte 0x7 - 429 004f 7F000000 .4byte .LASF5 - 430 0053 02 .uleb128 0x2 - 431 0054 08 .byte 0x8 - 432 0055 05 .byte 0x5 - 433 0056 8B010000 .4byte .LASF6 - 434 005a 02 .uleb128 0x2 - 435 005b 08 .byte 0x8 - 436 005c 07 .byte 0x7 - 437 005d 36010000 .4byte .LASF7 - 438 0061 03 .uleb128 0x3 - 439 0062 04 .byte 0x4 - 440 0063 05 .byte 0x5 - 441 0064 696E7400 .ascii "int\000" - 442 0068 02 .uleb128 0x2 - 443 0069 04 .byte 0x4 - 444 006a 07 .byte 0x7 - 445 006b 29010000 .4byte .LASF8 - 446 006f 04 .uleb128 0x4 - 447 0070 C2000000 .4byte .LASF9 - 448 0074 02 .byte 0x2 - 449 0075 5B .byte 0x5b - 450 0076 30000000 .4byte 0x30 - 451 007a 04 .uleb128 0x4 - 452 007b 04010000 .4byte .LASF10 - 453 007f 02 .byte 0x2 - 454 0080 5C .byte 0x5c - 455 0081 3E000000 .4byte 0x3e - 456 0085 04 .uleb128 0x4 - 457 0086 0B010000 .4byte .LASF11 - 458 008a 02 .byte 0x2 - 459 008b 5D .byte 0x5d - 460 008c 4C000000 .4byte 0x4c - 461 0090 02 .uleb128 0x2 - 462 0091 04 .byte 0x4 - 463 0092 04 .byte 0x4 - 464 0093 69000000 .4byte .LASF12 - 465 0097 02 .uleb128 0x2 - 466 0098 08 .byte 0x8 - 467 0099 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 14 - - - 468 009a D6000000 .4byte .LASF13 - 469 009e 02 .uleb128 0x2 - 470 009f 01 .byte 0x1 - 471 00a0 08 .byte 0x8 - 472 00a1 99010000 .4byte .LASF14 - 473 00a5 04 .uleb128 0x4 - 474 00a6 00000000 .4byte .LASF15 - 475 00aa 02 .byte 0x2 - 476 00ab E8 .byte 0xe8 - 477 00ac 4C000000 .4byte 0x4c - 478 00b0 02 .uleb128 0x2 - 479 00b1 04 .byte 0x4 - 480 00b2 07 .byte 0x7 - 481 00b3 82010000 .4byte .LASF16 - 482 00b7 05 .uleb128 0x5 - 483 00b8 01 .byte 0x1 - 484 00b9 52000000 .4byte .LASF17 - 485 00bd 01 .byte 0x1 - 486 00be 3E .byte 0x3e - 487 00bf 01 .byte 0x1 - 488 00c0 00000000 .4byte .LFB0 - 489 00c4 18000000 .4byte .LFE0 - 490 00c8 00000000 .4byte .LLST0 - 491 00cc 01 .byte 0x1 - 492 00cd E6000000 .4byte 0xe6 - 493 00d1 06 .uleb128 0x6 - 494 00d2 0C000000 .4byte .LVL0 - 495 00d6 48030000 .4byte 0x348 - 496 00da 07 .uleb128 0x7 - 497 00db 01 .byte 0x1 - 498 00dc 51 .byte 0x51 - 499 00dd 01 .byte 0x1 - 500 00de 32 .byte 0x32 - 501 00df 07 .uleb128 0x7 - 502 00e0 01 .byte 0x1 - 503 00e1 50 .byte 0x50 - 504 00e2 01 .byte 0x1 - 505 00e3 30 .byte 0x30 - 506 00e4 00 .byte 0 - 507 00e5 00 .byte 0 - 508 00e6 08 .uleb128 0x8 - 509 00e7 01 .byte 0x1 - 510 00e8 1A020000 .4byte .LASF18 - 511 00ec 01 .byte 0x1 - 512 00ed 59 .byte 0x59 - 513 00ee 01 .byte 0x1 - 514 00ef 00000000 .4byte .LFB1 - 515 00f3 04000000 .4byte .LFE1 - 516 00f7 02 .byte 0x2 - 517 00f8 7D .byte 0x7d - 518 00f9 00 .sleb128 0 - 519 00fa 01 .byte 0x1 - 520 00fb 0A010000 .4byte 0x10a - 521 00ff 09 .uleb128 0x9 - 522 0100 04000000 .4byte .LVL1 - 523 0104 01 .byte 0x1 - 524 0105 61030000 .4byte 0x361 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 15 - - - 525 0109 00 .byte 0 - 526 010a 08 .uleb128 0x8 - 527 010b 01 .byte 0x1 - 528 010c 29000000 .4byte .LASF19 - 529 0110 01 .byte 0x1 - 530 0111 70 .byte 0x70 - 531 0112 01 .byte 0x1 - 532 0113 00000000 .4byte .LFB2 - 533 0117 06000000 .4byte .LFE2 - 534 011b 02 .byte 0x2 - 535 011c 7D .byte 0x7d - 536 011d 00 .sleb128 0 - 537 011e 01 .byte 0x1 - 538 011f 34010000 .4byte 0x134 - 539 0123 0A .uleb128 0xa - 540 0124 06000000 .4byte .LVL2 - 541 0128 01 .byte 0x1 - 542 0129 6B030000 .4byte 0x36b - 543 012d 07 .uleb128 0x7 - 544 012e 01 .byte 0x1 - 545 012f 50 .byte 0x50 - 546 0130 01 .byte 0x1 - 547 0131 31 .byte 0x31 - 548 0132 00 .byte 0 - 549 0133 00 .byte 0 - 550 0134 0B .uleb128 0xb - 551 0135 01 .byte 0x1 - 552 0136 ED000000 .4byte .LASF26 - 553 013a 01 .byte 0x1 - 554 013b 8D .byte 0x8d - 555 013c 01 .byte 0x1 - 556 013d A5000000 .4byte 0xa5 - 557 0141 00000000 .4byte .LFB3 - 558 0145 54000000 .4byte .LFE3 - 559 0149 20000000 .4byte .LLST1 - 560 014d 01 .byte 0x1 - 561 014e 01020000 .4byte 0x201 - 562 0152 0C .uleb128 0xc - 563 0153 4C000000 .4byte .LASF20 - 564 0157 01 .byte 0x1 - 565 0158 8D .byte 0x8d - 566 0159 01020000 .4byte 0x201 - 567 015d 40000000 .4byte .LLST2 - 568 0161 0C .uleb128 0xc - 569 0162 7A000000 .4byte .LASF21 - 570 0166 01 .byte 0x1 - 571 0167 8D .byte 0x8d - 572 0168 7A000000 .4byte 0x7a - 573 016c 6C000000 .4byte .LLST3 - 574 0170 0C .uleb128 0xc - 575 0171 10000000 .4byte .LASF22 - 576 0175 01 .byte 0x1 - 577 0176 8D .byte 0x8d - 578 0177 07020000 .4byte 0x207 - 579 017b 8D000000 .4byte .LLST4 - 580 017f 0C .uleb128 0xc - 581 0180 75010000 .4byte .LASF23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 16 - - - 582 0184 01 .byte 0x1 - 583 0185 8D .byte 0x8d - 584 0186 6F000000 .4byte 0x6f - 585 018a AB000000 .4byte .LLST5 - 586 018e 0D .uleb128 0xd - 587 018f 7D010000 .4byte .LASF24 - 588 0193 01 .byte 0x1 - 589 0194 90 .byte 0x90 - 590 0195 7A000000 .4byte 0x7a - 591 0199 CC000000 .4byte .LLST6 - 592 019d 0D .uleb128 0xd - 593 019e 09000000 .4byte .LASF25 - 594 01a2 01 .byte 0x1 - 595 01a3 91 .byte 0x91 - 596 01a4 A5000000 .4byte 0xa5 - 597 01a8 F6000000 .4byte .LLST7 - 598 01ac 0E .uleb128 0xe - 599 01ad 14000000 .4byte .LVL7 - 600 01b1 7F030000 .4byte 0x37f - 601 01b5 CB010000 .4byte 0x1cb - 602 01b9 07 .uleb128 0x7 - 603 01ba 01 .byte 0x1 - 604 01bb 52 .byte 0x52 - 605 01bc 02 .byte 0x2 - 606 01bd 08 .byte 0x8 - 607 01be 40 .byte 0x40 - 608 01bf 07 .uleb128 0x7 - 609 01c0 01 .byte 0x1 - 610 01c1 51 .byte 0x51 - 611 01c2 02 .byte 0x2 - 612 01c3 77 .byte 0x77 - 613 01c4 00 .sleb128 0 - 614 01c5 07 .uleb128 0x7 - 615 01c6 01 .byte 0x1 - 616 01c7 50 .byte 0x50 - 617 01c8 01 .byte 0x1 - 618 01c9 32 .byte 0x32 - 619 01ca 00 .byte 0 - 620 01cb 0E .uleb128 0xe - 621 01cc 24000000 .4byte .LVL10 - 622 01d0 A8030000 .4byte 0x3a8 - 623 01d4 DE010000 .4byte 0x1de - 624 01d8 07 .uleb128 0x7 - 625 01d9 01 .byte 0x1 - 626 01da 50 .byte 0x50 - 627 01db 01 .byte 0x1 - 628 01dc 32 .byte 0x32 - 629 01dd 00 .byte 0 - 630 01de 0E .uleb128 0xe - 631 01df 38000000 .4byte .LVL12 - 632 01e3 C0030000 .4byte 0x3c0 - 633 01e7 F1010000 .4byte 0x1f1 - 634 01eb 07 .uleb128 0x7 - 635 01ec 01 .byte 0x1 - 636 01ed 50 .byte 0x50 - 637 01ee 01 .byte 0x1 - 638 01ef 31 .byte 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 17 - - - 639 01f0 00 .byte 0 - 640 01f1 06 .uleb128 0x6 - 641 01f2 42000000 .4byte .LVL14 - 642 01f6 A8030000 .4byte 0x3a8 - 643 01fa 07 .uleb128 0x7 - 644 01fb 01 .byte 0x1 - 645 01fc 50 .byte 0x50 - 646 01fd 01 .byte 0x1 - 647 01fe 32 .byte 0x32 - 648 01ff 00 .byte 0 - 649 0200 00 .byte 0 - 650 0201 0F .uleb128 0xf - 651 0202 04 .byte 0x4 - 652 0203 6F000000 .4byte 0x6f - 653 0207 0F .uleb128 0xf - 654 0208 04 .byte 0x4 - 655 0209 7A000000 .4byte 0x7a - 656 020d 0B .uleb128 0xb - 657 020e 01 .byte 0x1 - 658 020f 5F010000 .4byte .LASF27 - 659 0213 01 .byte 0x1 - 660 0214 C7 .byte 0xc7 - 661 0215 01 .byte 0x1 - 662 0216 A5000000 .4byte 0xa5 - 663 021a 00000000 .4byte .LFB4 - 664 021e B0000000 .4byte .LFE4 - 665 0222 15010000 .4byte .LLST8 - 666 0226 01 .byte 0x1 - 667 0227 26030000 .4byte 0x326 - 668 022b 0C .uleb128 0xc - 669 022c 4C000000 .4byte .LASF20 - 670 0230 01 .byte 0x1 - 671 0231 C7 .byte 0xc7 - 672 0232 01020000 .4byte 0x201 - 673 0236 35010000 .4byte .LLST9 - 674 023a 0C .uleb128 0xc - 675 023b 7A000000 .4byte .LASF21 - 676 023f 01 .byte 0x1 - 677 0240 C7 .byte 0xc7 - 678 0241 7A000000 .4byte 0x7a - 679 0245 69010000 .4byte .LLST10 - 680 0249 0C .uleb128 0xc - 681 024a 10000000 .4byte .LASF22 - 682 024e 01 .byte 0x1 - 683 024f C7 .byte 0xc7 - 684 0250 07020000 .4byte 0x207 - 685 0254 FC010000 .4byte .LLST11 - 686 0258 0C .uleb128 0xc - 687 0259 75010000 .4byte .LASF23 - 688 025d 01 .byte 0x1 - 689 025e C7 .byte 0xc7 - 690 025f 6F000000 .4byte 0x6f - 691 0263 1A020000 .4byte .LLST12 - 692 0267 0D .uleb128 0xd - 693 0268 09000000 .4byte .LASF25 - 694 026c 01 .byte 0x1 - 695 026d CA .byte 0xca - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 18 - - - 696 026e A5000000 .4byte 0xa5 - 697 0272 3B020000 .4byte .LLST13 - 698 0276 0D .uleb128 0xd - 699 0277 7D010000 .4byte .LASF24 - 700 027b 01 .byte 0x1 - 701 027c CB .byte 0xcb - 702 027d 7A000000 .4byte 0x7a - 703 0281 66020000 .4byte .LLST14 - 704 0285 10 .uleb128 0x10 - 705 0286 1C000000 .4byte .LVL23 - 706 028a D4030000 .4byte 0x3d4 - 707 028e 0E .uleb128 0xe - 708 028f 30000000 .4byte .LVL25 - 709 0293 C0030000 .4byte 0x3c0 - 710 0297 A1020000 .4byte 0x2a1 - 711 029b 07 .uleb128 0x7 - 712 029c 01 .byte 0x1 - 713 029d 50 .byte 0x50 - 714 029e 01 .byte 0x1 - 715 029f 31 .byte 0x31 - 716 02a0 00 .byte 0 - 717 02a1 10 .uleb128 0x10 - 718 02a2 3A000000 .4byte .LVL27 - 719 02a6 D4030000 .4byte 0x3d4 - 720 02aa 10 .uleb128 0x10 - 721 02ab 40000000 .4byte .LVL28 - 722 02af E2030000 .4byte 0x3e2 - 723 02b3 10 .uleb128 0x10 - 724 02b4 44000000 .4byte .LVL29 - 725 02b8 0A010000 .4byte 0x10a - 726 02bc 10 .uleb128 0x10 - 727 02bd 50000000 .4byte .LVL31 - 728 02c1 E2030000 .4byte 0x3e2 - 729 02c5 10 .uleb128 0x10 - 730 02c6 5A000000 .4byte .LVL32 - 731 02ca D4030000 .4byte 0x3d4 - 732 02ce 10 .uleb128 0x10 - 733 02cf 62000000 .4byte .LVL33 - 734 02d3 0A010000 .4byte 0x10a - 735 02d7 10 .uleb128 0x10 - 736 02d8 74000000 .4byte .LVL36 - 737 02dc C0030000 .4byte 0x3c0 - 738 02e0 0E .uleb128 0xe - 739 02e1 7C000000 .4byte .LVL38 - 740 02e5 A8030000 .4byte 0x3a8 - 741 02e9 F3020000 .4byte 0x2f3 - 742 02ed 07 .uleb128 0x7 - 743 02ee 01 .byte 0x1 - 744 02ef 50 .byte 0x50 - 745 02f0 01 .byte 0x1 - 746 02f1 31 .byte 0x31 - 747 02f2 00 .byte 0 - 748 02f3 10 .uleb128 0x10 - 749 02f4 88000000 .4byte .LVL40 - 750 02f8 A8030000 .4byte 0x3a8 - 751 02fc 06 .uleb128 0x6 - 752 02fd 9A000000 .4byte .LVL41 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 19 - - - 753 0301 F0030000 .4byte 0x3f0 - 754 0305 07 .uleb128 0x7 - 755 0306 01 .byte 0x1 - 756 0307 52 .byte 0x52 - 757 0308 15 .byte 0x15 - 758 0309 77 .byte 0x77 - 759 030a 00 .sleb128 0 - 760 030b 12 .byte 0x12 - 761 030c 40 .byte 0x40 - 762 030d 4B .byte 0x4b - 763 030e 24 .byte 0x24 - 764 030f 22 .byte 0x22 - 765 0310 08 .byte 0x8 - 766 0311 40 .byte 0x40 - 767 0312 16 .byte 0x16 - 768 0313 14 .byte 0x14 - 769 0314 40 .byte 0x40 - 770 0315 4B .byte 0x4b - 771 0316 24 .byte 0x24 - 772 0317 22 .byte 0x22 - 773 0318 2D .byte 0x2d - 774 0319 28 .byte 0x28 - 775 031a 0100 .2byte 0x1 - 776 031c 16 .byte 0x16 - 777 031d 13 .byte 0x13 - 778 031e 07 .uleb128 0x7 - 779 031f 01 .byte 0x1 - 780 0320 51 .byte 0x51 - 781 0321 02 .byte 0x2 - 782 0322 78 .byte 0x78 - 783 0323 00 .sleb128 0 - 784 0324 00 .byte 0 - 785 0325 00 .byte 0 - 786 0326 11 .uleb128 0x11 - 787 0327 4A020000 .4byte .LASF28 - 788 032b 01 .byte 0x1 - 789 032c 26 .byte 0x26 - 790 032d 7A000000 .4byte 0x7a - 791 0331 05 .byte 0x5 - 792 0332 03 .byte 0x3 - 793 0333 02000000 .4byte USBFS_universalTime - 794 0337 11 .uleb128 0x11 - 795 0338 3C020000 .4byte .LASF29 - 796 033c 01 .byte 0x1 - 797 033d 27 .byte 0x27 - 798 033e 6F000000 .4byte 0x6f - 799 0342 05 .byte 0x5 - 800 0343 03 .byte 0x3 - 801 0344 00000000 .4byte USBFS_started - 802 0348 12 .uleb128 0x12 - 803 0349 01 .byte 0x1 - 804 034a 40000000 .4byte .LASF30 - 805 034e 03 .byte 0x3 - 806 034f BF .byte 0xbf - 807 0350 01 .byte 0x1 - 808 0351 01 .byte 0x1 - 809 0352 61030000 .4byte 0x361 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 20 - - - 810 0356 13 .uleb128 0x13 - 811 0357 6F000000 .4byte 0x6f - 812 035b 13 .uleb128 0x13 - 813 035c 6F000000 .4byte 0x6f - 814 0360 00 .byte 0 - 815 0361 14 .uleb128 0x14 - 816 0362 01 .byte 0x1 - 817 0363 6F000000 .4byte .LASF40 - 818 0367 03 .byte 0x3 - 819 0368 C2 .byte 0xc2 - 820 0369 01 .byte 0x1 - 821 036a 01 .byte 0x1 - 822 036b 12 .uleb128 0x12 - 823 036c 01 .byte 0x1 - 824 036d 4D010000 .4byte .LASF31 - 825 0371 03 .byte 0x3 - 826 0372 CE .byte 0xce - 827 0373 01 .byte 0x1 - 828 0374 01 .byte 0x1 - 829 0375 7F030000 .4byte 0x37f - 830 0379 13 .uleb128 0x13 - 831 037a 6F000000 .4byte 0x6f - 832 037e 00 .byte 0 - 833 037f 12 .uleb128 0x12 - 834 0380 01 .byte 0x1 - 835 0381 9E010000 .4byte .LASF32 - 836 0385 03 .byte 0x3 - 837 0386 CA .byte 0xca - 838 0387 01 .byte 0x1 - 839 0388 01 .byte 0x1 - 840 0389 9D030000 .4byte 0x39d - 841 038d 13 .uleb128 0x13 - 842 038e 6F000000 .4byte 0x6f - 843 0392 13 .uleb128 0x13 - 844 0393 9D030000 .4byte 0x39d - 845 0397 13 .uleb128 0x13 - 846 0398 7A000000 .4byte 0x7a - 847 039c 00 .byte 0 - 848 039d 0F .uleb128 0xf - 849 039e 04 .byte 0x4 - 850 039f A3030000 .4byte 0x3a3 - 851 03a3 15 .uleb128 0x15 - 852 03a4 6F000000 .4byte 0x6f - 853 03a8 16 .uleb128 0x16 - 854 03a9 01 .byte 0x1 - 855 03aa 00020000 .4byte .LASF41 - 856 03ae 03 .byte 0x3 - 857 03af C8 .byte 0xc8 - 858 03b0 01 .byte 0x1 - 859 03b1 6F000000 .4byte 0x6f - 860 03b5 01 .byte 0x1 - 861 03b6 C0030000 .4byte 0x3c0 - 862 03ba 13 .uleb128 0x13 - 863 03bb 6F000000 .4byte 0x6f - 864 03bf 00 .byte 0 - 865 03c0 12 .uleb128 0x12 - 866 03c1 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 21 - - - 867 03c2 5E020000 .4byte .LASF33 - 868 03c6 04 .byte 0x4 - 869 03c7 77 .byte 0x77 - 870 03c8 01 .byte 0x1 - 871 03c9 01 .byte 0x1 - 872 03ca D4030000 .4byte 0x3d4 - 873 03ce 13 .uleb128 0x13 - 874 03cf 85000000 .4byte 0x85 - 875 03d3 00 .byte 0 - 876 03d4 17 .uleb128 0x17 - 877 03d5 01 .byte 0x1 - 878 03d6 12010000 .4byte .LASF34 - 879 03da 03 .byte 0x3 - 880 03db C4 .byte 0xc4 - 881 03dc 01 .byte 0x1 - 882 03dd 6F000000 .4byte 0x6f - 883 03e1 01 .byte 0x1 - 884 03e2 17 .uleb128 0x17 - 885 03e3 01 .byte 0x1 - 886 03e4 8C020000 .4byte .LASF35 - 887 03e8 03 .byte 0x3 - 888 03e9 C5 .byte 0xc5 - 889 03ea 01 .byte 0x1 - 890 03eb 6F000000 .4byte 0x6f - 891 03ef 01 .byte 0x1 - 892 03f0 18 .uleb128 0x18 - 893 03f1 01 .byte 0x1 - 894 03f2 DD000000 .4byte .LASF36 - 895 03f6 03 .byte 0x3 - 896 03f7 CC .byte 0xcc - 897 03f8 01 .byte 0x1 - 898 03f9 7A000000 .4byte 0x7a - 899 03fd 01 .byte 0x1 - 900 03fe 13 .uleb128 0x13 - 901 03ff 6F000000 .4byte 0x6f - 902 0403 13 .uleb128 0x13 - 903 0404 01020000 .4byte 0x201 - 904 0408 13 .uleb128 0x13 - 905 0409 7A000000 .4byte 0x7a - 906 040d 00 .byte 0 - 907 040e 00 .byte 0 - 908 .section .debug_abbrev,"",%progbits - 909 .Ldebug_abbrev0: - 910 0000 01 .uleb128 0x1 - 911 0001 11 .uleb128 0x11 - 912 0002 01 .byte 0x1 - 913 0003 25 .uleb128 0x25 - 914 0004 0E .uleb128 0xe - 915 0005 13 .uleb128 0x13 - 916 0006 0B .uleb128 0xb - 917 0007 03 .uleb128 0x3 - 918 0008 0E .uleb128 0xe - 919 0009 1B .uleb128 0x1b - 920 000a 0E .uleb128 0xe - 921 000b 55 .uleb128 0x55 - 922 000c 06 .uleb128 0x6 - 923 000d 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 22 - - - 924 000e 01 .uleb128 0x1 - 925 000f 52 .uleb128 0x52 - 926 0010 01 .uleb128 0x1 - 927 0011 10 .uleb128 0x10 - 928 0012 06 .uleb128 0x6 - 929 0013 00 .byte 0 - 930 0014 00 .byte 0 - 931 0015 02 .uleb128 0x2 - 932 0016 24 .uleb128 0x24 - 933 0017 00 .byte 0 - 934 0018 0B .uleb128 0xb - 935 0019 0B .uleb128 0xb - 936 001a 3E .uleb128 0x3e - 937 001b 0B .uleb128 0xb - 938 001c 03 .uleb128 0x3 - 939 001d 0E .uleb128 0xe - 940 001e 00 .byte 0 - 941 001f 00 .byte 0 - 942 0020 03 .uleb128 0x3 - 943 0021 24 .uleb128 0x24 - 944 0022 00 .byte 0 - 945 0023 0B .uleb128 0xb - 946 0024 0B .uleb128 0xb - 947 0025 3E .uleb128 0x3e - 948 0026 0B .uleb128 0xb - 949 0027 03 .uleb128 0x3 - 950 0028 08 .uleb128 0x8 - 951 0029 00 .byte 0 - 952 002a 00 .byte 0 - 953 002b 04 .uleb128 0x4 - 954 002c 16 .uleb128 0x16 - 955 002d 00 .byte 0 - 956 002e 03 .uleb128 0x3 - 957 002f 0E .uleb128 0xe - 958 0030 3A .uleb128 0x3a - 959 0031 0B .uleb128 0xb - 960 0032 3B .uleb128 0x3b - 961 0033 0B .uleb128 0xb - 962 0034 49 .uleb128 0x49 - 963 0035 13 .uleb128 0x13 - 964 0036 00 .byte 0 - 965 0037 00 .byte 0 - 966 0038 05 .uleb128 0x5 - 967 0039 2E .uleb128 0x2e - 968 003a 01 .byte 0x1 - 969 003b 3F .uleb128 0x3f - 970 003c 0C .uleb128 0xc - 971 003d 03 .uleb128 0x3 - 972 003e 0E .uleb128 0xe - 973 003f 3A .uleb128 0x3a - 974 0040 0B .uleb128 0xb - 975 0041 3B .uleb128 0x3b - 976 0042 0B .uleb128 0xb - 977 0043 27 .uleb128 0x27 - 978 0044 0C .uleb128 0xc - 979 0045 11 .uleb128 0x11 - 980 0046 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 23 - - - 981 0047 12 .uleb128 0x12 - 982 0048 01 .uleb128 0x1 - 983 0049 40 .uleb128 0x40 - 984 004a 06 .uleb128 0x6 - 985 004b 9742 .uleb128 0x2117 - 986 004d 0C .uleb128 0xc - 987 004e 01 .uleb128 0x1 - 988 004f 13 .uleb128 0x13 - 989 0050 00 .byte 0 - 990 0051 00 .byte 0 - 991 0052 06 .uleb128 0x6 - 992 0053 898201 .uleb128 0x4109 - 993 0056 01 .byte 0x1 - 994 0057 11 .uleb128 0x11 - 995 0058 01 .uleb128 0x1 - 996 0059 31 .uleb128 0x31 - 997 005a 13 .uleb128 0x13 - 998 005b 00 .byte 0 - 999 005c 00 .byte 0 - 1000 005d 07 .uleb128 0x7 - 1001 005e 8A8201 .uleb128 0x410a - 1002 0061 00 .byte 0 - 1003 0062 02 .uleb128 0x2 - 1004 0063 0A .uleb128 0xa - 1005 0064 9142 .uleb128 0x2111 - 1006 0066 0A .uleb128 0xa - 1007 0067 00 .byte 0 - 1008 0068 00 .byte 0 - 1009 0069 08 .uleb128 0x8 - 1010 006a 2E .uleb128 0x2e - 1011 006b 01 .byte 0x1 - 1012 006c 3F .uleb128 0x3f - 1013 006d 0C .uleb128 0xc - 1014 006e 03 .uleb128 0x3 - 1015 006f 0E .uleb128 0xe - 1016 0070 3A .uleb128 0x3a - 1017 0071 0B .uleb128 0xb - 1018 0072 3B .uleb128 0x3b - 1019 0073 0B .uleb128 0xb - 1020 0074 27 .uleb128 0x27 - 1021 0075 0C .uleb128 0xc - 1022 0076 11 .uleb128 0x11 - 1023 0077 01 .uleb128 0x1 - 1024 0078 12 .uleb128 0x12 - 1025 0079 01 .uleb128 0x1 - 1026 007a 40 .uleb128 0x40 - 1027 007b 0A .uleb128 0xa - 1028 007c 9742 .uleb128 0x2117 - 1029 007e 0C .uleb128 0xc - 1030 007f 01 .uleb128 0x1 - 1031 0080 13 .uleb128 0x13 - 1032 0081 00 .byte 0 - 1033 0082 00 .byte 0 - 1034 0083 09 .uleb128 0x9 - 1035 0084 898201 .uleb128 0x4109 - 1036 0087 00 .byte 0 - 1037 0088 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 24 - - - 1038 0089 01 .uleb128 0x1 - 1039 008a 9542 .uleb128 0x2115 - 1040 008c 0C .uleb128 0xc - 1041 008d 31 .uleb128 0x31 - 1042 008e 13 .uleb128 0x13 - 1043 008f 00 .byte 0 - 1044 0090 00 .byte 0 - 1045 0091 0A .uleb128 0xa - 1046 0092 898201 .uleb128 0x4109 - 1047 0095 01 .byte 0x1 - 1048 0096 11 .uleb128 0x11 - 1049 0097 01 .uleb128 0x1 - 1050 0098 9542 .uleb128 0x2115 - 1051 009a 0C .uleb128 0xc - 1052 009b 31 .uleb128 0x31 - 1053 009c 13 .uleb128 0x13 - 1054 009d 00 .byte 0 - 1055 009e 00 .byte 0 - 1056 009f 0B .uleb128 0xb - 1057 00a0 2E .uleb128 0x2e - 1058 00a1 01 .byte 0x1 - 1059 00a2 3F .uleb128 0x3f - 1060 00a3 0C .uleb128 0xc - 1061 00a4 03 .uleb128 0x3 - 1062 00a5 0E .uleb128 0xe - 1063 00a6 3A .uleb128 0x3a - 1064 00a7 0B .uleb128 0xb - 1065 00a8 3B .uleb128 0x3b - 1066 00a9 0B .uleb128 0xb - 1067 00aa 27 .uleb128 0x27 - 1068 00ab 0C .uleb128 0xc - 1069 00ac 49 .uleb128 0x49 - 1070 00ad 13 .uleb128 0x13 - 1071 00ae 11 .uleb128 0x11 - 1072 00af 01 .uleb128 0x1 - 1073 00b0 12 .uleb128 0x12 - 1074 00b1 01 .uleb128 0x1 - 1075 00b2 40 .uleb128 0x40 - 1076 00b3 06 .uleb128 0x6 - 1077 00b4 9742 .uleb128 0x2117 - 1078 00b6 0C .uleb128 0xc - 1079 00b7 01 .uleb128 0x1 - 1080 00b8 13 .uleb128 0x13 - 1081 00b9 00 .byte 0 - 1082 00ba 00 .byte 0 - 1083 00bb 0C .uleb128 0xc - 1084 00bc 05 .uleb128 0x5 - 1085 00bd 00 .byte 0 - 1086 00be 03 .uleb128 0x3 - 1087 00bf 0E .uleb128 0xe - 1088 00c0 3A .uleb128 0x3a - 1089 00c1 0B .uleb128 0xb - 1090 00c2 3B .uleb128 0x3b - 1091 00c3 0B .uleb128 0xb - 1092 00c4 49 .uleb128 0x49 - 1093 00c5 13 .uleb128 0x13 - 1094 00c6 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 25 - - - 1095 00c7 06 .uleb128 0x6 - 1096 00c8 00 .byte 0 - 1097 00c9 00 .byte 0 - 1098 00ca 0D .uleb128 0xd - 1099 00cb 34 .uleb128 0x34 - 1100 00cc 00 .byte 0 - 1101 00cd 03 .uleb128 0x3 - 1102 00ce 0E .uleb128 0xe - 1103 00cf 3A .uleb128 0x3a - 1104 00d0 0B .uleb128 0xb - 1105 00d1 3B .uleb128 0x3b - 1106 00d2 0B .uleb128 0xb - 1107 00d3 49 .uleb128 0x49 - 1108 00d4 13 .uleb128 0x13 - 1109 00d5 02 .uleb128 0x2 - 1110 00d6 06 .uleb128 0x6 - 1111 00d7 00 .byte 0 - 1112 00d8 00 .byte 0 - 1113 00d9 0E .uleb128 0xe - 1114 00da 898201 .uleb128 0x4109 - 1115 00dd 01 .byte 0x1 - 1116 00de 11 .uleb128 0x11 - 1117 00df 01 .uleb128 0x1 - 1118 00e0 31 .uleb128 0x31 - 1119 00e1 13 .uleb128 0x13 - 1120 00e2 01 .uleb128 0x1 - 1121 00e3 13 .uleb128 0x13 - 1122 00e4 00 .byte 0 - 1123 00e5 00 .byte 0 - 1124 00e6 0F .uleb128 0xf - 1125 00e7 0F .uleb128 0xf - 1126 00e8 00 .byte 0 - 1127 00e9 0B .uleb128 0xb - 1128 00ea 0B .uleb128 0xb - 1129 00eb 49 .uleb128 0x49 - 1130 00ec 13 .uleb128 0x13 - 1131 00ed 00 .byte 0 - 1132 00ee 00 .byte 0 - 1133 00ef 10 .uleb128 0x10 - 1134 00f0 898201 .uleb128 0x4109 - 1135 00f3 00 .byte 0 - 1136 00f4 11 .uleb128 0x11 - 1137 00f5 01 .uleb128 0x1 - 1138 00f6 31 .uleb128 0x31 - 1139 00f7 13 .uleb128 0x13 - 1140 00f8 00 .byte 0 - 1141 00f9 00 .byte 0 - 1142 00fa 11 .uleb128 0x11 - 1143 00fb 34 .uleb128 0x34 - 1144 00fc 00 .byte 0 - 1145 00fd 03 .uleb128 0x3 - 1146 00fe 0E .uleb128 0xe - 1147 00ff 3A .uleb128 0x3a - 1148 0100 0B .uleb128 0xb - 1149 0101 3B .uleb128 0x3b - 1150 0102 0B .uleb128 0xb - 1151 0103 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 26 - - - 1152 0104 13 .uleb128 0x13 - 1153 0105 02 .uleb128 0x2 - 1154 0106 0A .uleb128 0xa - 1155 0107 00 .byte 0 - 1156 0108 00 .byte 0 - 1157 0109 12 .uleb128 0x12 - 1158 010a 2E .uleb128 0x2e - 1159 010b 01 .byte 0x1 - 1160 010c 3F .uleb128 0x3f - 1161 010d 0C .uleb128 0xc - 1162 010e 03 .uleb128 0x3 - 1163 010f 0E .uleb128 0xe - 1164 0110 3A .uleb128 0x3a - 1165 0111 0B .uleb128 0xb - 1166 0112 3B .uleb128 0x3b - 1167 0113 0B .uleb128 0xb - 1168 0114 27 .uleb128 0x27 - 1169 0115 0C .uleb128 0xc - 1170 0116 3C .uleb128 0x3c - 1171 0117 0C .uleb128 0xc - 1172 0118 01 .uleb128 0x1 - 1173 0119 13 .uleb128 0x13 - 1174 011a 00 .byte 0 - 1175 011b 00 .byte 0 - 1176 011c 13 .uleb128 0x13 - 1177 011d 05 .uleb128 0x5 - 1178 011e 00 .byte 0 - 1179 011f 49 .uleb128 0x49 - 1180 0120 13 .uleb128 0x13 - 1181 0121 00 .byte 0 - 1182 0122 00 .byte 0 - 1183 0123 14 .uleb128 0x14 - 1184 0124 2E .uleb128 0x2e - 1185 0125 00 .byte 0 - 1186 0126 3F .uleb128 0x3f - 1187 0127 0C .uleb128 0xc - 1188 0128 03 .uleb128 0x3 - 1189 0129 0E .uleb128 0xe - 1190 012a 3A .uleb128 0x3a - 1191 012b 0B .uleb128 0xb - 1192 012c 3B .uleb128 0x3b - 1193 012d 0B .uleb128 0xb - 1194 012e 27 .uleb128 0x27 - 1195 012f 0C .uleb128 0xc - 1196 0130 3C .uleb128 0x3c - 1197 0131 0C .uleb128 0xc - 1198 0132 00 .byte 0 - 1199 0133 00 .byte 0 - 1200 0134 15 .uleb128 0x15 - 1201 0135 26 .uleb128 0x26 - 1202 0136 00 .byte 0 - 1203 0137 49 .uleb128 0x49 - 1204 0138 13 .uleb128 0x13 - 1205 0139 00 .byte 0 - 1206 013a 00 .byte 0 - 1207 013b 16 .uleb128 0x16 - 1208 013c 2E .uleb128 0x2e - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 27 - - - 1209 013d 01 .byte 0x1 - 1210 013e 3F .uleb128 0x3f - 1211 013f 0C .uleb128 0xc - 1212 0140 03 .uleb128 0x3 - 1213 0141 0E .uleb128 0xe - 1214 0142 3A .uleb128 0x3a - 1215 0143 0B .uleb128 0xb - 1216 0144 3B .uleb128 0x3b - 1217 0145 0B .uleb128 0xb - 1218 0146 27 .uleb128 0x27 - 1219 0147 0C .uleb128 0xc - 1220 0148 49 .uleb128 0x49 - 1221 0149 13 .uleb128 0x13 - 1222 014a 3C .uleb128 0x3c - 1223 014b 0C .uleb128 0xc - 1224 014c 01 .uleb128 0x1 - 1225 014d 13 .uleb128 0x13 - 1226 014e 00 .byte 0 - 1227 014f 00 .byte 0 - 1228 0150 17 .uleb128 0x17 - 1229 0151 2E .uleb128 0x2e - 1230 0152 00 .byte 0 - 1231 0153 3F .uleb128 0x3f - 1232 0154 0C .uleb128 0xc - 1233 0155 03 .uleb128 0x3 - 1234 0156 0E .uleb128 0xe - 1235 0157 3A .uleb128 0x3a - 1236 0158 0B .uleb128 0xb - 1237 0159 3B .uleb128 0x3b - 1238 015a 0B .uleb128 0xb - 1239 015b 27 .uleb128 0x27 - 1240 015c 0C .uleb128 0xc - 1241 015d 49 .uleb128 0x49 - 1242 015e 13 .uleb128 0x13 - 1243 015f 3C .uleb128 0x3c - 1244 0160 0C .uleb128 0xc - 1245 0161 00 .byte 0 - 1246 0162 00 .byte 0 - 1247 0163 18 .uleb128 0x18 - 1248 0164 2E .uleb128 0x2e - 1249 0165 01 .byte 0x1 - 1250 0166 3F .uleb128 0x3f - 1251 0167 0C .uleb128 0xc - 1252 0168 03 .uleb128 0x3 - 1253 0169 0E .uleb128 0xe - 1254 016a 3A .uleb128 0x3a - 1255 016b 0B .uleb128 0xb - 1256 016c 3B .uleb128 0x3b - 1257 016d 0B .uleb128 0xb - 1258 016e 27 .uleb128 0x27 - 1259 016f 0C .uleb128 0xc - 1260 0170 49 .uleb128 0x49 - 1261 0171 13 .uleb128 0x13 - 1262 0172 3C .uleb128 0x3c - 1263 0173 0C .uleb128 0xc - 1264 0174 00 .byte 0 - 1265 0175 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 28 - - - 1266 0176 00 .byte 0 - 1267 .section .debug_loc,"",%progbits - 1268 .Ldebug_loc0: - 1269 .LLST0: - 1270 0000 00000000 .4byte .LFB0 - 1271 0004 02000000 .4byte .LCFI0 - 1272 0008 0200 .2byte 0x2 - 1273 000a 7D .byte 0x7d - 1274 000b 00 .sleb128 0 - 1275 000c 02000000 .4byte .LCFI0 - 1276 0010 18000000 .4byte .LFE0 - 1277 0014 0200 .2byte 0x2 - 1278 0016 7D .byte 0x7d - 1279 0017 08 .sleb128 8 - 1280 0018 00000000 .4byte 0 - 1281 001c 00000000 .4byte 0 - 1282 .LLST1: - 1283 0020 00000000 .4byte .LFB3 - 1284 0024 02000000 .4byte .LCFI1 - 1285 0028 0200 .2byte 0x2 - 1286 002a 7D .byte 0x7d - 1287 002b 00 .sleb128 0 - 1288 002c 02000000 .4byte .LCFI1 - 1289 0030 54000000 .4byte .LFE3 - 1290 0034 0200 .2byte 0x2 - 1291 0036 7D .byte 0x7d - 1292 0037 18 .sleb128 24 - 1293 0038 00000000 .4byte 0 - 1294 003c 00000000 .4byte 0 - 1295 .LLST2: - 1296 0040 00000000 .4byte .LVL3 - 1297 0044 08000000 .4byte .LVL4 - 1298 0048 0100 .2byte 0x1 - 1299 004a 50 .byte 0x50 - 1300 004b 08000000 .4byte .LVL4 - 1301 004f 1E000000 .4byte .LVL9 - 1302 0053 0100 .2byte 0x1 - 1303 0055 57 .byte 0x57 - 1304 0056 1E000000 .4byte .LVL9 - 1305 005a 54000000 .4byte .LFE3 - 1306 005e 0400 .2byte 0x4 - 1307 0060 F3 .byte 0xf3 - 1308 0061 01 .uleb128 0x1 - 1309 0062 50 .byte 0x50 - 1310 0063 9F .byte 0x9f - 1311 0064 00000000 .4byte 0 - 1312 0068 00000000 .4byte 0 - 1313 .LLST3: - 1314 006c 00000000 .4byte .LVL3 - 1315 0070 0C000000 .4byte .LVL5 - 1316 0074 0100 .2byte 0x1 - 1317 0076 51 .byte 0x51 - 1318 0077 0C000000 .4byte .LVL5 - 1319 007b 54000000 .4byte .LFE3 - 1320 007f 0400 .2byte 0x4 - 1321 0081 F3 .byte 0xf3 - 1322 0082 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 29 - - - 1323 0083 51 .byte 0x51 - 1324 0084 9F .byte 0x9f - 1325 0085 00000000 .4byte 0 - 1326 0089 00000000 .4byte 0 - 1327 .LLST4: - 1328 008d 00000000 .4byte .LVL3 - 1329 0091 0E000000 .4byte .LVL6 - 1330 0095 0100 .2byte 0x1 - 1331 0097 52 .byte 0x52 - 1332 0098 0E000000 .4byte .LVL6 - 1333 009c 54000000 .4byte .LFE3 - 1334 00a0 0100 .2byte 0x1 - 1335 00a2 55 .byte 0x55 - 1336 00a3 00000000 .4byte 0 - 1337 00a7 00000000 .4byte 0 - 1338 .LLST5: - 1339 00ab 00000000 .4byte .LVL3 - 1340 00af 13000000 .4byte .LVL7-1 - 1341 00b3 0100 .2byte 0x1 - 1342 00b5 53 .byte 0x53 - 1343 00b6 13000000 .4byte .LVL7-1 - 1344 00ba 54000000 .4byte .LFE3 - 1345 00be 0400 .2byte 0x4 - 1346 00c0 F3 .byte 0xf3 - 1347 00c1 01 .uleb128 0x1 - 1348 00c2 53 .byte 0x53 - 1349 00c3 9F .byte 0x9f - 1350 00c4 00000000 .4byte 0 - 1351 00c8 00000000 .4byte 0 - 1352 .LLST6: - 1353 00cc 1C000000 .4byte .LVL8 - 1354 00d0 1E000000 .4byte .LVL9 - 1355 00d4 0200 .2byte 0x2 - 1356 00d6 30 .byte 0x30 - 1357 00d7 9F .byte 0x9f - 1358 00d8 1E000000 .4byte .LVL9 - 1359 00dc 2E000000 .4byte .LVL11 - 1360 00e0 0100 .2byte 0x1 - 1361 00e2 54 .byte 0x54 - 1362 00e3 2E000000 .4byte .LVL11 - 1363 00e7 3C000000 .4byte .LVL13 - 1364 00eb 0100 .2byte 0x1 - 1365 00ed 57 .byte 0x57 - 1366 00ee 00000000 .4byte 0 - 1367 00f2 00000000 .4byte 0 - 1368 .LLST7: - 1369 00f6 46000000 .4byte .LVL15 - 1370 00fa 4A000000 .4byte .LVL16 - 1371 00fe 0200 .2byte 0x2 - 1372 0100 30 .byte 0x30 - 1373 0101 9F .byte 0x9f - 1374 0102 4C000000 .4byte .LVL17 - 1375 0106 54000000 .4byte .LFE3 - 1376 010a 0100 .2byte 0x1 - 1377 010c 50 .byte 0x50 - 1378 010d 00000000 .4byte 0 - 1379 0111 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 30 - - - 1380 .LLST8: - 1381 0115 00000000 .4byte .LFB4 - 1382 0119 04000000 .4byte .LCFI2 - 1383 011d 0200 .2byte 0x2 - 1384 011f 7D .byte 0x7d - 1385 0120 00 .sleb128 0 - 1386 0121 04000000 .4byte .LCFI2 - 1387 0125 B0000000 .4byte .LFE4 - 1388 0129 0200 .2byte 0x2 - 1389 012b 7D .byte 0x7d - 1390 012c 18 .sleb128 24 - 1391 012d 00000000 .4byte 0 - 1392 0131 00000000 .4byte 0 - 1393 .LLST9: - 1394 0135 00000000 .4byte .LVL18 - 1395 0139 18000000 .4byte .LVL22 - 1396 013d 0100 .2byte 0x1 - 1397 013f 50 .byte 0x50 - 1398 0140 18000000 .4byte .LVL22 - 1399 0144 4C000000 .4byte .LVL30 - 1400 0148 0100 .2byte 0x1 - 1401 014a 58 .byte 0x58 - 1402 014b 4C000000 .4byte .LVL30 - 1403 014f 4F000000 .4byte .LVL31-1 - 1404 0153 0100 .2byte 0x1 - 1405 0155 50 .byte 0x50 - 1406 0156 4F000000 .4byte .LVL31-1 - 1407 015a B0000000 .4byte .LFE4 - 1408 015e 0100 .2byte 0x1 - 1409 0160 58 .byte 0x58 - 1410 0161 00000000 .4byte 0 - 1411 0165 00000000 .4byte 0 - 1412 .LLST10: - 1413 0169 00000000 .4byte .LVL18 - 1414 016d 14000000 .4byte .LVL21 - 1415 0171 0100 .2byte 0x1 - 1416 0173 51 .byte 0x51 - 1417 0174 14000000 .4byte .LVL21 - 1418 0178 18000000 .4byte .LVL22 - 1419 017c 1600 .2byte 0x16 - 1420 017e 71 .byte 0x71 - 1421 017f 00 .sleb128 0 - 1422 0180 12 .byte 0x12 - 1423 0181 0A .byte 0xa - 1424 0182 FFFF .2byte 0xffff - 1425 0184 1A .byte 0x1a - 1426 0185 08 .byte 0x8 - 1427 0186 40 .byte 0x40 - 1428 0187 16 .byte 0x16 - 1429 0188 14 .byte 0x14 - 1430 0189 0A .byte 0xa - 1431 018a FFFF .2byte 0xffff - 1432 018c 1A .byte 0x1a - 1433 018d 2D .byte 0x2d - 1434 018e 28 .byte 0x28 - 1435 018f 0100 .2byte 0x1 - 1436 0191 16 .byte 0x16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 31 - - - 1437 0192 13 .byte 0x13 - 1438 0193 9F .byte 0x9f - 1439 0194 18000000 .4byte .LVL22 - 1440 0198 4C000000 .4byte .LVL30 - 1441 019c 1600 .2byte 0x16 - 1442 019e 77 .byte 0x77 - 1443 019f 00 .sleb128 0 - 1444 01a0 12 .byte 0x12 - 1445 01a1 0A .byte 0xa - 1446 01a2 FFFF .2byte 0xffff - 1447 01a4 1A .byte 0x1a - 1448 01a5 08 .byte 0x8 - 1449 01a6 40 .byte 0x40 - 1450 01a7 16 .byte 0x16 - 1451 01a8 14 .byte 0x14 - 1452 01a9 0A .byte 0xa - 1453 01aa FFFF .2byte 0xffff - 1454 01ac 1A .byte 0x1a - 1455 01ad 2D .byte 0x2d - 1456 01ae 28 .byte 0x28 - 1457 01af 0100 .2byte 0x1 - 1458 01b1 16 .byte 0x16 - 1459 01b2 13 .byte 0x13 - 1460 01b3 9F .byte 0x9f - 1461 01b4 4C000000 .4byte .LVL30 - 1462 01b8 4F000000 .4byte .LVL31-1 - 1463 01bc 1600 .2byte 0x16 - 1464 01be 71 .byte 0x71 - 1465 01bf 00 .sleb128 0 - 1466 01c0 12 .byte 0x12 - 1467 01c1 0A .byte 0xa - 1468 01c2 FFFF .2byte 0xffff - 1469 01c4 1A .byte 0x1a - 1470 01c5 08 .byte 0x8 - 1471 01c6 40 .byte 0x40 - 1472 01c7 16 .byte 0x16 - 1473 01c8 14 .byte 0x14 - 1474 01c9 0A .byte 0xa - 1475 01ca FFFF .2byte 0xffff - 1476 01cc 1A .byte 0x1a - 1477 01cd 2D .byte 0x2d - 1478 01ce 28 .byte 0x28 - 1479 01cf 0100 .2byte 0x1 - 1480 01d1 16 .byte 0x16 - 1481 01d2 13 .byte 0x13 - 1482 01d3 9F .byte 0x9f - 1483 01d4 4F000000 .4byte .LVL31-1 - 1484 01d8 B0000000 .4byte .LFE4 - 1485 01dc 1600 .2byte 0x16 - 1486 01de 77 .byte 0x77 - 1487 01df 00 .sleb128 0 - 1488 01e0 12 .byte 0x12 - 1489 01e1 0A .byte 0xa - 1490 01e2 FFFF .2byte 0xffff - 1491 01e4 1A .byte 0x1a - 1492 01e5 08 .byte 0x8 - 1493 01e6 40 .byte 0x40 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 32 - - - 1494 01e7 16 .byte 0x16 - 1495 01e8 14 .byte 0x14 - 1496 01e9 0A .byte 0xa - 1497 01ea FFFF .2byte 0xffff - 1498 01ec 1A .byte 0x1a - 1499 01ed 2D .byte 0x2d - 1500 01ee 28 .byte 0x28 - 1501 01ef 0100 .2byte 0x1 - 1502 01f1 16 .byte 0x16 - 1503 01f2 13 .byte 0x13 - 1504 01f3 9F .byte 0x9f - 1505 01f4 00000000 .4byte 0 - 1506 01f8 00000000 .4byte 0 - 1507 .LLST11: - 1508 01fc 00000000 .4byte .LVL18 - 1509 0200 08000000 .4byte .LVL19 - 1510 0204 0100 .2byte 0x1 - 1511 0206 52 .byte 0x52 - 1512 0207 08000000 .4byte .LVL19 - 1513 020b B0000000 .4byte .LFE4 - 1514 020f 0100 .2byte 0x1 - 1515 0211 55 .byte 0x55 - 1516 0212 00000000 .4byte 0 - 1517 0216 00000000 .4byte 0 - 1518 .LLST12: - 1519 021a 00000000 .4byte .LVL18 - 1520 021e 0A000000 .4byte .LVL20 - 1521 0222 0100 .2byte 0x1 - 1522 0224 53 .byte 0x53 - 1523 0225 0A000000 .4byte .LVL20 - 1524 0229 B0000000 .4byte .LFE4 - 1525 022d 0400 .2byte 0x4 - 1526 022f F3 .byte 0xf3 - 1527 0230 01 .uleb128 0x1 - 1528 0231 53 .byte 0x53 - 1529 0232 9F .byte 0x9f - 1530 0233 00000000 .4byte 0 - 1531 0237 00000000 .4byte 0 - 1532 .LLST13: - 1533 023b 9C000000 .4byte .LVL42 - 1534 023f A2000000 .4byte .LVL43 - 1535 0243 0200 .2byte 0x2 - 1536 0245 30 .byte 0x30 - 1537 0246 9F .byte 0x9f - 1538 0247 A6000000 .4byte .LVL44 - 1539 024b A8000000 .4byte .LVL45 - 1540 024f 0200 .2byte 0x2 - 1541 0251 40 .byte 0x40 - 1542 0252 9F .byte 0x9f - 1543 0253 A8000000 .4byte .LVL45 - 1544 0257 B0000000 .4byte .LFE4 - 1545 025b 0100 .2byte 0x1 - 1546 025d 50 .byte 0x50 - 1547 025e 00000000 .4byte 0 - 1548 0262 00000000 .4byte 0 - 1549 .LLST14: - 1550 0266 14000000 .4byte .LVL21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 33 - - - 1551 026a 18000000 .4byte .LVL22 - 1552 026e 0200 .2byte 0x2 - 1553 0270 30 .byte 0x30 - 1554 0271 9F .byte 0x9f - 1555 0272 18000000 .4byte .LVL22 - 1556 0276 26000000 .4byte .LVL24 - 1557 027a 0100 .2byte 0x1 - 1558 027c 54 .byte 0x54 - 1559 027d 26000000 .4byte .LVL24 - 1560 0281 36000000 .4byte .LVL26 - 1561 0285 0100 .2byte 0x1 - 1562 0287 56 .byte 0x56 - 1563 0288 36000000 .4byte .LVL26 - 1564 028c 4C000000 .4byte .LVL30 - 1565 0290 0100 .2byte 0x1 - 1566 0292 54 .byte 0x54 - 1567 0293 4C000000 .4byte .LVL30 - 1568 0297 64000000 .4byte .LVL34 - 1569 029b 0200 .2byte 0x2 - 1570 029d 30 .byte 0x30 - 1571 029e 9F .byte 0x9f - 1572 029f 64000000 .4byte .LVL34 - 1573 02a3 6C000000 .4byte .LVL35 - 1574 02a7 0100 .2byte 0x1 - 1575 02a9 54 .byte 0x54 - 1576 02aa 6C000000 .4byte .LVL35 - 1577 02ae 76000000 .4byte .LVL37 - 1578 02b2 0100 .2byte 0x1 - 1579 02b4 56 .byte 0x56 - 1580 02b5 76000000 .4byte .LVL37 - 1581 02b9 84000000 .4byte .LVL39 - 1582 02bd 0100 .2byte 0x1 - 1583 02bf 54 .byte 0x54 - 1584 02c0 00000000 .4byte 0 - 1585 02c4 00000000 .4byte 0 - 1586 .section .debug_aranges,"",%progbits - 1587 0000 3C000000 .4byte 0x3c - 1588 0004 0200 .2byte 0x2 - 1589 0006 00000000 .4byte .Ldebug_info0 - 1590 000a 04 .byte 0x4 - 1591 000b 00 .byte 0 - 1592 000c 0000 .2byte 0 - 1593 000e 0000 .2byte 0 - 1594 0010 00000000 .4byte .LFB0 - 1595 0014 18000000 .4byte .LFE0-.LFB0 - 1596 0018 00000000 .4byte .LFB1 - 1597 001c 04000000 .4byte .LFE1-.LFB1 - 1598 0020 00000000 .4byte .LFB2 - 1599 0024 06000000 .4byte .LFE2-.LFB2 - 1600 0028 00000000 .4byte .LFB3 - 1601 002c 54000000 .4byte .LFE3-.LFB3 - 1602 0030 00000000 .4byte .LFB4 - 1603 0034 B0000000 .4byte .LFE4-.LFB4 - 1604 0038 00000000 .4byte 0 - 1605 003c 00000000 .4byte 0 - 1606 .section .debug_ranges,"",%progbits - 1607 .Ldebug_ranges0: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 34 - - - 1608 0000 00000000 .4byte .LFB0 - 1609 0004 18000000 .4byte .LFE0 - 1610 0008 00000000 .4byte .LFB1 - 1611 000c 04000000 .4byte .LFE1 - 1612 0010 00000000 .4byte .LFB2 - 1613 0014 06000000 .4byte .LFE2 - 1614 0018 00000000 .4byte .LFB3 - 1615 001c 54000000 .4byte .LFE3 - 1616 0020 00000000 .4byte .LFB4 - 1617 0024 B0000000 .4byte .LFE4 - 1618 0028 00000000 .4byte 0 - 1619 002c 00000000 .4byte 0 - 1620 .section .debug_line,"",%progbits - 1621 .Ldebug_line0: - 1622 0000 47010000 .section .debug_str,"MS",%progbits,1 - 1622 02005F00 - 1622 00000201 - 1622 FB0E0D00 - 1622 01010101 - 1623 .LASF15: - 1624 0000 63797374 .ascii "cystatus\000" - 1624 61747573 - 1624 00 - 1625 .LASF25: - 1626 0009 73746174 .ascii "status\000" - 1626 757300 - 1627 .LASF22: - 1628 0010 636F756E .ascii "count\000" - 1628 7400 - 1629 .LASF3: - 1630 0016 73686F72 .ascii "short unsigned int\000" - 1630 7420756E - 1630 7369676E - 1630 65642069 - 1630 6E7400 - 1631 .LASF19: - 1632 0029 55534246 .ascii "USBFS_CyBtldrCommReset\000" - 1632 535F4379 - 1632 42746C64 - 1632 72436F6D - 1632 6D526573 - 1633 .LASF30: - 1634 0040 55534246 .ascii "USBFS_Start\000" - 1634 535F5374 - 1634 61727400 - 1635 .LASF20: - 1636 004c 70446174 .ascii "pData\000" - 1636 6100 - 1637 .LASF17: - 1638 0052 55534246 .ascii "USBFS_CyBtldrCommStart\000" - 1638 535F4379 - 1638 42746C64 - 1638 72436F6D - 1638 6D537461 - 1639 .LASF12: - 1640 0069 666C6F61 .ascii "float\000" - 1640 7400 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 35 - - - 1641 .LASF40: - 1642 006f 55534246 .ascii "USBFS_Stop\000" - 1642 535F5374 - 1642 6F7000 - 1643 .LASF21: - 1644 007a 73697A65 .ascii "size\000" - 1644 00 - 1645 .LASF5: - 1646 007f 6C6F6E67 .ascii "long unsigned int\000" - 1646 20756E73 - 1646 69676E65 - 1646 6420696E - 1646 7400 - 1647 .LASF39: - 1648 0091 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 1648 43534932 - 1648 53445C73 - 1648 6F667477 - 1648 6172655C - 1649 00c0 6E00 .ascii "n\000" - 1650 .LASF9: - 1651 00c2 75696E74 .ascii "uint8\000" - 1651 3800 - 1652 .LASF1: - 1653 00c8 756E7369 .ascii "unsigned char\000" - 1653 676E6564 - 1653 20636861 - 1653 7200 - 1654 .LASF13: - 1655 00d6 646F7562 .ascii "double\000" - 1655 6C6500 - 1656 .LASF36: - 1657 00dd 55534246 .ascii "USBFS_ReadOutEP\000" - 1657 535F5265 - 1657 61644F75 - 1657 74455000 - 1658 .LASF26: - 1659 00ed 55534246 .ascii "USBFS_CyBtldrCommWrite\000" - 1659 535F4379 - 1659 42746C64 - 1659 72436F6D - 1659 6D577269 - 1660 .LASF10: - 1661 0104 75696E74 .ascii "uint16\000" - 1661 313600 - 1662 .LASF11: - 1663 010b 75696E74 .ascii "uint32\000" - 1663 333200 - 1664 .LASF34: - 1665 0112 55534246 .ascii "USBFS_GetConfiguration\000" - 1665 535F4765 - 1665 74436F6E - 1665 66696775 - 1665 72617469 - 1666 .LASF8: - 1667 0129 756E7369 .ascii "unsigned int\000" - 1667 676E6564 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 36 - - - 1667 20696E74 - 1667 00 - 1668 .LASF7: - 1669 0136 6C6F6E67 .ascii "long long unsigned int\000" - 1669 206C6F6E - 1669 6720756E - 1669 7369676E - 1669 65642069 - 1670 .LASF31: - 1671 014d 55534246 .ascii "USBFS_EnableOutEP\000" - 1671 535F456E - 1671 61626C65 - 1671 4F757445 - 1671 5000 - 1672 .LASF27: - 1673 015f 55534246 .ascii "USBFS_CyBtldrCommRead\000" - 1673 535F4379 - 1673 42746C64 - 1673 72436F6D - 1673 6D526561 - 1674 .LASF23: - 1675 0175 74696D65 .ascii "timeOut\000" - 1675 4F757400 - 1676 .LASF24: - 1677 017d 74696D65 .ascii "time\000" - 1677 00 - 1678 .LASF16: - 1679 0182 73697A65 .ascii "sizetype\000" - 1679 74797065 - 1679 00 - 1680 .LASF6: - 1681 018b 6C6F6E67 .ascii "long long int\000" - 1681 206C6F6E - 1681 6720696E - 1681 7400 - 1682 .LASF14: - 1683 0199 63686172 .ascii "char\000" - 1683 00 - 1684 .LASF32: - 1685 019e 55534246 .ascii "USBFS_LoadInEP\000" - 1685 535F4C6F - 1685 6164496E - 1685 455000 - 1686 .LASF2: - 1687 01ad 73686F72 .ascii "short int\000" - 1687 7420696E - 1687 7400 - 1688 .LASF37: - 1689 01b7 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 1689 4320342E - 1689 372E3320 - 1689 32303133 - 1689 30333132 - 1690 01ea 616E6368 .ascii "anch revision 196615]\000" - 1690 20726576 - 1690 6973696F - 1690 6E203139 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc8co29w.s page 37 - - - 1690 36363135 - 1691 .LASF41: - 1692 0200 55534246 .ascii "USBFS_GetEPState\000" - 1692 535F4765 - 1692 74455053 - 1692 74617465 - 1692 00 - 1693 .LASF4: - 1694 0211 6C6F6E67 .ascii "long int\000" - 1694 20696E74 - 1694 00 - 1695 .LASF18: - 1696 021a 55534246 .ascii "USBFS_CyBtldrCommStop\000" - 1696 535F4379 - 1696 42746C64 - 1696 72436F6D - 1696 6D53746F - 1697 .LASF0: - 1698 0230 7369676E .ascii "signed char\000" - 1698 65642063 - 1698 68617200 - 1699 .LASF29: - 1700 023c 55534246 .ascii "USBFS_started\000" - 1700 535F7374 - 1700 61727465 - 1700 6400 - 1701 .LASF28: - 1702 024a 55534246 .ascii "USBFS_universalTime\000" - 1702 535F756E - 1702 69766572 - 1702 73616C54 - 1702 696D6500 - 1703 .LASF33: - 1704 025e 43794465 .ascii "CyDelay\000" - 1704 6C617900 - 1705 .LASF38: - 1706 0266 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_boot.c\000" - 1706 6E657261 - 1706 7465645F - 1706 536F7572 - 1706 63655C50 - 1707 .LASF35: - 1708 028c 55534246 .ascii "USBFS_IsConfigurationChanged\000" - 1708 535F4973 - 1708 436F6E66 - 1708 69677572 - 1708 6174696F - 1709 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_boot.o deleted file mode 100755 index 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zmR@IiC5TVX$obP>UT1WBZGS$Yu{cvF$^CbagJ2HLePCn9lixx_u}!L=;aXHs1gQT`JS@BWsvU~+dmrY8tfSy8034wc~1@M_257E9^u{b)c^nh diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst deleted file mode 100755 index 338358c..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.lst +++ /dev/null @@ -1,943 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "USBFS_cls.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.USBFS_DispatchClassRqst,"ax",%progbits - 19 .align 1 - 20 .global USBFS_DispatchClassRqst - 21 .thumb - 22 .thumb_func - 23 .type USBFS_DispatchClassRqst, %function - 24 USBFS_DispatchClassRqst: - 25 .LFB0: - 26 .file 1 ".\\Generated_Source\\PSoC5\\USBFS_cls.c" - 1:.\Generated_Source\PSoC5/USBFS_cls.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/USBFS_cls.c **** * File Name: USBFS_cls.c - 3:.\Generated_Source\PSoC5/USBFS_cls.c **** * Version 2.60 - 4:.\Generated_Source\PSoC5/USBFS_cls.c **** * - 5:.\Generated_Source\PSoC5/USBFS_cls.c **** * Description: - 6:.\Generated_Source\PSoC5/USBFS_cls.c **** * USB Class request handler. - 7:.\Generated_Source\PSoC5/USBFS_cls.c **** * - 8:.\Generated_Source\PSoC5/USBFS_cls.c **** * Note: - 9:.\Generated_Source\PSoC5/USBFS_cls.c **** * - 10:.\Generated_Source\PSoC5/USBFS_cls.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/USBFS_cls.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/USBFS_cls.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/USBFS_cls.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/USBFS_cls.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/USBFS_cls.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/USBFS_cls.c **** - 17:.\Generated_Source\PSoC5/USBFS_cls.c **** #include "USBFS.h" - 18:.\Generated_Source\PSoC5/USBFS_cls.c **** - 19:.\Generated_Source\PSoC5/USBFS_cls.c **** #if(USBFS_EXTERN_CLS == USBFS_FALSE) - 20:.\Generated_Source\PSoC5/USBFS_cls.c **** - 21:.\Generated_Source\PSoC5/USBFS_cls.c **** #include "USBFS_pvt.h" - 22:.\Generated_Source\PSoC5/USBFS_cls.c **** - 23:.\Generated_Source\PSoC5/USBFS_cls.c **** - 24:.\Generated_Source\PSoC5/USBFS_cls.c **** /*************************************** - 25:.\Generated_Source\PSoC5/USBFS_cls.c **** * User Implemented Class Driver Declarations. - 26:.\Generated_Source\PSoC5/USBFS_cls.c **** ***************************************/ - 27:.\Generated_Source\PSoC5/USBFS_cls.c **** /* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */ - 28:.\Generated_Source\PSoC5/USBFS_cls.c **** - 29:.\Generated_Source\PSoC5/USBFS_cls.c **** /* `#END` */ - 30:.\Generated_Source\PSoC5/USBFS_cls.c **** - 31:.\Generated_Source\PSoC5/USBFS_cls.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 2 - - - 32:.\Generated_Source\PSoC5/USBFS_cls.c **** /******************************************************************************* - 33:.\Generated_Source\PSoC5/USBFS_cls.c **** * Function Name: USBFS_DispatchClassRqst - 34:.\Generated_Source\PSoC5/USBFS_cls.c **** ******************************************************************************** - 35:.\Generated_Source\PSoC5/USBFS_cls.c **** * Summary: - 36:.\Generated_Source\PSoC5/USBFS_cls.c **** * This routine dispatches class specific requests depend on interface class. - 37:.\Generated_Source\PSoC5/USBFS_cls.c **** * - 38:.\Generated_Source\PSoC5/USBFS_cls.c **** * Parameters: - 39:.\Generated_Source\PSoC5/USBFS_cls.c **** * None. - 40:.\Generated_Source\PSoC5/USBFS_cls.c **** * - 41:.\Generated_Source\PSoC5/USBFS_cls.c **** * Return: - 42:.\Generated_Source\PSoC5/USBFS_cls.c **** * requestHandled. - 43:.\Generated_Source\PSoC5/USBFS_cls.c **** * - 44:.\Generated_Source\PSoC5/USBFS_cls.c **** * Reentrant: - 45:.\Generated_Source\PSoC5/USBFS_cls.c **** * No. - 46:.\Generated_Source\PSoC5/USBFS_cls.c **** * - 47:.\Generated_Source\PSoC5/USBFS_cls.c **** *******************************************************************************/ - 48:.\Generated_Source\PSoC5/USBFS_cls.c **** uint8 USBFS_DispatchClassRqst(void) - 49:.\Generated_Source\PSoC5/USBFS_cls.c **** { - 27 .loc 1 49 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 32 .LVL0: - 50:.\Generated_Source\PSoC5/USBFS_cls.c **** uint8 requestHandled = USBFS_FALSE; - 51:.\Generated_Source\PSoC5/USBFS_cls.c **** uint8 interfaceNumber = 0u; - 52:.\Generated_Source\PSoC5/USBFS_cls.c **** - 53:.\Generated_Source\PSoC5/USBFS_cls.c **** switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - 33 .loc 1 53 0 - 34 0000 0F4B ldr r3, .L11 - 35 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 36 0004 00F00301 and r1, r0, #3 - 37 0008 0129 cmp r1, #1 - 38 000a 0CD0 beq .L3 - 39 000c 0229 cmp r1, #2 - 40 000e 0DD1 bne .L8 - 54:.\Generated_Source\PSoC5/USBFS_cls.c **** { - 55:.\Generated_Source\PSoC5/USBFS_cls.c **** case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */ - 56:.\Generated_Source\PSoC5/USBFS_cls.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */ - 57:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 58:.\Generated_Source\PSoC5/USBFS_cls.c **** case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */ - 59:.\Generated_Source\PSoC5/USBFS_cls.c **** /* Find related interface to the endpoint, wIndexLo contain EP number */ - 60:.\Generated_Source\PSoC5/USBFS_cls.c **** interfaceNumber = - 61:.\Generated_Source\PSoC5/USBFS_cls.c **** USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface; - 41 .loc 1 61 0 - 42 0010 0C4A ldr r2, .L11+4 - 60:.\Generated_Source\PSoC5/USBFS_cls.c **** interfaceNumber = - 43 .loc 1 60 0 - 44 0012 0C21 movs r1, #12 - 45 .loc 1 61 0 - 46 0014 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 60:.\Generated_Source\PSoC5/USBFS_cls.c **** interfaceNumber = - 47 .loc 1 60 0 - 48 0016 0C4A ldr r2, .L11+8 - 49 .loc 1 61 0 - 50 0018 00F07F03 and r3, r0, #127 - 60:.\Generated_Source\PSoC5/USBFS_cls.c **** interfaceNumber = - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 3 - - - 51 .loc 1 60 0 - 52 001c 01FB0320 mla r0, r1, r3, r2 - 53 0020 0830 adds r0, r0, #8 - 54 0022 8378 ldrb r3, [r0, #2] @ zero_extendqisi2 - 55 .LVL1: - 62:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 56 .loc 1 62 0 - 57 0024 03E0 b .L2 - 58 .LVL2: - 59 .L3: - 56:.\Generated_Source\PSoC5/USBFS_cls.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */ - 60 .loc 1 56 0 - 61 0026 074B ldr r3, .L11+4 - 62 0028 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 63 .LVL3: - 57:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 64 .loc 1 57 0 - 65 002a 00E0 b .L2 - 66 .LVL4: - 67 .L8: - 51:.\Generated_Source\PSoC5/USBFS_cls.c **** uint8 interfaceNumber = 0u; - 68 .loc 1 51 0 - 69 002c 0023 movs r3, #0 - 70 .LVL5: - 71 .L2: - 63:.\Generated_Source\PSoC5/USBFS_cls.c **** default: /* RequestHandled is initialized as FALSE by default */ - 64:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 65:.\Generated_Source\PSoC5/USBFS_cls.c **** } - 66:.\Generated_Source\PSoC5/USBFS_cls.c **** /* Handle Class request depend on interface type */ - 67:.\Generated_Source\PSoC5/USBFS_cls.c **** switch(USBFS_interfaceClass[interfaceNumber]) - 72 .loc 1 67 0 - 73 002e 0749 ldr r1, .L11+12 - 74 0030 0A68 ldr r2, [r1, #0] - 75 0032 D05C ldrb r0, [r2, r3] @ zero_extendqisi2 - 76 0034 0328 cmp r0, #3 - 77 0036 01D1 bne .L9 - 68:.\Generated_Source\PSoC5/USBFS_cls.c **** { - 69:.\Generated_Source\PSoC5/USBFS_cls.c **** case USBFS_CLASS_HID: - 70:.\Generated_Source\PSoC5/USBFS_cls.c **** #if defined(USBFS_ENABLE_HID_CLASS) - 71:.\Generated_Source\PSoC5/USBFS_cls.c **** requestHandled = USBFS_DispatchHIDClassRqst(); - 72:.\Generated_Source\PSoC5/USBFS_cls.c **** #endif /* USBFS_ENABLE_HID_CLASS */ - 73:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 74:.\Generated_Source\PSoC5/USBFS_cls.c **** case USBFS_CLASS_AUDIO: - 75:.\Generated_Source\PSoC5/USBFS_cls.c **** #if defined(USBFS_ENABLE_AUDIO_CLASS) - 76:.\Generated_Source\PSoC5/USBFS_cls.c **** requestHandled = USBFS_DispatchAUDIOClassRqst(); - 77:.\Generated_Source\PSoC5/USBFS_cls.c **** #endif /* USBFS_ENABLE_HID_CLASS */ - 78:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 79:.\Generated_Source\PSoC5/USBFS_cls.c **** case USBFS_CLASS_CDC: - 80:.\Generated_Source\PSoC5/USBFS_cls.c **** #if defined(USBFS_ENABLE_CDC_CLASS) - 81:.\Generated_Source\PSoC5/USBFS_cls.c **** requestHandled = USBFS_DispatchCDCClassRqst(); - 82:.\Generated_Source\PSoC5/USBFS_cls.c **** #endif /* USBFS_ENABLE_CDC_CLASS */ - 83:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 84:.\Generated_Source\PSoC5/USBFS_cls.c **** default: /* requestHandled is initialized as FALSE by default */ - 85:.\Generated_Source\PSoC5/USBFS_cls.c **** break; - 86:.\Generated_Source\PSoC5/USBFS_cls.c **** } - 87:.\Generated_Source\PSoC5/USBFS_cls.c **** - 88:.\Generated_Source\PSoC5/USBFS_cls.c **** /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 4 - - - 89:.\Generated_Source\PSoC5/USBFS_cls.c **** - 90:.\Generated_Source\PSoC5/USBFS_cls.c **** /* `#END` */ - 91:.\Generated_Source\PSoC5/USBFS_cls.c **** - 92:.\Generated_Source\PSoC5/USBFS_cls.c **** return(requestHandled); - 93:.\Generated_Source\PSoC5/USBFS_cls.c **** } - 78 .loc 1 93 0 - 71:.\Generated_Source\PSoC5/USBFS_cls.c **** requestHandled = USBFS_DispatchHIDClassRqst(); - 79 .loc 1 71 0 - 80 0038 FFF7FEBF b USBFS_DispatchHIDClassRqst - 81 .LVL6: - 82 .L9: - 83 .loc 1 93 0 - 84 003c 0020 movs r0, #0 - 85 003e 7047 bx lr - 86 .L12: - 87 .align 2 - 88 .L11: - 89 0040 00600040 .word 1073766400 - 90 0044 04600040 .word 1073766404 - 91 0048 00000000 .word USBFS_EP - 92 004c 00000000 .word USBFS_interfaceClass - 93 .cfi_endproc - 94 .LFE0: - 95 .size USBFS_DispatchClassRqst, .-USBFS_DispatchClassRqst - 96 .text - 97 .Letext0: - 98 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 99 .file 3 ".\\Generated_Source\\PSoC5\\USBFS.h" - 100 .file 4 ".\\Generated_Source\\PSoC5\\USBFS_pvt.h" - 101 .section .debug_info,"",%progbits - 102 .Ldebug_info0: - 103 0000 CB010000 .4byte 0x1cb - 104 0004 0200 .2byte 0x2 - 105 0006 00000000 .4byte .Ldebug_abbrev0 - 106 000a 04 .byte 0x4 - 107 000b 01 .uleb128 0x1 - 108 000c 99010000 .4byte .LASF30 - 109 0010 01 .byte 0x1 - 110 0011 01020000 .4byte .LASF31 - 111 0015 A5000000 .4byte .LASF32 - 112 0019 00000000 .4byte .Ldebug_ranges0+0 - 113 001d 00000000 .4byte 0 - 114 0021 00000000 .4byte 0 - 115 0025 00000000 .4byte .Ldebug_line0 - 116 0029 02 .uleb128 0x2 - 117 002a 01 .byte 0x1 - 118 002b 06 .byte 0x6 - 119 002c F5010000 .4byte .LASF0 - 120 0030 02 .uleb128 0x2 - 121 0031 01 .byte 0x1 - 122 0032 08 .byte 0x8 - 123 0033 F4000000 .4byte .LASF1 - 124 0037 02 .uleb128 0x2 - 125 0038 02 .byte 0x2 - 126 0039 05 .byte 0x5 - 127 003a 89010000 .4byte .LASF2 - 128 003e 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 5 - - - 129 003f 02 .byte 0x2 - 130 0040 07 .byte 0x7 - 131 0041 00000000 .4byte .LASF3 - 132 0045 02 .uleb128 0x2 - 133 0046 04 .byte 0x4 - 134 0047 05 .byte 0x5 - 135 0048 EC010000 .4byte .LASF4 - 136 004c 02 .uleb128 0x2 - 137 004d 04 .byte 0x4 - 138 004e 07 .byte 0x7 - 139 004f 93000000 .4byte .LASF5 - 140 0053 02 .uleb128 0x2 - 141 0054 08 .byte 0x8 - 142 0055 05 .byte 0x5 - 143 0056 6B010000 .4byte .LASF6 - 144 005a 02 .uleb128 0x2 - 145 005b 08 .byte 0x8 - 146 005c 07 .byte 0x7 - 147 005d 3A010000 .4byte .LASF7 - 148 0061 03 .uleb128 0x3 - 149 0062 04 .byte 0x4 - 150 0063 05 .byte 0x5 - 151 0064 696E7400 .ascii "int\000" - 152 0068 02 .uleb128 0x2 - 153 0069 04 .byte 0x4 - 154 006a 07 .byte 0x7 - 155 006b 2D010000 .4byte .LASF8 - 156 006f 04 .uleb128 0x4 - 157 0070 93010000 .4byte .LASF9 - 158 0074 02 .byte 0x2 - 159 0075 5B .byte 0x5b - 160 0076 30000000 .4byte 0x30 - 161 007a 04 .uleb128 0x4 - 162 007b 1B010000 .4byte .LASF10 - 163 007f 02 .byte 0x2 - 164 0080 5C .byte 0x5c - 165 0081 3E000000 .4byte 0x3e - 166 0085 02 .uleb128 0x2 - 167 0086 04 .byte 0x4 - 168 0087 04 .byte 0x4 - 169 0088 52000000 .4byte .LASF11 - 170 008c 02 .uleb128 0x2 - 171 008d 08 .byte 0x8 - 172 008e 04 .byte 0x4 - 173 008f 02010000 .4byte .LASF12 - 174 0093 02 .uleb128 0x2 - 175 0094 01 .byte 0x1 - 176 0095 08 .byte 0x8 - 177 0096 79010000 .4byte .LASF13 - 178 009a 04 .uleb128 0x4 - 179 009b 76000000 .4byte .LASF14 - 180 009f 02 .byte 0x2 - 181 00a0 F0 .byte 0xf0 - 182 00a1 A5000000 .4byte 0xa5 - 183 00a5 05 .uleb128 0x5 - 184 00a6 6F000000 .4byte 0x6f - 185 00aa 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 6 - - - 186 00ab 04 .byte 0x4 - 187 00ac 07 .byte 0x7 - 188 00ad 5B010000 .4byte .LASF15 - 189 00b1 06 .uleb128 0x6 - 190 00b2 0C .byte 0xc - 191 00b3 03 .byte 0x3 - 192 00b4 79 .byte 0x79 - 193 00b5 38010000 .4byte 0x138 - 194 00b9 07 .uleb128 0x7 - 195 00ba 09010000 .4byte .LASF16 - 196 00be 03 .byte 0x3 - 197 00bf 7B .byte 0x7b - 198 00c0 6F000000 .4byte 0x6f - 199 00c4 02 .byte 0x2 - 200 00c5 23 .byte 0x23 - 201 00c6 00 .uleb128 0 - 202 00c7 07 .uleb128 0x7 - 203 00c8 22010000 .4byte .LASF17 - 204 00cc 03 .byte 0x3 - 205 00cd 7C .byte 0x7c - 206 00ce 6F000000 .4byte 0x6f - 207 00d2 02 .byte 0x2 - 208 00d3 23 .byte 0x23 - 209 00d4 01 .uleb128 0x1 - 210 00d5 07 .uleb128 0x7 - 211 00d6 51010000 .4byte .LASF18 - 212 00da 03 .byte 0x3 - 213 00db 7D .byte 0x7d - 214 00dc 6F000000 .4byte 0x6f - 215 00e0 02 .byte 0x2 - 216 00e1 23 .byte 0x23 - 217 00e2 02 .uleb128 0x2 - 218 00e3 07 .uleb128 0x7 - 219 00e4 58000000 .4byte .LASF19 - 220 00e8 03 .byte 0x3 - 221 00e9 7E .byte 0x7e - 222 00ea 6F000000 .4byte 0x6f - 223 00ee 02 .byte 0x2 - 224 00ef 23 .byte 0x23 - 225 00f0 03 .uleb128 0x3 - 226 00f1 07 .uleb128 0x7 - 227 00f2 D6000000 .4byte .LASF20 - 228 00f6 03 .byte 0x3 - 229 00f7 7F .byte 0x7f - 230 00f8 6F000000 .4byte 0x6f - 231 00fc 02 .byte 0x2 - 232 00fd 23 .byte 0x23 - 233 00fe 04 .uleb128 0x4 - 234 00ff 07 .uleb128 0x7 - 235 0100 64010000 .4byte .LASF21 - 236 0104 03 .byte 0x3 - 237 0105 80 .byte 0x80 - 238 0106 6F000000 .4byte 0x6f - 239 010a 02 .byte 0x2 - 240 010b 23 .byte 0x23 - 241 010c 05 .uleb128 0x5 - 242 010d 07 .uleb128 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 7 - - - 243 010e 10010000 .4byte .LASF22 - 244 0112 03 .byte 0x3 - 245 0113 81 .byte 0x81 - 246 0114 7A000000 .4byte 0x7a - 247 0118 02 .byte 0x2 - 248 0119 23 .byte 0x23 - 249 011a 06 .uleb128 0x6 - 250 011b 07 .uleb128 0x7 - 251 011c 7E010000 .4byte .LASF23 - 252 0120 03 .byte 0x3 - 253 0121 82 .byte 0x82 - 254 0122 7A000000 .4byte 0x7a - 255 0126 02 .byte 0x2 - 256 0127 23 .byte 0x23 - 257 0128 08 .uleb128 0x8 - 258 0129 07 .uleb128 0x7 - 259 012a E2010000 .4byte .LASF24 - 260 012e 03 .byte 0x3 - 261 012f 83 .byte 0x83 - 262 0130 6F000000 .4byte 0x6f - 263 0134 02 .byte 0x2 - 264 0135 23 .byte 0x23 - 265 0136 0A .uleb128 0xa - 266 0137 00 .byte 0 - 267 0138 04 .uleb128 0x4 - 268 0139 13000000 .4byte .LASF25 - 269 013d 03 .byte 0x3 - 270 013e 84 .byte 0x84 - 271 013f B1000000 .4byte 0xb1 - 272 0143 08 .uleb128 0x8 - 273 0144 01 .byte 0x1 - 274 0145 7B000000 .4byte .LASF33 - 275 0149 01 .byte 0x1 - 276 014a 30 .byte 0x30 - 277 014b 01 .byte 0x1 - 278 014c 6F000000 .4byte 0x6f - 279 0150 00000000 .4byte .LFB0 - 280 0154 50000000 .4byte .LFE0 - 281 0158 02 .byte 0x2 - 282 0159 7D .byte 0x7d - 283 015a 00 .sleb128 0 - 284 015b 01 .byte 0x1 - 285 015c 86010000 .4byte 0x186 - 286 0160 09 .uleb128 0x9 - 287 0161 43000000 .4byte .LASF26 - 288 0165 01 .byte 0x1 - 289 0166 32 .byte 0x32 - 290 0167 6F000000 .4byte 0x6f - 291 016b 00 .byte 0 - 292 016c 0A .uleb128 0xa - 293 016d DB000000 .4byte .LASF27 - 294 0171 01 .byte 0x1 - 295 0172 33 .byte 0x33 - 296 0173 6F000000 .4byte 0x6f - 297 0177 00000000 .4byte .LLST0 - 298 017b 0B .uleb128 0xb - 299 017c 3C000000 .4byte .LVL6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 8 - - - 300 0180 01 .byte 0x1 - 301 0181 C0010000 .4byte 0x1c0 - 302 0185 00 .byte 0 - 303 0186 0C .uleb128 0xc - 304 0187 61000000 .4byte .LASF28 - 305 018b 04 .byte 0x4 - 306 018c 3D .byte 0x3d - 307 018d 93010000 .4byte 0x193 - 308 0191 01 .byte 0x1 - 309 0192 01 .byte 0x1 - 310 0193 0D .uleb128 0xd - 311 0194 04 .byte 0x4 - 312 0195 99010000 .4byte 0x199 - 313 0199 0E .uleb128 0xe - 314 019a 6F000000 .4byte 0x6f - 315 019e 0F .uleb128 0xf - 316 019f 38010000 .4byte 0x138 - 317 01a3 AE010000 .4byte 0x1ae - 318 01a7 10 .uleb128 0x10 - 319 01a8 AA000000 .4byte 0xaa - 320 01ac 08 .byte 0x8 - 321 01ad 00 .byte 0 - 322 01ae 0C .uleb128 0xc - 323 01af EB000000 .4byte .LASF29 - 324 01b3 04 .byte 0x4 - 325 01b4 3F .byte 0x3f - 326 01b5 BB010000 .4byte 0x1bb - 327 01b9 01 .byte 0x1 - 328 01ba 01 .byte 0x1 - 329 01bb 05 .uleb128 0x5 - 330 01bc 9E010000 .4byte 0x19e - 331 01c0 11 .uleb128 0x11 - 332 01c1 01 .byte 0x1 - 333 01c2 28000000 .4byte .LASF34 - 334 01c6 04 .byte 0x4 - 335 01c7 7F .byte 0x7f - 336 01c8 01 .byte 0x1 - 337 01c9 6F000000 .4byte 0x6f - 338 01cd 01 .byte 0x1 - 339 01ce 00 .byte 0 - 340 .section .debug_abbrev,"",%progbits - 341 .Ldebug_abbrev0: - 342 0000 01 .uleb128 0x1 - 343 0001 11 .uleb128 0x11 - 344 0002 01 .byte 0x1 - 345 0003 25 .uleb128 0x25 - 346 0004 0E .uleb128 0xe - 347 0005 13 .uleb128 0x13 - 348 0006 0B .uleb128 0xb - 349 0007 03 .uleb128 0x3 - 350 0008 0E .uleb128 0xe - 351 0009 1B .uleb128 0x1b - 352 000a 0E .uleb128 0xe - 353 000b 55 .uleb128 0x55 - 354 000c 06 .uleb128 0x6 - 355 000d 11 .uleb128 0x11 - 356 000e 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 9 - - - 357 000f 52 .uleb128 0x52 - 358 0010 01 .uleb128 0x1 - 359 0011 10 .uleb128 0x10 - 360 0012 06 .uleb128 0x6 - 361 0013 00 .byte 0 - 362 0014 00 .byte 0 - 363 0015 02 .uleb128 0x2 - 364 0016 24 .uleb128 0x24 - 365 0017 00 .byte 0 - 366 0018 0B .uleb128 0xb - 367 0019 0B .uleb128 0xb - 368 001a 3E .uleb128 0x3e - 369 001b 0B .uleb128 0xb - 370 001c 03 .uleb128 0x3 - 371 001d 0E .uleb128 0xe - 372 001e 00 .byte 0 - 373 001f 00 .byte 0 - 374 0020 03 .uleb128 0x3 - 375 0021 24 .uleb128 0x24 - 376 0022 00 .byte 0 - 377 0023 0B .uleb128 0xb - 378 0024 0B .uleb128 0xb - 379 0025 3E .uleb128 0x3e - 380 0026 0B .uleb128 0xb - 381 0027 03 .uleb128 0x3 - 382 0028 08 .uleb128 0x8 - 383 0029 00 .byte 0 - 384 002a 00 .byte 0 - 385 002b 04 .uleb128 0x4 - 386 002c 16 .uleb128 0x16 - 387 002d 00 .byte 0 - 388 002e 03 .uleb128 0x3 - 389 002f 0E .uleb128 0xe - 390 0030 3A .uleb128 0x3a - 391 0031 0B .uleb128 0xb - 392 0032 3B .uleb128 0x3b - 393 0033 0B .uleb128 0xb - 394 0034 49 .uleb128 0x49 - 395 0035 13 .uleb128 0x13 - 396 0036 00 .byte 0 - 397 0037 00 .byte 0 - 398 0038 05 .uleb128 0x5 - 399 0039 35 .uleb128 0x35 - 400 003a 00 .byte 0 - 401 003b 49 .uleb128 0x49 - 402 003c 13 .uleb128 0x13 - 403 003d 00 .byte 0 - 404 003e 00 .byte 0 - 405 003f 06 .uleb128 0x6 - 406 0040 13 .uleb128 0x13 - 407 0041 01 .byte 0x1 - 408 0042 0B .uleb128 0xb - 409 0043 0B .uleb128 0xb - 410 0044 3A .uleb128 0x3a - 411 0045 0B .uleb128 0xb - 412 0046 3B .uleb128 0x3b - 413 0047 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 10 - - - 414 0048 01 .uleb128 0x1 - 415 0049 13 .uleb128 0x13 - 416 004a 00 .byte 0 - 417 004b 00 .byte 0 - 418 004c 07 .uleb128 0x7 - 419 004d 0D .uleb128 0xd - 420 004e 00 .byte 0 - 421 004f 03 .uleb128 0x3 - 422 0050 0E .uleb128 0xe - 423 0051 3A .uleb128 0x3a - 424 0052 0B .uleb128 0xb - 425 0053 3B .uleb128 0x3b - 426 0054 0B .uleb128 0xb - 427 0055 49 .uleb128 0x49 - 428 0056 13 .uleb128 0x13 - 429 0057 38 .uleb128 0x38 - 430 0058 0A .uleb128 0xa - 431 0059 00 .byte 0 - 432 005a 00 .byte 0 - 433 005b 08 .uleb128 0x8 - 434 005c 2E .uleb128 0x2e - 435 005d 01 .byte 0x1 - 436 005e 3F .uleb128 0x3f - 437 005f 0C .uleb128 0xc - 438 0060 03 .uleb128 0x3 - 439 0061 0E .uleb128 0xe - 440 0062 3A .uleb128 0x3a - 441 0063 0B .uleb128 0xb - 442 0064 3B .uleb128 0x3b - 443 0065 0B .uleb128 0xb - 444 0066 27 .uleb128 0x27 - 445 0067 0C .uleb128 0xc - 446 0068 49 .uleb128 0x49 - 447 0069 13 .uleb128 0x13 - 448 006a 11 .uleb128 0x11 - 449 006b 01 .uleb128 0x1 - 450 006c 12 .uleb128 0x12 - 451 006d 01 .uleb128 0x1 - 452 006e 40 .uleb128 0x40 - 453 006f 0A .uleb128 0xa - 454 0070 9742 .uleb128 0x2117 - 455 0072 0C .uleb128 0xc - 456 0073 01 .uleb128 0x1 - 457 0074 13 .uleb128 0x13 - 458 0075 00 .byte 0 - 459 0076 00 .byte 0 - 460 0077 09 .uleb128 0x9 - 461 0078 34 .uleb128 0x34 - 462 0079 00 .byte 0 - 463 007a 03 .uleb128 0x3 - 464 007b 0E .uleb128 0xe - 465 007c 3A .uleb128 0x3a - 466 007d 0B .uleb128 0xb - 467 007e 3B .uleb128 0x3b - 468 007f 0B .uleb128 0xb - 469 0080 49 .uleb128 0x49 - 470 0081 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 11 - - - 471 0082 1C .uleb128 0x1c - 472 0083 0B .uleb128 0xb - 473 0084 00 .byte 0 - 474 0085 00 .byte 0 - 475 0086 0A .uleb128 0xa - 476 0087 34 .uleb128 0x34 - 477 0088 00 .byte 0 - 478 0089 03 .uleb128 0x3 - 479 008a 0E .uleb128 0xe - 480 008b 3A .uleb128 0x3a - 481 008c 0B .uleb128 0xb - 482 008d 3B .uleb128 0x3b - 483 008e 0B .uleb128 0xb - 484 008f 49 .uleb128 0x49 - 485 0090 13 .uleb128 0x13 - 486 0091 02 .uleb128 0x2 - 487 0092 06 .uleb128 0x6 - 488 0093 00 .byte 0 - 489 0094 00 .byte 0 - 490 0095 0B .uleb128 0xb - 491 0096 898201 .uleb128 0x4109 - 492 0099 00 .byte 0 - 493 009a 11 .uleb128 0x11 - 494 009b 01 .uleb128 0x1 - 495 009c 9542 .uleb128 0x2115 - 496 009e 0C .uleb128 0xc - 497 009f 31 .uleb128 0x31 - 498 00a0 13 .uleb128 0x13 - 499 00a1 00 .byte 0 - 500 00a2 00 .byte 0 - 501 00a3 0C .uleb128 0xc - 502 00a4 34 .uleb128 0x34 - 503 00a5 00 .byte 0 - 504 00a6 03 .uleb128 0x3 - 505 00a7 0E .uleb128 0xe - 506 00a8 3A .uleb128 0x3a - 507 00a9 0B .uleb128 0xb - 508 00aa 3B .uleb128 0x3b - 509 00ab 0B .uleb128 0xb - 510 00ac 49 .uleb128 0x49 - 511 00ad 13 .uleb128 0x13 - 512 00ae 3F .uleb128 0x3f - 513 00af 0C .uleb128 0xc - 514 00b0 3C .uleb128 0x3c - 515 00b1 0C .uleb128 0xc - 516 00b2 00 .byte 0 - 517 00b3 00 .byte 0 - 518 00b4 0D .uleb128 0xd - 519 00b5 0F .uleb128 0xf - 520 00b6 00 .byte 0 - 521 00b7 0B .uleb128 0xb - 522 00b8 0B .uleb128 0xb - 523 00b9 49 .uleb128 0x49 - 524 00ba 13 .uleb128 0x13 - 525 00bb 00 .byte 0 - 526 00bc 00 .byte 0 - 527 00bd 0E .uleb128 0xe - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 12 - - - 528 00be 26 .uleb128 0x26 - 529 00bf 00 .byte 0 - 530 00c0 49 .uleb128 0x49 - 531 00c1 13 .uleb128 0x13 - 532 00c2 00 .byte 0 - 533 00c3 00 .byte 0 - 534 00c4 0F .uleb128 0xf - 535 00c5 01 .uleb128 0x1 - 536 00c6 01 .byte 0x1 - 537 00c7 49 .uleb128 0x49 - 538 00c8 13 .uleb128 0x13 - 539 00c9 01 .uleb128 0x1 - 540 00ca 13 .uleb128 0x13 - 541 00cb 00 .byte 0 - 542 00cc 00 .byte 0 - 543 00cd 10 .uleb128 0x10 - 544 00ce 21 .uleb128 0x21 - 545 00cf 00 .byte 0 - 546 00d0 49 .uleb128 0x49 - 547 00d1 13 .uleb128 0x13 - 548 00d2 2F .uleb128 0x2f - 549 00d3 0B .uleb128 0xb - 550 00d4 00 .byte 0 - 551 00d5 00 .byte 0 - 552 00d6 11 .uleb128 0x11 - 553 00d7 2E .uleb128 0x2e - 554 00d8 00 .byte 0 - 555 00d9 3F .uleb128 0x3f - 556 00da 0C .uleb128 0xc - 557 00db 03 .uleb128 0x3 - 558 00dc 0E .uleb128 0xe - 559 00dd 3A .uleb128 0x3a - 560 00de 0B .uleb128 0xb - 561 00df 3B .uleb128 0x3b - 562 00e0 0B .uleb128 0xb - 563 00e1 27 .uleb128 0x27 - 564 00e2 0C .uleb128 0xc - 565 00e3 49 .uleb128 0x49 - 566 00e4 13 .uleb128 0x13 - 567 00e5 3C .uleb128 0x3c - 568 00e6 0C .uleb128 0xc - 569 00e7 00 .byte 0 - 570 00e8 00 .byte 0 - 571 00e9 00 .byte 0 - 572 .section .debug_loc,"",%progbits - 573 .Ldebug_loc0: - 574 .LLST0: - 575 0000 00000000 .4byte .LVL0 - 576 0004 24000000 .4byte .LVL1 - 577 0008 0200 .2byte 0x2 - 578 000a 30 .byte 0x30 - 579 000b 9F .byte 0x9f - 580 000c 24000000 .4byte .LVL1 - 581 0010 26000000 .4byte .LVL2 - 582 0014 0100 .2byte 0x1 - 583 0016 53 .byte 0x53 - 584 0017 26000000 .4byte .LVL2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 13 - - - 585 001b 2A000000 .4byte .LVL3 - 586 001f 0200 .2byte 0x2 - 587 0021 30 .byte 0x30 - 588 0022 9F .byte 0x9f - 589 0023 2A000000 .4byte .LVL3 - 590 0027 2C000000 .4byte .LVL4 - 591 002b 0100 .2byte 0x1 - 592 002d 53 .byte 0x53 - 593 002e 2C000000 .4byte .LVL4 - 594 0032 2E000000 .4byte .LVL5 - 595 0036 0200 .2byte 0x2 - 596 0038 30 .byte 0x30 - 597 0039 9F .byte 0x9f - 598 003a 2E000000 .4byte .LVL5 - 599 003e 3B000000 .4byte .LVL6-1 - 600 0042 0100 .2byte 0x1 - 601 0044 53 .byte 0x53 - 602 0045 3C000000 .4byte .LVL6 - 603 0049 50000000 .4byte .LFE0 - 604 004d 0100 .2byte 0x1 - 605 004f 53 .byte 0x53 - 606 0050 00000000 .4byte 0 - 607 0054 00000000 .4byte 0 - 608 .section .debug_aranges,"",%progbits - 609 0000 1C000000 .4byte 0x1c - 610 0004 0200 .2byte 0x2 - 611 0006 00000000 .4byte .Ldebug_info0 - 612 000a 04 .byte 0x4 - 613 000b 00 .byte 0 - 614 000c 0000 .2byte 0 - 615 000e 0000 .2byte 0 - 616 0010 00000000 .4byte .LFB0 - 617 0014 50000000 .4byte .LFE0-.LFB0 - 618 0018 00000000 .4byte 0 - 619 001c 00000000 .4byte 0 - 620 .section .debug_ranges,"",%progbits - 621 .Ldebug_ranges0: - 622 0000 00000000 .4byte .LFB0 - 623 0004 50000000 .4byte .LFE0 - 624 0008 00000000 .4byte 0 - 625 000c 00000000 .4byte 0 - 626 .section .debug_line,"",%progbits - 627 .Ldebug_line0: - 628 0000 92000000 .section .debug_str,"MS",%progbits,1 - 628 02006200 - 628 00000201 - 628 FB0E0D00 - 628 01010101 - 629 .LASF3: - 630 0000 73686F72 .ascii "short unsigned int\000" - 630 7420756E - 630 7369676E - 630 65642069 - 630 6E7400 - 631 .LASF25: - 632 0013 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 632 4246535F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 14 - - - 632 45505F43 - 632 544C5F42 - 632 4C4F434B - 633 .LASF34: - 634 0028 55534246 .ascii "USBFS_DispatchHIDClassRqst\000" - 634 535F4469 - 634 73706174 - 634 63684849 - 634 44436C61 - 635 .LASF26: - 636 0043 72657175 .ascii "requestHandled\000" - 636 65737448 - 636 616E646C - 636 656400 - 637 .LASF11: - 638 0052 666C6F61 .ascii "float\000" - 638 7400 - 639 .LASF19: - 640 0058 6570546F .ascii "epToggle\000" - 640 67676C65 - 640 00 - 641 .LASF28: - 642 0061 55534246 .ascii "USBFS_interfaceClass\000" - 642 535F696E - 642 74657266 - 642 61636543 - 642 6C617373 - 643 .LASF14: - 644 0076 72656738 .ascii "reg8\000" - 644 00 - 645 .LASF33: - 646 007b 55534246 .ascii "USBFS_DispatchClassRqst\000" - 646 535F4469 - 646 73706174 - 646 6368436C - 646 61737352 - 647 .LASF5: - 648 0093 6C6F6E67 .ascii "long unsigned int\000" - 648 20756E73 - 648 69676E65 - 648 6420696E - 648 7400 - 649 .LASF32: - 650 00a5 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 650 43534932 - 650 53445C73 - 650 6F667477 - 650 6172655C - 651 00d4 6E00 .ascii "n\000" - 652 .LASF20: - 653 00d6 61646472 .ascii "addr\000" - 653 00 - 654 .LASF27: - 655 00db 696E7465 .ascii "interfaceNumber\000" - 655 72666163 - 655 654E756D - 655 62657200 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 15 - - - 656 .LASF29: - 657 00eb 55534246 .ascii "USBFS_EP\000" - 657 535F4550 - 657 00 - 658 .LASF1: - 659 00f4 756E7369 .ascii "unsigned char\000" - 659 676E6564 - 659 20636861 - 659 7200 - 660 .LASF12: - 661 0102 646F7562 .ascii "double\000" - 661 6C6500 - 662 .LASF16: - 663 0109 61747472 .ascii "attrib\000" - 663 696200 - 664 .LASF22: - 665 0110 62756666 .ascii "buffOffset\000" - 665 4F666673 - 665 657400 - 666 .LASF10: - 667 011b 75696E74 .ascii "uint16\000" - 667 313600 - 668 .LASF17: - 669 0122 61706945 .ascii "apiEpState\000" - 669 70537461 - 669 746500 - 670 .LASF8: - 671 012d 756E7369 .ascii "unsigned int\000" - 671 676E6564 - 671 20696E74 - 671 00 - 672 .LASF7: - 673 013a 6C6F6E67 .ascii "long long unsigned int\000" - 673 206C6F6E - 673 6720756E - 673 7369676E - 673 65642069 - 674 .LASF18: - 675 0151 68774570 .ascii "hwEpState\000" - 675 53746174 - 675 6500 - 676 .LASF15: - 677 015b 73697A65 .ascii "sizetype\000" - 677 74797065 - 677 00 - 678 .LASF21: - 679 0164 65704D6F .ascii "epMode\000" - 679 646500 - 680 .LASF6: - 681 016b 6C6F6E67 .ascii "long long int\000" - 681 206C6F6E - 681 6720696E - 681 7400 - 682 .LASF13: - 683 0179 63686172 .ascii "char\000" - 683 00 - 684 .LASF23: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccfm3BeD.s page 16 - - - 685 017e 62756666 .ascii "bufferSize\000" - 685 65725369 - 685 7A6500 - 686 .LASF2: - 687 0189 73686F72 .ascii "short int\000" - 687 7420696E - 687 7400 - 688 .LASF9: - 689 0193 75696E74 .ascii "uint8\000" - 689 3800 - 690 .LASF30: - 691 0199 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 691 4320342E - 691 372E3320 - 691 32303133 - 691 30333132 - 692 01cc 616E6368 .ascii "anch revision 196615]\000" - 692 20726576 - 692 6973696F - 692 6E203139 - 692 36363135 - 693 .LASF24: - 694 01e2 696E7465 .ascii "interface\000" - 694 72666163 - 694 6500 - 695 .LASF4: - 696 01ec 6C6F6E67 .ascii "long int\000" - 696 20696E74 - 696 00 - 697 .LASF0: - 698 01f5 7369676E .ascii "signed char\000" - 698 65642063 - 698 68617200 - 699 .LASF31: - 700 0201 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_cls.c\000" - 700 6E657261 - 700 7465645F - 700 536F7572 - 700 63655C50 - 701 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_cls.o deleted file mode 100755 index 6a62d977efa47a52109421925046196a274aed92..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4092 zcmb_fU2Ggz6+U-n*1Ptu*LK{xNgcIglBQ0nCu=)NUH2!6H%{WlNley(N^vo>yR-Jv z_0DEyoY-kv(;q?014vW_Atc%dctPUtffxD!LPbL2fmW(2Bwi|1ULX&l0`X9(>38nj zyE}GO!2?IS^PRtY&Y64e+`YRsJAXf)4udv&+6Mt=BRk*_J2P94cV>J z^c6a8Vd$KHL_$LfmiRt+At3!&TN7xAu79(y$ovah!$`ftl96T?!%E#`$x6Sl*Qk|iE=I;)?>UlLiAePh&;RX@tgh(qyHz6GL-uV`yG2z`lWsd7!aeZ+LFly zi2-q6elTn1hx3=Z2E;|t--TNCQ#SiJl&Dy-*jd&PnfdALBiT8;O6mwPbPbAZmURL` zy0`5x)r0JgIF^fN+@G5p91y$2@t*I^cuLxfr}`k2CU$8HV0enA?|?C=%un%Az8C$IUo>~fSvu`Cy}*sU z>T=0n4=Uc$Ldh>4A-YtWIaOM&G(xAsUwmaV+H85Dv&w?BCD`TG)hHIxCRv$T5JTU* zcjVrYv3c{leF($sx6QksG`}j$A;;)J4dJREMD}_!tgke^s?A^E;&PmIc44`=IKMnI zf1!9*6>_p3w%n+)dS>oqvEhc{#VcV%fp=xy3!^h`v)b^gRBQNdL|$vrUs-8*Y9iu# zLCvjravG+rOzjBSiP!L(E88pj()3cPSelzCom>k2T6E0~ytV?hF3*_V_9oDaV+%BxeIlt;9Ch&Bbo3nXA362yuf-RhPicX)uWEbtj z&O^?mJy95+EKH71*rS2h@Z8WlXkR{Y@!TN~?^UgO)v?3N4~>-rw^>=W1Mg}*tou!S z{NbZV$B#VKS%$a(&Y+qtOZcq4x0Kv^bh=oawnw?9Mc;3PcFhlLRAA4l3hafzuXthT z2jRj0N6{xH@SV7xTdtElw^BuHQ*UGJ+$44Nq|bF5yR19Jo#HNYx7Z`@7WY_utP_9k zw?Tr88~I$Xl%bL&KSd|pT#MW?IbjsUxT-lskI1RIkxNcF49US#JFIl#h0t5SvrnZ* z)hn;BEZ3VgACo2TmdoftJU`Yn{7O=E(Wn(qWr#gKt!dPoo{oqT$*K5jYaV*%VA-8` zv#v+mqtpU-&C~Duzu+*Oc-?UHN{a6fN&v*i8_@`O_A`}frytvx?#JM($ba)Iz-MRP z_Vn;Avg z#@C2sytfdqA3BbQU%_@f{>jmEz|yY}kNq@h+qa-d#(Osr4@=&T_apFn4#)UC;(eDH zMcVcT+SsumZ)MiEz_k-zOjO2UVOsvZtu(2P%*8m3cw&@Jw{jDu^a&gYY z>(Oo;SS=`dPvaURJr3E0%7k0?%3K3t&_D8h8`k9xQ?LQjZ?n|)=_mG&u4|4Kq zbOt$%JBj8Qhlr+t_u$p|d@`^xuw}@=xy5^q5v~&VFv55rBO3Rh()0djziEXh6v{l% z^Ewlo|rwV_q@DB>#Q}}_x4;6Alcz#~tUWE@R zd|2VELO!pJ6w#tWSLxRjUSq_+kQ>VW4W<9N!rv)GdKrgzF~^hZ3go`C%x4wju)=)` s`8SUBj=~9ra($tfe^Y_8NxuQ zUw-Peon-HO@69*w&AgeNne}Irg9D19kSq#y)2v3cIO5g>HoMSGi>R$$FL{lq3TM(T zeQOXDZ6`6_E3lCxxe{eP<03q9StYK-y0wDv(7LDpC!S1G!2owNcbsl%P%E^+B>wQ^s!& zJQECRR@V`7d6=4YA{E0_n>*VTQdV|RFu)^Mf&m`5vPdCLQt12oiXSLFih5WHa|?HD zy7D+=4K7sxdf@M@=|PL@LV@4A5IhFZ^gyZNaNRx7 z^i%A2PZy%-*FjgtH$qf({p;)|q_=THC3FE0D7ZDjvyhuY>K86R4gQJ49C2$_QSc}? zI_hak@GkUJz2DQ+;D5R9i=L(hS8=-sD(rEU9$XXve#xtABK>I%>aj;r*`%uvu0_M( zMdly(7!(XM|Ag0CB|XG}PO9KFEl^LH%zvFdf7N49@IH?H2v=~l#a#F3K35A-NIwQW zq;nYkBpV;wh+mBGYn+4T0;#8E+$XtXPq?YU07CkcAhhUzVe2>Uh8$+%k02~K0im7T z_e5L!GAv2}ETYzDB<&4J>!!#c>a-ni`Dnjo+PCr3hOxQch$83VKzpMT7U^w~I zB~78o3ikHT-9FkH$Zp^EN*cU%vbT$tk2b_K4*EGs)2MAFWQ~-EeLP3BVUGp?dQHW5uQ)&7e0>b<+${+mLl6Z z&ST%2_0oDTkD2y3l3v@UGIlIx;y_(M=Z7Gj9sV$xc7gl`F_I`GPFA%><7B^+j(0wox! z6SlWt;kUsHlbT@hSF3 zzGd)%F1f$*XAcCG#`stHcWVTDBX&m&4*z50yUdDN%{gW=cWXOiiGcp{li48{#(p5&fvd=Tx1;~9k9o$AkyjAgRv(M&cI?;A|M zQzxn6OMH0#3RVpp_}qbBX&gPG5B8K*b)vP3U7D!V}8yleM{+yGeT-h;9$0=1NDUoM;bNTxBucxKGV_6?3CK6>@Rc^STa$GDL&QX7r_aod`3KAEeUbpwKD z`z*`BK#C?--JzmgpaLQbStFUr zU?~{$S-9S-RkkXVbC=beHRe`d%9+lVOSV&=BY$LXj_OVdQ@JYHrB9js{?n{GUcho$ z4UT2Vlp59G8n|e1!yQ^l|%-QC;=$?3b=w@?&-Ygc);)c!HZ5#5{ zT%|A-t(te0?2=W9_I_~d*4{093Es@=M6Mt*!u_}1Ee@%2-)}b^WwSErOi_NQWEY5b zB@#QL-Q0zYWtHvdgjJ0qU^FQLMn|hw!L)6wYOi}Q`WWYnWX{axOQdu|3?#4vnFluv zZK9@@;83%=NMEchQI=}gE6bGS%1!!8g<|%h{Z1|qbgCXsNeN9IiWPZhiREpZVn|!8 zYIz2hi)OwynJrZ&EYMszm(L?}9#dG5&q-_!f>171OerG{#R}H`{U(wbLt><_ zZ@B?PKF@GKyT$uP5()rEyIVT(%RD~Vxis>)j>}p+IM&~m*8>i>k^b3VMmm8k58?HY zoAJo9cnQ&AC=2m0haZl2D;{5SIs&ClI`P$QhwS%v68?6g6YP(3ApPz3wShu!VWk9&5h*Kdx?b{V(iYXgz?!e5pJQKY{bbe1`fT%PB+ z=%XxL$IoGbl6MxDq64tWB6&w)z}!wtdvXEc8*#QUk4rlqxdvE22;L(sh$4B6a&Ecm zT$^X$_P7DMZ|1Q9V*K#}hbCZxcN38Si#Oo?5 z^f4f>WgaQl-wWJYn+L8 zdUNJ==tm$+{#sP}`6hHf|0yUZ!I$xV0{waDxPrU!UW5K3WJBl|pf7{NbwXc`De8mH zdEx$vLrtEET}5HI+_mL$wuXDiJSg>paz1x!|CQice9QZ;cj9034fEPUUFLfFu5bNw z@3_}IfcN0yc$x2xYwm{l5_pHR;JY|^9_-hZ`BOxpXn&Hq)$ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst deleted file mode 100755 index f6fc75b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.lst +++ /dev/null @@ -1,4240 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "USBFS_drv.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.USBFS_LoadEP0,"ax",%progbits - 19 .align 1 - 20 .global USBFS_LoadEP0 - 21 .thumb - 22 .thumb_func - 23 .type USBFS_LoadEP0, %function - 24 USBFS_LoadEP0: - 25 .LFB4: - 26 .file 1 ".\\Generated_Source\\PSoC5\\USBFS_drv.c" - 1:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/USBFS_drv.c **** * File Name: USBFS_drv.c - 3:.\Generated_Source\PSoC5/USBFS_drv.c **** * Version 2.60 - 4:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 5:.\Generated_Source\PSoC5/USBFS_drv.c **** * Description: - 6:.\Generated_Source\PSoC5/USBFS_drv.c **** * Endpoint 0 Driver for the USBFS Component. - 7:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 8:.\Generated_Source\PSoC5/USBFS_drv.c **** * Note: - 9:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 10:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/USBFS_drv.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/USBFS_drv.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/USBFS_drv.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/USBFS_drv.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/USBFS_drv.c **** - 17:.\Generated_Source\PSoC5/USBFS_drv.c **** #include "USBFS.h" - 18:.\Generated_Source\PSoC5/USBFS_drv.c **** #include "USBFS_pvt.h" - 19:.\Generated_Source\PSoC5/USBFS_drv.c **** - 20:.\Generated_Source\PSoC5/USBFS_drv.c **** - 21:.\Generated_Source\PSoC5/USBFS_drv.c **** /*************************************** - 22:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global data allocation - 23:.\Generated_Source\PSoC5/USBFS_drv.c **** ***************************************/ - 24:.\Generated_Source\PSoC5/USBFS_drv.c **** - 25:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; - 26:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_configuration; - 27:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_interfaceNumber; - 28:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_configurationChanged; - 29:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_deviceAddress; - 30:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_deviceStatus; - 31:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 2 - - - 32:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; - 33:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; - 34:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_device; - 35:.\Generated_Source\PSoC5/USBFS_drv.c **** const uint8 CYCODE *USBFS_interfaceClass; - 36:.\Generated_Source\PSoC5/USBFS_drv.c **** - 37:.\Generated_Source\PSoC5/USBFS_drv.c **** - 38:.\Generated_Source\PSoC5/USBFS_drv.c **** /*************************************** - 39:.\Generated_Source\PSoC5/USBFS_drv.c **** * Local data allocation - 40:.\Generated_Source\PSoC5/USBFS_drv.c **** ***************************************/ - 41:.\Generated_Source\PSoC5/USBFS_drv.c **** - 42:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_ep0Toggle; - 43:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_lastPacketSize; - 44:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_transferState; - 45:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile T_USBFS_TD USBFS_currentTD; - 46:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_ep0Mode; - 47:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint8 USBFS_ep0Count; - 48:.\Generated_Source\PSoC5/USBFS_drv.c **** volatile uint16 USBFS_transferByteCount; - 49:.\Generated_Source\PSoC5/USBFS_drv.c **** - 50:.\Generated_Source\PSoC5/USBFS_drv.c **** - 51:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 52:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_ep_0_Interrupt - 53:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 54:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 55:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 56:.\Generated_Source\PSoC5/USBFS_drv.c **** * This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. - 57:.\Generated_Source\PSoC5/USBFS_drv.c **** * It dispatches setup requests and handles the data and status stages. - 58:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 59:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 60:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 61:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 62:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 63:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 64:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 65:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 66:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_ISR(USBFS_EP_0_ISR) - 67:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 68:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 bRegTemp; - 69:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 modifyReg; - 70:.\Generated_Source\PSoC5/USBFS_drv.c **** - 71:.\Generated_Source\PSoC5/USBFS_drv.c **** - 72:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); - 73:.\Generated_Source\PSoC5/USBFS_drv.c **** if ((bRegTemp & USBFS_MODE_ACKD) != 0u) - 74:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 75:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = 1u; - 76:.\Generated_Source\PSoC5/USBFS_drv.c **** if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u) - 77:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 78:.\Generated_Source\PSoC5/USBFS_drv.c **** if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) - 79:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 80:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = 0u; /* When mode not NAK_IN_OUT => - 81:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 82:.\Generated_Source\PSoC5/USBFS_drv.c **** else - 83:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 84:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_HandleSetup(); - 85:.\Generated_Source\PSoC5/USBFS_drv.c **** if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) - 86:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 87:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = 0u; /* if SETUP bit set -> exit without mod - 88:.\Generated_Source\PSoC5/USBFS_drv.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 3 - - - 89:.\Generated_Source\PSoC5/USBFS_drv.c **** - 90:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 91:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 92:.\Generated_Source\PSoC5/USBFS_drv.c **** else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u) - 93:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 94:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_HandleIN(); - 95:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 96:.\Generated_Source\PSoC5/USBFS_drv.c **** else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u) - 97:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 98:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_HandleOUT(); - 99:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 100:.\Generated_Source\PSoC5/USBFS_drv.c **** else - 101:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 102:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = 0u; - 103:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 104:.\Generated_Source\PSoC5/USBFS_drv.c **** if(modifyReg != 0u) - 105:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 106:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - 107:.\Generated_Source\PSoC5/USBFS_drv.c **** if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwi - 108:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 109:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the count register */ - 110:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count; - 111:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp); - 112:.\Generated_Source\PSoC5/USBFS_drv.c **** if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was success - 113:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 114:.\Generated_Source\PSoC5/USBFS_drv.c **** do - 115:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 116:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = USBFS_ep0Mode; /* Init temporary variable */ - 117:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Unlock registers */ - 118:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; - 119:.\Generated_Source\PSoC5/USBFS_drv.c **** if(bRegTemp == 0u) /* Check if SETUP bit is not se - 120:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 121:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Set the Mode Register */ - 122:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode); - 123:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Writing check */ - 124:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK; - 125:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 126:.\Generated_Source\PSoC5/USBFS_drv.c **** }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */ - 127:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 128:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 129:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 130:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 131:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 132:.\Generated_Source\PSoC5/USBFS_drv.c **** - 133:.\Generated_Source\PSoC5/USBFS_drv.c **** - 134:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 135:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_HandleSetup - 136:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 137:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 138:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 139:.\Generated_Source\PSoC5/USBFS_drv.c **** * This Routine dispatches requests for the four USB request types - 140:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 141:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 142:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 143:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 144:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 145:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 4 - - - 146:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 147:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 148:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 149:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 150:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 151:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_HandleSetup(void) - 152:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 153:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 requestHandled; - 154:.\Generated_Source\PSoC5/USBFS_drv.c **** - 155:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - 156:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */ - 157:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */ - 158:.\Generated_Source\PSoC5/USBFS_drv.c **** if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) - 159:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 160:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mo - 161:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 162:.\Generated_Source\PSoC5/USBFS_drv.c **** else - 163:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 164:.\Generated_Source\PSoC5/USBFS_drv.c **** /* In case the previous transfer did not complete, close it out */ - 165:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); - 166:.\Generated_Source\PSoC5/USBFS_drv.c **** - 167:.\Generated_Source\PSoC5/USBFS_drv.c **** switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK) - 168:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 169:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_RQST_TYPE_STD: - 170:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = USBFS_HandleStandardRqst(); - 171:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 172:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_RQST_TYPE_CLS: - 173:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = USBFS_DispatchClassRqst(); - 174:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 175:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_RQST_TYPE_VND: - 176:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = USBFS_HandleVendorRqst(); - 177:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 178:.\Generated_Source\PSoC5/USBFS_drv.c **** default: - 179:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = USBFS_FALSE; - 180:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 181:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 182:.\Generated_Source\PSoC5/USBFS_drv.c **** if (requestHandled == USBFS_FALSE) - 183:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 184:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 185:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 186:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 187:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 188:.\Generated_Source\PSoC5/USBFS_drv.c **** - 189:.\Generated_Source\PSoC5/USBFS_drv.c **** - 190:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 191:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_HandleIN - 192:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 193:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 194:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 195:.\Generated_Source\PSoC5/USBFS_drv.c **** * This routine handles EP0 IN transfers. - 196:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 197:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 198:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 199:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 200:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 201:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 202:.\Generated_Source\PSoC5/USBFS_drv.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 5 - - - 203:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 204:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 205:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 206:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 207:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_HandleIN(void) - 208:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 209:.\Generated_Source\PSoC5/USBFS_drv.c **** switch (USBFS_transferState) - 210:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 211:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_IDLE: - 212:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 213:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_CONTROL_READ: - 214:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ControlReadDataStage(); - 215:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 216:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_CONTROL_WRITE: - 217:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ControlWriteStatusStage(); - 218:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 219:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_NO_DATA_CONTROL: - 220:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_NoDataControlStatusStage(); - 221:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 222:.\Generated_Source\PSoC5/USBFS_drv.c **** default: /* there are no more states */ - 223:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 224:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 225:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 226:.\Generated_Source\PSoC5/USBFS_drv.c **** - 227:.\Generated_Source\PSoC5/USBFS_drv.c **** - 228:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 229:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_HandleOUT - 230:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 231:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 232:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 233:.\Generated_Source\PSoC5/USBFS_drv.c **** * This routine handles EP0 OUT transfers. - 234:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 235:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 236:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 237:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 238:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 239:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 240:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 241:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 242:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 243:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 244:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 245:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_HandleOUT(void) - 246:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 247:.\Generated_Source\PSoC5/USBFS_drv.c **** switch (USBFS_transferState) - 248:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 249:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_IDLE: - 250:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 251:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_CONTROL_READ: - 252:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ControlReadStatusStage(); - 253:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 254:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_CONTROL_WRITE: - 255:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ControlWriteDataStage(); - 256:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 257:.\Generated_Source\PSoC5/USBFS_drv.c **** case USBFS_TRANS_STATE_NO_DATA_CONTROL: - 258:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the completion block */ - 259:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 6 - - - 260:.\Generated_Source\PSoC5/USBFS_drv.c **** /* We expect no more data, so stall INs and OUTs */ - 261:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 262:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 263:.\Generated_Source\PSoC5/USBFS_drv.c **** default: /* There are no more states */ - 264:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 265:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 266:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 267:.\Generated_Source\PSoC5/USBFS_drv.c **** - 268:.\Generated_Source\PSoC5/USBFS_drv.c **** - 269:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 270:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_LoadEP0 - 271:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 272:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 273:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 274:.\Generated_Source\PSoC5/USBFS_drv.c **** * This routine loads the EP0 data registers for OUT transfers. It uses the - 275:.\Generated_Source\PSoC5/USBFS_drv.c **** * currentTD (previously initialized by the _InitControlWrite function and - 276:.\Generated_Source\PSoC5/USBFS_drv.c **** * updated for each OUT transfer, and the bLastPacketSize) to determine how - 277:.\Generated_Source\PSoC5/USBFS_drv.c **** * many uint8s to transfer on the current OUT. - 278:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 279:.\Generated_Source\PSoC5/USBFS_drv.c **** * If the number of uint8s remaining is zero and the last transfer was full, - 280:.\Generated_Source\PSoC5/USBFS_drv.c **** * we need to send a zero length packet. Otherwise we send the minimum - 281:.\Generated_Source\PSoC5/USBFS_drv.c **** * of the control endpoint size (8) or remaining number of uint8s for the - 282:.\Generated_Source\PSoC5/USBFS_drv.c **** * transaction. - 283:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 284:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 285:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 286:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 287:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 288:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 289:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 290:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 291:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferByteCount - Update the transfer byte count from the - 292:.\Generated_Source\PSoC5/USBFS_drv.c **** * last transaction. - 293:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Count - counts the data loaded to the SIE memory in - 294:.\Generated_Source\PSoC5/USBFS_drv.c **** * current packet. - 295:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_lastPacketSize - remembers the USBFS_ep0Count value for the - 296:.\Generated_Source\PSoC5/USBFS_drv.c **** * next packet. - 297:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferByteCount - sum of the previous bytes transferred - 298:.\Generated_Source\PSoC5/USBFS_drv.c **** * on previous packets(sum of USBFS_lastPacketSize) - 299:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Toggle - inverted - 300:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Mode - prepare for mode register content. - 301:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferState - set to TRANS_STATE_CONTROL_READ - 302:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 303:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 304:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 305:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 306:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 307:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_LoadEP0(void) - 308:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 27 .loc 1 308 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 32 .LVL0: - 309:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 ep0Count = 0u; - 310:.\Generated_Source\PSoC5/USBFS_drv.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 7 - - - 311:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the transfer byte count from the last transaction */ - 312:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferByteCount += USBFS_lastPacketSize; - 33 .loc 1 312 0 - 34 0000 1B4B ldr r3, .L16 - 35 0002 1C49 ldr r1, .L16+4 - 36 0004 1A88 ldrh r2, [r3, #0] - 37 0006 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 38 0008 8218 adds r2, r0, r2 - 39 000a 91B2 uxth r1, r2 - 40 000c 1980 strh r1, [r3, #0] @ movhi - 313:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Now load the next transaction */ - 314:.\Generated_Source\PSoC5/USBFS_drv.c **** while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) - 41 .loc 1 314 0 - 42 000e 1A49 ldr r1, .L16+8 - 43 .LVL1: - 44 .L2: - 45 .loc 1 314 0 is_stmt 0 discriminator 1 - 46 0010 1A4B ldr r3, .L16+12 - 47 0012 CAB2 uxtb r2, r1 - 48 0014 1888 ldrh r0, [r3, #0] - 49 0016 80B2 uxth r0, r0 - 50 0018 78B1 cbz r0, .L3 - 51 .loc 1 314 0 discriminator 2 - 52 001a 194A ldr r2, .L16+16 - 53 001c 9142 cmp r1, r2 - 54 001e 0BD0 beq .L15 - 55 .L4: - 315:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 316:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData); - 56 .loc 1 316 0 is_stmt 1 - 57 0020 5A68 ldr r2, [r3, #4] - 58 0022 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 59 0024 01F8010B strb r0, [r1], #1 - 317:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; - 60 .loc 1 317 0 - 61 0028 5A68 ldr r2, [r3, #4] - 62 002a 501C adds r0, r2, #1 - 63 002c 5860 str r0, [r3, #4] - 318:.\Generated_Source\PSoC5/USBFS_drv.c **** ep0Count++; - 319:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.count--; - 64 .loc 1 319 0 - 65 002e 1A88 ldrh r2, [r3, #0] - 66 0030 501E subs r0, r2, #1 - 67 0032 82B2 uxth r2, r0 - 68 0034 1A80 strh r2, [r3, #0] @ movhi - 69 0036 EBE7 b .L2 - 70 .L15: - 314:.\Generated_Source\PSoC5/USBFS_drv.c **** while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) - 71 .loc 1 314 0 - 72 0038 0822 movs r2, #8 - 73 .L3: - 320:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 321:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Support zero-length packet*/ - 322:.\Generated_Source\PSoC5/USBFS_drv.c **** if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) ) - 74 .loc 1 322 0 - 75 003a 0E49 ldr r1, .L16+4 - 76 003c 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 8 - - - 77 003e 082B cmp r3, #8 - 78 0040 00D0 beq .L5 - 79 .loc 1 322 0 is_stmt 0 discriminator 1 - 80 0042 5AB1 cbz r2, .L6 - 81 .L5: - 323:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 324:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the data toggle */ - 325:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; - 82 .loc 1 325 0 is_stmt 1 - 83 0044 0F48 ldr r0, .L16+20 - 84 0046 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 85 0048 81F08003 eor r3, r1, #128 - 326:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Set the Mode Register */ - 327:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; - 86 .loc 1 327 0 - 87 004c 0E49 ldr r1, .L16+24 - 325:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; - 88 .loc 1 325 0 - 89 004e 0370 strb r3, [r0, #0] - 90 .loc 1 327 0 - 91 0050 0F20 movs r0, #15 - 328:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the state (or stay the same) */ - 329:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - 92 .loc 1 329 0 - 93 0052 0E4B ldr r3, .L16+28 - 327:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; - 94 .loc 1 327 0 - 95 0054 0870 strb r0, [r1, #0] - 96 .loc 1 329 0 - 97 0056 0220 movs r0, #2 - 98 0058 1870 strb r0, [r3, #0] - 99 005a 04E0 b .L7 - 100 .L6: - 330:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 331:.\Generated_Source\PSoC5/USBFS_drv.c **** else - 332:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 333:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Expect Status Stage Out */ - 334:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; - 101 .loc 1 334 0 - 102 005c 0A49 ldr r1, .L16+24 - 335:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the state (or stay the same) */ - 336:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - 103 .loc 1 336 0 - 104 005e 0B4B ldr r3, .L16+28 - 334:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; - 105 .loc 1 334 0 - 106 0060 0220 movs r0, #2 - 107 0062 0870 strb r0, [r1, #0] - 108 .loc 1 336 0 - 109 0064 1870 strb r0, [r3, #0] - 110 .L7: - 337:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 338:.\Generated_Source\PSoC5/USBFS_drv.c **** - 339:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Save the packet size for next time */ - 340:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_lastPacketSize = ep0Count; - 111 .loc 1 340 0 - 112 0066 0349 ldr r1, .L16+4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 9 - - - 341:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Count = ep0Count; - 113 .loc 1 341 0 - 114 0068 0948 ldr r0, .L16+32 - 340:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_lastPacketSize = ep0Count; - 115 .loc 1 340 0 - 116 006a 0A70 strb r2, [r1, #0] - 117 .loc 1 341 0 - 118 006c 0270 strb r2, [r0, #0] - 119 006e 7047 bx lr - 120 .L17: - 121 .align 2 - 122 .L16: - 123 0070 00000000 .word USBFS_transferByteCount - 124 0074 00000000 .word USBFS_lastPacketSize - 125 0078 00600040 .word 1073766400 - 126 007c 00000000 .word USBFS_currentTD - 127 0080 08600040 .word 1073766408 - 128 0084 00000000 .word USBFS_ep0Toggle - 129 0088 00000000 .word USBFS_ep0Mode - 130 008c 00000000 .word USBFS_transferState - 131 0090 00000000 .word USBFS_ep0Count - 132 .cfi_endproc - 133 .LFE4: - 134 .size USBFS_LoadEP0, .-USBFS_LoadEP0 - 135 .section .text.USBFS_InitZeroLengthControlTransfer,"ax",%progbits - 136 .align 1 - 137 .global USBFS_InitZeroLengthControlTransfer - 138 .thumb - 139 .thumb_func - 140 .type USBFS_InitZeroLengthControlTransfer, %function - 141 USBFS_InitZeroLengthControlTransfer: - 142 .LFB6: - 342:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 343:.\Generated_Source\PSoC5/USBFS_drv.c **** - 344:.\Generated_Source\PSoC5/USBFS_drv.c **** - 345:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 346:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_InitControlRead - 347:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 348:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 349:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 350:.\Generated_Source\PSoC5/USBFS_drv.c **** * Initialize a control read transaction, usable to send data to the host. - 351:.\Generated_Source\PSoC5/USBFS_drv.c **** * The following global variables should be initialized before this function - 352:.\Generated_Source\PSoC5/USBFS_drv.c **** * called. To send zero length packet use InitZeroLengthControlTransfer - 353:.\Generated_Source\PSoC5/USBFS_drv.c **** * function. - 354:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 355:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 356:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 357:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 358:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 359:.\Generated_Source\PSoC5/USBFS_drv.c **** * requestHandled state. - 360:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 361:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 362:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_currentTD.count - counts of data to be sent. - 363:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_currentTD.pData - data pointer. - 364:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 365:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 366:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 10 - - - 367:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 368:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 369:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 USBFS_InitControlRead(void) - 370:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 371:.\Generated_Source\PSoC5/USBFS_drv.c **** uint16 xferCount; - 372:.\Generated_Source\PSoC5/USBFS_drv.c **** if(USBFS_currentTD.count == 0u) - 373:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 374:.\Generated_Source\PSoC5/USBFS_drv.c **** (void) USBFS_InitZeroLengthControlTransfer(); - 375:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 376:.\Generated_Source\PSoC5/USBFS_drv.c **** else - 377:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 378:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Set up the state machine */ - 379:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - 380:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Set the toggle, it gets updated in LoadEP */ - 381:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = 0u; - 382:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Initialize the Status Block */ - 383:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_InitializeStatusBlock(); - 384:.\Generated_Source\PSoC5/USBFS_drv.c **** xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - 385:.\Generated_Source\PSoC5/USBFS_drv.c **** - 386:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_currentTD.count > xferCount) - 387:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 388:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.count = xferCount; - 389:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 390:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_LoadEP0(); - 391:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 392:.\Generated_Source\PSoC5/USBFS_drv.c **** - 393:.\Generated_Source\PSoC5/USBFS_drv.c **** return(USBFS_TRUE); - 394:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 395:.\Generated_Source\PSoC5/USBFS_drv.c **** - 396:.\Generated_Source\PSoC5/USBFS_drv.c **** - 397:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 398:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_InitZeroLengthControlTransfer - 399:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 400:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 401:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 402:.\Generated_Source\PSoC5/USBFS_drv.c **** * Initialize a zero length data IN transfer. - 403:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 404:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 405:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 406:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 407:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 408:.\Generated_Source\PSoC5/USBFS_drv.c **** * requestHandled state. - 409:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 410:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 411:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE - 412:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Mode - prepare for mode register content. - 413:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferState - set to TRANS_STATE_CONTROL_READ - 414:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Count - cleared, means the zero-length packet. - 415:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_lastPacketSize - cleared. - 416:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 417:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 418:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 419:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 420:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 421:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 USBFS_InitZeroLengthControlTransfer(void) - 422:.\Generated_Source\PSoC5/USBFS_drv.c **** - 423:.\Generated_Source\PSoC5/USBFS_drv.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 11 - - - 143 .loc 1 423 0 - 144 .cfi_startproc - 145 @ args = 0, pretend = 0, frame = 0 - 146 @ frame_needed = 0, uses_anonymous_args = 0 - 147 @ link register save eliminated. - 424:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the state */ - 425:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - 148 .loc 1 425 0 - 149 0000 074B ldr r3, .L19 - 150 0002 0222 movs r2, #2 - 151 0004 1A70 strb r2, [r3, #0] - 426:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Set the data toggle */ - 427:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 152 .loc 1 427 0 - 153 0006 0749 ldr r1, .L19+4 - 428:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Set the Mode Register */ - 429:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; - 154 .loc 1 429 0 - 155 0008 074B ldr r3, .L19+8 - 427:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 156 .loc 1 427 0 - 157 000a 8020 movs r0, #128 - 158 .loc 1 429 0 - 159 000c 0F22 movs r2, #15 - 427:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 160 .loc 1 427 0 - 161 000e 0870 strb r0, [r1, #0] - 162 .loc 1 429 0 - 163 0010 1A70 strb r2, [r3, #0] - 430:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Save the packet size for next time */ - 431:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_lastPacketSize = 0u; - 164 .loc 1 431 0 - 165 0012 0649 ldr r1, .L19+12 - 432:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Count = 0u; - 166 .loc 1 432 0 - 167 0014 064A ldr r2, .L19+16 - 431:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_lastPacketSize = 0u; - 168 .loc 1 431 0 - 169 0016 0020 movs r0, #0 - 170 0018 0870 strb r0, [r1, #0] - 171 .loc 1 432 0 - 172 001a 1070 strb r0, [r2, #0] - 433:.\Generated_Source\PSoC5/USBFS_drv.c **** - 434:.\Generated_Source\PSoC5/USBFS_drv.c **** return(USBFS_TRUE); - 435:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 173 .loc 1 435 0 - 174 001c 0120 movs r0, #1 - 175 001e 7047 bx lr - 176 .L20: - 177 .align 2 - 178 .L19: - 179 0020 00000000 .word USBFS_transferState - 180 0024 00000000 .word USBFS_ep0Toggle - 181 0028 00000000 .word USBFS_ep0Mode - 182 002c 00000000 .word USBFS_lastPacketSize - 183 0030 00000000 .word USBFS_ep0Count - 184 .cfi_endproc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 12 - - - 185 .LFE6: - 186 .size USBFS_InitZeroLengthControlTransfer, .-USBFS_InitZeroLengthControlTransfer - 187 .section .text.USBFS_ControlReadDataStage,"ax",%progbits - 188 .align 1 - 189 .global USBFS_ControlReadDataStage - 190 .thumb - 191 .thumb_func - 192 .type USBFS_ControlReadDataStage, %function - 193 USBFS_ControlReadDataStage: - 194 .LFB7: - 436:.\Generated_Source\PSoC5/USBFS_drv.c **** - 437:.\Generated_Source\PSoC5/USBFS_drv.c **** - 438:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 439:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_ControlReadDataStage - 440:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 441:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 442:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 443:.\Generated_Source\PSoC5/USBFS_drv.c **** * Handle the Data Stage of a control read transfer. - 444:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 445:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 446:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 447:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 448:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 449:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 450:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 451:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 452:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 453:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 454:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 455:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_ControlReadDataStage(void) - 456:.\Generated_Source\PSoC5/USBFS_drv.c **** - 457:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 195 .loc 1 457 0 - 196 .cfi_startproc - 197 @ args = 0, pretend = 0, frame = 0 - 198 @ frame_needed = 0, uses_anonymous_args = 0 - 199 @ link register save eliminated. - 458:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_LoadEP0(); - 459:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 200 .loc 1 459 0 - 458:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_LoadEP0(); - 201 .loc 1 458 0 - 202 0000 FFF7FEBF b USBFS_LoadEP0 - 203 .LVL2: - 204 .cfi_endproc - 205 .LFE7: - 206 .size USBFS_ControlReadDataStage, .-USBFS_ControlReadDataStage - 207 .section .text.USBFS_ControlWriteDataStage,"ax",%progbits - 208 .align 1 - 209 .global USBFS_ControlWriteDataStage - 210 .thumb - 211 .thumb_func - 212 .type USBFS_ControlWriteDataStage, %function - 213 USBFS_ControlWriteDataStage: - 214 .LFB10: - 460:.\Generated_Source\PSoC5/USBFS_drv.c **** - 461:.\Generated_Source\PSoC5/USBFS_drv.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 13 - - - 462:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 463:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_ControlReadStatusStage - 464:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 465:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 466:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 467:.\Generated_Source\PSoC5/USBFS_drv.c **** * Handle the Status Stage of a control read transfer. - 468:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 469:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 470:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 471:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 472:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 473:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 474:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 475:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 476:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_USBFS_transferByteCount - updated with last packet size. - 477:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferState - set to TRANS_STATE_IDLE. - 478:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Mode - set to MODE_STALL_IN_OUT. - 479:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 480:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 481:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 482:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 483:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 484:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_ControlReadStatusStage(void) - 485:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 486:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the transfer byte count */ - 487:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferByteCount += USBFS_lastPacketSize; - 488:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Go Idle */ - 489:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 490:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the completion block */ - 491:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - 492:.\Generated_Source\PSoC5/USBFS_drv.c **** /* We expect no more data, so stall INs and OUTs */ - 493:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 494:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 495:.\Generated_Source\PSoC5/USBFS_drv.c **** - 496:.\Generated_Source\PSoC5/USBFS_drv.c **** - 497:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 498:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_InitControlWrite - 499:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 500:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 501:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 502:.\Generated_Source\PSoC5/USBFS_drv.c **** * Initialize a control write transaction - 503:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 504:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 505:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 506:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 507:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 508:.\Generated_Source\PSoC5/USBFS_drv.c **** * requestHandled state. - 509:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 510:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 511:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE - 512:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE - 513:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN - 514:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 515:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 516:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 517:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 518:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 14 - - - 519:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 USBFS_InitControlWrite(void) - 520:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 521:.\Generated_Source\PSoC5/USBFS_drv.c **** uint16 xferCount; - 522:.\Generated_Source\PSoC5/USBFS_drv.c **** - 523:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Set up the state machine */ - 524:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; - 525:.\Generated_Source\PSoC5/USBFS_drv.c **** /* This might not be necessary */ - 526:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 527:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Initialize the Status Block */ - 528:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_InitializeStatusBlock(); - 529:.\Generated_Source\PSoC5/USBFS_drv.c **** - 530:.\Generated_Source\PSoC5/USBFS_drv.c **** xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - 531:.\Generated_Source\PSoC5/USBFS_drv.c **** - 532:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_currentTD.count > xferCount) - 533:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 534:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.count = xferCount; - 535:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 536:.\Generated_Source\PSoC5/USBFS_drv.c **** - 537:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Expect Data or Status Stage */ - 538:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; - 539:.\Generated_Source\PSoC5/USBFS_drv.c **** - 540:.\Generated_Source\PSoC5/USBFS_drv.c **** return(USBFS_TRUE); - 541:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 542:.\Generated_Source\PSoC5/USBFS_drv.c **** - 543:.\Generated_Source\PSoC5/USBFS_drv.c **** - 544:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 545:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_ControlWriteDataStage - 546:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 547:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 548:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 549:.\Generated_Source\PSoC5/USBFS_drv.c **** * Handle the Data Stage of a control write transfer - 550:.\Generated_Source\PSoC5/USBFS_drv.c **** * 1. Get the data (We assume the destination was validated previously) - 551:.\Generated_Source\PSoC5/USBFS_drv.c **** * 2. Update the count and data toggle - 552:.\Generated_Source\PSoC5/USBFS_drv.c **** * 3. Update the mode register for the next transaction - 553:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 554:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 555:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 556:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 557:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 558:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 559:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 560:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 561:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferByteCount - Update the transfer byte count from the - 562:.\Generated_Source\PSoC5/USBFS_drv.c **** * last transaction. - 563:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Count - counts the data loaded from the SIE memory - 564:.\Generated_Source\PSoC5/USBFS_drv.c **** * in current packet. - 565:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferByteCount - sum of the previous bytes transferred - 566:.\Generated_Source\PSoC5/USBFS_drv.c **** * on previous packets(sum of USBFS_lastPacketSize) - 567:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Toggle - inverted - 568:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. - 569:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 570:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 571:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 572:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 573:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 574:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_ControlWriteDataStage(void) - 575:.\Generated_Source\PSoC5/USBFS_drv.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 15 - - - 215 .loc 1 575 0 - 216 .cfi_startproc - 217 @ args = 0, pretend = 0, frame = 0 - 218 @ frame_needed = 0, uses_anonymous_args = 0 - 219 .LVL3: - 220 0000 10B5 push {r4, lr} - 221 .LCFI0: - 222 .cfi_def_cfa_offset 8 - 223 .cfi_offset 4, -8 - 224 .cfi_offset 14, -4 - 576:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 ep0Count; - 577:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 regIndex = 0u; - 578:.\Generated_Source\PSoC5/USBFS_drv.c **** - 579:.\Generated_Source\PSoC5/USBFS_drv.c **** ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - - 225 .loc 1 579 0 - 226 0002 154B ldr r3, .L29 - 227 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 580:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_EPX_CNTX_CRC_COUNT; - 581:.\Generated_Source\PSoC5/USBFS_drv.c **** - 582:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferByteCount += ep0Count; - 228 .loc 1 582 0 - 229 0006 154B ldr r3, .L29+4 - 579:.\Generated_Source\PSoC5/USBFS_drv.c **** ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - - 230 .loc 1 579 0 - 231 0008 02F00F00 and r0, r2, #15 - 232 000c 811E subs r1, r0, #2 - 233 .loc 1 582 0 - 234 000e 1888 ldrh r0, [r3, #0] - 579:.\Generated_Source\PSoC5/USBFS_drv.c **** ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - - 235 .loc 1 579 0 - 236 0010 CAB2 uxtb r2, r1 - 237 .LVL4: - 238 .loc 1 582 0 - 239 0012 1118 adds r1, r2, r0 - 240 .LVL5: - 241 0014 88B2 uxth r0, r1 - 583:.\Generated_Source\PSoC5/USBFS_drv.c **** - 584:.\Generated_Source\PSoC5/USBFS_drv.c **** while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) - 242 .loc 1 584 0 - 243 0016 1249 ldr r1, .L29+8 - 582:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferByteCount += ep0Count; - 244 .loc 1 582 0 - 245 0018 1880 strh r0, [r3, #0] @ movhi - 246 .LVL6: - 247 .L23: - 248 .loc 1 584 0 discriminator 1 - 249 001a 124B ldr r3, .L29+12 - 250 001c 1888 ldrh r0, [r3, #0] - 251 001e 80B2 uxth r0, r0 - 252 0020 70B1 cbz r0, .L24 - 253 .loc 1 584 0 is_stmt 0 discriminator 2 - 254 0022 6AB1 cbz r2, .L24 - 255 .L25: - 585:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 586:.\Generated_Source\PSoC5/USBFS_drv.c **** *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); - 256 .loc 1 586 0 is_stmt 1 - 257 0024 5868 ldr r0, [r3, #4] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 16 - - - 258 0026 11F8014B ldrb r4, [r1], #1 @ zero_extendqisi2 - 587:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; - 588:.\Generated_Source\PSoC5/USBFS_drv.c **** regIndex++; - 589:.\Generated_Source\PSoC5/USBFS_drv.c **** ep0Count--; - 259 .loc 1 589 0 - 260 002a 013A subs r2, r2, #1 - 261 .LVL7: - 586:.\Generated_Source\PSoC5/USBFS_drv.c **** *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); - 262 .loc 1 586 0 - 263 002c 0470 strb r4, [r0, #0] - 587:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; - 264 .loc 1 587 0 - 265 002e 5868 ldr r0, [r3, #4] - 266 .loc 1 589 0 - 267 0030 D2B2 uxtb r2, r2 - 268 .LVL8: - 587:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; - 269 .loc 1 587 0 - 270 0032 0130 adds r0, r0, #1 - 271 0034 5860 str r0, [r3, #4] - 272 .LVL9: - 590:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.count--; - 273 .loc 1 590 0 - 274 0036 1888 ldrh r0, [r3, #0] - 275 0038 0138 subs r0, r0, #1 - 276 003a 80B2 uxth r0, r0 - 277 003c 1880 strh r0, [r3, #0] @ movhi - 278 003e ECE7 b .L23 - 279 .L24: - 591:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 592:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Count = ep0Count; - 280 .loc 1 592 0 - 281 0040 0949 ldr r1, .L29+16 - 593:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the data toggle */ - 594:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; - 282 .loc 1 594 0 - 283 0042 0A4B ldr r3, .L29+20 - 592:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Count = ep0Count; - 284 .loc 1 592 0 - 285 0044 0A70 strb r2, [r1, #0] - 286 .loc 1 594 0 - 287 0046 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 288 .LVL10: - 595:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Expect Data or Status Stage */ - 596:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; - 289 .loc 1 596 0 - 290 0048 0B21 movs r1, #11 - 594:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; - 291 .loc 1 594 0 - 292 004a 82F08000 eor r0, r2, #128 - 293 004e 1870 strb r0, [r3, #0] - 294 .loc 1 596 0 - 295 0050 074B ldr r3, .L29+24 - 296 0052 1970 strb r1, [r3, #0] - 297 0054 10BD pop {r4, pc} - 298 .L30: - 299 0056 00BF .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 17 - - - 300 .L29: - 301 0058 29600040 .word 1073766441 - 302 005c 00000000 .word USBFS_transferByteCount - 303 0060 00600040 .word 1073766400 - 304 0064 00000000 .word USBFS_currentTD - 305 0068 00000000 .word USBFS_ep0Count - 306 006c 00000000 .word USBFS_ep0Toggle - 307 0070 00000000 .word USBFS_ep0Mode - 308 .cfi_endproc - 309 .LFE10: - 310 .size USBFS_ControlWriteDataStage, .-USBFS_ControlWriteDataStage - 311 .section .text.USBFS_InitNoDataControlTransfer,"ax",%progbits - 312 .align 1 - 313 .global USBFS_InitNoDataControlTransfer - 314 .thumb - 315 .thumb_func - 316 .type USBFS_InitNoDataControlTransfer, %function - 317 USBFS_InitNoDataControlTransfer: - 318 .LFB12: - 597:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 598:.\Generated_Source\PSoC5/USBFS_drv.c **** - 599:.\Generated_Source\PSoC5/USBFS_drv.c **** - 600:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 601:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_ControlWriteStatusStage - 602:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 603:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 604:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 605:.\Generated_Source\PSoC5/USBFS_drv.c **** * Handle the Status Stage of a control write transfer - 606:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 607:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 608:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 609:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 610:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 611:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 612:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 613:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 614:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferState - set to TRANS_STATE_IDLE. - 615:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. - 616:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 617:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 618:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 619:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 620:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 621:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_ControlWriteStatusStage(void) - 622:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 623:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Go Idle */ - 624:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 625:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the completion block */ - 626:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - 627:.\Generated_Source\PSoC5/USBFS_drv.c **** /* We expect no more data, so stall INs and OUTs */ - 628:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 629:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 630:.\Generated_Source\PSoC5/USBFS_drv.c **** - 631:.\Generated_Source\PSoC5/USBFS_drv.c **** - 632:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 633:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_InitNoDataControlTransfer - 634:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 18 - - - 635:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 636:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 637:.\Generated_Source\PSoC5/USBFS_drv.c **** * Initialize a no data control transfer - 638:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 639:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 640:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 641:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 642:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 643:.\Generated_Source\PSoC5/USBFS_drv.c **** * requestHandled state. - 644:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 645:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 646:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. - 647:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. - 648:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Count - cleared. - 649:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE - 650:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 651:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 652:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 653:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 654:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 655:.\Generated_Source\PSoC5/USBFS_drv.c **** uint8 USBFS_InitNoDataControlTransfer(void) - 656:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 319 .loc 1 656 0 - 320 .cfi_startproc - 321 @ args = 0, pretend = 0, frame = 0 - 322 @ frame_needed = 0, uses_anonymous_args = 0 - 323 @ link register save eliminated. - 657:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; - 324 .loc 1 657 0 - 325 0000 064A ldr r2, .L32 - 658:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; - 326 .loc 1 658 0 - 327 0002 0748 ldr r0, .L32+4 - 657:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; - 328 .loc 1 657 0 - 329 0004 0623 movs r3, #6 - 330 0006 1370 strb r3, [r2, #0] - 331 .loc 1 658 0 - 332 0008 0370 strb r3, [r0, #0] - 659:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 333 .loc 1 659 0 - 334 000a 064B ldr r3, .L32+8 - 660:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Count = 0u; - 335 .loc 1 660 0 - 336 000c 0648 ldr r0, .L32+12 - 659:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 337 .loc 1 659 0 - 338 000e 8021 movs r1, #128 - 339 .loc 1 660 0 - 340 0010 0022 movs r2, #0 - 659:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 341 .loc 1 659 0 - 342 0012 1970 strb r1, [r3, #0] - 343 .loc 1 660 0 - 344 0014 0270 strb r2, [r0, #0] - 661:.\Generated_Source\PSoC5/USBFS_drv.c **** - 662:.\Generated_Source\PSoC5/USBFS_drv.c **** return(USBFS_TRUE); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 19 - - - 663:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 345 .loc 1 663 0 - 346 0016 0120 movs r0, #1 - 347 0018 7047 bx lr - 348 .L33: - 349 001a 00BF .align 2 - 350 .L32: - 351 001c 00000000 .word USBFS_transferState - 352 0020 00000000 .word USBFS_ep0Mode - 353 0024 00000000 .word USBFS_ep0Toggle - 354 0028 00000000 .word USBFS_ep0Count - 355 .cfi_endproc - 356 .LFE12: - 357 .size USBFS_InitNoDataControlTransfer, .-USBFS_InitNoDataControlTransfer - 358 .section .text.USBFS_UpdateStatusBlock,"ax",%progbits - 359 .align 1 - 360 .global USBFS_UpdateStatusBlock - 361 .thumb - 362 .thumb_func - 363 .type USBFS_UpdateStatusBlock, %function - 364 USBFS_UpdateStatusBlock: - 365 .LFB14: - 664:.\Generated_Source\PSoC5/USBFS_drv.c **** - 665:.\Generated_Source\PSoC5/USBFS_drv.c **** - 666:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 667:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_NoDataControlStatusStage - 668:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 669:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 670:.\Generated_Source\PSoC5/USBFS_drv.c **** * Handle the Status Stage of a no data control transfer. - 671:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 672:.\Generated_Source\PSoC5/USBFS_drv.c **** * SET_ADDRESS is special, since we need to receive the status stage with - 673:.\Generated_Source\PSoC5/USBFS_drv.c **** * the old address. - 674:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 675:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 676:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 677:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 678:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 679:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 680:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 681:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 682:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferState - set to TRANS_STATE_IDLE. - 683:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Mode - set to MODE_STALL_IN_OUT. - 684:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE - 685:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_deviceAddress - used to set new address and cleared - 686:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 687:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 688:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 689:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 690:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 691:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_NoDataControlStatusStage(void) - 692:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 693:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Change the USB address register if we got a SET_ADDRESS. */ - 694:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_deviceAddress != 0u) - 695:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 696:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); - 697:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_deviceAddress = 0u; - 698:.\Generated_Source\PSoC5/USBFS_drv.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 20 - - - 699:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Go Idle */ - 700:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 701:.\Generated_Source\PSoC5/USBFS_drv.c **** /* Update the completion block */ - 702:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - 703:.\Generated_Source\PSoC5/USBFS_drv.c **** /* We expect no more data, so stall INs and OUTs */ - 704:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 705:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 706:.\Generated_Source\PSoC5/USBFS_drv.c **** - 707:.\Generated_Source\PSoC5/USBFS_drv.c **** - 708:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 709:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_UpdateStatusBlock - 710:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 711:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 712:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 713:.\Generated_Source\PSoC5/USBFS_drv.c **** * Update the Completion Status Block for a Request. The block is updated - 714:.\Generated_Source\PSoC5/USBFS_drv.c **** * with the completion code the USBFS_transferByteCount. The - 715:.\Generated_Source\PSoC5/USBFS_drv.c **** * StatusBlock Pointer is set to NULL. - 716:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 717:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 718:.\Generated_Source\PSoC5/USBFS_drv.c **** * completionCode - status. - 719:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 720:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 721:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 722:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 723:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 724:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_currentTD.pStatusBlock->status - updated by the - 725:.\Generated_Source\PSoC5/USBFS_drv.c **** * completionCode parameter. - 726:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_currentTD.pStatusBlock->length - updated. - 727:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_currentTD.pStatusBlock - cleared. - 728:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 729:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 730:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 731:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 732:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 733:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_UpdateStatusBlock(uint8 completionCode) - 734:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 366 .loc 1 734 0 - 367 .cfi_startproc - 368 @ args = 0, pretend = 0, frame = 0 - 369 @ frame_needed = 0, uses_anonymous_args = 0 - 370 @ link register save eliminated. - 371 .LVL11: - 735:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_currentTD.pStatusBlock != NULL) - 372 .loc 1 735 0 - 373 0000 054B ldr r3, .L39 - 374 0002 9A68 ldr r2, [r3, #8] - 375 0004 3AB1 cbz r2, .L34 - 736:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 737:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pStatusBlock->status = completionCode; - 376 .loc 1 737 0 - 377 0006 9968 ldr r1, [r3, #8] - 738:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pStatusBlock->length = USBFS_transferByteCount; - 378 .loc 1 738 0 - 379 0008 044A ldr r2, .L39+4 - 737:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pStatusBlock->status = completionCode; - 380 .loc 1 737 0 - 381 000a 0870 strb r0, [r1, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 21 - - - 382 .loc 1 738 0 - 383 000c 9868 ldr r0, [r3, #8] - 384 .LVL12: - 385 000e 1188 ldrh r1, [r2, #0] - 386 .LVL13: - 387 0010 4180 strh r1, [r0, #2] @ movhi - 739:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pStatusBlock = NULL; - 388 .loc 1 739 0 - 389 0012 0020 movs r0, #0 - 390 0014 9860 str r0, [r3, #8] - 391 .L34: - 392 0016 7047 bx lr - 393 .L40: - 394 .align 2 - 395 .L39: - 396 0018 00000000 .word USBFS_currentTD - 397 001c 00000000 .word USBFS_transferByteCount - 398 .cfi_endproc - 399 .LFE14: - 400 .size USBFS_UpdateStatusBlock, .-USBFS_UpdateStatusBlock - 401 .section .text.USBFS_NoDataControlStatusStage,"ax",%progbits - 402 .align 1 - 403 .global USBFS_NoDataControlStatusStage - 404 .thumb - 405 .thumb_func - 406 .type USBFS_NoDataControlStatusStage, %function - 407 USBFS_NoDataControlStatusStage: - 408 .LFB13: - 692:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 409 .loc 1 692 0 - 410 .cfi_startproc - 411 @ args = 0, pretend = 0, frame = 0 - 412 @ frame_needed = 0, uses_anonymous_args = 0 - 413 0000 08B5 push {r3, lr} - 414 .LCFI1: - 415 .cfi_def_cfa_offset 8 - 416 .cfi_offset 3, -8 - 417 .cfi_offset 14, -4 - 694:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_deviceAddress != 0u) - 418 .loc 1 694 0 - 419 0002 0A4B ldr r3, .L46 - 420 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 421 0006 32B1 cbz r2, .L42 - 696:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); - 422 .loc 1 696 0 - 423 0008 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 424 000a 094A ldr r2, .L46+4 - 425 000c 41F08000 orr r0, r1, #128 - 697:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_deviceAddress = 0u; - 426 .loc 1 697 0 - 427 0010 0021 movs r1, #0 - 696:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); - 428 .loc 1 696 0 - 429 0012 1070 strb r0, [r2, #0] - 697:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_deviceAddress = 0u; - 430 .loc 1 697 0 - 431 0014 1970 strb r1, [r3, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 22 - - - 432 .L42: - 700:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 433 .loc 1 700 0 - 434 0016 074B ldr r3, .L46+8 - 435 0018 0020 movs r0, #0 - 436 001a 1870 strb r0, [r3, #0] - 702:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - 437 .loc 1 702 0 - 438 001c 0120 movs r0, #1 - 439 001e FFF7FEFF bl USBFS_UpdateStatusBlock - 440 .LVL14: - 704:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 441 .loc 1 704 0 - 442 0022 0549 ldr r1, .L46+12 - 443 0024 0322 movs r2, #3 - 444 0026 0A70 strb r2, [r1, #0] - 445 0028 08BD pop {r3, pc} - 446 .L47: - 447 002a 00BF .align 2 - 448 .L46: - 449 002c 00000000 .word USBFS_deviceAddress - 450 0030 08600040 .word 1073766408 - 451 0034 00000000 .word USBFS_transferState - 452 0038 00000000 .word USBFS_ep0Mode - 453 .cfi_endproc - 454 .LFE13: - 455 .size USBFS_NoDataControlStatusStage, .-USBFS_NoDataControlStatusStage - 456 .section .text.USBFS_ControlWriteStatusStage,"ax",%progbits - 457 .align 1 - 458 .global USBFS_ControlWriteStatusStage - 459 .thumb - 460 .thumb_func - 461 .type USBFS_ControlWriteStatusStage, %function - 462 USBFS_ControlWriteStatusStage: - 463 .LFB11: - 622:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 464 .loc 1 622 0 - 465 .cfi_startproc - 466 @ args = 0, pretend = 0, frame = 0 - 467 @ frame_needed = 0, uses_anonymous_args = 0 - 468 0000 08B5 push {r3, lr} - 469 .LCFI2: - 470 .cfi_def_cfa_offset 8 - 471 .cfi_offset 3, -8 - 472 .cfi_offset 14, -4 - 624:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 473 .loc 1 624 0 - 474 0002 054B ldr r3, .L49 - 475 0004 0022 movs r2, #0 - 626:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - 476 .loc 1 626 0 - 477 0006 0120 movs r0, #1 - 624:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 478 .loc 1 624 0 - 479 0008 1A70 strb r2, [r3, #0] - 626:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - 480 .loc 1 626 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 23 - - - 481 000a FFF7FEFF bl USBFS_UpdateStatusBlock - 482 .LVL15: - 628:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 483 .loc 1 628 0 - 484 000e 0349 ldr r1, .L49+4 - 485 0010 0320 movs r0, #3 - 486 0012 0870 strb r0, [r1, #0] - 487 0014 08BD pop {r3, pc} - 488 .L50: - 489 0016 00BF .align 2 - 490 .L49: - 491 0018 00000000 .word USBFS_transferState - 492 001c 00000000 .word USBFS_ep0Mode - 493 .cfi_endproc - 494 .LFE11: - 495 .size USBFS_ControlWriteStatusStage, .-USBFS_ControlWriteStatusStage - 496 .section .text.USBFS_HandleIN,"ax",%progbits - 497 .align 1 - 498 .global USBFS_HandleIN - 499 .thumb - 500 .thumb_func - 501 .type USBFS_HandleIN, %function - 502 USBFS_HandleIN: - 503 .LFB2: - 208:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 504 .loc 1 208 0 - 505 .cfi_startproc - 506 @ args = 0, pretend = 0, frame = 0 - 507 @ frame_needed = 0, uses_anonymous_args = 0 - 508 @ link register save eliminated. - 209:.\Generated_Source\PSoC5/USBFS_drv.c **** switch (USBFS_transferState) - 509 .loc 1 209 0 - 510 0000 074B ldr r3, .L57 - 511 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 512 0004 0428 cmp r0, #4 - 513 0006 05D0 beq .L54 - 514 0008 0628 cmp r0, #6 - 515 000a 05D0 beq .L55 - 516 000c 0228 cmp r0, #2 - 517 000e 05D1 bne .L56 - 225:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 518 .loc 1 225 0 - 519 .LBB4: - 520 .LBB5: - 458:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_LoadEP0(); - 521 .loc 1 458 0 - 522 0010 FFF7FEBF b USBFS_LoadEP0 - 523 .LVL16: - 524 .L54: - 525 .LBE5: - 526 .LBE4: - 225:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 527 .loc 1 225 0 - 217:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ControlWriteStatusStage(); - 528 .loc 1 217 0 - 529 0014 FFF7FEBF b USBFS_ControlWriteStatusStage - 530 .LVL17: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 24 - - - 531 .L55: - 225:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 532 .loc 1 225 0 - 220:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_NoDataControlStatusStage(); - 533 .loc 1 220 0 - 534 0018 FFF7FEBF b USBFS_NoDataControlStatusStage - 535 .LVL18: - 536 .L56: - 537 001c 7047 bx lr - 538 .L58: - 539 001e 00BF .align 2 - 540 .L57: - 541 0020 00000000 .word USBFS_transferState - 542 .cfi_endproc - 543 .LFE2: - 544 .size USBFS_HandleIN, .-USBFS_HandleIN - 545 .section .text.USBFS_ControlReadStatusStage,"ax",%progbits - 546 .align 1 - 547 .global USBFS_ControlReadStatusStage - 548 .thumb - 549 .thumb_func - 550 .type USBFS_ControlReadStatusStage, %function - 551 USBFS_ControlReadStatusStage: - 552 .LFB8: - 485:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 553 .loc 1 485 0 - 554 .cfi_startproc - 555 @ args = 0, pretend = 0, frame = 0 - 556 @ frame_needed = 0, uses_anonymous_args = 0 - 557 0000 08B5 push {r3, lr} - 558 .LCFI3: - 559 .cfi_def_cfa_offset 8 - 560 .cfi_offset 3, -8 - 561 .cfi_offset 14, -4 - 487:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferByteCount += USBFS_lastPacketSize; - 562 .loc 1 487 0 - 563 0002 0849 ldr r1, .L60 - 564 0004 084B ldr r3, .L60+4 - 565 0006 1A88 ldrh r2, [r3, #0] - 566 0008 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 567 000a 8218 adds r2, r0, r2 - 568 000c 91B2 uxth r1, r2 - 569 000e 1980 strh r1, [r3, #0] @ movhi - 489:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_IDLE; - 570 .loc 1 489 0 - 571 0010 064B ldr r3, .L60+8 - 572 0012 0020 movs r0, #0 - 573 0014 1870 strb r0, [r3, #0] - 491:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - 574 .loc 1 491 0 - 575 0016 0120 movs r0, #1 - 576 0018 FFF7FEFF bl USBFS_UpdateStatusBlock - 577 .LVL19: - 493:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 578 .loc 1 493 0 - 579 001c 0449 ldr r1, .L60+12 - 580 001e 0322 movs r2, #3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 25 - - - 581 0020 0A70 strb r2, [r1, #0] - 582 0022 08BD pop {r3, pc} - 583 .L61: - 584 .align 2 - 585 .L60: - 586 0024 00000000 .word USBFS_lastPacketSize - 587 0028 00000000 .word USBFS_transferByteCount - 588 002c 00000000 .word USBFS_transferState - 589 0030 00000000 .word USBFS_ep0Mode - 590 .cfi_endproc - 591 .LFE8: - 592 .size USBFS_ControlReadStatusStage, .-USBFS_ControlReadStatusStage - 593 .section .text.USBFS_HandleOUT,"ax",%progbits - 594 .align 1 - 595 .global USBFS_HandleOUT - 596 .thumb - 597 .thumb_func - 598 .type USBFS_HandleOUT, %function - 599 USBFS_HandleOUT: - 600 .LFB3: - 246:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 601 .loc 1 246 0 - 602 .cfi_startproc - 603 @ args = 0, pretend = 0, frame = 0 - 604 @ frame_needed = 0, uses_anonymous_args = 0 - 605 0000 08B5 push {r3, lr} - 606 .LCFI4: - 607 .cfi_def_cfa_offset 8 - 608 .cfi_offset 3, -8 - 609 .cfi_offset 14, -4 - 247:.\Generated_Source\PSoC5/USBFS_drv.c **** switch (USBFS_transferState) - 610 .loc 1 247 0 - 611 0002 0B4B ldr r3, .L67 - 612 0004 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 613 0006 0428 cmp r0, #4 - 614 0008 07D0 beq .L65 - 615 000a 0628 cmp r0, #6 - 616 000c 09D0 beq .L66 - 617 000e 0228 cmp r0, #2 - 618 0010 0DD1 bne .L62 - 266:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 619 .loc 1 266 0 - 620 0012 BDE80840 pop {r3, lr} - 252:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ControlReadStatusStage(); - 621 .loc 1 252 0 - 622 0016 FFF7FEBF b USBFS_ControlReadStatusStage - 623 .LVL20: - 624 .L65: - 266:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 625 .loc 1 266 0 - 626 001a BDE80840 pop {r3, lr} - 255:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ControlWriteDataStage(); - 627 .loc 1 255 0 - 628 001e FFF7FEBF b USBFS_ControlWriteDataStage - 629 .LVL21: - 630 .L66: - 259:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 26 - - - 631 .loc 1 259 0 - 632 0022 0320 movs r0, #3 - 633 0024 FFF7FEFF bl USBFS_UpdateStatusBlock - 634 .LVL22: - 261:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 635 .loc 1 261 0 - 636 0028 0249 ldr r1, .L67+4 - 637 002a 0322 movs r2, #3 - 638 002c 0A70 strb r2, [r1, #0] - 639 .L62: - 640 002e 08BD pop {r3, pc} - 641 .L68: - 642 .align 2 - 643 .L67: - 644 0030 00000000 .word USBFS_transferState - 645 0034 00000000 .word USBFS_ep0Mode - 646 .cfi_endproc - 647 .LFE3: - 648 .size USBFS_HandleOUT, .-USBFS_HandleOUT - 649 .section .text.USBFS_HandleSetup,"ax",%progbits - 650 .align 1 - 651 .global USBFS_HandleSetup - 652 .thumb - 653 .thumb_func - 654 .type USBFS_HandleSetup, %function - 655 USBFS_HandleSetup: - 656 .LFB1: - 152:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 657 .loc 1 152 0 - 658 .cfi_startproc - 659 @ args = 0, pretend = 0, frame = 0 - 660 @ frame_needed = 0, uses_anonymous_args = 0 - 661 0000 08B5 push {r3, lr} - 662 .LCFI5: - 663 .cfi_def_cfa_offset 8 - 664 .cfi_offset 3, -8 - 665 .cfi_offset 14, -4 - 155:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - 666 .loc 1 155 0 - 667 0002 114B ldr r3, .L77 - 668 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 669 .LVL23: - 156:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */ - 670 .loc 1 156 0 - 671 0006 1A70 strb r2, [r3, #0] - 157:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */ - 672 .loc 1 157 0 - 673 0008 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 674 .LVL24: - 158:.\Generated_Source\PSoC5/USBFS_drv.c **** if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) - 675 .loc 1 158 0 - 676 000a 0206 lsls r2, r0, #24 - 677 000c 02D5 bpl .L70 - 160:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mo - 678 .loc 1 160 0 - 679 000e 0F4B ldr r3, .L77+4 - 680 0010 1870 strb r0, [r3, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 27 - - - 681 0012 08BD pop {r3, pc} - 682 .L70: - 165:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); - 683 .loc 1 165 0 - 684 0014 0220 movs r0, #2 - 685 .LVL25: - 686 0016 FFF7FEFF bl USBFS_UpdateStatusBlock - 687 .LVL26: - 167:.\Generated_Source\PSoC5/USBFS_drv.c **** switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK) - 688 .loc 1 167 0 - 689 001a 0D49 ldr r1, .L77+8 - 690 001c 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 691 001e 03F06002 and r2, r3, #96 - 692 0022 202A cmp r2, #32 - 693 0024 05D0 beq .L74 - 694 0026 402A cmp r2, #64 - 695 0028 06D0 beq .L75 - 696 002a 42B9 cbnz r2, .L72 - 170:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = USBFS_HandleStandardRqst(); - 697 .loc 1 170 0 - 698 002c FFF7FEFF bl USBFS_HandleStandardRqst - 699 .LVL27: - 171:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 700 .loc 1 171 0 - 701 0030 04E0 b .L76 - 702 .LVL28: - 703 .L74: - 173:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = USBFS_DispatchClassRqst(); - 704 .loc 1 173 0 - 705 0032 FFF7FEFF bl USBFS_DispatchClassRqst - 706 .LVL29: - 174:.\Generated_Source\PSoC5/USBFS_drv.c **** break; - 707 .loc 1 174 0 - 708 0036 01E0 b .L76 - 709 .LVL30: - 710 .L75: - 176:.\Generated_Source\PSoC5/USBFS_drv.c **** requestHandled = USBFS_HandleVendorRqst(); - 711 .loc 1 176 0 - 712 0038 FFF7FEFF bl USBFS_HandleVendorRqst - 713 .LVL31: - 714 .L76: - 182:.\Generated_Source\PSoC5/USBFS_drv.c **** if (requestHandled == USBFS_FALSE) - 715 .loc 1 182 0 - 716 003c 10B9 cbnz r0, .L69 - 717 .LVL32: - 718 .L72: - 184:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - 719 .loc 1 184 0 - 720 003e 0349 ldr r1, .L77+4 - 721 0040 0320 movs r0, #3 - 722 0042 0870 strb r0, [r1, #0] - 723 .L69: - 724 0044 08BD pop {r3, pc} - 725 .L78: - 726 0046 00BF .align 2 - 727 .L77: - 728 0048 28600040 .word 1073766440 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 28 - - - 729 004c 00000000 .word USBFS_ep0Mode - 730 0050 00600040 .word 1073766400 - 731 .cfi_endproc - 732 .LFE1: - 733 .size USBFS_HandleSetup, .-USBFS_HandleSetup - 734 .section .text.USBFS_EP_0_ISR,"ax",%progbits - 735 .align 1 - 736 .global USBFS_EP_0_ISR - 737 .thumb - 738 .thumb_func - 739 .type USBFS_EP_0_ISR, %function - 740 USBFS_EP_0_ISR: - 741 .LFB0: - 67:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 742 .loc 1 67 0 - 743 .cfi_startproc - 744 @ args = 0, pretend = 0, frame = 0 - 745 @ frame_needed = 0, uses_anonymous_args = 0 - 746 0000 08B5 push {r3, lr} - 747 .LCFI6: - 748 .cfi_def_cfa_offset 8 - 749 .cfi_offset 3, -8 - 750 .cfi_offset 14, -4 - 72:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); - 751 .loc 1 72 0 - 752 0002 224B ldr r3, .L95 - 753 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 754 0006 D0B2 uxtb r0, r2 - 755 .LVL33: - 73:.\Generated_Source\PSoC5/USBFS_drv.c **** if ((bRegTemp & USBFS_MODE_ACKD) != 0u) - 756 .loc 1 73 0 - 757 0008 00F01001 and r1, r0, #16 - 758 000c CBB2 uxtb r3, r1 - 759 000e 002B cmp r3, #0 - 760 0010 3BD0 beq .L79 - 761 .LVL34: - 76:.\Generated_Source\PSoC5/USBFS_drv.c **** if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u) - 762 .loc 1 76 0 - 763 0012 52B2 sxtb r2, r2 - 764 0014 002A cmp r2, #0 - 765 0016 0ADA bge .L82 - 78:.\Generated_Source\PSoC5/USBFS_drv.c **** if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) - 766 .loc 1 78 0 - 767 0018 00F00F01 and r1, r0, #15 - 768 001c 0129 cmp r1, #1 - 769 001e 34D1 bne .L79 - 84:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_HandleSetup(); - 770 .loc 1 84 0 - 771 0020 FFF7FEFF bl USBFS_HandleSetup - 772 .LVL35: - 85:.\Generated_Source\PSoC5/USBFS_drv.c **** if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) - 773 .loc 1 85 0 - 774 0024 1A4B ldr r3, .L95+4 - 775 0026 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 776 0028 0006 lsls r0, r0, #24 - 777 002a 0DD5 bpl .L84 - 778 002c 08BD pop {r3, pc} - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 29 - - - 779 .LVL36: - 780 .L82: - 92:.\Generated_Source\PSoC5/USBFS_drv.c **** else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u) - 781 .loc 1 92 0 - 782 002e 00F04001 and r1, r0, #64 - 783 0032 CBB2 uxtb r3, r1 - 784 0034 13B1 cbz r3, .L85 - 94:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_HandleIN(); - 785 .loc 1 94 0 - 786 0036 FFF7FEFF bl USBFS_HandleIN - 787 .LVL37: - 788 003a 05E0 b .L84 - 789 .LVL38: - 790 .L85: - 96:.\Generated_Source\PSoC5/USBFS_drv.c **** else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u) - 791 .loc 1 96 0 - 792 003c 00F02000 and r0, r0, #32 - 793 0040 C2B2 uxtb r2, r0 - 794 .LVL39: - 795 0042 12B3 cbz r2, .L79 - 98:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_HandleOUT(); - 796 .loc 1 98 0 - 797 0044 FFF7FEFF bl USBFS_HandleOUT - 798 .LVL40: - 799 .L84: - 106:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - 800 .loc 1 106 0 - 801 0048 104A ldr r2, .L95 - 802 004a 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 803 .LVL41: - 107:.\Generated_Source\PSoC5/USBFS_drv.c **** if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwi - 804 .loc 1 107 0 - 805 004c 0906 lsls r1, r1, #24 - 806 .LVL42: - 807 004e 1CD4 bmi .L79 - 808 .L89: - 110:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count; - 809 .loc 1 110 0 - 810 0050 104B ldr r3, .L95+8 - 811 0052 114A ldr r2, .L95+12 - 812 0054 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 813 0056 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 814 0058 41EA0003 orr r3, r1, r0 - 815 .LVL43: - 111:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp); - 816 .loc 1 111 0 - 817 005c 0F48 ldr r0, .L95+16 - 818 005e 0370 strb r3, [r0, #0] - 112:.\Generated_Source\PSoC5/USBFS_drv.c **** if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was success - 819 .loc 1 112 0 - 820 0060 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 821 0062 9342 cmp r3, r2 - 822 0064 11D1 bne .L79 - 823 .LVL44: - 824 .L92: - 116:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = USBFS_ep0Mode; /* Init temporary variable */ - 825 .loc 1 116 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 30 - - - 826 0066 0A49 ldr r1, .L95+4 - 118:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; - 827 .loc 1 118 0 - 828 0068 084B ldr r3, .L95 - 116:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = USBFS_ep0Mode; /* Init temporary variable */ - 829 .loc 1 116 0 - 830 006a 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 831 .LVL45: - 118:.\Generated_Source\PSoC5/USBFS_drv.c **** bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; - 832 .loc 1 118 0 - 833 006c 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 834 .LVL46: - 119:.\Generated_Source\PSoC5/USBFS_drv.c **** if(bRegTemp == 0u) /* Check if SETUP bit is not se - 835 .loc 1 119 0 - 836 006e 00F08000 and r0, r0, #128 - 837 .LVL47: - 838 0072 C0B2 uxtb r0, r0 - 839 0074 20B9 cbnz r0, .L87 - 122:.\Generated_Source\PSoC5/USBFS_drv.c **** CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode); - 840 .loc 1 122 0 - 841 0076 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 842 .LVL48: - 843 0078 1A70 strb r2, [r3, #0] - 124:.\Generated_Source\PSoC5/USBFS_drv.c **** modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK; - 844 .loc 1 124 0 - 845 007a 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 846 007c 01F00F02 and r2, r1, #15 - 847 .LVL49: - 848 .L87: - 126:.\Generated_Source\PSoC5/USBFS_drv.c **** }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */ - 849 .loc 1 126 0 - 850 0080 034B ldr r3, .L95+4 - 851 0082 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 852 0084 8242 cmp r2, r0 - 853 0086 EED1 bne .L92 - 854 0088 08BD pop {r3, pc} - 855 .LVL50: - 856 .L79: - 857 008a 08BD pop {r3, pc} - 858 .L96: - 859 .align 2 - 860 .L95: - 861 008c 28600040 .word 1073766440 - 862 0090 00000000 .word USBFS_ep0Mode - 863 0094 00000000 .word USBFS_ep0Toggle - 864 0098 00000000 .word USBFS_ep0Count - 865 009c 29600040 .word 1073766441 - 866 .cfi_endproc - 867 .LFE0: - 868 .size USBFS_EP_0_ISR, .-USBFS_EP_0_ISR - 869 .section .text.USBFS_InitializeStatusBlock,"ax",%progbits - 870 .align 1 - 871 .global USBFS_InitializeStatusBlock - 872 .thumb - 873 .thumb_func - 874 .type USBFS_InitializeStatusBlock, %function - 875 USBFS_InitializeStatusBlock: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 31 - - - 876 .LFB15: - 740:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 741:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 742:.\Generated_Source\PSoC5/USBFS_drv.c **** - 743:.\Generated_Source\PSoC5/USBFS_drv.c **** - 744:.\Generated_Source\PSoC5/USBFS_drv.c **** /******************************************************************************* - 745:.\Generated_Source\PSoC5/USBFS_drv.c **** * Function Name: USBFS_InitializeStatusBlock - 746:.\Generated_Source\PSoC5/USBFS_drv.c **** ******************************************************************************** - 747:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 748:.\Generated_Source\PSoC5/USBFS_drv.c **** * Summary: - 749:.\Generated_Source\PSoC5/USBFS_drv.c **** * Initialize the Completion Status Block for a Request. The completion - 750:.\Generated_Source\PSoC5/USBFS_drv.c **** * code is set to USB_XFER_IDLE. - 751:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 752:.\Generated_Source\PSoC5/USBFS_drv.c **** * Also, initializes USBFS_transferByteCount. Save some space, - 753:.\Generated_Source\PSoC5/USBFS_drv.c **** * this is the only consumer. - 754:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 755:.\Generated_Source\PSoC5/USBFS_drv.c **** * Parameters: - 756:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 757:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 758:.\Generated_Source\PSoC5/USBFS_drv.c **** * Return: - 759:.\Generated_Source\PSoC5/USBFS_drv.c **** * None. - 760:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 761:.\Generated_Source\PSoC5/USBFS_drv.c **** * Global variables: - 762:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. - 763:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_currentTD.pStatusBlock->length - cleared. - 764:.\Generated_Source\PSoC5/USBFS_drv.c **** * USBFS_transferByteCount - cleared. - 765:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 766:.\Generated_Source\PSoC5/USBFS_drv.c **** * Reentrant: - 767:.\Generated_Source\PSoC5/USBFS_drv.c **** * No. - 768:.\Generated_Source\PSoC5/USBFS_drv.c **** * - 769:.\Generated_Source\PSoC5/USBFS_drv.c **** *******************************************************************************/ - 770:.\Generated_Source\PSoC5/USBFS_drv.c **** void USBFS_InitializeStatusBlock(void) - 771:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 877 .loc 1 771 0 - 878 .cfi_startproc - 879 @ args = 0, pretend = 0, frame = 0 - 880 @ frame_needed = 0, uses_anonymous_args = 0 - 881 @ link register save eliminated. - 772:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferByteCount = 0u; - 882 .loc 1 772 0 - 883 0000 054A ldr r2, .L102 - 884 0002 0023 movs r3, #0 - 885 0004 1380 strh r3, [r2, #0] @ movhi - 773:.\Generated_Source\PSoC5/USBFS_drv.c **** if(USBFS_currentTD.pStatusBlock != NULL) - 886 .loc 1 773 0 - 887 0006 054A ldr r2, .L102+4 - 888 0008 9168 ldr r1, [r2, #8] - 889 000a 19B1 cbz r1, .L97 - 774:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 775:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; - 890 .loc 1 775 0 - 891 000c 9168 ldr r1, [r2, #8] - 892 000e 0B70 strb r3, [r1, #0] - 776:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.pStatusBlock->length = 0u; - 893 .loc 1 776 0 - 894 0010 9068 ldr r0, [r2, #8] - 895 0012 4380 strh r3, [r0, #2] @ movhi - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 32 - - - 896 .L97: - 897 0014 7047 bx lr - 898 .L103: - 899 0016 00BF .align 2 - 900 .L102: - 901 0018 00000000 .word USBFS_transferByteCount - 902 001c 00000000 .word USBFS_currentTD - 903 .cfi_endproc - 904 .LFE15: - 905 .size USBFS_InitializeStatusBlock, .-USBFS_InitializeStatusBlock - 906 .section .text.USBFS_InitControlWrite,"ax",%progbits - 907 .align 1 - 908 .global USBFS_InitControlWrite - 909 .thumb - 910 .thumb_func - 911 .type USBFS_InitControlWrite, %function - 912 USBFS_InitControlWrite: - 913 .LFB9: - 520:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 914 .loc 1 520 0 - 915 .cfi_startproc - 916 @ args = 0, pretend = 0, frame = 0 - 917 @ frame_needed = 0, uses_anonymous_args = 0 - 918 0000 08B5 push {r3, lr} - 919 .LCFI7: - 920 .cfi_def_cfa_offset 8 - 921 .cfi_offset 3, -8 - 922 .cfi_offset 14, -4 - 526:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 923 .loc 1 526 0 - 924 0002 0C49 ldr r1, .L106 - 524:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; - 925 .loc 1 524 0 - 926 0004 0C4B ldr r3, .L106+4 - 927 0006 0422 movs r2, #4 - 526:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 928 .loc 1 526 0 - 929 0008 8020 movs r0, #128 - 524:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; - 930 .loc 1 524 0 - 931 000a 1A70 strb r2, [r3, #0] - 526:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - 932 .loc 1 526 0 - 933 000c 0870 strb r0, [r1, #0] - 528:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_InitializeStatusBlock(); - 934 .loc 1 528 0 - 935 000e FFF7FEFF bl USBFS_InitializeStatusBlock - 936 .LVL51: - 530:.\Generated_Source\PSoC5/USBFS_drv.c **** xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - 937 .loc 1 530 0 - 938 0012 0A4B ldr r3, .L106+8 - 939 0014 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 940 0016 581E subs r0, r3, #1 - 532:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_currentTD.count > xferCount) - 941 .loc 1 532 0 - 942 0018 094B ldr r3, .L106+12 - 530:.\Generated_Source\PSoC5/USBFS_drv.c **** xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 33 - - - 943 .loc 1 530 0 - 944 001a 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 532:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_currentTD.count > xferCount) - 945 .loc 1 532 0 - 946 001c 1888 ldrh r0, [r3, #0] - 530:.\Generated_Source\PSoC5/USBFS_drv.c **** xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - 947 .loc 1 530 0 - 948 001e 41EA0222 orr r2, r1, r2, lsl #8 - 949 .LVL52: - 532:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_currentTD.count > xferCount) - 950 .loc 1 532 0 - 951 0022 81B2 uxth r1, r0 - 952 0024 9142 cmp r1, r2 - 534:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.count = xferCount; - 953 .loc 1 534 0 - 954 0026 88BF it hi - 955 0028 1A80 strhhi r2, [r3, #0] @ movhi - 538:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; - 956 .loc 1 538 0 - 957 002a 064B ldr r3, .L106+16 - 958 002c 0B22 movs r2, #11 - 959 .LVL53: - 960 002e 1A70 strb r2, [r3, #0] - 541:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 961 .loc 1 541 0 - 962 0030 0120 movs r0, #1 - 963 0032 08BD pop {r3, pc} - 964 .L107: - 965 .align 2 - 966 .L106: - 967 0034 00000000 .word USBFS_ep0Toggle - 968 0038 00000000 .word USBFS_transferState - 969 003c 07600040 .word 1073766407 - 970 0040 00000000 .word USBFS_currentTD - 971 0044 00000000 .word USBFS_ep0Mode - 972 .cfi_endproc - 973 .LFE9: - 974 .size USBFS_InitControlWrite, .-USBFS_InitControlWrite - 975 .section .text.USBFS_InitControlRead,"ax",%progbits - 976 .align 1 - 977 .global USBFS_InitControlRead - 978 .thumb - 979 .thumb_func - 980 .type USBFS_InitControlRead, %function - 981 USBFS_InitControlRead: - 982 .LFB5: - 370:.\Generated_Source\PSoC5/USBFS_drv.c **** { - 983 .loc 1 370 0 - 984 .cfi_startproc - 985 @ args = 0, pretend = 0, frame = 0 - 986 @ frame_needed = 0, uses_anonymous_args = 0 - 987 0000 10B5 push {r4, lr} - 988 .LCFI8: - 989 .cfi_def_cfa_offset 8 - 990 .cfi_offset 4, -8 - 991 .cfi_offset 14, -4 - 372:.\Generated_Source\PSoC5/USBFS_drv.c **** if(USBFS_currentTD.count == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 34 - - - 992 .loc 1 372 0 - 993 0002 0F4C ldr r4, .L112 - 994 0004 2388 ldrh r3, [r4, #0] - 995 0006 98B2 uxth r0, r3 - 996 0008 10B9 cbnz r0, .L109 - 374:.\Generated_Source\PSoC5/USBFS_drv.c **** (void) USBFS_InitZeroLengthControlTransfer(); - 997 .loc 1 374 0 - 998 000a FFF7FEFF bl USBFS_InitZeroLengthControlTransfer - 999 .LVL54: - 1000 000e 14E0 b .L110 - 1001 .L109: - 379:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - 1002 .loc 1 379 0 - 1003 0010 0C49 ldr r1, .L112+4 - 381:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = 0u; - 1004 .loc 1 381 0 - 1005 0012 0D4B ldr r3, .L112+8 - 379:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - 1006 .loc 1 379 0 - 1007 0014 0222 movs r2, #2 - 381:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = 0u; - 1008 .loc 1 381 0 - 1009 0016 0020 movs r0, #0 - 379:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - 1010 .loc 1 379 0 - 1011 0018 0A70 strb r2, [r1, #0] - 381:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_ep0Toggle = 0u; - 1012 .loc 1 381 0 - 1013 001a 1870 strb r0, [r3, #0] - 383:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_InitializeStatusBlock(); - 1014 .loc 1 383 0 - 1015 001c FFF7FEFF bl USBFS_InitializeStatusBlock - 1016 .LVL55: - 384:.\Generated_Source\PSoC5/USBFS_drv.c **** xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - 1017 .loc 1 384 0 - 1018 0020 0A49 ldr r1, .L112+12 - 1019 0022 481E subs r0, r1, #1 - 1020 0024 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 1021 0026 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 1022 0028 43EA0221 orr r1, r3, r2, lsl #8 - 1023 .LVL56: - 386:.\Generated_Source\PSoC5/USBFS_drv.c **** if (USBFS_currentTD.count > xferCount) - 1024 .loc 1 386 0 - 1025 002c 2288 ldrh r2, [r4, #0] - 1026 002e 90B2 uxth r0, r2 - 1027 0030 8842 cmp r0, r1 - 388:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_currentTD.count = xferCount; - 1028 .loc 1 388 0 - 1029 0032 88BF it hi - 1030 0034 2180 strhhi r1, [r4, #0] @ movhi - 390:.\Generated_Source\PSoC5/USBFS_drv.c **** USBFS_LoadEP0(); - 1031 .loc 1 390 0 - 1032 0036 FFF7FEFF bl USBFS_LoadEP0 - 1033 .LVL57: - 1034 .L110: - 394:.\Generated_Source\PSoC5/USBFS_drv.c **** } - 1035 .loc 1 394 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 35 - - - 1036 003a 0120 movs r0, #1 - 1037 003c 10BD pop {r4, pc} - 1038 .L113: - 1039 003e 00BF .align 2 - 1040 .L112: - 1041 0040 00000000 .word USBFS_currentTD - 1042 0044 00000000 .word USBFS_transferState - 1043 0048 00000000 .word USBFS_ep0Toggle - 1044 004c 07600040 .word 1073766407 - 1045 .cfi_endproc - 1046 .LFE5: - 1047 .size USBFS_InitControlRead, .-USBFS_InitControlRead - 1048 .comm USBFS_transferByteCount,2,2 - 1049 .comm USBFS_ep0Count,1,1 - 1050 .comm USBFS_ep0Mode,1,1 - 1051 .comm USBFS_currentTD,12,4 - 1052 .comm USBFS_transferState,1,1 - 1053 .comm USBFS_lastPacketSize,1,1 - 1054 .comm USBFS_ep0Toggle,1,1 - 1055 .comm USBFS_interfaceClass,4,4 - 1056 .comm USBFS_device,1,1 - 1057 .comm USBFS_interfaceStatus,1,1 - 1058 .comm USBFS_interfaceSetting_last,1,1 - 1059 .comm USBFS_interfaceSetting,1,1 - 1060 .comm USBFS_deviceStatus,1,1 - 1061 .comm USBFS_deviceAddress,1,1 - 1062 .comm USBFS_configurationChanged,1,1 - 1063 .comm USBFS_interfaceNumber,1,1 - 1064 .comm USBFS_configuration,1,1 - 1065 .comm USBFS_EP,108,2 - 1066 .text - 1067 .Letext0: - 1068 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 1069 .file 3 ".\\Generated_Source\\PSoC5\\USBFS.h" - 1070 .file 4 ".\\Generated_Source\\PSoC5\\USBFS_pvt.h" - 1071 .section .debug_info,"",%progbits - 1072 .Ldebug_info0: - 1073 0000 B3060000 .4byte 0x6b3 - 1074 0004 0200 .2byte 0x2 - 1075 0006 00000000 .4byte .Ldebug_abbrev0 - 1076 000a 04 .byte 0x4 - 1077 000b 01 .uleb128 0x1 - 1078 000c 09030000 .4byte .LASF74 - 1079 0010 01 .byte 0x1 - 1080 0011 FA000000 .4byte .LASF75 - 1081 0015 31020000 .4byte .LASF76 - 1082 0019 00000000 .4byte .Ldebug_ranges0+0 - 1083 001d 00000000 .4byte 0 - 1084 0021 00000000 .4byte 0 - 1085 0025 00000000 .4byte .Ldebug_line0 - 1086 0029 02 .uleb128 0x2 - 1087 002a 01 .byte 0x1 - 1088 002b 06 .byte 0x6 - 1089 002c AC000000 .4byte .LASF0 - 1090 0030 02 .uleb128 0x2 - 1091 0031 01 .byte 0x1 - 1092 0032 08 .byte 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 36 - - - 1093 0033 6B030000 .4byte .LASF1 - 1094 0037 02 .uleb128 0x2 - 1095 0038 02 .byte 0x2 - 1096 0039 05 .byte 0x5 - 1097 003a 95030000 .4byte .LASF2 - 1098 003e 02 .uleb128 0x2 - 1099 003f 02 .byte 0x2 - 1100 0040 07 .byte 0x7 - 1101 0041 C9010000 .4byte .LASF3 - 1102 0045 02 .uleb128 0x2 - 1103 0046 04 .byte 0x4 - 1104 0047 05 .byte 0x5 - 1105 0048 E2000000 .4byte .LASF4 - 1106 004c 02 .uleb128 0x2 - 1107 004d 04 .byte 0x4 - 1108 004e 07 .byte 0x7 - 1109 004f A9010000 .4byte .LASF5 - 1110 0053 02 .uleb128 0x2 - 1111 0054 08 .byte 0x8 - 1112 0055 05 .byte 0x5 - 1113 0056 9E000000 .4byte .LASF6 - 1114 005a 02 .uleb128 0x2 - 1115 005b 08 .byte 0x8 - 1116 005c 07 .byte 0x7 - 1117 005d 67000000 .4byte .LASF7 - 1118 0061 03 .uleb128 0x3 - 1119 0062 04 .byte 0x4 - 1120 0063 05 .byte 0x5 - 1121 0064 696E7400 .ascii "int\000" - 1122 0068 02 .uleb128 0x2 - 1123 0069 04 .byte 0x4 - 1124 006a 07 .byte 0x7 - 1125 006b 84010000 .4byte .LASF8 - 1126 006f 04 .uleb128 0x4 - 1127 0070 EB000000 .4byte .LASF9 - 1128 0074 02 .byte 0x2 - 1129 0075 5B .byte 0x5b - 1130 0076 30000000 .4byte 0x30 - 1131 007a 04 .uleb128 0x4 - 1132 007b 13000000 .4byte .LASF10 - 1133 007f 02 .byte 0x2 - 1134 0080 5C .byte 0x5c - 1135 0081 3E000000 .4byte 0x3e - 1136 0085 02 .uleb128 0x2 - 1137 0086 04 .byte 0x4 - 1138 0087 04 .byte 0x4 - 1139 0088 EF020000 .4byte .LASF11 - 1140 008c 02 .uleb128 0x2 - 1141 008d 08 .byte 0x8 - 1142 008e 04 .byte 0x4 - 1143 008f 1F010000 .4byte .LASF12 - 1144 0093 02 .uleb128 0x2 - 1145 0094 01 .byte 0x1 - 1146 0095 08 .byte 0x8 - 1147 0096 6A040000 .4byte .LASF13 - 1148 009a 04 .uleb128 0x4 - 1149 009b 52030000 .4byte .LASF14 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 37 - - - 1150 009f 02 .byte 0x2 - 1151 00a0 F0 .byte 0xf0 - 1152 00a1 A5000000 .4byte 0xa5 - 1153 00a5 05 .uleb128 0x5 - 1154 00a6 6F000000 .4byte 0x6f - 1155 00aa 05 .uleb128 0x5 - 1156 00ab 7A000000 .4byte 0x7a - 1157 00af 02 .uleb128 0x2 - 1158 00b0 04 .byte 0x4 - 1159 00b1 07 .byte 0x7 - 1160 00b2 81020000 .4byte .LASF15 - 1161 00b6 06 .uleb128 0x6 - 1162 00b7 0C .byte 0xc - 1163 00b8 03 .byte 0x3 - 1164 00b9 79 .byte 0x79 - 1165 00ba 3D010000 .4byte 0x13d - 1166 00be 07 .uleb128 0x7 - 1167 00bf A8020000 .4byte .LASF16 - 1168 00c3 03 .byte 0x3 - 1169 00c4 7B .byte 0x7b - 1170 00c5 6F000000 .4byte 0x6f - 1171 00c9 02 .byte 0x2 - 1172 00ca 23 .byte 0x23 - 1173 00cb 00 .uleb128 0 - 1174 00cc 07 .uleb128 0x7 - 1175 00cd F5020000 .4byte .LASF17 - 1176 00d1 03 .byte 0x3 - 1177 00d2 7C .byte 0x7c - 1178 00d3 6F000000 .4byte 0x6f - 1179 00d7 02 .byte 0x2 - 1180 00d8 23 .byte 0x23 - 1181 00d9 01 .uleb128 0x1 - 1182 00da 07 .uleb128 0x7 - 1183 00db 77020000 .4byte .LASF18 - 1184 00df 03 .byte 0x3 - 1185 00e0 7D .byte 0x7d - 1186 00e1 6F000000 .4byte 0x6f - 1187 00e5 02 .byte 0x2 - 1188 00e6 23 .byte 0x23 - 1189 00e7 02 .uleb128 0x2 - 1190 00e8 07 .uleb128 0x7 - 1191 00e9 F1000000 .4byte .LASF19 - 1192 00ed 03 .byte 0x3 - 1193 00ee 7E .byte 0x7e - 1194 00ef 6F000000 .4byte 0x6f - 1195 00f3 02 .byte 0x2 - 1196 00f4 23 .byte 0x23 - 1197 00f5 03 .uleb128 0x3 - 1198 00f6 07 .uleb128 0x7 - 1199 00f7 7E000000 .4byte .LASF20 - 1200 00fb 03 .byte 0x3 - 1201 00fc 7F .byte 0x7f - 1202 00fd 6F000000 .4byte 0x6f - 1203 0101 02 .byte 0x2 - 1204 0102 23 .byte 0x23 - 1205 0103 04 .uleb128 0x4 - 1206 0104 07 .uleb128 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 38 - - - 1207 0105 49010000 .4byte .LASF21 - 1208 0109 03 .byte 0x3 - 1209 010a 80 .byte 0x80 - 1210 010b 6F000000 .4byte 0x6f - 1211 010f 02 .byte 0x2 - 1212 0110 23 .byte 0x23 - 1213 0111 05 .uleb128 0x5 - 1214 0112 07 .uleb128 0x7 - 1215 0113 89040000 .4byte .LASF22 - 1216 0117 03 .byte 0x3 - 1217 0118 81 .byte 0x81 - 1218 0119 7A000000 .4byte 0x7a - 1219 011d 02 .byte 0x2 - 1220 011e 23 .byte 0x23 - 1221 011f 06 .uleb128 0x6 - 1222 0120 07 .uleb128 0x7 - 1223 0121 6F040000 .4byte .LASF23 - 1224 0125 03 .byte 0x3 - 1225 0126 82 .byte 0x82 - 1226 0127 7A000000 .4byte 0x7a - 1227 012b 02 .byte 0x2 - 1228 012c 23 .byte 0x23 - 1229 012d 08 .uleb128 0x8 - 1230 012e 07 .uleb128 0x7 - 1231 012f 0C020000 .4byte .LASF24 - 1232 0133 03 .byte 0x3 - 1233 0134 83 .byte 0x83 - 1234 0135 6F000000 .4byte 0x6f - 1235 0139 02 .byte 0x2 - 1236 013a 23 .byte 0x23 - 1237 013b 0A .uleb128 0xa - 1238 013c 00 .byte 0 - 1239 013d 04 .uleb128 0x4 - 1240 013e D6030000 .4byte .LASF25 - 1241 0142 03 .byte 0x3 - 1242 0143 84 .byte 0x84 - 1243 0144 B6000000 .4byte 0xb6 - 1244 0148 06 .uleb128 0x6 - 1245 0149 04 .byte 0x4 - 1246 014a 03 .byte 0x3 - 1247 014b 90 .byte 0x90 - 1248 014c 6D010000 .4byte 0x16d - 1249 0150 07 .uleb128 0x7 - 1250 0151 DF040000 .4byte .LASF26 - 1251 0155 03 .byte 0x3 - 1252 0156 92 .byte 0x92 - 1253 0157 6F000000 .4byte 0x6f - 1254 015b 02 .byte 0x2 - 1255 015c 23 .byte 0x23 - 1256 015d 00 .uleb128 0 - 1257 015e 07 .uleb128 0x7 - 1258 015f 63040000 .4byte .LASF27 - 1259 0163 03 .byte 0x3 - 1260 0164 93 .byte 0x93 - 1261 0165 7A000000 .4byte 0x7a - 1262 0169 02 .byte 0x2 - 1263 016a 23 .byte 0x23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 39 - - - 1264 016b 02 .uleb128 0x2 - 1265 016c 00 .byte 0 - 1266 016d 04 .uleb128 0x4 - 1267 016e BE020000 .4byte .LASF28 - 1268 0172 03 .byte 0x3 - 1269 0173 94 .byte 0x94 - 1270 0174 48010000 .4byte 0x148 - 1271 0178 06 .uleb128 0x6 - 1272 0179 0C .byte 0xc - 1273 017a 03 .byte 0x3 - 1274 017b 96 .byte 0x96 - 1275 017c AB010000 .4byte 0x1ab - 1276 0180 07 .uleb128 0x7 - 1277 0181 0D000000 .4byte .LASF29 - 1278 0185 03 .byte 0x3 - 1279 0186 98 .byte 0x98 - 1280 0187 7A000000 .4byte 0x7a - 1281 018b 02 .byte 0x2 - 1282 018c 23 .byte 0x23 - 1283 018d 00 .uleb128 0 - 1284 018e 07 .uleb128 0x7 - 1285 018f 2F010000 .4byte .LASF30 - 1286 0193 03 .byte 0x3 - 1287 0194 99 .byte 0x99 - 1288 0195 AB010000 .4byte 0x1ab - 1289 0199 02 .byte 0x2 - 1290 019a 23 .byte 0x23 - 1291 019b 04 .uleb128 0x4 - 1292 019c 07 .uleb128 0x7 - 1293 019d 00000000 .4byte .LASF31 - 1294 01a1 03 .byte 0x3 - 1295 01a2 9A .byte 0x9a - 1296 01a3 B1010000 .4byte 0x1b1 - 1297 01a7 02 .byte 0x2 - 1298 01a8 23 .byte 0x23 - 1299 01a9 08 .uleb128 0x8 - 1300 01aa 00 .byte 0 - 1301 01ab 08 .uleb128 0x8 - 1302 01ac 04 .byte 0x4 - 1303 01ad A5000000 .4byte 0xa5 - 1304 01b1 08 .uleb128 0x8 - 1305 01b2 04 .byte 0x4 - 1306 01b3 6D010000 .4byte 0x16d - 1307 01b7 04 .uleb128 0x4 - 1308 01b8 9F030000 .4byte .LASF32 - 1309 01bc 03 .byte 0x3 - 1310 01bd 9B .byte 0x9b - 1311 01be 78010000 .4byte 0x178 - 1312 01c2 09 .uleb128 0x9 - 1313 01c3 01 .byte 0x1 - 1314 01c4 83000000 .4byte .LASF77 - 1315 01c8 01 .byte 0x1 - 1316 01c9 C701 .2byte 0x1c7 - 1317 01cb 01 .byte 0x1 - 1318 01cc 01 .byte 0x1 - 1319 01cd 0A .uleb128 0xa - 1320 01ce 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 40 - - - 1321 01cf BB010000 .4byte .LASF33 - 1322 01d3 01 .byte 0x1 - 1323 01d4 3301 .2byte 0x133 - 1324 01d6 01 .byte 0x1 - 1325 01d7 00000000 .4byte .LFB4 - 1326 01db 94000000 .4byte .LFE4 - 1327 01df 02 .byte 0x2 - 1328 01e0 7D .byte 0x7d - 1329 01e1 00 .sleb128 0 - 1330 01e2 01 .byte 0x1 - 1331 01e3 F8010000 .4byte 0x1f8 - 1332 01e7 0B .uleb128 0xb - 1333 01e8 EB010000 .4byte .LASF35 - 1334 01ec 01 .byte 0x1 - 1335 01ed 3501 .2byte 0x135 - 1336 01ef 6F000000 .4byte 0x6f - 1337 01f3 00000000 .4byte .LLST0 - 1338 01f7 00 .byte 0 - 1339 01f8 0C .uleb128 0xc - 1340 01f9 01 .byte 0x1 - 1341 01fa 37050000 .4byte .LASF37 - 1342 01fe 01 .byte 0x1 - 1343 01ff A501 .2byte 0x1a5 - 1344 0201 01 .byte 0x1 - 1345 0202 6F000000 .4byte 0x6f - 1346 0206 00000000 .4byte .LFB6 - 1347 020a 34000000 .4byte .LFE6 - 1348 020e 02 .byte 0x2 - 1349 020f 7D .byte 0x7d - 1350 0210 00 .sleb128 0 - 1351 0211 01 .byte 0x1 - 1352 0212 0D .uleb128 0xd - 1353 0213 C2010000 .4byte 0x1c2 - 1354 0217 00000000 .4byte .LFB7 - 1355 021b 04000000 .4byte .LFE7 - 1356 021f 02 .byte 0x2 - 1357 0220 7D .byte 0x7d - 1358 0221 00 .sleb128 0 - 1359 0222 01 .byte 0x1 - 1360 0223 32020000 .4byte 0x232 - 1361 0227 0E .uleb128 0xe - 1362 0228 04000000 .4byte .LVL2 - 1363 022c 01 .byte 0x1 - 1364 022d CD010000 .4byte 0x1cd - 1365 0231 00 .byte 0 - 1366 0232 0F .uleb128 0xf - 1367 0233 01 .byte 0x1 - 1368 0234 47040000 .4byte .LASF34 - 1369 0238 01 .byte 0x1 - 1370 0239 3E02 .2byte 0x23e - 1371 023b 01 .byte 0x1 - 1372 023c 00000000 .4byte .LFB10 - 1373 0240 74000000 .4byte .LFE10 - 1374 0244 14000000 .4byte .LLST1 - 1375 0248 01 .byte 0x1 - 1376 0249 6E020000 .4byte 0x26e - 1377 024d 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 41 - - - 1378 024e EB010000 .4byte .LASF35 - 1379 0252 01 .byte 0x1 - 1380 0253 4002 .2byte 0x240 - 1381 0255 6F000000 .4byte 0x6f - 1382 0259 34000000 .4byte .LLST2 - 1383 025d 0B .uleb128 0xb - 1384 025e 39000000 .4byte .LASF36 - 1385 0262 01 .byte 0x1 - 1386 0263 4102 .2byte 0x241 - 1387 0265 6F000000 .4byte 0x6f - 1388 0269 6A000000 .4byte .LLST3 - 1389 026d 00 .byte 0 - 1390 026e 0C .uleb128 0xc - 1391 026f 01 .byte 0x1 - 1392 0270 0A040000 .4byte .LASF38 - 1393 0274 01 .byte 0x1 - 1394 0275 8F02 .2byte 0x28f - 1395 0277 01 .byte 0x1 - 1396 0278 6F000000 .4byte 0x6f - 1397 027c 00000000 .4byte .LFB12 - 1398 0280 2C000000 .4byte .LFE12 - 1399 0284 02 .byte 0x2 - 1400 0285 7D .byte 0x7d - 1401 0286 00 .sleb128 0 - 1402 0287 01 .byte 0x1 - 1403 0288 0A .uleb128 0xa - 1404 0289 01 .byte 0x1 - 1405 028a 91010000 .4byte .LASF39 - 1406 028e 01 .byte 0x1 - 1407 028f DD02 .2byte 0x2dd - 1408 0291 01 .byte 0x1 - 1409 0292 00000000 .4byte .LFB14 - 1410 0296 20000000 .4byte .LFE14 - 1411 029a 02 .byte 0x2 - 1412 029b 7D .byte 0x7d - 1413 029c 00 .sleb128 0 - 1414 029d 01 .byte 0x1 - 1415 029e B3020000 .4byte 0x2b3 - 1416 02a2 10 .uleb128 0x10 - 1417 02a3 42000000 .4byte .LASF78 - 1418 02a7 01 .byte 0x1 - 1419 02a8 DD02 .2byte 0x2dd - 1420 02aa 6F000000 .4byte 0x6f - 1421 02ae 7E000000 .4byte .LLST4 - 1422 02b2 00 .byte 0 - 1423 02b3 0F .uleb128 0xf - 1424 02b4 01 .byte 0x1 - 1425 02b5 EB030000 .4byte .LASF40 - 1426 02b9 01 .byte 0x1 - 1427 02ba B302 .2byte 0x2b3 - 1428 02bc 01 .byte 0x1 - 1429 02bd 00000000 .4byte .LFB13 - 1430 02c1 3C000000 .4byte .LFE13 - 1431 02c5 AB000000 .4byte .LLST5 - 1432 02c9 01 .byte 0x1 - 1433 02ca DE020000 .4byte 0x2de - 1434 02ce 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 42 - - - 1435 02cf 22000000 .4byte .LVL14 - 1436 02d3 88020000 .4byte 0x288 - 1437 02d7 12 .uleb128 0x12 - 1438 02d8 01 .byte 0x1 - 1439 02d9 50 .byte 0x50 - 1440 02da 01 .byte 0x1 - 1441 02db 31 .byte 0x31 - 1442 02dc 00 .byte 0 - 1443 02dd 00 .byte 0 - 1444 02de 0F .uleb128 0xf - 1445 02df 01 .byte 0x1 - 1446 02e0 5B050000 .4byte .LASF41 - 1447 02e4 01 .byte 0x1 - 1448 02e5 6D02 .2byte 0x26d - 1449 02e7 01 .byte 0x1 - 1450 02e8 00000000 .4byte .LFB11 - 1451 02ec 20000000 .4byte .LFE11 - 1452 02f0 CB000000 .4byte .LLST6 - 1453 02f4 01 .byte 0x1 - 1454 02f5 09030000 .4byte 0x309 - 1455 02f9 11 .uleb128 0x11 - 1456 02fa 0E000000 .4byte .LVL15 - 1457 02fe 88020000 .4byte 0x288 - 1458 0302 12 .uleb128 0x12 - 1459 0303 01 .byte 0x1 - 1460 0304 50 .byte 0x50 - 1461 0305 01 .byte 0x1 - 1462 0306 31 .byte 0x31 - 1463 0307 00 .byte 0 - 1464 0308 00 .byte 0 - 1465 0309 13 .uleb128 0x13 - 1466 030a 01 .byte 0x1 - 1467 030b DC010000 .4byte .LASF42 - 1468 030f 01 .byte 0x1 - 1469 0310 CF .byte 0xcf - 1470 0311 01 .byte 0x1 - 1471 0312 00000000 .4byte .LFB2 - 1472 0316 24000000 .4byte .LFE2 - 1473 031a 02 .byte 0x2 - 1474 031b 7D .byte 0x7d - 1475 031c 00 .sleb128 0 - 1476 031d 01 .byte 0x1 - 1477 031e 55030000 .4byte 0x355 - 1478 0322 14 .uleb128 0x14 - 1479 0323 C2010000 .4byte 0x1c2 - 1480 0327 10000000 .4byte .LBB4 - 1481 032b 14000000 .4byte .LBE4 - 1482 032f 01 .byte 0x1 - 1483 0330 D6 .byte 0xd6 - 1484 0331 40030000 .4byte 0x340 - 1485 0335 0E .uleb128 0xe - 1486 0336 14000000 .4byte .LVL16 - 1487 033a 01 .byte 0x1 - 1488 033b CD010000 .4byte 0x1cd - 1489 033f 00 .byte 0 - 1490 0340 0E .uleb128 0xe - 1491 0341 18000000 .4byte .LVL17 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 43 - - - 1492 0345 01 .byte 0x1 - 1493 0346 DE020000 .4byte 0x2de - 1494 034a 0E .uleb128 0xe - 1495 034b 1C000000 .4byte .LVL18 - 1496 034f 01 .byte 0x1 - 1497 0350 B3020000 .4byte 0x2b3 - 1498 0354 00 .byte 0 - 1499 0355 0F .uleb128 0xf - 1500 0356 01 .byte 0x1 - 1501 0357 67010000 .4byte .LASF43 - 1502 035b 01 .byte 0x1 - 1503 035c E401 .2byte 0x1e4 - 1504 035e 01 .byte 0x1 - 1505 035f 00000000 .4byte .LFB8 - 1506 0363 34000000 .4byte .LFE8 - 1507 0367 EB000000 .4byte .LLST7 - 1508 036b 01 .byte 0x1 - 1509 036c 80030000 .4byte 0x380 - 1510 0370 11 .uleb128 0x11 - 1511 0371 1C000000 .4byte .LVL19 - 1512 0375 88020000 .4byte 0x288 - 1513 0379 12 .uleb128 0x12 - 1514 037a 01 .byte 0x1 - 1515 037b 50 .byte 0x50 - 1516 037c 01 .byte 0x1 - 1517 037d 31 .byte 0x31 - 1518 037e 00 .byte 0 - 1519 037f 00 .byte 0 - 1520 0380 15 .uleb128 0x15 - 1521 0381 01 .byte 0x1 - 1522 0382 8A020000 .4byte .LASF44 - 1523 0386 01 .byte 0x1 - 1524 0387 F5 .byte 0xf5 - 1525 0388 01 .byte 0x1 - 1526 0389 00000000 .4byte .LFB3 - 1527 038d 38000000 .4byte .LFE3 - 1528 0391 0B010000 .4byte .LLST8 - 1529 0395 01 .byte 0x1 - 1530 0396 BE030000 .4byte 0x3be - 1531 039a 0E .uleb128 0xe - 1532 039b 1A000000 .4byte .LVL20 - 1533 039f 01 .byte 0x1 - 1534 03a0 55030000 .4byte 0x355 - 1535 03a4 0E .uleb128 0xe - 1536 03a5 22000000 .4byte .LVL21 - 1537 03a9 01 .byte 0x1 - 1538 03aa 32020000 .4byte 0x232 - 1539 03ae 11 .uleb128 0x11 - 1540 03af 28000000 .4byte .LVL22 - 1541 03b3 88020000 .4byte 0x288 - 1542 03b7 12 .uleb128 0x12 - 1543 03b8 01 .byte 0x1 - 1544 03b9 50 .byte 0x50 - 1545 03ba 01 .byte 0x1 - 1546 03bb 33 .byte 0x33 - 1547 03bc 00 .byte 0 - 1548 03bd 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 44 - - - 1549 03be 15 .uleb128 0x15 - 1550 03bf 01 .byte 0x1 - 1551 03c0 CD040000 .4byte .LASF45 - 1552 03c4 01 .byte 0x1 - 1553 03c5 97 .byte 0x97 - 1554 03c6 01 .byte 0x1 - 1555 03c7 00000000 .4byte .LFB1 - 1556 03cb 54000000 .4byte .LFE1 - 1557 03cf 2B010000 .4byte .LLST9 - 1558 03d3 01 .byte 0x1 - 1559 03d4 16040000 .4byte 0x416 - 1560 03d8 16 .uleb128 0x16 - 1561 03d9 7A040000 .4byte .LASF46 - 1562 03dd 01 .byte 0x1 - 1563 03de 99 .byte 0x99 - 1564 03df 6F000000 .4byte 0x6f - 1565 03e3 4B010000 .4byte .LLST10 - 1566 03e7 17 .uleb128 0x17 - 1567 03e8 1A000000 .4byte .LVL26 - 1568 03ec 88020000 .4byte 0x288 - 1569 03f0 FA030000 .4byte 0x3fa - 1570 03f4 12 .uleb128 0x12 - 1571 03f5 01 .byte 0x1 - 1572 03f6 50 .byte 0x50 - 1573 03f7 01 .byte 0x1 - 1574 03f8 32 .byte 0x32 - 1575 03f9 00 .byte 0 - 1576 03fa 18 .uleb128 0x18 - 1577 03fb 30000000 .4byte .LVL27 - 1578 03ff 8C060000 .4byte 0x68c - 1579 0403 18 .uleb128 0x18 - 1580 0404 36000000 .4byte .LVL29 - 1581 0408 9A060000 .4byte 0x69a - 1582 040c 18 .uleb128 0x18 - 1583 040d 3C000000 .4byte .LVL31 - 1584 0411 A8060000 .4byte 0x6a8 - 1585 0415 00 .byte 0 - 1586 0416 15 .uleb128 0x15 - 1587 0417 01 .byte 0x1 - 1588 0418 1A000000 .4byte .LASF47 - 1589 041c 01 .byte 0x1 - 1590 041d 42 .byte 0x42 - 1591 041e 01 .byte 0x1 - 1592 041f 00000000 .4byte .LFB0 - 1593 0423 A0000000 .4byte .LFE0 - 1594 0427 8A010000 .4byte .LLST11 - 1595 042b 01 .byte 0x1 - 1596 042c 6A040000 .4byte 0x46a - 1597 0430 16 .uleb128 0x16 - 1598 0431 26010000 .4byte .LASF48 - 1599 0435 01 .byte 0x1 - 1600 0436 44 .byte 0x44 - 1601 0437 6F000000 .4byte 0x6f - 1602 043b AA010000 .4byte .LLST12 - 1603 043f 16 .uleb128 0x16 - 1604 0440 C3040000 .4byte .LASF49 - 1605 0444 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 45 - - - 1606 0445 45 .byte 0x45 - 1607 0446 6F000000 .4byte 0x6f - 1608 044a F9010000 .4byte .LLST13 - 1609 044e 18 .uleb128 0x18 - 1610 044f 24000000 .4byte .LVL35 - 1611 0453 BE030000 .4byte 0x3be - 1612 0457 18 .uleb128 0x18 - 1613 0458 3A000000 .4byte .LVL37 - 1614 045c 09030000 .4byte 0x309 - 1615 0460 18 .uleb128 0x18 - 1616 0461 48000000 .4byte .LVL40 - 1617 0465 80030000 .4byte 0x380 - 1618 0469 00 .byte 0 - 1619 046a 19 .uleb128 0x19 - 1620 046b 01 .byte 0x1 - 1621 046c 79030000 .4byte .LASF79 - 1622 0470 01 .byte 0x1 - 1623 0471 0203 .2byte 0x302 - 1624 0473 01 .byte 0x1 - 1625 0474 00000000 .4byte .LFB15 - 1626 0478 20000000 .4byte .LFE15 - 1627 047c 02 .byte 0x2 - 1628 047d 7D .byte 0x7d - 1629 047e 00 .sleb128 0 - 1630 047f 01 .byte 0x1 - 1631 0480 1A .uleb128 0x1a - 1632 0481 01 .byte 0x1 - 1633 0482 D8020000 .4byte .LASF51 - 1634 0486 01 .byte 0x1 - 1635 0487 0702 .2byte 0x207 - 1636 0489 01 .byte 0x1 - 1637 048a 6F000000 .4byte 0x6f - 1638 048e 00000000 .4byte .LFB9 - 1639 0492 48000000 .4byte .LFE9 - 1640 0496 23020000 .4byte .LLST14 - 1641 049a 01 .byte 0x1 - 1642 049b B9040000 .4byte 0x4b9 - 1643 049f 0B .uleb128 0xb - 1644 04a0 FE040000 .4byte .LASF50 - 1645 04a4 01 .byte 0x1 - 1646 04a5 0902 .2byte 0x209 - 1647 04a7 7A000000 .4byte 0x7a - 1648 04ab 43020000 .4byte .LLST15 - 1649 04af 18 .uleb128 0x18 - 1650 04b0 12000000 .4byte .LVL51 - 1651 04b4 6A040000 .4byte 0x46a - 1652 04b8 00 .byte 0 - 1653 04b9 1A .uleb128 0x1a - 1654 04ba 01 .byte 0x1 - 1655 04bb 51000000 .4byte .LASF52 - 1656 04bf 01 .byte 0x1 - 1657 04c0 7101 .2byte 0x171 - 1658 04c2 01 .byte 0x1 - 1659 04c3 6F000000 .4byte 0x6f - 1660 04c7 00000000 .4byte .LFB5 - 1661 04cb 50000000 .4byte .LFE5 - 1662 04cf 56020000 .4byte .LLST16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 46 - - - 1663 04d3 01 .byte 0x1 - 1664 04d4 04050000 .4byte 0x504 - 1665 04d8 0B .uleb128 0xb - 1666 04d9 FE040000 .4byte .LASF50 - 1667 04dd 01 .byte 0x1 - 1668 04de 7301 .2byte 0x173 - 1669 04e0 7A000000 .4byte 0x7a - 1670 04e4 76020000 .4byte .LLST17 - 1671 04e8 18 .uleb128 0x18 - 1672 04e9 0E000000 .4byte .LVL54 - 1673 04ed F8010000 .4byte 0x1f8 - 1674 04f1 18 .uleb128 0x18 - 1675 04f2 20000000 .4byte .LVL55 - 1676 04f6 6A040000 .4byte 0x46a - 1677 04fa 18 .uleb128 0x18 - 1678 04fb 3A000000 .4byte .LVL57 - 1679 04ff CD010000 .4byte 0x1cd - 1680 0503 00 .byte 0 - 1681 0504 1B .uleb128 0x1b - 1682 0505 2A040000 .4byte .LASF53 - 1683 0509 01 .byte 0x1 - 1684 050a 22 .byte 0x22 - 1685 050b A5000000 .4byte 0xa5 - 1686 050f 01 .byte 0x1 - 1687 0510 05 .byte 0x5 - 1688 0511 03 .byte 0x3 - 1689 0512 00000000 .4byte USBFS_device - 1690 0516 1B .uleb128 0x1b - 1691 0517 57030000 .4byte .LASF54 - 1692 051b 01 .byte 0x1 - 1693 051c 2C .byte 0x2c - 1694 051d A5000000 .4byte 0xa5 - 1695 0521 01 .byte 0x1 - 1696 0522 05 .byte 0x5 - 1697 0523 03 .byte 0x3 - 1698 0524 00000000 .4byte USBFS_transferState - 1699 0528 1B .uleb128 0x1b - 1700 0529 35010000 .4byte .LASF55 - 1701 052d 01 .byte 0x1 - 1702 052e 1A .byte 0x1a - 1703 052f A5000000 .4byte 0xa5 - 1704 0533 01 .byte 0x1 - 1705 0534 05 .byte 0x5 - 1706 0535 03 .byte 0x3 - 1707 0536 00000000 .4byte USBFS_configuration - 1708 053a 1B .uleb128 0x1b - 1709 053b 16020000 .4byte .LASF56 - 1710 053f 01 .byte 0x1 - 1711 0540 1C .byte 0x1c - 1712 0541 A5000000 .4byte 0xa5 - 1713 0545 01 .byte 0x1 - 1714 0546 05 .byte 0x5 - 1715 0547 03 .byte 0x3 - 1716 0548 00000000 .4byte USBFS_configurationChanged - 1717 054c 1B .uleb128 0x1b - 1718 054d 94040000 .4byte .LASF57 - 1719 0551 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 47 - - - 1720 0552 1E .byte 0x1e - 1721 0553 A5000000 .4byte 0xa5 - 1722 0557 01 .byte 0x1 - 1723 0558 05 .byte 0x5 - 1724 0559 03 .byte 0x3 - 1725 055a 00000000 .4byte USBFS_deviceStatus - 1726 055e 1B .uleb128 0x1b - 1727 055f CC000000 .4byte .LASF58 - 1728 0563 01 .byte 0x1 - 1729 0564 1B .byte 0x1b - 1730 0565 A5000000 .4byte 0xa5 - 1731 0569 01 .byte 0x1 - 1732 056a 05 .byte 0x5 - 1733 056b 03 .byte 0x3 - 1734 056c 00000000 .4byte USBFS_interfaceNumber - 1735 0570 1C .uleb128 0x1c - 1736 0571 6F000000 .4byte 0x6f - 1737 0575 80050000 .4byte 0x580 - 1738 0579 1D .uleb128 0x1d - 1739 057a AF000000 .4byte 0xaf - 1740 057e 00 .byte 0 - 1741 057f 00 .byte 0 - 1742 0580 1B .uleb128 0x1b - 1743 0581 BF030000 .4byte .LASF59 - 1744 0585 01 .byte 0x1 - 1745 0586 1F .byte 0x1f - 1746 0587 92050000 .4byte 0x592 - 1747 058b 01 .byte 0x1 - 1748 058c 05 .byte 0x5 - 1749 058d 03 .byte 0x3 - 1750 058e 00000000 .4byte USBFS_interfaceSetting - 1751 0592 05 .uleb128 0x5 - 1752 0593 70050000 .4byte 0x570 - 1753 0597 1B .uleb128 0x1b - 1754 0598 A7040000 .4byte .LASF60 - 1755 059c 01 .byte 0x1 - 1756 059d 20 .byte 0x20 - 1757 059e A9050000 .4byte 0x5a9 - 1758 05a2 01 .byte 0x1 - 1759 05a3 05 .byte 0x5 - 1760 05a4 03 .byte 0x3 - 1761 05a5 00000000 .4byte USBFS_interfaceSetting_last - 1762 05a9 05 .uleb128 0x5 - 1763 05aa 70050000 .4byte 0x570 - 1764 05ae 1B .uleb128 0x1b - 1765 05af B8000000 .4byte .LASF61 - 1766 05b3 01 .byte 0x1 - 1767 05b4 1D .byte 0x1d - 1768 05b5 A5000000 .4byte 0xa5 - 1769 05b9 01 .byte 0x1 - 1770 05ba 05 .byte 0x5 - 1771 05bb 03 .byte 0x3 - 1772 05bc 00000000 .4byte USBFS_deviceAddress - 1773 05c0 1B .uleb128 0x1b - 1774 05c1 08050000 .4byte .LASF62 - 1775 05c5 01 .byte 0x1 - 1776 05c6 21 .byte 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 48 - - - 1777 05c7 D2050000 .4byte 0x5d2 - 1778 05cb 01 .byte 0x1 - 1779 05cc 05 .byte 0x5 - 1780 05cd 03 .byte 0x3 - 1781 05ce 00000000 .4byte USBFS_interfaceStatus - 1782 05d2 05 .uleb128 0x5 - 1783 05d3 70050000 .4byte 0x570 - 1784 05d7 1B .uleb128 0x1b - 1785 05d8 62020000 .4byte .LASF63 - 1786 05dc 01 .byte 0x1 - 1787 05dd 23 .byte 0x23 - 1788 05de E9050000 .4byte 0x5e9 - 1789 05e2 01 .byte 0x1 - 1790 05e3 05 .byte 0x5 - 1791 05e4 03 .byte 0x3 - 1792 05e5 00000000 .4byte USBFS_interfaceClass - 1793 05e9 08 .uleb128 0x8 - 1794 05ea 04 .byte 0x4 - 1795 05eb EF050000 .4byte 0x5ef - 1796 05ef 1E .uleb128 0x1e - 1797 05f0 6F000000 .4byte 0x6f - 1798 05f4 1C .uleb128 0x1c - 1799 05f5 3D010000 .4byte 0x13d - 1800 05f9 04060000 .4byte 0x604 - 1801 05fd 1D .uleb128 0x1d - 1802 05fe AF000000 .4byte 0xaf - 1803 0602 08 .byte 0x8 - 1804 0603 00 .byte 0 - 1805 0604 1B .uleb128 0x1b - 1806 0605 00030000 .4byte .LASF64 - 1807 0609 01 .byte 0x1 - 1808 060a 19 .byte 0x19 - 1809 060b 16060000 .4byte 0x616 - 1810 060f 01 .byte 0x1 - 1811 0610 05 .byte 0x5 - 1812 0611 03 .byte 0x3 - 1813 0612 00000000 .4byte USBFS_EP - 1814 0616 05 .uleb128 0x5 - 1815 0617 F4050000 .4byte 0x5f4 - 1816 061b 1B .uleb128 0x1b - 1817 061c 29000000 .4byte .LASF65 - 1818 0620 01 .byte 0x1 - 1819 0621 2D .byte 0x2d - 1820 0622 2D060000 .4byte 0x62d - 1821 0626 01 .byte 0x1 - 1822 0627 05 .byte 0x5 - 1823 0628 03 .byte 0x3 - 1824 0629 00000000 .4byte USBFS_currentTD - 1825 062d 05 .uleb128 0x5 - 1826 062e B7010000 .4byte 0x1b7 - 1827 0632 1B .uleb128 0x1b - 1828 0633 37040000 .4byte .LASF66 - 1829 0637 01 .byte 0x1 - 1830 0638 2A .byte 0x2a - 1831 0639 A5000000 .4byte 0xa5 - 1832 063d 01 .byte 0x1 - 1833 063e 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 49 - - - 1834 063f 03 .byte 0x3 - 1835 0640 00000000 .4byte USBFS_ep0Toggle - 1836 0644 1B .uleb128 0x1b - 1837 0645 AA030000 .4byte .LASF67 - 1838 0649 01 .byte 0x1 - 1839 064a 2B .byte 0x2b - 1840 064b A5000000 .4byte 0xa5 - 1841 064f 01 .byte 0x1 - 1842 0650 05 .byte 0x5 - 1843 0651 03 .byte 0x3 - 1844 0652 00000000 .4byte USBFS_lastPacketSize - 1845 0656 1B .uleb128 0x1b - 1846 0657 9A020000 .4byte .LASF68 - 1847 065b 01 .byte 0x1 - 1848 065c 2E .byte 0x2e - 1849 065d A5000000 .4byte 0xa5 - 1850 0661 01 .byte 0x1 - 1851 0662 05 .byte 0x5 - 1852 0663 03 .byte 0x3 - 1853 0664 00000000 .4byte USBFS_ep0Mode - 1854 0668 1B .uleb128 0x1b - 1855 0669 AF020000 .4byte .LASF69 - 1856 066d 01 .byte 0x1 - 1857 066e 2F .byte 0x2f - 1858 066f A5000000 .4byte 0xa5 - 1859 0673 01 .byte 0x1 - 1860 0674 05 .byte 0x5 - 1861 0675 03 .byte 0x3 - 1862 0676 00000000 .4byte USBFS_ep0Count - 1863 067a 1B .uleb128 0x1b - 1864 067b F4010000 .4byte .LASF70 - 1865 067f 01 .byte 0x1 - 1866 0680 30 .byte 0x30 - 1867 0681 AA000000 .4byte 0xaa - 1868 0685 01 .byte 0x1 - 1869 0686 05 .byte 0x5 - 1870 0687 03 .byte 0x3 - 1871 0688 00000000 .4byte USBFS_transferByteCount - 1872 068c 1F .uleb128 0x1f - 1873 068d 01 .byte 0x1 - 1874 068e 1E050000 .4byte .LASF71 - 1875 0692 04 .byte 0x4 - 1876 0693 B1 .byte 0xb1 - 1877 0694 01 .byte 0x1 - 1878 0695 6F000000 .4byte 0x6f - 1879 0699 01 .byte 0x1 - 1880 069a 1F .uleb128 0x1f - 1881 069b 01 .byte 0x1 - 1882 069c E6040000 .4byte .LASF72 - 1883 06a0 04 .byte 0x4 - 1884 06a1 B2 .byte 0xb2 - 1885 06a2 01 .byte 0x1 - 1886 06a3 6F000000 .4byte 0x6f - 1887 06a7 01 .byte 0x1 - 1888 06a8 1F .uleb128 0x1f - 1889 06a9 01 .byte 0x1 - 1890 06aa 50010000 .4byte .LASF73 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 50 - - - 1891 06ae 04 .byte 0x4 - 1892 06af B3 .byte 0xb3 - 1893 06b0 01 .byte 0x1 - 1894 06b1 6F000000 .4byte 0x6f - 1895 06b5 01 .byte 0x1 - 1896 06b6 00 .byte 0 - 1897 .section .debug_abbrev,"",%progbits - 1898 .Ldebug_abbrev0: - 1899 0000 01 .uleb128 0x1 - 1900 0001 11 .uleb128 0x11 - 1901 0002 01 .byte 0x1 - 1902 0003 25 .uleb128 0x25 - 1903 0004 0E .uleb128 0xe - 1904 0005 13 .uleb128 0x13 - 1905 0006 0B .uleb128 0xb - 1906 0007 03 .uleb128 0x3 - 1907 0008 0E .uleb128 0xe - 1908 0009 1B .uleb128 0x1b - 1909 000a 0E .uleb128 0xe - 1910 000b 55 .uleb128 0x55 - 1911 000c 06 .uleb128 0x6 - 1912 000d 11 .uleb128 0x11 - 1913 000e 01 .uleb128 0x1 - 1914 000f 52 .uleb128 0x52 - 1915 0010 01 .uleb128 0x1 - 1916 0011 10 .uleb128 0x10 - 1917 0012 06 .uleb128 0x6 - 1918 0013 00 .byte 0 - 1919 0014 00 .byte 0 - 1920 0015 02 .uleb128 0x2 - 1921 0016 24 .uleb128 0x24 - 1922 0017 00 .byte 0 - 1923 0018 0B .uleb128 0xb - 1924 0019 0B .uleb128 0xb - 1925 001a 3E .uleb128 0x3e - 1926 001b 0B .uleb128 0xb - 1927 001c 03 .uleb128 0x3 - 1928 001d 0E .uleb128 0xe - 1929 001e 00 .byte 0 - 1930 001f 00 .byte 0 - 1931 0020 03 .uleb128 0x3 - 1932 0021 24 .uleb128 0x24 - 1933 0022 00 .byte 0 - 1934 0023 0B .uleb128 0xb - 1935 0024 0B .uleb128 0xb - 1936 0025 3E .uleb128 0x3e - 1937 0026 0B .uleb128 0xb - 1938 0027 03 .uleb128 0x3 - 1939 0028 08 .uleb128 0x8 - 1940 0029 00 .byte 0 - 1941 002a 00 .byte 0 - 1942 002b 04 .uleb128 0x4 - 1943 002c 16 .uleb128 0x16 - 1944 002d 00 .byte 0 - 1945 002e 03 .uleb128 0x3 - 1946 002f 0E .uleb128 0xe - 1947 0030 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 51 - - - 1948 0031 0B .uleb128 0xb - 1949 0032 3B .uleb128 0x3b - 1950 0033 0B .uleb128 0xb - 1951 0034 49 .uleb128 0x49 - 1952 0035 13 .uleb128 0x13 - 1953 0036 00 .byte 0 - 1954 0037 00 .byte 0 - 1955 0038 05 .uleb128 0x5 - 1956 0039 35 .uleb128 0x35 - 1957 003a 00 .byte 0 - 1958 003b 49 .uleb128 0x49 - 1959 003c 13 .uleb128 0x13 - 1960 003d 00 .byte 0 - 1961 003e 00 .byte 0 - 1962 003f 06 .uleb128 0x6 - 1963 0040 13 .uleb128 0x13 - 1964 0041 01 .byte 0x1 - 1965 0042 0B .uleb128 0xb - 1966 0043 0B .uleb128 0xb - 1967 0044 3A .uleb128 0x3a - 1968 0045 0B .uleb128 0xb - 1969 0046 3B .uleb128 0x3b - 1970 0047 0B .uleb128 0xb - 1971 0048 01 .uleb128 0x1 - 1972 0049 13 .uleb128 0x13 - 1973 004a 00 .byte 0 - 1974 004b 00 .byte 0 - 1975 004c 07 .uleb128 0x7 - 1976 004d 0D .uleb128 0xd - 1977 004e 00 .byte 0 - 1978 004f 03 .uleb128 0x3 - 1979 0050 0E .uleb128 0xe - 1980 0051 3A .uleb128 0x3a - 1981 0052 0B .uleb128 0xb - 1982 0053 3B .uleb128 0x3b - 1983 0054 0B .uleb128 0xb - 1984 0055 49 .uleb128 0x49 - 1985 0056 13 .uleb128 0x13 - 1986 0057 38 .uleb128 0x38 - 1987 0058 0A .uleb128 0xa - 1988 0059 00 .byte 0 - 1989 005a 00 .byte 0 - 1990 005b 08 .uleb128 0x8 - 1991 005c 0F .uleb128 0xf - 1992 005d 00 .byte 0 - 1993 005e 0B .uleb128 0xb - 1994 005f 0B .uleb128 0xb - 1995 0060 49 .uleb128 0x49 - 1996 0061 13 .uleb128 0x13 - 1997 0062 00 .byte 0 - 1998 0063 00 .byte 0 - 1999 0064 09 .uleb128 0x9 - 2000 0065 2E .uleb128 0x2e - 2001 0066 00 .byte 0 - 2002 0067 3F .uleb128 0x3f - 2003 0068 0C .uleb128 0xc - 2004 0069 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 52 - - - 2005 006a 0E .uleb128 0xe - 2006 006b 3A .uleb128 0x3a - 2007 006c 0B .uleb128 0xb - 2008 006d 3B .uleb128 0x3b - 2009 006e 05 .uleb128 0x5 - 2010 006f 27 .uleb128 0x27 - 2011 0070 0C .uleb128 0xc - 2012 0071 20 .uleb128 0x20 - 2013 0072 0B .uleb128 0xb - 2014 0073 00 .byte 0 - 2015 0074 00 .byte 0 - 2016 0075 0A .uleb128 0xa - 2017 0076 2E .uleb128 0x2e - 2018 0077 01 .byte 0x1 - 2019 0078 3F .uleb128 0x3f - 2020 0079 0C .uleb128 0xc - 2021 007a 03 .uleb128 0x3 - 2022 007b 0E .uleb128 0xe - 2023 007c 3A .uleb128 0x3a - 2024 007d 0B .uleb128 0xb - 2025 007e 3B .uleb128 0x3b - 2026 007f 05 .uleb128 0x5 - 2027 0080 27 .uleb128 0x27 - 2028 0081 0C .uleb128 0xc - 2029 0082 11 .uleb128 0x11 - 2030 0083 01 .uleb128 0x1 - 2031 0084 12 .uleb128 0x12 - 2032 0085 01 .uleb128 0x1 - 2033 0086 40 .uleb128 0x40 - 2034 0087 0A .uleb128 0xa - 2035 0088 9742 .uleb128 0x2117 - 2036 008a 0C .uleb128 0xc - 2037 008b 01 .uleb128 0x1 - 2038 008c 13 .uleb128 0x13 - 2039 008d 00 .byte 0 - 2040 008e 00 .byte 0 - 2041 008f 0B .uleb128 0xb - 2042 0090 34 .uleb128 0x34 - 2043 0091 00 .byte 0 - 2044 0092 03 .uleb128 0x3 - 2045 0093 0E .uleb128 0xe - 2046 0094 3A .uleb128 0x3a - 2047 0095 0B .uleb128 0xb - 2048 0096 3B .uleb128 0x3b - 2049 0097 05 .uleb128 0x5 - 2050 0098 49 .uleb128 0x49 - 2051 0099 13 .uleb128 0x13 - 2052 009a 02 .uleb128 0x2 - 2053 009b 06 .uleb128 0x6 - 2054 009c 00 .byte 0 - 2055 009d 00 .byte 0 - 2056 009e 0C .uleb128 0xc - 2057 009f 2E .uleb128 0x2e - 2058 00a0 00 .byte 0 - 2059 00a1 3F .uleb128 0x3f - 2060 00a2 0C .uleb128 0xc - 2061 00a3 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 53 - - - 2062 00a4 0E .uleb128 0xe - 2063 00a5 3A .uleb128 0x3a - 2064 00a6 0B .uleb128 0xb - 2065 00a7 3B .uleb128 0x3b - 2066 00a8 05 .uleb128 0x5 - 2067 00a9 27 .uleb128 0x27 - 2068 00aa 0C .uleb128 0xc - 2069 00ab 49 .uleb128 0x49 - 2070 00ac 13 .uleb128 0x13 - 2071 00ad 11 .uleb128 0x11 - 2072 00ae 01 .uleb128 0x1 - 2073 00af 12 .uleb128 0x12 - 2074 00b0 01 .uleb128 0x1 - 2075 00b1 40 .uleb128 0x40 - 2076 00b2 0A .uleb128 0xa - 2077 00b3 9742 .uleb128 0x2117 - 2078 00b5 0C .uleb128 0xc - 2079 00b6 00 .byte 0 - 2080 00b7 00 .byte 0 - 2081 00b8 0D .uleb128 0xd - 2082 00b9 2E .uleb128 0x2e - 2083 00ba 01 .byte 0x1 - 2084 00bb 31 .uleb128 0x31 - 2085 00bc 13 .uleb128 0x13 - 2086 00bd 11 .uleb128 0x11 - 2087 00be 01 .uleb128 0x1 - 2088 00bf 12 .uleb128 0x12 - 2089 00c0 01 .uleb128 0x1 - 2090 00c1 40 .uleb128 0x40 - 2091 00c2 0A .uleb128 0xa - 2092 00c3 9742 .uleb128 0x2117 - 2093 00c5 0C .uleb128 0xc - 2094 00c6 01 .uleb128 0x1 - 2095 00c7 13 .uleb128 0x13 - 2096 00c8 00 .byte 0 - 2097 00c9 00 .byte 0 - 2098 00ca 0E .uleb128 0xe - 2099 00cb 898201 .uleb128 0x4109 - 2100 00ce 00 .byte 0 - 2101 00cf 11 .uleb128 0x11 - 2102 00d0 01 .uleb128 0x1 - 2103 00d1 9542 .uleb128 0x2115 - 2104 00d3 0C .uleb128 0xc - 2105 00d4 31 .uleb128 0x31 - 2106 00d5 13 .uleb128 0x13 - 2107 00d6 00 .byte 0 - 2108 00d7 00 .byte 0 - 2109 00d8 0F .uleb128 0xf - 2110 00d9 2E .uleb128 0x2e - 2111 00da 01 .byte 0x1 - 2112 00db 3F .uleb128 0x3f - 2113 00dc 0C .uleb128 0xc - 2114 00dd 03 .uleb128 0x3 - 2115 00de 0E .uleb128 0xe - 2116 00df 3A .uleb128 0x3a - 2117 00e0 0B .uleb128 0xb - 2118 00e1 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 54 - - - 2119 00e2 05 .uleb128 0x5 - 2120 00e3 27 .uleb128 0x27 - 2121 00e4 0C .uleb128 0xc - 2122 00e5 11 .uleb128 0x11 - 2123 00e6 01 .uleb128 0x1 - 2124 00e7 12 .uleb128 0x12 - 2125 00e8 01 .uleb128 0x1 - 2126 00e9 40 .uleb128 0x40 - 2127 00ea 06 .uleb128 0x6 - 2128 00eb 9742 .uleb128 0x2117 - 2129 00ed 0C .uleb128 0xc - 2130 00ee 01 .uleb128 0x1 - 2131 00ef 13 .uleb128 0x13 - 2132 00f0 00 .byte 0 - 2133 00f1 00 .byte 0 - 2134 00f2 10 .uleb128 0x10 - 2135 00f3 05 .uleb128 0x5 - 2136 00f4 00 .byte 0 - 2137 00f5 03 .uleb128 0x3 - 2138 00f6 0E .uleb128 0xe - 2139 00f7 3A .uleb128 0x3a - 2140 00f8 0B .uleb128 0xb - 2141 00f9 3B .uleb128 0x3b - 2142 00fa 05 .uleb128 0x5 - 2143 00fb 49 .uleb128 0x49 - 2144 00fc 13 .uleb128 0x13 - 2145 00fd 02 .uleb128 0x2 - 2146 00fe 06 .uleb128 0x6 - 2147 00ff 00 .byte 0 - 2148 0100 00 .byte 0 - 2149 0101 11 .uleb128 0x11 - 2150 0102 898201 .uleb128 0x4109 - 2151 0105 01 .byte 0x1 - 2152 0106 11 .uleb128 0x11 - 2153 0107 01 .uleb128 0x1 - 2154 0108 31 .uleb128 0x31 - 2155 0109 13 .uleb128 0x13 - 2156 010a 00 .byte 0 - 2157 010b 00 .byte 0 - 2158 010c 12 .uleb128 0x12 - 2159 010d 8A8201 .uleb128 0x410a - 2160 0110 00 .byte 0 - 2161 0111 02 .uleb128 0x2 - 2162 0112 0A .uleb128 0xa - 2163 0113 9142 .uleb128 0x2111 - 2164 0115 0A .uleb128 0xa - 2165 0116 00 .byte 0 - 2166 0117 00 .byte 0 - 2167 0118 13 .uleb128 0x13 - 2168 0119 2E .uleb128 0x2e - 2169 011a 01 .byte 0x1 - 2170 011b 3F .uleb128 0x3f - 2171 011c 0C .uleb128 0xc - 2172 011d 03 .uleb128 0x3 - 2173 011e 0E .uleb128 0xe - 2174 011f 3A .uleb128 0x3a - 2175 0120 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 55 - - - 2176 0121 3B .uleb128 0x3b - 2177 0122 0B .uleb128 0xb - 2178 0123 27 .uleb128 0x27 - 2179 0124 0C .uleb128 0xc - 2180 0125 11 .uleb128 0x11 - 2181 0126 01 .uleb128 0x1 - 2182 0127 12 .uleb128 0x12 - 2183 0128 01 .uleb128 0x1 - 2184 0129 40 .uleb128 0x40 - 2185 012a 0A .uleb128 0xa - 2186 012b 9742 .uleb128 0x2117 - 2187 012d 0C .uleb128 0xc - 2188 012e 01 .uleb128 0x1 - 2189 012f 13 .uleb128 0x13 - 2190 0130 00 .byte 0 - 2191 0131 00 .byte 0 - 2192 0132 14 .uleb128 0x14 - 2193 0133 1D .uleb128 0x1d - 2194 0134 01 .byte 0x1 - 2195 0135 31 .uleb128 0x31 - 2196 0136 13 .uleb128 0x13 - 2197 0137 11 .uleb128 0x11 - 2198 0138 01 .uleb128 0x1 - 2199 0139 12 .uleb128 0x12 - 2200 013a 01 .uleb128 0x1 - 2201 013b 58 .uleb128 0x58 - 2202 013c 0B .uleb128 0xb - 2203 013d 59 .uleb128 0x59 - 2204 013e 0B .uleb128 0xb - 2205 013f 01 .uleb128 0x1 - 2206 0140 13 .uleb128 0x13 - 2207 0141 00 .byte 0 - 2208 0142 00 .byte 0 - 2209 0143 15 .uleb128 0x15 - 2210 0144 2E .uleb128 0x2e - 2211 0145 01 .byte 0x1 - 2212 0146 3F .uleb128 0x3f - 2213 0147 0C .uleb128 0xc - 2214 0148 03 .uleb128 0x3 - 2215 0149 0E .uleb128 0xe - 2216 014a 3A .uleb128 0x3a - 2217 014b 0B .uleb128 0xb - 2218 014c 3B .uleb128 0x3b - 2219 014d 0B .uleb128 0xb - 2220 014e 27 .uleb128 0x27 - 2221 014f 0C .uleb128 0xc - 2222 0150 11 .uleb128 0x11 - 2223 0151 01 .uleb128 0x1 - 2224 0152 12 .uleb128 0x12 - 2225 0153 01 .uleb128 0x1 - 2226 0154 40 .uleb128 0x40 - 2227 0155 06 .uleb128 0x6 - 2228 0156 9742 .uleb128 0x2117 - 2229 0158 0C .uleb128 0xc - 2230 0159 01 .uleb128 0x1 - 2231 015a 13 .uleb128 0x13 - 2232 015b 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 56 - - - 2233 015c 00 .byte 0 - 2234 015d 16 .uleb128 0x16 - 2235 015e 34 .uleb128 0x34 - 2236 015f 00 .byte 0 - 2237 0160 03 .uleb128 0x3 - 2238 0161 0E .uleb128 0xe - 2239 0162 3A .uleb128 0x3a - 2240 0163 0B .uleb128 0xb - 2241 0164 3B .uleb128 0x3b - 2242 0165 0B .uleb128 0xb - 2243 0166 49 .uleb128 0x49 - 2244 0167 13 .uleb128 0x13 - 2245 0168 02 .uleb128 0x2 - 2246 0169 06 .uleb128 0x6 - 2247 016a 00 .byte 0 - 2248 016b 00 .byte 0 - 2249 016c 17 .uleb128 0x17 - 2250 016d 898201 .uleb128 0x4109 - 2251 0170 01 .byte 0x1 - 2252 0171 11 .uleb128 0x11 - 2253 0172 01 .uleb128 0x1 - 2254 0173 31 .uleb128 0x31 - 2255 0174 13 .uleb128 0x13 - 2256 0175 01 .uleb128 0x1 - 2257 0176 13 .uleb128 0x13 - 2258 0177 00 .byte 0 - 2259 0178 00 .byte 0 - 2260 0179 18 .uleb128 0x18 - 2261 017a 898201 .uleb128 0x4109 - 2262 017d 00 .byte 0 - 2263 017e 11 .uleb128 0x11 - 2264 017f 01 .uleb128 0x1 - 2265 0180 31 .uleb128 0x31 - 2266 0181 13 .uleb128 0x13 - 2267 0182 00 .byte 0 - 2268 0183 00 .byte 0 - 2269 0184 19 .uleb128 0x19 - 2270 0185 2E .uleb128 0x2e - 2271 0186 00 .byte 0 - 2272 0187 3F .uleb128 0x3f - 2273 0188 0C .uleb128 0xc - 2274 0189 03 .uleb128 0x3 - 2275 018a 0E .uleb128 0xe - 2276 018b 3A .uleb128 0x3a - 2277 018c 0B .uleb128 0xb - 2278 018d 3B .uleb128 0x3b - 2279 018e 05 .uleb128 0x5 - 2280 018f 27 .uleb128 0x27 - 2281 0190 0C .uleb128 0xc - 2282 0191 11 .uleb128 0x11 - 2283 0192 01 .uleb128 0x1 - 2284 0193 12 .uleb128 0x12 - 2285 0194 01 .uleb128 0x1 - 2286 0195 40 .uleb128 0x40 - 2287 0196 0A .uleb128 0xa - 2288 0197 9742 .uleb128 0x2117 - 2289 0199 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 57 - - - 2290 019a 00 .byte 0 - 2291 019b 00 .byte 0 - 2292 019c 1A .uleb128 0x1a - 2293 019d 2E .uleb128 0x2e - 2294 019e 01 .byte 0x1 - 2295 019f 3F .uleb128 0x3f - 2296 01a0 0C .uleb128 0xc - 2297 01a1 03 .uleb128 0x3 - 2298 01a2 0E .uleb128 0xe - 2299 01a3 3A .uleb128 0x3a - 2300 01a4 0B .uleb128 0xb - 2301 01a5 3B .uleb128 0x3b - 2302 01a6 05 .uleb128 0x5 - 2303 01a7 27 .uleb128 0x27 - 2304 01a8 0C .uleb128 0xc - 2305 01a9 49 .uleb128 0x49 - 2306 01aa 13 .uleb128 0x13 - 2307 01ab 11 .uleb128 0x11 - 2308 01ac 01 .uleb128 0x1 - 2309 01ad 12 .uleb128 0x12 - 2310 01ae 01 .uleb128 0x1 - 2311 01af 40 .uleb128 0x40 - 2312 01b0 06 .uleb128 0x6 - 2313 01b1 9742 .uleb128 0x2117 - 2314 01b3 0C .uleb128 0xc - 2315 01b4 01 .uleb128 0x1 - 2316 01b5 13 .uleb128 0x13 - 2317 01b6 00 .byte 0 - 2318 01b7 00 .byte 0 - 2319 01b8 1B .uleb128 0x1b - 2320 01b9 34 .uleb128 0x34 - 2321 01ba 00 .byte 0 - 2322 01bb 03 .uleb128 0x3 - 2323 01bc 0E .uleb128 0xe - 2324 01bd 3A .uleb128 0x3a - 2325 01be 0B .uleb128 0xb - 2326 01bf 3B .uleb128 0x3b - 2327 01c0 0B .uleb128 0xb - 2328 01c1 49 .uleb128 0x49 - 2329 01c2 13 .uleb128 0x13 - 2330 01c3 3F .uleb128 0x3f - 2331 01c4 0C .uleb128 0xc - 2332 01c5 02 .uleb128 0x2 - 2333 01c6 0A .uleb128 0xa - 2334 01c7 00 .byte 0 - 2335 01c8 00 .byte 0 - 2336 01c9 1C .uleb128 0x1c - 2337 01ca 01 .uleb128 0x1 - 2338 01cb 01 .byte 0x1 - 2339 01cc 49 .uleb128 0x49 - 2340 01cd 13 .uleb128 0x13 - 2341 01ce 01 .uleb128 0x1 - 2342 01cf 13 .uleb128 0x13 - 2343 01d0 00 .byte 0 - 2344 01d1 00 .byte 0 - 2345 01d2 1D .uleb128 0x1d - 2346 01d3 21 .uleb128 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 58 - - - 2347 01d4 00 .byte 0 - 2348 01d5 49 .uleb128 0x49 - 2349 01d6 13 .uleb128 0x13 - 2350 01d7 2F .uleb128 0x2f - 2351 01d8 0B .uleb128 0xb - 2352 01d9 00 .byte 0 - 2353 01da 00 .byte 0 - 2354 01db 1E .uleb128 0x1e - 2355 01dc 26 .uleb128 0x26 - 2356 01dd 00 .byte 0 - 2357 01de 49 .uleb128 0x49 - 2358 01df 13 .uleb128 0x13 - 2359 01e0 00 .byte 0 - 2360 01e1 00 .byte 0 - 2361 01e2 1F .uleb128 0x1f - 2362 01e3 2E .uleb128 0x2e - 2363 01e4 00 .byte 0 - 2364 01e5 3F .uleb128 0x3f - 2365 01e6 0C .uleb128 0xc - 2366 01e7 03 .uleb128 0x3 - 2367 01e8 0E .uleb128 0xe - 2368 01e9 3A .uleb128 0x3a - 2369 01ea 0B .uleb128 0xb - 2370 01eb 3B .uleb128 0x3b - 2371 01ec 0B .uleb128 0xb - 2372 01ed 27 .uleb128 0x27 - 2373 01ee 0C .uleb128 0xc - 2374 01ef 49 .uleb128 0x49 - 2375 01f0 13 .uleb128 0x13 - 2376 01f1 3C .uleb128 0x3c - 2377 01f2 0C .uleb128 0xc - 2378 01f3 00 .byte 0 - 2379 01f4 00 .byte 0 - 2380 01f5 00 .byte 0 - 2381 .section .debug_loc,"",%progbits - 2382 .Ldebug_loc0: - 2383 .LLST0: - 2384 0000 00000000 .4byte .LVL0 - 2385 0004 10000000 .4byte .LVL1 - 2386 0008 0200 .2byte 0x2 - 2387 000a 30 .byte 0x30 - 2388 000b 9F .byte 0x9f - 2389 000c 00000000 .4byte 0 - 2390 0010 00000000 .4byte 0 - 2391 .LLST1: - 2392 0014 00000000 .4byte .LFB10 - 2393 0018 02000000 .4byte .LCFI0 - 2394 001c 0200 .2byte 0x2 - 2395 001e 7D .byte 0x7d - 2396 001f 00 .sleb128 0 - 2397 0020 02000000 .4byte .LCFI0 - 2398 0024 74000000 .4byte .LFE10 - 2399 0028 0200 .2byte 0x2 - 2400 002a 7D .byte 0x7d - 2401 002b 08 .sleb128 8 - 2402 002c 00000000 .4byte 0 - 2403 0030 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 59 - - - 2404 .LLST2: - 2405 0034 12000000 .4byte .LVL4 - 2406 0038 14000000 .4byte .LVL5 - 2407 003c 0100 .2byte 0x1 - 2408 003e 51 .byte 0x51 - 2409 003f 14000000 .4byte .LVL5 - 2410 0043 2C000000 .4byte .LVL7 - 2411 0047 0100 .2byte 0x1 - 2412 0049 52 .byte 0x52 - 2413 004a 2C000000 .4byte .LVL7 - 2414 004e 32000000 .4byte .LVL8 - 2415 0052 0300 .2byte 0x3 - 2416 0054 72 .byte 0x72 - 2417 0055 01 .sleb128 1 - 2418 0056 9F .byte 0x9f - 2419 0057 36000000 .4byte .LVL9 - 2420 005b 48000000 .4byte .LVL10 - 2421 005f 0100 .2byte 0x1 - 2422 0061 52 .byte 0x52 - 2423 0062 00000000 .4byte 0 - 2424 0066 00000000 .4byte 0 - 2425 .LLST3: - 2426 006a 00000000 .4byte .LVL3 - 2427 006e 1A000000 .4byte .LVL6 - 2428 0072 0200 .2byte 0x2 - 2429 0074 30 .byte 0x30 - 2430 0075 9F .byte 0x9f - 2431 0076 00000000 .4byte 0 - 2432 007a 00000000 .4byte 0 - 2433 .LLST4: - 2434 007e 00000000 .4byte .LVL11 - 2435 0082 0E000000 .4byte .LVL12 - 2436 0086 0100 .2byte 0x1 - 2437 0088 50 .byte 0x50 - 2438 0089 0E000000 .4byte .LVL12 - 2439 008d 10000000 .4byte .LVL13 - 2440 0091 0200 .2byte 0x2 - 2441 0093 71 .byte 0x71 - 2442 0094 00 .sleb128 0 - 2443 0095 10000000 .4byte .LVL13 - 2444 0099 20000000 .4byte .LFE14 - 2445 009d 0400 .2byte 0x4 - 2446 009f F3 .byte 0xf3 - 2447 00a0 01 .uleb128 0x1 - 2448 00a1 50 .byte 0x50 - 2449 00a2 9F .byte 0x9f - 2450 00a3 00000000 .4byte 0 - 2451 00a7 00000000 .4byte 0 - 2452 .LLST5: - 2453 00ab 00000000 .4byte .LFB13 - 2454 00af 02000000 .4byte .LCFI1 - 2455 00b3 0200 .2byte 0x2 - 2456 00b5 7D .byte 0x7d - 2457 00b6 00 .sleb128 0 - 2458 00b7 02000000 .4byte .LCFI1 - 2459 00bb 3C000000 .4byte .LFE13 - 2460 00bf 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 60 - - - 2461 00c1 7D .byte 0x7d - 2462 00c2 08 .sleb128 8 - 2463 00c3 00000000 .4byte 0 - 2464 00c7 00000000 .4byte 0 - 2465 .LLST6: - 2466 00cb 00000000 .4byte .LFB11 - 2467 00cf 02000000 .4byte .LCFI2 - 2468 00d3 0200 .2byte 0x2 - 2469 00d5 7D .byte 0x7d - 2470 00d6 00 .sleb128 0 - 2471 00d7 02000000 .4byte .LCFI2 - 2472 00db 20000000 .4byte .LFE11 - 2473 00df 0200 .2byte 0x2 - 2474 00e1 7D .byte 0x7d - 2475 00e2 08 .sleb128 8 - 2476 00e3 00000000 .4byte 0 - 2477 00e7 00000000 .4byte 0 - 2478 .LLST7: - 2479 00eb 00000000 .4byte .LFB8 - 2480 00ef 02000000 .4byte .LCFI3 - 2481 00f3 0200 .2byte 0x2 - 2482 00f5 7D .byte 0x7d - 2483 00f6 00 .sleb128 0 - 2484 00f7 02000000 .4byte .LCFI3 - 2485 00fb 34000000 .4byte .LFE8 - 2486 00ff 0200 .2byte 0x2 - 2487 0101 7D .byte 0x7d - 2488 0102 08 .sleb128 8 - 2489 0103 00000000 .4byte 0 - 2490 0107 00000000 .4byte 0 - 2491 .LLST8: - 2492 010b 00000000 .4byte .LFB3 - 2493 010f 02000000 .4byte .LCFI4 - 2494 0113 0200 .2byte 0x2 - 2495 0115 7D .byte 0x7d - 2496 0116 00 .sleb128 0 - 2497 0117 02000000 .4byte .LCFI4 - 2498 011b 38000000 .4byte .LFE3 - 2499 011f 0200 .2byte 0x2 - 2500 0121 7D .byte 0x7d - 2501 0122 08 .sleb128 8 - 2502 0123 00000000 .4byte 0 - 2503 0127 00000000 .4byte 0 - 2504 .LLST9: - 2505 012b 00000000 .4byte .LFB1 - 2506 012f 02000000 .4byte .LCFI5 - 2507 0133 0200 .2byte 0x2 - 2508 0135 7D .byte 0x7d - 2509 0136 00 .sleb128 0 - 2510 0137 02000000 .4byte .LCFI5 - 2511 013b 54000000 .4byte .LFE1 - 2512 013f 0200 .2byte 0x2 - 2513 0141 7D .byte 0x7d - 2514 0142 08 .sleb128 8 - 2515 0143 00000000 .4byte 0 - 2516 0147 00000000 .4byte 0 - 2517 .LLST10: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 61 - - - 2518 014b 06000000 .4byte .LVL23 - 2519 014f 0A000000 .4byte .LVL24 - 2520 0153 0100 .2byte 0x1 - 2521 0155 52 .byte 0x52 - 2522 0156 0A000000 .4byte .LVL24 - 2523 015a 16000000 .4byte .LVL25 - 2524 015e 0100 .2byte 0x1 - 2525 0160 50 .byte 0x50 - 2526 0161 30000000 .4byte .LVL27 - 2527 0165 32000000 .4byte .LVL28 - 2528 0169 0100 .2byte 0x1 - 2529 016b 50 .byte 0x50 - 2530 016c 36000000 .4byte .LVL29 - 2531 0170 38000000 .4byte .LVL30 - 2532 0174 0100 .2byte 0x1 - 2533 0176 50 .byte 0x50 - 2534 0177 3C000000 .4byte .LVL31 - 2535 017b 3E000000 .4byte .LVL32 - 2536 017f 0100 .2byte 0x1 - 2537 0181 50 .byte 0x50 - 2538 0182 00000000 .4byte 0 - 2539 0186 00000000 .4byte 0 - 2540 .LLST11: - 2541 018a 00000000 .4byte .LFB0 - 2542 018e 02000000 .4byte .LCFI6 - 2543 0192 0200 .2byte 0x2 - 2544 0194 7D .byte 0x7d - 2545 0195 00 .sleb128 0 - 2546 0196 02000000 .4byte .LCFI6 - 2547 019a A0000000 .4byte .LFE0 - 2548 019e 0200 .2byte 0x2 - 2549 01a0 7D .byte 0x7d - 2550 01a1 08 .sleb128 8 - 2551 01a2 00000000 .4byte 0 - 2552 01a6 00000000 .4byte 0 - 2553 .LLST12: - 2554 01aa 08000000 .4byte .LVL33 - 2555 01ae 23000000 .4byte .LVL35-1 - 2556 01b2 0100 .2byte 0x1 - 2557 01b4 52 .byte 0x52 - 2558 01b5 2E000000 .4byte .LVL36 - 2559 01b9 39000000 .4byte .LVL37-1 - 2560 01bd 0100 .2byte 0x1 - 2561 01bf 52 .byte 0x52 - 2562 01c0 3C000000 .4byte .LVL38 - 2563 01c4 42000000 .4byte .LVL39 - 2564 01c8 0100 .2byte 0x1 - 2565 01ca 52 .byte 0x52 - 2566 01cb 4C000000 .4byte .LVL41 - 2567 01cf 4E000000 .4byte .LVL42 - 2568 01d3 0100 .2byte 0x1 - 2569 01d5 51 .byte 0x51 - 2570 01d6 5C000000 .4byte .LVL43 - 2571 01da 66000000 .4byte .LVL44 - 2572 01de 0100 .2byte 0x1 - 2573 01e0 53 .byte 0x53 - 2574 01e1 6E000000 .4byte .LVL46 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 62 - - - 2575 01e5 72000000 .4byte .LVL47 - 2576 01e9 0600 .2byte 0x6 - 2577 01eb 70 .byte 0x70 - 2578 01ec 00 .sleb128 0 - 2579 01ed 09 .byte 0x9 - 2580 01ee 80 .byte 0x80 - 2581 01ef 1A .byte 0x1a - 2582 01f0 9F .byte 0x9f - 2583 01f1 00000000 .4byte 0 - 2584 01f5 00000000 .4byte 0 - 2585 .LLST13: - 2586 01f9 12000000 .4byte .LVL34 - 2587 01fd 66000000 .4byte .LVL44 - 2588 0201 0200 .2byte 0x2 - 2589 0203 31 .byte 0x31 - 2590 0204 9F .byte 0x9f - 2591 0205 6C000000 .4byte .LVL45 - 2592 0209 78000000 .4byte .LVL48 - 2593 020d 0100 .2byte 0x1 - 2594 020f 52 .byte 0x52 - 2595 0210 80000000 .4byte .LVL49 - 2596 0214 8A000000 .4byte .LVL50 - 2597 0218 0100 .2byte 0x1 - 2598 021a 52 .byte 0x52 - 2599 021b 00000000 .4byte 0 - 2600 021f 00000000 .4byte 0 - 2601 .LLST14: - 2602 0223 00000000 .4byte .LFB9 - 2603 0227 02000000 .4byte .LCFI7 - 2604 022b 0200 .2byte 0x2 - 2605 022d 7D .byte 0x7d - 2606 022e 00 .sleb128 0 - 2607 022f 02000000 .4byte .LCFI7 - 2608 0233 48000000 .4byte .LFE9 - 2609 0237 0200 .2byte 0x2 - 2610 0239 7D .byte 0x7d - 2611 023a 08 .sleb128 8 - 2612 023b 00000000 .4byte 0 - 2613 023f 00000000 .4byte 0 - 2614 .LLST15: - 2615 0243 22000000 .4byte .LVL52 - 2616 0247 2E000000 .4byte .LVL53 - 2617 024b 0100 .2byte 0x1 - 2618 024d 52 .byte 0x52 - 2619 024e 00000000 .4byte 0 - 2620 0252 00000000 .4byte 0 - 2621 .LLST16: - 2622 0256 00000000 .4byte .LFB5 - 2623 025a 02000000 .4byte .LCFI8 - 2624 025e 0200 .2byte 0x2 - 2625 0260 7D .byte 0x7d - 2626 0261 00 .sleb128 0 - 2627 0262 02000000 .4byte .LCFI8 - 2628 0266 50000000 .4byte .LFE5 - 2629 026a 0200 .2byte 0x2 - 2630 026c 7D .byte 0x7d - 2631 026d 08 .sleb128 8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 63 - - - 2632 026e 00000000 .4byte 0 - 2633 0272 00000000 .4byte 0 - 2634 .LLST17: - 2635 0276 2C000000 .4byte .LVL56 - 2636 027a 39000000 .4byte .LVL57-1 - 2637 027e 0100 .2byte 0x1 - 2638 0280 51 .byte 0x51 - 2639 0281 00000000 .4byte 0 - 2640 0285 00000000 .4byte 0 - 2641 .section .debug_aranges,"",%progbits - 2642 0000 94000000 .4byte 0x94 - 2643 0004 0200 .2byte 0x2 - 2644 0006 00000000 .4byte .Ldebug_info0 - 2645 000a 04 .byte 0x4 - 2646 000b 00 .byte 0 - 2647 000c 0000 .2byte 0 - 2648 000e 0000 .2byte 0 - 2649 0010 00000000 .4byte .LFB4 - 2650 0014 94000000 .4byte .LFE4-.LFB4 - 2651 0018 00000000 .4byte .LFB6 - 2652 001c 34000000 .4byte .LFE6-.LFB6 - 2653 0020 00000000 .4byte .LFB7 - 2654 0024 04000000 .4byte .LFE7-.LFB7 - 2655 0028 00000000 .4byte .LFB10 - 2656 002c 74000000 .4byte .LFE10-.LFB10 - 2657 0030 00000000 .4byte .LFB12 - 2658 0034 2C000000 .4byte .LFE12-.LFB12 - 2659 0038 00000000 .4byte .LFB14 - 2660 003c 20000000 .4byte .LFE14-.LFB14 - 2661 0040 00000000 .4byte .LFB13 - 2662 0044 3C000000 .4byte .LFE13-.LFB13 - 2663 0048 00000000 .4byte .LFB11 - 2664 004c 20000000 .4byte .LFE11-.LFB11 - 2665 0050 00000000 .4byte .LFB2 - 2666 0054 24000000 .4byte .LFE2-.LFB2 - 2667 0058 00000000 .4byte .LFB8 - 2668 005c 34000000 .4byte .LFE8-.LFB8 - 2669 0060 00000000 .4byte .LFB3 - 2670 0064 38000000 .4byte .LFE3-.LFB3 - 2671 0068 00000000 .4byte .LFB1 - 2672 006c 54000000 .4byte .LFE1-.LFB1 - 2673 0070 00000000 .4byte .LFB0 - 2674 0074 A0000000 .4byte .LFE0-.LFB0 - 2675 0078 00000000 .4byte .LFB15 - 2676 007c 20000000 .4byte .LFE15-.LFB15 - 2677 0080 00000000 .4byte .LFB9 - 2678 0084 48000000 .4byte .LFE9-.LFB9 - 2679 0088 00000000 .4byte .LFB5 - 2680 008c 50000000 .4byte .LFE5-.LFB5 - 2681 0090 00000000 .4byte 0 - 2682 0094 00000000 .4byte 0 - 2683 .section .debug_ranges,"",%progbits - 2684 .Ldebug_ranges0: - 2685 0000 00000000 .4byte .LFB4 - 2686 0004 94000000 .4byte .LFE4 - 2687 0008 00000000 .4byte .LFB6 - 2688 000c 34000000 .4byte .LFE6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 64 - - - 2689 0010 00000000 .4byte .LFB7 - 2690 0014 04000000 .4byte .LFE7 - 2691 0018 00000000 .4byte .LFB10 - 2692 001c 74000000 .4byte .LFE10 - 2693 0020 00000000 .4byte .LFB12 - 2694 0024 2C000000 .4byte .LFE12 - 2695 0028 00000000 .4byte .LFB14 - 2696 002c 20000000 .4byte .LFE14 - 2697 0030 00000000 .4byte .LFB13 - 2698 0034 3C000000 .4byte .LFE13 - 2699 0038 00000000 .4byte .LFB11 - 2700 003c 20000000 .4byte .LFE11 - 2701 0040 00000000 .4byte .LFB2 - 2702 0044 24000000 .4byte .LFE2 - 2703 0048 00000000 .4byte .LFB8 - 2704 004c 34000000 .4byte .LFE8 - 2705 0050 00000000 .4byte .LFB3 - 2706 0054 38000000 .4byte .LFE3 - 2707 0058 00000000 .4byte .LFB1 - 2708 005c 54000000 .4byte .LFE1 - 2709 0060 00000000 .4byte .LFB0 - 2710 0064 A0000000 .4byte .LFE0 - 2711 0068 00000000 .4byte .LFB15 - 2712 006c 20000000 .4byte .LFE15 - 2713 0070 00000000 .4byte .LFB9 - 2714 0074 48000000 .4byte .LFE9 - 2715 0078 00000000 .4byte .LFB5 - 2716 007c 50000000 .4byte .LFE5 - 2717 0080 00000000 .4byte 0 - 2718 0084 00000000 .4byte 0 - 2719 .section .debug_line,"",%progbits - 2720 .Ldebug_line0: - 2721 0000 49020000 .section .debug_str,"MS",%progbits,1 - 2721 02006200 - 2721 00000201 - 2721 FB0E0D00 - 2721 01010101 - 2722 .LASF31: - 2723 0000 70537461 .ascii "pStatusBlock\000" - 2723 74757342 - 2723 6C6F636B - 2723 00 - 2724 .LASF29: - 2725 000d 636F756E .ascii "count\000" - 2725 7400 - 2726 .LASF10: - 2727 0013 75696E74 .ascii "uint16\000" - 2727 313600 - 2728 .LASF47: - 2729 001a 55534246 .ascii "USBFS_EP_0_ISR\000" - 2729 535F4550 - 2729 5F305F49 - 2729 535200 - 2730 .LASF65: - 2731 0029 55534246 .ascii "USBFS_currentTD\000" - 2731 535F6375 - 2731 7272656E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 65 - - - 2731 74544400 - 2732 .LASF36: - 2733 0039 72656749 .ascii "regIndex\000" - 2733 6E646578 - 2733 00 - 2734 .LASF78: - 2735 0042 636F6D70 .ascii "completionCode\000" - 2735 6C657469 - 2735 6F6E436F - 2735 646500 - 2736 .LASF52: - 2737 0051 55534246 .ascii "USBFS_InitControlRead\000" - 2737 535F496E - 2737 6974436F - 2737 6E74726F - 2737 6C526561 - 2738 .LASF7: - 2739 0067 6C6F6E67 .ascii "long long unsigned int\000" - 2739 206C6F6E - 2739 6720756E - 2739 7369676E - 2739 65642069 - 2740 .LASF20: - 2741 007e 61646472 .ascii "addr\000" - 2741 00 - 2742 .LASF77: - 2743 0083 55534246 .ascii "USBFS_ControlReadDataStage\000" - 2743 535F436F - 2743 6E74726F - 2743 6C526561 - 2743 64446174 - 2744 .LASF6: - 2745 009e 6C6F6E67 .ascii "long long int\000" - 2745 206C6F6E - 2745 6720696E - 2745 7400 - 2746 .LASF0: - 2747 00ac 7369676E .ascii "signed char\000" - 2747 65642063 - 2747 68617200 - 2748 .LASF61: - 2749 00b8 55534246 .ascii "USBFS_deviceAddress\000" - 2749 535F6465 - 2749 76696365 - 2749 41646472 - 2749 65737300 - 2750 .LASF58: - 2751 00cc 55534246 .ascii "USBFS_interfaceNumber\000" - 2751 535F696E - 2751 74657266 - 2751 6163654E - 2751 756D6265 - 2752 .LASF4: - 2753 00e2 6C6F6E67 .ascii "long int\000" - 2753 20696E74 - 2753 00 - 2754 .LASF9: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 66 - - - 2755 00eb 75696E74 .ascii "uint8\000" - 2755 3800 - 2756 .LASF19: - 2757 00f1 6570546F .ascii "epToggle\000" - 2757 67676C65 - 2757 00 - 2758 .LASF75: - 2759 00fa 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_drv.c\000" - 2759 6E657261 - 2759 7465645F - 2759 536F7572 - 2759 63655C50 - 2760 .LASF12: - 2761 011f 646F7562 .ascii "double\000" - 2761 6C6500 - 2762 .LASF48: - 2763 0126 62526567 .ascii "bRegTemp\000" - 2763 54656D70 - 2763 00 - 2764 .LASF30: - 2765 012f 70446174 .ascii "pData\000" - 2765 6100 - 2766 .LASF55: - 2767 0135 55534246 .ascii "USBFS_configuration\000" - 2767 535F636F - 2767 6E666967 - 2767 75726174 - 2767 696F6E00 - 2768 .LASF21: - 2769 0149 65704D6F .ascii "epMode\000" - 2769 646500 - 2770 .LASF73: - 2771 0150 55534246 .ascii "USBFS_HandleVendorRqst\000" - 2771 535F4861 - 2771 6E646C65 - 2771 56656E64 - 2771 6F725271 - 2772 .LASF43: - 2773 0167 55534246 .ascii "USBFS_ControlReadStatusStage\000" - 2773 535F436F - 2773 6E74726F - 2773 6C526561 - 2773 64537461 - 2774 .LASF8: - 2775 0184 756E7369 .ascii "unsigned int\000" - 2775 676E6564 - 2775 20696E74 - 2775 00 - 2776 .LASF39: - 2777 0191 55534246 .ascii "USBFS_UpdateStatusBlock\000" - 2777 535F5570 - 2777 64617465 - 2777 53746174 - 2777 7573426C - 2778 .LASF5: - 2779 01a9 6C6F6E67 .ascii "long unsigned int\000" - 2779 20756E73 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 67 - - - 2779 69676E65 - 2779 6420696E - 2779 7400 - 2780 .LASF33: - 2781 01bb 55534246 .ascii "USBFS_LoadEP0\000" - 2781 535F4C6F - 2781 61644550 - 2781 3000 - 2782 .LASF3: - 2783 01c9 73686F72 .ascii "short unsigned int\000" - 2783 7420756E - 2783 7369676E - 2783 65642069 - 2783 6E7400 - 2784 .LASF42: - 2785 01dc 55534246 .ascii "USBFS_HandleIN\000" - 2785 535F4861 - 2785 6E646C65 - 2785 494E00 - 2786 .LASF35: - 2787 01eb 65703043 .ascii "ep0Count\000" - 2787 6F756E74 - 2787 00 - 2788 .LASF70: - 2789 01f4 55534246 .ascii "USBFS_transferByteCount\000" - 2789 535F7472 - 2789 616E7366 - 2789 65724279 - 2789 7465436F - 2790 .LASF24: - 2791 020c 696E7465 .ascii "interface\000" - 2791 72666163 - 2791 6500 - 2792 .LASF56: - 2793 0216 55534246 .ascii "USBFS_configurationChanged\000" - 2793 535F636F - 2793 6E666967 - 2793 75726174 - 2793 696F6E43 - 2794 .LASF76: - 2795 0231 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 2795 43534932 - 2795 53445C73 - 2795 6F667477 - 2795 6172655C - 2796 0260 6E00 .ascii "n\000" - 2797 .LASF63: - 2798 0262 55534246 .ascii "USBFS_interfaceClass\000" - 2798 535F696E - 2798 74657266 - 2798 61636543 - 2798 6C617373 - 2799 .LASF18: - 2800 0277 68774570 .ascii "hwEpState\000" - 2800 53746174 - 2800 6500 - 2801 .LASF15: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 68 - - - 2802 0281 73697A65 .ascii "sizetype\000" - 2802 74797065 - 2802 00 - 2803 .LASF44: - 2804 028a 55534246 .ascii "USBFS_HandleOUT\000" - 2804 535F4861 - 2804 6E646C65 - 2804 4F555400 - 2805 .LASF68: - 2806 029a 55534246 .ascii "USBFS_ep0Mode\000" - 2806 535F6570 - 2806 304D6F64 - 2806 6500 - 2807 .LASF16: - 2808 02a8 61747472 .ascii "attrib\000" - 2808 696200 - 2809 .LASF69: - 2810 02af 55534246 .ascii "USBFS_ep0Count\000" - 2810 535F6570 - 2810 30436F75 - 2810 6E7400 - 2811 .LASF28: - 2812 02be 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" - 2812 4246535F - 2812 58464552 - 2812 5F535441 - 2812 5455535F - 2813 .LASF51: - 2814 02d8 55534246 .ascii "USBFS_InitControlWrite\000" - 2814 535F496E - 2814 6974436F - 2814 6E74726F - 2814 6C577269 - 2815 .LASF11: - 2816 02ef 666C6F61 .ascii "float\000" - 2816 7400 - 2817 .LASF17: - 2818 02f5 61706945 .ascii "apiEpState\000" - 2818 70537461 - 2818 746500 - 2819 .LASF64: - 2820 0300 55534246 .ascii "USBFS_EP\000" - 2820 535F4550 - 2820 00 - 2821 .LASF74: - 2822 0309 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 2822 4320342E - 2822 372E3320 - 2822 32303133 - 2822 30333132 - 2823 033c 616E6368 .ascii "anch revision 196615]\000" - 2823 20726576 - 2823 6973696F - 2823 6E203139 - 2823 36363135 - 2824 .LASF14: - 2825 0352 72656738 .ascii "reg8\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 69 - - - 2825 00 - 2826 .LASF54: - 2827 0357 55534246 .ascii "USBFS_transferState\000" - 2827 535F7472 - 2827 616E7366 - 2827 65725374 - 2827 61746500 - 2828 .LASF1: - 2829 036b 756E7369 .ascii "unsigned char\000" - 2829 676E6564 - 2829 20636861 - 2829 7200 - 2830 .LASF79: - 2831 0379 55534246 .ascii "USBFS_InitializeStatusBlock\000" - 2831 535F496E - 2831 69746961 - 2831 6C697A65 - 2831 53746174 - 2832 .LASF2: - 2833 0395 73686F72 .ascii "short int\000" - 2833 7420696E - 2833 7400 - 2834 .LASF32: - 2835 039f 545F5553 .ascii "T_USBFS_TD\000" - 2835 4246535F - 2835 544400 - 2836 .LASF67: - 2837 03aa 55534246 .ascii "USBFS_lastPacketSize\000" - 2837 535F6C61 - 2837 73745061 - 2837 636B6574 - 2837 53697A65 - 2838 .LASF59: - 2839 03bf 55534246 .ascii "USBFS_interfaceSetting\000" - 2839 535F696E - 2839 74657266 - 2839 61636553 - 2839 65747469 - 2840 .LASF25: - 2841 03d6 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 2841 4246535F - 2841 45505F43 - 2841 544C5F42 - 2841 4C4F434B - 2842 .LASF40: - 2843 03eb 55534246 .ascii "USBFS_NoDataControlStatusStage\000" - 2843 535F4E6F - 2843 44617461 - 2843 436F6E74 - 2843 726F6C53 - 2844 .LASF38: - 2845 040a 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" - 2845 535F496E - 2845 69744E6F - 2845 44617461 - 2845 436F6E74 - 2846 .LASF53: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 70 - - - 2847 042a 55534246 .ascii "USBFS_device\000" - 2847 535F6465 - 2847 76696365 - 2847 00 - 2848 .LASF66: - 2849 0437 55534246 .ascii "USBFS_ep0Toggle\000" - 2849 535F6570 - 2849 30546F67 - 2849 676C6500 - 2850 .LASF34: - 2851 0447 55534246 .ascii "USBFS_ControlWriteDataStage\000" - 2851 535F436F - 2851 6E74726F - 2851 6C577269 - 2851 74654461 - 2852 .LASF27: - 2853 0463 6C656E67 .ascii "length\000" - 2853 746800 - 2854 .LASF13: - 2855 046a 63686172 .ascii "char\000" - 2855 00 - 2856 .LASF23: - 2857 046f 62756666 .ascii "bufferSize\000" - 2857 65725369 - 2857 7A6500 - 2858 .LASF46: - 2859 047a 72657175 .ascii "requestHandled\000" - 2859 65737448 - 2859 616E646C - 2859 656400 - 2860 .LASF22: - 2861 0489 62756666 .ascii "buffOffset\000" - 2861 4F666673 - 2861 657400 - 2862 .LASF57: - 2863 0494 55534246 .ascii "USBFS_deviceStatus\000" - 2863 535F6465 - 2863 76696365 - 2863 53746174 - 2863 757300 - 2864 .LASF60: - 2865 04a7 55534246 .ascii "USBFS_interfaceSetting_last\000" - 2865 535F696E - 2865 74657266 - 2865 61636553 - 2865 65747469 - 2866 .LASF49: - 2867 04c3 6D6F6469 .ascii "modifyReg\000" - 2867 66795265 - 2867 6700 - 2868 .LASF45: - 2869 04cd 55534246 .ascii "USBFS_HandleSetup\000" - 2869 535F4861 - 2869 6E646C65 - 2869 53657475 - 2869 7000 - 2870 .LASF26: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccyD9XKy.s page 71 - - - 2871 04df 73746174 .ascii "status\000" - 2871 757300 - 2872 .LASF72: - 2873 04e6 55534246 .ascii "USBFS_DispatchClassRqst\000" - 2873 535F4469 - 2873 73706174 - 2873 6368436C - 2873 61737352 - 2874 .LASF50: - 2875 04fe 78666572 .ascii "xferCount\000" - 2875 436F756E - 2875 7400 - 2876 .LASF62: - 2877 0508 55534246 .ascii "USBFS_interfaceStatus\000" - 2877 535F696E - 2877 74657266 - 2877 61636553 - 2877 74617475 - 2878 .LASF71: - 2879 051e 55534246 .ascii "USBFS_HandleStandardRqst\000" - 2879 535F4861 - 2879 6E646C65 - 2879 5374616E - 2879 64617264 - 2880 .LASF37: - 2881 0537 55534246 .ascii "USBFS_InitZeroLengthControlTransfer\000" - 2881 535F496E - 2881 69745A65 - 2881 726F4C65 - 2881 6E677468 - 2882 .LASF41: - 2883 055b 55534246 .ascii "USBFS_ControlWriteStatusStage\000" - 2883 535F436F - 2883 6E74726F - 2883 6C577269 - 2883 74655374 - 2884 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_drv.o deleted file mode 100755 index 789579ad707e366aae935e1d8e1a614bc79a57b7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 15604 zcmc&*dvqMtdA~EWyIQSeJ#Dd;WqGtxK*pelZHxm(=wXA_G9WA&9OFb@Nvj9Q+GVve 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zN6-!hb|}|Nd+>ya`0`Uq#CI!xUmz|M#McjHqOuPVv5B7{dVY7I9sV?;DK%pLGJ66 zhXkhuZxXyy@J|JKzC!!I5#(=jDgS^NRO-iquZsS+M0CPiB8N=KVf2aMDZ~=|a#4`` zIAxwgkarUi52Kxe+}Fu>vE+Y9xmUg%?t7uz2v={h=;a&1^-<1pC^L< zsL1?&Yt|_BH9_wC%zs|wmx$ndm59Oe3&G<=*u5okiRIW;5iwb71WyxOBe+4ZOR!In zKYC?7L&R111&-i25%pXx@&O|3ZY9Q)`ncdhBJ3U#`4Pd#1)m|J+&73A?9T~4Pei$Y zl>C1c`Blk(TQCrC$}JI$62Z5M*o+^X37$p-U%TX=D{`mETSdNvh;lqHA|?c_a`Fi~aVrkd* za8ct{L2P+i#ulIvU83H^*9a7b61HxPhniPF&{>HoML=+QpULHC1M=(6R{8MB%=TK z5MxSB5Yhf=BI2AQu2E{9h`1Jr@R!LuZ^D%Ep`T-bs9Nu%dOpD~?I--w&xt^r`7qM+ z3fN2;e(L8NU>jxltLGa~#{s`LQ4j1Sf^4&3FA;HU6YM7{SXoU{xuQ){g4R%@Z%Nj7vHncAO5Eg>(}kNN!k^D=yrsRBHAC_Zjg1m!7trT zkbA|yJw(Vle)y^5g{YE~en}~Q`7Wq{o;!=zQ i`~iutPGp-1r#FhciHLsS|H09I8xe7jiabF?{Qm>{gn7FF diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst deleted file mode 100755 index bca12e6..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.lst +++ /dev/null @@ -1,1472 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "USBFS_episr.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.USBFS_EP_1_ISR,"ax",%progbits - 19 .align 1 - 20 .global USBFS_EP_1_ISR - 21 .thumb - 22 .thumb_func - 23 .type USBFS_EP_1_ISR, %function - 24 USBFS_EP_1_ISR: - 25 .LFB0: - 26 .file 1 ".\\Generated_Source\\PSoC5\\USBFS_episr.c" - 1:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/USBFS_episr.c **** * File Name: USBFS_episr.c - 3:.\Generated_Source\PSoC5/USBFS_episr.c **** * Version 2.60 - 4:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 5:.\Generated_Source\PSoC5/USBFS_episr.c **** * Description: - 6:.\Generated_Source\PSoC5/USBFS_episr.c **** * Data endpoint Interrupt Service Routines - 7:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 8:.\Generated_Source\PSoC5/USBFS_episr.c **** * Note: - 9:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 10:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/USBFS_episr.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/USBFS_episr.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/USBFS_episr.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/USBFS_episr.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/USBFS_episr.c **** - 17:.\Generated_Source\PSoC5/USBFS_episr.c **** #include "USBFS.h" - 18:.\Generated_Source\PSoC5/USBFS_episr.c **** #include "USBFS_pvt.h" - 19:.\Generated_Source\PSoC5/USBFS_episr.c **** #if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) - 20:.\Generated_Source\PSoC5/USBFS_episr.c **** #include "USBFS_midi.h" - 21:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - 22:.\Generated_Source\PSoC5/USBFS_episr.c **** - 23:.\Generated_Source\PSoC5/USBFS_episr.c **** - 24:.\Generated_Source\PSoC5/USBFS_episr.c **** /*************************************** - 25:.\Generated_Source\PSoC5/USBFS_episr.c **** * Custom Declarations - 26:.\Generated_Source\PSoC5/USBFS_episr.c **** ***************************************/ - 27:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START CUSTOM_DECLARATIONS` Place your declaration here */ - 28:.\Generated_Source\PSoC5/USBFS_episr.c **** - 29:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 30:.\Generated_Source\PSoC5/USBFS_episr.c **** - 31:.\Generated_Source\PSoC5/USBFS_episr.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 2 - - - 32:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP1_ISR_REMOVE == 0u) - 33:.\Generated_Source\PSoC5/USBFS_episr.c **** - 34:.\Generated_Source\PSoC5/USBFS_episr.c **** - 35:.\Generated_Source\PSoC5/USBFS_episr.c **** /****************************************************************************** - 36:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_1_ISR - 37:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************* - 38:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 39:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 40:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 1 Interrupt Service Routine - 41:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 42:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 43:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 44:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 45:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 46:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 47:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 48:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************/ - 49:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_1_ISR) - 50:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 27 .loc 1 50 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 51:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 52:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 53:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - 54:.\Generated_Source\PSoC5/USBFS_episr.c **** - 55:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP1_USER_CODE` Place your code here */ - 56:.\Generated_Source\PSoC5/USBFS_episr.c **** - 57:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 58:.\Generated_Source\PSoC5/USBFS_episr.c **** - 59:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 60:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 61:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 62:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - 63:.\Generated_Source\PSoC5/USBFS_episr.c **** - 64:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */ - 32 .loc 1 64 0 - 33 0000 094B ldr r3, .L7 - 65:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 66:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) != - 34 .loc 1 66 0 - 35 0002 0A48 ldr r0, .L7+4 - 64:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */ - 36 .loc 1 64 0 - 37 0004 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 38 .loc 1 66 0 - 39 0006 027B ldrb r2, [r0, #12] @ zero_extendqisi2 - 40 0008 02F00301 and r1, r2, #3 - 41 000c 0129 cmp r1, #1 - 42 000e 03D0 beq .L2 - 67:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 68:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 69:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 43 .loc 1 69 0 - 44 0010 C37B ldrb r3, [r0, #15] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 3 - - - 45 0012 83F08002 eor r2, r3, #128 - 46 0016 C273 strb r2, [r0, #15] - 47 .L2: - 70:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 71:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; - 48 .loc 1 71 0 - 49 0018 0121 movs r1, #1 - 50 001a 4173 strb r1, [r0, #13] - 72:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) & - 51 .loc 1 72 0 - 52 001c 0448 ldr r0, .L7+8 - 53 001e 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 54 0020 03F0FE02 and r2, r3, #254 - 55 0024 0270 strb r2, [r0, #0] - 56 0026 7047 bx lr - 57 .L8: - 58 .align 2 - 59 .L7: - 60 0028 0E600040 .word 1073766414 - 61 002c 00000000 .word USBFS_EP - 62 0030 0B600040 .word 1073766411 - 63 .cfi_endproc - 64 .LFE0: - 65 .size USBFS_EP_1_ISR, .-USBFS_EP_1_ISR - 66 .section .text.USBFS_EP_2_ISR,"ax",%progbits - 67 .align 1 - 68 .global USBFS_EP_2_ISR - 69 .thumb - 70 .thumb_func - 71 .type USBFS_EP_2_ISR, %function - 72 USBFS_EP_2_ISR: - 73 .LFB1: - 73:.\Generated_Source\PSoC5/USBFS_episr.c **** (uint8)~USBFS_SIE_EP_INT_EP1_MA - 74:.\Generated_Source\PSoC5/USBFS_episr.c **** - 75:.\Generated_Source\PSoC5/USBFS_episr.c **** #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) - 76:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP1) - 77:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 78:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 79:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 80:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 81:.\Generated_Source\PSoC5/USBFS_episr.c **** - 82:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP1_END_USER_CODE` Place your code here */ - 83:.\Generated_Source\PSoC5/USBFS_episr.c **** - 84:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 85:.\Generated_Source\PSoC5/USBFS_episr.c **** - 86:.\Generated_Source\PSoC5/USBFS_episr.c **** #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) - 87:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - 88:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - 89:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 90:.\Generated_Source\PSoC5/USBFS_episr.c **** - 91:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP1_ISR_REMOVE */ - 92:.\Generated_Source\PSoC5/USBFS_episr.c **** - 93:.\Generated_Source\PSoC5/USBFS_episr.c **** - 94:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP2_ISR_REMOVE == 0u) - 95:.\Generated_Source\PSoC5/USBFS_episr.c **** - 96:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 97:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_2_ISR - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 4 - - - 98:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 99:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 100:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 101:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 2 Interrupt Service Routine - 102:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 103:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 104:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 105:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 106:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 107:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 108:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 109:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 110:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_2_ISR) - 111:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 74 .loc 1 111 0 - 75 .cfi_startproc - 76 @ args = 0, pretend = 0, frame = 0 - 77 @ frame_needed = 0, uses_anonymous_args = 0 - 78 @ link register save eliminated. - 112:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 113:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 114:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - 115:.\Generated_Source\PSoC5/USBFS_episr.c **** - 116:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP2_USER_CODE` Place your code here */ - 117:.\Generated_Source\PSoC5/USBFS_episr.c **** - 118:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 119:.\Generated_Source\PSoC5/USBFS_episr.c **** - 120:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) - 121:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 122:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 123:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - 124:.\Generated_Source\PSoC5/USBFS_episr.c **** - 125:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */ - 79 .loc 1 125 0 - 80 0000 094B ldr r3, .L14 - 126:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 127:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) != - 81 .loc 1 127 0 - 82 0002 0A48 ldr r0, .L14+4 - 125:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */ - 83 .loc 1 125 0 - 84 0004 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 85 .loc 1 127 0 - 86 0006 027E ldrb r2, [r0, #24] @ zero_extendqisi2 - 87 0008 02F00301 and r1, r2, #3 - 88 000c 0129 cmp r1, #1 - 89 000e 03D0 beq .L10 - 128:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 129:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 130:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 90 .loc 1 130 0 - 91 0010 C37E ldrb r3, [r0, #27] @ zero_extendqisi2 - 92 0012 83F08002 eor r2, r3, #128 - 93 0016 C276 strb r2, [r0, #27] - 94 .L10: - 131:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 132:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 5 - - - 95 .loc 1 132 0 - 96 0018 0121 movs r1, #1 - 97 001a 4176 strb r1, [r0, #25] - 133:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - 98 .loc 1 133 0 - 99 001c 0448 ldr r0, .L14+8 - 100 001e 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 101 0020 03F0FD02 and r2, r3, #253 - 102 0024 0270 strb r2, [r0, #0] - 103 0026 7047 bx lr - 104 .L15: - 105 .align 2 - 106 .L14: - 107 0028 1E600040 .word 1073766430 - 108 002c 00000000 .word USBFS_EP - 109 0030 0B600040 .word 1073766411 - 110 .cfi_endproc - 111 .LFE1: - 112 .size USBFS_EP_2_ISR, .-USBFS_EP_2_ISR - 113 .section .text.USBFS_SOF_ISR,"ax",%progbits - 114 .align 1 - 115 .global USBFS_SOF_ISR - 116 .thumb - 117 .thumb_func - 118 .type USBFS_SOF_ISR, %function - 119 USBFS_SOF_ISR: - 120 .LFB2: - 134:.\Generated_Source\PSoC5/USBFS_episr.c **** & (uint8)~USBFS_SIE_EP_INT_ - 135:.\Generated_Source\PSoC5/USBFS_episr.c **** - 136:.\Generated_Source\PSoC5/USBFS_episr.c **** #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) - 137:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP2) - 138:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 139:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 140:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 141:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 142:.\Generated_Source\PSoC5/USBFS_episr.c **** - 143:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP2_END_USER_CODE` Place your code here */ - 144:.\Generated_Source\PSoC5/USBFS_episr.c **** - 145:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 146:.\Generated_Source\PSoC5/USBFS_episr.c **** - 147:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 148:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - 149:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - 150:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 151:.\Generated_Source\PSoC5/USBFS_episr.c **** - 152:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP2_ISR_REMOVE */ - 153:.\Generated_Source\PSoC5/USBFS_episr.c **** - 154:.\Generated_Source\PSoC5/USBFS_episr.c **** - 155:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP3_ISR_REMOVE == 0u) - 156:.\Generated_Source\PSoC5/USBFS_episr.c **** - 157:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 158:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_3_ISR - 159:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 160:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 161:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 162:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 3 Interrupt Service Routine - 163:.\Generated_Source\PSoC5/USBFS_episr.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 6 - - - 164:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 165:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 166:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 167:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 168:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 169:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 170:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 171:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_3_ISR) - 172:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 173:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 174:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 175:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - 176:.\Generated_Source\PSoC5/USBFS_episr.c **** - 177:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP3_USER_CODE` Place your code here */ - 178:.\Generated_Source\PSoC5/USBFS_episr.c **** - 179:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 180:.\Generated_Source\PSoC5/USBFS_episr.c **** - 181:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 182:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 183:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 184:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 185:.\Generated_Source\PSoC5/USBFS_episr.c **** - 186:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */ - 187:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 188:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) != - 189:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 190:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 191:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 192:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 193:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; - 194:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - 195:.\Generated_Source\PSoC5/USBFS_episr.c **** & (uint8)~USBFS_SIE_EP_INT_ - 196:.\Generated_Source\PSoC5/USBFS_episr.c **** - 197:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - 198:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP3) - 199:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 200:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 201:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 202:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 203:.\Generated_Source\PSoC5/USBFS_episr.c **** - 204:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP3_END_USER_CODE` Place your code here */ - 205:.\Generated_Source\PSoC5/USBFS_episr.c **** - 206:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 207:.\Generated_Source\PSoC5/USBFS_episr.c **** - 208:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 209:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - 210:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 211:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 212:.\Generated_Source\PSoC5/USBFS_episr.c **** - 213:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP3_ISR_REMOVE */ - 214:.\Generated_Source\PSoC5/USBFS_episr.c **** - 215:.\Generated_Source\PSoC5/USBFS_episr.c **** - 216:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP4_ISR_REMOVE == 0u) - 217:.\Generated_Source\PSoC5/USBFS_episr.c **** - 218:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 219:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_4_ISR - 220:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 7 - - - 221:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 222:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 223:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 4 Interrupt Service Routine - 224:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 225:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 226:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 227:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 228:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 229:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 230:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 231:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 232:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_4_ISR) - 233:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 234:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 235:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 236:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 237:.\Generated_Source\PSoC5/USBFS_episr.c **** - 238:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP4_USER_CODE` Place your code here */ - 239:.\Generated_Source\PSoC5/USBFS_episr.c **** - 240:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 241:.\Generated_Source\PSoC5/USBFS_episr.c **** - 242:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 243:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 244:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 245:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 246:.\Generated_Source\PSoC5/USBFS_episr.c **** - 247:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */ - 248:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 249:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) != - 250:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 251:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 252:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 253:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 254:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; - 255:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - 256:.\Generated_Source\PSoC5/USBFS_episr.c **** & (uint8)~USBFS_SIE_EP_INT_ - 257:.\Generated_Source\PSoC5/USBFS_episr.c **** - 258:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - 259:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP4) - 260:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 261:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 262:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 263:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 264:.\Generated_Source\PSoC5/USBFS_episr.c **** - 265:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP4_END_USER_CODE` Place your code here */ - 266:.\Generated_Source\PSoC5/USBFS_episr.c **** - 267:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 268:.\Generated_Source\PSoC5/USBFS_episr.c **** - 269:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 270:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - 271:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 272:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 273:.\Generated_Source\PSoC5/USBFS_episr.c **** - 274:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP4_ISR_REMOVE */ - 275:.\Generated_Source\PSoC5/USBFS_episr.c **** - 276:.\Generated_Source\PSoC5/USBFS_episr.c **** - 277:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP5_ISR_REMOVE == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 8 - - - 278:.\Generated_Source\PSoC5/USBFS_episr.c **** - 279:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 280:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_5_ISR - 281:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 282:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 283:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 284:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 5 Interrupt Service Routine - 285:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 286:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 287:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 288:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 289:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 290:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 291:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 292:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 293:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_5_ISR) - 294:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 295:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 296:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 297:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 298:.\Generated_Source\PSoC5/USBFS_episr.c **** - 299:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP5_USER_CODE` Place your code here */ - 300:.\Generated_Source\PSoC5/USBFS_episr.c **** - 301:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 302:.\Generated_Source\PSoC5/USBFS_episr.c **** - 303:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 304:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 305:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 306:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 307:.\Generated_Source\PSoC5/USBFS_episr.c **** - 308:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */ - 309:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 310:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) != - 311:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 312:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 313:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 314:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 315:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; - 316:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - 317:.\Generated_Source\PSoC5/USBFS_episr.c **** & (uint8)~USBFS_SIE_EP_INT_ - 318:.\Generated_Source\PSoC5/USBFS_episr.c **** - 319:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - 320:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP5) - 321:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 322:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 323:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 324:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 325:.\Generated_Source\PSoC5/USBFS_episr.c **** - 326:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP5_END_USER_CODE` Place your code here */ - 327:.\Generated_Source\PSoC5/USBFS_episr.c **** - 328:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 329:.\Generated_Source\PSoC5/USBFS_episr.c **** - 330:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 331:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - 332:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 333:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 334:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP5_ISR_REMOVE */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 9 - - - 335:.\Generated_Source\PSoC5/USBFS_episr.c **** - 336:.\Generated_Source\PSoC5/USBFS_episr.c **** - 337:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP6_ISR_REMOVE == 0u) - 338:.\Generated_Source\PSoC5/USBFS_episr.c **** - 339:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 340:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_6_ISR - 341:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 342:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 343:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 344:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 6 Interrupt Service Routine - 345:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 346:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 347:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 348:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 349:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 350:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 351:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 352:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 353:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_6_ISR) - 354:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 355:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 356:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 357:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 358:.\Generated_Source\PSoC5/USBFS_episr.c **** - 359:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP6_USER_CODE` Place your code here */ - 360:.\Generated_Source\PSoC5/USBFS_episr.c **** - 361:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 362:.\Generated_Source\PSoC5/USBFS_episr.c **** - 363:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 364:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 365:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 366:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 367:.\Generated_Source\PSoC5/USBFS_episr.c **** - 368:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */ - 369:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 370:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) != - 371:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 372:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 373:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 374:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 375:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; - 376:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - 377:.\Generated_Source\PSoC5/USBFS_episr.c **** & (uint8)~USBFS_SIE_EP_INT_ - 378:.\Generated_Source\PSoC5/USBFS_episr.c **** - 379:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - 380:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP6) - 381:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 382:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 383:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 384:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 385:.\Generated_Source\PSoC5/USBFS_episr.c **** - 386:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP6_END_USER_CODE` Place your code here */ - 387:.\Generated_Source\PSoC5/USBFS_episr.c **** - 388:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 389:.\Generated_Source\PSoC5/USBFS_episr.c **** - 390:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 391:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 10 - - - 392:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 393:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 394:.\Generated_Source\PSoC5/USBFS_episr.c **** - 395:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP6_ISR_REMOVE */ - 396:.\Generated_Source\PSoC5/USBFS_episr.c **** - 397:.\Generated_Source\PSoC5/USBFS_episr.c **** - 398:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP7_ISR_REMOVE == 0u) - 399:.\Generated_Source\PSoC5/USBFS_episr.c **** - 400:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 401:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_7_ISR - 402:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 403:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 404:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 405:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 7 Interrupt Service Routine - 406:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 407:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 408:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 409:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 410:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 411:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 412:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 413:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 414:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_7_ISR) - 415:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 416:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 417:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 418:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 419:.\Generated_Source\PSoC5/USBFS_episr.c **** - 420:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP7_USER_CODE` Place your code here */ - 421:.\Generated_Source\PSoC5/USBFS_episr.c **** - 422:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 423:.\Generated_Source\PSoC5/USBFS_episr.c **** - 424:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 425:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 426:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 427:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 428:.\Generated_Source\PSoC5/USBFS_episr.c **** - 429:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */ - 430:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 431:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) != - 432:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 433:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 434:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 435:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 436:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; - 437:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - 438:.\Generated_Source\PSoC5/USBFS_episr.c **** & (uint8)~USBFS_SIE_EP_INT_ - 439:.\Generated_Source\PSoC5/USBFS_episr.c **** - 440:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - 441:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP7) - 442:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 443:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 444:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 445:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 446:.\Generated_Source\PSoC5/USBFS_episr.c **** - 447:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP7_END_USER_CODE` Place your code here */ - 448:.\Generated_Source\PSoC5/USBFS_episr.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 11 - - - 449:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 450:.\Generated_Source\PSoC5/USBFS_episr.c **** - 451:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 452:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - 453:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 454:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 455:.\Generated_Source\PSoC5/USBFS_episr.c **** - 456:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP7_ISR_REMOVE */ - 457:.\Generated_Source\PSoC5/USBFS_episr.c **** - 458:.\Generated_Source\PSoC5/USBFS_episr.c **** - 459:.\Generated_Source\PSoC5/USBFS_episr.c **** #if(USBFS_EP8_ISR_REMOVE == 0u) - 460:.\Generated_Source\PSoC5/USBFS_episr.c **** - 461:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 462:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_EP_8_ISR - 463:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 464:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 465:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 466:.\Generated_Source\PSoC5/USBFS_episr.c **** * Endpoint 8 Interrupt Service Routine - 467:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 468:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 469:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 470:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 471:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 472:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 473:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 474:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 475:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_EP_8_ISR) - 476:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 477:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 478:.\Generated_Source\PSoC5/USBFS_episr.c **** uint8 int_en; - 479:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 480:.\Generated_Source\PSoC5/USBFS_episr.c **** - 481:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP8_USER_CODE` Place your code here */ - 482:.\Generated_Source\PSoC5/USBFS_episr.c **** - 483:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 484:.\Generated_Source\PSoC5/USBFS_episr.c **** - 485:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 486:.\Generated_Source\PSoC5/USBFS_episr.c **** int_en = EA; - 487:.\Generated_Source\PSoC5/USBFS_episr.c **** CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - 488:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 489:.\Generated_Source\PSoC5/USBFS_episr.c **** - 490:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */ - 491:.\Generated_Source\PSoC5/USBFS_episr.c **** /* Do not toggle ISOC endpoint */ - 492:.\Generated_Source\PSoC5/USBFS_episr.c **** if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) != - 493:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP_TYPE_I - 494:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 495:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - 496:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 497:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; - 498:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - 499:.\Generated_Source\PSoC5/USBFS_episr.c **** & (uint8)~USBFS_SIE_EP_INT_ - 500:.\Generated_Source\PSoC5/USBFS_episr.c **** - 501:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - 502:.\Generated_Source\PSoC5/USBFS_episr.c **** if(USBFS_midi_out_ep == USBFS_EP8) - 503:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 504:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_MIDI_OUT_EP_Service(); - 505:.\Generated_Source\PSoC5/USBFS_episr.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 12 - - - 506:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - 507:.\Generated_Source\PSoC5/USBFS_episr.c **** - 508:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START EP8_END_USER_CODE` Place your code here */ - 509:.\Generated_Source\PSoC5/USBFS_episr.c **** - 510:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 511:.\Generated_Source\PSoC5/USBFS_episr.c **** - 512:.\Generated_Source\PSoC5/USBFS_episr.c **** #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - 513:.\Generated_Source\PSoC5/USBFS_episr.c **** EA = int_en; - 514:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - 515:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 516:.\Generated_Source\PSoC5/USBFS_episr.c **** - 517:.\Generated_Source\PSoC5/USBFS_episr.c **** #endif /* End USBFS_EP8_ISR_REMOVE */ - 518:.\Generated_Source\PSoC5/USBFS_episr.c **** - 519:.\Generated_Source\PSoC5/USBFS_episr.c **** - 520:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 521:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_SOF_ISR - 522:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 523:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 524:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 525:.\Generated_Source\PSoC5/USBFS_episr.c **** * Start of Frame Interrupt Service Routine - 526:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 527:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 528:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 529:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 530:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 531:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 532:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 533:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 534:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_SOF_ISR) - 535:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 121 .loc 1 535 0 - 122 .cfi_startproc - 123 @ args = 0, pretend = 0, frame = 0 - 124 @ frame_needed = 0, uses_anonymous_args = 0 - 125 @ link register save eliminated. - 126 0000 7047 bx lr - 127 .cfi_endproc - 128 .LFE2: - 129 .size USBFS_SOF_ISR, .-USBFS_SOF_ISR - 130 .section .text.USBFS_BUS_RESET_ISR,"ax",%progbits - 131 .align 1 - 132 .global USBFS_BUS_RESET_ISR - 133 .thumb - 134 .thumb_func - 135 .type USBFS_BUS_RESET_ISR, %function - 136 USBFS_BUS_RESET_ISR: - 137 .LFB3: - 536:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START SOF_USER_CODE` Place your code here */ - 537:.\Generated_Source\PSoC5/USBFS_episr.c **** - 538:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 539:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 540:.\Generated_Source\PSoC5/USBFS_episr.c **** - 541:.\Generated_Source\PSoC5/USBFS_episr.c **** - 542:.\Generated_Source\PSoC5/USBFS_episr.c **** /******************************************************************************* - 543:.\Generated_Source\PSoC5/USBFS_episr.c **** * Function Name: USBFS_BUS_RESET_ISR - 544:.\Generated_Source\PSoC5/USBFS_episr.c **** ******************************************************************************** - 545:.\Generated_Source\PSoC5/USBFS_episr.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 13 - - - 546:.\Generated_Source\PSoC5/USBFS_episr.c **** * Summary: - 547:.\Generated_Source\PSoC5/USBFS_episr.c **** * USB Bus Reset Interrupt Service Routine. Calls _Start with the same - 548:.\Generated_Source\PSoC5/USBFS_episr.c **** * parameters as the last USER call to _Start - 549:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 550:.\Generated_Source\PSoC5/USBFS_episr.c **** * Parameters: - 551:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 552:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 553:.\Generated_Source\PSoC5/USBFS_episr.c **** * Return: - 554:.\Generated_Source\PSoC5/USBFS_episr.c **** * None. - 555:.\Generated_Source\PSoC5/USBFS_episr.c **** * - 556:.\Generated_Source\PSoC5/USBFS_episr.c **** *******************************************************************************/ - 557:.\Generated_Source\PSoC5/USBFS_episr.c **** CY_ISR(USBFS_BUS_RESET_ISR) - 558:.\Generated_Source\PSoC5/USBFS_episr.c **** { - 138 .loc 1 558 0 - 139 .cfi_startproc - 140 @ args = 0, pretend = 0, frame = 0 - 141 @ frame_needed = 0, uses_anonymous_args = 0 - 142 @ link register save eliminated. - 559:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#START BUS_RESET_USER_CODE` Place your code here */ - 560:.\Generated_Source\PSoC5/USBFS_episr.c **** - 561:.\Generated_Source\PSoC5/USBFS_episr.c **** /* `#END` */ - 562:.\Generated_Source\PSoC5/USBFS_episr.c **** - 563:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_ReInitComponent(); - 564:.\Generated_Source\PSoC5/USBFS_episr.c **** } - 143 .loc 1 564 0 - 563:.\Generated_Source\PSoC5/USBFS_episr.c **** USBFS_ReInitComponent(); - 144 .loc 1 563 0 - 145 0000 FFF7FEBF b USBFS_ReInitComponent - 146 .LVL0: - 147 .cfi_endproc - 148 .LFE3: - 149 .size USBFS_BUS_RESET_ISR, .-USBFS_BUS_RESET_ISR - 150 .text - 151 .Letext0: - 152 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 153 .file 3 ".\\Generated_Source\\PSoC5\\USBFS.h" - 154 .file 4 ".\\Generated_Source\\PSoC5\\USBFS_pvt.h" - 155 .section .debug_info,"",%progbits - 156 .Ldebug_info0: - 157 0000 D1010000 .4byte 0x1d1 - 158 0004 0200 .2byte 0x2 - 159 0006 00000000 .4byte .Ldebug_abbrev0 - 160 000a 04 .byte 0x4 - 161 000b 01 .uleb128 0x1 - 162 000c A0010000 .4byte .LASF29 - 163 0010 01 .byte 0x1 - 164 0011 6F000000 .4byte .LASF30 - 165 0015 AD000000 .4byte .LASF31 - 166 0019 00000000 .4byte .Ldebug_ranges0+0 - 167 001d 00000000 .4byte 0 - 168 0021 00000000 .4byte 0 - 169 0025 00000000 .4byte .Ldebug_line0 - 170 0029 02 .uleb128 0x2 - 171 002a 01 .byte 0x1 - 172 002b 06 .byte 0x6 - 173 002c 0B020000 .4byte .LASF0 - 174 0030 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 14 - - - 175 0031 01 .byte 0x1 - 176 0032 08 .byte 0x8 - 177 0033 61000000 .4byte .LASF1 - 178 0037 02 .uleb128 0x2 - 179 0038 02 .byte 0x2 - 180 0039 05 .byte 0x5 - 181 003a 90010000 .4byte .LASF2 - 182 003e 02 .uleb128 0x2 - 183 003f 02 .byte 0x2 - 184 0040 07 .byte 0x7 - 185 0041 16000000 .4byte .LASF3 - 186 0045 02 .uleb128 0x2 - 187 0046 04 .byte 0x4 - 188 0047 05 .byte 0x5 - 189 0048 F3010000 .4byte .LASF4 - 190 004c 02 .uleb128 0x2 - 191 004d 04 .byte 0x4 - 192 004e 07 .byte 0x7 - 193 004f 9B000000 .4byte .LASF5 - 194 0053 02 .uleb128 0x2 - 195 0054 08 .byte 0x8 - 196 0055 05 .byte 0x5 - 197 0056 72010000 .4byte .LASF6 - 198 005a 02 .uleb128 0x2 - 199 005b 08 .byte 0x8 - 200 005c 07 .byte 0x7 - 201 005d 32010000 .4byte .LASF7 - 202 0061 03 .uleb128 0x3 - 203 0062 04 .byte 0x4 - 204 0063 05 .byte 0x5 - 205 0064 696E7400 .ascii "int\000" - 206 0068 02 .uleb128 0x2 - 207 0069 04 .byte 0x4 - 208 006a 07 .byte 0x7 - 209 006b 25010000 .4byte .LASF8 - 210 006f 04 .uleb128 0x4 - 211 0070 9A010000 .4byte .LASF9 - 212 0074 02 .byte 0x2 - 213 0075 5B .byte 0x5b - 214 0076 30000000 .4byte 0x30 - 215 007a 04 .uleb128 0x4 - 216 007b 13010000 .4byte .LASF10 - 217 007f 02 .byte 0x2 - 218 0080 5C .byte 0x5c - 219 0081 3E000000 .4byte 0x3e - 220 0085 02 .uleb128 0x2 - 221 0086 04 .byte 0x4 - 222 0087 04 .byte 0x4 - 223 0088 52000000 .4byte .LASF11 - 224 008c 02 .uleb128 0x2 - 225 008d 08 .byte 0x8 - 226 008e 04 .byte 0x4 - 227 008f FA000000 .4byte .LASF12 - 228 0093 02 .uleb128 0x2 - 229 0094 01 .byte 0x1 - 230 0095 08 .byte 0x8 - 231 0096 80010000 .4byte .LASF13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 15 - - - 232 009a 04 .uleb128 0x4 - 233 009b 96000000 .4byte .LASF14 - 234 009f 02 .byte 0x2 - 235 00a0 F0 .byte 0xf0 - 236 00a1 A5000000 .4byte 0xa5 - 237 00a5 05 .uleb128 0x5 - 238 00a6 6F000000 .4byte 0x6f - 239 00aa 02 .uleb128 0x2 - 240 00ab 04 .byte 0x4 - 241 00ac 07 .byte 0x7 - 242 00ad 62010000 .4byte .LASF15 - 243 00b1 06 .uleb128 0x6 - 244 00b2 0C .byte 0xc - 245 00b3 03 .byte 0x3 - 246 00b4 79 .byte 0x79 - 247 00b5 38010000 .4byte 0x138 - 248 00b9 07 .uleb128 0x7 - 249 00ba 01010000 .4byte .LASF16 - 250 00be 03 .byte 0x3 - 251 00bf 7B .byte 0x7b - 252 00c0 6F000000 .4byte 0x6f - 253 00c4 02 .byte 0x2 - 254 00c5 23 .byte 0x23 - 255 00c6 00 .uleb128 0 - 256 00c7 07 .uleb128 0x7 - 257 00c8 1A010000 .4byte .LASF17 - 258 00cc 03 .byte 0x3 - 259 00cd 7C .byte 0x7c - 260 00ce 6F000000 .4byte 0x6f - 261 00d2 02 .byte 0x2 - 262 00d3 23 .byte 0x23 - 263 00d4 01 .uleb128 0x1 - 264 00d5 07 .uleb128 0x7 - 265 00d6 49010000 .4byte .LASF18 - 266 00da 03 .byte 0x3 - 267 00db 7D .byte 0x7d - 268 00dc 6F000000 .4byte 0x6f - 269 00e0 02 .byte 0x2 - 270 00e1 23 .byte 0x23 - 271 00e2 02 .uleb128 0x2 - 272 00e3 07 .uleb128 0x7 - 273 00e4 58000000 .4byte .LASF19 - 274 00e8 03 .byte 0x3 - 275 00e9 7E .byte 0x7e - 276 00ea 6F000000 .4byte 0x6f - 277 00ee 02 .byte 0x2 - 278 00ef 23 .byte 0x23 - 279 00f0 03 .uleb128 0x3 - 280 00f1 07 .uleb128 0x7 - 281 00f2 DE000000 .4byte .LASF20 - 282 00f6 03 .byte 0x3 - 283 00f7 7F .byte 0x7f - 284 00f8 6F000000 .4byte 0x6f - 285 00fc 02 .byte 0x2 - 286 00fd 23 .byte 0x23 - 287 00fe 04 .uleb128 0x4 - 288 00ff 07 .uleb128 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 16 - - - 289 0100 6B010000 .4byte .LASF21 - 290 0104 03 .byte 0x3 - 291 0105 80 .byte 0x80 - 292 0106 6F000000 .4byte 0x6f - 293 010a 02 .byte 0x2 - 294 010b 23 .byte 0x23 - 295 010c 05 .uleb128 0x5 - 296 010d 07 .uleb128 0x7 - 297 010e 08010000 .4byte .LASF22 - 298 0112 03 .byte 0x3 - 299 0113 81 .byte 0x81 - 300 0114 7A000000 .4byte 0x7a - 301 0118 02 .byte 0x2 - 302 0119 23 .byte 0x23 - 303 011a 06 .uleb128 0x6 - 304 011b 07 .uleb128 0x7 - 305 011c 85010000 .4byte .LASF23 - 306 0120 03 .byte 0x3 - 307 0121 82 .byte 0x82 - 308 0122 7A000000 .4byte 0x7a - 309 0126 02 .byte 0x2 - 310 0127 23 .byte 0x23 - 311 0128 08 .uleb128 0x8 - 312 0129 07 .uleb128 0x7 - 313 012a E9010000 .4byte .LASF24 - 314 012e 03 .byte 0x3 - 315 012f 83 .byte 0x83 - 316 0130 6F000000 .4byte 0x6f - 317 0134 02 .byte 0x2 - 318 0135 23 .byte 0x23 - 319 0136 0A .uleb128 0xa - 320 0137 00 .byte 0 - 321 0138 04 .uleb128 0x4 - 322 0139 29000000 .4byte .LASF25 - 323 013d 03 .byte 0x3 - 324 013e 84 .byte 0x84 - 325 013f B1000000 .4byte 0xb1 - 326 0143 08 .uleb128 0x8 - 327 0144 01 .byte 0x1 - 328 0145 53010000 .4byte .LASF26 - 329 0149 01 .byte 0x1 - 330 014a 31 .byte 0x31 - 331 014b 01 .byte 0x1 - 332 014c 00000000 .4byte .LFB0 - 333 0150 34000000 .4byte .LFE0 - 334 0154 02 .byte 0x2 - 335 0155 7D .byte 0x7d - 336 0156 00 .sleb128 0 - 337 0157 01 .byte 0x1 - 338 0158 08 .uleb128 0x8 - 339 0159 01 .byte 0x1 - 340 015a FC010000 .4byte .LASF27 - 341 015e 01 .byte 0x1 - 342 015f 6E .byte 0x6e - 343 0160 01 .byte 0x1 - 344 0161 00000000 .4byte .LFB1 - 345 0165 34000000 .4byte .LFE1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 17 - - - 346 0169 02 .byte 0x2 - 347 016a 7D .byte 0x7d - 348 016b 00 .sleb128 0 - 349 016c 01 .byte 0x1 - 350 016d 09 .uleb128 0x9 - 351 016e 01 .byte 0x1 - 352 016f E3000000 .4byte .LASF28 - 353 0173 01 .byte 0x1 - 354 0174 1602 .2byte 0x216 - 355 0176 01 .byte 0x1 - 356 0177 00000000 .4byte .LFB2 - 357 017b 02000000 .4byte .LFE2 - 358 017f 02 .byte 0x2 - 359 0180 7D .byte 0x7d - 360 0181 00 .sleb128 0 - 361 0182 01 .byte 0x1 - 362 0183 0A .uleb128 0xa - 363 0184 01 .byte 0x1 - 364 0185 3E000000 .4byte .LASF32 - 365 0189 01 .byte 0x1 - 366 018a 2D02 .2byte 0x22d - 367 018c 01 .byte 0x1 - 368 018d 00000000 .4byte .LFB3 - 369 0191 04000000 .4byte .LFE3 - 370 0195 02 .byte 0x2 - 371 0196 7D .byte 0x7d - 372 0197 00 .sleb128 0 - 373 0198 01 .byte 0x1 - 374 0199 A8010000 .4byte 0x1a8 - 375 019d 0B .uleb128 0xb - 376 019e 04000000 .4byte .LVL0 - 377 01a2 01 .byte 0x1 - 378 01a3 CA010000 .4byte 0x1ca - 379 01a7 00 .byte 0 - 380 01a8 0C .uleb128 0xc - 381 01a9 38010000 .4byte 0x138 - 382 01ad B8010000 .4byte 0x1b8 - 383 01b1 0D .uleb128 0xd - 384 01b2 AA000000 .4byte 0xaa - 385 01b6 08 .byte 0x8 - 386 01b7 00 .byte 0 - 387 01b8 0E .uleb128 0xe - 388 01b9 F1000000 .4byte .LASF33 - 389 01bd 04 .byte 0x4 - 390 01be 3F .byte 0x3f - 391 01bf C5010000 .4byte 0x1c5 - 392 01c3 01 .byte 0x1 - 393 01c4 01 .byte 0x1 - 394 01c5 05 .uleb128 0x5 - 395 01c6 A8010000 .4byte 0x1a8 - 396 01ca 0F .uleb128 0xf - 397 01cb 01 .byte 0x1 - 398 01cc 00000000 .4byte .LASF34 - 399 01d0 04 .byte 0x4 - 400 01d1 51 .byte 0x51 - 401 01d2 01 .byte 0x1 - 402 01d3 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 18 - - - 403 01d4 00 .byte 0 - 404 .section .debug_abbrev,"",%progbits - 405 .Ldebug_abbrev0: - 406 0000 01 .uleb128 0x1 - 407 0001 11 .uleb128 0x11 - 408 0002 01 .byte 0x1 - 409 0003 25 .uleb128 0x25 - 410 0004 0E .uleb128 0xe - 411 0005 13 .uleb128 0x13 - 412 0006 0B .uleb128 0xb - 413 0007 03 .uleb128 0x3 - 414 0008 0E .uleb128 0xe - 415 0009 1B .uleb128 0x1b - 416 000a 0E .uleb128 0xe - 417 000b 55 .uleb128 0x55 - 418 000c 06 .uleb128 0x6 - 419 000d 11 .uleb128 0x11 - 420 000e 01 .uleb128 0x1 - 421 000f 52 .uleb128 0x52 - 422 0010 01 .uleb128 0x1 - 423 0011 10 .uleb128 0x10 - 424 0012 06 .uleb128 0x6 - 425 0013 00 .byte 0 - 426 0014 00 .byte 0 - 427 0015 02 .uleb128 0x2 - 428 0016 24 .uleb128 0x24 - 429 0017 00 .byte 0 - 430 0018 0B .uleb128 0xb - 431 0019 0B .uleb128 0xb - 432 001a 3E .uleb128 0x3e - 433 001b 0B .uleb128 0xb - 434 001c 03 .uleb128 0x3 - 435 001d 0E .uleb128 0xe - 436 001e 00 .byte 0 - 437 001f 00 .byte 0 - 438 0020 03 .uleb128 0x3 - 439 0021 24 .uleb128 0x24 - 440 0022 00 .byte 0 - 441 0023 0B .uleb128 0xb - 442 0024 0B .uleb128 0xb - 443 0025 3E .uleb128 0x3e - 444 0026 0B .uleb128 0xb - 445 0027 03 .uleb128 0x3 - 446 0028 08 .uleb128 0x8 - 447 0029 00 .byte 0 - 448 002a 00 .byte 0 - 449 002b 04 .uleb128 0x4 - 450 002c 16 .uleb128 0x16 - 451 002d 00 .byte 0 - 452 002e 03 .uleb128 0x3 - 453 002f 0E .uleb128 0xe - 454 0030 3A .uleb128 0x3a - 455 0031 0B .uleb128 0xb - 456 0032 3B .uleb128 0x3b - 457 0033 0B .uleb128 0xb - 458 0034 49 .uleb128 0x49 - 459 0035 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 19 - - - 460 0036 00 .byte 0 - 461 0037 00 .byte 0 - 462 0038 05 .uleb128 0x5 - 463 0039 35 .uleb128 0x35 - 464 003a 00 .byte 0 - 465 003b 49 .uleb128 0x49 - 466 003c 13 .uleb128 0x13 - 467 003d 00 .byte 0 - 468 003e 00 .byte 0 - 469 003f 06 .uleb128 0x6 - 470 0040 13 .uleb128 0x13 - 471 0041 01 .byte 0x1 - 472 0042 0B .uleb128 0xb - 473 0043 0B .uleb128 0xb - 474 0044 3A .uleb128 0x3a - 475 0045 0B .uleb128 0xb - 476 0046 3B .uleb128 0x3b - 477 0047 0B .uleb128 0xb - 478 0048 01 .uleb128 0x1 - 479 0049 13 .uleb128 0x13 - 480 004a 00 .byte 0 - 481 004b 00 .byte 0 - 482 004c 07 .uleb128 0x7 - 483 004d 0D .uleb128 0xd - 484 004e 00 .byte 0 - 485 004f 03 .uleb128 0x3 - 486 0050 0E .uleb128 0xe - 487 0051 3A .uleb128 0x3a - 488 0052 0B .uleb128 0xb - 489 0053 3B .uleb128 0x3b - 490 0054 0B .uleb128 0xb - 491 0055 49 .uleb128 0x49 - 492 0056 13 .uleb128 0x13 - 493 0057 38 .uleb128 0x38 - 494 0058 0A .uleb128 0xa - 495 0059 00 .byte 0 - 496 005a 00 .byte 0 - 497 005b 08 .uleb128 0x8 - 498 005c 2E .uleb128 0x2e - 499 005d 00 .byte 0 - 500 005e 3F .uleb128 0x3f - 501 005f 0C .uleb128 0xc - 502 0060 03 .uleb128 0x3 - 503 0061 0E .uleb128 0xe - 504 0062 3A .uleb128 0x3a - 505 0063 0B .uleb128 0xb - 506 0064 3B .uleb128 0x3b - 507 0065 0B .uleb128 0xb - 508 0066 27 .uleb128 0x27 - 509 0067 0C .uleb128 0xc - 510 0068 11 .uleb128 0x11 - 511 0069 01 .uleb128 0x1 - 512 006a 12 .uleb128 0x12 - 513 006b 01 .uleb128 0x1 - 514 006c 40 .uleb128 0x40 - 515 006d 0A .uleb128 0xa - 516 006e 9742 .uleb128 0x2117 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 20 - - - 517 0070 0C .uleb128 0xc - 518 0071 00 .byte 0 - 519 0072 00 .byte 0 - 520 0073 09 .uleb128 0x9 - 521 0074 2E .uleb128 0x2e - 522 0075 00 .byte 0 - 523 0076 3F .uleb128 0x3f - 524 0077 0C .uleb128 0xc - 525 0078 03 .uleb128 0x3 - 526 0079 0E .uleb128 0xe - 527 007a 3A .uleb128 0x3a - 528 007b 0B .uleb128 0xb - 529 007c 3B .uleb128 0x3b - 530 007d 05 .uleb128 0x5 - 531 007e 27 .uleb128 0x27 - 532 007f 0C .uleb128 0xc - 533 0080 11 .uleb128 0x11 - 534 0081 01 .uleb128 0x1 - 535 0082 12 .uleb128 0x12 - 536 0083 01 .uleb128 0x1 - 537 0084 40 .uleb128 0x40 - 538 0085 0A .uleb128 0xa - 539 0086 9742 .uleb128 0x2117 - 540 0088 0C .uleb128 0xc - 541 0089 00 .byte 0 - 542 008a 00 .byte 0 - 543 008b 0A .uleb128 0xa - 544 008c 2E .uleb128 0x2e - 545 008d 01 .byte 0x1 - 546 008e 3F .uleb128 0x3f - 547 008f 0C .uleb128 0xc - 548 0090 03 .uleb128 0x3 - 549 0091 0E .uleb128 0xe - 550 0092 3A .uleb128 0x3a - 551 0093 0B .uleb128 0xb - 552 0094 3B .uleb128 0x3b - 553 0095 05 .uleb128 0x5 - 554 0096 27 .uleb128 0x27 - 555 0097 0C .uleb128 0xc - 556 0098 11 .uleb128 0x11 - 557 0099 01 .uleb128 0x1 - 558 009a 12 .uleb128 0x12 - 559 009b 01 .uleb128 0x1 - 560 009c 40 .uleb128 0x40 - 561 009d 0A .uleb128 0xa - 562 009e 9742 .uleb128 0x2117 - 563 00a0 0C .uleb128 0xc - 564 00a1 01 .uleb128 0x1 - 565 00a2 13 .uleb128 0x13 - 566 00a3 00 .byte 0 - 567 00a4 00 .byte 0 - 568 00a5 0B .uleb128 0xb - 569 00a6 898201 .uleb128 0x4109 - 570 00a9 00 .byte 0 - 571 00aa 11 .uleb128 0x11 - 572 00ab 01 .uleb128 0x1 - 573 00ac 9542 .uleb128 0x2115 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 21 - - - 574 00ae 0C .uleb128 0xc - 575 00af 31 .uleb128 0x31 - 576 00b0 13 .uleb128 0x13 - 577 00b1 00 .byte 0 - 578 00b2 00 .byte 0 - 579 00b3 0C .uleb128 0xc - 580 00b4 01 .uleb128 0x1 - 581 00b5 01 .byte 0x1 - 582 00b6 49 .uleb128 0x49 - 583 00b7 13 .uleb128 0x13 - 584 00b8 01 .uleb128 0x1 - 585 00b9 13 .uleb128 0x13 - 586 00ba 00 .byte 0 - 587 00bb 00 .byte 0 - 588 00bc 0D .uleb128 0xd - 589 00bd 21 .uleb128 0x21 - 590 00be 00 .byte 0 - 591 00bf 49 .uleb128 0x49 - 592 00c0 13 .uleb128 0x13 - 593 00c1 2F .uleb128 0x2f - 594 00c2 0B .uleb128 0xb - 595 00c3 00 .byte 0 - 596 00c4 00 .byte 0 - 597 00c5 0E .uleb128 0xe - 598 00c6 34 .uleb128 0x34 - 599 00c7 00 .byte 0 - 600 00c8 03 .uleb128 0x3 - 601 00c9 0E .uleb128 0xe - 602 00ca 3A .uleb128 0x3a - 603 00cb 0B .uleb128 0xb - 604 00cc 3B .uleb128 0x3b - 605 00cd 0B .uleb128 0xb - 606 00ce 49 .uleb128 0x49 - 607 00cf 13 .uleb128 0x13 - 608 00d0 3F .uleb128 0x3f - 609 00d1 0C .uleb128 0xc - 610 00d2 3C .uleb128 0x3c - 611 00d3 0C .uleb128 0xc - 612 00d4 00 .byte 0 - 613 00d5 00 .byte 0 - 614 00d6 0F .uleb128 0xf - 615 00d7 2E .uleb128 0x2e - 616 00d8 00 .byte 0 - 617 00d9 3F .uleb128 0x3f - 618 00da 0C .uleb128 0xc - 619 00db 03 .uleb128 0x3 - 620 00dc 0E .uleb128 0xe - 621 00dd 3A .uleb128 0x3a - 622 00de 0B .uleb128 0xb - 623 00df 3B .uleb128 0x3b - 624 00e0 0B .uleb128 0xb - 625 00e1 27 .uleb128 0x27 - 626 00e2 0C .uleb128 0xc - 627 00e3 3C .uleb128 0x3c - 628 00e4 0C .uleb128 0xc - 629 00e5 00 .byte 0 - 630 00e6 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 22 - - - 631 00e7 00 .byte 0 - 632 .section .debug_aranges,"",%progbits - 633 0000 34000000 .4byte 0x34 - 634 0004 0200 .2byte 0x2 - 635 0006 00000000 .4byte .Ldebug_info0 - 636 000a 04 .byte 0x4 - 637 000b 00 .byte 0 - 638 000c 0000 .2byte 0 - 639 000e 0000 .2byte 0 - 640 0010 00000000 .4byte .LFB0 - 641 0014 34000000 .4byte .LFE0-.LFB0 - 642 0018 00000000 .4byte .LFB1 - 643 001c 34000000 .4byte .LFE1-.LFB1 - 644 0020 00000000 .4byte .LFB2 - 645 0024 02000000 .4byte .LFE2-.LFB2 - 646 0028 00000000 .4byte .LFB3 - 647 002c 04000000 .4byte .LFE3-.LFB3 - 648 0030 00000000 .4byte 0 - 649 0034 00000000 .4byte 0 - 650 .section .debug_ranges,"",%progbits - 651 .Ldebug_ranges0: - 652 0000 00000000 .4byte .LFB0 - 653 0004 34000000 .4byte .LFE0 - 654 0008 00000000 .4byte .LFB1 - 655 000c 34000000 .4byte .LFE1 - 656 0010 00000000 .4byte .LFB2 - 657 0014 02000000 .4byte .LFE2 - 658 0018 00000000 .4byte .LFB3 - 659 001c 04000000 .4byte .LFE3 - 660 0020 00000000 .4byte 0 - 661 0024 00000000 .4byte 0 - 662 .section .debug_line,"",%progbits - 663 .Ldebug_line0: - 664 0000 BD000000 .section .debug_str,"MS",%progbits,1 - 664 02006400 - 664 00000201 - 664 FB0E0D00 - 664 01010101 - 665 .LASF34: - 666 0000 55534246 .ascii "USBFS_ReInitComponent\000" - 666 535F5265 - 666 496E6974 - 666 436F6D70 - 666 6F6E656E - 667 .LASF3: - 668 0016 73686F72 .ascii "short unsigned int\000" - 668 7420756E - 668 7369676E - 668 65642069 - 668 6E7400 - 669 .LASF25: - 670 0029 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 670 4246535F - 670 45505F43 - 670 544C5F42 - 670 4C4F434B - 671 .LASF32: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 23 - - - 672 003e 55534246 .ascii "USBFS_BUS_RESET_ISR\000" - 672 535F4255 - 672 535F5245 - 672 5345545F - 672 49535200 - 673 .LASF11: - 674 0052 666C6F61 .ascii "float\000" - 674 7400 - 675 .LASF19: - 676 0058 6570546F .ascii "epToggle\000" - 676 67676C65 - 676 00 - 677 .LASF1: - 678 0061 756E7369 .ascii "unsigned char\000" - 678 676E6564 - 678 20636861 - 678 7200 - 679 .LASF30: - 680 006f 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_episr.c\000" - 680 6E657261 - 680 7465645F - 680 536F7572 - 680 63655C50 - 681 .LASF14: - 682 0096 72656738 .ascii "reg8\000" - 682 00 - 683 .LASF5: - 684 009b 6C6F6E67 .ascii "long unsigned int\000" - 684 20756E73 - 684 69676E65 - 684 6420696E - 684 7400 - 685 .LASF31: - 686 00ad 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 686 43534932 - 686 53445C73 - 686 6F667477 - 686 6172655C - 687 00dc 6E00 .ascii "n\000" - 688 .LASF20: - 689 00de 61646472 .ascii "addr\000" - 689 00 - 690 .LASF28: - 691 00e3 55534246 .ascii "USBFS_SOF_ISR\000" - 691 535F534F - 691 465F4953 - 691 5200 - 692 .LASF33: - 693 00f1 55534246 .ascii "USBFS_EP\000" - 693 535F4550 - 693 00 - 694 .LASF12: - 695 00fa 646F7562 .ascii "double\000" - 695 6C6500 - 696 .LASF16: - 697 0101 61747472 .ascii "attrib\000" - 697 696200 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 24 - - - 698 .LASF22: - 699 0108 62756666 .ascii "buffOffset\000" - 699 4F666673 - 699 657400 - 700 .LASF10: - 701 0113 75696E74 .ascii "uint16\000" - 701 313600 - 702 .LASF17: - 703 011a 61706945 .ascii "apiEpState\000" - 703 70537461 - 703 746500 - 704 .LASF8: - 705 0125 756E7369 .ascii "unsigned int\000" - 705 676E6564 - 705 20696E74 - 705 00 - 706 .LASF7: - 707 0132 6C6F6E67 .ascii "long long unsigned int\000" - 707 206C6F6E - 707 6720756E - 707 7369676E - 707 65642069 - 708 .LASF18: - 709 0149 68774570 .ascii "hwEpState\000" - 709 53746174 - 709 6500 - 710 .LASF26: - 711 0153 55534246 .ascii "USBFS_EP_1_ISR\000" - 711 535F4550 - 711 5F315F49 - 711 535200 - 712 .LASF15: - 713 0162 73697A65 .ascii "sizetype\000" - 713 74797065 - 713 00 - 714 .LASF21: - 715 016b 65704D6F .ascii "epMode\000" - 715 646500 - 716 .LASF6: - 717 0172 6C6F6E67 .ascii "long long int\000" - 717 206C6F6E - 717 6720696E - 717 7400 - 718 .LASF13: - 719 0180 63686172 .ascii "char\000" - 719 00 - 720 .LASF23: - 721 0185 62756666 .ascii "bufferSize\000" - 721 65725369 - 721 7A6500 - 722 .LASF2: - 723 0190 73686F72 .ascii "short int\000" - 723 7420696E - 723 7400 - 724 .LASF9: - 725 019a 75696E74 .ascii "uint8\000" - 725 3800 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccPPhPqT.s page 25 - - - 726 .LASF29: - 727 01a0 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 727 4320342E - 727 372E3320 - 727 32303133 - 727 30333132 - 728 01d3 616E6368 .ascii "anch revision 196615]\000" - 728 20726576 - 728 6973696F - 728 6E203139 - 728 36363135 - 729 .LASF24: - 730 01e9 696E7465 .ascii "interface\000" - 730 72666163 - 730 6500 - 731 .LASF4: - 732 01f3 6C6F6E67 .ascii "long int\000" - 732 20696E74 - 732 00 - 733 .LASF27: - 734 01fc 55534246 .ascii "USBFS_EP_2_ISR\000" - 734 535F4550 - 734 5F325F49 - 734 535200 - 735 .LASF0: - 736 020b 7369676E .ascii "signed char\000" - 736 65642063 - 736 68617200 - 737 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_episr.o deleted file mode 100755 index 9995c86fe65c4aa77f3dd967aa00865e617c5897..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4544 zcmb_fU2Ggz6+U-n_Q&4!Cbm=OSJoy?6bIo=)^<`iL`~wYt&T@Yx7`{v&;cV?M2! zdvCw<+HX*fA+uZJCD6hJ^NJL7{um;efuSMNHWY@Dc%D6t)DUx4;&04Zsc$luPI%0v zQ)2+rN;H}Q>rQ~PzQLMXXJBRxGP(GW^ta}vqxDY)k=|j`7nt7t4t^6{6e3h1PG-%m zNnncGYHmx-{ggVy+>;?EQnSoG6>>)EQ}8zLgq)fBBXduOoRxZ)qO5ApPU4_umZZvm`}uR|h4f{pj!f#~Dti|7|8 za)TK&cQ|)5*)QhB-Xu~Tr%dJ{2vN5pvHPqcGIQrMAIZ!PqR(fEAvq{A8I}n!slLcy zvKN^PbTJ!xoXqx%0dcAK?o^hjCz2;ROEx60es}4m$mR4+!-mfW(ojviK)B5Cn^t&Rz179 zw37FnjfUTFoB85{=gt++K1zt@cy)V86~GyyLdR60a_&yR5S1=n5m^L5wD zBUgS}<;vgi+$G2NUC%%D|0wVB7|xLG*wqG!5s--zcA&F4dTpGNy{T(G#(=d?+$Z*% z2gE^fNDN!Y1mVQfJq$s{leui4{}g=;rw##r5)fDEM1zfnBA7A9x|IXbQCi zRH)g3O@*rOQvpj*U|}KZVz}Jzp$OX>x7M4n+qm;2No~!kt}j;_&AN;9lD4Z=tZrC= zl3>l39aU5)dbeb?(R6eO%!&$2?%En3_5#+m5FUf|pfgI{v)3Hm!Vkp5u;5n=UL|tq zi&nAGMSBziwlkHY+m3ZSPU7LupAWL*Z-wr>@tFGR|1j)&@aVC!Cyajx0=D6Y^UdOk z$6EpaUh$?OkH>4p;&Bgjyw7yS`xbcp(g7LK8(nrUg4eaj?L08?yqmGSEZ2Fz23q%$ z{a?oOyO=s|$~X;xLRfRoCGLF>K` zI-d6*dkJ5^VP1TLM0sD2`GBOmh{tw%=y*ScARaH@Pjm?~o(Dol@%{i>`+%g^5RZNJ z(7NA35Rdm5;^iUZcmsHJpWgt@KD-Zk>_D+Uw!p08=S_v$?k+aTXCc!=+r13|N@{6& zIz=?D86ey7$bir^^A})ug9$bC-bukIK98MPU-rXR&jaGM&l0!=c;rbkvE z(Jq91{tx2eczf}1PRt`3f5)N*5!YFJOx!Uii{82y*O?t!jvudt`FKX=Ey8w=4NI3xR0>(ZfJ_C&014iD@23mZA5r00UKjeHKS$|&PWrbH2URU@Dg^wzHTwzP$ zw!$we{E9;P*B0^R-(?{G;pTilR`?5rzgPGtg@0AZ3&i$0g+~;ANa2GDrxngICUAc! z{IrtWjM&nSLRZOeGh*v*E98H|obStw*uq~`_@creDgCb$@+mTK(0D&^-UE!tlV?QS z5k_?sSkHTj5hl`3t``{T4|}AReliaHjwpY=U)k?D<@d6(dsXSB-;l}=JKpOCc$pvZ SClt@`FRtrh#b0Gap8o 0u) - 37 .loc 1 66 0 - 38 0006 084B ldr r3, .L6+4 - 39 0008 195C ldrb r1, [r3, r0] @ zero_extendqisi2 - 40 000a 29B1 cbz r1, .L3 - 67:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 68:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interface]--; - 41 .loc 1 68 0 - 42 000c 195C ldrb r1, [r3, r0] @ zero_extendqisi2 - 43 000e 4A1E subs r2, r1, #1 - 44 0010 D1B2 uxtb r1, r2 - 45 0012 1954 strb r1, [r3, r0] - 46 .LVL1: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 3 - - - 69:.\Generated_Source\PSoC5/USBFS_hid.c **** stat = USBFS_IDLE_TIMER_RUNNING; - 47 .loc 1 69 0 - 48 0014 0220 movs r0, #2 - 49 .LVL2: - 50 0016 7047 bx lr - 51 .LVL3: - 52 .L3: - 70:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 71:.\Generated_Source\PSoC5/USBFS_hid.c **** else - 72:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 73:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interface] = USBFS_hidIdleRate[interface]; - 53 .loc 1 73 0 - 54 0018 125C ldrb r2, [r2, r0] @ zero_extendqisi2 - 55 001a 1A54 strb r2, [r3, r0] - 56 .LVL4: - 74:.\Generated_Source\PSoC5/USBFS_hid.c **** stat = USBFS_IDLE_TIMER_EXPIRED; - 57 .loc 1 74 0 - 58 001c 0120 movs r0, #1 - 59 .LVL5: - 60 001e 7047 bx lr - 61 .LVL6: - 62 .L4: - 62:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 stat = USBFS_IDLE_TIMER_INDEFINITE; - 63 .loc 1 62 0 - 64 0020 1846 mov r0, r3 - 65 .LVL7: - 75:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 76:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 77:.\Generated_Source\PSoC5/USBFS_hid.c **** - 78:.\Generated_Source\PSoC5/USBFS_hid.c **** return(stat); - 79:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 66 .loc 1 79 0 - 67 0022 7047 bx lr - 68 .L7: - 69 .align 2 - 70 .L6: - 71 0024 00000000 .word USBFS_hidIdleRate - 72 0028 00000000 .word USBFS_hidIdleTimer - 73 .cfi_endproc - 74 .LFE0: - 75 .size USBFS_UpdateHIDTimer, .-USBFS_UpdateHIDTimer - 76 .section .text.USBFS_GetProtocol,"ax",%progbits - 77 .align 1 - 78 .global USBFS_GetProtocol - 79 .thumb - 80 .thumb_func - 81 .type USBFS_GetProtocol, %function - 82 USBFS_GetProtocol: - 83 .LFB1: - 80:.\Generated_Source\PSoC5/USBFS_hid.c **** - 81:.\Generated_Source\PSoC5/USBFS_hid.c **** - 82:.\Generated_Source\PSoC5/USBFS_hid.c **** /******************************************************************************* - 83:.\Generated_Source\PSoC5/USBFS_hid.c **** * Function Name: USBFS_GetProtocol - 84:.\Generated_Source\PSoC5/USBFS_hid.c **** ******************************************************************************** - 85:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 86:.\Generated_Source\PSoC5/USBFS_hid.c **** * Summary: - 87:.\Generated_Source\PSoC5/USBFS_hid.c **** * Returns the selected protocol value to the application - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 4 - - - 88:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 89:.\Generated_Source\PSoC5/USBFS_hid.c **** * Parameters: - 90:.\Generated_Source\PSoC5/USBFS_hid.c **** * interface: Interface Number. - 91:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 92:.\Generated_Source\PSoC5/USBFS_hid.c **** * Return: - 93:.\Generated_Source\PSoC5/USBFS_hid.c **** * Interface protocol. - 94:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 95:.\Generated_Source\PSoC5/USBFS_hid.c **** *******************************************************************************/ - 96:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 USBFS_GetProtocol(uint8 interface) - 97:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 84 .loc 1 97 0 - 85 .cfi_startproc - 86 @ args = 0, pretend = 0, frame = 0 - 87 @ frame_needed = 0, uses_anonymous_args = 0 - 88 @ link register save eliminated. - 89 .LVL8: - 98:.\Generated_Source\PSoC5/USBFS_hid.c **** return(USBFS_hidProtocol[interface]); - 90 .loc 1 98 0 - 91 0000 014B ldr r3, .L9 - 92 0002 185C ldrb r0, [r3, r0] @ zero_extendqisi2 - 93 .LVL9: - 99:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 94 .loc 1 99 0 - 95 0004 7047 bx lr - 96 .L10: - 97 0006 00BF .align 2 - 98 .L9: - 99 0008 00000000 .word USBFS_hidProtocol - 100 .cfi_endproc - 101 .LFE1: - 102 .size USBFS_GetProtocol, .-USBFS_GetProtocol - 103 .section .text.USBFS_FindHidClassDecriptor,"ax",%progbits - 104 .align 1 - 105 .global USBFS_FindHidClassDecriptor - 106 .thumb - 107 .thumb_func - 108 .type USBFS_FindHidClassDecriptor, %function - 109 USBFS_FindHidClassDecriptor: - 110 .LFB3: - 100:.\Generated_Source\PSoC5/USBFS_hid.c **** - 101:.\Generated_Source\PSoC5/USBFS_hid.c **** - 102:.\Generated_Source\PSoC5/USBFS_hid.c **** /******************************************************************************* - 103:.\Generated_Source\PSoC5/USBFS_hid.c **** * Function Name: USBFS_DispatchHIDClassRqst - 104:.\Generated_Source\PSoC5/USBFS_hid.c **** ******************************************************************************** - 105:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 106:.\Generated_Source\PSoC5/USBFS_hid.c **** * Summary: - 107:.\Generated_Source\PSoC5/USBFS_hid.c **** * This routine dispatches class requests - 108:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 109:.\Generated_Source\PSoC5/USBFS_hid.c **** * Parameters: - 110:.\Generated_Source\PSoC5/USBFS_hid.c **** * None. - 111:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 112:.\Generated_Source\PSoC5/USBFS_hid.c **** * Return: - 113:.\Generated_Source\PSoC5/USBFS_hid.c **** * requestHandled - 114:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 115:.\Generated_Source\PSoC5/USBFS_hid.c **** * Reentrant: - 116:.\Generated_Source\PSoC5/USBFS_hid.c **** * No. - 117:.\Generated_Source\PSoC5/USBFS_hid.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 5 - - - 118:.\Generated_Source\PSoC5/USBFS_hid.c **** *******************************************************************************/ - 119:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 USBFS_DispatchHIDClassRqst(void) - 120:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 121:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 requestHandled = USBFS_FALSE; - 122:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 interfaceNumber; - 123:.\Generated_Source\PSoC5/USBFS_hid.c **** - 124:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - 125:.\Generated_Source\PSoC5/USBFS_hid.c **** if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - 126:.\Generated_Source\PSoC5/USBFS_hid.c **** { /* Control Read */ - 127:.\Generated_Source\PSoC5/USBFS_hid.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 128:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 129:.\Generated_Source\PSoC5/USBFS_hid.c **** case USBFS_GET_DESCRIPTOR: - 130:.\Generated_Source\PSoC5/USBFS_hid.c **** if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS) - 131:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 132:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindHidClassDecriptor(); - 133:.\Generated_Source\PSoC5/USBFS_hid.c **** if (USBFS_currentTD.count != 0u) - 134:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 135:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlRead(); - 136:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 137:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 138:.\Generated_Source\PSoC5/USBFS_hid.c **** else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT) - 139:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 140:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindReportDescriptor(); - 141:.\Generated_Source\PSoC5/USBFS_hid.c **** if (USBFS_currentTD.count != 0u) - 142:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 143:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlRead(); - 144:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 145:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 146:.\Generated_Source\PSoC5/USBFS_hid.c **** else - 147:.\Generated_Source\PSoC5/USBFS_hid.c **** { /* requestHandled is initialezed as FALSE by default */ - 148:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 149:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 150:.\Generated_Source\PSoC5/USBFS_hid.c **** case USBFS_HID_GET_REPORT: - 151:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindReport(); - 152:.\Generated_Source\PSoC5/USBFS_hid.c **** if (USBFS_currentTD.count != 0u) - 153:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 154:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlRead(); - 155:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 156:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 157:.\Generated_Source\PSoC5/USBFS_hid.c **** - 158:.\Generated_Source\PSoC5/USBFS_hid.c **** case USBFS_HID_GET_IDLE: - 159:.\Generated_Source\PSoC5/USBFS_hid.c **** /* This function does not support multiple reports per interface*/ - 160:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Validate interfaceNumber and Report ID (should be 0) */ - 161:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 162:.\Generated_Source\PSoC5/USBFS_hid.c **** (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ - 163:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 164:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = 1u; - 165:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; - 166:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlRead(); - 167:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 168:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 169:.\Generated_Source\PSoC5/USBFS_hid.c **** case USBFS_HID_GET_PROTOCOL: - 170:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Validate interfaceNumber */ - 171:.\Generated_Source\PSoC5/USBFS_hid.c **** if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) - 172:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 173:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = 1u; - 174:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 6 - - - 175:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlRead(); - 176:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 177:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 178:.\Generated_Source\PSoC5/USBFS_hid.c **** default: /* requestHandled is initialized as FALSE by default */ - 179:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 180:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 181:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 182:.\Generated_Source\PSoC5/USBFS_hid.c **** else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == - 183:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_RQST_DIR_H2D) - 184:.\Generated_Source\PSoC5/USBFS_hid.c **** { /* Control Write */ - 185:.\Generated_Source\PSoC5/USBFS_hid.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 186:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 187:.\Generated_Source\PSoC5/USBFS_hid.c **** case USBFS_HID_SET_REPORT: - 188:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindReport(); - 189:.\Generated_Source\PSoC5/USBFS_hid.c **** if (USBFS_currentTD.count != 0u) - 190:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 191:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlWrite(); - 192:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 193:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 194:.\Generated_Source\PSoC5/USBFS_hid.c **** case USBFS_HID_SET_IDLE: - 195:.\Generated_Source\PSoC5/USBFS_hid.c **** /* This function does not support multiple reports per interface */ - 196:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Validate interfaceNumber and Report ID (should be 0) */ - 197:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 198:.\Generated_Source\PSoC5/USBFS_hid.c **** (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ - 199:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 200:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi); - 201:.\Generated_Source\PSoC5/USBFS_hid.c **** /* With regards to HID spec: "7.2.4 Set_Idle Request" - 202:.\Generated_Source\PSoC5/USBFS_hid.c **** * Latency. If the current period has gone past the - 203:.\Generated_Source\PSoC5/USBFS_hid.c **** * newly proscribed time duration, then a report - 204:.\Generated_Source\PSoC5/USBFS_hid.c **** * will be generated immediately. - 205:.\Generated_Source\PSoC5/USBFS_hid.c **** */ - 206:.\Generated_Source\PSoC5/USBFS_hid.c **** if(USBFS_hidIdleRate[interfaceNumber] < - 207:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber]) - 208:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 209:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER - 210:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber] = 0u; - 211:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 212:.\Generated_Source\PSoC5/USBFS_hid.c **** /* If the new request is received within 4 milliseconds - 213:.\Generated_Source\PSoC5/USBFS_hid.c **** * (1 count) of the end of the current period, then the - 214:.\Generated_Source\PSoC5/USBFS_hid.c **** * new request will have no effect until after the report. - 215:.\Generated_Source\PSoC5/USBFS_hid.c **** */ - 216:.\Generated_Source\PSoC5/USBFS_hid.c **** else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) - 217:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 218:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Do nothing. - 219:.\Generated_Source\PSoC5/USBFS_hid.c **** * Let the UpdateHIDTimer() API continue to work and - 220:.\Generated_Source\PSoC5/USBFS_hid.c **** * return IDLE_TIMER_EXPIRED status - 221:.\Generated_Source\PSoC5/USBFS_hid.c **** */ - 222:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 223:.\Generated_Source\PSoC5/USBFS_hid.c **** else - 224:.\Generated_Source\PSoC5/USBFS_hid.c **** { /* Reload the timer*/ - 225:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber] = - 226:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleRate[interfaceNumber]; - 227:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 228:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 229:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 230:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 231:.\Generated_Source\PSoC5/USBFS_hid.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 7 - - - 232:.\Generated_Source\PSoC5/USBFS_hid.c **** case USBFS_HID_SET_PROTOCOL: - 233:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Validate interfaceNumber and protocol (must be 0 or 1) */ - 234:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 235:.\Generated_Source\PSoC5/USBFS_hid.c **** (CY_GET_REG8(USBFS_wValueLo) <= 1u) ) - 236:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 237:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo); - 238:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 239:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 240:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 241:.\Generated_Source\PSoC5/USBFS_hid.c **** default: /* requestHandled is initialized as FALSE by default */ - 242:.\Generated_Source\PSoC5/USBFS_hid.c **** break; - 243:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 244:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 245:.\Generated_Source\PSoC5/USBFS_hid.c **** else - 246:.\Generated_Source\PSoC5/USBFS_hid.c **** { /* requestHandled is initialized as FALSE by default */ - 247:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 248:.\Generated_Source\PSoC5/USBFS_hid.c **** - 249:.\Generated_Source\PSoC5/USBFS_hid.c **** return(requestHandled); - 250:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 251:.\Generated_Source\PSoC5/USBFS_hid.c **** - 252:.\Generated_Source\PSoC5/USBFS_hid.c **** - 253:.\Generated_Source\PSoC5/USBFS_hid.c **** /******************************************************************************* - 254:.\Generated_Source\PSoC5/USBFS_hid.c **** * Function Name: USB_FindHidClassDescriptor - 255:.\Generated_Source\PSoC5/USBFS_hid.c **** ******************************************************************************** - 256:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 257:.\Generated_Source\PSoC5/USBFS_hid.c **** * Summary: - 258:.\Generated_Source\PSoC5/USBFS_hid.c **** * This routine find Hid Class Descriptor pointer based on the Interface number - 259:.\Generated_Source\PSoC5/USBFS_hid.c **** * and Alternate setting then loads the currentTD structure with the address of - 260:.\Generated_Source\PSoC5/USBFS_hid.c **** * the buffer and the size. - 261:.\Generated_Source\PSoC5/USBFS_hid.c **** * The HID Class Descriptor resides inside the config descriptor. - 262:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 263:.\Generated_Source\PSoC5/USBFS_hid.c **** * Parameters: - 264:.\Generated_Source\PSoC5/USBFS_hid.c **** * None. - 265:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 266:.\Generated_Source\PSoC5/USBFS_hid.c **** * Return: - 267:.\Generated_Source\PSoC5/USBFS_hid.c **** * currentTD - 268:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 269:.\Generated_Source\PSoC5/USBFS_hid.c **** * Reentrant: - 270:.\Generated_Source\PSoC5/USBFS_hid.c **** * No. - 271:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 272:.\Generated_Source\PSoC5/USBFS_hid.c **** *******************************************************************************/ - 273:.\Generated_Source\PSoC5/USBFS_hid.c **** void USBFS_FindHidClassDecriptor(void) - 274:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 111 .loc 1 274 0 - 112 .cfi_startproc - 113 @ args = 0, pretend = 0, frame = 0 - 114 @ frame_needed = 0, uses_anonymous_args = 0 - 115 0000 08B5 push {r3, lr} - 116 .LCFI0: - 117 .cfi_def_cfa_offset 8 - 118 .cfi_offset 3, -8 - 119 .cfi_offset 14, -4 - 275:.\Generated_Source\PSoC5/USBFS_hid.c **** const T_USBFS_LUT CYCODE *pTmp; - 276:.\Generated_Source\PSoC5/USBFS_hid.c **** volatile uint8 *pDescr; - 277:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 interfaceN; - 278:.\Generated_Source\PSoC5/USBFS_hid.c **** - 279:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 8 - - - 120 .loc 1 279 0 - 121 0002 0B4B ldr r3, .L12 - 122 0004 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 123 0006 411E subs r1, r0, #1 - 124 0008 C8B2 uxtb r0, r1 - 125 000a FFF7FEFF bl USBFS_GetConfigTablePtr - 126 .LVL10: - 280:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceN = CY_GET_REG8(USBFS_wIndexLo); - 127 .loc 1 280 0 - 128 000e 094A ldr r2, .L12+4 - 281:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Third entry in the LUT starts the Interface Table pointers */ - 282:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Now use the request interface number*/ - 283:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[interfaceN + 2u]; - 284:.\Generated_Source\PSoC5/USBFS_hid.c **** /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ - 285:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 286:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Now use Alternate setting number */ - 287:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - 129 .loc 1 287 0 - 130 0010 0949 ldr r1, .L12+8 - 280:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceN = CY_GET_REG8(USBFS_wIndexLo); - 131 .loc 1 280 0 - 132 0012 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 133 .LVL11: - 283:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[interfaceN + 2u]; - 134 .loc 1 283 0 - 135 0014 00EBC300 add r0, r0, r3, lsl #3 - 136 .LVL12: - 285:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 137 .loc 1 285 0 - 138 0018 4269 ldr r2, [r0, #20] - 139 .LVL13: - 140 .loc 1 287 0 - 141 001a CB5C ldrb r3, [r1, r3] @ zero_extendqisi2 - 142 .LVL14: - 143 001c 02EBC300 add r0, r2, r3, lsl #3 - 144 .LVL15: - 288:.\Generated_Source\PSoC5/USBFS_hid.c **** /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ - 289:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 290:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ - 291:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[4u]; - 292:.\Generated_Source\PSoC5/USBFS_hid.c **** pDescr = (volatile uint8 *)pTmp->p_list; - 145 .loc 1 292 0 - 146 0020 4268 ldr r2, [r0, #4] - 293:.\Generated_Source\PSoC5/USBFS_hid.c **** /* The first byte contains the descriptor length */ - 294:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = *pDescr; - 147 .loc 1 294 0 - 148 0022 064B ldr r3, .L12+12 - 292:.\Generated_Source\PSoC5/USBFS_hid.c **** pDescr = (volatile uint8 *)pTmp->p_list; - 149 .loc 1 292 0 - 150 0024 506A ldr r0, [r2, #36] - 151 .LVL16: - 152 .loc 1 294 0 - 153 0026 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 154 0028 1980 strh r1, [r3, #0] @ movhi - 295:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = pDescr; - 155 .loc 1 295 0 - 156 002a 5860 str r0, [r3, #4] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 9 - - - 157 002c 08BD pop {r3, pc} - 158 .L13: - 159 002e 00BF .align 2 - 160 .L12: - 161 0030 00000000 .word USBFS_configuration - 162 0034 04600040 .word 1073766404 - 163 0038 00000000 .word USBFS_interfaceSetting - 164 003c 00000000 .word USBFS_currentTD - 165 .cfi_endproc - 166 .LFE3: - 167 .size USBFS_FindHidClassDecriptor, .-USBFS_FindHidClassDecriptor - 168 .section .text.USBFS_FindReportDescriptor,"ax",%progbits - 169 .align 1 - 170 .global USBFS_FindReportDescriptor - 171 .thumb - 172 .thumb_func - 173 .type USBFS_FindReportDescriptor, %function - 174 USBFS_FindReportDescriptor: - 175 .LFB4: - 296:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 297:.\Generated_Source\PSoC5/USBFS_hid.c **** - 298:.\Generated_Source\PSoC5/USBFS_hid.c **** - 299:.\Generated_Source\PSoC5/USBFS_hid.c **** /******************************************************************************* - 300:.\Generated_Source\PSoC5/USBFS_hid.c **** * Function Name: USB_FindReportDescriptor - 301:.\Generated_Source\PSoC5/USBFS_hid.c **** ******************************************************************************** - 302:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 303:.\Generated_Source\PSoC5/USBFS_hid.c **** * Summary: - 304:.\Generated_Source\PSoC5/USBFS_hid.c **** * This routine find Hid Report Descriptor pointer based on the Interface - 305:.\Generated_Source\PSoC5/USBFS_hid.c **** * number, then loads the currentTD structure with the address of the buffer - 306:.\Generated_Source\PSoC5/USBFS_hid.c **** * and the size. - 307:.\Generated_Source\PSoC5/USBFS_hid.c **** * Hid Report Descriptor is located after IN/OUT/FEATURE reports. - 308:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 309:.\Generated_Source\PSoC5/USBFS_hid.c **** * Parameters: - 310:.\Generated_Source\PSoC5/USBFS_hid.c **** * void - 311:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 312:.\Generated_Source\PSoC5/USBFS_hid.c **** * Return: - 313:.\Generated_Source\PSoC5/USBFS_hid.c **** * currentTD - 314:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 315:.\Generated_Source\PSoC5/USBFS_hid.c **** * Reentrant: - 316:.\Generated_Source\PSoC5/USBFS_hid.c **** * No. - 317:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 318:.\Generated_Source\PSoC5/USBFS_hid.c **** *******************************************************************************/ - 319:.\Generated_Source\PSoC5/USBFS_hid.c **** void USBFS_FindReportDescriptor(void) - 320:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 176 .loc 1 320 0 - 177 .cfi_startproc - 178 @ args = 0, pretend = 0, frame = 0 - 179 @ frame_needed = 0, uses_anonymous_args = 0 - 180 0000 08B5 push {r3, lr} - 181 .LCFI1: - 182 .cfi_def_cfa_offset 8 - 183 .cfi_offset 3, -8 - 184 .cfi_offset 14, -4 - 321:.\Generated_Source\PSoC5/USBFS_hid.c **** const T_USBFS_LUT CYCODE *pTmp; - 322:.\Generated_Source\PSoC5/USBFS_hid.c **** volatile uint8 *pDescr; - 323:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 interfaceN; - 324:.\Generated_Source\PSoC5/USBFS_hid.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 10 - - - 325:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 185 .loc 1 325 0 - 186 0002 0D4B ldr r3, .L15 - 187 0004 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 188 0006 411E subs r1, r0, #1 - 189 0008 C8B2 uxtb r0, r1 - 190 000a FFF7FEFF bl USBFS_GetConfigTablePtr - 191 .LVL17: - 326:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceN = CY_GET_REG8(USBFS_wIndexLo); - 192 .loc 1 326 0 - 193 000e 0B4A ldr r2, .L15+4 - 327:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Third entry in the LUT starts the Interface Table pointers */ - 328:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Now use the request interface number */ - 329:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[interfaceN + 2u]; - 330:.\Generated_Source\PSoC5/USBFS_hid.c **** /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ - 331:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 332:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Now use Alternate setting number */ - 333:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - 194 .loc 1 333 0 - 195 0010 0B49 ldr r1, .L15+8 - 326:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceN = CY_GET_REG8(USBFS_wIndexLo); - 196 .loc 1 326 0 - 197 0012 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 198 .LVL18: - 329:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[interfaceN + 2u]; - 199 .loc 1 329 0 - 200 0014 00EBC300 add r0, r0, r3, lsl #3 - 201 .LVL19: - 331:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 202 .loc 1 331 0 - 203 0018 4269 ldr r2, [r0, #20] - 204 .LVL20: - 205 .loc 1 333 0 - 206 001a CB5C ldrb r3, [r1, r3] @ zero_extendqisi2 - 207 .LVL21: - 208 001c 02EBC300 add r0, r2, r3, lsl #3 - 209 .LVL22: - 334:.\Generated_Source\PSoC5/USBFS_hid.c **** /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ - 335:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 336:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Fourth entry in the LUT starts the Hid Report Descriptor */ - 337:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[3u]; - 338:.\Generated_Source\PSoC5/USBFS_hid.c **** pDescr = (volatile uint8 *)pTmp->p_list; - 210 .loc 1 338 0 - 211 0020 4268 ldr r2, [r0, #4] - 212 0022 D369 ldr r3, [r2, #28] - 213 .LVL23: - 339:.\Generated_Source\PSoC5/USBFS_hid.c **** /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ - 340:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]); - 214 .loc 1 340 0 - 215 0024 074A ldr r2, .L15+12 - 216 0026 5978 ldrb r1, [r3, #1] @ zero_extendqisi2 - 217 0028 13F8020B ldrb r0, [r3], #2 @ zero_extendqisi2 - 218 .LVL24: - 219 002c 40EA0121 orr r1, r0, r1, lsl #8 - 220 0030 1180 strh r1, [r2, #0] @ movhi - 341:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = &pDescr[2u]; - 221 .loc 1 341 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 11 - - - 222 0032 5360 str r3, [r2, #4] - 223 0034 08BD pop {r3, pc} - 224 .L16: - 225 0036 00BF .align 2 - 226 .L15: - 227 0038 00000000 .word USBFS_configuration - 228 003c 04600040 .word 1073766404 - 229 0040 00000000 .word USBFS_interfaceSetting - 230 0044 00000000 .word USBFS_currentTD - 231 .cfi_endproc - 232 .LFE4: - 233 .size USBFS_FindReportDescriptor, .-USBFS_FindReportDescriptor - 234 .section .text.USBFS_FindReport,"ax",%progbits - 235 .align 1 - 236 .global USBFS_FindReport - 237 .thumb - 238 .thumb_func - 239 .type USBFS_FindReport, %function - 240 USBFS_FindReport: - 241 .LFB5: - 342:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 343:.\Generated_Source\PSoC5/USBFS_hid.c **** - 344:.\Generated_Source\PSoC5/USBFS_hid.c **** - 345:.\Generated_Source\PSoC5/USBFS_hid.c **** /******************************************************************************* - 346:.\Generated_Source\PSoC5/USBFS_hid.c **** * Function Name: USBFS_FindReport - 347:.\Generated_Source\PSoC5/USBFS_hid.c **** ******************************************************************************** - 348:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 349:.\Generated_Source\PSoC5/USBFS_hid.c **** * Summary: - 350:.\Generated_Source\PSoC5/USBFS_hid.c **** * This routine sets up a transfer based on the Interface number, Report Type - 351:.\Generated_Source\PSoC5/USBFS_hid.c **** * and Report ID, then loads the currentTD structure with the address of the - 352:.\Generated_Source\PSoC5/USBFS_hid.c **** * buffer and the size. The caller has to decide if it is a control read or - 353:.\Generated_Source\PSoC5/USBFS_hid.c **** * control write. - 354:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 355:.\Generated_Source\PSoC5/USBFS_hid.c **** * Parameters: - 356:.\Generated_Source\PSoC5/USBFS_hid.c **** * None. - 357:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 358:.\Generated_Source\PSoC5/USBFS_hid.c **** * Return: - 359:.\Generated_Source\PSoC5/USBFS_hid.c **** * currentTD - 360:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 361:.\Generated_Source\PSoC5/USBFS_hid.c **** * Reentrant: - 362:.\Generated_Source\PSoC5/USBFS_hid.c **** * No. - 363:.\Generated_Source\PSoC5/USBFS_hid.c **** * - 364:.\Generated_Source\PSoC5/USBFS_hid.c **** *******************************************************************************/ - 365:.\Generated_Source\PSoC5/USBFS_hid.c **** void USBFS_FindReport(void) - 366:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 242 .loc 1 366 0 - 243 .cfi_startproc - 244 @ args = 0, pretend = 0, frame = 0 - 245 @ frame_needed = 0, uses_anonymous_args = 0 - 246 0000 10B5 push {r4, lr} - 247 .LCFI2: - 248 .cfi_def_cfa_offset 8 - 249 .cfi_offset 4, -8 - 250 .cfi_offset 14, -4 - 367:.\Generated_Source\PSoC5/USBFS_hid.c **** const T_USBFS_LUT CYCODE *pTmp; - 368:.\Generated_Source\PSoC5/USBFS_hid.c **** T_USBFS_TD *pTD; - 369:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 interfaceN; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 12 - - - 370:.\Generated_Source\PSoC5/USBFS_hid.c **** uint8 reportType; - 371:.\Generated_Source\PSoC5/USBFS_hid.c **** - 372:.\Generated_Source\PSoC5/USBFS_hid.c **** /* `#START HID_FINDREPORT` Place custom handling here */ - 373:.\Generated_Source\PSoC5/USBFS_hid.c **** - 374:.\Generated_Source\PSoC5/USBFS_hid.c **** /* `#END` */ - 375:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = 0u; /* Init not supported condition */ - 251 .loc 1 375 0 - 252 0002 164C ldr r4, .L19 - 253 0004 0023 movs r3, #0 - 376:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 254 .loc 1 376 0 - 255 0006 1648 ldr r0, .L19+4 - 375:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = 0u; /* Init not supported condition */ - 256 .loc 1 375 0 - 257 0008 2380 strh r3, [r4, #0] @ movhi - 258 .loc 1 376 0 - 259 000a 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 260 000c 4A1E subs r2, r1, #1 - 261 000e D0B2 uxtb r0, r2 - 262 0010 FFF7FEFF bl USBFS_GetConfigTablePtr - 263 .LVL25: - 377:.\Generated_Source\PSoC5/USBFS_hid.c **** reportType = CY_GET_REG8(USBFS_wValueHi); - 378:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceN = CY_GET_REG8(USBFS_wIndexLo); - 264 .loc 1 378 0 - 265 0014 1349 ldr r1, .L19+8 - 377:.\Generated_Source\PSoC5/USBFS_hid.c **** reportType = CY_GET_REG8(USBFS_wValueHi); - 266 .loc 1 377 0 - 267 0016 144B ldr r3, .L19+12 - 268 0018 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 269 .LVL26: - 270 .loc 1 378 0 - 271 001a 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 272 .LVL27: - 379:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */ - 380:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Now use the request interface number */ - 381:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[interfaceN + 2u]; - 273 .loc 1 381 0 - 274 001c 00EBC200 add r0, r0, r2, lsl #3 - 275 .LVL28: - 382:.\Generated_Source\PSoC5/USBFS_hid.c **** /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/ - 383:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 276 .loc 1 383 0 - 277 0020 4169 ldr r1, [r0, #20] - 278 .LVL29: - 384:.\Generated_Source\PSoC5/USBFS_hid.c **** if(interfaceN < USBFS_MAX_INTERFACES_NUMBER) - 279 .loc 1 384 0 - 280 0022 D2B9 cbnz r2, .L17 - 385:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 386:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Now use Alternate setting number */ - 387:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - 281 .loc 1 387 0 - 282 0024 114A ldr r2, .L19+16 - 283 .LVL30: - 388:.\Generated_Source\PSoC5/USBFS_hid.c **** /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ - 389:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 390:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Validate reportType to comply with "7.2.1 Get_Report Request" */ - 391:.\Generated_Source\PSoC5/USBFS_hid.c **** if((reportType >= USBFS_HID_GET_REPORT_INPUT) && - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 13 - - - 284 .loc 1 391 0 - 285 0026 013B subs r3, r3, #1 - 286 .LVL31: - 387:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - 287 .loc 1 387 0 - 288 0028 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 289 .loc 1 391 0 - 290 002a DAB2 uxtb r2, r3 - 387:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - 291 .loc 1 387 0 - 292 002c 01EBC001 add r1, r1, r0, lsl #3 - 293 .LVL32: - 294 .loc 1 391 0 - 295 0030 022A cmp r2, #2 - 389:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - 296 .loc 1 389 0 - 297 0032 4968 ldr r1, [r1, #4] - 298 .LVL33: - 299 .loc 1 391 0 - 300 0034 11D8 bhi .L17 - 392:.\Generated_Source\PSoC5/USBFS_hid.c **** (reportType <= USBFS_HID_GET_REPORT_FEATURE)) - 393:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 394:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ - 395:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[reportType - 1u]; - 396:.\Generated_Source\PSoC5/USBFS_hid.c **** reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */ - 301 .loc 1 396 0 - 302 0036 0E4A ldr r2, .L19+20 - 395:.\Generated_Source\PSoC5/USBFS_hid.c **** pTmp = &pTmp[reportType - 1u]; - 303 .loc 1 395 0 - 304 0038 01EBC300 add r0, r1, r3, lsl #3 - 305 .LVL34: - 306 .loc 1 396 0 - 307 003c 1278 ldrb r2, [r2, #0] @ zero_extendqisi2 - 308 .LVL35: - 397:.\Generated_Source\PSoC5/USBFS_hid.c **** /* Validate table support by the HID descriptor, compare table count with reportID */ - 398:.\Generated_Source\PSoC5/USBFS_hid.c **** if(pTmp->c >= reportType) - 309 .loc 1 398 0 - 310 003e 11F83310 ldrb r1, [r1, r3, lsl #3] @ zero_extendqisi2 - 311 0042 9142 cmp r1, r2 - 312 0044 09D3 bcc .L17 - 399:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 400:.\Generated_Source\PSoC5/USBFS_hid.c **** pTD = (T_USBFS_TD *) pTmp->p_list; - 401:.\Generated_Source\PSoC5/USBFS_hid.c **** pTD = &pTD[reportType]; /* select entry depend on report I - 313 .loc 1 401 0 - 314 0046 0C23 movs r3, #12 - 315 0048 5A43 muls r2, r3, r2 - 316 .LVL36: - 400:.\Generated_Source\PSoC5/USBFS_hid.c **** pTD = (T_USBFS_TD *) pTmp->p_list; - 317 .loc 1 400 0 - 318 004a 4168 ldr r1, [r0, #4] - 319 .LVL37: - 320 .loc 1 401 0 - 321 004c 8B18 adds r3, r1, r2 - 322 .LVL38: - 402:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ - 323 .loc 1 402 0 - 324 004e 5868 ldr r0, [r3, #4] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 14 - - - 325 .LVL39: - 403:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = pTD->count; /* Buffer Size */ - 326 .loc 1 403 0 - 327 0050 8A5A ldrh r2, [r1, r2] - 404:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pStatusBlock = pTD->pStatusBlock; - 328 .loc 1 404 0 - 329 0052 9968 ldr r1, [r3, #8] - 402:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ - 330 .loc 1 402 0 - 331 0054 6060 str r0, [r4, #4] - 403:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = pTD->count; /* Buffer Size */ - 332 .loc 1 403 0 - 333 0056 2280 strh r2, [r4, #0] @ movhi - 334 .loc 1 404 0 - 335 0058 A160 str r1, [r4, #8] - 336 .LVL40: - 337 .L17: - 338 005a 10BD pop {r4, pc} - 339 .L20: - 340 .align 2 - 341 .L19: - 342 005c 00000000 .word USBFS_currentTD - 343 0060 00000000 .word USBFS_configuration - 344 0064 04600040 .word 1073766404 - 345 0068 03600040 .word 1073766403 - 346 006c 00000000 .word USBFS_interfaceSetting - 347 0070 02600040 .word 1073766402 - 348 .cfi_endproc - 349 .LFE5: - 350 .size USBFS_FindReport, .-USBFS_FindReport - 351 .section .text.USBFS_DispatchHIDClassRqst,"ax",%progbits - 352 .align 1 - 353 .global USBFS_DispatchHIDClassRqst - 354 .thumb - 355 .thumb_func - 356 .type USBFS_DispatchHIDClassRqst, %function - 357 USBFS_DispatchHIDClassRqst: - 358 .LFB2: - 120:.\Generated_Source\PSoC5/USBFS_hid.c **** { - 359 .loc 1 120 0 - 360 .cfi_startproc - 361 @ args = 0, pretend = 0, frame = 0 - 362 @ frame_needed = 0, uses_anonymous_args = 0 - 363 .LVL41: - 364 0000 10B5 push {r4, lr} - 365 .LCFI3: - 366 .cfi_def_cfa_offset 8 - 367 .cfi_offset 4, -8 - 368 .cfi_offset 14, -4 - 124:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - 369 .loc 1 124 0 - 370 0002 3A4B ldr r3, .L57 - 125:.\Generated_Source\PSoC5/USBFS_hid.c **** if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - 371 .loc 1 125 0 - 372 0004 3A4A ldr r2, .L57+4 - 124:.\Generated_Source\PSoC5/USBFS_hid.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - 373 .loc 1 124 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 15 - - - 374 0006 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 375 .LVL42: - 125:.\Generated_Source\PSoC5/USBFS_hid.c **** if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - 376 .loc 1 125 0 - 377 0008 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 378 000a 0906 lsls r1, r1, #24 - 379 000c 34D5 bpl .L22 - 127:.\Generated_Source\PSoC5/USBFS_hid.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 380 .loc 1 127 0 - 381 000e 511C adds r1, r2, #1 - 382 0010 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 383 0012 5A1E subs r2, r3, #1 - 384 0014 052A cmp r2, #5 - 385 0016 67D8 bhi .L23 - 386 0018 DFE802F0 tbb [pc, r2] - 387 .L28: - 388 001c 10 .byte (.L24-.L28)/2 - 389 001d 18 .byte (.L25-.L28)/2 - 390 001e 27 .byte (.L26-.L28)/2 - 391 001f 66 .byte (.L23-.L28)/2 - 392 0020 66 .byte (.L23-.L28)/2 - 393 0021 03 .byte (.L27-.L28)/2 - 394 .align 1 - 395 .L27: - 130:.\Generated_Source\PSoC5/USBFS_hid.c **** if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS) - 396 .loc 1 130 0 - 397 0022 3448 ldr r0, .L57+8 - 398 .LVL43: - 399 0024 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 400 0026 2129 cmp r1, #33 - 401 0028 02D1 bne .L29 - 132:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindHidClassDecriptor(); - 402 .loc 1 132 0 - 403 002a FFF7FEFF bl USBFS_FindHidClassDecriptor - 404 .LVL44: - 405 002e 07E0 b .L54 - 406 .L29: - 138:.\Generated_Source\PSoC5/USBFS_hid.c **** else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT) - 407 .loc 1 138 0 - 408 0030 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 409 0032 222B cmp r3, #34 - 410 0034 58D1 bne .L23 - 140:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindReportDescriptor(); - 411 .loc 1 140 0 - 412 0036 FFF7FEFF bl USBFS_FindReportDescriptor - 413 .LVL45: - 414 003a 01E0 b .L54 - 415 .LVL46: - 416 .L24: - 151:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindReport(); - 417 .loc 1 151 0 - 418 003c FFF7FEFF bl USBFS_FindReport - 419 .LVL47: - 420 .L54: - 152:.\Generated_Source\PSoC5/USBFS_hid.c **** if (USBFS_currentTD.count != 0u) - 421 .loc 1 152 0 - 422 0040 2D49 ldr r1, .L57+12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 16 - - - 423 0042 0B88 ldrh r3, [r1, #0] - 424 0044 98B2 uxth r0, r3 - 425 0046 0028 cmp r0, #0 - 426 0048 4ED0 beq .L23 - 427 004a 0AE0 b .L51 - 428 .LVL48: - 429 .L25: - 161:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 430 .loc 1 161 0 - 431 004c 0028 cmp r0, #0 - 432 004e 4BD1 bne .L23 - 162:.\Generated_Source\PSoC5/USBFS_hid.c **** (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ - 433 .loc 1 162 0 discriminator 1 - 434 0050 2A4B ldr r3, .L57+16 - 435 0052 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 436 .LVL49: - 161:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 437 .loc 1 161 0 discriminator 1 - 438 0054 0028 cmp r0, #0 - 439 0056 47D1 bne .L23 - 164:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = 1u; - 440 .loc 1 164 0 - 441 0058 2748 ldr r0, .L57+12 - 442 005a 0122 movs r2, #1 - 165:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; - 443 .loc 1 165 0 - 444 005c 2849 ldr r1, .L57+20 - 164:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = 1u; - 445 .loc 1 164 0 - 446 005e 0280 strh r2, [r0, #0] @ movhi - 447 .L52: - 165:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; - 448 .loc 1 165 0 - 449 0060 4160 str r1, [r0, #4] - 450 .L51: - 250:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 451 .loc 1 250 0 - 452 0062 BDE81040 pop {r4, lr} - 166:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlRead(); - 453 .loc 1 166 0 - 454 0066 FFF7FEBF b USBFS_InitControlRead - 455 .LVL50: - 456 .L26: - 171:.\Generated_Source\PSoC5/USBFS_hid.c **** if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) - 457 .loc 1 171 0 - 458 006a 0028 cmp r0, #0 - 459 006c 3CD1 bne .L23 - 173:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.count = 1u; - 460 .loc 1 173 0 - 461 006e 2248 ldr r0, .L57+12 - 462 .LVL51: - 463 0070 0122 movs r2, #1 - 464 0072 0280 strh r2, [r0, #0] @ movhi - 174:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; - 465 .loc 1 174 0 - 466 0074 2349 ldr r1, .L57+24 - 467 0076 F3E7 b .L52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 17 - - - 468 .LVL52: - 469 .L22: - 182:.\Generated_Source\PSoC5/USBFS_hid.c **** else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == - 470 .loc 1 182 0 - 471 0078 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 472 007a 1A06 lsls r2, r3, #24 - 473 007c 34D4 bmi .L23 - 185:.\Generated_Source\PSoC5/USBFS_hid.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 474 .loc 1 185 0 - 475 007e 224A ldr r2, .L57+28 - 476 0080 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 477 0082 0929 cmp r1, #9 - 478 0084 05D0 beq .L32 - 479 0086 2FD3 bcc .L23 - 480 0088 0A29 cmp r1, #10 - 481 008a 0DD0 beq .L33 - 482 008c 0B29 cmp r1, #11 - 483 008e 2BD1 bne .L23 - 484 0090 22E0 b .L56 - 485 .L32: - 188:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_FindReport(); - 486 .loc 1 188 0 - 487 0092 FFF7FEFF bl USBFS_FindReport - 488 .LVL53: - 189:.\Generated_Source\PSoC5/USBFS_hid.c **** if (USBFS_currentTD.count != 0u) - 489 .loc 1 189 0 - 490 0096 184B ldr r3, .L57+12 - 491 0098 1A88 ldrh r2, [r3, #0] - 492 009a 90B2 uxth r0, r2 - 493 009c 0028 cmp r0, #0 - 494 009e 23D0 beq .L23 - 250:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 495 .loc 1 250 0 - 496 00a0 BDE81040 pop {r4, lr} - 191:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitControlWrite(); - 497 .loc 1 191 0 - 498 00a4 FFF7FEBF b USBFS_InitControlWrite - 499 .LVL54: - 500 .L33: - 197:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 501 .loc 1 197 0 - 502 00a8 F0B9 cbnz r0, .L23 - 198:.\Generated_Source\PSoC5/USBFS_hid.c **** (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ - 503 .loc 1 198 0 discriminator 1 - 504 00aa 1448 ldr r0, .L57+16 - 505 .LVL55: - 506 00ac 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 197:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 507 .loc 1 197 0 discriminator 1 - 508 00ae D9B9 cbnz r1, .L23 - 200:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi); - 509 .loc 1 200 0 - 510 00b0 441C adds r4, r0, #1 - 511 00b2 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 512 00b4 124A ldr r2, .L57+20 - 513 00b6 1370 strb r3, [r2, #0] - 207:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber]) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 18 - - - 514 .loc 1 207 0 - 515 00b8 144B ldr r3, .L57+32 - 206:.\Generated_Source\PSoC5/USBFS_hid.c **** if(USBFS_hidIdleRate[interfaceNumber] < - 516 .loc 1 206 0 - 517 00ba 1478 ldrb r4, [r2, #0] @ zero_extendqisi2 - 207:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber]) - 518 .loc 1 207 0 - 519 00bc 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 206:.\Generated_Source\PSoC5/USBFS_hid.c **** if(USBFS_hidIdleRate[interfaceNumber] < - 520 .loc 1 206 0 - 521 00be 8442 cmp r4, r0 - 522 00c0 01D2 bcs .L35 - 210:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber] = 0u; - 523 .loc 1 210 0 - 524 00c2 1970 strb r1, [r3, #0] - 525 00c4 04E0 b .L36 - 526 .L35: - 216:.\Generated_Source\PSoC5/USBFS_hid.c **** else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) - 527 .loc 1 216 0 - 528 00c6 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 529 00c8 0129 cmp r1, #1 - 530 00ca 01D9 bls .L36 - 226:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleRate[interfaceNumber]; - 531 .loc 1 226 0 - 532 00cc 1278 ldrb r2, [r2, #0] @ zero_extendqisi2 - 533 .L50: - 225:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidIdleTimer[interfaceNumber] = - 534 .loc 1 225 0 - 535 00ce 1A70 strb r2, [r3, #0] - 536 .L36: - 250:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 537 .loc 1 250 0 - 538 00d0 BDE81040 pop {r4, lr} - 228:.\Generated_Source\PSoC5/USBFS_hid.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 539 .loc 1 228 0 - 540 00d4 FFF7FEBF b USBFS_InitNoDataControlTransfer - 541 .LVL56: - 542 .L56: - 234:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 543 .loc 1 234 0 - 544 00d8 30B9 cbnz r0, .L23 - 235:.\Generated_Source\PSoC5/USBFS_hid.c **** (CY_GET_REG8(USBFS_wValueLo) <= 1u) ) - 545 .loc 1 235 0 discriminator 1 - 546 00da 0848 ldr r0, .L57+16 - 547 .LVL57: - 548 00dc 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 234:.\Generated_Source\PSoC5/USBFS_hid.c **** if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - 549 .loc 1 234 0 discriminator 1 - 550 00de 012B cmp r3, #1 - 551 00e0 02D8 bhi .L23 - 237:.\Generated_Source\PSoC5/USBFS_hid.c **** USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo); - 552 .loc 1 237 0 - 553 00e2 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 554 00e4 074B ldr r3, .L57+24 - 555 00e6 F2E7 b .L50 - 556 .L23: - 557 .LVL58: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 19 - - - 250:.\Generated_Source\PSoC5/USBFS_hid.c **** } - 558 .loc 1 250 0 - 559 00e8 0020 movs r0, #0 - 560 00ea 10BD pop {r4, pc} - 561 .L58: - 562 .align 2 - 563 .L57: - 564 00ec 04600040 .word 1073766404 - 565 00f0 00600040 .word 1073766400 - 566 00f4 03600040 .word 1073766403 - 567 00f8 00000000 .word USBFS_currentTD - 568 00fc 02600040 .word 1073766402 - 569 0100 00000000 .word USBFS_hidIdleRate - 570 0104 00000000 .word USBFS_hidProtocol - 571 0108 01600040 .word 1073766401 - 572 010c 00000000 .word USBFS_hidIdleTimer - 573 .cfi_endproc - 574 .LFE2: - 575 .size USBFS_DispatchHIDClassRqst, .-USBFS_DispatchHIDClassRqst - 576 .comm USBFS_hidIdleTimer,1,1 - 577 .comm USBFS_hidIdleRate,1,1 - 578 .comm USBFS_hidProtocol,1,1 - 579 .text - 580 .Letext0: - 581 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 582 .file 3 ".\\Generated_Source\\PSoC5\\USBFS.h" - 583 .file 4 ".\\Generated_Source\\PSoC5\\USBFS_pvt.h" - 584 .section .debug_info,"",%progbits - 585 .Ldebug_info0: - 586 0000 2C040000 .4byte 0x42c - 587 0004 0200 .2byte 0x2 - 588 0006 00000000 .4byte .Ldebug_abbrev0 - 589 000a 04 .byte 0x4 - 590 000b 01 .uleb128 0x1 - 591 000c B5020000 .4byte .LASF48 - 592 0010 01 .byte 0x1 - 593 0011 0D000000 .4byte .LASF49 - 594 0015 1D010000 .4byte .LASF50 - 595 0019 00000000 .4byte .Ldebug_ranges0+0 - 596 001d 00000000 .4byte 0 - 597 0021 00000000 .4byte 0 - 598 0025 00000000 .4byte .Ldebug_line0 - 599 0029 02 .uleb128 0x2 - 600 002a 01 .byte 0x1 - 601 002b 06 .byte 0x6 - 602 002c 11030000 .4byte .LASF0 - 603 0030 02 .uleb128 0x2 - 604 0031 01 .byte 0x1 - 605 0032 08 .byte 0x8 - 606 0033 DE000000 .4byte .LASF1 - 607 0037 02 .uleb128 0x2 - 608 0038 02 .byte 0x2 - 609 0039 05 .byte 0x5 - 610 003a B2010000 .4byte .LASF2 - 611 003e 02 .uleb128 0x2 - 612 003f 02 .byte 0x2 - 613 0040 07 .byte 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 20 - - - 614 0041 67000000 .4byte .LASF3 - 615 0045 02 .uleb128 0x2 - 616 0046 04 .byte 0x4 - 617 0047 05 .byte 0x5 - 618 0048 08030000 .4byte .LASF4 - 619 004c 02 .uleb128 0x2 - 620 004d 04 .byte 0x4 - 621 004e 07 .byte 0x7 - 622 004f 0B010000 .4byte .LASF5 - 623 0053 02 .uleb128 0x2 - 624 0054 08 .byte 0x8 - 625 0055 05 .byte 0x5 - 626 0056 53020000 .4byte .LASF6 - 627 005a 02 .uleb128 0x2 - 628 005b 08 .byte 0x8 - 629 005c 07 .byte 0x7 - 630 005d 0A020000 .4byte .LASF7 - 631 0061 03 .uleb128 0x3 - 632 0062 04 .byte 0x4 - 633 0063 05 .byte 0x5 - 634 0064 696E7400 .ascii "int\000" - 635 0068 02 .uleb128 0x2 - 636 0069 04 .byte 0x4 - 637 006a 07 .byte 0x7 - 638 006b E2010000 .4byte .LASF8 - 639 006f 04 .uleb128 0x4 - 640 0070 4E010000 .4byte .LASF9 - 641 0074 02 .byte 0x2 - 642 0075 5B .byte 0x5b - 643 0076 30000000 .4byte 0x30 - 644 007a 04 .uleb128 0x4 - 645 007b BC010000 .4byte .LASF10 - 646 007f 02 .byte 0x2 - 647 0080 5C .byte 0x5c - 648 0081 3E000000 .4byte 0x3e - 649 0085 02 .uleb128 0x2 - 650 0086 04 .byte 0x4 - 651 0087 04 .byte 0x4 - 652 0088 B9000000 .4byte .LASF11 - 653 008c 02 .uleb128 0x2 - 654 008d 08 .byte 0x8 - 655 008e 04 .byte 0x4 - 656 008f 95010000 .4byte .LASF12 - 657 0093 02 .uleb128 0x2 - 658 0094 01 .byte 0x1 - 659 0095 08 .byte 0x8 - 660 0096 6D020000 .4byte .LASF13 - 661 009a 04 .uleb128 0x4 - 662 009b EC000000 .4byte .LASF14 - 663 009f 02 .byte 0x2 - 664 00a0 F0 .byte 0xf0 - 665 00a1 A5000000 .4byte 0xa5 - 666 00a5 05 .uleb128 0x5 - 667 00a6 6F000000 .4byte 0x6f - 668 00aa 02 .uleb128 0x2 - 669 00ab 04 .byte 0x4 - 670 00ac 07 .byte 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 21 - - - 671 00ad 4A020000 .4byte .LASF15 - 672 00b1 06 .uleb128 0x6 - 673 00b2 04 .byte 0x4 - 674 00b3 03 .byte 0x3 - 675 00b4 90 .byte 0x90 - 676 00b5 D6000000 .4byte 0xd6 - 677 00b9 07 .uleb128 0x7 - 678 00ba 85000000 .4byte .LASF16 - 679 00be 03 .byte 0x3 - 680 00bf 92 .byte 0x92 - 681 00c0 6F000000 .4byte 0x6f - 682 00c4 02 .byte 0x2 - 683 00c5 23 .byte 0x23 - 684 00c6 00 .uleb128 0 - 685 00c7 07 .uleb128 0x7 - 686 00c8 42030000 .4byte .LASF17 - 687 00cc 03 .byte 0x3 - 688 00cd 93 .byte 0x93 - 689 00ce 7A000000 .4byte 0x7a - 690 00d2 02 .byte 0x2 - 691 00d3 23 .byte 0x23 - 692 00d4 02 .uleb128 0x2 - 693 00d5 00 .byte 0 - 694 00d6 04 .uleb128 0x4 - 695 00d7 F1000000 .4byte .LASF18 - 696 00db 03 .byte 0x3 - 697 00dc 94 .byte 0x94 - 698 00dd B1000000 .4byte 0xb1 - 699 00e1 06 .uleb128 0x6 - 700 00e2 0C .byte 0xc - 701 00e3 03 .byte 0x3 - 702 00e4 96 .byte 0x96 - 703 00e5 14010000 .4byte 0x114 - 704 00e9 07 .uleb128 0x7 - 705 00ea 46000000 .4byte .LASF19 - 706 00ee 03 .byte 0x3 - 707 00ef 98 .byte 0x98 - 708 00f0 7A000000 .4byte 0x7a - 709 00f4 02 .byte 0x2 - 710 00f5 23 .byte 0x23 - 711 00f6 00 .uleb128 0 - 712 00f7 07 .uleb128 0x7 - 713 00f8 8C000000 .4byte .LASF20 - 714 00fc 03 .byte 0x3 - 715 00fd 99 .byte 0x99 - 716 00fe 14010000 .4byte 0x114 - 717 0102 02 .byte 0x2 - 718 0103 23 .byte 0x23 - 719 0104 04 .uleb128 0x4 - 720 0105 07 .uleb128 0x7 - 721 0106 00000000 .4byte .LASF21 - 722 010a 03 .byte 0x3 - 723 010b 9A .byte 0x9a - 724 010c 1A010000 .4byte 0x11a - 725 0110 02 .byte 0x2 - 726 0111 23 .byte 0x23 - 727 0112 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 22 - - - 728 0113 00 .byte 0 - 729 0114 08 .uleb128 0x8 - 730 0115 04 .byte 0x4 - 731 0116 A5000000 .4byte 0xa5 - 732 011a 08 .uleb128 0x8 - 733 011b 04 .byte 0x4 - 734 011c D6000000 .4byte 0xd6 - 735 0120 04 .uleb128 0x4 - 736 0121 AE000000 .4byte .LASF22 - 737 0125 03 .byte 0x3 - 738 0126 9B .byte 0x9b - 739 0127 E1000000 .4byte 0xe1 - 740 012b 06 .uleb128 0x6 - 741 012c 08 .byte 0x8 - 742 012d 03 .byte 0x3 - 743 012e 9E .byte 0x9e - 744 012f 4E010000 .4byte 0x14e - 745 0133 09 .uleb128 0x9 - 746 0134 6300 .ascii "c\000" - 747 0136 03 .byte 0x3 - 748 0137 A0 .byte 0xa0 - 749 0138 6F000000 .4byte 0x6f - 750 013c 02 .byte 0x2 - 751 013d 23 .byte 0x23 - 752 013e 00 .uleb128 0 - 753 013f 07 .uleb128 0x7 - 754 0140 21020000 .4byte .LASF23 - 755 0144 03 .byte 0x3 - 756 0145 A1 .byte 0xa1 - 757 0146 4E010000 .4byte 0x14e - 758 014a 02 .byte 0x2 - 759 014b 23 .byte 0x23 - 760 014c 04 .uleb128 0x4 - 761 014d 00 .byte 0 - 762 014e 08 .uleb128 0x8 - 763 014f 04 .byte 0x4 - 764 0150 54010000 .4byte 0x154 - 765 0154 0A .uleb128 0xa - 766 0155 04 .uleb128 0x4 - 767 0156 61020000 .4byte .LASF24 - 768 015a 03 .byte 0x3 - 769 015b A2 .byte 0xa2 - 770 015c 2B010000 .4byte 0x12b - 771 0160 0B .uleb128 0xb - 772 0161 01 .byte 0x1 - 773 0162 A0020000 .4byte .LASF25 - 774 0166 01 .byte 0x1 - 775 0167 3C .byte 0x3c - 776 0168 01 .byte 0x1 - 777 0169 6F000000 .4byte 0x6f - 778 016d 00000000 .4byte .LFB0 - 779 0171 2C000000 .4byte .LFE0 - 780 0175 02 .byte 0x2 - 781 0176 7D .byte 0x7d - 782 0177 00 .sleb128 0 - 783 0178 01 .byte 0x1 - 784 0179 9C010000 .4byte 0x19c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 23 - - - 785 017d 0C .uleb128 0xc - 786 017e FE020000 .4byte .LASF27 - 787 0182 01 .byte 0x1 - 788 0183 3C .byte 0x3c - 789 0184 6F000000 .4byte 0x6f - 790 0188 00000000 .4byte .LLST0 - 791 018c 0D .uleb128 0xd - 792 018d 32000000 .4byte .LASF28 - 793 0191 01 .byte 0x1 - 794 0192 3E .byte 0x3e - 795 0193 6F000000 .4byte 0x6f - 796 0197 53000000 .4byte .LLST1 - 797 019b 00 .byte 0 - 798 019c 0B .uleb128 0xb - 799 019d 01 .byte 0x1 - 800 019e 38020000 .4byte .LASF26 - 801 01a2 01 .byte 0x1 - 802 01a3 60 .byte 0x60 - 803 01a4 01 .byte 0x1 - 804 01a5 6F000000 .4byte 0x6f - 805 01a9 00000000 .4byte .LFB1 - 806 01ad 0C000000 .4byte .LFE1 - 807 01b1 02 .byte 0x2 - 808 01b2 7D .byte 0x7d - 809 01b3 00 .sleb128 0 - 810 01b4 01 .byte 0x1 - 811 01b5 C9010000 .4byte 0x1c9 - 812 01b9 0C .uleb128 0xc - 813 01ba FE020000 .4byte .LASF27 - 814 01be 01 .byte 0x1 - 815 01bf 60 .byte 0x60 - 816 01c0 6F000000 .4byte 0x6f - 817 01c4 A2000000 .4byte .LLST2 - 818 01c8 00 .byte 0 - 819 01c9 0E .uleb128 0xe - 820 01ca 01 .byte 0x1 - 821 01cb 92000000 .4byte .LASF32 - 822 01cf 01 .byte 0x1 - 823 01d0 1101 .2byte 0x111 - 824 01d2 01 .byte 0x1 - 825 01d3 00000000 .4byte .LFB3 - 826 01d7 40000000 .4byte .LFE3 - 827 01db C3000000 .4byte .LLST3 - 828 01df 01 .byte 0x1 - 829 01e0 1C020000 .4byte 0x21c - 830 01e4 0F .uleb128 0xf - 831 01e5 72020000 .4byte .LASF29 - 832 01e9 01 .byte 0x1 - 833 01ea 1301 .2byte 0x113 - 834 01ec 1C020000 .4byte 0x21c - 835 01f0 E3000000 .4byte .LLST4 - 836 01f4 10 .uleb128 0x10 - 837 01f5 DB010000 .4byte .LASF30 - 838 01f9 01 .byte 0x1 - 839 01fa 1401 .2byte 0x114 - 840 01fc 14010000 .4byte 0x114 - 841 0200 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 24 - - - 842 0201 50 .byte 0x50 - 843 0202 0F .uleb128 0xf - 844 0203 7A000000 .4byte .LASF31 - 845 0207 01 .byte 0x1 - 846 0208 1501 .2byte 0x115 - 847 020a 6F000000 .4byte 0x6f - 848 020e 1E010000 .4byte .LLST5 - 849 0212 11 .uleb128 0x11 - 850 0213 0E000000 .4byte .LVL10 - 851 0217 ED030000 .4byte 0x3ed - 852 021b 00 .byte 0 - 853 021c 08 .uleb128 0x8 - 854 021d 04 .byte 0x4 - 855 021e 22020000 .4byte 0x222 - 856 0222 12 .uleb128 0x12 - 857 0223 55010000 .4byte 0x155 - 858 0227 0E .uleb128 0xe - 859 0228 01 .byte 0x1 - 860 0229 4C000000 .4byte .LASF33 - 861 022d 01 .byte 0x1 - 862 022e 3F01 .2byte 0x13f - 863 0230 01 .byte 0x1 - 864 0231 00000000 .4byte .LFB4 - 865 0235 48000000 .4byte .LFE4 - 866 0239 31010000 .4byte .LLST6 - 867 023d 01 .byte 0x1 - 868 023e 7C020000 .4byte 0x27c - 869 0242 0F .uleb128 0xf - 870 0243 72020000 .4byte .LASF29 - 871 0247 01 .byte 0x1 - 872 0248 4101 .2byte 0x141 - 873 024a 1C020000 .4byte 0x21c - 874 024e 51010000 .4byte .LLST7 - 875 0252 0F .uleb128 0xf - 876 0253 DB010000 .4byte .LASF30 - 877 0257 01 .byte 0x1 - 878 0258 4201 .2byte 0x142 - 879 025a 14010000 .4byte 0x114 - 880 025e 7F010000 .4byte .LLST8 - 881 0262 0F .uleb128 0xf - 882 0263 7A000000 .4byte .LASF31 - 883 0267 01 .byte 0x1 - 884 0268 4301 .2byte 0x143 - 885 026a 6F000000 .4byte 0x6f - 886 026e 9F010000 .4byte .LLST9 - 887 0272 11 .uleb128 0x11 - 888 0273 0E000000 .4byte .LVL17 - 889 0277 ED030000 .4byte 0x3ed - 890 027b 00 .byte 0 - 891 027c 0E .uleb128 0xe - 892 027d 01 .byte 0x1 - 893 027e 84010000 .4byte .LASF34 - 894 0282 01 .byte 0x1 - 895 0283 6D01 .2byte 0x16d - 896 0285 01 .byte 0x1 - 897 0286 00000000 .4byte .LFB5 - 898 028a 74000000 .4byte .LFE5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 25 - - - 899 028e B2010000 .4byte .LLST10 - 900 0292 01 .byte 0x1 - 901 0293 E1020000 .4byte 0x2e1 - 902 0297 0F .uleb128 0xf - 903 0298 72020000 .4byte .LASF29 - 904 029c 01 .byte 0x1 - 905 029d 6F01 .2byte 0x16f - 906 029f 1C020000 .4byte 0x21c - 907 02a3 D2010000 .4byte .LLST11 - 908 02a7 13 .uleb128 0x13 - 909 02a8 70544400 .ascii "pTD\000" - 910 02ac 01 .byte 0x1 - 911 02ad 7001 .2byte 0x170 - 912 02af E1020000 .4byte 0x2e1 - 913 02b3 FB010000 .4byte .LLST12 - 914 02b7 0F .uleb128 0xf - 915 02b8 7A000000 .4byte .LASF31 - 916 02bc 01 .byte 0x1 - 917 02bd 7101 .2byte 0x171 - 918 02bf 6F000000 .4byte 0x6f - 919 02c3 19020000 .4byte .LLST13 - 920 02c7 0F .uleb128 0xf - 921 02c8 BF000000 .4byte .LASF35 - 922 02cc 01 .byte 0x1 - 923 02cd 7201 .2byte 0x172 - 924 02cf 6F000000 .4byte 0x6f - 925 02d3 2C020000 .4byte .LLST14 - 926 02d7 11 .uleb128 0x11 - 927 02d8 14000000 .4byte .LVL25 - 928 02dc ED030000 .4byte 0x3ed - 929 02e0 00 .byte 0 - 930 02e1 08 .uleb128 0x8 - 931 02e2 04 .byte 0x4 - 932 02e3 20010000 .4byte 0x120 - 933 02e7 14 .uleb128 0x14 - 934 02e8 01 .byte 0x1 - 935 02e9 EF010000 .4byte .LASF36 - 936 02ed 01 .byte 0x1 - 937 02ee 77 .byte 0x77 - 938 02ef 01 .byte 0x1 - 939 02f0 6F000000 .4byte 0x6f - 940 02f4 00000000 .4byte .LFB2 - 941 02f8 10010000 .4byte .LFE2 - 942 02fc 57020000 .4byte .LLST15 - 943 0300 01 .byte 0x1 - 944 0301 66030000 .4byte 0x366 - 945 0305 0D .uleb128 0xd - 946 0306 37000000 .4byte .LASF37 - 947 030a 01 .byte 0x1 - 948 030b 79 .byte 0x79 - 949 030c 6F000000 .4byte 0x6f - 950 0310 77020000 .4byte .LLST16 - 951 0314 0D .uleb128 0xd - 952 0315 54010000 .4byte .LASF38 - 953 0319 01 .byte 0x1 - 954 031a 7A .byte 0x7a - 955 031b 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 26 - - - 956 031f 8B020000 .4byte .LLST17 - 957 0323 11 .uleb128 0x11 - 958 0324 2E000000 .4byte .LVL44 - 959 0328 C9010000 .4byte 0x1c9 - 960 032c 11 .uleb128 0x11 - 961 032d 3A000000 .4byte .LVL45 - 962 0331 27020000 .4byte 0x227 - 963 0335 11 .uleb128 0x11 - 964 0336 40000000 .4byte .LVL47 - 965 033a 7C020000 .4byte 0x27c - 966 033e 15 .uleb128 0x15 - 967 033f 6A000000 .4byte .LVL50 - 968 0343 01 .byte 0x1 - 969 0344 05040000 .4byte 0x405 - 970 0348 11 .uleb128 0x11 - 971 0349 96000000 .4byte .LVL53 - 972 034d 7C020000 .4byte 0x27c - 973 0351 15 .uleb128 0x15 - 974 0352 A8000000 .4byte .LVL54 - 975 0356 01 .byte 0x1 - 976 0357 13040000 .4byte 0x413 - 977 035b 15 .uleb128 0x15 - 978 035c D8000000 .4byte .LVL56 - 979 0360 01 .byte 0x1 - 980 0361 21040000 .4byte 0x421 - 981 0365 00 .byte 0 - 982 0366 16 .uleb128 0x16 - 983 0367 CA000000 .4byte .LASF39 - 984 036b 03 .byte 0x3 - 985 036c 1A02 .2byte 0x21a - 986 036e A5000000 .4byte 0xa5 - 987 0372 01 .byte 0x1 - 988 0373 01 .byte 0x1 - 989 0374 17 .uleb128 0x17 - 990 0375 6F000000 .4byte 0x6f - 991 0379 84030000 .4byte 0x384 - 992 037d 18 .uleb128 0x18 - 993 037e AA000000 .4byte 0xaa - 994 0382 00 .byte 0 - 995 0383 00 .byte 0 - 996 0384 19 .uleb128 0x19 - 997 0385 8E020000 .4byte .LASF40 - 998 0389 01 .byte 0x1 - 999 038a 1D .byte 0x1d - 1000 038b 96030000 .4byte 0x396 - 1001 038f 01 .byte 0x1 - 1002 0390 05 .byte 0x5 - 1003 0391 03 .byte 0x3 - 1004 0392 00000000 .4byte USBFS_hidProtocol - 1005 0396 05 .uleb128 0x5 - 1006 0397 74030000 .4byte 0x374 - 1007 039b 19 .uleb128 0x19 - 1008 039c 1D030000 .4byte .LASF41 - 1009 03a0 01 .byte 0x1 - 1010 03a1 1E .byte 0x1e - 1011 03a2 AD030000 .4byte 0x3ad - 1012 03a6 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 27 - - - 1013 03a7 05 .byte 0x5 - 1014 03a8 03 .byte 0x3 - 1015 03a9 00000000 .4byte USBFS_hidIdleRate - 1016 03ad 05 .uleb128 0x5 - 1017 03ae 74030000 .4byte 0x374 - 1018 03b2 19 .uleb128 0x19 - 1019 03b3 2F030000 .4byte .LASF42 - 1020 03b7 01 .byte 0x1 - 1021 03b8 1F .byte 0x1f - 1022 03b9 C4030000 .4byte 0x3c4 - 1023 03bd 01 .byte 0x1 - 1024 03be 05 .byte 0x5 - 1025 03bf 03 .byte 0x3 - 1026 03c0 00000000 .4byte USBFS_hidIdleTimer - 1027 03c4 05 .uleb128 0x5 - 1028 03c5 74030000 .4byte 0x374 - 1029 03c9 1A .uleb128 0x1a - 1030 03ca 77020000 .4byte .LASF43 - 1031 03ce 04 .byte 0x4 - 1032 03cf 39 .byte 0x39 - 1033 03d0 D6030000 .4byte 0x3d6 - 1034 03d4 01 .byte 0x1 - 1035 03d5 01 .byte 0x1 - 1036 03d6 05 .uleb128 0x5 - 1037 03d7 74030000 .4byte 0x374 - 1038 03db 1A .uleb128 0x1a - 1039 03dc 28020000 .4byte .LASF44 - 1040 03e0 04 .byte 0x4 - 1041 03e1 40 .byte 0x40 - 1042 03e2 E8030000 .4byte 0x3e8 - 1043 03e6 01 .byte 0x1 - 1044 03e7 01 .byte 0x1 - 1045 03e8 05 .uleb128 0x5 - 1046 03e9 20010000 .4byte 0x120 - 1047 03ed 1B .uleb128 0x1b - 1048 03ee 01 .byte 0x1 - 1049 03ef C3010000 .4byte .LASF51 - 1050 03f3 04 .byte 0x4 - 1051 03f4 6D .byte 0x6d - 1052 03f5 01 .byte 0x1 - 1053 03f6 1C020000 .4byte 0x21c - 1054 03fa 01 .byte 0x1 - 1055 03fb 05040000 .4byte 0x405 - 1056 03ff 1C .uleb128 0x1c - 1057 0400 6F000000 .4byte 0x6f - 1058 0404 00 .byte 0 - 1059 0405 1D .uleb128 0x1d - 1060 0406 01 .byte 0x1 - 1061 0407 9C010000 .4byte .LASF45 - 1062 040b 04 .byte 0x4 - 1063 040c 56 .byte 0x56 - 1064 040d 01 .byte 0x1 - 1065 040e 6F000000 .4byte 0x6f - 1066 0412 01 .byte 0x1 - 1067 0413 1D .uleb128 0x1d - 1068 0414 01 .byte 0x1 - 1069 0415 49030000 .4byte .LASF46 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 28 - - - 1070 0419 04 .byte 0x4 - 1071 041a 5C .byte 0x5c - 1072 041b 01 .byte 0x1 - 1073 041c 6F000000 .4byte 0x6f - 1074 0420 01 .byte 0x1 - 1075 0421 1D .uleb128 0x1d - 1076 0422 01 .byte 0x1 - 1077 0423 64010000 .4byte .LASF47 - 1078 0427 04 .byte 0x4 - 1079 0428 63 .byte 0x63 - 1080 0429 01 .byte 0x1 - 1081 042a 6F000000 .4byte 0x6f - 1082 042e 01 .byte 0x1 - 1083 042f 00 .byte 0 - 1084 .section .debug_abbrev,"",%progbits - 1085 .Ldebug_abbrev0: - 1086 0000 01 .uleb128 0x1 - 1087 0001 11 .uleb128 0x11 - 1088 0002 01 .byte 0x1 - 1089 0003 25 .uleb128 0x25 - 1090 0004 0E .uleb128 0xe - 1091 0005 13 .uleb128 0x13 - 1092 0006 0B .uleb128 0xb - 1093 0007 03 .uleb128 0x3 - 1094 0008 0E .uleb128 0xe - 1095 0009 1B .uleb128 0x1b - 1096 000a 0E .uleb128 0xe - 1097 000b 55 .uleb128 0x55 - 1098 000c 06 .uleb128 0x6 - 1099 000d 11 .uleb128 0x11 - 1100 000e 01 .uleb128 0x1 - 1101 000f 52 .uleb128 0x52 - 1102 0010 01 .uleb128 0x1 - 1103 0011 10 .uleb128 0x10 - 1104 0012 06 .uleb128 0x6 - 1105 0013 00 .byte 0 - 1106 0014 00 .byte 0 - 1107 0015 02 .uleb128 0x2 - 1108 0016 24 .uleb128 0x24 - 1109 0017 00 .byte 0 - 1110 0018 0B .uleb128 0xb - 1111 0019 0B .uleb128 0xb - 1112 001a 3E .uleb128 0x3e - 1113 001b 0B .uleb128 0xb - 1114 001c 03 .uleb128 0x3 - 1115 001d 0E .uleb128 0xe - 1116 001e 00 .byte 0 - 1117 001f 00 .byte 0 - 1118 0020 03 .uleb128 0x3 - 1119 0021 24 .uleb128 0x24 - 1120 0022 00 .byte 0 - 1121 0023 0B .uleb128 0xb - 1122 0024 0B .uleb128 0xb - 1123 0025 3E .uleb128 0x3e - 1124 0026 0B .uleb128 0xb - 1125 0027 03 .uleb128 0x3 - 1126 0028 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 29 - - - 1127 0029 00 .byte 0 - 1128 002a 00 .byte 0 - 1129 002b 04 .uleb128 0x4 - 1130 002c 16 .uleb128 0x16 - 1131 002d 00 .byte 0 - 1132 002e 03 .uleb128 0x3 - 1133 002f 0E .uleb128 0xe - 1134 0030 3A .uleb128 0x3a - 1135 0031 0B .uleb128 0xb - 1136 0032 3B .uleb128 0x3b - 1137 0033 0B .uleb128 0xb - 1138 0034 49 .uleb128 0x49 - 1139 0035 13 .uleb128 0x13 - 1140 0036 00 .byte 0 - 1141 0037 00 .byte 0 - 1142 0038 05 .uleb128 0x5 - 1143 0039 35 .uleb128 0x35 - 1144 003a 00 .byte 0 - 1145 003b 49 .uleb128 0x49 - 1146 003c 13 .uleb128 0x13 - 1147 003d 00 .byte 0 - 1148 003e 00 .byte 0 - 1149 003f 06 .uleb128 0x6 - 1150 0040 13 .uleb128 0x13 - 1151 0041 01 .byte 0x1 - 1152 0042 0B .uleb128 0xb - 1153 0043 0B .uleb128 0xb - 1154 0044 3A .uleb128 0x3a - 1155 0045 0B .uleb128 0xb - 1156 0046 3B .uleb128 0x3b - 1157 0047 0B .uleb128 0xb - 1158 0048 01 .uleb128 0x1 - 1159 0049 13 .uleb128 0x13 - 1160 004a 00 .byte 0 - 1161 004b 00 .byte 0 - 1162 004c 07 .uleb128 0x7 - 1163 004d 0D .uleb128 0xd - 1164 004e 00 .byte 0 - 1165 004f 03 .uleb128 0x3 - 1166 0050 0E .uleb128 0xe - 1167 0051 3A .uleb128 0x3a - 1168 0052 0B .uleb128 0xb - 1169 0053 3B .uleb128 0x3b - 1170 0054 0B .uleb128 0xb - 1171 0055 49 .uleb128 0x49 - 1172 0056 13 .uleb128 0x13 - 1173 0057 38 .uleb128 0x38 - 1174 0058 0A .uleb128 0xa - 1175 0059 00 .byte 0 - 1176 005a 00 .byte 0 - 1177 005b 08 .uleb128 0x8 - 1178 005c 0F .uleb128 0xf - 1179 005d 00 .byte 0 - 1180 005e 0B .uleb128 0xb - 1181 005f 0B .uleb128 0xb - 1182 0060 49 .uleb128 0x49 - 1183 0061 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 30 - - - 1184 0062 00 .byte 0 - 1185 0063 00 .byte 0 - 1186 0064 09 .uleb128 0x9 - 1187 0065 0D .uleb128 0xd - 1188 0066 00 .byte 0 - 1189 0067 03 .uleb128 0x3 - 1190 0068 08 .uleb128 0x8 - 1191 0069 3A .uleb128 0x3a - 1192 006a 0B .uleb128 0xb - 1193 006b 3B .uleb128 0x3b - 1194 006c 0B .uleb128 0xb - 1195 006d 49 .uleb128 0x49 - 1196 006e 13 .uleb128 0x13 - 1197 006f 38 .uleb128 0x38 - 1198 0070 0A .uleb128 0xa - 1199 0071 00 .byte 0 - 1200 0072 00 .byte 0 - 1201 0073 0A .uleb128 0xa - 1202 0074 26 .uleb128 0x26 - 1203 0075 00 .byte 0 - 1204 0076 00 .byte 0 - 1205 0077 00 .byte 0 - 1206 0078 0B .uleb128 0xb - 1207 0079 2E .uleb128 0x2e - 1208 007a 01 .byte 0x1 - 1209 007b 3F .uleb128 0x3f - 1210 007c 0C .uleb128 0xc - 1211 007d 03 .uleb128 0x3 - 1212 007e 0E .uleb128 0xe - 1213 007f 3A .uleb128 0x3a - 1214 0080 0B .uleb128 0xb - 1215 0081 3B .uleb128 0x3b - 1216 0082 0B .uleb128 0xb - 1217 0083 27 .uleb128 0x27 - 1218 0084 0C .uleb128 0xc - 1219 0085 49 .uleb128 0x49 - 1220 0086 13 .uleb128 0x13 - 1221 0087 11 .uleb128 0x11 - 1222 0088 01 .uleb128 0x1 - 1223 0089 12 .uleb128 0x12 - 1224 008a 01 .uleb128 0x1 - 1225 008b 40 .uleb128 0x40 - 1226 008c 0A .uleb128 0xa - 1227 008d 9742 .uleb128 0x2117 - 1228 008f 0C .uleb128 0xc - 1229 0090 01 .uleb128 0x1 - 1230 0091 13 .uleb128 0x13 - 1231 0092 00 .byte 0 - 1232 0093 00 .byte 0 - 1233 0094 0C .uleb128 0xc - 1234 0095 05 .uleb128 0x5 - 1235 0096 00 .byte 0 - 1236 0097 03 .uleb128 0x3 - 1237 0098 0E .uleb128 0xe - 1238 0099 3A .uleb128 0x3a - 1239 009a 0B .uleb128 0xb - 1240 009b 3B .uleb128 0x3b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 31 - - - 1241 009c 0B .uleb128 0xb - 1242 009d 49 .uleb128 0x49 - 1243 009e 13 .uleb128 0x13 - 1244 009f 02 .uleb128 0x2 - 1245 00a0 06 .uleb128 0x6 - 1246 00a1 00 .byte 0 - 1247 00a2 00 .byte 0 - 1248 00a3 0D .uleb128 0xd - 1249 00a4 34 .uleb128 0x34 - 1250 00a5 00 .byte 0 - 1251 00a6 03 .uleb128 0x3 - 1252 00a7 0E .uleb128 0xe - 1253 00a8 3A .uleb128 0x3a - 1254 00a9 0B .uleb128 0xb - 1255 00aa 3B .uleb128 0x3b - 1256 00ab 0B .uleb128 0xb - 1257 00ac 49 .uleb128 0x49 - 1258 00ad 13 .uleb128 0x13 - 1259 00ae 02 .uleb128 0x2 - 1260 00af 06 .uleb128 0x6 - 1261 00b0 00 .byte 0 - 1262 00b1 00 .byte 0 - 1263 00b2 0E .uleb128 0xe - 1264 00b3 2E .uleb128 0x2e - 1265 00b4 01 .byte 0x1 - 1266 00b5 3F .uleb128 0x3f - 1267 00b6 0C .uleb128 0xc - 1268 00b7 03 .uleb128 0x3 - 1269 00b8 0E .uleb128 0xe - 1270 00b9 3A .uleb128 0x3a - 1271 00ba 0B .uleb128 0xb - 1272 00bb 3B .uleb128 0x3b - 1273 00bc 05 .uleb128 0x5 - 1274 00bd 27 .uleb128 0x27 - 1275 00be 0C .uleb128 0xc - 1276 00bf 11 .uleb128 0x11 - 1277 00c0 01 .uleb128 0x1 - 1278 00c1 12 .uleb128 0x12 - 1279 00c2 01 .uleb128 0x1 - 1280 00c3 40 .uleb128 0x40 - 1281 00c4 06 .uleb128 0x6 - 1282 00c5 9742 .uleb128 0x2117 - 1283 00c7 0C .uleb128 0xc - 1284 00c8 01 .uleb128 0x1 - 1285 00c9 13 .uleb128 0x13 - 1286 00ca 00 .byte 0 - 1287 00cb 00 .byte 0 - 1288 00cc 0F .uleb128 0xf - 1289 00cd 34 .uleb128 0x34 - 1290 00ce 00 .byte 0 - 1291 00cf 03 .uleb128 0x3 - 1292 00d0 0E .uleb128 0xe - 1293 00d1 3A .uleb128 0x3a - 1294 00d2 0B .uleb128 0xb - 1295 00d3 3B .uleb128 0x3b - 1296 00d4 05 .uleb128 0x5 - 1297 00d5 49 .uleb128 0x49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 32 - - - 1298 00d6 13 .uleb128 0x13 - 1299 00d7 02 .uleb128 0x2 - 1300 00d8 06 .uleb128 0x6 - 1301 00d9 00 .byte 0 - 1302 00da 00 .byte 0 - 1303 00db 10 .uleb128 0x10 - 1304 00dc 34 .uleb128 0x34 - 1305 00dd 00 .byte 0 - 1306 00de 03 .uleb128 0x3 - 1307 00df 0E .uleb128 0xe - 1308 00e0 3A .uleb128 0x3a - 1309 00e1 0B .uleb128 0xb - 1310 00e2 3B .uleb128 0x3b - 1311 00e3 05 .uleb128 0x5 - 1312 00e4 49 .uleb128 0x49 - 1313 00e5 13 .uleb128 0x13 - 1314 00e6 02 .uleb128 0x2 - 1315 00e7 0A .uleb128 0xa - 1316 00e8 00 .byte 0 - 1317 00e9 00 .byte 0 - 1318 00ea 11 .uleb128 0x11 - 1319 00eb 898201 .uleb128 0x4109 - 1320 00ee 00 .byte 0 - 1321 00ef 11 .uleb128 0x11 - 1322 00f0 01 .uleb128 0x1 - 1323 00f1 31 .uleb128 0x31 - 1324 00f2 13 .uleb128 0x13 - 1325 00f3 00 .byte 0 - 1326 00f4 00 .byte 0 - 1327 00f5 12 .uleb128 0x12 - 1328 00f6 26 .uleb128 0x26 - 1329 00f7 00 .byte 0 - 1330 00f8 49 .uleb128 0x49 - 1331 00f9 13 .uleb128 0x13 - 1332 00fa 00 .byte 0 - 1333 00fb 00 .byte 0 - 1334 00fc 13 .uleb128 0x13 - 1335 00fd 34 .uleb128 0x34 - 1336 00fe 00 .byte 0 - 1337 00ff 03 .uleb128 0x3 - 1338 0100 08 .uleb128 0x8 - 1339 0101 3A .uleb128 0x3a - 1340 0102 0B .uleb128 0xb - 1341 0103 3B .uleb128 0x3b - 1342 0104 05 .uleb128 0x5 - 1343 0105 49 .uleb128 0x49 - 1344 0106 13 .uleb128 0x13 - 1345 0107 02 .uleb128 0x2 - 1346 0108 06 .uleb128 0x6 - 1347 0109 00 .byte 0 - 1348 010a 00 .byte 0 - 1349 010b 14 .uleb128 0x14 - 1350 010c 2E .uleb128 0x2e - 1351 010d 01 .byte 0x1 - 1352 010e 3F .uleb128 0x3f - 1353 010f 0C .uleb128 0xc - 1354 0110 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 33 - - - 1355 0111 0E .uleb128 0xe - 1356 0112 3A .uleb128 0x3a - 1357 0113 0B .uleb128 0xb - 1358 0114 3B .uleb128 0x3b - 1359 0115 0B .uleb128 0xb - 1360 0116 27 .uleb128 0x27 - 1361 0117 0C .uleb128 0xc - 1362 0118 49 .uleb128 0x49 - 1363 0119 13 .uleb128 0x13 - 1364 011a 11 .uleb128 0x11 - 1365 011b 01 .uleb128 0x1 - 1366 011c 12 .uleb128 0x12 - 1367 011d 01 .uleb128 0x1 - 1368 011e 40 .uleb128 0x40 - 1369 011f 06 .uleb128 0x6 - 1370 0120 9742 .uleb128 0x2117 - 1371 0122 0C .uleb128 0xc - 1372 0123 01 .uleb128 0x1 - 1373 0124 13 .uleb128 0x13 - 1374 0125 00 .byte 0 - 1375 0126 00 .byte 0 - 1376 0127 15 .uleb128 0x15 - 1377 0128 898201 .uleb128 0x4109 - 1378 012b 00 .byte 0 - 1379 012c 11 .uleb128 0x11 - 1380 012d 01 .uleb128 0x1 - 1381 012e 9542 .uleb128 0x2115 - 1382 0130 0C .uleb128 0xc - 1383 0131 31 .uleb128 0x31 - 1384 0132 13 .uleb128 0x13 - 1385 0133 00 .byte 0 - 1386 0134 00 .byte 0 - 1387 0135 16 .uleb128 0x16 - 1388 0136 34 .uleb128 0x34 - 1389 0137 00 .byte 0 - 1390 0138 03 .uleb128 0x3 - 1391 0139 0E .uleb128 0xe - 1392 013a 3A .uleb128 0x3a - 1393 013b 0B .uleb128 0xb - 1394 013c 3B .uleb128 0x3b - 1395 013d 05 .uleb128 0x5 - 1396 013e 49 .uleb128 0x49 - 1397 013f 13 .uleb128 0x13 - 1398 0140 3F .uleb128 0x3f - 1399 0141 0C .uleb128 0xc - 1400 0142 3C .uleb128 0x3c - 1401 0143 0C .uleb128 0xc - 1402 0144 00 .byte 0 - 1403 0145 00 .byte 0 - 1404 0146 17 .uleb128 0x17 - 1405 0147 01 .uleb128 0x1 - 1406 0148 01 .byte 0x1 - 1407 0149 49 .uleb128 0x49 - 1408 014a 13 .uleb128 0x13 - 1409 014b 01 .uleb128 0x1 - 1410 014c 13 .uleb128 0x13 - 1411 014d 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 34 - - - 1412 014e 00 .byte 0 - 1413 014f 18 .uleb128 0x18 - 1414 0150 21 .uleb128 0x21 - 1415 0151 00 .byte 0 - 1416 0152 49 .uleb128 0x49 - 1417 0153 13 .uleb128 0x13 - 1418 0154 2F .uleb128 0x2f - 1419 0155 0B .uleb128 0xb - 1420 0156 00 .byte 0 - 1421 0157 00 .byte 0 - 1422 0158 19 .uleb128 0x19 - 1423 0159 34 .uleb128 0x34 - 1424 015a 00 .byte 0 - 1425 015b 03 .uleb128 0x3 - 1426 015c 0E .uleb128 0xe - 1427 015d 3A .uleb128 0x3a - 1428 015e 0B .uleb128 0xb - 1429 015f 3B .uleb128 0x3b - 1430 0160 0B .uleb128 0xb - 1431 0161 49 .uleb128 0x49 - 1432 0162 13 .uleb128 0x13 - 1433 0163 3F .uleb128 0x3f - 1434 0164 0C .uleb128 0xc - 1435 0165 02 .uleb128 0x2 - 1436 0166 0A .uleb128 0xa - 1437 0167 00 .byte 0 - 1438 0168 00 .byte 0 - 1439 0169 1A .uleb128 0x1a - 1440 016a 34 .uleb128 0x34 - 1441 016b 00 .byte 0 - 1442 016c 03 .uleb128 0x3 - 1443 016d 0E .uleb128 0xe - 1444 016e 3A .uleb128 0x3a - 1445 016f 0B .uleb128 0xb - 1446 0170 3B .uleb128 0x3b - 1447 0171 0B .uleb128 0xb - 1448 0172 49 .uleb128 0x49 - 1449 0173 13 .uleb128 0x13 - 1450 0174 3F .uleb128 0x3f - 1451 0175 0C .uleb128 0xc - 1452 0176 3C .uleb128 0x3c - 1453 0177 0C .uleb128 0xc - 1454 0178 00 .byte 0 - 1455 0179 00 .byte 0 - 1456 017a 1B .uleb128 0x1b - 1457 017b 2E .uleb128 0x2e - 1458 017c 01 .byte 0x1 - 1459 017d 3F .uleb128 0x3f - 1460 017e 0C .uleb128 0xc - 1461 017f 03 .uleb128 0x3 - 1462 0180 0E .uleb128 0xe - 1463 0181 3A .uleb128 0x3a - 1464 0182 0B .uleb128 0xb - 1465 0183 3B .uleb128 0x3b - 1466 0184 0B .uleb128 0xb - 1467 0185 27 .uleb128 0x27 - 1468 0186 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 35 - - - 1469 0187 49 .uleb128 0x49 - 1470 0188 13 .uleb128 0x13 - 1471 0189 3C .uleb128 0x3c - 1472 018a 0C .uleb128 0xc - 1473 018b 01 .uleb128 0x1 - 1474 018c 13 .uleb128 0x13 - 1475 018d 00 .byte 0 - 1476 018e 00 .byte 0 - 1477 018f 1C .uleb128 0x1c - 1478 0190 05 .uleb128 0x5 - 1479 0191 00 .byte 0 - 1480 0192 49 .uleb128 0x49 - 1481 0193 13 .uleb128 0x13 - 1482 0194 00 .byte 0 - 1483 0195 00 .byte 0 - 1484 0196 1D .uleb128 0x1d - 1485 0197 2E .uleb128 0x2e - 1486 0198 00 .byte 0 - 1487 0199 3F .uleb128 0x3f - 1488 019a 0C .uleb128 0xc - 1489 019b 03 .uleb128 0x3 - 1490 019c 0E .uleb128 0xe - 1491 019d 3A .uleb128 0x3a - 1492 019e 0B .uleb128 0xb - 1493 019f 3B .uleb128 0x3b - 1494 01a0 0B .uleb128 0xb - 1495 01a1 27 .uleb128 0x27 - 1496 01a2 0C .uleb128 0xc - 1497 01a3 49 .uleb128 0x49 - 1498 01a4 13 .uleb128 0x13 - 1499 01a5 3C .uleb128 0x3c - 1500 01a6 0C .uleb128 0xc - 1501 01a7 00 .byte 0 - 1502 01a8 00 .byte 0 - 1503 01a9 00 .byte 0 - 1504 .section .debug_loc,"",%progbits - 1505 .Ldebug_loc0: - 1506 .LLST0: - 1507 0000 00000000 .4byte .LVL0 - 1508 0004 16000000 .4byte .LVL2 - 1509 0008 0100 .2byte 0x1 - 1510 000a 50 .byte 0x50 - 1511 000b 16000000 .4byte .LVL2 - 1512 000f 18000000 .4byte .LVL3 - 1513 0013 0400 .2byte 0x4 - 1514 0015 F3 .byte 0xf3 - 1515 0016 01 .uleb128 0x1 - 1516 0017 50 .byte 0x50 - 1517 0018 9F .byte 0x9f - 1518 0019 18000000 .4byte .LVL3 - 1519 001d 1E000000 .4byte .LVL5 - 1520 0021 0100 .2byte 0x1 - 1521 0023 50 .byte 0x50 - 1522 0024 1E000000 .4byte .LVL5 - 1523 0028 20000000 .4byte .LVL6 - 1524 002c 0400 .2byte 0x4 - 1525 002e F3 .byte 0xf3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 36 - - - 1526 002f 01 .uleb128 0x1 - 1527 0030 50 .byte 0x50 - 1528 0031 9F .byte 0x9f - 1529 0032 20000000 .4byte .LVL6 - 1530 0036 22000000 .4byte .LVL7 - 1531 003a 0100 .2byte 0x1 - 1532 003c 50 .byte 0x50 - 1533 003d 22000000 .4byte .LVL7 - 1534 0041 2C000000 .4byte .LFE0 - 1535 0045 0400 .2byte 0x4 - 1536 0047 F3 .byte 0xf3 - 1537 0048 01 .uleb128 0x1 - 1538 0049 50 .byte 0x50 - 1539 004a 9F .byte 0x9f - 1540 004b 00000000 .4byte 0 - 1541 004f 00000000 .4byte 0 - 1542 .LLST1: - 1543 0053 00000000 .4byte .LVL0 - 1544 0057 14000000 .4byte .LVL1 - 1545 005b 0200 .2byte 0x2 - 1546 005d 30 .byte 0x30 - 1547 005e 9F .byte 0x9f - 1548 005f 14000000 .4byte .LVL1 - 1549 0063 18000000 .4byte .LVL3 - 1550 0067 0200 .2byte 0x2 - 1551 0069 32 .byte 0x32 - 1552 006a 9F .byte 0x9f - 1553 006b 18000000 .4byte .LVL3 - 1554 006f 1C000000 .4byte .LVL4 - 1555 0073 0200 .2byte 0x2 - 1556 0075 30 .byte 0x30 - 1557 0076 9F .byte 0x9f - 1558 0077 1C000000 .4byte .LVL4 - 1559 007b 20000000 .4byte .LVL6 - 1560 007f 0200 .2byte 0x2 - 1561 0081 31 .byte 0x31 - 1562 0082 9F .byte 0x9f - 1563 0083 20000000 .4byte .LVL6 - 1564 0087 22000000 .4byte .LVL7 - 1565 008b 0200 .2byte 0x2 - 1566 008d 30 .byte 0x30 - 1567 008e 9F .byte 0x9f - 1568 008f 22000000 .4byte .LVL7 - 1569 0093 2C000000 .4byte .LFE0 - 1570 0097 0100 .2byte 0x1 - 1571 0099 50 .byte 0x50 - 1572 009a 00000000 .4byte 0 - 1573 009e 00000000 .4byte 0 - 1574 .LLST2: - 1575 00a2 00000000 .4byte .LVL8 - 1576 00a6 04000000 .4byte .LVL9 - 1577 00aa 0100 .2byte 0x1 - 1578 00ac 50 .byte 0x50 - 1579 00ad 04000000 .4byte .LVL9 - 1580 00b1 0C000000 .4byte .LFE1 - 1581 00b5 0400 .2byte 0x4 - 1582 00b7 F3 .byte 0xf3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 37 - - - 1583 00b8 01 .uleb128 0x1 - 1584 00b9 50 .byte 0x50 - 1585 00ba 9F .byte 0x9f - 1586 00bb 00000000 .4byte 0 - 1587 00bf 00000000 .4byte 0 - 1588 .LLST3: - 1589 00c3 00000000 .4byte .LFB3 - 1590 00c7 02000000 .4byte .LCFI0 - 1591 00cb 0200 .2byte 0x2 - 1592 00cd 7D .byte 0x7d - 1593 00ce 00 .sleb128 0 - 1594 00cf 02000000 .4byte .LCFI0 - 1595 00d3 40000000 .4byte .LFE3 - 1596 00d7 0200 .2byte 0x2 - 1597 00d9 7D .byte 0x7d - 1598 00da 08 .sleb128 8 - 1599 00db 00000000 .4byte 0 - 1600 00df 00000000 .4byte 0 - 1601 .LLST4: - 1602 00e3 0E000000 .4byte .LVL10 - 1603 00e7 18000000 .4byte .LVL12 - 1604 00eb 0100 .2byte 0x1 - 1605 00ed 50 .byte 0x50 - 1606 00ee 1A000000 .4byte .LVL13 - 1607 00f2 20000000 .4byte .LVL15 - 1608 00f6 0100 .2byte 0x1 - 1609 00f8 52 .byte 0x52 - 1610 00f9 20000000 .4byte .LVL15 - 1611 00fd 26000000 .4byte .LVL16 - 1612 0101 0600 .2byte 0x6 - 1613 0103 70 .byte 0x70 - 1614 0104 04 .sleb128 4 - 1615 0105 06 .byte 0x6 - 1616 0106 23 .byte 0x23 - 1617 0107 20 .uleb128 0x20 - 1618 0108 9F .byte 0x9f - 1619 0109 26000000 .4byte .LVL16 - 1620 010d 40000000 .4byte .LFE3 - 1621 0111 0300 .2byte 0x3 - 1622 0113 72 .byte 0x72 - 1623 0114 20 .sleb128 32 - 1624 0115 9F .byte 0x9f - 1625 0116 00000000 .4byte 0 - 1626 011a 00000000 .4byte 0 - 1627 .LLST5: - 1628 011e 14000000 .4byte .LVL11 - 1629 0122 1C000000 .4byte .LVL14 - 1630 0126 0100 .2byte 0x1 - 1631 0128 53 .byte 0x53 - 1632 0129 00000000 .4byte 0 - 1633 012d 00000000 .4byte 0 - 1634 .LLST6: - 1635 0131 00000000 .4byte .LFB4 - 1636 0135 02000000 .4byte .LCFI1 - 1637 0139 0200 .2byte 0x2 - 1638 013b 7D .byte 0x7d - 1639 013c 00 .sleb128 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 38 - - - 1640 013d 02000000 .4byte .LCFI1 - 1641 0141 48000000 .4byte .LFE4 - 1642 0145 0200 .2byte 0x2 - 1643 0147 7D .byte 0x7d - 1644 0148 08 .sleb128 8 - 1645 0149 00000000 .4byte 0 - 1646 014d 00000000 .4byte 0 - 1647 .LLST7: - 1648 0151 0E000000 .4byte .LVL17 - 1649 0155 18000000 .4byte .LVL19 - 1650 0159 0100 .2byte 0x1 - 1651 015b 50 .byte 0x50 - 1652 015c 1A000000 .4byte .LVL20 - 1653 0160 20000000 .4byte .LVL22 - 1654 0164 0100 .2byte 0x1 - 1655 0166 52 .byte 0x52 - 1656 0167 20000000 .4byte .LVL22 - 1657 016b 2C000000 .4byte .LVL24 - 1658 016f 0600 .2byte 0x6 - 1659 0171 70 .byte 0x70 - 1660 0172 04 .sleb128 4 - 1661 0173 06 .byte 0x6 - 1662 0174 23 .byte 0x23 - 1663 0175 18 .uleb128 0x18 - 1664 0176 9F .byte 0x9f - 1665 0177 00000000 .4byte 0 - 1666 017b 00000000 .4byte 0 - 1667 .LLST8: - 1668 017f 24000000 .4byte .LVL23 - 1669 0183 2C000000 .4byte .LVL24 - 1670 0187 0100 .2byte 0x1 - 1671 0189 53 .byte 0x53 - 1672 018a 2C000000 .4byte .LVL24 - 1673 018e 48000000 .4byte .LFE4 - 1674 0192 0300 .2byte 0x3 - 1675 0194 73 .byte 0x73 - 1676 0195 7E .sleb128 -2 - 1677 0196 9F .byte 0x9f - 1678 0197 00000000 .4byte 0 - 1679 019b 00000000 .4byte 0 - 1680 .LLST9: - 1681 019f 14000000 .4byte .LVL18 - 1682 01a3 1C000000 .4byte .LVL21 - 1683 01a7 0100 .2byte 0x1 - 1684 01a9 53 .byte 0x53 - 1685 01aa 00000000 .4byte 0 - 1686 01ae 00000000 .4byte 0 - 1687 .LLST10: - 1688 01b2 00000000 .4byte .LFB5 - 1689 01b6 02000000 .4byte .LCFI2 - 1690 01ba 0200 .2byte 0x2 - 1691 01bc 7D .byte 0x7d - 1692 01bd 00 .sleb128 0 - 1693 01be 02000000 .4byte .LCFI2 - 1694 01c2 74000000 .4byte .LFE5 - 1695 01c6 0200 .2byte 0x2 - 1696 01c8 7D .byte 0x7d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 39 - - - 1697 01c9 08 .sleb128 8 - 1698 01ca 00000000 .4byte 0 - 1699 01ce 00000000 .4byte 0 - 1700 .LLST11: - 1701 01d2 14000000 .4byte .LVL25 - 1702 01d6 20000000 .4byte .LVL28 - 1703 01da 0100 .2byte 0x1 - 1704 01dc 50 .byte 0x50 - 1705 01dd 22000000 .4byte .LVL29 - 1706 01e1 3C000000 .4byte .LVL34 - 1707 01e5 0100 .2byte 0x1 - 1708 01e7 51 .byte 0x51 - 1709 01e8 3C000000 .4byte .LVL34 - 1710 01ec 50000000 .4byte .LVL39 - 1711 01f0 0100 .2byte 0x1 - 1712 01f2 50 .byte 0x50 - 1713 01f3 00000000 .4byte 0 - 1714 01f7 00000000 .4byte 0 - 1715 .LLST12: - 1716 01fb 4C000000 .4byte .LVL37 - 1717 01ff 4E000000 .4byte .LVL38 - 1718 0203 0100 .2byte 0x1 - 1719 0205 51 .byte 0x51 - 1720 0206 4E000000 .4byte .LVL38 - 1721 020a 5A000000 .4byte .LVL40 - 1722 020e 0100 .2byte 0x1 - 1723 0210 53 .byte 0x53 - 1724 0211 00000000 .4byte 0 - 1725 0215 00000000 .4byte 0 - 1726 .LLST13: - 1727 0219 1C000000 .4byte .LVL27 - 1728 021d 26000000 .4byte .LVL30 - 1729 0221 0100 .2byte 0x1 - 1730 0223 52 .byte 0x52 - 1731 0224 00000000 .4byte 0 - 1732 0228 00000000 .4byte 0 - 1733 .LLST14: - 1734 022c 1A000000 .4byte .LVL26 - 1735 0230 28000000 .4byte .LVL31 - 1736 0234 0100 .2byte 0x1 - 1737 0236 53 .byte 0x53 - 1738 0237 28000000 .4byte .LVL31 - 1739 023b 3E000000 .4byte .LVL35 - 1740 023f 0300 .2byte 0x3 - 1741 0241 73 .byte 0x73 - 1742 0242 01 .sleb128 1 - 1743 0243 9F .byte 0x9f - 1744 0244 3E000000 .4byte .LVL35 - 1745 0248 4A000000 .4byte .LVL36 - 1746 024c 0100 .2byte 0x1 - 1747 024e 52 .byte 0x52 - 1748 024f 00000000 .4byte 0 - 1749 0253 00000000 .4byte 0 - 1750 .LLST15: - 1751 0257 00000000 .4byte .LFB2 - 1752 025b 02000000 .4byte .LCFI3 - 1753 025f 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 40 - - - 1754 0261 7D .byte 0x7d - 1755 0262 00 .sleb128 0 - 1756 0263 02000000 .4byte .LCFI3 - 1757 0267 10010000 .4byte .LFE2 - 1758 026b 0200 .2byte 0x2 - 1759 026d 7D .byte 0x7d - 1760 026e 08 .sleb128 8 - 1761 026f 00000000 .4byte 0 - 1762 0273 00000000 .4byte 0 - 1763 .LLST16: - 1764 0277 00000000 .4byte .LVL41 - 1765 027b E8000000 .4byte .LVL58 - 1766 027f 0200 .2byte 0x2 - 1767 0281 30 .byte 0x30 - 1768 0282 9F .byte 0x9f - 1769 0283 00000000 .4byte 0 - 1770 0287 00000000 .4byte 0 - 1771 .LLST17: - 1772 028b 08000000 .4byte .LVL42 - 1773 028f 24000000 .4byte .LVL43 - 1774 0293 0100 .2byte 0x1 - 1775 0295 50 .byte 0x50 - 1776 0296 3C000000 .4byte .LVL46 - 1777 029a 3F000000 .4byte .LVL47-1 - 1778 029e 0100 .2byte 0x1 - 1779 02a0 50 .byte 0x50 - 1780 02a1 4C000000 .4byte .LVL48 - 1781 02a5 54000000 .4byte .LVL49 - 1782 02a9 0100 .2byte 0x1 - 1783 02ab 50 .byte 0x50 - 1784 02ac 6A000000 .4byte .LVL50 - 1785 02b0 70000000 .4byte .LVL51 - 1786 02b4 0100 .2byte 0x1 - 1787 02b6 50 .byte 0x50 - 1788 02b7 78000000 .4byte .LVL52 - 1789 02bb 95000000 .4byte .LVL53-1 - 1790 02bf 0100 .2byte 0x1 - 1791 02c1 50 .byte 0x50 - 1792 02c2 A8000000 .4byte .LVL54 - 1793 02c6 AC000000 .4byte .LVL55 - 1794 02ca 0100 .2byte 0x1 - 1795 02cc 50 .byte 0x50 - 1796 02cd D8000000 .4byte .LVL56 - 1797 02d1 DC000000 .4byte .LVL57 - 1798 02d5 0100 .2byte 0x1 - 1799 02d7 50 .byte 0x50 - 1800 02d8 00000000 .4byte 0 - 1801 02dc 00000000 .4byte 0 - 1802 .section .debug_aranges,"",%progbits - 1803 0000 44000000 .4byte 0x44 - 1804 0004 0200 .2byte 0x2 - 1805 0006 00000000 .4byte .Ldebug_info0 - 1806 000a 04 .byte 0x4 - 1807 000b 00 .byte 0 - 1808 000c 0000 .2byte 0 - 1809 000e 0000 .2byte 0 - 1810 0010 00000000 .4byte .LFB0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 41 - - - 1811 0014 2C000000 .4byte .LFE0-.LFB0 - 1812 0018 00000000 .4byte .LFB1 - 1813 001c 0C000000 .4byte .LFE1-.LFB1 - 1814 0020 00000000 .4byte .LFB3 - 1815 0024 40000000 .4byte .LFE3-.LFB3 - 1816 0028 00000000 .4byte .LFB4 - 1817 002c 48000000 .4byte .LFE4-.LFB4 - 1818 0030 00000000 .4byte .LFB5 - 1819 0034 74000000 .4byte .LFE5-.LFB5 - 1820 0038 00000000 .4byte .LFB2 - 1821 003c 10010000 .4byte .LFE2-.LFB2 - 1822 0040 00000000 .4byte 0 - 1823 0044 00000000 .4byte 0 - 1824 .section .debug_ranges,"",%progbits - 1825 .Ldebug_ranges0: - 1826 0000 00000000 .4byte .LFB0 - 1827 0004 2C000000 .4byte .LFE0 - 1828 0008 00000000 .4byte .LFB1 - 1829 000c 0C000000 .4byte .LFE1 - 1830 0010 00000000 .4byte .LFB3 - 1831 0014 40000000 .4byte .LFE3 - 1832 0018 00000000 .4byte .LFB4 - 1833 001c 48000000 .4byte .LFE4 - 1834 0020 00000000 .4byte .LFB5 - 1835 0024 74000000 .4byte .LFE5 - 1836 0028 00000000 .4byte .LFB2 - 1837 002c 10010000 .4byte .LFE2 - 1838 0030 00000000 .4byte 0 - 1839 0034 00000000 .4byte 0 - 1840 .section .debug_line,"",%progbits - 1841 .Ldebug_line0: - 1842 0000 6E010000 .section .debug_str,"MS",%progbits,1 - 1842 02006200 - 1842 00000201 - 1842 FB0E0D00 - 1842 01010101 - 1843 .LASF21: - 1844 0000 70537461 .ascii "pStatusBlock\000" - 1844 74757342 - 1844 6C6F636B - 1844 00 - 1845 .LASF49: - 1846 000d 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_hid.c\000" - 1846 6E657261 - 1846 7465645F - 1846 536F7572 - 1846 63655C50 - 1847 .LASF28: - 1848 0032 73746174 .ascii "stat\000" - 1848 00 - 1849 .LASF37: - 1850 0037 72657175 .ascii "requestHandled\000" - 1850 65737448 - 1850 616E646C - 1850 656400 - 1851 .LASF19: - 1852 0046 636F756E .ascii "count\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 42 - - - 1852 7400 - 1853 .LASF33: - 1854 004c 55534246 .ascii "USBFS_FindReportDescriptor\000" - 1854 535F4669 - 1854 6E645265 - 1854 706F7274 - 1854 44657363 - 1855 .LASF3: - 1856 0067 73686F72 .ascii "short unsigned int\000" - 1856 7420756E - 1856 7369676E - 1856 65642069 - 1856 6E7400 - 1857 .LASF31: - 1858 007a 696E7465 .ascii "interfaceN\000" - 1858 72666163 - 1858 654E00 - 1859 .LASF16: - 1860 0085 73746174 .ascii "status\000" - 1860 757300 - 1861 .LASF20: - 1862 008c 70446174 .ascii "pData\000" - 1862 6100 - 1863 .LASF32: - 1864 0092 55534246 .ascii "USBFS_FindHidClassDecriptor\000" - 1864 535F4669 - 1864 6E644869 - 1864 64436C61 - 1864 73734465 - 1865 .LASF22: - 1866 00ae 545F5553 .ascii "T_USBFS_TD\000" - 1866 4246535F - 1866 544400 - 1867 .LASF11: - 1868 00b9 666C6F61 .ascii "float\000" - 1868 7400 - 1869 .LASF35: - 1870 00bf 7265706F .ascii "reportType\000" - 1870 72745479 - 1870 706500 - 1871 .LASF39: - 1872 00ca 55534246 .ascii "USBFS_configuration\000" - 1872 535F636F - 1872 6E666967 - 1872 75726174 - 1872 696F6E00 - 1873 .LASF1: - 1874 00de 756E7369 .ascii "unsigned char\000" - 1874 676E6564 - 1874 20636861 - 1874 7200 - 1875 .LASF14: - 1876 00ec 72656738 .ascii "reg8\000" - 1876 00 - 1877 .LASF18: - 1878 00f1 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" - 1878 4246535F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 43 - - - 1878 58464552 - 1878 5F535441 - 1878 5455535F - 1879 .LASF5: - 1880 010b 6C6F6E67 .ascii "long unsigned int\000" - 1880 20756E73 - 1880 69676E65 - 1880 6420696E - 1880 7400 - 1881 .LASF50: - 1882 011d 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 1882 43534932 - 1882 53445C73 - 1882 6F667477 - 1882 6172655C - 1883 014c 6E00 .ascii "n\000" - 1884 .LASF9: - 1885 014e 75696E74 .ascii "uint8\000" - 1885 3800 - 1886 .LASF38: - 1887 0154 696E7465 .ascii "interfaceNumber\000" - 1887 72666163 - 1887 654E756D - 1887 62657200 - 1888 .LASF47: - 1889 0164 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" - 1889 535F496E - 1889 69744E6F - 1889 44617461 - 1889 436F6E74 - 1890 .LASF34: - 1891 0184 55534246 .ascii "USBFS_FindReport\000" - 1891 535F4669 - 1891 6E645265 - 1891 706F7274 - 1891 00 - 1892 .LASF12: - 1893 0195 646F7562 .ascii "double\000" - 1893 6C6500 - 1894 .LASF45: - 1895 019c 55534246 .ascii "USBFS_InitControlRead\000" - 1895 535F496E - 1895 6974436F - 1895 6E74726F - 1895 6C526561 - 1896 .LASF2: - 1897 01b2 73686F72 .ascii "short int\000" - 1897 7420696E - 1897 7400 - 1898 .LASF10: - 1899 01bc 75696E74 .ascii "uint16\000" - 1899 313600 - 1900 .LASF51: - 1901 01c3 55534246 .ascii "USBFS_GetConfigTablePtr\000" - 1901 535F4765 - 1901 74436F6E - 1901 66696754 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 44 - - - 1901 61626C65 - 1902 .LASF30: - 1903 01db 70446573 .ascii "pDescr\000" - 1903 637200 - 1904 .LASF8: - 1905 01e2 756E7369 .ascii "unsigned int\000" - 1905 676E6564 - 1905 20696E74 - 1905 00 - 1906 .LASF36: - 1907 01ef 55534246 .ascii "USBFS_DispatchHIDClassRqst\000" - 1907 535F4469 - 1907 73706174 - 1907 63684849 - 1907 44436C61 - 1908 .LASF7: - 1909 020a 6C6F6E67 .ascii "long long unsigned int\000" - 1909 206C6F6E - 1909 6720756E - 1909 7369676E - 1909 65642069 - 1910 .LASF23: - 1911 0221 705F6C69 .ascii "p_list\000" - 1911 737400 - 1912 .LASF44: - 1913 0228 55534246 .ascii "USBFS_currentTD\000" - 1913 535F6375 - 1913 7272656E - 1913 74544400 - 1914 .LASF26: - 1915 0238 55534246 .ascii "USBFS_GetProtocol\000" - 1915 535F4765 - 1915 7450726F - 1915 746F636F - 1915 6C00 - 1916 .LASF15: - 1917 024a 73697A65 .ascii "sizetype\000" - 1917 74797065 - 1917 00 - 1918 .LASF6: - 1919 0253 6C6F6E67 .ascii "long long int\000" - 1919 206C6F6E - 1919 6720696E - 1919 7400 - 1920 .LASF24: - 1921 0261 545F5553 .ascii "T_USBFS_LUT\000" - 1921 4246535F - 1921 4C555400 - 1922 .LASF13: - 1923 026d 63686172 .ascii "char\000" - 1923 00 - 1924 .LASF29: - 1925 0272 70546D70 .ascii "pTmp\000" - 1925 00 - 1926 .LASF43: - 1927 0277 55534246 .ascii "USBFS_interfaceSetting\000" - 1927 535F696E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 45 - - - 1927 74657266 - 1927 61636553 - 1927 65747469 - 1928 .LASF40: - 1929 028e 55534246 .ascii "USBFS_hidProtocol\000" - 1929 535F6869 - 1929 6450726F - 1929 746F636F - 1929 6C00 - 1930 .LASF25: - 1931 02a0 55534246 .ascii "USBFS_UpdateHIDTimer\000" - 1931 535F5570 - 1931 64617465 - 1931 48494454 - 1931 696D6572 - 1932 .LASF48: - 1933 02b5 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 1933 4320342E - 1933 372E3320 - 1933 32303133 - 1933 30333132 - 1934 02e8 616E6368 .ascii "anch revision 196615]\000" - 1934 20726576 - 1934 6973696F - 1934 6E203139 - 1934 36363135 - 1935 .LASF27: - 1936 02fe 696E7465 .ascii "interface\000" - 1936 72666163 - 1936 6500 - 1937 .LASF4: - 1938 0308 6C6F6E67 .ascii "long int\000" - 1938 20696E74 - 1938 00 - 1939 .LASF0: - 1940 0311 7369676E .ascii "signed char\000" - 1940 65642063 - 1940 68617200 - 1941 .LASF41: - 1942 031d 55534246 .ascii "USBFS_hidIdleRate\000" - 1942 535F6869 - 1942 6449646C - 1942 65526174 - 1942 6500 - 1943 .LASF42: - 1944 032f 55534246 .ascii "USBFS_hidIdleTimer\000" - 1944 535F6869 - 1944 6449646C - 1944 6554696D - 1944 657200 - 1945 .LASF17: - 1946 0342 6C656E67 .ascii "length\000" - 1946 746800 - 1947 .LASF46: - 1948 0349 55534246 .ascii "USBFS_InitControlWrite\000" - 1948 535F496E - 1948 6974436F - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccAt1N4e.s page 46 - - - 1948 6E74726F - 1948 6C577269 - 1949 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_hid.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_hid.o deleted file mode 100755 index 1744134fa0f003234a0454d4bb4b7f4637c48238..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9688 zcmb_i3vgW3c|Pafm9)}IvR*clY)iY6z%s_GhlK%SY`w7cupJ}G;DSp!OUXc{rAafjaYCFnZA~*B+=MiQBn=(fxZii~ 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z0I1)m>mSkh4UIq0_=?82HJ;bF1RI{~+(<+_AtK^#A!1`)sc|O}?ey#VsMZhY`nbkv zji)t!LE}>zzpe2_BHDSGhu+lOr$)cWwp*&PP2)C=AJdrAh~-h^KuCou?=UW& z5gebXu~p+`8aHa(tWo71?0dAnTO;=o=jDLLLmHDB3mS_Wk88Y5quLKhe$^l3M?HDu zg-JvnV9VI+K%@~7c4|C8m@0cUE+{Gv{Fagjs(9!(zX?m@g^?OBkoOnHbMkPAI{Xe1 q;m7{~VY@0GE?p`f?3F)s)jzbmiSeOt)$Q)m`c=B!Nv&szi1%-cQv1UI diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst deleted file mode 100755 index 091ea62..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.lst +++ /dev/null @@ -1,5914 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "USBFS_std.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.USBFS_ConfigReg,"ax",%progbits - 19 .align 1 - 20 .global USBFS_ConfigReg - 21 .thumb - 22 .thumb_func - 23 .type USBFS_ConfigReg, %function - 24 USBFS_ConfigReg: - 25 .LFB1: - 26 .file 1 ".\\Generated_Source\\PSoC5\\USBFS_std.c" - 1:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/USBFS_std.c **** * File Name: USBFS_std.c - 3:.\Generated_Source\PSoC5/USBFS_std.c **** * Version 2.60 - 4:.\Generated_Source\PSoC5/USBFS_std.c **** * - 5:.\Generated_Source\PSoC5/USBFS_std.c **** * Description: - 6:.\Generated_Source\PSoC5/USBFS_std.c **** * USB Standard request handler. - 7:.\Generated_Source\PSoC5/USBFS_std.c **** * - 8:.\Generated_Source\PSoC5/USBFS_std.c **** * Note: - 9:.\Generated_Source\PSoC5/USBFS_std.c **** * - 10:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/USBFS_std.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/USBFS_std.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/USBFS_std.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/USBFS_std.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/USBFS_std.c **** - 17:.\Generated_Source\PSoC5/USBFS_std.c **** #include "USBFS.h" - 18:.\Generated_Source\PSoC5/USBFS_std.c **** #include "USBFS_cdc.h" - 19:.\Generated_Source\PSoC5/USBFS_std.c **** #include "USBFS_pvt.h" - 20:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_MIDI_STREAMING) - 21:.\Generated_Source\PSoC5/USBFS_std.c **** #include "USBFS_midi.h" - 22:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - 23:.\Generated_Source\PSoC5/USBFS_std.c **** - 24:.\Generated_Source\PSoC5/USBFS_std.c **** - 25:.\Generated_Source\PSoC5/USBFS_std.c **** /*************************************** - 26:.\Generated_Source\PSoC5/USBFS_std.c **** * Static data allocation - 27:.\Generated_Source\PSoC5/USBFS_std.c **** ***************************************/ - 28:.\Generated_Source\PSoC5/USBFS_std.c **** - 29:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_FWSN_STRING) - 30:.\Generated_Source\PSoC5/USBFS_std.c **** static volatile uint8 *USBFS_fwSerialNumberStringDescriptor; - 31:.\Generated_Source\PSoC5/USBFS_std.c **** static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 2 - - - 32:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* USBFS_ENABLE_FWSN_STRING */ - 33:.\Generated_Source\PSoC5/USBFS_std.c **** - 34:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_FWSN_STRING) - 35:.\Generated_Source\PSoC5/USBFS_std.c **** - 36:.\Generated_Source\PSoC5/USBFS_std.c **** - 37:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 38:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_SerialNumString - 39:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 40:.\Generated_Source\PSoC5/USBFS_std.c **** * - 41:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 42:.\Generated_Source\PSoC5/USBFS_std.c **** * Application firmware may supply the source of the USB device descriptors - 43:.\Generated_Source\PSoC5/USBFS_std.c **** * serial number string during runtime. - 44:.\Generated_Source\PSoC5/USBFS_std.c **** * - 45:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 46:.\Generated_Source\PSoC5/USBFS_std.c **** * snString: pointer to string. - 47:.\Generated_Source\PSoC5/USBFS_std.c **** * - 48:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 49:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 50:.\Generated_Source\PSoC5/USBFS_std.c **** * - 51:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: - 52:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - 53:.\Generated_Source\PSoC5/USBFS_std.c **** * - 54:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 55:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_SerialNumString(uint8 snString[]) - 56:.\Generated_Source\PSoC5/USBFS_std.c **** { - 57:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_snStringConfirm = USBFS_FALSE; - 58:.\Generated_Source\PSoC5/USBFS_std.c **** if(snString != NULL) - 59:.\Generated_Source\PSoC5/USBFS_std.c **** { - 60:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_fwSerialNumberStringDescriptor = snString; - 61:.\Generated_Source\PSoC5/USBFS_std.c **** /* Check descriptor validation */ - 62:.\Generated_Source\PSoC5/USBFS_std.c **** if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) ) - 63:.\Generated_Source\PSoC5/USBFS_std.c **** { - 64:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_snStringConfirm = USBFS_TRUE; - 65:.\Generated_Source\PSoC5/USBFS_std.c **** } - 66:.\Generated_Source\PSoC5/USBFS_std.c **** } - 67:.\Generated_Source\PSoC5/USBFS_std.c **** } - 68:.\Generated_Source\PSoC5/USBFS_std.c **** - 69:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* USBFS_ENABLE_FWSN_STRING */ - 70:.\Generated_Source\PSoC5/USBFS_std.c **** - 71:.\Generated_Source\PSoC5/USBFS_std.c **** - 72:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 73:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_HandleStandardRqst - 74:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 75:.\Generated_Source\PSoC5/USBFS_std.c **** * - 76:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 77:.\Generated_Source\PSoC5/USBFS_std.c **** * This Routine dispatches standard requests - 78:.\Generated_Source\PSoC5/USBFS_std.c **** * - 79:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 80:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 81:.\Generated_Source\PSoC5/USBFS_std.c **** * - 82:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 83:.\Generated_Source\PSoC5/USBFS_std.c **** * TRUE if request handled. - 84:.\Generated_Source\PSoC5/USBFS_std.c **** * - 85:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: - 86:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - 87:.\Generated_Source\PSoC5/USBFS_std.c **** * - 88:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 3 - - - 89:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 USBFS_HandleStandardRqst(void) - 90:.\Generated_Source\PSoC5/USBFS_std.c **** { - 91:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 requestHandled = USBFS_FALSE; - 92:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 interfaceNumber; - 93:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_STRINGS) - 94:.\Generated_Source\PSoC5/USBFS_std.c **** volatile uint8 *pStr = 0u; - 95:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) - 96:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 nStr; - 97:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 descrLength; - 98:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ - 99:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* USBFS_ENABLE_STRINGS */ - 100:.\Generated_Source\PSoC5/USBFS_std.c **** static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; - 101:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *pTmp; - 102:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = 0u; - 103:.\Generated_Source\PSoC5/USBFS_std.c **** - 104:.\Generated_Source\PSoC5/USBFS_std.c **** if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - 105:.\Generated_Source\PSoC5/USBFS_std.c **** { - 106:.\Generated_Source\PSoC5/USBFS_std.c **** /* Control Read */ - 107:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 108:.\Generated_Source\PSoC5/USBFS_std.c **** { - 109:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_GET_DESCRIPTOR: - 110:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE) - 111:.\Generated_Source\PSoC5/USBFS_std.c **** { - 112:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetDeviceTablePtr(); - 113:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - 114:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; - 115:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 116:.\Generated_Source\PSoC5/USBFS_std.c **** } - 117:.\Generated_Source\PSoC5/USBFS_std.c **** else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG) - 118:.\Generated_Source\PSoC5/USBFS_std.c **** { - 119:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo)); - 120:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - 121:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ - 122:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ - 123:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; - 124:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 125:.\Generated_Source\PSoC5/USBFS_std.c **** } - 126:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_STRINGS) - 127:.\Generated_Source\PSoC5/USBFS_std.c **** else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING) - 128:.\Generated_Source\PSoC5/USBFS_std.c **** { - 129:.\Generated_Source\PSoC5/USBFS_std.c **** /* Descriptor Strings*/ - 130:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) - 131:.\Generated_Source\PSoC5/USBFS_std.c **** nStr = 0u; - 132:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u]; - 133:.\Generated_Source\PSoC5/USBFS_std.c **** while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) - 134:.\Generated_Source\PSoC5/USBFS_std.c **** { - 135:.\Generated_Source\PSoC5/USBFS_std.c **** /* Read descriptor length from 1st byte */ - 136:.\Generated_Source\PSoC5/USBFS_std.c **** descrLength = *pStr; - 137:.\Generated_Source\PSoC5/USBFS_std.c **** /* Move to next string descriptor */ - 138:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = &pStr[descrLength]; - 139:.\Generated_Source\PSoC5/USBFS_std.c **** nStr++; - 140:.\Generated_Source\PSoC5/USBFS_std.c **** } - 141:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */ - 142:.\Generated_Source\PSoC5/USBFS_std.c **** /* Microsoft OS String*/ - 143:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_MSOS_STRING) - 144:.\Generated_Source\PSoC5/USBFS_std.c **** if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS ) - 145:.\Generated_Source\PSoC5/USBFS_std.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 4 - - - 146:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u]; - 147:.\Generated_Source\PSoC5/USBFS_std.c **** } - 148:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_MSOS_STRING*/ - 149:.\Generated_Source\PSoC5/USBFS_std.c **** /* SN string */ - 150:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_SN_STRING) - 151:.\Generated_Source\PSoC5/USBFS_std.c **** if( (CY_GET_REG8(USBFS_wValueLo) != 0u) && - 152:.\Generated_Source\PSoC5/USBFS_std.c **** (CY_GET_REG8(USBFS_wValueLo) == - 153:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) ) - 154:.\Generated_Source\PSoC5/USBFS_std.c **** { - 155:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; - 156:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_FWSN_STRING) - 157:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_snStringConfirm != USBFS_FALSE) - 158:.\Generated_Source\PSoC5/USBFS_std.c **** { - 159:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = USBFS_fwSerialNumberStringDescriptor; - 160:.\Generated_Source\PSoC5/USBFS_std.c **** } - 161:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* USBFS_ENABLE_FWSN_STRING */ - 162:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_IDSN_STRING) - 163:.\Generated_Source\PSoC5/USBFS_std.c **** /* Read DIE ID and generate string descriptor in RAM */ - 164:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); - 165:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = USBFS_idSerialNumberStringDescriptor; - 166:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_IDSN_STRING */ - 167:.\Generated_Source\PSoC5/USBFS_std.c **** } - 168:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_SN_STRING */ - 169:.\Generated_Source\PSoC5/USBFS_std.c **** if (*pStr != 0u) - 170:.\Generated_Source\PSoC5/USBFS_std.c **** { - 171:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = *pStr; - 172:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = pStr; - 173:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 174:.\Generated_Source\PSoC5/USBFS_std.c **** } - 175:.\Generated_Source\PSoC5/USBFS_std.c **** } - 176:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_STRINGS */ - 177:.\Generated_Source\PSoC5/USBFS_std.c **** else - 178:.\Generated_Source\PSoC5/USBFS_std.c **** { - 179:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_DispatchClassRqst(); - 180:.\Generated_Source\PSoC5/USBFS_std.c **** } - 181:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 182:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_GET_STATUS: - 183:.\Generated_Source\PSoC5/USBFS_std.c **** switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)) - 184:.\Generated_Source\PSoC5/USBFS_std.c **** { - 185:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_EP: - 186:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; - 187:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[0u] = USBFS_EP[ \ - 188:.\Generated_Source\PSoC5/USBFS_std.c **** CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; - 189:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[1u] = 0u; - 190:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = &USBFS_tBuffer[0u]; - 191:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 192:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 193:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_DEV: - 194:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; - 195:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[0u] = USBFS_deviceStatus; - 196:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[1u] = 0u; - 197:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = &USBFS_tBuffer[0u]; - 198:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 199:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 200:.\Generated_Source\PSoC5/USBFS_std.c **** default: /* requestHandled is initialized as FALSE by default */ - 201:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 202:.\Generated_Source\PSoC5/USBFS_std.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 5 - - - 203:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 204:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_GET_CONFIGURATION: - 205:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = 1u; - 206:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration; - 207:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 208:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 209:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_GET_INTERFACE: - 210:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = 1u; - 211:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \ - 212:.\Generated_Source\PSoC5/USBFS_std.c **** CY_GET_REG8(USBFS_wInde - 213:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 214:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 215:.\Generated_Source\PSoC5/USBFS_std.c **** default: /* requestHandled is initialized as FALSE by default */ - 216:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 217:.\Generated_Source\PSoC5/USBFS_std.c **** } - 218:.\Generated_Source\PSoC5/USBFS_std.c **** } - 219:.\Generated_Source\PSoC5/USBFS_std.c **** else { - 220:.\Generated_Source\PSoC5/USBFS_std.c **** /* Control Write */ - 221:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 222:.\Generated_Source\PSoC5/USBFS_std.c **** { - 223:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_SET_ADDRESS: - 224:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo); - 225:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 226:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 227:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_SET_CONFIGURATION: - 228:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configuration = CY_GET_REG8(USBFS_wValueLo); - 229:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configurationChanged = USBFS_TRUE; - 230:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_Config(USBFS_TRUE); - 231:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 232:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 233:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_SET_INTERFACE: - 234:.\Generated_Source\PSoC5/USBFS_std.c **** if (USBFS_ValidateAlternateSetting() != 0u) - 235:.\Generated_Source\PSoC5/USBFS_std.c **** { - 236:.\Generated_Source\PSoC5/USBFS_std.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - 237:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceNumber = interfaceNumber; - 238:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configurationChanged = USBFS_TRUE; - 239:.\Generated_Source\PSoC5/USBFS_std.c **** #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ - 240:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_EP_MM == USBFS__EP_MANUAL) ) - 241:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_Config(USBFS_FALSE); - 242:.\Generated_Source\PSoC5/USBFS_std.c **** #else - 243:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ConfigAltChanged(); - 244:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ - 245:.\Generated_Source\PSoC5/USBFS_std.c **** /* Update handled Alt setting changes status */ - 246:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[interfaceNumber] = - 247:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting[interfaceNumber]; - 248:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 249:.\Generated_Source\PSoC5/USBFS_std.c **** } - 250:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 251:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_CLEAR_FEATURE: - 252:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - 253:.\Generated_Source\PSoC5/USBFS_std.c **** { - 254:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_EP: - 255:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) - 256:.\Generated_Source\PSoC5/USBFS_std.c **** { - 257:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_ClearEndpointHalt(); - 258:.\Generated_Source\PSoC5/USBFS_std.c **** } - 259:.\Generated_Source\PSoC5/USBFS_std.c **** break; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 6 - - - 260:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_DEV: - 261:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear device REMOTE_WAKEUP */ - 262:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) - 263:.\Generated_Source\PSoC5/USBFS_std.c **** { - 264:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; - 265:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 266:.\Generated_Source\PSoC5/USBFS_std.c **** } - 267:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 268:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_IFC: - 269:.\Generated_Source\PSoC5/USBFS_std.c **** /* Validate interfaceNumber */ - 270:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) - 271:.\Generated_Source\PSoC5/USBFS_std.c **** { - 272:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - 273:.\Generated_Source\PSoC5/USBFS_std.c **** (uint8)~(CY_GET_REG8(USBFS_wValueLo - 274:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 275:.\Generated_Source\PSoC5/USBFS_std.c **** } - 276:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 277:.\Generated_Source\PSoC5/USBFS_std.c **** default: /* requestHandled is initialized as FALSE by default */ - 278:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 279:.\Generated_Source\PSoC5/USBFS_std.c **** } - 280:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 281:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_SET_FEATURE: - 282:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - 283:.\Generated_Source\PSoC5/USBFS_std.c **** { - 284:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_EP: - 285:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) - 286:.\Generated_Source\PSoC5/USBFS_std.c **** { - 287:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_SetEndpointHalt(); - 288:.\Generated_Source\PSoC5/USBFS_std.c **** } - 289:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 290:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_DEV: - 291:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set device REMOTE_WAKEUP */ - 292:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) - 293:.\Generated_Source\PSoC5/USBFS_std.c **** { - 294:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; - 295:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 296:.\Generated_Source\PSoC5/USBFS_std.c **** } - 297:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 298:.\Generated_Source\PSoC5/USBFS_std.c **** case USBFS_RQST_RCPT_IFC: - 299:.\Generated_Source\PSoC5/USBFS_std.c **** /* Validate interfaceNumber */ - 300:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) - 301:.\Generated_Source\PSoC5/USBFS_std.c **** { - 302:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - 303:.\Generated_Source\PSoC5/USBFS_std.c **** (uint8)~(CY_GET_REG8(USBFS_wValueLo - 304:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 305:.\Generated_Source\PSoC5/USBFS_std.c **** } - 306:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 307:.\Generated_Source\PSoC5/USBFS_std.c **** default: /* requestHandled is initialized as FALSE by default */ - 308:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 309:.\Generated_Source\PSoC5/USBFS_std.c **** } - 310:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 311:.\Generated_Source\PSoC5/USBFS_std.c **** default: /* requestHandled is initialized as FALSE by default */ - 312:.\Generated_Source\PSoC5/USBFS_std.c **** break; - 313:.\Generated_Source\PSoC5/USBFS_std.c **** } - 314:.\Generated_Source\PSoC5/USBFS_std.c **** } - 315:.\Generated_Source\PSoC5/USBFS_std.c **** return(requestHandled); - 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 7 - - - 317:.\Generated_Source\PSoC5/USBFS_std.c **** - 318:.\Generated_Source\PSoC5/USBFS_std.c **** - 319:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_IDSN_STRING) - 320:.\Generated_Source\PSoC5/USBFS_std.c **** - 321:.\Generated_Source\PSoC5/USBFS_std.c **** /*************************************************************************** - 322:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_ReadDieID - 323:.\Generated_Source\PSoC5/USBFS_std.c **** **************************************************************************** - 324:.\Generated_Source\PSoC5/USBFS_std.c **** * - 325:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 326:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine read Die ID and generate Serial Number string descriptor. - 327:.\Generated_Source\PSoC5/USBFS_std.c **** * - 328:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 329:.\Generated_Source\PSoC5/USBFS_std.c **** * descr: pointer on string descriptor. - 330:.\Generated_Source\PSoC5/USBFS_std.c **** * - 331:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 332:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 333:.\Generated_Source\PSoC5/USBFS_std.c **** * - 334:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: - 335:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - 336:.\Generated_Source\PSoC5/USBFS_std.c **** * - 337:.\Generated_Source\PSoC5/USBFS_std.c **** ***************************************************************************/ - 338:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_ReadDieID(uint8 descr[]) - 339:.\Generated_Source\PSoC5/USBFS_std.c **** { - 340:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 i; - 341:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 j = 0u; - 342:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 value; - 343:.\Generated_Source\PSoC5/USBFS_std.c **** const char8 CYCODE hex[16u] = "0123456789ABCDEF"; - 344:.\Generated_Source\PSoC5/USBFS_std.c **** - 345:.\Generated_Source\PSoC5/USBFS_std.c **** - 346:.\Generated_Source\PSoC5/USBFS_std.c **** /* Check descriptor validation */ - 347:.\Generated_Source\PSoC5/USBFS_std.c **** if( descr != NULL) - 348:.\Generated_Source\PSoC5/USBFS_std.c **** { - 349:.\Generated_Source\PSoC5/USBFS_std.c **** descr[0u] = USBFS_IDSN_DESCR_LENGTH; - 350:.\Generated_Source\PSoC5/USBFS_std.c **** descr[1u] = USBFS_DESCR_STRING; - 351:.\Generated_Source\PSoC5/USBFS_std.c **** - 352:.\Generated_Source\PSoC5/USBFS_std.c **** /* fill descriptor */ - 353:.\Generated_Source\PSoC5/USBFS_std.c **** for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) - 354:.\Generated_Source\PSoC5/USBFS_std.c **** { - 355:.\Generated_Source\PSoC5/USBFS_std.c **** value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j)); - 356:.\Generated_Source\PSoC5/USBFS_std.c **** j++; - 357:.\Generated_Source\PSoC5/USBFS_std.c **** descr[i] = (uint8)hex[value >> 4u]; - 358:.\Generated_Source\PSoC5/USBFS_std.c **** descr[i + 2u] = (uint8)hex[value & 0x0Fu]; - 359:.\Generated_Source\PSoC5/USBFS_std.c **** } - 360:.\Generated_Source\PSoC5/USBFS_std.c **** } - 361:.\Generated_Source\PSoC5/USBFS_std.c **** } - 362:.\Generated_Source\PSoC5/USBFS_std.c **** - 363:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_IDSN_STRING */ - 364:.\Generated_Source\PSoC5/USBFS_std.c **** - 365:.\Generated_Source\PSoC5/USBFS_std.c **** - 366:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 367:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_ConfigReg - 368:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 369:.\Generated_Source\PSoC5/USBFS_std.c **** * - 370:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 371:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine configures hardware registers from the variables. - 372:.\Generated_Source\PSoC5/USBFS_std.c **** * It is called from USBFS_Config() function and from RestoreConfig - 373:.\Generated_Source\PSoC5/USBFS_std.c **** * after Wakeup. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 8 - - - 374:.\Generated_Source\PSoC5/USBFS_std.c **** * - 375:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 376:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 377:.\Generated_Source\PSoC5/USBFS_std.c **** * - 378:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 379:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 380:.\Generated_Source\PSoC5/USBFS_std.c **** * - 381:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 382:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_ConfigReg(void) - 383:.\Generated_Source\PSoC5/USBFS_std.c **** { - 27 .loc 1 383 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 .LVL0: - 32 0000 30B5 push {r4, r5, lr} - 33 .LCFI0: - 34 .cfi_def_cfa_offset 12 - 35 .cfi_offset 4, -12 - 36 .cfi_offset 5, -8 - 37 .cfi_offset 14, -4 - 384:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep; - 385:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 i; - 386:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - 387:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep_type = 0u; - 388:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - 389:.\Generated_Source\PSoC5/USBFS_std.c **** - 390:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set the endpoint buffer addresses */ - 391:.\Generated_Source\PSoC5/USBFS_std.c **** ep = USBFS_EP1; - 38 .loc 1 391 0 - 39 0002 0122 movs r2, #1 - 40 .LVL1: - 41 .L2: - 382:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_ConfigReg(void) - 42 .loc 1 382 0 discriminator 1 - 43 0004 02F10F03 add r3, r2, #15 - 44 0008 1801 lsls r0, r3, #4 - 392:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < 0x80u; i+= 0x10u) - 45 .loc 1 392 0 discriminator 1 - 46 000a 092A cmp r2, #9 - 382:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_ConfigReg(void) - 47 .loc 1 382 0 discriminator 1 - 48 000c C3B2 uxtb r3, r0 - 49 .LVL2: - 50 .loc 1 392 0 discriminator 1 - 51 000e 3BD0 beq .L9 - 52 .L6: - 393:.\Generated_Source\PSoC5/USBFS_std.c **** { - 394:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS | - 395:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ARB_EPX_CFG_RESET); - 396:.\Generated_Source\PSoC5/USBFS_std.c **** - 397:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM != USBFS__EP_MANUAL) - 398:.\Generated_Source\PSoC5/USBFS_std.c **** /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in - 399:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK); - 400:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - 401:.\Generated_Source\PSoC5/USBFS_std.c **** - 402:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 9 - - - 53 .loc 1 402 0 - 54 0010 1F49 ldr r1, .L10 - 394:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS | - 55 .loc 1 394 0 - 56 0012 03F18044 add r4, r3, #1073741824 - 57 0016 0C20 movs r0, #12 - 58 .LVL3: - 59 0018 04F5C145 add r5, r4, #24704 - 60 .loc 1 402 0 - 61 001c 00FB0214 mla r4, r0, r2, r1 - 394:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS | - 62 .loc 1 394 0 - 63 0020 2870 strb r0, [r5, #0] - 64 0022 1C49 ldr r1, .L10+4 - 65 .loc 1 402 0 - 66 0024 6579 ldrb r5, [r4, #5] @ zero_extendqisi2 - 67 0026 5918 adds r1, r3, r1 - 68 0028 25B1 cbz r5, .L3 - 403:.\Generated_Source\PSoC5/USBFS_std.c **** { - 404:.\Generated_Source\PSoC5/USBFS_std.c **** if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u ) - 69 .loc 1 404 0 - 70 002a 2479 ldrb r4, [r4, #4] @ zero_extendqisi2 - 71 002c 2406 lsls r4, r4, #24 - 405:.\Generated_Source\PSoC5/USBFS_std.c **** { - 406:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN); - 407:.\Generated_Source\PSoC5/USBFS_std.c **** } - 408:.\Generated_Source\PSoC5/USBFS_std.c **** else - 409:.\Generated_Source\PSoC5/USBFS_std.c **** { - 410:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT); - 72 .loc 1 410 0 - 73 002e 58BF it pl - 74 0030 0820 movpl r0, #8 - 75 0032 00E0 b .L7 - 76 .L3: - 411:.\Generated_Source\PSoC5/USBFS_std.c **** /* Prepare EP type mask for automatic memory allocation */ - 412:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - 413:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type |= (uint8)(0x01u << (ep - USBFS_EP1)); - 414:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - 415:.\Generated_Source\PSoC5/USBFS_std.c **** } - 416:.\Generated_Source\PSoC5/USBFS_std.c **** } - 417:.\Generated_Source\PSoC5/USBFS_std.c **** else - 418:.\Generated_Source\PSoC5/USBFS_std.c **** { - 419:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP); - 77 .loc 1 419 0 - 78 0034 8020 movs r0, #128 - 79 .L7: - 80 0036 0870 strb r0, [r1, #0] - 420:.\Generated_Source\PSoC5/USBFS_std.c **** } - 421:.\Generated_Source\PSoC5/USBFS_std.c **** - 422:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - 423:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u); - 81 .loc 1 423 0 - 82 0038 1749 ldr r1, .L10+8 - 83 003a 0C24 movs r4, #12 - 84 003c 5818 adds r0, r3, r1 - 85 003e 1449 ldr r1, .L10 - 86 0040 04FB0211 mla r1, r4, r2, r1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 10 - - - 87 0044 0C89 ldrh r4, [r1, #8] - 424:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu); - 425:.\Generated_Source\PSoC5/USBFS_std.c **** - 426:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - 427:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - 428:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - 429:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - 430:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - 431:.\Generated_Source\PSoC5/USBFS_std.c **** - 432:.\Generated_Source\PSoC5/USBFS_std.c **** ep++; - 88 .loc 1 432 0 - 89 0046 0132 adds r2, r2, #1 - 90 .LVL4: - 423:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u); - 91 .loc 1 423 0 - 92 0048 C4F30724 ubfx r4, r4, #8, #8 - 93 004c 0470 strb r4, [r0, #0] - 424:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu); - 94 .loc 1 424 0 - 95 004e 0C89 ldrh r4, [r1, #8] - 96 0050 1248 ldr r0, .L10+12 - 97 0052 E4B2 uxtb r4, r4 - 98 0054 1818 adds r0, r3, r0 - 99 0056 0470 strb r4, [r0, #0] - 426:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - 100 .loc 1 426 0 - 101 0058 CC88 ldrh r4, [r1, #6] - 102 005a 1148 ldr r0, .L10+16 - 103 005c E4B2 uxtb r4, r4 - 104 005e 1818 adds r0, r3, r0 - 105 0060 0470 strb r4, [r0, #0] - 427:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - 106 .loc 1 427 0 - 107 0062 CC88 ldrh r4, [r1, #6] - 108 0064 0F48 ldr r0, .L10+20 - 109 0066 C4F30724 ubfx r4, r4, #8, #8 - 110 006a 1818 adds r0, r3, r0 - 111 006c 0470 strb r4, [r0, #0] - 428:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - 112 .loc 1 428 0 - 113 006e CC88 ldrh r4, [r1, #6] - 114 0070 0D48 ldr r0, .L10+24 - 115 0072 E4B2 uxtb r4, r4 - 116 0074 1818 adds r0, r3, r0 - 117 0076 0470 strb r4, [r0, #0] - 429:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - 118 .loc 1 429 0 - 119 0078 0C48 ldr r0, .L10+28 - 120 .loc 1 432 0 - 121 007a D2B2 uxtb r2, r2 - 122 .LVL5: - 429:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - 123 .loc 1 429 0 - 124 007c 1818 adds r0, r3, r0 - 125 007e CB88 ldrh r3, [r1, #6] - 126 0080 C3F30721 ubfx r1, r3, #8, #8 - 127 0084 0170 strb r1, [r0, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 11 - - - 128 0086 BDE7 b .L2 - 129 .LVL6: - 130 .L9: - 433:.\Generated_Source\PSoC5/USBFS_std.c **** } - 434:.\Generated_Source\PSoC5/USBFS_std.c **** - 435:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - 436:.\Generated_Source\PSoC5/USBFS_std.c **** /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11- - 437:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; - 438:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */ - 439:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_DMA_THRES_MSB_REG = 0u; - 440:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK; - 441:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP_TYPE_REG = ep_type; - 442:.\Generated_Source\PSoC5/USBFS_std.c **** /* Cfg_cmp bit set to 1 once configuration is complete. */ - 443:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM | - 444:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ARB_CFG_CFG_CPM; - 445:.\Generated_Source\PSoC5/USBFS_std.c **** /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ - 446:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - 447:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - 448:.\Generated_Source\PSoC5/USBFS_std.c **** - 449:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu); - 131 .loc 1 449 0 - 132 0088 0949 ldr r1, .L10+32 - 133 008a FF22 movs r2, #255 - 134 .LVL7: - 135 008c 0A70 strb r2, [r1, #0] - 136 008e 30BD pop {r4, r5, pc} - 137 .L11: - 138 .align 2 - 139 .L10: - 140 0090 00000000 .word USBFS_EP - 141 0094 0E600040 .word 1073766414 - 142 0098 0C600040 .word 1073766412 - 143 009c 0D600040 .word 1073766413 - 144 00a0 86600040 .word 1073766534 - 145 00a4 87600040 .word 1073766535 - 146 00a8 84600040 .word 1073766532 - 147 00ac 85600040 .word 1073766533 - 148 00b0 0A600040 .word 1073766410 - 149 .cfi_endproc - 150 .LFE1: - 151 .size USBFS_ConfigReg, .-USBFS_ConfigReg - 152 .section .text.USBFS_GetConfigTablePtr,"ax",%progbits - 153 .align 1 - 154 .global USBFS_GetConfigTablePtr - 155 .thumb - 156 .thumb_func - 157 .type USBFS_GetConfigTablePtr, %function - 158 USBFS_GetConfigTablePtr: - 159 .LFB4: - 450:.\Generated_Source\PSoC5/USBFS_std.c **** } - 451:.\Generated_Source\PSoC5/USBFS_std.c **** - 452:.\Generated_Source\PSoC5/USBFS_std.c **** - 453:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 454:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_Config - 455:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 456:.\Generated_Source\PSoC5/USBFS_std.c **** * - 457:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 12 - - - 458:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine configures endpoints for the entire configuration by scanning - 459:.\Generated_Source\PSoC5/USBFS_std.c **** * the configuration descriptor. - 460:.\Generated_Source\PSoC5/USBFS_std.c **** * - 461:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 462:.\Generated_Source\PSoC5/USBFS_std.c **** * clearAltSetting: It configures the bAlternateSetting 0 for each interface. - 463:.\Generated_Source\PSoC5/USBFS_std.c **** * - 464:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 465:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 466:.\Generated_Source\PSoC5/USBFS_std.c **** * - 467:.\Generated_Source\PSoC5/USBFS_std.c **** * USBFS_interfaceClass - Initialized class array for each interface. - 468:.\Generated_Source\PSoC5/USBFS_std.c **** * It is used for handling Class specific requests depend on interface class. - 469:.\Generated_Source\PSoC5/USBFS_std.c **** * Different classes in multiple Alternate settings does not supported. - 470:.\Generated_Source\PSoC5/USBFS_std.c **** * - 471:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: - 472:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - 473:.\Generated_Source\PSoC5/USBFS_std.c **** * - 474:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 475:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_Config(uint8 clearAltSetting) - 476:.\Generated_Source\PSoC5/USBFS_std.c **** { - 477:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep; - 478:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 cur_ep; - 479:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 i; - 480:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep_type; - 481:.\Generated_Source\PSoC5/USBFS_std.c **** const uint8 *pDescr; - 482:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - 483:.\Generated_Source\PSoC5/USBFS_std.c **** uint16 buffCount = 0u; - 484:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - 485:.\Generated_Source\PSoC5/USBFS_std.c **** - 486:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *pTmp; - 487:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; - 488:.\Generated_Source\PSoC5/USBFS_std.c **** - 489:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear all of the endpoints */ - 490:.\Generated_Source\PSoC5/USBFS_std.c **** for (ep = 0u; ep < USBFS_MAX_EP; ep++) - 491:.\Generated_Source\PSoC5/USBFS_std.c **** { - 492:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].attrib = 0u; - 493:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].hwEpState = 0u; - 494:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; - 495:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epToggle = 0u; - 496:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; - 497:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].bufferSize = 0u; - 498:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].interface = 0u; - 499:.\Generated_Source\PSoC5/USBFS_std.c **** - 500:.\Generated_Source\PSoC5/USBFS_std.c **** } - 501:.\Generated_Source\PSoC5/USBFS_std.c **** - 502:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear Alternate settings for all interfaces */ - 503:.\Generated_Source\PSoC5/USBFS_std.c **** if(clearAltSetting != 0u) - 504:.\Generated_Source\PSoC5/USBFS_std.c **** { - 505:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - 506:.\Generated_Source\PSoC5/USBFS_std.c **** { - 507:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting[i] = 0x00u; - 508:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[i] = 0x00u; - 509:.\Generated_Source\PSoC5/USBFS_std.c **** } - 510:.\Generated_Source\PSoC5/USBFS_std.c **** } - 511:.\Generated_Source\PSoC5/USBFS_std.c **** - 512:.\Generated_Source\PSoC5/USBFS_std.c **** /* Init Endpoints and Device Status if configured */ - 513:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_configuration > 0u) - 514:.\Generated_Source\PSoC5/USBFS_std.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 13 - - - 515:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 516:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set Power status for current configuration */ - 517:.\Generated_Source\PSoC5/USBFS_std.c **** pDescr = (const uint8 *)pTmp->p_list; - 518:.\Generated_Source\PSoC5/USBFS_std.c **** if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) - 519:.\Generated_Source\PSoC5/USBFS_std.c **** { - 520:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; - 521:.\Generated_Source\PSoC5/USBFS_std.c **** } - 522:.\Generated_Source\PSoC5/USBFS_std.c **** else - 523:.\Generated_Source\PSoC5/USBFS_std.c **** { - 524:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; - 525:.\Generated_Source\PSoC5/USBFS_std.c **** } - 526:.\Generated_Source\PSoC5/USBFS_std.c **** /* Move to next element */ - 527:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = &pTmp[1u]; - 528:.\Generated_Source\PSoC5/USBFS_std.c **** ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - 529:.\Generated_Source\PSoC5/USBFS_std.c **** - 530:.\Generated_Source\PSoC5/USBFS_std.c **** #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ - 531:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_EP_MM == USBFS__EP_MANUAL) ) - 532:.\Generated_Source\PSoC5/USBFS_std.c **** /* Configure for dynamic EP memory allocation */ - 533:.\Generated_Source\PSoC5/USBFS_std.c **** /* p_list points the endpoint setting table. */ - 534:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; - 535:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 536:.\Generated_Source\PSoC5/USBFS_std.c **** { - 537:.\Generated_Source\PSoC5/USBFS_std.c **** /* Compare current Alternate setting with EP Alt*/ - 538:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) - 539:.\Generated_Source\PSoC5/USBFS_std.c **** { - 540:.\Generated_Source\PSoC5/USBFS_std.c **** cur_ep = pEP->addr & USBFS_DIR_UNUSED; - 541:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - 542:.\Generated_Source\PSoC5/USBFS_std.c **** if (pEP->addr & USBFS_DIR_IN) - 543:.\Generated_Source\PSoC5/USBFS_std.c **** { - 544:.\Generated_Source\PSoC5/USBFS_std.c **** /* IN Endpoint */ - 545:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - 546:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 547:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - 548:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_CDC_CLASS) - 549:.\Generated_Source\PSoC5/USBFS_std.c **** if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - 550:.\Generated_Source\PSoC5/USBFS_std.c **** (pEP->bMisc == USBFS_CLASS_CDC)) && - 551:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type != USBFS_EP_TYPE_INT)) - 552:.\Generated_Source\PSoC5/USBFS_std.c **** { - 553:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_cdc_data_in_ep = cur_ep; - 554:.\Generated_Source\PSoC5/USBFS_std.c **** } - 555:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_CDC_CLASS*/ - 556:.\Generated_Source\PSoC5/USBFS_std.c **** #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - 557:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_MIDI_IN_BUFF_SIZE > 0) ) - 558:.\Generated_Source\PSoC5/USBFS_std.c **** if((pEP->bMisc == USBFS_CLASS_AUDIO) && - 559:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type == USBFS_EP_TYPE_BULK)) - 560:.\Generated_Source\PSoC5/USBFS_std.c **** { - 561:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_midi_in_ep = cur_ep; - 562:.\Generated_Source\PSoC5/USBFS_std.c **** } - 563:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - 564:.\Generated_Source\PSoC5/USBFS_std.c **** } - 565:.\Generated_Source\PSoC5/USBFS_std.c **** else - 566:.\Generated_Source\PSoC5/USBFS_std.c **** { - 567:.\Generated_Source\PSoC5/USBFS_std.c **** /* OUT Endpoint */ - 568:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; - 569:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 570:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - 571:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_CDC_CLASS) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 14 - - - 572:.\Generated_Source\PSoC5/USBFS_std.c **** if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - 573:.\Generated_Source\PSoC5/USBFS_std.c **** (pEP->bMisc == USBFS_CLASS_CDC)) && - 574:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type != USBFS_EP_TYPE_INT)) - 575:.\Generated_Source\PSoC5/USBFS_std.c **** { - 576:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_cdc_data_out_ep = cur_ep; - 577:.\Generated_Source\PSoC5/USBFS_std.c **** } - 578:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_CDC_CLASS*/ - 579:.\Generated_Source\PSoC5/USBFS_std.c **** #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - 580:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) - 581:.\Generated_Source\PSoC5/USBFS_std.c **** if((pEP->bMisc == USBFS_CLASS_AUDIO) && - 582:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type == USBFS_EP_TYPE_BULK)) - 583:.\Generated_Source\PSoC5/USBFS_std.c **** { - 584:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_midi_out_ep = cur_ep; - 585:.\Generated_Source\PSoC5/USBFS_std.c **** } - 586:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - 587:.\Generated_Source\PSoC5/USBFS_std.c **** } - 588:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - 589:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].addr = pEP->addr; - 590:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].attrib = pEP->attributes; - 591:.\Generated_Source\PSoC5/USBFS_std.c **** } - 592:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = &pEP[1u]; - 593:.\Generated_Source\PSoC5/USBFS_std.c **** } - 594:.\Generated_Source\PSoC5/USBFS_std.c **** #else /* Config for static EP memory allocation */ - 595:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) - 596:.\Generated_Source\PSoC5/USBFS_std.c **** { - 597:.\Generated_Source\PSoC5/USBFS_std.c **** /* p_list points the endpoint setting table. */ - 598:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; - 599:.\Generated_Source\PSoC5/USBFS_std.c **** /* Find max length for each EP and select it (length could be different in differen - 600:.\Generated_Source\PSoC5/USBFS_std.c **** /* but other settings should be correct with regards to Interface alt Setting */ - 601:.\Generated_Source\PSoC5/USBFS_std.c **** for (cur_ep = 0u; cur_ep < ep; cur_ep++) - 602:.\Generated_Source\PSoC5/USBFS_std.c **** { - 603:.\Generated_Source\PSoC5/USBFS_std.c **** /* EP count is equal to EP # in table and we found larger EP length than have b - 604:.\Generated_Source\PSoC5/USBFS_std.c **** if(i == (pEP->addr & USBFS_DIR_UNUSED)) - 605:.\Generated_Source\PSoC5/USBFS_std.c **** { - 606:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_EP[i].bufferSize < pEP->bufferSize) - 607:.\Generated_Source\PSoC5/USBFS_std.c **** { - 608:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].bufferSize = pEP->bufferSize; - 609:.\Generated_Source\PSoC5/USBFS_std.c **** } - 610:.\Generated_Source\PSoC5/USBFS_std.c **** /* Compare current Alternate setting with EP Alt*/ - 611:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) - 612:.\Generated_Source\PSoC5/USBFS_std.c **** { - 613:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - 614:.\Generated_Source\PSoC5/USBFS_std.c **** if ((pEP->addr & USBFS_DIR_IN) != 0u) - 615:.\Generated_Source\PSoC5/USBFS_std.c **** { - 616:.\Generated_Source\PSoC5/USBFS_std.c **** /* IN Endpoint */ - 617:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; - 618:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 619:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - 620:.\Generated_Source\PSoC5/USBFS_std.c **** /* Find and init CDC IN endpoint number */ - 621:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_CDC_CLASS) - 622:.\Generated_Source\PSoC5/USBFS_std.c **** if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - 623:.\Generated_Source\PSoC5/USBFS_std.c **** (pEP->bMisc == USBFS_CLASS_CDC)) && - 624:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type != USBFS_EP_TYPE_INT)) - 625:.\Generated_Source\PSoC5/USBFS_std.c **** { - 626:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_cdc_data_in_ep = i; - 627:.\Generated_Source\PSoC5/USBFS_std.c **** } - 628:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_CDC_CLASS*/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 15 - - - 629:.\Generated_Source\PSoC5/USBFS_std.c **** #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - 630:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_MIDI_IN_BUFF_SIZE > 0) ) - 631:.\Generated_Source\PSoC5/USBFS_std.c **** if((pEP->bMisc == USBFS_CLASS_AUDIO) && - 632:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type == USBFS_EP_TYPE_BULK)) - 633:.\Generated_Source\PSoC5/USBFS_std.c **** { - 634:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_midi_in_ep = i; - 635:.\Generated_Source\PSoC5/USBFS_std.c **** } - 636:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - 637:.\Generated_Source\PSoC5/USBFS_std.c **** } - 638:.\Generated_Source\PSoC5/USBFS_std.c **** else - 639:.\Generated_Source\PSoC5/USBFS_std.c **** { - 640:.\Generated_Source\PSoC5/USBFS_std.c **** /* OUT Endpoint */ - 641:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; - 642:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 643:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - 644:.\Generated_Source\PSoC5/USBFS_std.c **** /* Find and init CDC IN endpoint number */ - 645:.\Generated_Source\PSoC5/USBFS_std.c **** #if defined(USBFS_ENABLE_CDC_CLASS) - 646:.\Generated_Source\PSoC5/USBFS_std.c **** if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - 647:.\Generated_Source\PSoC5/USBFS_std.c **** (pEP->bMisc == USBFS_CLASS_CDC)) && - 648:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type != USBFS_EP_TYPE_INT)) - 649:.\Generated_Source\PSoC5/USBFS_std.c **** { - 650:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_cdc_data_out_ep = i; - 651:.\Generated_Source\PSoC5/USBFS_std.c **** } - 652:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_CDC_CLASS*/ - 653:.\Generated_Source\PSoC5/USBFS_std.c **** #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - 654:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) - 655:.\Generated_Source\PSoC5/USBFS_std.c **** if((pEP->bMisc == USBFS_CLASS_AUDIO) && - 656:.\Generated_Source\PSoC5/USBFS_std.c **** (ep_type == USBFS_EP_TYPE_BULK)) - 657:.\Generated_Source\PSoC5/USBFS_std.c **** { - 658:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_midi_out_ep = i; - 659:.\Generated_Source\PSoC5/USBFS_std.c **** } - 660:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - 661:.\Generated_Source\PSoC5/USBFS_std.c **** } - 662:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].addr = pEP->addr; - 663:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].attrib = pEP->attributes; - 664:.\Generated_Source\PSoC5/USBFS_std.c **** - 665:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - 666:.\Generated_Source\PSoC5/USBFS_std.c **** break; /* use first EP setting in Auto memory managment */ - 667:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - 668:.\Generated_Source\PSoC5/USBFS_std.c **** } - 669:.\Generated_Source\PSoC5/USBFS_std.c **** } - 670:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = &pEP[1u]; - 671:.\Generated_Source\PSoC5/USBFS_std.c **** } - 672:.\Generated_Source\PSoC5/USBFS_std.c **** } - 673:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ - 674:.\Generated_Source\PSoC5/USBFS_std.c **** - 675:.\Generated_Source\PSoC5/USBFS_std.c **** /* Init class array for each interface and interface number for each EP. - 676:.\Generated_Source\PSoC5/USBFS_std.c **** * It is used for handling Class specific requests directed to either an - 677:.\Generated_Source\PSoC5/USBFS_std.c **** * interface or the endpoint. - 678:.\Generated_Source\PSoC5/USBFS_std.c **** */ - 679:.\Generated_Source\PSoC5/USBFS_std.c **** /* p_list points the endpoint setting table. */ - 680:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; - 681:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 682:.\Generated_Source\PSoC5/USBFS_std.c **** { - 683:.\Generated_Source\PSoC5/USBFS_std.c **** /* Configure interface number for each EP*/ - 684:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; - 685:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = &pEP[1u]; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 16 - - - 686:.\Generated_Source\PSoC5/USBFS_std.c **** } - 687:.\Generated_Source\PSoC5/USBFS_std.c **** /* Init pointer on interface class table*/ - 688:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); - 689:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set the endpoint buffer addresses */ - 690:.\Generated_Source\PSoC5/USBFS_std.c **** - 691:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - 692:.\Generated_Source\PSoC5/USBFS_std.c **** for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) - 693:.\Generated_Source\PSoC5/USBFS_std.c **** { - 694:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].buffOffset = buffCount; - 695:.\Generated_Source\PSoC5/USBFS_std.c **** buffCount += USBFS_EP[ep].bufferSize; - 696:.\Generated_Source\PSoC5/USBFS_std.c **** } - 697:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - 698:.\Generated_Source\PSoC5/USBFS_std.c **** - 699:.\Generated_Source\PSoC5/USBFS_std.c **** /* Configure hardware registers */ - 700:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ConfigReg(); - 701:.\Generated_Source\PSoC5/USBFS_std.c **** } /* USBFS_configuration > 0 */ - 702:.\Generated_Source\PSoC5/USBFS_std.c **** } - 703:.\Generated_Source\PSoC5/USBFS_std.c **** - 704:.\Generated_Source\PSoC5/USBFS_std.c **** - 705:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 706:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_ConfigAltChanged - 707:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 708:.\Generated_Source\PSoC5/USBFS_std.c **** * - 709:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 710:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine update configuration for the required endpoints only. - 711:.\Generated_Source\PSoC5/USBFS_std.c **** * It is called after SET_INTERFACE request when Static memory allocation used. - 712:.\Generated_Source\PSoC5/USBFS_std.c **** * - 713:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 714:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 715:.\Generated_Source\PSoC5/USBFS_std.c **** * - 716:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 717:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 718:.\Generated_Source\PSoC5/USBFS_std.c **** * - 719:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: - 720:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - 721:.\Generated_Source\PSoC5/USBFS_std.c **** * - 722:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 723:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_ConfigAltChanged(void) - 724:.\Generated_Source\PSoC5/USBFS_std.c **** { - 725:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep; - 726:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 cur_ep; - 727:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 i; - 728:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep_type; - 729:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ri; - 730:.\Generated_Source\PSoC5/USBFS_std.c **** - 731:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *pTmp; - 732:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; - 733:.\Generated_Source\PSoC5/USBFS_std.c **** - 734:.\Generated_Source\PSoC5/USBFS_std.c **** - 735:.\Generated_Source\PSoC5/USBFS_std.c **** /* Init Endpoints and Device Status if configured */ - 736:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_configuration > 0u) - 737:.\Generated_Source\PSoC5/USBFS_std.c **** { - 738:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 739:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = &pTmp[1u]; - 740:.\Generated_Source\PSoC5/USBFS_std.c **** ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - 741:.\Generated_Source\PSoC5/USBFS_std.c **** - 742:.\Generated_Source\PSoC5/USBFS_std.c **** /* Do not touch EP which doesn't need reconfiguration */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 17 - - - 743:.\Generated_Source\PSoC5/USBFS_std.c **** /* When Alt setting changed, the only required endpoints need to be reconfigured */ - 744:.\Generated_Source\PSoC5/USBFS_std.c **** /* p_list points the endpoint setting table. */ - 745:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; - 746:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 747:.\Generated_Source\PSoC5/USBFS_std.c **** { - 748:.\Generated_Source\PSoC5/USBFS_std.c **** /*If Alt setting changed and new is same with EP Alt */ - 749:.\Generated_Source\PSoC5/USBFS_std.c **** if((USBFS_interfaceSetting[pEP->interface] != - 750:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[pEP->interface] ) && - 751:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && - 752:.\Generated_Source\PSoC5/USBFS_std.c **** (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) - 753:.\Generated_Source\PSoC5/USBFS_std.c **** { - 754:.\Generated_Source\PSoC5/USBFS_std.c **** cur_ep = pEP->addr & USBFS_DIR_UNUSED; - 755:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 756:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - 757:.\Generated_Source\PSoC5/USBFS_std.c **** if ((pEP->addr & USBFS_DIR_IN) != 0u) - 758:.\Generated_Source\PSoC5/USBFS_std.c **** { - 759:.\Generated_Source\PSoC5/USBFS_std.c **** /* IN Endpoint */ - 760:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - 761:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 762:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - 763:.\Generated_Source\PSoC5/USBFS_std.c **** } - 764:.\Generated_Source\PSoC5/USBFS_std.c **** else - 765:.\Generated_Source\PSoC5/USBFS_std.c **** { - 766:.\Generated_Source\PSoC5/USBFS_std.c **** /* OUT Endpoint */ - 767:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; - 768:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 769:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - 770:.\Generated_Source\PSoC5/USBFS_std.c **** } - 771:.\Generated_Source\PSoC5/USBFS_std.c **** /* Change the SIE mode for the selected EP to NAK ALL */ - 772:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); - 773:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - 774:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].addr = pEP->addr; - 775:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].attrib = pEP->attributes; - 776:.\Generated_Source\PSoC5/USBFS_std.c **** - 777:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear the data toggle */ - 778:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epToggle = 0u; - 779:.\Generated_Source\PSoC5/USBFS_std.c **** - 780:.\Generated_Source\PSoC5/USBFS_std.c **** /* Dynamic reconfiguration for mode 3 transfer */ - 781:.\Generated_Source\PSoC5/USBFS_std.c **** #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - 782:.\Generated_Source\PSoC5/USBFS_std.c **** /* In_data_rdy for selected EP should be set to 0 */ - 783:.\Generated_Source\PSoC5/USBFS_std.c **** * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; - 784:.\Generated_Source\PSoC5/USBFS_std.c **** - 785:.\Generated_Source\PSoC5/USBFS_std.c **** /* write the EP number for which reconfiguration is required */ - 786:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) << - 787:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_DYN_RECONFIG_EP_SHIFT; - 788:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set the dyn_config_en bit in dynamic reconfiguration register */ - 789:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; - 790:.\Generated_Source\PSoC5/USBFS_std.c **** /* wait for the dyn_config_rdy bit to set by the block, - 791:.\Generated_Source\PSoC5/USBFS_std.c **** * this bit will be set to 1 when block is ready for reconfiguration. - 792:.\Generated_Source\PSoC5/USBFS_std.c **** */ - 793:.\Generated_Source\PSoC5/USBFS_std.c **** while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u) - 794:.\Generated_Source\PSoC5/USBFS_std.c **** { - 795:.\Generated_Source\PSoC5/USBFS_std.c **** ; - 796:.\Generated_Source\PSoC5/USBFS_std.c **** } - 797:.\Generated_Source\PSoC5/USBFS_std.c **** /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */ - 798:.\Generated_Source\PSoC5/USBFS_std.c **** /* Change EP Type with new direction */ - 799:.\Generated_Source\PSoC5/USBFS_std.c **** if((pEP->addr & USBFS_DIR_IN) == 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 18 - - - 800:.\Generated_Source\PSoC5/USBFS_std.c **** { - 801:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1)); - 802:.\Generated_Source\PSoC5/USBFS_std.c **** } - 803:.\Generated_Source\PSoC5/USBFS_std.c **** else - 804:.\Generated_Source\PSoC5/USBFS_std.c **** { - 805:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1)); - 806:.\Generated_Source\PSoC5/USBFS_std.c **** } - 807:.\Generated_Source\PSoC5/USBFS_std.c **** /* dynamic reconfiguration enable bit cleared, pointers and control/status - 808:.\Generated_Source\PSoC5/USBFS_std.c **** * signals for the selected EP is cleared/re-initialized on negative edge - 809:.\Generated_Source\PSoC5/USBFS_std.c **** * of dynamic reconfiguration enable bit). - 810:.\Generated_Source\PSoC5/USBFS_std.c **** */ - 811:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE; - 812:.\Generated_Source\PSoC5/USBFS_std.c **** /* The main loop has to re-enable DMA and OUT endpoint*/ - 813:.\Generated_Source\PSoC5/USBFS_std.c **** #else - 814:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), - 815:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].bufferSize >> 8u); - 816:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), - 817:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].bufferSize & 0xFFu - 818:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri), - 819:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].buffOffset & 0xFFu - 820:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri), - 821:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].buffOffset >> 8u); - 822:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri), - 823:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].buffOffset & 0xFFu - 824:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri), - 825:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].buffOffset >> 8u); - 826:.\Generated_Source\PSoC5/USBFS_std.c **** #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - 827:.\Generated_Source\PSoC5/USBFS_std.c **** } - 828:.\Generated_Source\PSoC5/USBFS_std.c **** /* Get next EP element */ - 829:.\Generated_Source\PSoC5/USBFS_std.c **** pEP = &pEP[1u]; - 830:.\Generated_Source\PSoC5/USBFS_std.c **** } - 831:.\Generated_Source\PSoC5/USBFS_std.c **** } /* USBFS_configuration > 0 */ - 832:.\Generated_Source\PSoC5/USBFS_std.c **** } - 833:.\Generated_Source\PSoC5/USBFS_std.c **** - 834:.\Generated_Source\PSoC5/USBFS_std.c **** - 835:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 836:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_GetConfigTablePtr - 837:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 838:.\Generated_Source\PSoC5/USBFS_std.c **** * - 839:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 840:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine returns a pointer a configuration table entry - 841:.\Generated_Source\PSoC5/USBFS_std.c **** * - 842:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 843:.\Generated_Source\PSoC5/USBFS_std.c **** * c: Configuration Index - 844:.\Generated_Source\PSoC5/USBFS_std.c **** * - 845:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 846:.\Generated_Source\PSoC5/USBFS_std.c **** * Device Descriptor pointer. - 847:.\Generated_Source\PSoC5/USBFS_std.c **** * - 848:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 849:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c) - 850:.\Generated_Source\PSoC5/USBFS_std.c **** - 851:.\Generated_Source\PSoC5/USBFS_std.c **** { - 160 .loc 1 851 0 - 161 .cfi_startproc - 162 @ args = 0, pretend = 0, frame = 0 - 163 @ frame_needed = 0, uses_anonymous_args = 0 - 164 @ link register save eliminated. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 19 - - - 165 .LVL8: - 852:.\Generated_Source\PSoC5/USBFS_std.c **** /* Device Table */ - 853:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *pTmp; - 854:.\Generated_Source\PSoC5/USBFS_std.c **** - 855:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; - 166 .loc 1 855 0 - 167 0000 044B ldr r3, .L13 - 168 0002 0549 ldr r1, .L13+4 - 169 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 170 .LVL9: - 171 0006 01EBC203 add r3, r1, r2, lsl #3 - 856:.\Generated_Source\PSoC5/USBFS_std.c **** - 857:.\Generated_Source\PSoC5/USBFS_std.c **** /* The first entry points to the Device Descriptor, - 858:.\Generated_Source\PSoC5/USBFS_std.c **** * the rest configuration entries. - 859:.\Generated_Source\PSoC5/USBFS_std.c **** */ - 860:.\Generated_Source\PSoC5/USBFS_std.c **** return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list ); - 172 .loc 1 860 0 - 173 000a 5A68 ldr r2, [r3, #4] - 174 .LVL10: - 175 000c 02EBC000 add r0, r2, r0, lsl #3 - 176 .LVL11: - 861:.\Generated_Source\PSoC5/USBFS_std.c **** } - 177 .loc 1 861 0 - 178 0010 C068 ldr r0, [r0, #12] - 179 0012 7047 bx lr - 180 .L14: - 181 .align 2 - 182 .L13: - 183 0014 00000000 .word USBFS_device - 184 0018 00000000 .word USBFS_TABLE - 185 .cfi_endproc - 186 .LFE4: - 187 .size USBFS_GetConfigTablePtr, .-USBFS_GetConfigTablePtr - 188 .section .text.USBFS_ConfigAltChanged,"ax",%progbits - 189 .align 1 - 190 .global USBFS_ConfigAltChanged - 191 .thumb - 192 .thumb_func - 193 .type USBFS_ConfigAltChanged, %function - 194 USBFS_ConfigAltChanged: - 195 .LFB3: - 724:.\Generated_Source\PSoC5/USBFS_std.c **** { - 196 .loc 1 724 0 - 197 .cfi_startproc - 198 @ args = 0, pretend = 0, frame = 0 - 199 @ frame_needed = 0, uses_anonymous_args = 0 - 200 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 201 .LCFI1: - 202 .cfi_def_cfa_offset 24 - 203 .cfi_offset 3, -24 - 204 .cfi_offset 4, -20 - 205 .cfi_offset 5, -16 - 206 .cfi_offset 6, -12 - 207 .cfi_offset 7, -8 - 208 .cfi_offset 14, -4 - 736:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_configuration > 0u) - 209 .loc 1 736 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 20 - - - 210 0002 3D4B ldr r3, .L28 - 211 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 212 0006 002A cmp r2, #0 - 213 0008 74D0 beq .L15 - 738:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 214 .loc 1 738 0 - 215 000a 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 216 000c 411E subs r1, r0, #1 - 217 000e C8B2 uxtb r0, r1 - 218 0010 FFF7FEFF bl USBFS_GetConfigTablePtr - 219 .LVL12: - 723:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_ConfigAltChanged(void) - 220 .loc 1 723 0 - 221 0014 C368 ldr r3, [r0, #12] - 740:.\Generated_Source\PSoC5/USBFS_std.c **** ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - 222 .loc 1 740 0 - 223 0016 057A ldrb r5, [r0, #8] @ zero_extendqisi2 - 224 .LVL13: - 723:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_ConfigAltChanged(void) - 225 .loc 1 723 0 - 226 0018 0833 adds r3, r3, #8 - 227 .LVL14: - 746:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 228 .loc 1 746 0 - 229 001a 0020 movs r0, #0 - 230 .LVL15: - 231 .L17: - 746:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 232 .loc 1 746 0 is_stmt 0 discriminator 1 - 233 001c A842 cmp r0, r5 - 234 001e 69D0 beq .L15 - 235 .L23: - 749:.\Generated_Source\PSoC5/USBFS_std.c **** if((USBFS_interfaceSetting[pEP->interface] != - 236 .loc 1 749 0 is_stmt 1 - 237 0020 13F8082C ldrb r2, [r3, #-8] @ zero_extendqisi2 - 238 0024 3549 ldr r1, .L28+4 - 750:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[pEP->interface] ) && - 239 .loc 1 750 0 - 240 0026 364C ldr r4, .L28+8 - 749:.\Generated_Source\PSoC5/USBFS_std.c **** if((USBFS_interfaceSetting[pEP->interface] != - 241 .loc 1 749 0 - 242 0028 8E5C ldrb r6, [r1, r2] @ zero_extendqisi2 - 750:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[pEP->interface] ) && - 243 .loc 1 750 0 - 244 002a A45C ldrb r4, [r4, r2] @ zero_extendqisi2 - 749:.\Generated_Source\PSoC5/USBFS_std.c **** if((USBFS_interfaceSetting[pEP->interface] != - 245 .loc 1 749 0 - 246 002c A642 cmp r6, r4 - 247 002e 5DD0 beq .L18 - 751:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && - 248 .loc 1 751 0 - 249 0030 895C ldrb r1, [r1, r2] @ zero_extendqisi2 - 750:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[pEP->interface] ) && - 250 .loc 1 750 0 - 251 0032 13F8074C ldrb r4, [r3, #-7] @ zero_extendqisi2 - 252 0036 8C42 cmp r4, r1 - 253 0038 58D1 bne .L18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 21 - - - 752:.\Generated_Source\PSoC5/USBFS_std.c **** (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) - 254 .loc 1 752 0 - 255 003a 3249 ldr r1, .L28+12 - 256 003c 0978 ldrb r1, [r1, #0] @ zero_extendqisi2 - 751:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && - 257 .loc 1 751 0 - 258 003e 8A42 cmp r2, r1 - 259 0040 54D1 bne .L18 - 754:.\Generated_Source\PSoC5/USBFS_std.c **** cur_ep = pEP->addr & USBFS_DIR_UNUSED; - 260 .loc 1 754 0 - 261 0042 13F8067C ldrb r7, [r3, #-6] @ zero_extendqisi2 - 262 0046 07F07F02 and r2, r7, #127 - 263 .LVL16: - 755:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 264 .loc 1 755 0 - 265 004a 561E subs r6, r2, #1 - 266 004c 3401 lsls r4, r6, #4 - 267 004e E1B2 uxtb r1, r4 - 268 .LVL17: - 756:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - 269 .loc 1 756 0 - 270 0050 13F8056C ldrb r6, [r3, #-5] @ zero_extendqisi2 - 271 0054 2C4C ldr r4, .L28+16 - 272 .LVL18: - 757:.\Generated_Source\PSoC5/USBFS_std.c **** if ((pEP->addr & USBFS_DIR_IN) != 0u) - 273 .loc 1 757 0 - 274 0056 17F0800F tst r7, #128 - 275 005a 4FF00C07 mov r7, #12 - 756:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - 276 .loc 1 756 0 - 277 005e 06F00306 and r6, r6, #3 - 278 .LVL19: - 760:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - 279 .loc 1 760 0 - 280 0062 07FB0244 mla r4, r7, r2, r4 - 757:.\Generated_Source\PSoC5/USBFS_std.c **** if ((pEP->addr & USBFS_DIR_IN) != 0u) - 281 .loc 1 757 0 - 282 0066 06D0 beq .L19 - 760:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - 283 .loc 1 760 0 - 284 0068 0127 movs r7, #1 - 285 006a 6770 strb r7, [r4, #1] - 761:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 286 .loc 1 761 0 - 287 006c BE42 cmp r6, r7 - 288 006e 14BF ite ne - 289 0070 0D26 movne r6, #13 - 290 0072 0726 moveq r6, #7 - 291 .LVL20: - 292 0074 05E0 b .L27 - 293 .LVL21: - 294 .L19: - 767:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; - 295 .loc 1 767 0 - 296 0076 0027 movs r7, #0 - 297 0078 6770 strb r7, [r4, #1] - 768:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 22 - - - 298 .loc 1 768 0 - 299 007a 012E cmp r6, #1 - 300 007c 14BF ite ne - 301 007e 0926 movne r6, #9 - 302 0080 0526 moveq r6, #5 - 303 .LVL22: - 304 .L27: - 305 0082 6671 strb r6, [r4, #5] - 772:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); - 306 .loc 1 772 0 - 307 0084 214C ldr r4, .L28+20 - 308 0086 0126 movs r6, #1 - 309 0088 0F19 adds r7, r1, r4 - 773:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - 310 .loc 1 773 0 - 311 008a 0C24 movs r4, #12 - 312 008c 5443 muls r4, r2, r4 - 772:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); - 313 .loc 1 772 0 - 314 008e 3E70 strb r6, [r7, #0] - 773:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - 315 .loc 1 773 0 - 316 0090 1D4E ldr r6, .L28+16 - 317 0092 33F8047C ldrh r7, [r3, #-4] - 318 0096 3219 adds r2, r6, r4 - 319 .LVL23: - 320 0098 1781 strh r7, [r2, #8] @ movhi - 774:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].addr = pEP->addr; - 321 .loc 1 774 0 - 322 009a 13F8067C ldrb r7, [r3, #-6] @ zero_extendqisi2 - 323 009e 1771 strb r7, [r2, #4] - 775:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].attrib = pEP->attributes; - 324 .loc 1 775 0 - 325 00a0 13F8057C ldrb r7, [r3, #-5] @ zero_extendqisi2 - 326 00a4 3755 strb r7, [r6, r4] - 778:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[cur_ep].epToggle = 0u; - 327 .loc 1 778 0 - 328 00a6 0026 movs r6, #0 - 329 00a8 D670 strb r6, [r2, #3] - 814:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), - 330 .loc 1 814 0 - 331 00aa 1689 ldrh r6, [r2, #8] - 332 00ac 184C ldr r4, .L28+24 - 333 00ae C6F30726 ubfx r6, r6, #8, #8 - 334 00b2 0C19 adds r4, r1, r4 - 335 00b4 2670 strb r6, [r4, #0] - 816:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), - 336 .loc 1 816 0 - 337 00b6 1689 ldrh r6, [r2, #8] - 338 00b8 164C ldr r4, .L28+28 - 339 00ba F6B2 uxtb r6, r6 - 340 00bc 0C19 adds r4, r1, r4 - 341 00be 2670 strb r6, [r4, #0] - 818:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri), - 342 .loc 1 818 0 - 343 00c0 D688 ldrh r6, [r2, #6] - 344 00c2 154C ldr r4, .L28+32 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 23 - - - 345 00c4 F6B2 uxtb r6, r6 - 346 00c6 0C19 adds r4, r1, r4 - 347 00c8 2670 strb r6, [r4, #0] - 820:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri), - 348 .loc 1 820 0 - 349 00ca D688 ldrh r6, [r2, #6] - 350 00cc 134C ldr r4, .L28+36 - 351 00ce C6F30726 ubfx r6, r6, #8, #8 - 352 00d2 0C19 adds r4, r1, r4 - 353 00d4 2670 strb r6, [r4, #0] - 822:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri), - 354 .loc 1 822 0 - 355 00d6 D688 ldrh r6, [r2, #6] - 356 00d8 114C ldr r4, .L28+40 - 357 00da F6B2 uxtb r6, r6 - 358 00dc 0C19 adds r4, r1, r4 - 359 00de 2670 strb r6, [r4, #0] - 824:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri), - 360 .loc 1 824 0 - 361 00e0 104C ldr r4, .L28+44 - 362 00e2 0C19 adds r4, r1, r4 - 363 00e4 D188 ldrh r1, [r2, #6] - 364 .LVL24: - 365 00e6 C1F30722 ubfx r2, r1, #8, #8 - 366 00ea 2270 strb r2, [r4, #0] - 367 .LVL25: - 368 .L18: - 746:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 369 .loc 1 746 0 - 370 00ec 0130 adds r0, r0, #1 - 371 .LVL26: - 372 00ee C0B2 uxtb r0, r0 - 373 .LVL27: - 374 00f0 0833 adds r3, r3, #8 - 375 00f2 93E7 b .L17 - 376 .LVL28: - 377 .L15: - 378 00f4 F8BD pop {r3, r4, r5, r6, r7, pc} - 379 .L29: - 380 00f6 00BF .align 2 - 381 .L28: - 382 00f8 00000000 .word USBFS_configuration - 383 00fc 00000000 .word USBFS_interfaceSetting - 384 0100 00000000 .word USBFS_interfaceSetting_last - 385 0104 04600040 .word 1073766404 - 386 0108 00000000 .word USBFS_EP - 387 010c 0E600040 .word 1073766414 - 388 0110 0C600040 .word 1073766412 - 389 0114 0D600040 .word 1073766413 - 390 0118 86600040 .word 1073766534 - 391 011c 87600040 .word 1073766535 - 392 0120 84600040 .word 1073766532 - 393 0124 85600040 .word 1073766533 - 394 .cfi_endproc - 395 .LFE3: - 396 .size USBFS_ConfigAltChanged, .-USBFS_ConfigAltChanged - 397 .section .text.USBFS_GetDeviceTablePtr,"ax",%progbits - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 24 - - - 398 .align 1 - 399 .global USBFS_GetDeviceTablePtr - 400 .thumb - 401 .thumb_func - 402 .type USBFS_GetDeviceTablePtr, %function - 403 USBFS_GetDeviceTablePtr: - 404 .LFB5: - 862:.\Generated_Source\PSoC5/USBFS_std.c **** - 863:.\Generated_Source\PSoC5/USBFS_std.c **** - 864:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 865:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_GetDeviceTablePtr - 866:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 867:.\Generated_Source\PSoC5/USBFS_std.c **** * - 868:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 869:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine returns a pointer to the Device table - 870:.\Generated_Source\PSoC5/USBFS_std.c **** * - 871:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 872:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 873:.\Generated_Source\PSoC5/USBFS_std.c **** * - 874:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 875:.\Generated_Source\PSoC5/USBFS_std.c **** * Device Table pointer - 876:.\Generated_Source\PSoC5/USBFS_std.c **** * - 877:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 878:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) - 879:.\Generated_Source\PSoC5/USBFS_std.c **** - 880:.\Generated_Source\PSoC5/USBFS_std.c **** { - 405 .loc 1 880 0 - 406 .cfi_startproc - 407 @ args = 0, pretend = 0, frame = 0 - 408 @ frame_needed = 0, uses_anonymous_args = 0 - 409 @ link register save eliminated. - 881:.\Generated_Source\PSoC5/USBFS_std.c **** /* Device Table */ - 882:.\Generated_Source\PSoC5/USBFS_std.c **** return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); - 410 .loc 1 882 0 - 411 0000 034B ldr r3, .L31 - 412 0002 0448 ldr r0, .L31+4 - 413 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 414 0006 00EBC201 add r1, r0, r2, lsl #3 - 883:.\Generated_Source\PSoC5/USBFS_std.c **** } - 415 .loc 1 883 0 - 416 000a 4868 ldr r0, [r1, #4] - 417 000c 7047 bx lr - 418 .L32: - 419 000e 00BF .align 2 - 420 .L31: - 421 0010 00000000 .word USBFS_device - 422 0014 00000000 .word USBFS_TABLE - 423 .cfi_endproc - 424 .LFE5: - 425 .size USBFS_GetDeviceTablePtr, .-USBFS_GetDeviceTablePtr - 426 .section .text.USBFS_GetInterfaceClassTablePtr,"ax",%progbits - 427 .align 1 - 428 .global USBFS_GetInterfaceClassTablePtr - 429 .thumb - 430 .thumb_func - 431 .type USBFS_GetInterfaceClassTablePtr, %function - 432 USBFS_GetInterfaceClassTablePtr: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 25 - - - 433 .LFB6: - 884:.\Generated_Source\PSoC5/USBFS_std.c **** - 885:.\Generated_Source\PSoC5/USBFS_std.c **** - 886:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 887:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USB_GetInterfaceClassTablePtr - 888:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 889:.\Generated_Source\PSoC5/USBFS_std.c **** * - 890:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 891:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine returns Interface Class table pointer, which contains - 892:.\Generated_Source\PSoC5/USBFS_std.c **** * the relation between interface number and interface class. - 893:.\Generated_Source\PSoC5/USBFS_std.c **** * - 894:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 895:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 896:.\Generated_Source\PSoC5/USBFS_std.c **** * - 897:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 898:.\Generated_Source\PSoC5/USBFS_std.c **** * Interface Class table pointer. - 899:.\Generated_Source\PSoC5/USBFS_std.c **** * - 900:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 901:.\Generated_Source\PSoC5/USBFS_std.c **** const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) - 902:.\Generated_Source\PSoC5/USBFS_std.c **** - 903:.\Generated_Source\PSoC5/USBFS_std.c **** { - 434 .loc 1 903 0 - 435 .cfi_startproc - 436 @ args = 0, pretend = 0, frame = 0 - 437 @ frame_needed = 0, uses_anonymous_args = 0 - 438 0000 08B5 push {r3, lr} - 439 .LCFI2: - 440 .cfi_def_cfa_offset 8 - 441 .cfi_offset 3, -8 - 442 .cfi_offset 14, -4 - 904:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *pTmp; - 905:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 currentInterfacesNum; - 906:.\Generated_Source\PSoC5/USBFS_std.c **** - 907:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 443 .loc 1 907 0 - 444 0002 064B ldr r3, .L34 - 445 0004 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 446 0006 411E subs r1, r0, #1 - 447 0008 C8B2 uxtb r0, r1 - 448 000a FFF7FEFF bl USBFS_GetConfigTablePtr - 449 .LVL29: - 908:.\Generated_Source\PSoC5/USBFS_std.c **** currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; - 450 .loc 1 908 0 - 451 000e 4268 ldr r2, [r0, #4] - 909:.\Generated_Source\PSoC5/USBFS_std.c **** /* Third entry in the LUT starts the Interface Table pointers */ - 910:.\Generated_Source\PSoC5/USBFS_std.c **** /* The INTERFACE_CLASS table is located after all interfaces */ - 911:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = &pTmp[currentInterfacesNum + 2u]; - 452 .loc 1 911 0 - 453 0010 1379 ldrb r3, [r2, #4] @ zero_extendqisi2 - 454 .LVL30: - 912:.\Generated_Source\PSoC5/USBFS_std.c **** return( (const uint8 CYCODE *) pTmp->p_list ); - 455 .loc 1 912 0 - 456 0012 00EBC300 add r0, r0, r3, lsl #3 - 457 .LVL31: - 913:.\Generated_Source\PSoC5/USBFS_std.c **** } - 458 .loc 1 913 0 - 459 0016 4069 ldr r0, [r0, #20] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 26 - - - 460 0018 08BD pop {r3, pc} - 461 .L35: - 462 001a 00BF .align 2 - 463 .L34: - 464 001c 00000000 .word USBFS_configuration - 465 .cfi_endproc - 466 .LFE6: - 467 .size USBFS_GetInterfaceClassTablePtr, .-USBFS_GetInterfaceClassTablePtr - 468 .section .text.USBFS_Config,"ax",%progbits - 469 .align 1 - 470 .global USBFS_Config - 471 .thumb - 472 .thumb_func - 473 .type USBFS_Config, %function - 474 USBFS_Config: - 475 .LFB2: - 476:.\Generated_Source\PSoC5/USBFS_std.c **** { - 476 .loc 1 476 0 - 477 .cfi_startproc - 478 @ args = 0, pretend = 0, frame = 0 - 479 @ frame_needed = 0, uses_anonymous_args = 0 - 480 .LVL32: - 481 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 482 .LCFI3: - 483 .cfi_def_cfa_offset 24 - 484 .cfi_offset 3, -24 - 485 .cfi_offset 4, -20 - 486 .cfi_offset 5, -16 - 487 .cfi_offset 6, -12 - 488 .cfi_offset 7, -8 - 489 .cfi_offset 14, -4 - 476:.\Generated_Source\PSoC5/USBFS_std.c **** { - 490 .loc 1 476 0 - 491 0002 0021 movs r1, #0 - 492 .LVL33: - 493 .L37: - 492:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].attrib = 0u; - 494 .loc 1 492 0 discriminator 2 - 495 0004 0C24 movs r4, #12 - 496 0006 4C43 muls r4, r1, r4 - 497 0008 514D ldr r5, .L68 - 498 000a 0131 adds r1, r1, #1 - 499 000c 0023 movs r3, #0 - 500 000e 2A19 adds r2, r5, r4 - 490:.\Generated_Source\PSoC5/USBFS_std.c **** for (ep = 0u; ep < USBFS_MAX_EP; ep++) - 501 .loc 1 490 0 discriminator 2 - 502 0010 0929 cmp r1, #9 - 492:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].attrib = 0u; - 503 .loc 1 492 0 discriminator 2 - 504 0012 2B55 strb r3, [r5, r4] - 493:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].hwEpState = 0u; - 505 .loc 1 493 0 discriminator 2 - 506 0014 9370 strb r3, [r2, #2] - 497:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].bufferSize = 0u; - 507 .loc 1 497 0 discriminator 2 - 508 0016 02F10804 add r4, r2, #8 - 494:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 27 - - - 509 .loc 1 494 0 discriminator 2 - 510 001a 5370 strb r3, [r2, #1] - 495:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epToggle = 0u; - 511 .loc 1 495 0 discriminator 2 - 512 001c D370 strb r3, [r2, #3] - 496:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; - 513 .loc 1 496 0 discriminator 2 - 514 001e 5371 strb r3, [r2, #5] - 497:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].bufferSize = 0u; - 515 .loc 1 497 0 discriminator 2 - 516 0020 1381 strh r3, [r2, #8] @ movhi - 498:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].interface = 0u; - 517 .loc 1 498 0 discriminator 2 - 518 0022 9372 strb r3, [r2, #10] - 490:.\Generated_Source\PSoC5/USBFS_std.c **** for (ep = 0u; ep < USBFS_MAX_EP; ep++) - 519 .loc 1 490 0 discriminator 2 - 520 0024 EED1 bne .L37 - 503:.\Generated_Source\PSoC5/USBFS_std.c **** if(clearAltSetting != 0u) - 521 .loc 1 503 0 - 522 0026 18B1 cbz r0, .L38 - 507:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting[i] = 0x00u; - 523 .loc 1 507 0 discriminator 2 - 524 0028 4A48 ldr r0, .L68+4 - 525 .LVL34: - 508:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[i] = 0x00u; - 526 .loc 1 508 0 discriminator 2 - 527 002a 4B4A ldr r2, .L68+8 - 507:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting[i] = 0x00u; - 528 .loc 1 507 0 discriminator 2 - 529 002c 0370 strb r3, [r0, #0] - 508:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[i] = 0x00u; - 530 .loc 1 508 0 discriminator 2 - 531 002e 1370 strb r3, [r2, #0] - 532 .LVL35: - 533 .L38: - 513:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_configuration > 0u) - 534 .loc 1 513 0 - 535 0030 4A4B ldr r3, .L68+12 - 536 0032 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 537 0034 0029 cmp r1, #0 - 538 0036 00F08A80 beq .L36 - 515:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 539 .loc 1 515 0 - 540 003a 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 541 003c 601E subs r0, r4, #1 - 542 003e C0B2 uxtb r0, r0 - 543 0040 FFF7FEFF bl USBFS_GetConfigTablePtr - 544 .LVL36: - 518:.\Generated_Source\PSoC5/USBFS_std.c **** if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) - 545 .loc 1 518 0 - 546 0044 4268 ldr r2, [r0, #4] - 547 0046 D379 ldrb r3, [r2, #7] @ zero_extendqisi2 - 548 0048 03F04001 and r1, r3, #64 - 549 004c CCB2 uxtb r4, r1 - 550 004e 444B ldr r3, .L68+16 - 551 0050 1CB1 cbz r4, .L40 - 520:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 28 - - - 552 .loc 1 520 0 - 553 0052 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 554 0054 44F00101 orr r1, r4, #1 - 555 .LVL37: - 556 0058 02E0 b .L64 - 557 .L40: - 524:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; - 558 .loc 1 524 0 - 559 005a 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 560 005c 02F0FE01 and r1, r2, #254 - 561 .L64: - 528:.\Generated_Source\PSoC5/USBFS_std.c **** ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - 562 .loc 1 528 0 - 563 0060 047A ldrb r4, [r0, #8] @ zero_extendqisi2 - 564 .LVL38: - 524:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; - 565 .loc 1 524 0 - 566 0062 1970 strb r1, [r3, #0] - 567 .LVL39: - 528:.\Generated_Source\PSoC5/USBFS_std.c **** ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - 568 .loc 1 528 0 - 569 0064 0122 movs r2, #1 - 570 .LVL40: - 571 .L52: - 475:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_Config(uint8 clearAltSetting) - 572 .loc 1 475 0 - 573 0066 C368 ldr r3, [r0, #12] - 601:.\Generated_Source\PSoC5/USBFS_std.c **** for (cur_ep = 0u; cur_ep < ep; cur_ep++) - 574 .loc 1 601 0 - 575 0068 0021 movs r1, #0 - 576 .LVL41: - 475:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_Config(uint8 clearAltSetting) - 577 .loc 1 475 0 - 578 006a 0833 adds r3, r3, #8 - 579 .LVL42: - 580 .L42: - 601:.\Generated_Source\PSoC5/USBFS_std.c **** for (cur_ep = 0u; cur_ep < ep; cur_ep++) - 581 .loc 1 601 0 discriminator 1 - 582 006c A142 cmp r1, r4 - 583 006e 43D0 beq .L66 - 584 .L51: - 604:.\Generated_Source\PSoC5/USBFS_std.c **** if(i == (pEP->addr & USBFS_DIR_UNUSED)) - 585 .loc 1 604 0 - 586 0070 13F8065C ldrb r5, [r3, #-6] @ zero_extendqisi2 - 587 0074 05F07F06 and r6, r5, #127 - 588 0078 B242 cmp r2, r6 - 589 007a 39D1 bne .L44 - 606:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_EP[i].bufferSize < pEP->bufferSize) - 590 .loc 1 606 0 - 591 007c 344E ldr r6, .L68 - 592 007e 0C27 movs r7, #12 - 593 0080 07FB0266 mla r6, r7, r2, r6 - 594 0084 B6F808E0 ldrh lr, [r6, #8] - 595 0088 33F8047C ldrh r7, [r3, #-4] - 596 008c 1FFA8EFC uxth ip, lr - 597 0090 BC45 cmp ip, r7 - 608:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].bufferSize = pEP->bufferSize; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 29 - - - 598 .loc 1 608 0 - 599 0092 38BF it cc - 600 0094 3781 strhcc r7, [r6, #8] @ movhi - 611:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) - 601 .loc 1 611 0 - 602 0096 13F8086C ldrb r6, [r3, #-8] @ zero_extendqisi2 - 603 009a 2E4F ldr r7, .L68+4 - 604 009c BE5D ldrb r6, [r7, r6] @ zero_extendqisi2 - 605 009e 13F8077C ldrb r7, [r3, #-7] @ zero_extendqisi2 - 606 00a2 B742 cmp r7, r6 - 607 00a4 24D1 bne .L44 - 613:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - 608 .loc 1 613 0 - 609 00a6 13F8056C ldrb r6, [r3, #-5] @ zero_extendqisi2 - 614:.\Generated_Source\PSoC5/USBFS_std.c **** if ((pEP->addr & USBFS_DIR_IN) != 0u) - 610 .loc 1 614 0 - 611 00aa 15F0800F tst r5, #128 - 612 00ae 284D ldr r5, .L68 - 613 00b0 4FF00C07 mov r7, #12 - 613:.\Generated_Source\PSoC5/USBFS_std.c **** ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - 614 .loc 1 613 0 - 615 00b4 06F00306 and r6, r6, #3 - 616 .LVL43: - 617:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; - 617 .loc 1 617 0 - 618 00b8 07FB0255 mla r5, r7, r2, r5 - 614:.\Generated_Source\PSoC5/USBFS_std.c **** if ((pEP->addr & USBFS_DIR_IN) != 0u) - 619 .loc 1 614 0 - 620 00bc 06D0 beq .L47 - 617:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; - 621 .loc 1 617 0 - 622 00be 0127 movs r7, #1 - 623 00c0 6F70 strb r7, [r5, #1] - 618:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 624 .loc 1 618 0 - 625 00c2 BE42 cmp r6, r7 - 626 00c4 14BF ite ne - 627 00c6 0D26 movne r6, #13 - 628 00c8 0726 moveq r6, #7 - 629 .LVL44: - 630 00ca 05E0 b .L65 - 631 .LVL45: - 632 .L47: - 641:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; - 633 .loc 1 641 0 - 634 00cc 0027 movs r7, #0 - 635 00ce 6F70 strb r7, [r5, #1] - 642:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - 636 .loc 1 642 0 - 637 00d0 012E cmp r6, #1 - 638 00d2 14BF ite ne - 639 00d4 0926 movne r6, #9 - 640 00d6 0526 moveq r6, #5 - 641 .LVL46: - 642 .L65: - 643 00d8 6E71 strb r6, [r5, #5] - 662:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].addr = pEP->addr; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 30 - - - 644 .loc 1 662 0 - 645 00da 0C25 movs r5, #12 - 646 00dc 5543 muls r5, r2, r5 - 647 00de 1C4E ldr r6, .L68 - 648 00e0 13F806EC ldrb lr, [r3, #-6] @ zero_extendqisi2 - 649 00e4 7719 adds r7, r6, r5 - 650 00e6 87F804E0 strb lr, [r7, #4] - 663:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[i].attrib = pEP->attributes; - 651 .loc 1 663 0 - 652 00ea 13F8057C ldrb r7, [r3, #-5] @ zero_extendqisi2 - 653 00ee 7755 strb r7, [r6, r5] - 654 .LVL47: - 655 .L44: - 601:.\Generated_Source\PSoC5/USBFS_std.c **** for (cur_ep = 0u; cur_ep < ep; cur_ep++) - 656 .loc 1 601 0 - 657 00f0 0131 adds r1, r1, #1 - 658 .LVL48: - 659 00f2 C9B2 uxtb r1, r1 - 660 .LVL49: - 661 00f4 0833 adds r3, r3, #8 - 662 00f6 B9E7 b .L42 - 663 .L66: - 664 00f8 0132 adds r2, r2, #1 - 595:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) - 665 .loc 1 595 0 - 666 00fa 092A cmp r2, #9 - 667 00fc B3D1 bne .L52 - 668 .LVL50: - 669 00fe C368 ldr r3, [r0, #12] - 681:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 670 .loc 1 681 0 - 671 0100 0022 movs r2, #0 - 672 .LVL51: - 673 .L53: - 674 0102 0833 adds r3, r3, #8 - 681:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 675 .loc 1 681 0 is_stmt 0 discriminator 1 - 676 0104 A242 cmp r2, r4 - 677 0106 0DD0 beq .L67 - 678 .L54: - 684:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; - 679 .loc 1 684 0 is_stmt 1 discriminator 2 - 680 0108 13F8065C ldrb r5, [r3, #-6] @ zero_extendqisi2 - 681 010c 0C26 movs r6, #12 - 682 010e 05F07F01 and r1, r5, #127 - 683 0112 0F4D ldr r5, .L68 - 684 0114 13F8080C ldrb r0, [r3, #-8] @ zero_extendqisi2 - 685 0118 06FB0151 mla r1, r6, r1, r5 - 681:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 686 .loc 1 681 0 discriminator 2 - 687 011c 0132 adds r2, r2, #1 - 688 .LVL52: - 684:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; - 689 .loc 1 684 0 discriminator 2 - 690 011e 8872 strb r0, [r1, #10] - 681:.\Generated_Source\PSoC5/USBFS_std.c **** for (i = 0u; i < ep; i++) - 691 .loc 1 681 0 discriminator 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 31 - - - 692 0120 D2B2 uxtb r2, r2 - 693 .LVL53: - 694 0122 EEE7 b .L53 - 695 .L67: - 688:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); - 696 .loc 1 688 0 - 697 0124 FFF7FEFF bl USBFS_GetInterfaceClassTablePtr - 698 .LVL54: - 699 0128 0E4B ldr r3, .L68+20 - 483:.\Generated_Source\PSoC5/USBFS_std.c **** uint16 buffCount = 0u; - 700 .loc 1 483 0 - 701 012a 0022 movs r2, #0 - 688:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); - 702 .loc 1 688 0 - 703 012c 1860 str r0, [r3, #0] - 704 .LVL55: - 705 012e 0123 movs r3, #1 - 706 .LVL56: - 707 .L55: - 694:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].buffOffset = buffCount; - 708 .loc 1 694 0 discriminator 2 - 709 0130 0749 ldr r1, .L68 - 710 0132 0C20 movs r0, #12 - 711 0134 00FB0310 mla r0, r0, r3, r1 - 712 0138 C280 strh r2, [r0, #6] @ movhi - 695:.\Generated_Source\PSoC5/USBFS_std.c **** buffCount += USBFS_EP[ep].bufferSize; - 713 .loc 1 695 0 discriminator 2 - 714 013a 0189 ldrh r1, [r0, #8] - 715 013c 0133 adds r3, r3, #1 - 716 013e 5218 adds r2, r2, r1 - 692:.\Generated_Source\PSoC5/USBFS_std.c **** for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) - 717 .loc 1 692 0 discriminator 2 - 718 0140 092B cmp r3, #9 - 695:.\Generated_Source\PSoC5/USBFS_std.c **** buffCount += USBFS_EP[ep].bufferSize; - 719 .loc 1 695 0 discriminator 2 - 720 0142 92B2 uxth r2, r2 - 721 .LVL57: - 692:.\Generated_Source\PSoC5/USBFS_std.c **** for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) - 722 .loc 1 692 0 discriminator 2 - 723 0144 F4D1 bne .L55 - 702:.\Generated_Source\PSoC5/USBFS_std.c **** } - 724 .loc 1 702 0 - 725 0146 BDE8F840 pop {r3, r4, r5, r6, r7, lr} - 700:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ConfigReg(); - 726 .loc 1 700 0 - 727 014a FFF7FEBF b USBFS_ConfigReg - 728 .LVL58: - 729 .L36: - 730 014e F8BD pop {r3, r4, r5, r6, r7, pc} - 731 .L69: - 732 .align 2 - 733 .L68: - 734 0150 00000000 .word USBFS_EP - 735 0154 00000000 .word USBFS_interfaceSetting - 736 0158 00000000 .word USBFS_interfaceSetting_last - 737 015c 00000000 .word USBFS_configuration - 738 0160 00000000 .word USBFS_deviceStatus - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 32 - - - 739 0164 00000000 .word USBFS_interfaceClass - 740 .cfi_endproc - 741 .LFE2: - 742 .size USBFS_Config, .-USBFS_Config - 743 .section .text.USBFS_TerminateEP,"ax",%progbits - 744 .align 1 - 745 .global USBFS_TerminateEP - 746 .thumb - 747 .thumb_func - 748 .type USBFS_TerminateEP, %function - 749 USBFS_TerminateEP: - 750 .LFB7: - 914:.\Generated_Source\PSoC5/USBFS_std.c **** - 915:.\Generated_Source\PSoC5/USBFS_std.c **** - 916:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 917:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_TerminateEP - 918:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 919:.\Generated_Source\PSoC5/USBFS_std.c **** * - 920:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 921:.\Generated_Source\PSoC5/USBFS_std.c **** * This function terminates the specified USBFS endpoint. - 922:.\Generated_Source\PSoC5/USBFS_std.c **** * This function should be used before endpoint reconfiguration. - 923:.\Generated_Source\PSoC5/USBFS_std.c **** * - 924:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 925:.\Generated_Source\PSoC5/USBFS_std.c **** * Endpoint number. - 926:.\Generated_Source\PSoC5/USBFS_std.c **** * - 927:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 928:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 929:.\Generated_Source\PSoC5/USBFS_std.c **** * - 930:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: - 931:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - 932:.\Generated_Source\PSoC5/USBFS_std.c **** * - 933:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 934:.\Generated_Source\PSoC5/USBFS_std.c **** void USBFS_TerminateEP(uint8 ep) - 935:.\Generated_Source\PSoC5/USBFS_std.c **** { - 751 .loc 1 935 0 - 752 .cfi_startproc - 753 @ args = 0, pretend = 0, frame = 0 - 754 @ frame_needed = 0, uses_anonymous_args = 0 - 755 @ link register save eliminated. - 756 .LVL59: - 936:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ri; - 937:.\Generated_Source\PSoC5/USBFS_std.c **** - 938:.\Generated_Source\PSoC5/USBFS_std.c **** ep &= USBFS_DIR_UNUSED; - 757 .loc 1 938 0 - 758 0000 00F07F00 and r0, r0, #127 - 759 .LVL60: - 939:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 760 .loc 1 939 0 - 761 0004 421E subs r2, r0, #1 - 762 0006 D1B2 uxtb r1, r2 - 763 .LVL61: - 940:.\Generated_Source\PSoC5/USBFS_std.c **** - 941:.\Generated_Source\PSoC5/USBFS_std.c **** if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) - 764 .loc 1 941 0 - 765 0008 0729 cmp r1, #7 - 766 000a 14D8 bhi .L70 - 939:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 33 - - - 767 .loc 1 939 0 - 768 000c 0B01 lsls r3, r1, #4 - 769 000e DAB2 uxtb r2, r3 - 942:.\Generated_Source\PSoC5/USBFS_std.c **** { - 943:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set the endpoint Halt */ - 944:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); - 770 .loc 1 944 0 - 771 0010 094B ldr r3, .L74 - 772 0012 0C21 movs r1, #12 - 773 .LVL62: - 774 0014 01FB0030 mla r0, r1, r0, r3 - 775 .LVL63: - 776 0018 8378 ldrb r3, [r0, #2] @ zero_extendqisi2 - 777 001a 43F00103 orr r3, r3, #1 - 778 001e 8370 strb r3, [r0, #2] - 945:.\Generated_Source\PSoC5/USBFS_std.c **** - 946:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear the data toggle */ - 947:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epToggle = 0u; - 779 .loc 1 947 0 - 780 0020 0023 movs r3, #0 - 781 0022 C370 strb r3, [r0, #3] - 948:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED; - 782 .loc 1 948 0 - 783 0024 0223 movs r3, #2 - 784 0026 4370 strb r3, [r0, #1] - 949:.\Generated_Source\PSoC5/USBFS_std.c **** - 950:.\Generated_Source\PSoC5/USBFS_std.c **** if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - 785 .loc 1 950 0 - 786 0028 0079 ldrb r0, [r0, #4] @ zero_extendqisi2 - 787 002a 044B ldr r3, .L74+4 - 788 002c 10F0800F tst r0, #128 - 951:.\Generated_Source\PSoC5/USBFS_std.c **** { - 952:.\Generated_Source\PSoC5/USBFS_std.c **** /* IN Endpoint */ - 953:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); - 954:.\Generated_Source\PSoC5/USBFS_std.c **** } - 955:.\Generated_Source\PSoC5/USBFS_std.c **** else - 956:.\Generated_Source\PSoC5/USBFS_std.c **** { - 957:.\Generated_Source\PSoC5/USBFS_std.c **** /* OUT Endpoint */ - 958:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); - 789 .loc 1 958 0 - 790 0030 08BF it eq - 791 0032 0821 moveq r1, #8 - 792 0034 D154 strb r1, [r2, r3] - 793 .L70: - 794 0036 7047 bx lr - 795 .L75: - 796 .align 2 - 797 .L74: - 798 0038 00000000 .word USBFS_EP - 799 003c 0E600040 .word 1073766414 - 800 .cfi_endproc - 801 .LFE7: - 802 .size USBFS_TerminateEP, .-USBFS_TerminateEP - 803 .section .text.USBFS_SetEndpointHalt,"ax",%progbits - 804 .align 1 - 805 .global USBFS_SetEndpointHalt - 806 .thumb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 34 - - - 807 .thumb_func - 808 .type USBFS_SetEndpointHalt, %function - 809 USBFS_SetEndpointHalt: - 810 .LFB8: - 959:.\Generated_Source\PSoC5/USBFS_std.c **** } - 960:.\Generated_Source\PSoC5/USBFS_std.c **** } - 961:.\Generated_Source\PSoC5/USBFS_std.c **** } - 962:.\Generated_Source\PSoC5/USBFS_std.c **** - 963:.\Generated_Source\PSoC5/USBFS_std.c **** - 964:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* - 965:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_SetEndpointHalt - 966:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** - 967:.\Generated_Source\PSoC5/USBFS_std.c **** * - 968:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: - 969:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine handles set endpoint halt. - 970:.\Generated_Source\PSoC5/USBFS_std.c **** * - 971:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: - 972:.\Generated_Source\PSoC5/USBFS_std.c **** * None. - 973:.\Generated_Source\PSoC5/USBFS_std.c **** * - 974:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: - 975:.\Generated_Source\PSoC5/USBFS_std.c **** * requestHandled. - 976:.\Generated_Source\PSoC5/USBFS_std.c **** * - 977:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: - 978:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - 979:.\Generated_Source\PSoC5/USBFS_std.c **** * - 980:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ - 981:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 USBFS_SetEndpointHalt(void) - 982:.\Generated_Source\PSoC5/USBFS_std.c **** { - 811 .loc 1 982 0 - 812 .cfi_startproc - 813 @ args = 0, pretend = 0, frame = 0 - 814 @ frame_needed = 0, uses_anonymous_args = 0 - 815 @ link register save eliminated. - 816 .LVL64: - 983:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep; - 984:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ri; - 985:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 requestHandled = USBFS_FALSE; - 986:.\Generated_Source\PSoC5/USBFS_std.c **** - 987:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set endpoint halt */ - 988:.\Generated_Source\PSoC5/USBFS_std.c **** ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - 817 .loc 1 988 0 - 818 0000 124B ldr r3, .L81 - 819 0002 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 820 0004 01F07F01 and r1, r1, #127 - 821 .LVL65: - 989:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 822 .loc 1 989 0 - 823 0008 4A1E subs r2, r1, #1 - 824 000a D0B2 uxtb r0, r2 - 825 .LVL66: - 990:.\Generated_Source\PSoC5/USBFS_std.c **** - 991:.\Generated_Source\PSoC5/USBFS_std.c **** if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) - 826 .loc 1 991 0 - 827 000c 0728 cmp r0, #7 - 828 000e 1AD8 bhi .L77 - 989:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 829 .loc 1 989 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 35 - - - 830 0010 0301 lsls r3, r0, #4 - 831 0012 DAB2 uxtb r2, r3 - 992:.\Generated_Source\PSoC5/USBFS_std.c **** { - 993:.\Generated_Source\PSoC5/USBFS_std.c **** /* Set the endpoint Halt */ - 994:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); - 832 .loc 1 994 0 - 833 0014 0E4B ldr r3, .L81+4 - 834 0016 0C20 movs r0, #12 - 835 .LVL67: - 836 0018 00FB0130 mla r0, r0, r1, r3 - 837 001c 8178 ldrb r1, [r0, #2] @ zero_extendqisi2 - 838 .LVL68: - 839 001e 41F00103 orr r3, r1, #1 - 995:.\Generated_Source\PSoC5/USBFS_std.c **** - 996:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear the data toggle */ - 997:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epToggle = 0u; - 840 .loc 1 997 0 - 841 0022 0021 movs r1, #0 - 994:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); - 842 .loc 1 994 0 - 843 0024 8370 strb r3, [r0, #2] - 844 .loc 1 997 0 - 845 0026 C170 strb r1, [r0, #3] - 998:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].apiEpState |= USBFS_NO_EVENT_ALLOWED; - 846 .loc 1 998 0 - 847 0028 4378 ldrb r3, [r0, #1] @ zero_extendqisi2 - 848 002a 43F00201 orr r1, r3, #2 - 849 002e 4170 strb r1, [r0, #1] - 999:.\Generated_Source\PSoC5/USBFS_std.c **** -1000:.\Generated_Source\PSoC5/USBFS_std.c **** if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - 850 .loc 1 1000 0 - 851 0030 0079 ldrb r0, [r0, #4] @ zero_extendqisi2 - 852 0032 084B ldr r3, .L81+8 - 853 0034 10F0800F tst r0, #128 - 854 0038 01D0 beq .L78 -1001:.\Generated_Source\PSoC5/USBFS_std.c **** { -1002:.\Generated_Source\PSoC5/USBFS_std.c **** /* IN Endpoint */ -1003:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | - 855 .loc 1 1003 0 - 856 003a 8D21 movs r1, #141 - 857 003c 00E0 b .L80 - 858 .L78: -1004:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ACK_IN); -1005:.\Generated_Source\PSoC5/USBFS_std.c **** } -1006:.\Generated_Source\PSoC5/USBFS_std.c **** else -1007:.\Generated_Source\PSoC5/USBFS_std.c **** { -1008:.\Generated_Source\PSoC5/USBFS_std.c **** /* OUT Endpoint */ -1009:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | - 859 .loc 1 1009 0 - 860 003e 8921 movs r1, #137 - 861 .L80: - 862 0040 D154 strb r1, [r2, r3] -1010:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_MODE_ACK_OUT); -1011:.\Generated_Source\PSoC5/USBFS_std.c **** } -1012:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); -1013:.\Generated_Source\PSoC5/USBFS_std.c **** } -1014:.\Generated_Source\PSoC5/USBFS_std.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 36 - - -1015:.\Generated_Source\PSoC5/USBFS_std.c **** return(requestHandled); -1016:.\Generated_Source\PSoC5/USBFS_std.c **** } - 863 .loc 1 1016 0 -1012:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 864 .loc 1 1012 0 - 865 0042 FFF7FEBF b USBFS_InitNoDataControlTransfer - 866 .LVL69: - 867 .L77: - 868 .loc 1 1016 0 - 869 0046 0020 movs r0, #0 - 870 .LVL70: - 871 0048 7047 bx lr - 872 .L82: - 873 004a 00BF .align 2 - 874 .L81: - 875 004c 04600040 .word 1073766404 - 876 0050 00000000 .word USBFS_EP - 877 0054 0E600040 .word 1073766414 - 878 .cfi_endproc - 879 .LFE8: - 880 .size USBFS_SetEndpointHalt, .-USBFS_SetEndpointHalt - 881 .section .text.USBFS_ClearEndpointHalt,"ax",%progbits - 882 .align 1 - 883 .global USBFS_ClearEndpointHalt - 884 .thumb - 885 .thumb_func - 886 .type USBFS_ClearEndpointHalt, %function - 887 USBFS_ClearEndpointHalt: - 888 .LFB9: -1017:.\Generated_Source\PSoC5/USBFS_std.c **** -1018:.\Generated_Source\PSoC5/USBFS_std.c **** -1019:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* -1020:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_ClearEndpointHalt -1021:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** -1022:.\Generated_Source\PSoC5/USBFS_std.c **** * -1023:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: -1024:.\Generated_Source\PSoC5/USBFS_std.c **** * This routine handles clear endpoint halt. -1025:.\Generated_Source\PSoC5/USBFS_std.c **** * -1026:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: -1027:.\Generated_Source\PSoC5/USBFS_std.c **** * None. -1028:.\Generated_Source\PSoC5/USBFS_std.c **** * -1029:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: -1030:.\Generated_Source\PSoC5/USBFS_std.c **** * requestHandled. -1031:.\Generated_Source\PSoC5/USBFS_std.c **** * -1032:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: -1033:.\Generated_Source\PSoC5/USBFS_std.c **** * No. -1034:.\Generated_Source\PSoC5/USBFS_std.c **** * -1035:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ -1036:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 USBFS_ClearEndpointHalt(void) -1037:.\Generated_Source\PSoC5/USBFS_std.c **** { - 889 .loc 1 1037 0 - 890 .cfi_startproc - 891 @ args = 0, pretend = 0, frame = 0 - 892 @ frame_needed = 0, uses_anonymous_args = 0 - 893 .LVL71: - 894 0000 10B5 push {r4, lr} - 895 .LCFI4: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 37 - - - 896 .cfi_def_cfa_offset 8 - 897 .cfi_offset 4, -8 - 898 .cfi_offset 14, -4 -1038:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ep; -1039:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 ri; -1040:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 requestHandled = USBFS_FALSE; -1041:.\Generated_Source\PSoC5/USBFS_std.c **** -1042:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear endpoint halt */ -1043:.\Generated_Source\PSoC5/USBFS_std.c **** ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - 899 .loc 1 1043 0 - 900 0002 1A4B ldr r3, .L90 - 901 0004 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 902 0006 00F07F03 and r3, r0, #127 - 903 .LVL72: -1044:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 904 .loc 1 1044 0 - 905 000a 5A1E subs r2, r3, #1 - 906 000c D2B2 uxtb r2, r2 - 907 .LVL73: -1045:.\Generated_Source\PSoC5/USBFS_std.c **** -1046:.\Generated_Source\PSoC5/USBFS_std.c **** if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) - 908 .loc 1 1046 0 - 909 000e 072A cmp r2, #7 - 910 0010 2AD8 bhi .L84 -1047:.\Generated_Source\PSoC5/USBFS_std.c **** { -1048:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear the endpoint Halt */ -1049:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT); - 911 .loc 1 1049 0 - 912 0012 1749 ldr r1, .L90+4 - 913 0014 0C20 movs r0, #12 - 914 0016 00FB0313 mla r3, r0, r3, r1 - 915 .LVL74: - 916 001a 9C78 ldrb r4, [r3, #2] @ zero_extendqisi2 -1044:.\Generated_Source\PSoC5/USBFS_std.c **** ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - 917 .loc 1 1044 0 - 918 001c 1201 lsls r2, r2, #4 - 919 .LVL75: - 920 .loc 1 1049 0 - 921 001e 04F0FE01 and r1, r4, #254 - 922 0022 9970 strb r1, [r3, #2] -1050:.\Generated_Source\PSoC5/USBFS_std.c **** -1051:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear the data toggle */ -1052:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epToggle = 0u; - 923 .loc 1 1052 0 - 924 0024 0024 movs r4, #0 -1053:.\Generated_Source\PSoC5/USBFS_std.c **** /* Clear toggle bit for already armed packet */ -1054:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8( - 925 .loc 1 1054 0 - 926 0026 1349 ldr r1, .L90+8 -1052:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].epToggle = 0u; - 927 .loc 1 1052 0 - 928 0028 DC70 strb r4, [r3, #3] - 929 .loc 1 1054 0 - 930 002a D2B2 uxtb r2, r2 - 931 002c 545C ldrb r4, [r2, r1] @ zero_extendqisi2 - 932 002e 04F07F04 and r4, r4, #127 - 933 0032 5454 strb r4, [r2, r1] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 38 - - -1055:.\Generated_Source\PSoC5/USBFS_std.c **** (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE); -1056:.\Generated_Source\PSoC5/USBFS_std.c **** /* Return API State as it was defined before */ -1057:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED; - 934 .loc 1 1057 0 - 935 0034 5978 ldrb r1, [r3, #1] @ zero_extendqisi2 - 936 0036 01F0FD01 and r1, r1, #253 - 937 003a 5970 strb r1, [r3, #1] -1058:.\Generated_Source\PSoC5/USBFS_std.c **** -1059:.\Generated_Source\PSoC5/USBFS_std.c **** if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - 938 .loc 1 1059 0 - 939 003c 1979 ldrb r1, [r3, #4] @ zero_extendqisi2 -1060:.\Generated_Source\PSoC5/USBFS_std.c **** { -1061:.\Generated_Source\PSoC5/USBFS_std.c **** /* IN Endpoint */ -1062:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) - 940 .loc 1 1062 0 - 941 003e 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 -1059:.\Generated_Source\PSoC5/USBFS_std.c **** if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - 942 .loc 1 1059 0 - 943 0040 11F0800F tst r1, #128 - 944 0044 0C49 ldr r1, .L90+12 - 945 0046 05D0 beq .L85 - 946 .loc 1 1062 0 - 947 0048 012B cmp r3, #1 - 948 004a 01D1 bne .L86 -1063:.\Generated_Source\PSoC5/USBFS_std.c **** { /* Wait for next packet from application */ -1064:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); - 949 .loc 1 1064 0 - 950 004c 5054 strb r0, [r2, r1] - 951 004e 07E0 b .L87 - 952 .L86: -1065:.\Generated_Source\PSoC5/USBFS_std.c **** } -1066:.\Generated_Source\PSoC5/USBFS_std.c **** else /* Continue armed transfer */ -1067:.\Generated_Source\PSoC5/USBFS_std.c **** { -1068:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN); - 953 .loc 1 1068 0 - 954 0050 0D20 movs r0, #13 - 955 0052 04E0 b .L89 - 956 .L85: -1069:.\Generated_Source\PSoC5/USBFS_std.c **** } -1070:.\Generated_Source\PSoC5/USBFS_std.c **** } -1071:.\Generated_Source\PSoC5/USBFS_std.c **** else -1072:.\Generated_Source\PSoC5/USBFS_std.c **** { -1073:.\Generated_Source\PSoC5/USBFS_std.c **** /* OUT Endpoint */ -1074:.\Generated_Source\PSoC5/USBFS_std.c **** if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) - 957 .loc 1 1074 0 - 958 0054 012B cmp r3, #1 - 959 0056 01D1 bne .L88 -1075:.\Generated_Source\PSoC5/USBFS_std.c **** { /* Allow application to read full buffer */ -1076:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); - 960 .loc 1 1076 0 - 961 0058 0820 movs r0, #8 - 962 005a 00E0 b .L89 - 963 .L88: -1077:.\Generated_Source\PSoC5/USBFS_std.c **** } -1078:.\Generated_Source\PSoC5/USBFS_std.c **** else /* Mark endpoint as empty, so it will be reloaded */ -1079:.\Generated_Source\PSoC5/USBFS_std.c **** { -1080:.\Generated_Source\PSoC5/USBFS_std.c **** CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 39 - - - 964 .loc 1 1080 0 - 965 005c 0920 movs r0, #9 - 966 .L89: - 967 005e 5054 strb r0, [r2, r1] - 968 .L87: -1081:.\Generated_Source\PSoC5/USBFS_std.c **** } -1082:.\Generated_Source\PSoC5/USBFS_std.c **** } -1083:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); -1084:.\Generated_Source\PSoC5/USBFS_std.c **** } -1085:.\Generated_Source\PSoC5/USBFS_std.c **** -1086:.\Generated_Source\PSoC5/USBFS_std.c **** return(requestHandled); -1087:.\Generated_Source\PSoC5/USBFS_std.c **** } - 969 .loc 1 1087 0 - 970 0060 BDE81040 pop {r4, lr} -1083:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 971 .loc 1 1083 0 - 972 0064 FFF7FEBF b USBFS_InitNoDataControlTransfer - 973 .LVL76: - 974 .L84: - 975 .loc 1 1087 0 - 976 0068 0020 movs r0, #0 - 977 006a 10BD pop {r4, pc} - 978 .L91: - 979 .align 2 - 980 .L90: - 981 006c 04600040 .word 1073766404 - 982 0070 00000000 .word USBFS_EP - 983 0074 0C600040 .word 1073766412 - 984 0078 0E600040 .word 1073766414 - 985 .cfi_endproc - 986 .LFE9: - 987 .size USBFS_ClearEndpointHalt, .-USBFS_ClearEndpointHalt - 988 .section .text.USBFS_ValidateAlternateSetting,"ax",%progbits - 989 .align 1 - 990 .global USBFS_ValidateAlternateSetting - 991 .thumb - 992 .thumb_func - 993 .type USBFS_ValidateAlternateSetting, %function - 994 USBFS_ValidateAlternateSetting: - 995 .LFB10: -1088:.\Generated_Source\PSoC5/USBFS_std.c **** -1089:.\Generated_Source\PSoC5/USBFS_std.c **** -1090:.\Generated_Source\PSoC5/USBFS_std.c **** /******************************************************************************* -1091:.\Generated_Source\PSoC5/USBFS_std.c **** * Function Name: USBFS_ValidateAlternateSetting -1092:.\Generated_Source\PSoC5/USBFS_std.c **** ******************************************************************************** -1093:.\Generated_Source\PSoC5/USBFS_std.c **** * -1094:.\Generated_Source\PSoC5/USBFS_std.c **** * Summary: -1095:.\Generated_Source\PSoC5/USBFS_std.c **** * Validates (and records) a SET INTERFACE request. -1096:.\Generated_Source\PSoC5/USBFS_std.c **** * -1097:.\Generated_Source\PSoC5/USBFS_std.c **** * Parameters: -1098:.\Generated_Source\PSoC5/USBFS_std.c **** * None. -1099:.\Generated_Source\PSoC5/USBFS_std.c **** * -1100:.\Generated_Source\PSoC5/USBFS_std.c **** * Return: -1101:.\Generated_Source\PSoC5/USBFS_std.c **** * requestHandled. -1102:.\Generated_Source\PSoC5/USBFS_std.c **** * -1103:.\Generated_Source\PSoC5/USBFS_std.c **** * Reentrant: -1104:.\Generated_Source\PSoC5/USBFS_std.c **** * No. - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 40 - - -1105:.\Generated_Source\PSoC5/USBFS_std.c **** * -1106:.\Generated_Source\PSoC5/USBFS_std.c **** *******************************************************************************/ -1107:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 USBFS_ValidateAlternateSetting(void) -1108:.\Generated_Source\PSoC5/USBFS_std.c **** { - 996 .loc 1 1108 0 - 997 .cfi_startproc - 998 @ args = 0, pretend = 0, frame = 0 - 999 @ frame_needed = 0, uses_anonymous_args = 0 - 1000 .LVL77: - 1001 0000 10B5 push {r4, lr} - 1002 .LCFI5: - 1003 .cfi_def_cfa_offset 8 - 1004 .cfi_offset 4, -8 - 1005 .cfi_offset 14, -4 -1109:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 requestHandled = USBFS_TRUE; -1110:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 interfaceNum; -1111:.\Generated_Source\PSoC5/USBFS_std.c **** const T_USBFS_LUT CYCODE *pTmp; -1112:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 currentInterfacesNum; -1113:.\Generated_Source\PSoC5/USBFS_std.c **** -1114:.\Generated_Source\PSoC5/USBFS_std.c **** interfaceNum = CY_GET_REG8(USBFS_wIndexLo); - 1006 .loc 1 1114 0 - 1007 0002 0C4B ldr r3, .L96 -1115:.\Generated_Source\PSoC5/USBFS_std.c **** /* Validate interface setting, stall if invalid. */ -1116:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - 1008 .loc 1 1116 0 - 1009 0004 0C48 ldr r0, .L96+4 -1114:.\Generated_Source\PSoC5/USBFS_std.c **** interfaceNum = CY_GET_REG8(USBFS_wIndexLo); - 1010 .loc 1 1114 0 - 1011 0006 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 1012 .LVL78: - 1013 .loc 1 1116 0 - 1014 0008 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 1015 000a 4A1E subs r2, r1, #1 - 1016 000c D0B2 uxtb r0, r2 - 1017 000e FFF7FEFF bl USBFS_GetConfigTablePtr - 1018 .LVL79: -1117:.\Generated_Source\PSoC5/USBFS_std.c **** currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; - 1019 .loc 1 1117 0 - 1020 0012 4368 ldr r3, [r0, #4] -1118:.\Generated_Source\PSoC5/USBFS_std.c **** -1119:.\Generated_Source\PSoC5/USBFS_std.c **** if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER)) - 1021 .loc 1 1119 0 - 1022 0014 1879 ldrb r0, [r3, #4] @ zero_extendqisi2 - 1023 .LVL80: - 1024 0016 A042 cmp r0, r4 - 1025 0018 09D9 bls .L95 - 1026 .loc 1 1119 0 is_stmt 0 discriminator 1 - 1027 001a 44B9 cbnz r4, .L95 -1120:.\Generated_Source\PSoC5/USBFS_std.c **** { /* Wrong interface number */ -1121:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_FALSE; -1122:.\Generated_Source\PSoC5/USBFS_std.c **** } -1123:.\Generated_Source\PSoC5/USBFS_std.c **** else -1124:.\Generated_Source\PSoC5/USBFS_std.c **** { -1125:.\Generated_Source\PSoC5/USBFS_std.c **** /* Save current Alt setting to find out the difference in Config() function */ -1126:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; - 1028 .loc 1 1126 0 is_stmt 1 - 1029 001c 074B ldr r3, .L96+8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 41 - - - 1030 .LVL81: - 1031 001e 084A ldr r2, .L96+12 - 1032 0020 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 -1127:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo); - 1033 .loc 1 1127 0 - 1034 0022 0848 ldr r0, .L96+16 - 1035 .LVL82: -1126:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; - 1036 .loc 1 1126 0 - 1037 0024 1170 strb r1, [r2, #0] - 1038 .loc 1 1127 0 - 1039 0026 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 -1109:.\Generated_Source\PSoC5/USBFS_std.c **** uint8 requestHandled = USBFS_TRUE; - 1040 .loc 1 1109 0 - 1041 0028 0120 movs r0, #1 - 1042 .loc 1 1127 0 - 1043 002a 1970 strb r1, [r3, #0] - 1044 002c 10BD pop {r4, pc} - 1045 .LVL83: - 1046 .L95: -1121:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_FALSE; - 1047 .loc 1 1121 0 - 1048 002e 0020 movs r0, #0 - 1049 .LVL84: -1128:.\Generated_Source\PSoC5/USBFS_std.c **** } -1129:.\Generated_Source\PSoC5/USBFS_std.c **** -1130:.\Generated_Source\PSoC5/USBFS_std.c **** return (requestHandled); -1131:.\Generated_Source\PSoC5/USBFS_std.c **** } - 1050 .loc 1 1131 0 - 1051 0030 10BD pop {r4, pc} - 1052 .L97: - 1053 0032 00BF .align 2 - 1054 .L96: - 1055 0034 04600040 .word 1073766404 - 1056 0038 00000000 .word USBFS_configuration - 1057 003c 00000000 .word USBFS_interfaceSetting - 1058 0040 00000000 .word USBFS_interfaceSetting_last - 1059 0044 02600040 .word 1073766402 - 1060 .cfi_endproc - 1061 .LFE10: - 1062 .size USBFS_ValidateAlternateSetting, .-USBFS_ValidateAlternateSetting - 1063 .section .text.USBFS_HandleStandardRqst,"ax",%progbits - 1064 .align 1 - 1065 .global USBFS_HandleStandardRqst - 1066 .thumb - 1067 .thumb_func - 1068 .type USBFS_HandleStandardRqst, %function - 1069 USBFS_HandleStandardRqst: - 1070 .LFB0: - 90:.\Generated_Source\PSoC5/USBFS_std.c **** { - 1071 .loc 1 90 0 - 1072 .cfi_startproc - 1073 @ args = 0, pretend = 0, frame = 0 - 1074 @ frame_needed = 0, uses_anonymous_args = 0 - 1075 .LVL85: - 1076 0000 10B5 push {r4, lr} - 1077 .LCFI6: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 42 - - - 1078 .cfi_def_cfa_offset 8 - 1079 .cfi_offset 4, -8 - 1080 .cfi_offset 14, -4 - 102:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = 0u; - 1081 .loc 1 102 0 - 1082 0002 7C4B ldr r3, .L151 - 1083 0004 0022 movs r2, #0 - 1084 0006 1A80 strh r2, [r3, #0] @ movhi - 104:.\Generated_Source\PSoC5/USBFS_std.c **** if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - 1085 .loc 1 104 0 - 1086 0008 7B4A ldr r2, .L151+4 - 1087 000a 7C48 ldr r0, .L151+8 - 1088 000c 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 1089 000e 11F0800F tst r1, #128 - 1090 0012 00F08A80 beq .L99 - 107:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 1091 .loc 1 107 0 - 1092 0016 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 1093 0018 0A29 cmp r1, #10 - 1094 001a 00F22281 bhi .L100 - 1095 001e DFE811F0 tbh [pc, r1, lsl #1] - 1096 .L105: - 1097 0022 5800 .2byte (.L101-.L105)/2 - 1098 0024 2001 .2byte (.L100-.L105)/2 - 1099 0026 2001 .2byte (.L100-.L105)/2 - 1100 0028 2001 .2byte (.L100-.L105)/2 - 1101 002a 2001 .2byte (.L100-.L105)/2 - 1102 002c 2001 .2byte (.L100-.L105)/2 - 1103 002e 0B00 .2byte (.L102-.L105)/2 - 1104 0030 2001 .2byte (.L100-.L105)/2 - 1105 0032 7800 .2byte (.L103-.L105)/2 - 1106 0034 2001 .2byte (.L100-.L105)/2 - 1107 0036 7C00 .2byte (.L104-.L105)/2 - 1108 .L102: - 110:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE) - 1109 .loc 1 110 0 - 1110 0038 714B ldr r3, .L151+12 - 1111 003a 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 1112 003c 0129 cmp r1, #1 - 1113 003e 0AD1 bne .L106 - 1114 .LBB4: - 1115 .LBB5: - 882:.\Generated_Source\PSoC5/USBFS_std.c **** return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); - 1116 .loc 1 882 0 - 1117 0040 7048 ldr r0, .L151+16 - 1118 0042 7149 ldr r1, .L151+20 - 1119 0044 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 1120 0046 01EBC203 add r3, r1, r2, lsl #3 - 1121 .LBE5: - 1122 .LBE4: - 113:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - 1123 .loc 1 113 0 - 1124 004a 5868 ldr r0, [r3, #4] - 114:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; - 1125 .loc 1 114 0 - 1126 004c 1223 movs r3, #18 - 113:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 43 - - - 1127 .loc 1 113 0 - 1128 004e 4268 ldr r2, [r0, #4] - 1129 0050 6848 ldr r0, .L151 - 1130 0052 4260 str r2, [r0, #4] - 1131 0054 0FE0 b .L142 - 1132 .L106: - 117:.\Generated_Source\PSoC5/USBFS_std.c **** else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG) - 1133 .loc 1 117 0 - 1134 0056 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1135 0058 0228 cmp r0, #2 - 1136 005a 11D1 bne .L107 - 119:.\Generated_Source\PSoC5/USBFS_std.c **** pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo)); - 1137 .loc 1 119 0 - 1138 005c 6B4B ldr r3, .L151+24 - 1139 005e 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1140 0060 FFF7FEFF bl USBFS_GetConfigTablePtr - 1141 .LVL86: - 120:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - 1142 .loc 1 120 0 - 1143 0064 4268 ldr r2, [r0, #4] - 1144 0066 6348 ldr r0, .L151 - 1145 .LVL87: - 1146 0068 4260 str r2, [r0, #4] - 121:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ - 1147 .loc 1 121 0 - 1148 006a 4168 ldr r1, [r0, #4] - 1149 006c CB78 ldrb r3, [r1, #3] @ zero_extendqisi2 - 123:.\Generated_Source\PSoC5/USBFS_std.c **** (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; - 1150 .loc 1 123 0 - 1151 006e 4268 ldr r2, [r0, #4] - 1152 0070 9178 ldrb r1, [r2, #2] @ zero_extendqisi2 - 121:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ - 1153 .loc 1 121 0 - 1154 0072 41EA0323 orr r3, r1, r3, lsl #8 - 1155 .L142: - 1156 0076 0380 strh r3, [r0, #0] @ movhi - 1157 .LVL88: - 1158 .L143: - 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - 1159 .loc 1 316 0 - 1160 0078 BDE81040 pop {r4, lr} - 124:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitControlRead(); - 1161 .loc 1 124 0 - 1162 007c FFF7FEBF b USBFS_InitControlRead - 1163 .LVL89: - 1164 .L107: - 127:.\Generated_Source\PSoC5/USBFS_std.c **** else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING) - 1165 .loc 1 127 0 - 1166 0080 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1167 0082 032A cmp r2, #3 - 1168 0084 21D1 bne .L150 - 1169 .L132: - 1170 0086 624B ldr r3, .L151+28 - 1171 0088 0022 movs r2, #0 - 1172 .LVL90: - 1173 .L108: - 133:.\Generated_Source\PSoC5/USBFS_std.c **** while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 44 - - - 1174 .loc 1 133 0 discriminator 1 - 1175 008a 6049 ldr r1, .L151+24 - 1176 008c 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 1177 008e 9042 cmp r0, r2 - 1178 0090 0AD8 bhi .L110 - 1179 .L114: - 151:.\Generated_Source\PSoC5/USBFS_std.c **** if( (CY_GET_REG8(USBFS_wValueLo) != 0u) && - 1180 .loc 1 151 0 - 1181 0092 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 1182 .LVL91: - 1183 0094 82B1 cbz r2, .L112 - 1184 .L111: - 152:.\Generated_Source\PSoC5/USBFS_std.c **** (CY_GET_REG8(USBFS_wValueLo) == - 1185 .loc 1 152 0 discriminator 1 - 1186 0096 5D49 ldr r1, .L151+24 - 155:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; - 1187 .loc 1 155 0 discriminator 1 - 1188 0098 5E48 ldr r0, .L151+32 - 152:.\Generated_Source\PSoC5/USBFS_std.c **** (CY_GET_REG8(USBFS_wValueLo) == - 1189 .loc 1 152 0 discriminator 1 - 1190 009a 0978 ldrb r1, [r1, #0] @ zero_extendqisi2 - 155:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; - 1191 .loc 1 155 0 discriminator 1 - 1192 009c 5E4A ldr r2, .L151+36 - 1193 009e 007C ldrb r0, [r0, #16] @ zero_extendqisi2 - 1194 00a0 8842 cmp r0, r1 - 1195 00a2 08BF it eq - 1196 00a4 1346 moveq r3, r2 - 1197 .LVL92: - 1198 00a6 07E0 b .L112 - 1199 .LVL93: - 1200 .L110: - 133:.\Generated_Source\PSoC5/USBFS_std.c **** while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) - 1201 .loc 1 133 0 discriminator 2 - 1202 00a8 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1203 00aa 0028 cmp r0, #0 - 1204 00ac F1D0 beq .L114 - 1205 .L113: - 136:.\Generated_Source\PSoC5/USBFS_std.c **** descrLength = *pStr; - 1206 .loc 1 136 0 - 1207 00ae 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 1208 .LVL94: - 139:.\Generated_Source\PSoC5/USBFS_std.c **** nStr++; - 1209 .loc 1 139 0 - 1210 00b0 501C adds r0, r2, #1 - 138:.\Generated_Source\PSoC5/USBFS_std.c **** pStr = &pStr[descrLength]; - 1211 .loc 1 138 0 - 1212 00b2 5B18 adds r3, r3, r1 - 1213 .LVL95: - 139:.\Generated_Source\PSoC5/USBFS_std.c **** nStr++; - 1214 .loc 1 139 0 - 1215 00b4 C2B2 uxtb r2, r0 - 1216 .LVL96: - 1217 00b6 E8E7 b .L108 - 1218 .LVL97: - 1219 .L112: - 169:.\Generated_Source\PSoC5/USBFS_std.c **** if (*pStr != 0u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 45 - - - 1220 .loc 1 169 0 - 1221 00b8 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 1222 00ba 0029 cmp r1, #0 - 1223 00bc 00F0D180 beq .L100 - 171:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = *pStr; - 1224 .loc 1 171 0 - 1225 00c0 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1226 00c2 4C4A ldr r2, .L151 - 1227 00c4 1080 strh r0, [r2, #0] @ movhi - 172:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = pStr; - 1228 .loc 1 172 0 - 1229 00c6 5360 str r3, [r2, #4] - 1230 00c8 D6E7 b .L143 - 1231 .LVL98: - 1232 .L150: - 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - 1233 .loc 1 316 0 - 1234 00ca BDE81040 pop {r4, lr} - 179:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_DispatchClassRqst(); - 1235 .loc 1 179 0 - 1236 00ce FFF7FEBF b USBFS_DispatchClassRqst - 1237 .LVL99: - 1238 .L101: - 183:.\Generated_Source\PSoC5/USBFS_std.c **** switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)) - 1239 .loc 1 183 0 - 1240 00d2 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 1241 00d4 11F00302 ands r2, r1, #3 - 1242 00d8 11D0 beq .L116 - 1243 00da 022A cmp r2, #2 - 1244 00dc 40F0C180 bne .L100 - 186:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; - 1245 .loc 1 186 0 - 1246 00e0 4449 ldr r1, .L151 - 188:.\Generated_Source\PSoC5/USBFS_std.c **** CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; - 1247 .loc 1 188 0 - 1248 00e2 4E4B ldr r3, .L151+40 - 186:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; - 1249 .loc 1 186 0 - 1250 00e4 0A80 strh r2, [r1, #0] @ movhi - 188:.\Generated_Source\PSoC5/USBFS_std.c **** CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; - 1251 .loc 1 188 0 - 1252 00e6 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1253 00e8 4D4A ldr r2, .L151+44 - 1254 00ea 00F07F03 and r3, r0, #127 - 1255 00ee 0C20 movs r0, #12 - 1256 00f0 00FB0323 mla r3, r0, r3, r2 - 1257 00f4 9878 ldrb r0, [r3, #2] @ zero_extendqisi2 - 187:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[0u] = USBFS_EP[ \ - 1258 .loc 1 187 0 - 1259 00f6 4B4B ldr r3, .L151+48 - 189:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[1u] = 0u; - 1260 .loc 1 189 0 - 1261 00f8 0022 movs r2, #0 - 187:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[0u] = USBFS_EP[ \ - 1262 .loc 1 187 0 - 1263 00fa 1870 strb r0, [r3, #0] - 1264 00fc 06E0 b .L146 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 46 - - - 1265 .L116: - 194:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; - 1266 .loc 1 194 0 - 1267 00fe 3D49 ldr r1, .L151 - 1268 0100 0223 movs r3, #2 - 195:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[0u] = USBFS_deviceStatus; - 1269 .loc 1 195 0 - 1270 0102 4948 ldr r0, .L151+52 - 194:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; - 1271 .loc 1 194 0 - 1272 0104 0B80 strh r3, [r1, #0] @ movhi - 195:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[0u] = USBFS_deviceStatus; - 1273 .loc 1 195 0 - 1274 0106 0078 ldrb r0, [r0, #0] @ zero_extendqisi2 - 1275 0108 464B ldr r3, .L151+48 - 1276 010a 1870 strb r0, [r3, #0] - 1277 .L146: - 196:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_tBuffer[1u] = 0u; - 1278 .loc 1 196 0 - 1279 010c 5A70 strb r2, [r3, #1] - 197:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = &USBFS_tBuffer[0u]; - 1280 .loc 1 197 0 - 1281 010e 4B60 str r3, [r1, #4] - 1282 0110 B2E7 b .L143 - 1283 .L103: - 205:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = 1u; - 1284 .loc 1 205 0 - 1285 0112 0122 movs r2, #1 - 1286 0114 1A80 strh r2, [r3, #0] @ movhi - 206:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration; - 1287 .loc 1 206 0 - 1288 0116 4548 ldr r0, .L151+56 - 1289 0118 05E0 b .L147 - 1290 .L104: - 210:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = 1u; - 1291 .loc 1 210 0 - 1292 011a 0122 movs r2, #1 - 212:.\Generated_Source\PSoC5/USBFS_std.c **** CY_GET_REG8(USBFS_wInde - 1293 .loc 1 212 0 - 1294 011c 3F48 ldr r0, .L151+40 - 210:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.count = 1u; - 1295 .loc 1 210 0 - 1296 011e 1A80 strh r2, [r3, #0] @ movhi - 212:.\Generated_Source\PSoC5/USBFS_std.c **** CY_GET_REG8(USBFS_wInde - 1297 .loc 1 212 0 - 1298 0120 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 211:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \ - 1299 .loc 1 211 0 - 1300 0122 4349 ldr r1, .L151+60 - 1301 0124 8818 adds r0, r1, r2 - 1302 .L147: - 1303 0126 5860 str r0, [r3, #4] - 1304 0128 A6E7 b .L143 - 1305 .L99: - 221:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 1306 .loc 1 221 0 - 1307 012a 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 47 - - - 1308 012c 581E subs r0, r3, #1 - 1309 012e 0A28 cmp r0, #10 - 1310 0130 00F29780 bhi .L100 - 1311 0134 DFE810F0 tbh [pc, r0, lsl #1] - 1312 .L123: - 1313 0138 2B00 .2byte (.L118-.L123)/2 - 1314 013a 9500 .2byte (.L100-.L123)/2 - 1315 013c 4400 .2byte (.L119-.L123)/2 - 1316 013e 9500 .2byte (.L100-.L123)/2 - 1317 0140 0B00 .2byte (.L120-.L123)/2 - 1318 0142 9500 .2byte (.L100-.L123)/2 - 1319 0144 9500 .2byte (.L100-.L123)/2 - 1320 0146 9500 .2byte (.L100-.L123)/2 - 1321 0148 0F00 .2byte (.L121-.L123)/2 - 1322 014a 9500 .2byte (.L100-.L123)/2 - 1323 014c 1900 .2byte (.L122-.L123)/2 - 1324 .L120: - 224:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo); - 1325 .loc 1 224 0 - 1326 014e 2F4B ldr r3, .L151+24 - 1327 0150 3849 ldr r1, .L151+64 - 1328 0152 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1329 0154 4CE0 b .L149 - 1330 .L121: - 228:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configuration = CY_GET_REG8(USBFS_wValueLo); - 1331 .loc 1 228 0 - 1332 0156 2D4B ldr r3, .L151+24 - 1333 0158 344A ldr r2, .L151+56 - 1334 015a 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 229:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configurationChanged = USBFS_TRUE; - 1335 .loc 1 229 0 - 1336 015c 3649 ldr r1, .L151+68 - 228:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configuration = CY_GET_REG8(USBFS_wValueLo); - 1337 .loc 1 228 0 - 1338 015e 1070 strb r0, [r2, #0] - 229:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configurationChanged = USBFS_TRUE; - 1339 .loc 1 229 0 - 1340 0160 0120 movs r0, #1 - 1341 0162 0870 strb r0, [r1, #0] - 230:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_Config(USBFS_TRUE); - 1342 .loc 1 230 0 - 1343 0164 FFF7FEFF bl USBFS_Config - 1344 .LVL100: - 1345 0168 77E0 b .L144 - 1346 .L122: - 234:.\Generated_Source\PSoC5/USBFS_std.c **** if (USBFS_ValidateAlternateSetting() != 0u) - 1347 .loc 1 234 0 - 1348 016a FFF7FEFF bl USBFS_ValidateAlternateSetting - 1349 .LVL101: - 1350 016e 0028 cmp r0, #0 - 1351 0170 77D0 beq .L100 - 236:.\Generated_Source\PSoC5/USBFS_std.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - 1352 .loc 1 236 0 - 1353 0172 2A4C ldr r4, .L151+40 - 237:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceNumber = interfaceNumber; - 1354 .loc 1 237 0 - 1355 0174 314A ldr r2, .L151+72 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 48 - - - 236:.\Generated_Source\PSoC5/USBFS_std.c **** interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - 1356 .loc 1 236 0 - 1357 0176 2478 ldrb r4, [r4, #0] @ zero_extendqisi2 - 1358 .LVL102: - 238:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configurationChanged = USBFS_TRUE; - 1359 .loc 1 238 0 - 1360 0178 2F4B ldr r3, .L151+68 - 1361 017a 0121 movs r1, #1 - 237:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceNumber = interfaceNumber; - 1362 .loc 1 237 0 - 1363 017c 1470 strb r4, [r2, #0] - 238:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_configurationChanged = USBFS_TRUE; - 1364 .loc 1 238 0 - 1365 017e 1970 strb r1, [r3, #0] - 243:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_ConfigAltChanged(); - 1366 .loc 1 243 0 - 1367 0180 FFF7FEFF bl USBFS_ConfigAltChanged - 1368 .LVL103: - 247:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting[interfaceNumber]; - 1369 .loc 1 247 0 - 1370 0184 2A48 ldr r0, .L151+60 - 246:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[interfaceNumber] = - 1371 .loc 1 246 0 - 1372 0186 2E49 ldr r1, .L151+76 - 247:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting[interfaceNumber]; - 1373 .loc 1 247 0 - 1374 0188 025D ldrb r2, [r0, r4] @ zero_extendqisi2 - 246:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceSetting_last[interfaceNumber] = - 1375 .loc 1 246 0 - 1376 018a 0A55 strb r2, [r1, r4] - 1377 018c 65E0 b .L144 - 1378 .LVL104: - 1379 .L118: - 252:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - 1380 .loc 1 252 0 - 1381 018e 1278 ldrb r2, [r2, #0] @ zero_extendqisi2 - 1382 0190 02F00301 and r1, r2, #3 - 1383 0194 0129 cmp r1, #1 - 1384 0196 55D0 beq .L129 - 1385 0198 09D3 bcc .L125 - 1386 019a 0229 cmp r1, #2 - 1387 019c 61D1 bne .L100 - 255:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) - 1388 .loc 1 255 0 - 1389 019e 1B4B ldr r3, .L151+24 - 1390 01a0 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1391 01a2 0028 cmp r0, #0 - 1392 01a4 5DD1 bne .L100 - 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - 1393 .loc 1 316 0 - 1394 01a6 BDE81040 pop {r4, lr} - 257:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_ClearEndpointHalt(); - 1395 .loc 1 257 0 - 1396 01aa FFF7FEBF b USBFS_ClearEndpointHalt - 1397 .LVL105: - 1398 .L125: - 262:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 49 - - - 1399 .loc 1 262 0 - 1400 01ae 174A ldr r2, .L151+24 - 1401 01b0 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 1402 01b2 0129 cmp r1, #1 - 1403 01b4 55D1 bne .L100 - 264:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; - 1404 .loc 1 264 0 - 1405 01b6 1C49 ldr r1, .L151+52 - 1406 01b8 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 1407 01ba 03F0FD00 and r0, r3, #253 - 1408 .LVL106: - 1409 01be 17E0 b .L149 - 1410 .L119: - 282:.\Generated_Source\PSoC5/USBFS_std.c **** switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - 1411 .loc 1 282 0 - 1412 01c0 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 1413 01c2 00F00302 and r2, r0, #3 - 1414 01c6 012A cmp r2, #1 - 1415 01c8 3CD0 beq .L129 - 1416 01ca 09D3 bcc .L128 - 1417 01cc 022A cmp r2, #2 - 1418 01ce 48D1 bne .L100 - 285:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) - 1419 .loc 1 285 0 - 1420 01d0 0E49 ldr r1, .L151+24 - 1421 01d2 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 1422 01d4 002B cmp r3, #0 - 1423 01d6 44D1 bne .L100 - 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - 1424 .loc 1 316 0 - 1425 01d8 BDE81040 pop {r4, lr} - 287:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_SetEndpointHalt(); - 1426 .loc 1 287 0 - 1427 01dc FFF7FEBF b USBFS_SetEndpointHalt - 1428 .LVL107: - 1429 .L128: - 292:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) - 1430 .loc 1 292 0 - 1431 01e0 0A48 ldr r0, .L151+24 - 1432 01e2 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 1433 01e4 012A cmp r2, #1 - 1434 01e6 3CD1 bne .L100 - 294:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; - 1435 .loc 1 294 0 - 1436 01e8 0F49 ldr r1, .L151+52 - 1437 01ea 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 1438 01ec 43F00200 orr r0, r3, #2 - 1439 .L149: - 1440 .LVL108: - 1441 01f0 0870 strb r0, [r1, #0] - 1442 01f2 32E0 b .L144 - 1443 .L152: - 1444 .align 2 - 1445 .L151: - 1446 01f4 00000000 .word USBFS_currentTD - 1447 01f8 00600040 .word 1073766400 - 1448 01fc 01600040 .word 1073766401 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 50 - - - 1449 0200 03600040 .word 1073766403 - 1450 0204 00000000 .word USBFS_device - 1451 0208 00000000 .word USBFS_TABLE - 1452 020c 02600040 .word 1073766402 - 1453 0210 00000000 .word USBFS_STRING_DESCRIPTORS - 1454 0214 00000000 .word USBFS_DEVICE0_DESCR - 1455 0218 00000000 .word USBFS_SN_STRING_DESCRIPTOR - 1456 021c 04600040 .word 1073766404 - 1457 0220 00000000 .word USBFS_EP - 1458 0224 00000000 .word .LANCHOR0 - 1459 0228 00000000 .word USBFS_deviceStatus - 1460 022c 00000000 .word USBFS_configuration - 1461 0230 00000000 .word USBFS_interfaceSetting - 1462 0234 00000000 .word USBFS_deviceAddress - 1463 0238 00000000 .word USBFS_configurationChanged - 1464 023c 00000000 .word USBFS_interfaceNumber - 1465 0240 00000000 .word USBFS_interfaceSetting_last - 1466 .LVL109: - 1467 .L129: - 300:.\Generated_Source\PSoC5/USBFS_std.c **** if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) - 1468 .loc 1 300 0 - 1469 0244 0848 ldr r0, .L153 - 1470 0246 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 1471 0248 5AB9 cbnz r2, .L100 - 302:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - 1472 .loc 1 302 0 - 1473 024a 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 1474 024c 074A ldr r2, .L153+4 - 303:.\Generated_Source\PSoC5/USBFS_std.c **** (uint8)~(CY_GET_REG8(USBFS_wValueLo - 1475 .loc 1 303 0 - 1476 024e 0848 ldr r0, .L153+8 - 302:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - 1477 .loc 1 302 0 - 1478 0250 D15C ldrb r1, [r2, r3] @ zero_extendqisi2 - 303:.\Generated_Source\PSoC5/USBFS_std.c **** (uint8)~(CY_GET_REG8(USBFS_wValueLo - 1479 .loc 1 303 0 - 1480 0252 0078 ldrb r0, [r0, #0] @ zero_extendqisi2 - 302:.\Generated_Source\PSoC5/USBFS_std.c **** USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - 1481 .loc 1 302 0 - 1482 0254 21EA0001 bic r1, r1, r0 - 1483 0258 D154 strb r1, [r2, r3] - 1484 .LVL110: - 1485 .L144: - 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - 1486 .loc 1 316 0 - 1487 025a BDE81040 pop {r4, lr} - 304:.\Generated_Source\PSoC5/USBFS_std.c **** requestHandled = USBFS_InitNoDataControlTransfer(); - 1488 .loc 1 304 0 - 1489 025e FFF7FEBF b USBFS_InitNoDataControlTransfer - 1490 .LVL111: - 1491 .L100: - 316:.\Generated_Source\PSoC5/USBFS_std.c **** } - 1492 .loc 1 316 0 - 1493 0262 0020 movs r0, #0 - 1494 0264 10BD pop {r4, pc} - 1495 .L154: - 1496 0266 00BF .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 51 - - - 1497 .L153: - 1498 0268 04600040 .word 1073766404 - 1499 026c 00000000 .word USBFS_interfaceStatus - 1500 0270 02600040 .word 1073766402 - 1501 .cfi_endproc - 1502 .LFE0: - 1503 .size USBFS_HandleStandardRqst, .-USBFS_HandleStandardRqst - 1504 .bss - 1505 .set .LANCHOR0,. + 0 - 1506 .type USBFS_tBuffer.5008, %object - 1507 .size USBFS_tBuffer.5008, 2 - 1508 USBFS_tBuffer.5008: - 1509 0000 0000 .space 2 - 1510 .text - 1511 .Letext0: - 1512 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 1513 .file 3 ".\\Generated_Source\\PSoC5\\USBFS.h" - 1514 .file 4 ".\\Generated_Source\\PSoC5\\USBFS_pvt.h" - 1515 .section .debug_info,"",%progbits - 1516 .Ldebug_info0: - 1517 0000 9A080000 .4byte 0x89a - 1518 0004 0200 .2byte 0x2 - 1519 0006 00000000 .4byte .Ldebug_abbrev0 - 1520 000a 04 .byte 0x4 - 1521 000b 01 .uleb128 0x1 - 1522 000c 6A030000 .4byte .LASF83 - 1523 0010 01 .byte 0x1 - 1524 0011 F3030000 .4byte .LASF84 - 1525 0015 22020000 .4byte .LASF85 - 1526 0019 00000000 .4byte .Ldebug_ranges0+0 - 1527 001d 00000000 .4byte 0 - 1528 0021 00000000 .4byte 0 - 1529 0025 00000000 .4byte .Ldebug_line0 - 1530 0029 02 .uleb128 0x2 - 1531 002a 01 .byte 0x1 - 1532 002b 06 .byte 0x6 - 1533 002c 9A000000 .4byte .LASF0 - 1534 0030 02 .uleb128 0x2 - 1535 0031 01 .byte 0x1 - 1536 0032 08 .byte 0x8 - 1537 0033 B8030000 .4byte .LASF1 - 1538 0037 02 .uleb128 0x2 - 1539 0038 02 .byte 0x2 - 1540 0039 05 .byte 0x5 - 1541 003a C6030000 .4byte .LASF2 - 1542 003e 02 .uleb128 0x2 - 1543 003f 02 .byte 0x2 - 1544 0040 07 .byte 0x7 - 1545 0041 C4010000 .4byte .LASF3 - 1546 0045 02 .uleb128 0x2 - 1547 0046 04 .byte 0x4 - 1548 0047 05 .byte 0x5 - 1549 0048 15010000 .4byte .LASF4 - 1550 004c 02 .uleb128 0x2 - 1551 004d 04 .byte 0x4 - 1552 004e 07 .byte 0x7 - 1553 004f 92010000 .4byte .LASF5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 52 - - - 1554 0053 02 .uleb128 0x2 - 1555 0054 08 .byte 0x8 - 1556 0055 05 .byte 0x5 - 1557 0056 8C000000 .4byte .LASF6 - 1558 005a 02 .uleb128 0x2 - 1559 005b 08 .byte 0x8 - 1560 005c 07 .byte 0x7 - 1561 005d 52000000 .4byte .LASF7 - 1562 0061 03 .uleb128 0x3 - 1563 0062 04 .byte 0x4 - 1564 0063 05 .byte 0x5 - 1565 0064 696E7400 .ascii "int\000" - 1566 0068 02 .uleb128 0x2 - 1567 0069 04 .byte 0x4 - 1568 006a 07 .byte 0x7 - 1569 006b 85010000 .4byte .LASF8 - 1570 006f 04 .uleb128 0x4 - 1571 0070 1E010000 .4byte .LASF9 - 1572 0074 02 .byte 0x2 - 1573 0075 5B .byte 0x5b - 1574 0076 30000000 .4byte 0x30 - 1575 007a 04 .uleb128 0x4 - 1576 007b 13000000 .4byte .LASF10 - 1577 007f 02 .byte 0x2 - 1578 0080 5C .byte 0x5c - 1579 0081 3E000000 .4byte 0x3e - 1580 0085 02 .uleb128 0x2 - 1581 0086 04 .byte 0x4 - 1582 0087 04 .byte 0x4 - 1583 0088 4B030000 .4byte .LASF11 - 1584 008c 02 .uleb128 0x2 - 1585 008d 08 .byte 0x8 - 1586 008e 04 .byte 0x4 - 1587 008f 2D010000 .4byte .LASF12 - 1588 0093 02 .uleb128 0x2 - 1589 0094 01 .byte 0x1 - 1590 0095 08 .byte 0x8 - 1591 0096 87040000 .4byte .LASF13 - 1592 009a 04 .uleb128 0x4 - 1593 009b B3030000 .4byte .LASF14 - 1594 009f 02 .byte 0x2 - 1595 00a0 F0 .byte 0xf0 - 1596 00a1 A5000000 .4byte 0xa5 - 1597 00a5 05 .uleb128 0x5 - 1598 00a6 6F000000 .4byte 0x6f - 1599 00aa 02 .uleb128 0x2 - 1600 00ab 04 .byte 0x4 - 1601 00ac 07 .byte 0x7 - 1602 00ad 97020000 .4byte .LASF15 - 1603 00b1 06 .uleb128 0x6 - 1604 00b2 0C .byte 0xc - 1605 00b3 03 .byte 0x3 - 1606 00b4 79 .byte 0x79 - 1607 00b5 38010000 .4byte 0x138 - 1608 00b9 07 .uleb128 0x7 - 1609 00ba B6020000 .4byte .LASF16 - 1610 00be 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 53 - - - 1611 00bf 7B .byte 0x7b - 1612 00c0 6F000000 .4byte 0x6f - 1613 00c4 02 .byte 0x2 - 1614 00c5 23 .byte 0x23 - 1615 00c6 00 .uleb128 0 - 1616 00c7 07 .uleb128 0x7 - 1617 00c8 51030000 .4byte .LASF17 - 1618 00cc 03 .byte 0x3 - 1619 00cd 7C .byte 0x7c - 1620 00ce 6F000000 .4byte 0x6f - 1621 00d2 02 .byte 0x2 - 1622 00d3 23 .byte 0x23 - 1623 00d4 01 .uleb128 0x1 - 1624 00d5 07 .uleb128 0x7 - 1625 00d6 81020000 .4byte .LASF18 - 1626 00da 03 .byte 0x3 - 1627 00db 7D .byte 0x7d - 1628 00dc 6F000000 .4byte 0x6f - 1629 00e0 02 .byte 0x2 - 1630 00e1 23 .byte 0x23 - 1631 00e2 02 .uleb128 0x2 - 1632 00e3 07 .uleb128 0x7 - 1633 00e4 24010000 .4byte .LASF19 - 1634 00e8 03 .byte 0x3 - 1635 00e9 7E .byte 0x7e - 1636 00ea 6F000000 .4byte 0x6f - 1637 00ee 02 .byte 0x2 - 1638 00ef 23 .byte 0x23 - 1639 00f0 03 .uleb128 0x3 - 1640 00f1 07 .uleb128 0x7 - 1641 00f2 69000000 .4byte .LASF20 - 1642 00f6 03 .byte 0x3 - 1643 00f7 7F .byte 0x7f - 1644 00f8 6F000000 .4byte 0x6f - 1645 00fc 02 .byte 0x2 - 1646 00fd 23 .byte 0x23 - 1647 00fe 04 .uleb128 0x4 - 1648 00ff 07 .uleb128 0x7 - 1649 0100 7E010000 .4byte .LASF21 - 1650 0104 03 .byte 0x3 - 1651 0105 80 .byte 0x80 - 1652 0106 6F000000 .4byte 0x6f - 1653 010a 02 .byte 0x2 - 1654 010b 23 .byte 0x23 - 1655 010c 05 .uleb128 0x5 - 1656 010d 07 .uleb128 0x7 - 1657 010e A6040000 .4byte .LASF22 - 1658 0112 03 .byte 0x3 - 1659 0113 81 .byte 0x81 - 1660 0114 7A000000 .4byte 0x7a - 1661 0118 02 .byte 0x2 - 1662 0119 23 .byte 0x23 - 1663 011a 06 .uleb128 0x6 - 1664 011b 07 .uleb128 0x7 - 1665 011c 8C040000 .4byte .LASF23 - 1666 0120 03 .byte 0x3 - 1667 0121 82 .byte 0x82 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 54 - - - 1668 0122 7A000000 .4byte 0x7a - 1669 0126 02 .byte 0x2 - 1670 0127 23 .byte 0x23 - 1671 0128 08 .uleb128 0x8 - 1672 0129 07 .uleb128 0x7 - 1673 012a DE010000 .4byte .LASF24 - 1674 012e 03 .byte 0x3 - 1675 012f 83 .byte 0x83 - 1676 0130 6F000000 .4byte 0x6f - 1677 0134 02 .byte 0x2 - 1678 0135 23 .byte 0x23 - 1679 0136 0A .uleb128 0xa - 1680 0137 00 .byte 0 - 1681 0138 04 .uleb128 0x4 - 1682 0139 2F040000 .4byte .LASF25 - 1683 013d 03 .byte 0x3 - 1684 013e 84 .byte 0x84 - 1685 013f B1000000 .4byte 0xb1 - 1686 0143 06 .uleb128 0x6 - 1687 0144 08 .byte 0x8 - 1688 0145 03 .byte 0x3 - 1689 0146 86 .byte 0x86 - 1690 0147 A0010000 .4byte 0x1a0 - 1691 014b 07 .uleb128 0x7 - 1692 014c DE010000 .4byte .LASF24 - 1693 0150 03 .byte 0x3 - 1694 0151 88 .byte 0x88 - 1695 0152 6F000000 .4byte 0x6f - 1696 0156 02 .byte 0x2 - 1697 0157 23 .byte 0x23 - 1698 0158 00 .uleb128 0 - 1699 0159 07 .uleb128 0x7 - 1700 015a 7C040000 .4byte .LASF26 - 1701 015e 03 .byte 0x3 - 1702 015f 89 .byte 0x89 - 1703 0160 6F000000 .4byte 0x6f - 1704 0164 02 .byte 0x2 - 1705 0165 23 .byte 0x23 - 1706 0166 01 .uleb128 0x1 - 1707 0167 07 .uleb128 0x7 - 1708 0168 69000000 .4byte .LASF20 - 1709 016c 03 .byte 0x3 - 1710 016d 8A .byte 0x8a - 1711 016e 6F000000 .4byte 0x6f - 1712 0172 02 .byte 0x2 - 1713 0173 23 .byte 0x23 - 1714 0174 02 .uleb128 0x2 - 1715 0175 07 .uleb128 0x7 - 1716 0176 71040000 .4byte .LASF27 - 1717 017a 03 .byte 0x3 - 1718 017b 8B .byte 0x8b - 1719 017c 6F000000 .4byte 0x6f - 1720 0180 02 .byte 0x2 - 1721 0181 23 .byte 0x23 - 1722 0182 03 .uleb128 0x3 - 1723 0183 07 .uleb128 0x7 - 1724 0184 8C040000 .4byte .LASF23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 55 - - - 1725 0188 03 .byte 0x3 - 1726 0189 8C .byte 0x8c - 1727 018a 7A000000 .4byte 0x7a - 1728 018e 02 .byte 0x2 - 1729 018f 23 .byte 0x23 - 1730 0190 04 .uleb128 0x4 - 1731 0191 07 .uleb128 0x7 - 1732 0192 32050000 .4byte .LASF28 - 1733 0196 03 .byte 0x3 - 1734 0197 8D .byte 0x8d - 1735 0198 6F000000 .4byte 0x6f - 1736 019c 02 .byte 0x2 - 1737 019d 23 .byte 0x23 - 1738 019e 06 .uleb128 0x6 - 1739 019f 00 .byte 0 - 1740 01a0 04 .uleb128 0x4 - 1741 01a1 34010000 .4byte .LASF29 - 1742 01a5 03 .byte 0x3 - 1743 01a6 8E .byte 0x8e - 1744 01a7 43010000 .4byte 0x143 - 1745 01ab 06 .uleb128 0x6 - 1746 01ac 04 .byte 0x4 - 1747 01ad 03 .byte 0x3 - 1748 01ae 90 .byte 0x90 - 1749 01af D0010000 .4byte 0x1d0 - 1750 01b3 07 .uleb128 0x7 - 1751 01b4 13050000 .4byte .LASF30 - 1752 01b8 03 .byte 0x3 - 1753 01b9 92 .byte 0x92 - 1754 01ba 6F000000 .4byte 0x6f - 1755 01be 02 .byte 0x2 - 1756 01bf 23 .byte 0x23 - 1757 01c0 00 .uleb128 0 - 1758 01c1 07 .uleb128 0x7 - 1759 01c2 F8040000 .4byte .LASF31 - 1760 01c6 03 .byte 0x3 - 1761 01c7 93 .byte 0x93 - 1762 01c8 7A000000 .4byte 0x7a - 1763 01cc 02 .byte 0x2 - 1764 01cd 23 .byte 0x23 - 1765 01ce 02 .uleb128 0x2 - 1766 01cf 00 .byte 0 - 1767 01d0 04 .uleb128 0x4 - 1768 01d1 10030000 .4byte .LASF32 - 1769 01d5 03 .byte 0x3 - 1770 01d6 94 .byte 0x94 - 1771 01d7 AB010000 .4byte 0x1ab - 1772 01db 06 .uleb128 0x6 - 1773 01dc 0C .byte 0xc - 1774 01dd 03 .byte 0x3 - 1775 01de 96 .byte 0x96 - 1776 01df 0E020000 .4byte 0x20e - 1777 01e3 07 .uleb128 0x7 - 1778 01e4 0D000000 .4byte .LASF33 - 1779 01e8 03 .byte 0x3 - 1780 01e9 98 .byte 0x98 - 1781 01ea 7A000000 .4byte 0x7a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 56 - - - 1782 01ee 02 .byte 0x2 - 1783 01ef 23 .byte 0x23 - 1784 01f0 00 .uleb128 0 - 1785 01f1 07 .uleb128 0x7 - 1786 01f2 64010000 .4byte .LASF34 - 1787 01f6 03 .byte 0x3 - 1788 01f7 99 .byte 0x99 - 1789 01f8 0E020000 .4byte 0x20e - 1790 01fc 02 .byte 0x2 - 1791 01fd 23 .byte 0x23 - 1792 01fe 04 .uleb128 0x4 - 1793 01ff 07 .uleb128 0x7 - 1794 0200 00000000 .4byte .LASF35 - 1795 0204 03 .byte 0x3 - 1796 0205 9A .byte 0x9a - 1797 0206 14020000 .4byte 0x214 - 1798 020a 02 .byte 0x2 - 1799 020b 23 .byte 0x23 - 1800 020c 08 .uleb128 0x8 - 1801 020d 00 .byte 0 - 1802 020e 08 .uleb128 0x8 - 1803 020f 04 .byte 0x4 - 1804 0210 A5000000 .4byte 0xa5 - 1805 0214 08 .uleb128 0x8 - 1806 0215 04 .byte 0x4 - 1807 0216 D0010000 .4byte 0x1d0 - 1808 021a 04 .uleb128 0x4 - 1809 021b D0030000 .4byte .LASF36 - 1810 021f 03 .byte 0x3 - 1811 0220 9B .byte 0x9b - 1812 0221 DB010000 .4byte 0x1db - 1813 0225 06 .uleb128 0x6 - 1814 0226 08 .byte 0x8 - 1815 0227 03 .byte 0x3 - 1816 0228 9E .byte 0x9e - 1817 0229 48020000 .4byte 0x248 - 1818 022d 09 .uleb128 0x9 - 1819 022e 6300 .ascii "c\000" - 1820 0230 03 .byte 0x3 - 1821 0231 A0 .byte 0xa0 - 1822 0232 6F000000 .4byte 0x6f - 1823 0236 02 .byte 0x2 - 1824 0237 23 .byte 0x23 - 1825 0238 00 .uleb128 0 - 1826 0239 07 .uleb128 0x7 - 1827 023a A5020000 .4byte .LASF37 - 1828 023e 03 .byte 0x3 - 1829 023f A1 .byte 0xa1 - 1830 0240 48020000 .4byte 0x248 - 1831 0244 02 .byte 0x2 - 1832 0245 23 .byte 0x23 - 1833 0246 04 .uleb128 0x4 - 1834 0247 00 .byte 0 - 1835 0248 08 .uleb128 0x8 - 1836 0249 04 .byte 0x4 - 1837 024a 4E020000 .4byte 0x24e - 1838 024e 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 57 - - - 1839 024f 04 .uleb128 0x4 - 1840 0250 67050000 .4byte .LASF38 - 1841 0254 03 .byte 0x3 - 1842 0255 A2 .byte 0xa2 - 1843 0256 25020000 .4byte 0x225 - 1844 025a 0B .uleb128 0xb - 1845 025b 01 .byte 0x1 - 1846 025c B1040000 .4byte .LASF79 - 1847 0260 01 .byte 0x1 - 1848 0261 6E03 .2byte 0x36e - 1849 0263 01 .byte 0x1 - 1850 0264 69020000 .4byte 0x269 - 1851 0268 01 .byte 0x1 - 1852 0269 08 .uleb128 0x8 - 1853 026a 04 .byte 0x4 - 1854 026b 6F020000 .4byte 0x26f - 1855 026f 0C .uleb128 0xc - 1856 0270 4F020000 .4byte 0x24f - 1857 0274 0D .uleb128 0xd - 1858 0275 01 .byte 0x1 - 1859 0276 05010000 .4byte .LASF40 - 1860 027a 01 .byte 0x1 - 1861 027b 7E01 .2byte 0x17e - 1862 027d 01 .byte 0x1 - 1863 027e 00000000 .4byte .LFB1 - 1864 0282 B4000000 .4byte .LFE1 - 1865 0286 00000000 .4byte .LLST0 - 1866 028a 01 .byte 0x1 - 1867 028b AD020000 .4byte 0x2ad - 1868 028f 0E .uleb128 0xe - 1869 0290 657000 .ascii "ep\000" - 1870 0293 01 .byte 0x1 - 1871 0294 8001 .2byte 0x180 - 1872 0296 6F000000 .4byte 0x6f - 1873 029a 20000000 .4byte .LLST1 - 1874 029e 0E .uleb128 0xe - 1875 029f 6900 .ascii "i\000" - 1876 02a1 01 .byte 0x1 - 1877 02a2 8101 .2byte 0x181 - 1878 02a4 6F000000 .4byte 0x6f - 1879 02a8 57000000 .4byte .LLST2 - 1880 02ac 00 .byte 0 - 1881 02ad 0F .uleb128 0xf - 1882 02ae 01 .byte 0x1 - 1883 02af DB030000 .4byte .LASF44 - 1884 02b3 01 .byte 0x1 - 1885 02b4 5103 .2byte 0x351 - 1886 02b6 01 .byte 0x1 - 1887 02b7 69020000 .4byte 0x269 - 1888 02bb 00000000 .4byte .LFB4 - 1889 02bf 1C000000 .4byte .LFE4 - 1890 02c3 02 .byte 0x2 - 1891 02c4 7D .byte 0x7d - 1892 02c5 00 .sleb128 0 - 1893 02c6 01 .byte 0x1 - 1894 02c7 EA020000 .4byte 0x2ea - 1895 02cb 10 .uleb128 0x10 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 58 - - - 1896 02cc 6300 .ascii "c\000" - 1897 02ce 01 .byte 0x1 - 1898 02cf 5103 .2byte 0x351 - 1899 02d1 6F000000 .4byte 0x6f - 1900 02d5 8C000000 .4byte .LLST3 - 1901 02d9 11 .uleb128 0x11 - 1902 02da A0020000 .4byte .LASF39 - 1903 02de 01 .byte 0x1 - 1904 02df 5503 .2byte 0x355 - 1905 02e1 69020000 .4byte 0x269 - 1906 02e5 AD000000 .4byte .LLST4 - 1907 02e9 00 .byte 0 - 1908 02ea 0D .uleb128 0xd - 1909 02eb 01 .byte 0x1 - 1910 02ec F9020000 .4byte .LASF41 - 1911 02f0 01 .byte 0x1 - 1912 02f1 D302 .2byte 0x2d3 - 1913 02f3 01 .byte 0x1 - 1914 02f4 00000000 .4byte .LFB3 - 1915 02f8 28010000 .4byte .LFE3 - 1916 02fc C6000000 .4byte .LLST5 - 1917 0300 01 .byte 0x1 - 1918 0301 7B030000 .4byte 0x37b - 1919 0305 0E .uleb128 0xe - 1920 0306 657000 .ascii "ep\000" - 1921 0309 01 .byte 0x1 - 1922 030a D502 .2byte 0x2d5 - 1923 030c 6F000000 .4byte 0x6f - 1924 0310 E6000000 .4byte .LLST6 - 1925 0314 11 .uleb128 0x11 - 1926 0315 0C050000 .4byte .LASF42 - 1927 0319 01 .byte 0x1 - 1928 031a D602 .2byte 0x2d6 - 1929 031c 6F000000 .4byte 0x6f - 1930 0320 05010000 .4byte .LLST7 - 1931 0324 0E .uleb128 0xe - 1932 0325 6900 .ascii "i\000" - 1933 0327 01 .byte 0x1 - 1934 0328 D702 .2byte 0x2d7 - 1935 032a 6F000000 .4byte 0x6f - 1936 032e 2A010000 .4byte .LLST8 - 1937 0332 11 .uleb128 0x11 - 1938 0333 04050000 .4byte .LASF43 - 1939 0337 01 .byte 0x1 - 1940 0338 D802 .2byte 0x2d8 - 1941 033a 6F000000 .4byte 0x6f - 1942 033e 61010000 .4byte .LLST9 - 1943 0342 0E .uleb128 0xe - 1944 0343 726900 .ascii "ri\000" - 1945 0346 01 .byte 0x1 - 1946 0347 D902 .2byte 0x2d9 - 1947 0349 6F000000 .4byte 0x6f - 1948 034d A1010000 .4byte .LLST10 - 1949 0351 11 .uleb128 0x11 - 1950 0352 A0020000 .4byte .LASF39 - 1951 0356 01 .byte 0x1 - 1952 0357 DB02 .2byte 0x2db - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 59 - - - 1953 0359 69020000 .4byte 0x269 - 1954 035d D0010000 .4byte .LLST11 - 1955 0361 0E .uleb128 0xe - 1956 0362 70455000 .ascii "pEP\000" - 1957 0366 01 .byte 0x1 - 1958 0367 DC02 .2byte 0x2dc - 1959 0369 7B030000 .4byte 0x37b - 1960 036d E5010000 .4byte .LLST12 - 1961 0371 12 .uleb128 0x12 - 1962 0372 14000000 .4byte .LVL12 - 1963 0376 AD020000 .4byte 0x2ad - 1964 037a 00 .byte 0 - 1965 037b 08 .uleb128 0x8 - 1966 037c 04 .byte 0x4 - 1967 037d 81030000 .4byte 0x381 - 1968 0381 0C .uleb128 0xc - 1969 0382 A0010000 .4byte 0x1a0 - 1970 0386 13 .uleb128 0x13 - 1971 0387 5A020000 .4byte 0x25a - 1972 038b 00000000 .4byte .LFB5 - 1973 038f 18000000 .4byte .LFE5 - 1974 0393 02 .byte 0x2 - 1975 0394 7D .byte 0x7d - 1976 0395 00 .sleb128 0 - 1977 0396 01 .byte 0x1 - 1978 0397 14 .uleb128 0x14 - 1979 0398 01 .byte 0x1 - 1980 0399 A4010000 .4byte .LASF45 - 1981 039d 01 .byte 0x1 - 1982 039e 8503 .2byte 0x385 - 1983 03a0 01 .byte 0x1 - 1984 03a1 E0030000 .4byte 0x3e0 - 1985 03a5 00000000 .4byte .LFB6 - 1986 03a9 20000000 .4byte .LFE6 - 1987 03ad 04020000 .4byte .LLST13 - 1988 03b1 01 .byte 0x1 - 1989 03b2 E0030000 .4byte 0x3e0 - 1990 03b6 11 .uleb128 0x11 - 1991 03b7 A0020000 .4byte .LASF39 - 1992 03bb 01 .byte 0x1 - 1993 03bc 8803 .2byte 0x388 - 1994 03be 69020000 .4byte 0x269 - 1995 03c2 24020000 .4byte .LLST14 - 1996 03c6 11 .uleb128 0x11 - 1997 03c7 E4020000 .4byte .LASF46 - 1998 03cb 01 .byte 0x1 - 1999 03cc 8903 .2byte 0x389 - 2000 03ce 6F000000 .4byte 0x6f - 2001 03d2 49020000 .4byte .LLST15 - 2002 03d6 12 .uleb128 0x12 - 2003 03d7 0E000000 .4byte .LVL29 - 2004 03db AD020000 .4byte 0x2ad - 2005 03df 00 .byte 0 - 2006 03e0 08 .uleb128 0x8 - 2007 03e1 04 .byte 0x4 - 2008 03e2 E6030000 .4byte 0x3e6 - 2009 03e6 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 60 - - - 2010 03e7 6F000000 .4byte 0x6f - 2011 03eb 0D .uleb128 0xd - 2012 03ec 01 .byte 0x1 - 2013 03ed F8000000 .4byte .LASF47 - 2014 03f1 01 .byte 0x1 - 2015 03f2 DB01 .2byte 0x1db - 2016 03f4 01 .byte 0x1 - 2017 03f5 00000000 .4byte .LFB2 - 2018 03f9 68010000 .4byte .LFE2 - 2019 03fd 6C020000 .4byte .LLST16 - 2020 0401 01 .byte 0x1 - 2021 0402 BB040000 .4byte 0x4bb - 2022 0406 15 .uleb128 0x15 - 2023 0407 A6000000 .4byte .LASF48 - 2024 040b 01 .byte 0x1 - 2025 040c DB01 .2byte 0x1db - 2026 040e 6F000000 .4byte 0x6f - 2027 0412 8C020000 .4byte .LLST17 - 2028 0416 0E .uleb128 0xe - 2029 0417 657000 .ascii "ep\000" - 2030 041a 01 .byte 0x1 - 2031 041b DD01 .2byte 0x1dd - 2032 041d 6F000000 .4byte 0x6f - 2033 0421 AD020000 .4byte .LLST18 - 2034 0425 11 .uleb128 0x11 - 2035 0426 0C050000 .4byte .LASF42 - 2036 042a 01 .byte 0x1 - 2037 042b DE01 .2byte 0x1de - 2038 042d 6F000000 .4byte 0x6f - 2039 0431 E4020000 .4byte .LLST19 - 2040 0435 0E .uleb128 0xe - 2041 0436 6900 .ascii "i\000" - 2042 0438 01 .byte 0x1 - 2043 0439 DF01 .2byte 0x1df - 2044 043b 6F000000 .4byte 0x6f - 2045 043f 1B030000 .4byte .LLST20 - 2046 0443 11 .uleb128 0x11 - 2047 0444 04050000 .4byte .LASF43 - 2048 0448 01 .byte 0x1 - 2049 0449 E001 .2byte 0x1e0 - 2050 044b 6F000000 .4byte 0x6f - 2051 044f 5E030000 .4byte .LLST21 - 2052 0453 11 .uleb128 0x11 - 2053 0454 D7010000 .4byte .LASF49 - 2054 0458 01 .byte 0x1 - 2055 0459 E101 .2byte 0x1e1 - 2056 045b E0030000 .4byte 0x3e0 - 2057 045f 9E030000 .4byte .LLST22 - 2058 0463 11 .uleb128 0x11 - 2059 0464 AC020000 .4byte .LASF50 - 2060 0468 01 .byte 0x1 - 2061 0469 E301 .2byte 0x1e3 - 2062 046b 7A000000 .4byte 0x7a - 2063 046f B2030000 .4byte .LLST23 - 2064 0473 11 .uleb128 0x11 - 2065 0474 A0020000 .4byte .LASF39 - 2066 0478 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 61 - - - 2067 0479 E601 .2byte 0x1e6 - 2068 047b 69020000 .4byte 0x269 - 2069 047f DD030000 .4byte .LLST24 - 2070 0483 0E .uleb128 0xe - 2071 0484 70455000 .ascii "pEP\000" - 2072 0488 01 .byte 0x1 - 2073 0489 E701 .2byte 0x1e7 - 2074 048b 7B030000 .4byte 0x37b - 2075 048f FD030000 .4byte .LLST25 - 2076 0493 16 .uleb128 0x16 - 2077 0494 44000000 .4byte .LVL36 - 2078 0498 AD020000 .4byte 0x2ad - 2079 049c A7040000 .4byte 0x4a7 - 2080 04a0 17 .uleb128 0x17 - 2081 04a1 01 .byte 0x1 - 2082 04a2 50 .byte 0x50 - 2083 04a3 02 .byte 0x2 - 2084 04a4 74 .byte 0x74 - 2085 04a5 7F .sleb128 -1 - 2086 04a6 00 .byte 0 - 2087 04a7 12 .uleb128 0x12 - 2088 04a8 28010000 .4byte .LVL54 - 2089 04ac 97030000 .4byte 0x397 - 2090 04b0 18 .uleb128 0x18 - 2091 04b1 4E010000 .4byte .LVL58 - 2092 04b5 01 .byte 0x1 - 2093 04b6 74020000 .4byte 0x274 - 2094 04ba 00 .byte 0 - 2095 04bb 19 .uleb128 0x19 - 2096 04bc 01 .byte 0x1 - 2097 04bd 1A000000 .4byte .LASF51 - 2098 04c1 01 .byte 0x1 - 2099 04c2 A603 .2byte 0x3a6 - 2100 04c4 01 .byte 0x1 - 2101 04c5 00000000 .4byte .LFB7 - 2102 04c9 40000000 .4byte .LFE7 - 2103 04cd 02 .byte 0x2 - 2104 04ce 7D .byte 0x7d - 2105 04cf 00 .sleb128 0 - 2106 04d0 01 .byte 0x1 - 2107 04d1 F4040000 .4byte 0x4f4 - 2108 04d5 10 .uleb128 0x10 - 2109 04d6 657000 .ascii "ep\000" - 2110 04d9 01 .byte 0x1 - 2111 04da A603 .2byte 0x3a6 - 2112 04dc 6F000000 .4byte 0x6f - 2113 04e0 1D040000 .4byte .LLST26 - 2114 04e4 0E .uleb128 0xe - 2115 04e5 726900 .ascii "ri\000" - 2116 04e8 01 .byte 0x1 - 2117 04e9 A803 .2byte 0x3a8 - 2118 04eb 6F000000 .4byte 0x6f - 2119 04ef 3B040000 .4byte .LLST27 - 2120 04f3 00 .byte 0 - 2121 04f4 0F .uleb128 0xf - 2122 04f5 01 .byte 0x1 - 2123 04f6 4E010000 .4byte .LASF52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 62 - - - 2124 04fa 01 .byte 0x1 - 2125 04fb D503 .2byte 0x3d5 - 2126 04fd 01 .byte 0x1 - 2127 04fe 6F000000 .4byte 0x6f - 2128 0502 00000000 .4byte .LFB8 - 2129 0506 58000000 .4byte .LFE8 - 2130 050a 02 .byte 0x2 - 2131 050b 7D .byte 0x7d - 2132 050c 00 .sleb128 0 - 2133 050d 01 .byte 0x1 - 2134 050e 48050000 .4byte 0x548 - 2135 0512 0E .uleb128 0xe - 2136 0513 657000 .ascii "ep\000" - 2137 0516 01 .byte 0x1 - 2138 0517 D703 .2byte 0x3d7 - 2139 0519 6F000000 .4byte 0x6f - 2140 051d 61040000 .4byte .LLST28 - 2141 0521 0E .uleb128 0xe - 2142 0522 726900 .ascii "ri\000" - 2143 0525 01 .byte 0x1 - 2144 0526 D803 .2byte 0x3d8 - 2145 0528 6F000000 .4byte 0x6f - 2146 052c 7F040000 .4byte .LLST29 - 2147 0530 1A .uleb128 0x1a - 2148 0531 97040000 .4byte .LASF53 - 2149 0535 01 .byte 0x1 - 2150 0536 D903 .2byte 0x3d9 - 2151 0538 6F000000 .4byte 0x6f - 2152 053c 00 .byte 0 - 2153 053d 18 .uleb128 0x18 - 2154 053e 46000000 .4byte .LVL69 - 2155 0542 01 .byte 0x1 - 2156 0543 73080000 .4byte 0x873 - 2157 0547 00 .byte 0 - 2158 0548 14 .uleb128 0x14 - 2159 0549 01 .byte 0x1 - 2160 054a CA000000 .4byte .LASF54 - 2161 054e 01 .byte 0x1 - 2162 054f 0C04 .2byte 0x40c - 2163 0551 01 .byte 0x1 - 2164 0552 6F000000 .4byte 0x6f - 2165 0556 00000000 .4byte .LFB9 - 2166 055a 7C000000 .4byte .LFE9 - 2167 055e C3040000 .4byte .LLST30 - 2168 0562 01 .byte 0x1 - 2169 0563 9D050000 .4byte 0x59d - 2170 0567 0E .uleb128 0xe - 2171 0568 657000 .ascii "ep\000" - 2172 056b 01 .byte 0x1 - 2173 056c 0E04 .2byte 0x40e - 2174 056e 6F000000 .4byte 0x6f - 2175 0572 E3040000 .4byte .LLST31 - 2176 0576 0E .uleb128 0xe - 2177 0577 726900 .ascii "ri\000" - 2178 057a 01 .byte 0x1 - 2179 057b 0F04 .2byte 0x40f - 2180 057d 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 63 - - - 2181 0581 01050000 .4byte .LLST32 - 2182 0585 1A .uleb128 0x1a - 2183 0586 97040000 .4byte .LASF53 - 2184 058a 01 .byte 0x1 - 2185 058b 1004 .2byte 0x410 - 2186 058d 6F000000 .4byte 0x6f - 2187 0591 00 .byte 0 - 2188 0592 18 .uleb128 0x18 - 2189 0593 68000000 .4byte .LVL76 - 2190 0597 01 .byte 0x1 - 2191 0598 73080000 .4byte 0x873 - 2192 059c 00 .byte 0 - 2193 059d 14 .uleb128 0x14 - 2194 059e 01 .byte 0x1 - 2195 059f E8010000 .4byte .LASF55 - 2196 05a3 01 .byte 0x1 - 2197 05a4 5304 .2byte 0x453 - 2198 05a6 01 .byte 0x1 - 2199 05a7 6F000000 .4byte 0x6f - 2200 05ab 00000000 .4byte .LFB10 - 2201 05af 48000000 .4byte .LFE10 - 2202 05b3 27050000 .4byte .LLST33 - 2203 05b7 01 .byte 0x1 - 2204 05b8 04060000 .4byte 0x604 - 2205 05bc 11 .uleb128 0x11 - 2206 05bd 97040000 .4byte .LASF53 - 2207 05c1 01 .byte 0x1 - 2208 05c2 5504 .2byte 0x455 - 2209 05c4 6F000000 .4byte 0x6f - 2210 05c8 47050000 .4byte .LLST34 - 2211 05cc 1B .uleb128 0x1b - 2212 05cd 2A030000 .4byte .LASF56 - 2213 05d1 01 .byte 0x1 - 2214 05d2 5604 .2byte 0x456 - 2215 05d4 6F000000 .4byte 0x6f - 2216 05d8 01 .byte 0x1 - 2217 05d9 54 .byte 0x54 - 2218 05da 11 .uleb128 0x11 - 2219 05db A0020000 .4byte .LASF39 - 2220 05df 01 .byte 0x1 - 2221 05e0 5704 .2byte 0x457 - 2222 05e2 69020000 .4byte 0x269 - 2223 05e6 66050000 .4byte .LLST35 - 2224 05ea 11 .uleb128 0x11 - 2225 05eb E4020000 .4byte .LASF46 - 2226 05ef 01 .byte 0x1 - 2227 05f0 5804 .2byte 0x458 - 2228 05f2 6F000000 .4byte 0x6f - 2229 05f6 79050000 .4byte .LLST36 - 2230 05fa 12 .uleb128 0x12 - 2231 05fb 12000000 .4byte .LVL79 - 2232 05ff AD020000 .4byte 0x2ad - 2233 0603 00 .byte 0 - 2234 0604 1C .uleb128 0x1c - 2235 0605 01 .byte 0x1 - 2236 0606 4E050000 .4byte .LASF57 - 2237 060a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 64 - - - 2238 060b 59 .byte 0x59 - 2239 060c 01 .byte 0x1 - 2240 060d 6F000000 .4byte 0x6f - 2241 0611 00000000 .4byte .LFB0 - 2242 0615 74020000 .4byte .LFE0 - 2243 0619 B3050000 .4byte .LLST37 - 2244 061d 01 .byte 0x1 - 2245 061e FD060000 .4byte 0x6fd - 2246 0622 1D .uleb128 0x1d - 2247 0623 97040000 .4byte .LASF53 - 2248 0627 01 .byte 0x1 - 2249 0628 5B .byte 0x5b - 2250 0629 6F000000 .4byte 0x6f - 2251 062d D3050000 .4byte .LLST38 - 2252 0631 1D .uleb128 0x1d - 2253 0632 6E000000 .4byte .LASF58 - 2254 0636 01 .byte 0x1 - 2255 0637 5C .byte 0x5c - 2256 0638 6F000000 .4byte 0x6f - 2257 063c E7050000 .4byte .LLST39 - 2258 0640 1D .uleb128 0x1d - 2259 0641 65030000 .4byte .LASF59 - 2260 0645 01 .byte 0x1 - 2261 0646 5E .byte 0x5e - 2262 0647 0E020000 .4byte 0x20e - 2263 064b FA050000 .4byte .LLST40 - 2264 064f 1D .uleb128 0x1d - 2265 0650 FF040000 .4byte .LASF60 - 2266 0654 01 .byte 0x1 - 2267 0655 60 .byte 0x60 - 2268 0656 6F000000 .4byte 0x6f - 2269 065a 3C060000 .4byte .LLST41 - 2270 065e 1D .uleb128 0x1d - 2271 065f 8B020000 .4byte .LASF61 - 2272 0663 01 .byte 0x1 - 2273 0664 61 .byte 0x61 - 2274 0665 6F000000 .4byte 0x6f - 2275 0669 65060000 .4byte .LLST42 - 2276 066d 1E .uleb128 0x1e - 2277 066e 7E000000 .4byte .LASF62 - 2278 0672 01 .byte 0x1 - 2279 0673 64 .byte 0x64 - 2280 0674 0D070000 .4byte 0x70d - 2281 0678 05 .byte 0x5 - 2282 0679 03 .byte 0x3 - 2283 067a 00000000 .4byte USBFS_tBuffer.5008 - 2284 067e 1D .uleb128 0x1d - 2285 067f A0020000 .4byte .LASF39 - 2286 0683 01 .byte 0x1 - 2287 0684 65 .byte 0x65 - 2288 0685 69020000 .4byte 0x269 - 2289 0689 78060000 .4byte .LLST43 - 2290 068d 1F .uleb128 0x1f - 2291 068e 5A020000 .4byte 0x25a - 2292 0692 40000000 .4byte .LBB4 - 2293 0696 4A000000 .4byte .LBE4 - 2294 069a 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 65 - - - 2295 069b 70 .byte 0x70 - 2296 069c 12 .uleb128 0x12 - 2297 069d 64000000 .4byte .LVL86 - 2298 06a1 AD020000 .4byte 0x2ad - 2299 06a5 18 .uleb128 0x18 - 2300 06a6 80000000 .4byte .LVL89 - 2301 06aa 01 .byte 0x1 - 2302 06ab 81080000 .4byte 0x881 - 2303 06af 18 .uleb128 0x18 - 2304 06b0 D2000000 .4byte .LVL99 - 2305 06b4 01 .byte 0x1 - 2306 06b5 8F080000 .4byte 0x88f - 2307 06b9 16 .uleb128 0x16 - 2308 06ba 68010000 .4byte .LVL100 - 2309 06be EB030000 .4byte 0x3eb - 2310 06c2 CC060000 .4byte 0x6cc - 2311 06c6 17 .uleb128 0x17 - 2312 06c7 01 .byte 0x1 - 2313 06c8 50 .byte 0x50 - 2314 06c9 01 .byte 0x1 - 2315 06ca 31 .byte 0x31 - 2316 06cb 00 .byte 0 - 2317 06cc 12 .uleb128 0x12 - 2318 06cd 6E010000 .4byte .LVL101 - 2319 06d1 9D050000 .4byte 0x59d - 2320 06d5 12 .uleb128 0x12 - 2321 06d6 84010000 .4byte .LVL103 - 2322 06da EA020000 .4byte 0x2ea - 2323 06de 18 .uleb128 0x18 - 2324 06df AE010000 .4byte .LVL105 - 2325 06e3 01 .byte 0x1 - 2326 06e4 48050000 .4byte 0x548 - 2327 06e8 18 .uleb128 0x18 - 2328 06e9 E0010000 .4byte .LVL107 - 2329 06ed 01 .byte 0x1 - 2330 06ee F4040000 .4byte 0x4f4 - 2331 06f2 18 .uleb128 0x18 - 2332 06f3 62020000 .4byte .LVL111 - 2333 06f7 01 .byte 0x1 - 2334 06f8 73080000 .4byte 0x873 - 2335 06fc 00 .byte 0 - 2336 06fd 20 .uleb128 0x20 - 2337 06fe 6F000000 .4byte 0x6f - 2338 0702 0D070000 .4byte 0x70d - 2339 0706 21 .uleb128 0x21 - 2340 0707 AA000000 .4byte 0xaa - 2341 070b 01 .byte 0x1 - 2342 070c 00 .byte 0 - 2343 070d 05 .uleb128 0x5 - 2344 070e FD060000 .4byte 0x6fd - 2345 0712 22 .uleb128 0x22 - 2346 0713 64040000 .4byte .LASF63 - 2347 0717 03 .byte 0x3 - 2348 0718 1802 .2byte 0x218 - 2349 071a A5000000 .4byte 0xa5 - 2350 071e 01 .byte 0x1 - 2351 071f 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 66 - - - 2352 0720 22 .uleb128 0x22 - 2353 0721 6A010000 .4byte .LASF64 - 2354 0725 03 .byte 0x3 - 2355 0726 1A02 .2byte 0x21a - 2356 0728 A5000000 .4byte 0xa5 - 2357 072c 01 .byte 0x1 - 2358 072d 01 .byte 0x1 - 2359 072e 22 .uleb128 0x22 - 2360 072f 07020000 .4byte .LASF65 - 2361 0733 03 .byte 0x3 - 2362 0734 1B02 .2byte 0x21b - 2363 0736 A5000000 .4byte 0xa5 - 2364 073a 01 .byte 0x1 - 2365 073b 01 .byte 0x1 - 2366 073c 22 .uleb128 0x22 - 2367 073d C9040000 .4byte .LASF66 - 2368 0741 03 .byte 0x3 - 2369 0742 1C02 .2byte 0x21c - 2370 0744 A5000000 .4byte 0xa5 - 2371 0748 01 .byte 0x1 - 2372 0749 01 .byte 0x1 - 2373 074a 20 .uleb128 0x20 - 2374 074b 6F000000 .4byte 0x6f - 2375 074f 5A070000 .4byte 0x75a - 2376 0753 21 .uleb128 0x21 - 2377 0754 AA000000 .4byte 0xaa - 2378 0758 11 .byte 0x11 - 2379 0759 00 .byte 0 - 2380 075a 23 .uleb128 0x23 - 2381 075b 37030000 .4byte .LASF67 - 2382 075f 04 .byte 0x4 - 2383 0760 1C .byte 0x1c - 2384 0761 67070000 .4byte 0x767 - 2385 0765 01 .byte 0x1 - 2386 0766 01 .byte 0x1 - 2387 0767 0C .uleb128 0xc - 2388 0768 4A070000 .4byte 0x74a - 2389 076c 20 .uleb128 0x20 - 2390 076d 4F020000 .4byte 0x24f - 2391 0771 7C070000 .4byte 0x77c - 2392 0775 21 .uleb128 0x21 - 2393 0776 AA000000 .4byte 0xaa - 2394 077a 00 .byte 0 - 2395 077b 00 .byte 0 - 2396 077c 23 .uleb128 0x23 - 2397 077d BD020000 .4byte .LASF68 - 2398 0781 04 .byte 0x4 - 2399 0782 23 .byte 0x23 - 2400 0783 89070000 .4byte 0x789 - 2401 0787 01 .byte 0x1 - 2402 0788 01 .byte 0x1 - 2403 0789 0C .uleb128 0xc - 2404 078a 6C070000 .4byte 0x76c - 2405 078e 20 .uleb128 0x20 - 2406 078f 6F000000 .4byte 0x6f - 2407 0793 9E070000 .4byte 0x79e - 2408 0797 21 .uleb128 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 67 - - - 2409 0798 AA000000 .4byte 0xaa - 2410 079c 09 .byte 0x9 - 2411 079d 00 .byte 0 - 2412 079e 23 .uleb128 0x23 - 2413 079f C9020000 .4byte .LASF69 - 2414 07a3 04 .byte 0x4 - 2415 07a4 24 .byte 0x24 - 2416 07a5 AB070000 .4byte 0x7ab - 2417 07a9 01 .byte 0x1 - 2418 07aa 01 .byte 0x1 - 2419 07ab 0C .uleb128 0xc - 2420 07ac 8E070000 .4byte 0x78e - 2421 07b0 20 .uleb128 0x20 - 2422 07b1 6F000000 .4byte 0x6f - 2423 07b5 C0070000 .4byte 0x7c0 - 2424 07b9 21 .uleb128 0x21 - 2425 07ba AA000000 .4byte 0xaa - 2426 07be 52 .byte 0x52 - 2427 07bf 00 .byte 0 - 2428 07c0 23 .uleb128 0x23 - 2429 07c1 68020000 .4byte .LASF70 - 2430 07c5 04 .byte 0x4 - 2431 07c6 25 .byte 0x25 - 2432 07c7 CD070000 .4byte 0x7cd - 2433 07cb 01 .byte 0x1 - 2434 07cc 01 .byte 0x1 - 2435 07cd 0C .uleb128 0xc - 2436 07ce B0070000 .4byte 0x7b0 - 2437 07d2 23 .uleb128 0x23 - 2438 07d3 E2000000 .4byte .LASF71 - 2439 07d7 04 .byte 0x4 - 2440 07d8 38 .byte 0x38 - 2441 07d9 A5000000 .4byte 0xa5 - 2442 07dd 01 .byte 0x1 - 2443 07de 01 .byte 0x1 - 2444 07df 20 .uleb128 0x20 - 2445 07e0 6F000000 .4byte 0x6f - 2446 07e4 EF070000 .4byte 0x7ef - 2447 07e8 21 .uleb128 0x21 - 2448 07e9 AA000000 .4byte 0xaa - 2449 07ed 00 .byte 0 - 2450 07ee 00 .byte 0 - 2451 07ef 23 .uleb128 0x23 - 2452 07f0 18040000 .4byte .LASF72 - 2453 07f4 04 .byte 0x4 - 2454 07f5 39 .byte 0x39 - 2455 07f6 FC070000 .4byte 0x7fc - 2456 07fa 01 .byte 0x1 - 2457 07fb 01 .byte 0x1 - 2458 07fc 05 .uleb128 0x5 - 2459 07fd DF070000 .4byte 0x7df - 2460 0801 23 .uleb128 0x23 - 2461 0802 DC040000 .4byte .LASF73 - 2462 0806 04 .byte 0x4 - 2463 0807 3A .byte 0x3a - 2464 0808 0E080000 .4byte 0x80e - 2465 080c 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 68 - - - 2466 080d 01 .byte 0x1 - 2467 080e 05 .uleb128 0x5 - 2468 080f DF070000 .4byte 0x7df - 2469 0813 23 .uleb128 0x23 - 2470 0814 B6000000 .4byte .LASF74 - 2471 0818 04 .byte 0x4 - 2472 0819 3B .byte 0x3b - 2473 081a A5000000 .4byte 0xa5 - 2474 081e 01 .byte 0x1 - 2475 081f 01 .byte 0x1 - 2476 0820 23 .uleb128 0x23 - 2477 0821 38050000 .4byte .LASF75 - 2478 0825 04 .byte 0x4 - 2479 0826 3C .byte 0x3c - 2480 0827 2D080000 .4byte 0x82d - 2481 082b 01 .byte 0x1 - 2482 082c 01 .byte 0x1 - 2483 082d 05 .uleb128 0x5 - 2484 082e DF070000 .4byte 0x7df - 2485 0832 23 .uleb128 0x23 - 2486 0833 53020000 .4byte .LASF76 - 2487 0837 04 .byte 0x4 - 2488 0838 3D .byte 0x3d - 2489 0839 E0030000 .4byte 0x3e0 - 2490 083d 01 .byte 0x1 - 2491 083e 01 .byte 0x1 - 2492 083f 20 .uleb128 0x20 - 2493 0840 38010000 .4byte 0x138 - 2494 0844 4F080000 .4byte 0x84f - 2495 0848 21 .uleb128 0x21 - 2496 0849 AA000000 .4byte 0xaa - 2497 084d 08 .byte 0x8 - 2498 084e 00 .byte 0 - 2499 084f 23 .uleb128 0x23 - 2500 0850 5C030000 .4byte .LASF77 - 2501 0854 04 .byte 0x4 - 2502 0855 3F .byte 0x3f - 2503 0856 5C080000 .4byte 0x85c - 2504 085a 01 .byte 0x1 - 2505 085b 01 .byte 0x1 - 2506 085c 05 .uleb128 0x5 - 2507 085d 3F080000 .4byte 0x83f - 2508 0861 23 .uleb128 0x23 - 2509 0862 2C000000 .4byte .LASF78 - 2510 0866 04 .byte 0x4 - 2511 0867 40 .byte 0x40 - 2512 0868 6E080000 .4byte 0x86e - 2513 086c 01 .byte 0x1 - 2514 086d 01 .byte 0x1 - 2515 086e 05 .uleb128 0x5 - 2516 086f 1A020000 .4byte 0x21a - 2517 0873 24 .uleb128 0x24 - 2518 0874 01 .byte 0x1 - 2519 0875 44040000 .4byte .LASF80 - 2520 0879 04 .byte 0x4 - 2521 087a 63 .byte 0x63 - 2522 087b 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 69 - - - 2523 087c 6F000000 .4byte 0x6f - 2524 0880 01 .byte 0x1 - 2525 0881 24 .uleb128 0x24 - 2526 0882 01 .byte 0x1 - 2527 0883 3C000000 .4byte .LASF81 - 2528 0887 04 .byte 0x4 - 2529 0888 56 .byte 0x56 - 2530 0889 01 .byte 0x1 - 2531 088a 6F000000 .4byte 0x6f - 2532 088e 01 .byte 0x1 - 2533 088f 24 .uleb128 0x24 - 2534 0890 01 .byte 0x1 - 2535 0891 1A050000 .4byte .LASF82 - 2536 0895 04 .byte 0x4 - 2537 0896 B2 .byte 0xb2 - 2538 0897 01 .byte 0x1 - 2539 0898 6F000000 .4byte 0x6f - 2540 089c 01 .byte 0x1 - 2541 089d 00 .byte 0 - 2542 .section .debug_abbrev,"",%progbits - 2543 .Ldebug_abbrev0: - 2544 0000 01 .uleb128 0x1 - 2545 0001 11 .uleb128 0x11 - 2546 0002 01 .byte 0x1 - 2547 0003 25 .uleb128 0x25 - 2548 0004 0E .uleb128 0xe - 2549 0005 13 .uleb128 0x13 - 2550 0006 0B .uleb128 0xb - 2551 0007 03 .uleb128 0x3 - 2552 0008 0E .uleb128 0xe - 2553 0009 1B .uleb128 0x1b - 2554 000a 0E .uleb128 0xe - 2555 000b 55 .uleb128 0x55 - 2556 000c 06 .uleb128 0x6 - 2557 000d 11 .uleb128 0x11 - 2558 000e 01 .uleb128 0x1 - 2559 000f 52 .uleb128 0x52 - 2560 0010 01 .uleb128 0x1 - 2561 0011 10 .uleb128 0x10 - 2562 0012 06 .uleb128 0x6 - 2563 0013 00 .byte 0 - 2564 0014 00 .byte 0 - 2565 0015 02 .uleb128 0x2 - 2566 0016 24 .uleb128 0x24 - 2567 0017 00 .byte 0 - 2568 0018 0B .uleb128 0xb - 2569 0019 0B .uleb128 0xb - 2570 001a 3E .uleb128 0x3e - 2571 001b 0B .uleb128 0xb - 2572 001c 03 .uleb128 0x3 - 2573 001d 0E .uleb128 0xe - 2574 001e 00 .byte 0 - 2575 001f 00 .byte 0 - 2576 0020 03 .uleb128 0x3 - 2577 0021 24 .uleb128 0x24 - 2578 0022 00 .byte 0 - 2579 0023 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 70 - - - 2580 0024 0B .uleb128 0xb - 2581 0025 3E .uleb128 0x3e - 2582 0026 0B .uleb128 0xb - 2583 0027 03 .uleb128 0x3 - 2584 0028 08 .uleb128 0x8 - 2585 0029 00 .byte 0 - 2586 002a 00 .byte 0 - 2587 002b 04 .uleb128 0x4 - 2588 002c 16 .uleb128 0x16 - 2589 002d 00 .byte 0 - 2590 002e 03 .uleb128 0x3 - 2591 002f 0E .uleb128 0xe - 2592 0030 3A .uleb128 0x3a - 2593 0031 0B .uleb128 0xb - 2594 0032 3B .uleb128 0x3b - 2595 0033 0B .uleb128 0xb - 2596 0034 49 .uleb128 0x49 - 2597 0035 13 .uleb128 0x13 - 2598 0036 00 .byte 0 - 2599 0037 00 .byte 0 - 2600 0038 05 .uleb128 0x5 - 2601 0039 35 .uleb128 0x35 - 2602 003a 00 .byte 0 - 2603 003b 49 .uleb128 0x49 - 2604 003c 13 .uleb128 0x13 - 2605 003d 00 .byte 0 - 2606 003e 00 .byte 0 - 2607 003f 06 .uleb128 0x6 - 2608 0040 13 .uleb128 0x13 - 2609 0041 01 .byte 0x1 - 2610 0042 0B .uleb128 0xb - 2611 0043 0B .uleb128 0xb - 2612 0044 3A .uleb128 0x3a - 2613 0045 0B .uleb128 0xb - 2614 0046 3B .uleb128 0x3b - 2615 0047 0B .uleb128 0xb - 2616 0048 01 .uleb128 0x1 - 2617 0049 13 .uleb128 0x13 - 2618 004a 00 .byte 0 - 2619 004b 00 .byte 0 - 2620 004c 07 .uleb128 0x7 - 2621 004d 0D .uleb128 0xd - 2622 004e 00 .byte 0 - 2623 004f 03 .uleb128 0x3 - 2624 0050 0E .uleb128 0xe - 2625 0051 3A .uleb128 0x3a - 2626 0052 0B .uleb128 0xb - 2627 0053 3B .uleb128 0x3b - 2628 0054 0B .uleb128 0xb - 2629 0055 49 .uleb128 0x49 - 2630 0056 13 .uleb128 0x13 - 2631 0057 38 .uleb128 0x38 - 2632 0058 0A .uleb128 0xa - 2633 0059 00 .byte 0 - 2634 005a 00 .byte 0 - 2635 005b 08 .uleb128 0x8 - 2636 005c 0F .uleb128 0xf - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 71 - - - 2637 005d 00 .byte 0 - 2638 005e 0B .uleb128 0xb - 2639 005f 0B .uleb128 0xb - 2640 0060 49 .uleb128 0x49 - 2641 0061 13 .uleb128 0x13 - 2642 0062 00 .byte 0 - 2643 0063 00 .byte 0 - 2644 0064 09 .uleb128 0x9 - 2645 0065 0D .uleb128 0xd - 2646 0066 00 .byte 0 - 2647 0067 03 .uleb128 0x3 - 2648 0068 08 .uleb128 0x8 - 2649 0069 3A .uleb128 0x3a - 2650 006a 0B .uleb128 0xb - 2651 006b 3B .uleb128 0x3b - 2652 006c 0B .uleb128 0xb - 2653 006d 49 .uleb128 0x49 - 2654 006e 13 .uleb128 0x13 - 2655 006f 38 .uleb128 0x38 - 2656 0070 0A .uleb128 0xa - 2657 0071 00 .byte 0 - 2658 0072 00 .byte 0 - 2659 0073 0A .uleb128 0xa - 2660 0074 26 .uleb128 0x26 - 2661 0075 00 .byte 0 - 2662 0076 00 .byte 0 - 2663 0077 00 .byte 0 - 2664 0078 0B .uleb128 0xb - 2665 0079 2E .uleb128 0x2e - 2666 007a 00 .byte 0 - 2667 007b 3F .uleb128 0x3f - 2668 007c 0C .uleb128 0xc - 2669 007d 03 .uleb128 0x3 - 2670 007e 0E .uleb128 0xe - 2671 007f 3A .uleb128 0x3a - 2672 0080 0B .uleb128 0xb - 2673 0081 3B .uleb128 0x3b - 2674 0082 05 .uleb128 0x5 - 2675 0083 27 .uleb128 0x27 - 2676 0084 0C .uleb128 0xc - 2677 0085 49 .uleb128 0x49 - 2678 0086 13 .uleb128 0x13 - 2679 0087 20 .uleb128 0x20 - 2680 0088 0B .uleb128 0xb - 2681 0089 00 .byte 0 - 2682 008a 00 .byte 0 - 2683 008b 0C .uleb128 0xc - 2684 008c 26 .uleb128 0x26 - 2685 008d 00 .byte 0 - 2686 008e 49 .uleb128 0x49 - 2687 008f 13 .uleb128 0x13 - 2688 0090 00 .byte 0 - 2689 0091 00 .byte 0 - 2690 0092 0D .uleb128 0xd - 2691 0093 2E .uleb128 0x2e - 2692 0094 01 .byte 0x1 - 2693 0095 3F .uleb128 0x3f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 72 - - - 2694 0096 0C .uleb128 0xc - 2695 0097 03 .uleb128 0x3 - 2696 0098 0E .uleb128 0xe - 2697 0099 3A .uleb128 0x3a - 2698 009a 0B .uleb128 0xb - 2699 009b 3B .uleb128 0x3b - 2700 009c 05 .uleb128 0x5 - 2701 009d 27 .uleb128 0x27 - 2702 009e 0C .uleb128 0xc - 2703 009f 11 .uleb128 0x11 - 2704 00a0 01 .uleb128 0x1 - 2705 00a1 12 .uleb128 0x12 - 2706 00a2 01 .uleb128 0x1 - 2707 00a3 40 .uleb128 0x40 - 2708 00a4 06 .uleb128 0x6 - 2709 00a5 9742 .uleb128 0x2117 - 2710 00a7 0C .uleb128 0xc - 2711 00a8 01 .uleb128 0x1 - 2712 00a9 13 .uleb128 0x13 - 2713 00aa 00 .byte 0 - 2714 00ab 00 .byte 0 - 2715 00ac 0E .uleb128 0xe - 2716 00ad 34 .uleb128 0x34 - 2717 00ae 00 .byte 0 - 2718 00af 03 .uleb128 0x3 - 2719 00b0 08 .uleb128 0x8 - 2720 00b1 3A .uleb128 0x3a - 2721 00b2 0B .uleb128 0xb - 2722 00b3 3B .uleb128 0x3b - 2723 00b4 05 .uleb128 0x5 - 2724 00b5 49 .uleb128 0x49 - 2725 00b6 13 .uleb128 0x13 - 2726 00b7 02 .uleb128 0x2 - 2727 00b8 06 .uleb128 0x6 - 2728 00b9 00 .byte 0 - 2729 00ba 00 .byte 0 - 2730 00bb 0F .uleb128 0xf - 2731 00bc 2E .uleb128 0x2e - 2732 00bd 01 .byte 0x1 - 2733 00be 3F .uleb128 0x3f - 2734 00bf 0C .uleb128 0xc - 2735 00c0 03 .uleb128 0x3 - 2736 00c1 0E .uleb128 0xe - 2737 00c2 3A .uleb128 0x3a - 2738 00c3 0B .uleb128 0xb - 2739 00c4 3B .uleb128 0x3b - 2740 00c5 05 .uleb128 0x5 - 2741 00c6 27 .uleb128 0x27 - 2742 00c7 0C .uleb128 0xc - 2743 00c8 49 .uleb128 0x49 - 2744 00c9 13 .uleb128 0x13 - 2745 00ca 11 .uleb128 0x11 - 2746 00cb 01 .uleb128 0x1 - 2747 00cc 12 .uleb128 0x12 - 2748 00cd 01 .uleb128 0x1 - 2749 00ce 40 .uleb128 0x40 - 2750 00cf 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 73 - - - 2751 00d0 9742 .uleb128 0x2117 - 2752 00d2 0C .uleb128 0xc - 2753 00d3 01 .uleb128 0x1 - 2754 00d4 13 .uleb128 0x13 - 2755 00d5 00 .byte 0 - 2756 00d6 00 .byte 0 - 2757 00d7 10 .uleb128 0x10 - 2758 00d8 05 .uleb128 0x5 - 2759 00d9 00 .byte 0 - 2760 00da 03 .uleb128 0x3 - 2761 00db 08 .uleb128 0x8 - 2762 00dc 3A .uleb128 0x3a - 2763 00dd 0B .uleb128 0xb - 2764 00de 3B .uleb128 0x3b - 2765 00df 05 .uleb128 0x5 - 2766 00e0 49 .uleb128 0x49 - 2767 00e1 13 .uleb128 0x13 - 2768 00e2 02 .uleb128 0x2 - 2769 00e3 06 .uleb128 0x6 - 2770 00e4 00 .byte 0 - 2771 00e5 00 .byte 0 - 2772 00e6 11 .uleb128 0x11 - 2773 00e7 34 .uleb128 0x34 - 2774 00e8 00 .byte 0 - 2775 00e9 03 .uleb128 0x3 - 2776 00ea 0E .uleb128 0xe - 2777 00eb 3A .uleb128 0x3a - 2778 00ec 0B .uleb128 0xb - 2779 00ed 3B .uleb128 0x3b - 2780 00ee 05 .uleb128 0x5 - 2781 00ef 49 .uleb128 0x49 - 2782 00f0 13 .uleb128 0x13 - 2783 00f1 02 .uleb128 0x2 - 2784 00f2 06 .uleb128 0x6 - 2785 00f3 00 .byte 0 - 2786 00f4 00 .byte 0 - 2787 00f5 12 .uleb128 0x12 - 2788 00f6 898201 .uleb128 0x4109 - 2789 00f9 00 .byte 0 - 2790 00fa 11 .uleb128 0x11 - 2791 00fb 01 .uleb128 0x1 - 2792 00fc 31 .uleb128 0x31 - 2793 00fd 13 .uleb128 0x13 - 2794 00fe 00 .byte 0 - 2795 00ff 00 .byte 0 - 2796 0100 13 .uleb128 0x13 - 2797 0101 2E .uleb128 0x2e - 2798 0102 00 .byte 0 - 2799 0103 31 .uleb128 0x31 - 2800 0104 13 .uleb128 0x13 - 2801 0105 11 .uleb128 0x11 - 2802 0106 01 .uleb128 0x1 - 2803 0107 12 .uleb128 0x12 - 2804 0108 01 .uleb128 0x1 - 2805 0109 40 .uleb128 0x40 - 2806 010a 0A .uleb128 0xa - 2807 010b 9742 .uleb128 0x2117 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 74 - - - 2808 010d 0C .uleb128 0xc - 2809 010e 00 .byte 0 - 2810 010f 00 .byte 0 - 2811 0110 14 .uleb128 0x14 - 2812 0111 2E .uleb128 0x2e - 2813 0112 01 .byte 0x1 - 2814 0113 3F .uleb128 0x3f - 2815 0114 0C .uleb128 0xc - 2816 0115 03 .uleb128 0x3 - 2817 0116 0E .uleb128 0xe - 2818 0117 3A .uleb128 0x3a - 2819 0118 0B .uleb128 0xb - 2820 0119 3B .uleb128 0x3b - 2821 011a 05 .uleb128 0x5 - 2822 011b 27 .uleb128 0x27 - 2823 011c 0C .uleb128 0xc - 2824 011d 49 .uleb128 0x49 - 2825 011e 13 .uleb128 0x13 - 2826 011f 11 .uleb128 0x11 - 2827 0120 01 .uleb128 0x1 - 2828 0121 12 .uleb128 0x12 - 2829 0122 01 .uleb128 0x1 - 2830 0123 40 .uleb128 0x40 - 2831 0124 06 .uleb128 0x6 - 2832 0125 9742 .uleb128 0x2117 - 2833 0127 0C .uleb128 0xc - 2834 0128 01 .uleb128 0x1 - 2835 0129 13 .uleb128 0x13 - 2836 012a 00 .byte 0 - 2837 012b 00 .byte 0 - 2838 012c 15 .uleb128 0x15 - 2839 012d 05 .uleb128 0x5 - 2840 012e 00 .byte 0 - 2841 012f 03 .uleb128 0x3 - 2842 0130 0E .uleb128 0xe - 2843 0131 3A .uleb128 0x3a - 2844 0132 0B .uleb128 0xb - 2845 0133 3B .uleb128 0x3b - 2846 0134 05 .uleb128 0x5 - 2847 0135 49 .uleb128 0x49 - 2848 0136 13 .uleb128 0x13 - 2849 0137 02 .uleb128 0x2 - 2850 0138 06 .uleb128 0x6 - 2851 0139 00 .byte 0 - 2852 013a 00 .byte 0 - 2853 013b 16 .uleb128 0x16 - 2854 013c 898201 .uleb128 0x4109 - 2855 013f 01 .byte 0x1 - 2856 0140 11 .uleb128 0x11 - 2857 0141 01 .uleb128 0x1 - 2858 0142 31 .uleb128 0x31 - 2859 0143 13 .uleb128 0x13 - 2860 0144 01 .uleb128 0x1 - 2861 0145 13 .uleb128 0x13 - 2862 0146 00 .byte 0 - 2863 0147 00 .byte 0 - 2864 0148 17 .uleb128 0x17 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 75 - - - 2865 0149 8A8201 .uleb128 0x410a - 2866 014c 00 .byte 0 - 2867 014d 02 .uleb128 0x2 - 2868 014e 0A .uleb128 0xa - 2869 014f 9142 .uleb128 0x2111 - 2870 0151 0A .uleb128 0xa - 2871 0152 00 .byte 0 - 2872 0153 00 .byte 0 - 2873 0154 18 .uleb128 0x18 - 2874 0155 898201 .uleb128 0x4109 - 2875 0158 00 .byte 0 - 2876 0159 11 .uleb128 0x11 - 2877 015a 01 .uleb128 0x1 - 2878 015b 9542 .uleb128 0x2115 - 2879 015d 0C .uleb128 0xc - 2880 015e 31 .uleb128 0x31 - 2881 015f 13 .uleb128 0x13 - 2882 0160 00 .byte 0 - 2883 0161 00 .byte 0 - 2884 0162 19 .uleb128 0x19 - 2885 0163 2E .uleb128 0x2e - 2886 0164 01 .byte 0x1 - 2887 0165 3F .uleb128 0x3f - 2888 0166 0C .uleb128 0xc - 2889 0167 03 .uleb128 0x3 - 2890 0168 0E .uleb128 0xe - 2891 0169 3A .uleb128 0x3a - 2892 016a 0B .uleb128 0xb - 2893 016b 3B .uleb128 0x3b - 2894 016c 05 .uleb128 0x5 - 2895 016d 27 .uleb128 0x27 - 2896 016e 0C .uleb128 0xc - 2897 016f 11 .uleb128 0x11 - 2898 0170 01 .uleb128 0x1 - 2899 0171 12 .uleb128 0x12 - 2900 0172 01 .uleb128 0x1 - 2901 0173 40 .uleb128 0x40 - 2902 0174 0A .uleb128 0xa - 2903 0175 9742 .uleb128 0x2117 - 2904 0177 0C .uleb128 0xc - 2905 0178 01 .uleb128 0x1 - 2906 0179 13 .uleb128 0x13 - 2907 017a 00 .byte 0 - 2908 017b 00 .byte 0 - 2909 017c 1A .uleb128 0x1a - 2910 017d 34 .uleb128 0x34 - 2911 017e 00 .byte 0 - 2912 017f 03 .uleb128 0x3 - 2913 0180 0E .uleb128 0xe - 2914 0181 3A .uleb128 0x3a - 2915 0182 0B .uleb128 0xb - 2916 0183 3B .uleb128 0x3b - 2917 0184 05 .uleb128 0x5 - 2918 0185 49 .uleb128 0x49 - 2919 0186 13 .uleb128 0x13 - 2920 0187 1C .uleb128 0x1c - 2921 0188 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 76 - - - 2922 0189 00 .byte 0 - 2923 018a 00 .byte 0 - 2924 018b 1B .uleb128 0x1b - 2925 018c 34 .uleb128 0x34 - 2926 018d 00 .byte 0 - 2927 018e 03 .uleb128 0x3 - 2928 018f 0E .uleb128 0xe - 2929 0190 3A .uleb128 0x3a - 2930 0191 0B .uleb128 0xb - 2931 0192 3B .uleb128 0x3b - 2932 0193 05 .uleb128 0x5 - 2933 0194 49 .uleb128 0x49 - 2934 0195 13 .uleb128 0x13 - 2935 0196 02 .uleb128 0x2 - 2936 0197 0A .uleb128 0xa - 2937 0198 00 .byte 0 - 2938 0199 00 .byte 0 - 2939 019a 1C .uleb128 0x1c - 2940 019b 2E .uleb128 0x2e - 2941 019c 01 .byte 0x1 - 2942 019d 3F .uleb128 0x3f - 2943 019e 0C .uleb128 0xc - 2944 019f 03 .uleb128 0x3 - 2945 01a0 0E .uleb128 0xe - 2946 01a1 3A .uleb128 0x3a - 2947 01a2 0B .uleb128 0xb - 2948 01a3 3B .uleb128 0x3b - 2949 01a4 0B .uleb128 0xb - 2950 01a5 27 .uleb128 0x27 - 2951 01a6 0C .uleb128 0xc - 2952 01a7 49 .uleb128 0x49 - 2953 01a8 13 .uleb128 0x13 - 2954 01a9 11 .uleb128 0x11 - 2955 01aa 01 .uleb128 0x1 - 2956 01ab 12 .uleb128 0x12 - 2957 01ac 01 .uleb128 0x1 - 2958 01ad 40 .uleb128 0x40 - 2959 01ae 06 .uleb128 0x6 - 2960 01af 9742 .uleb128 0x2117 - 2961 01b1 0C .uleb128 0xc - 2962 01b2 01 .uleb128 0x1 - 2963 01b3 13 .uleb128 0x13 - 2964 01b4 00 .byte 0 - 2965 01b5 00 .byte 0 - 2966 01b6 1D .uleb128 0x1d - 2967 01b7 34 .uleb128 0x34 - 2968 01b8 00 .byte 0 - 2969 01b9 03 .uleb128 0x3 - 2970 01ba 0E .uleb128 0xe - 2971 01bb 3A .uleb128 0x3a - 2972 01bc 0B .uleb128 0xb - 2973 01bd 3B .uleb128 0x3b - 2974 01be 0B .uleb128 0xb - 2975 01bf 49 .uleb128 0x49 - 2976 01c0 13 .uleb128 0x13 - 2977 01c1 02 .uleb128 0x2 - 2978 01c2 06 .uleb128 0x6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 77 - - - 2979 01c3 00 .byte 0 - 2980 01c4 00 .byte 0 - 2981 01c5 1E .uleb128 0x1e - 2982 01c6 34 .uleb128 0x34 - 2983 01c7 00 .byte 0 - 2984 01c8 03 .uleb128 0x3 - 2985 01c9 0E .uleb128 0xe - 2986 01ca 3A .uleb128 0x3a - 2987 01cb 0B .uleb128 0xb - 2988 01cc 3B .uleb128 0x3b - 2989 01cd 0B .uleb128 0xb - 2990 01ce 49 .uleb128 0x49 - 2991 01cf 13 .uleb128 0x13 - 2992 01d0 02 .uleb128 0x2 - 2993 01d1 0A .uleb128 0xa - 2994 01d2 00 .byte 0 - 2995 01d3 00 .byte 0 - 2996 01d4 1F .uleb128 0x1f - 2997 01d5 1D .uleb128 0x1d - 2998 01d6 00 .byte 0 - 2999 01d7 31 .uleb128 0x31 - 3000 01d8 13 .uleb128 0x13 - 3001 01d9 11 .uleb128 0x11 - 3002 01da 01 .uleb128 0x1 - 3003 01db 12 .uleb128 0x12 - 3004 01dc 01 .uleb128 0x1 - 3005 01dd 58 .uleb128 0x58 - 3006 01de 0B .uleb128 0xb - 3007 01df 59 .uleb128 0x59 - 3008 01e0 0B .uleb128 0xb - 3009 01e1 00 .byte 0 - 3010 01e2 00 .byte 0 - 3011 01e3 20 .uleb128 0x20 - 3012 01e4 01 .uleb128 0x1 - 3013 01e5 01 .byte 0x1 - 3014 01e6 49 .uleb128 0x49 - 3015 01e7 13 .uleb128 0x13 - 3016 01e8 01 .uleb128 0x1 - 3017 01e9 13 .uleb128 0x13 - 3018 01ea 00 .byte 0 - 3019 01eb 00 .byte 0 - 3020 01ec 21 .uleb128 0x21 - 3021 01ed 21 .uleb128 0x21 - 3022 01ee 00 .byte 0 - 3023 01ef 49 .uleb128 0x49 - 3024 01f0 13 .uleb128 0x13 - 3025 01f1 2F .uleb128 0x2f - 3026 01f2 0B .uleb128 0xb - 3027 01f3 00 .byte 0 - 3028 01f4 00 .byte 0 - 3029 01f5 22 .uleb128 0x22 - 3030 01f6 34 .uleb128 0x34 - 3031 01f7 00 .byte 0 - 3032 01f8 03 .uleb128 0x3 - 3033 01f9 0E .uleb128 0xe - 3034 01fa 3A .uleb128 0x3a - 3035 01fb 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 78 - - - 3036 01fc 3B .uleb128 0x3b - 3037 01fd 05 .uleb128 0x5 - 3038 01fe 49 .uleb128 0x49 - 3039 01ff 13 .uleb128 0x13 - 3040 0200 3F .uleb128 0x3f - 3041 0201 0C .uleb128 0xc - 3042 0202 3C .uleb128 0x3c - 3043 0203 0C .uleb128 0xc - 3044 0204 00 .byte 0 - 3045 0205 00 .byte 0 - 3046 0206 23 .uleb128 0x23 - 3047 0207 34 .uleb128 0x34 - 3048 0208 00 .byte 0 - 3049 0209 03 .uleb128 0x3 - 3050 020a 0E .uleb128 0xe - 3051 020b 3A .uleb128 0x3a - 3052 020c 0B .uleb128 0xb - 3053 020d 3B .uleb128 0x3b - 3054 020e 0B .uleb128 0xb - 3055 020f 49 .uleb128 0x49 - 3056 0210 13 .uleb128 0x13 - 3057 0211 3F .uleb128 0x3f - 3058 0212 0C .uleb128 0xc - 3059 0213 3C .uleb128 0x3c - 3060 0214 0C .uleb128 0xc - 3061 0215 00 .byte 0 - 3062 0216 00 .byte 0 - 3063 0217 24 .uleb128 0x24 - 3064 0218 2E .uleb128 0x2e - 3065 0219 00 .byte 0 - 3066 021a 3F .uleb128 0x3f - 3067 021b 0C .uleb128 0xc - 3068 021c 03 .uleb128 0x3 - 3069 021d 0E .uleb128 0xe - 3070 021e 3A .uleb128 0x3a - 3071 021f 0B .uleb128 0xb - 3072 0220 3B .uleb128 0x3b - 3073 0221 0B .uleb128 0xb - 3074 0222 27 .uleb128 0x27 - 3075 0223 0C .uleb128 0xc - 3076 0224 49 .uleb128 0x49 - 3077 0225 13 .uleb128 0x13 - 3078 0226 3C .uleb128 0x3c - 3079 0227 0C .uleb128 0xc - 3080 0228 00 .byte 0 - 3081 0229 00 .byte 0 - 3082 022a 00 .byte 0 - 3083 .section .debug_loc,"",%progbits - 3084 .Ldebug_loc0: - 3085 .LLST0: - 3086 0000 00000000 .4byte .LFB1 - 3087 0004 02000000 .4byte .LCFI0 - 3088 0008 0200 .2byte 0x2 - 3089 000a 7D .byte 0x7d - 3090 000b 00 .sleb128 0 - 3091 000c 02000000 .4byte .LCFI0 - 3092 0010 B4000000 .4byte .LFE1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 79 - - - 3093 0014 0200 .2byte 0x2 - 3094 0016 7D .byte 0x7d - 3095 0017 0C .sleb128 12 - 3096 0018 00000000 .4byte 0 - 3097 001c 00000000 .4byte 0 - 3098 .LLST1: - 3099 0020 00000000 .4byte .LVL0 - 3100 0024 04000000 .4byte .LVL1 - 3101 0028 0200 .2byte 0x2 - 3102 002a 31 .byte 0x31 - 3103 002b 9F .byte 0x9f - 3104 002c 0E000000 .4byte .LVL2 - 3105 0030 48000000 .4byte .LVL4 - 3106 0034 0100 .2byte 0x1 - 3107 0036 52 .byte 0x52 - 3108 0037 48000000 .4byte .LVL4 - 3109 003b 7C000000 .4byte .LVL5 - 3110 003f 0300 .2byte 0x3 - 3111 0041 72 .byte 0x72 - 3112 0042 7F .sleb128 -1 - 3113 0043 9F .byte 0x9f - 3114 0044 7C000000 .4byte .LVL5 - 3115 0048 8C000000 .4byte .LVL7 - 3116 004c 0100 .2byte 0x1 - 3117 004e 52 .byte 0x52 - 3118 004f 00000000 .4byte 0 - 3119 0053 00000000 .4byte 0 - 3120 .LLST2: - 3121 0057 00000000 .4byte .LVL0 - 3122 005b 04000000 .4byte .LVL1 - 3123 005f 0200 .2byte 0x2 - 3124 0061 30 .byte 0x30 - 3125 0062 9F .byte 0x9f - 3126 0063 0E000000 .4byte .LVL2 - 3127 0067 18000000 .4byte .LVL3 - 3128 006b 0100 .2byte 0x1 - 3129 006d 50 .byte 0x50 - 3130 006e 18000000 .4byte .LVL3 - 3131 0072 7C000000 .4byte .LVL5 - 3132 0076 0100 .2byte 0x1 - 3133 0078 53 .byte 0x53 - 3134 0079 88000000 .4byte .LVL6 - 3135 007d B4000000 .4byte .LFE1 - 3136 0081 0100 .2byte 0x1 - 3137 0083 50 .byte 0x50 - 3138 0084 00000000 .4byte 0 - 3139 0088 00000000 .4byte 0 - 3140 .LLST3: - 3141 008c 00000000 .4byte .LVL8 - 3142 0090 10000000 .4byte .LVL11 - 3143 0094 0100 .2byte 0x1 - 3144 0096 50 .byte 0x50 - 3145 0097 10000000 .4byte .LVL11 - 3146 009b 1C000000 .4byte .LFE4 - 3147 009f 0400 .2byte 0x4 - 3148 00a1 F3 .byte 0xf3 - 3149 00a2 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 80 - - - 3150 00a3 50 .byte 0x50 - 3151 00a4 9F .byte 0x9f - 3152 00a5 00000000 .4byte 0 - 3153 00a9 00000000 .4byte 0 - 3154 .LLST4: - 3155 00ad 06000000 .4byte .LVL9 - 3156 00b1 0C000000 .4byte .LVL10 - 3157 00b5 0700 .2byte 0x7 - 3158 00b7 72 .byte 0x72 - 3159 00b8 00 .sleb128 0 - 3160 00b9 08 .byte 0x8 - 3161 00ba FF .byte 0xff - 3162 00bb 1A .byte 0x1a - 3163 00bc 33 .byte 0x33 - 3164 00bd 24 .byte 0x24 - 3165 00be 00000000 .4byte 0 - 3166 00c2 00000000 .4byte 0 - 3167 .LLST5: - 3168 00c6 00000000 .4byte .LFB3 - 3169 00ca 02000000 .4byte .LCFI1 - 3170 00ce 0200 .2byte 0x2 - 3171 00d0 7D .byte 0x7d - 3172 00d1 00 .sleb128 0 - 3173 00d2 02000000 .4byte .LCFI1 - 3174 00d6 28010000 .4byte .LFE3 - 3175 00da 0200 .2byte 0x2 - 3176 00dc 7D .byte 0x7d - 3177 00dd 18 .sleb128 24 - 3178 00de 00000000 .4byte 0 - 3179 00e2 00000000 .4byte 0 - 3180 .LLST6: - 3181 00e6 18000000 .4byte .LVL13 - 3182 00ea 1C000000 .4byte .LVL15 - 3183 00ee 0200 .2byte 0x2 - 3184 00f0 70 .byte 0x70 - 3185 00f1 08 .sleb128 8 - 3186 00f2 1C000000 .4byte .LVL15 - 3187 00f6 F4000000 .4byte .LVL28 - 3188 00fa 0100 .2byte 0x1 - 3189 00fc 55 .byte 0x55 - 3190 00fd 00000000 .4byte 0 - 3191 0101 00000000 .4byte 0 - 3192 .LLST7: - 3193 0105 4A000000 .4byte .LVL16 - 3194 0109 98000000 .4byte .LVL23 - 3195 010d 0100 .2byte 0x1 - 3196 010f 52 .byte 0x52 - 3197 0110 98000000 .4byte .LVL23 - 3198 0114 EC000000 .4byte .LVL25 - 3199 0118 0800 .2byte 0x8 - 3200 011a 73 .byte 0x73 - 3201 011b 7A .sleb128 -6 - 3202 011c 94 .byte 0x94 - 3203 011d 01 .byte 0x1 - 3204 011e 08 .byte 0x8 - 3205 011f 7F .byte 0x7f - 3206 0120 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 81 - - - 3207 0121 9F .byte 0x9f - 3208 0122 00000000 .4byte 0 - 3209 0126 00000000 .4byte 0 - 3210 .LLST8: - 3211 012a 18000000 .4byte .LVL13 - 3212 012e 1C000000 .4byte .LVL15 - 3213 0132 0200 .2byte 0x2 - 3214 0134 30 .byte 0x30 - 3215 0135 9F .byte 0x9f - 3216 0136 1C000000 .4byte .LVL15 - 3217 013a EE000000 .4byte .LVL26 - 3218 013e 0100 .2byte 0x1 - 3219 0140 50 .byte 0x50 - 3220 0141 EE000000 .4byte .LVL26 - 3221 0145 F0000000 .4byte .LVL27 - 3222 0149 0300 .2byte 0x3 - 3223 014b 70 .byte 0x70 - 3224 014c 7F .sleb128 -1 - 3225 014d 9F .byte 0x9f - 3226 014e F0000000 .4byte .LVL27 - 3227 0152 F4000000 .4byte .LVL28 - 3228 0156 0100 .2byte 0x1 - 3229 0158 50 .byte 0x50 - 3230 0159 00000000 .4byte 0 - 3231 015d 00000000 .4byte 0 - 3232 .LLST9: - 3233 0161 62000000 .4byte .LVL19 - 3234 0165 74000000 .4byte .LVL20 - 3235 0169 0100 .2byte 0x1 - 3236 016b 56 .byte 0x56 - 3237 016c 74000000 .4byte .LVL20 - 3238 0170 76000000 .4byte .LVL21 - 3239 0174 0700 .2byte 0x7 - 3240 0176 73 .byte 0x73 - 3241 0177 7B .sleb128 -5 - 3242 0178 94 .byte 0x94 - 3243 0179 01 .byte 0x1 - 3244 017a 33 .byte 0x33 - 3245 017b 1A .byte 0x1a - 3246 017c 9F .byte 0x9f - 3247 017d 76000000 .4byte .LVL21 - 3248 0181 82000000 .4byte .LVL22 - 3249 0185 0100 .2byte 0x1 - 3250 0187 56 .byte 0x56 - 3251 0188 82000000 .4byte .LVL22 - 3252 018c EC000000 .4byte .LVL25 - 3253 0190 0700 .2byte 0x7 - 3254 0192 73 .byte 0x73 - 3255 0193 7B .sleb128 -5 - 3256 0194 94 .byte 0x94 - 3257 0195 01 .byte 0x1 - 3258 0196 33 .byte 0x33 - 3259 0197 1A .byte 0x1a - 3260 0198 9F .byte 0x9f - 3261 0199 00000000 .4byte 0 - 3262 019d 00000000 .4byte 0 - 3263 .LLST10: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 82 - - - 3264 01a1 50000000 .4byte .LVL17 - 3265 01a5 56000000 .4byte .LVL18 - 3266 01a9 0100 .2byte 0x1 - 3267 01ab 54 .byte 0x54 - 3268 01ac 56000000 .4byte .LVL18 - 3269 01b0 E6000000 .4byte .LVL24 - 3270 01b4 0100 .2byte 0x1 - 3271 01b6 51 .byte 0x51 - 3272 01b7 E6000000 .4byte .LVL24 - 3273 01bb EC000000 .4byte .LVL25 - 3274 01bf 0700 .2byte 0x7 - 3275 01c1 74 .byte 0x74 - 3276 01c2 FBBEFEFF .sleb128 -1073766533 - 3276 7B - 3277 01c7 9F .byte 0x9f - 3278 01c8 00000000 .4byte 0 - 3279 01cc 00000000 .4byte 0 - 3280 .LLST11: - 3281 01d0 14000000 .4byte .LVL12 - 3282 01d4 1C000000 .4byte .LVL15 - 3283 01d8 0300 .2byte 0x3 - 3284 01da 70 .byte 0x70 - 3285 01db 08 .sleb128 8 - 3286 01dc 9F .byte 0x9f - 3287 01dd 00000000 .4byte 0 - 3288 01e1 00000000 .4byte 0 - 3289 .LLST12: - 3290 01e5 18000000 .4byte .LVL13 - 3291 01e9 1A000000 .4byte .LVL14 - 3292 01ed 0100 .2byte 0x1 - 3293 01ef 53 .byte 0x53 - 3294 01f0 1A000000 .4byte .LVL14 - 3295 01f4 1C000000 .4byte .LVL15 - 3296 01f8 0200 .2byte 0x2 - 3297 01fa 70 .byte 0x70 - 3298 01fb 0C .sleb128 12 - 3299 01fc 00000000 .4byte 0 - 3300 0200 00000000 .4byte 0 - 3301 .LLST13: - 3302 0204 00000000 .4byte .LFB6 - 3303 0208 02000000 .4byte .LCFI2 - 3304 020c 0200 .2byte 0x2 - 3305 020e 7D .byte 0x7d - 3306 020f 00 .sleb128 0 - 3307 0210 02000000 .4byte .LCFI2 - 3308 0214 20000000 .4byte .LFE6 - 3309 0218 0200 .2byte 0x2 - 3310 021a 7D .byte 0x7d - 3311 021b 08 .sleb128 8 - 3312 021c 00000000 .4byte 0 - 3313 0220 00000000 .4byte 0 - 3314 .LLST14: - 3315 0224 0E000000 .4byte .LVL29 - 3316 0228 12000000 .4byte .LVL30 - 3317 022c 0100 .2byte 0x1 - 3318 022e 50 .byte 0x50 - 3319 022f 12000000 .4byte .LVL30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 83 - - - 3320 0233 16000000 .4byte .LVL31 - 3321 0237 0800 .2byte 0x8 - 3322 0239 73 .byte 0x73 - 3323 023a 02 .sleb128 2 - 3324 023b 33 .byte 0x33 - 3325 023c 24 .byte 0x24 - 3326 023d 70 .byte 0x70 - 3327 023e 00 .sleb128 0 - 3328 023f 22 .byte 0x22 - 3329 0240 9F .byte 0x9f - 3330 0241 00000000 .4byte 0 - 3331 0245 00000000 .4byte 0 - 3332 .LLST15: - 3333 0249 0E000000 .4byte .LVL29 - 3334 024d 16000000 .4byte .LVL31 - 3335 0251 0500 .2byte 0x5 - 3336 0253 70 .byte 0x70 - 3337 0254 04 .sleb128 4 - 3338 0255 06 .byte 0x6 - 3339 0256 23 .byte 0x23 - 3340 0257 04 .uleb128 0x4 - 3341 0258 16000000 .4byte .LVL31 - 3342 025c 20000000 .4byte .LFE6 - 3343 0260 0200 .2byte 0x2 - 3344 0262 72 .byte 0x72 - 3345 0263 04 .sleb128 4 - 3346 0264 00000000 .4byte 0 - 3347 0268 00000000 .4byte 0 - 3348 .LLST16: - 3349 026c 00000000 .4byte .LFB2 - 3350 0270 02000000 .4byte .LCFI3 - 3351 0274 0200 .2byte 0x2 - 3352 0276 7D .byte 0x7d - 3353 0277 00 .sleb128 0 - 3354 0278 02000000 .4byte .LCFI3 - 3355 027c 68010000 .4byte .LFE2 - 3356 0280 0200 .2byte 0x2 - 3357 0282 7D .byte 0x7d - 3358 0283 18 .sleb128 24 - 3359 0284 00000000 .4byte 0 - 3360 0288 00000000 .4byte 0 - 3361 .LLST17: - 3362 028c 00000000 .4byte .LVL32 - 3363 0290 2A000000 .4byte .LVL34 - 3364 0294 0100 .2byte 0x1 - 3365 0296 50 .byte 0x50 - 3366 0297 2A000000 .4byte .LVL34 - 3367 029b 68010000 .4byte .LFE2 - 3368 029f 0400 .2byte 0x4 - 3369 02a1 F3 .byte 0xf3 - 3370 02a2 01 .uleb128 0x1 - 3371 02a3 50 .byte 0x50 - 3372 02a4 9F .byte 0x9f - 3373 02a5 00000000 .4byte 0 - 3374 02a9 00000000 .4byte 0 - 3375 .LLST18: - 3376 02ad 00000000 .4byte .LVL32 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 84 - - - 3377 02b1 04000000 .4byte .LVL33 - 3378 02b5 0200 .2byte 0x2 - 3379 02b7 30 .byte 0x30 - 3380 02b8 9F .byte 0x9f - 3381 02b9 64000000 .4byte .LVL39 - 3382 02bd 02010000 .4byte .LVL51 - 3383 02c1 0200 .2byte 0x2 - 3384 02c3 70 .byte 0x70 - 3385 02c4 08 .sleb128 8 - 3386 02c5 02010000 .4byte .LVL51 - 3387 02c9 2E010000 .4byte .LVL55 - 3388 02cd 0100 .2byte 0x1 - 3389 02cf 54 .byte 0x54 - 3390 02d0 2E010000 .4byte .LVL55 - 3391 02d4 30010000 .4byte .LVL56 - 3392 02d8 0200 .2byte 0x2 - 3393 02da 31 .byte 0x31 - 3394 02db 9F .byte 0x9f - 3395 02dc 00000000 .4byte 0 - 3396 02e0 00000000 .4byte 0 - 3397 .LLST19: - 3398 02e4 66000000 .4byte .LVL40 - 3399 02e8 6C000000 .4byte .LVL42 - 3400 02ec 0200 .2byte 0x2 - 3401 02ee 30 .byte 0x30 - 3402 02ef 9F .byte 0x9f - 3403 02f0 6C000000 .4byte .LVL42 - 3404 02f4 F2000000 .4byte .LVL48 - 3405 02f8 0100 .2byte 0x1 - 3406 02fa 51 .byte 0x51 - 3407 02fb F2000000 .4byte .LVL48 - 3408 02ff F4000000 .4byte .LVL49 - 3409 0303 0300 .2byte 0x3 - 3410 0305 71 .byte 0x71 - 3411 0306 7F .sleb128 -1 - 3412 0307 9F .byte 0x9f - 3413 0308 F4000000 .4byte .LVL49 - 3414 030c 02010000 .4byte .LVL51 - 3415 0310 0100 .2byte 0x1 - 3416 0312 51 .byte 0x51 - 3417 0313 00000000 .4byte 0 - 3418 0317 00000000 .4byte 0 - 3419 .LLST20: - 3420 031b 64000000 .4byte .LVL39 - 3421 031f 66000000 .4byte .LVL40 - 3422 0323 0200 .2byte 0x2 - 3423 0325 31 .byte 0x31 - 3424 0326 9F .byte 0x9f - 3425 0327 FE000000 .4byte .LVL50 - 3426 032b 02010000 .4byte .LVL51 - 3427 032f 0200 .2byte 0x2 - 3428 0331 30 .byte 0x30 - 3429 0332 9F .byte 0x9f - 3430 0333 02010000 .4byte .LVL51 - 3431 0337 1E010000 .4byte .LVL52 - 3432 033b 0100 .2byte 0x1 - 3433 033d 52 .byte 0x52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 85 - - - 3434 033e 1E010000 .4byte .LVL52 - 3435 0342 22010000 .4byte .LVL53 - 3436 0346 0300 .2byte 0x3 - 3437 0348 72 .byte 0x72 - 3438 0349 7F .sleb128 -1 - 3439 034a 9F .byte 0x9f - 3440 034b 22010000 .4byte .LVL53 - 3441 034f 27010000 .4byte .LVL54-1 - 3442 0353 0100 .2byte 0x1 - 3443 0355 52 .byte 0x52 - 3444 0356 00000000 .4byte 0 - 3445 035a 00000000 .4byte 0 - 3446 .LLST21: - 3447 035e B8000000 .4byte .LVL43 - 3448 0362 CA000000 .4byte .LVL44 - 3449 0366 0100 .2byte 0x1 - 3450 0368 56 .byte 0x56 - 3451 0369 CA000000 .4byte .LVL44 - 3452 036d CC000000 .4byte .LVL45 - 3453 0371 0700 .2byte 0x7 - 3454 0373 73 .byte 0x73 - 3455 0374 7B .sleb128 -5 - 3456 0375 94 .byte 0x94 - 3457 0376 01 .byte 0x1 - 3458 0377 33 .byte 0x33 - 3459 0378 1A .byte 0x1a - 3460 0379 9F .byte 0x9f - 3461 037a CC000000 .4byte .LVL45 - 3462 037e D8000000 .4byte .LVL46 - 3463 0382 0100 .2byte 0x1 - 3464 0384 56 .byte 0x56 - 3465 0385 D8000000 .4byte .LVL46 - 3466 0389 F0000000 .4byte .LVL47 - 3467 038d 0700 .2byte 0x7 - 3468 038f 73 .byte 0x73 - 3469 0390 7B .sleb128 -5 - 3470 0391 94 .byte 0x94 - 3471 0392 01 .byte 0x1 - 3472 0393 33 .byte 0x33 - 3473 0394 1A .byte 0x1a - 3474 0395 9F .byte 0x9f - 3475 0396 00000000 .4byte 0 - 3476 039a 00000000 .4byte 0 - 3477 .LLST22: - 3478 039e 44000000 .4byte .LVL36 - 3479 03a2 02010000 .4byte .LVL51 - 3480 03a6 0200 .2byte 0x2 - 3481 03a8 70 .byte 0x70 - 3482 03a9 04 .sleb128 4 - 3483 03aa 00000000 .4byte 0 - 3484 03ae 00000000 .4byte 0 - 3485 .LLST23: - 3486 03b2 00000000 .4byte .LVL32 - 3487 03b6 30010000 .4byte .LVL56 - 3488 03ba 0200 .2byte 0x2 - 3489 03bc 30 .byte 0x30 - 3490 03bd 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 86 - - - 3491 03be 44010000 .4byte .LVL57 - 3492 03c2 4D010000 .4byte .LVL58-1 - 3493 03c6 0100 .2byte 0x1 - 3494 03c8 52 .byte 0x52 - 3495 03c9 4E010000 .4byte .LVL58 - 3496 03cd 68010000 .4byte .LFE2 - 3497 03d1 0200 .2byte 0x2 - 3498 03d3 30 .byte 0x30 - 3499 03d4 9F .byte 0x9f - 3500 03d5 00000000 .4byte 0 - 3501 03d9 00000000 .4byte 0 - 3502 .LLST24: - 3503 03dd 44000000 .4byte .LVL36 - 3504 03e1 64000000 .4byte .LVL39 - 3505 03e5 0100 .2byte 0x1 - 3506 03e7 50 .byte 0x50 - 3507 03e8 64000000 .4byte .LVL39 - 3508 03ec 02010000 .4byte .LVL51 - 3509 03f0 0300 .2byte 0x3 - 3510 03f2 70 .byte 0x70 - 3511 03f3 08 .sleb128 8 - 3512 03f4 9F .byte 0x9f - 3513 03f5 00000000 .4byte 0 - 3514 03f9 00000000 .4byte 0 - 3515 .LLST25: - 3516 03fd 66000000 .4byte .LVL40 - 3517 0401 6C000000 .4byte .LVL42 - 3518 0405 0200 .2byte 0x2 - 3519 0407 70 .byte 0x70 - 3520 0408 0C .sleb128 12 - 3521 0409 FE000000 .4byte .LVL50 - 3522 040d 02010000 .4byte .LVL51 - 3523 0411 0200 .2byte 0x2 - 3524 0413 70 .byte 0x70 - 3525 0414 0C .sleb128 12 - 3526 0415 00000000 .4byte 0 - 3527 0419 00000000 .4byte 0 - 3528 .LLST26: - 3529 041d 00000000 .4byte .LVL59 - 3530 0421 04000000 .4byte .LVL60 - 3531 0425 0100 .2byte 0x1 - 3532 0427 50 .byte 0x50 - 3533 0428 04000000 .4byte .LVL60 - 3534 042c 18000000 .4byte .LVL63 - 3535 0430 0100 .2byte 0x1 - 3536 0432 50 .byte 0x50 - 3537 0433 00000000 .4byte 0 - 3538 0437 00000000 .4byte 0 - 3539 .LLST27: - 3540 043b 08000000 .4byte .LVL61 - 3541 043f 14000000 .4byte .LVL62 - 3542 0443 0500 .2byte 0x5 - 3543 0445 71 .byte 0x71 - 3544 0446 00 .sleb128 0 - 3545 0447 34 .byte 0x34 - 3546 0448 24 .byte 0x24 - 3547 0449 9F .byte 0x9f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 87 - - - 3548 044a 14000000 .4byte .LVL62 - 3549 044e 18000000 .4byte .LVL63 - 3550 0452 0500 .2byte 0x5 - 3551 0454 70 .byte 0x70 - 3552 0455 7F .sleb128 -1 - 3553 0456 34 .byte 0x34 - 3554 0457 24 .byte 0x24 - 3555 0458 9F .byte 0x9f - 3556 0459 00000000 .4byte 0 - 3557 045d 00000000 .4byte 0 - 3558 .LLST28: - 3559 0461 08000000 .4byte .LVL65 - 3560 0465 1E000000 .4byte .LVL68 - 3561 0469 0100 .2byte 0x1 - 3562 046b 51 .byte 0x51 - 3563 046c 46000000 .4byte .LVL69 - 3564 0470 58000000 .4byte .LFE8 - 3565 0474 0100 .2byte 0x1 - 3566 0476 51 .byte 0x51 - 3567 0477 00000000 .4byte 0 - 3568 047b 00000000 .4byte 0 - 3569 .LLST29: - 3570 047f 0C000000 .4byte .LVL66 - 3571 0483 18000000 .4byte .LVL67 - 3572 0487 0500 .2byte 0x5 - 3573 0489 70 .byte 0x70 - 3574 048a 00 .sleb128 0 - 3575 048b 34 .byte 0x34 - 3576 048c 24 .byte 0x24 - 3577 048d 9F .byte 0x9f - 3578 048e 18000000 .4byte .LVL67 - 3579 0492 1E000000 .4byte .LVL68 - 3580 0496 0500 .2byte 0x5 - 3581 0498 71 .byte 0x71 - 3582 0499 7F .sleb128 -1 - 3583 049a 34 .byte 0x34 - 3584 049b 24 .byte 0x24 - 3585 049c 9F .byte 0x9f - 3586 049d 46000000 .4byte .LVL69 - 3587 04a1 48000000 .4byte .LVL70 - 3588 04a5 0500 .2byte 0x5 - 3589 04a7 70 .byte 0x70 - 3590 04a8 00 .sleb128 0 - 3591 04a9 34 .byte 0x34 - 3592 04aa 24 .byte 0x24 - 3593 04ab 9F .byte 0x9f - 3594 04ac 48000000 .4byte .LVL70 - 3595 04b0 58000000 .4byte .LFE8 - 3596 04b4 0500 .2byte 0x5 - 3597 04b6 72 .byte 0x72 - 3598 04b7 00 .sleb128 0 - 3599 04b8 34 .byte 0x34 - 3600 04b9 24 .byte 0x24 - 3601 04ba 9F .byte 0x9f - 3602 04bb 00000000 .4byte 0 - 3603 04bf 00000000 .4byte 0 - 3604 .LLST30: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 88 - - - 3605 04c3 00000000 .4byte .LFB9 - 3606 04c7 02000000 .4byte .LCFI4 - 3607 04cb 0200 .2byte 0x2 - 3608 04cd 7D .byte 0x7d - 3609 04ce 00 .sleb128 0 - 3610 04cf 02000000 .4byte .LCFI4 - 3611 04d3 7C000000 .4byte .LFE9 - 3612 04d7 0200 .2byte 0x2 - 3613 04d9 7D .byte 0x7d - 3614 04da 08 .sleb128 8 - 3615 04db 00000000 .4byte 0 - 3616 04df 00000000 .4byte 0 - 3617 .LLST31: - 3618 04e3 0A000000 .4byte .LVL72 - 3619 04e7 1A000000 .4byte .LVL74 - 3620 04eb 0100 .2byte 0x1 - 3621 04ed 53 .byte 0x53 - 3622 04ee 68000000 .4byte .LVL76 - 3623 04f2 7C000000 .4byte .LFE9 - 3624 04f6 0100 .2byte 0x1 - 3625 04f8 53 .byte 0x53 - 3626 04f9 00000000 .4byte 0 - 3627 04fd 00000000 .4byte 0 - 3628 .LLST32: - 3629 0501 0E000000 .4byte .LVL73 - 3630 0505 1E000000 .4byte .LVL75 - 3631 0509 0500 .2byte 0x5 - 3632 050b 72 .byte 0x72 - 3633 050c 00 .sleb128 0 - 3634 050d 34 .byte 0x34 - 3635 050e 24 .byte 0x24 - 3636 050f 9F .byte 0x9f - 3637 0510 68000000 .4byte .LVL76 - 3638 0514 7C000000 .4byte .LFE9 - 3639 0518 0500 .2byte 0x5 - 3640 051a 72 .byte 0x72 - 3641 051b 00 .sleb128 0 - 3642 051c 34 .byte 0x34 - 3643 051d 24 .byte 0x24 - 3644 051e 9F .byte 0x9f - 3645 051f 00000000 .4byte 0 - 3646 0523 00000000 .4byte 0 - 3647 .LLST33: - 3648 0527 00000000 .4byte .LFB10 - 3649 052b 02000000 .4byte .LCFI5 - 3650 052f 0200 .2byte 0x2 - 3651 0531 7D .byte 0x7d - 3652 0532 00 .sleb128 0 - 3653 0533 02000000 .4byte .LCFI5 - 3654 0537 48000000 .4byte .LFE10 - 3655 053b 0200 .2byte 0x2 - 3656 053d 7D .byte 0x7d - 3657 053e 08 .sleb128 8 - 3658 053f 00000000 .4byte 0 - 3659 0543 00000000 .4byte 0 - 3660 .LLST34: - 3661 0547 00000000 .4byte .LVL77 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 89 - - - 3662 054b 30000000 .4byte .LVL84 - 3663 054f 0200 .2byte 0x2 - 3664 0551 31 .byte 0x31 - 3665 0552 9F .byte 0x9f - 3666 0553 30000000 .4byte .LVL84 - 3667 0557 48000000 .4byte .LFE10 - 3668 055b 0100 .2byte 0x1 - 3669 055d 50 .byte 0x50 - 3670 055e 00000000 .4byte 0 - 3671 0562 00000000 .4byte 0 - 3672 .LLST35: - 3673 0566 12000000 .4byte .LVL79 - 3674 056a 16000000 .4byte .LVL80 - 3675 056e 0100 .2byte 0x1 - 3676 0570 50 .byte 0x50 - 3677 0571 00000000 .4byte 0 - 3678 0575 00000000 .4byte 0 - 3679 .LLST36: - 3680 0579 12000000 .4byte .LVL79 - 3681 057d 16000000 .4byte .LVL80 - 3682 0581 0500 .2byte 0x5 - 3683 0583 70 .byte 0x70 - 3684 0584 04 .sleb128 4 - 3685 0585 06 .byte 0x6 - 3686 0586 23 .byte 0x23 - 3687 0587 04 .uleb128 0x4 - 3688 0588 16000000 .4byte .LVL80 - 3689 058c 1E000000 .4byte .LVL81 - 3690 0590 0200 .2byte 0x2 - 3691 0592 73 .byte 0x73 - 3692 0593 04 .sleb128 4 - 3693 0594 1E000000 .4byte .LVL81 - 3694 0598 24000000 .4byte .LVL82 - 3695 059c 0100 .2byte 0x1 - 3696 059e 50 .byte 0x50 - 3697 059f 2E000000 .4byte .LVL83 - 3698 05a3 48000000 .4byte .LFE10 - 3699 05a7 0200 .2byte 0x2 - 3700 05a9 73 .byte 0x73 - 3701 05aa 04 .sleb128 4 - 3702 05ab 00000000 .4byte 0 - 3703 05af 00000000 .4byte 0 - 3704 .LLST37: - 3705 05b3 00000000 .4byte .LFB0 - 3706 05b7 02000000 .4byte .LCFI6 - 3707 05bb 0200 .2byte 0x2 - 3708 05bd 7D .byte 0x7d - 3709 05be 00 .sleb128 0 - 3710 05bf 02000000 .4byte .LCFI6 - 3711 05c3 74020000 .4byte .LFE0 - 3712 05c7 0200 .2byte 0x2 - 3713 05c9 7D .byte 0x7d - 3714 05ca 08 .sleb128 8 - 3715 05cb 00000000 .4byte 0 - 3716 05cf 00000000 .4byte 0 - 3717 .LLST38: - 3718 05d3 00000000 .4byte .LVL85 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 90 - - - 3719 05d7 62020000 .4byte .LVL111 - 3720 05db 0200 .2byte 0x2 - 3721 05dd 30 .byte 0x30 - 3722 05de 9F .byte 0x9f - 3723 05df 00000000 .4byte 0 - 3724 05e3 00000000 .4byte 0 - 3725 .LLST39: - 3726 05e7 78010000 .4byte .LVL102 - 3727 05eb 8E010000 .4byte .LVL104 - 3728 05ef 0100 .2byte 0x1 - 3729 05f1 54 .byte 0x54 - 3730 05f2 00000000 .4byte 0 - 3731 05f6 00000000 .4byte 0 - 3732 .LLST40: - 3733 05fa 00000000 .4byte .LVL85 - 3734 05fe 78000000 .4byte .LVL88 - 3735 0602 0200 .2byte 0x2 - 3736 0604 30 .byte 0x30 - 3737 0605 9F .byte 0x9f - 3738 0606 80000000 .4byte .LVL89 - 3739 060a 8A000000 .4byte .LVL90 - 3740 060e 0200 .2byte 0x2 - 3741 0610 30 .byte 0x30 - 3742 0611 9F .byte 0x9f - 3743 0612 8A000000 .4byte .LVL90 - 3744 0616 A6000000 .4byte .LVL92 - 3745 061a 0100 .2byte 0x1 - 3746 061c 53 .byte 0x53 - 3747 061d A8000000 .4byte .LVL93 - 3748 0621 CA000000 .4byte .LVL98 - 3749 0625 0100 .2byte 0x1 - 3750 0627 53 .byte 0x53 - 3751 0628 CA000000 .4byte .LVL98 - 3752 062c 62020000 .4byte .LVL111 - 3753 0630 0200 .2byte 0x2 - 3754 0632 30 .byte 0x30 - 3755 0633 9F .byte 0x9f - 3756 0634 00000000 .4byte 0 - 3757 0638 00000000 .4byte 0 - 3758 .LLST41: - 3759 063c 8A000000 .4byte .LVL90 - 3760 0640 94000000 .4byte .LVL91 - 3761 0644 0100 .2byte 0x1 - 3762 0646 52 .byte 0x52 - 3763 0647 A8000000 .4byte .LVL93 - 3764 064b B6000000 .4byte .LVL96 - 3765 064f 0100 .2byte 0x1 - 3766 0651 52 .byte 0x52 - 3767 0652 B6000000 .4byte .LVL96 - 3768 0656 B8000000 .4byte .LVL97 - 3769 065a 0100 .2byte 0x1 - 3770 065c 50 .byte 0x50 - 3771 065d 00000000 .4byte 0 - 3772 0661 00000000 .4byte 0 - 3773 .LLST42: - 3774 0665 B0000000 .4byte .LVL94 - 3775 0669 B8000000 .4byte .LVL97 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 91 - - - 3776 066d 0100 .2byte 0x1 - 3777 066f 51 .byte 0x51 - 3778 0670 00000000 .4byte 0 - 3779 0674 00000000 .4byte 0 - 3780 .LLST43: - 3781 0678 64000000 .4byte .LVL86 - 3782 067c 68000000 .4byte .LVL87 - 3783 0680 0100 .2byte 0x1 - 3784 0682 50 .byte 0x50 - 3785 0683 00000000 .4byte 0 - 3786 0687 00000000 .4byte 0 - 3787 .section .debug_aranges,"",%progbits - 3788 0000 6C000000 .4byte 0x6c - 3789 0004 0200 .2byte 0x2 - 3790 0006 00000000 .4byte .Ldebug_info0 - 3791 000a 04 .byte 0x4 - 3792 000b 00 .byte 0 - 3793 000c 0000 .2byte 0 - 3794 000e 0000 .2byte 0 - 3795 0010 00000000 .4byte .LFB1 - 3796 0014 B4000000 .4byte .LFE1-.LFB1 - 3797 0018 00000000 .4byte .LFB4 - 3798 001c 1C000000 .4byte .LFE4-.LFB4 - 3799 0020 00000000 .4byte .LFB3 - 3800 0024 28010000 .4byte .LFE3-.LFB3 - 3801 0028 00000000 .4byte .LFB5 - 3802 002c 18000000 .4byte .LFE5-.LFB5 - 3803 0030 00000000 .4byte .LFB6 - 3804 0034 20000000 .4byte .LFE6-.LFB6 - 3805 0038 00000000 .4byte .LFB2 - 3806 003c 68010000 .4byte .LFE2-.LFB2 - 3807 0040 00000000 .4byte .LFB7 - 3808 0044 40000000 .4byte .LFE7-.LFB7 - 3809 0048 00000000 .4byte .LFB8 - 3810 004c 58000000 .4byte .LFE8-.LFB8 - 3811 0050 00000000 .4byte .LFB9 - 3812 0054 7C000000 .4byte .LFE9-.LFB9 - 3813 0058 00000000 .4byte .LFB10 - 3814 005c 48000000 .4byte .LFE10-.LFB10 - 3815 0060 00000000 .4byte .LFB0 - 3816 0064 74020000 .4byte .LFE0-.LFB0 - 3817 0068 00000000 .4byte 0 - 3818 006c 00000000 .4byte 0 - 3819 .section .debug_ranges,"",%progbits - 3820 .Ldebug_ranges0: - 3821 0000 00000000 .4byte .LFB1 - 3822 0004 B4000000 .4byte .LFE1 - 3823 0008 00000000 .4byte .LFB4 - 3824 000c 1C000000 .4byte .LFE4 - 3825 0010 00000000 .4byte .LFB3 - 3826 0014 28010000 .4byte .LFE3 - 3827 0018 00000000 .4byte .LFB5 - 3828 001c 18000000 .4byte .LFE5 - 3829 0020 00000000 .4byte .LFB6 - 3830 0024 20000000 .4byte .LFE6 - 3831 0028 00000000 .4byte .LFB2 - 3832 002c 68010000 .4byte .LFE2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 92 - - - 3833 0030 00000000 .4byte .LFB7 - 3834 0034 40000000 .4byte .LFE7 - 3835 0038 00000000 .4byte .LFB8 - 3836 003c 58000000 .4byte .LFE8 - 3837 0040 00000000 .4byte .LFB9 - 3838 0044 7C000000 .4byte .LFE9 - 3839 0048 00000000 .4byte .LFB10 - 3840 004c 48000000 .4byte .LFE10 - 3841 0050 00000000 .4byte .LFB0 - 3842 0054 74020000 .4byte .LFE0 - 3843 0058 00000000 .4byte 0 - 3844 005c 00000000 .4byte 0 - 3845 .section .debug_line,"",%progbits - 3846 .Ldebug_line0: - 3847 0000 5C030000 .section .debug_str,"MS",%progbits,1 - 3847 02006200 - 3847 00000201 - 3847 FB0E0D00 - 3847 01010101 - 3848 .LASF35: - 3849 0000 70537461 .ascii "pStatusBlock\000" - 3849 74757342 - 3849 6C6F636B - 3849 00 - 3850 .LASF33: - 3851 000d 636F756E .ascii "count\000" - 3851 7400 - 3852 .LASF10: - 3853 0013 75696E74 .ascii "uint16\000" - 3853 313600 - 3854 .LASF51: - 3855 001a 55534246 .ascii "USBFS_TerminateEP\000" - 3855 535F5465 - 3855 726D696E - 3855 61746545 - 3855 5000 - 3856 .LASF78: - 3857 002c 55534246 .ascii "USBFS_currentTD\000" - 3857 535F6375 - 3857 7272656E - 3857 74544400 - 3858 .LASF81: - 3859 003c 55534246 .ascii "USBFS_InitControlRead\000" - 3859 535F496E - 3859 6974436F - 3859 6E74726F - 3859 6C526561 - 3860 .LASF7: - 3861 0052 6C6F6E67 .ascii "long long unsigned int\000" - 3861 206C6F6E - 3861 6720756E - 3861 7369676E - 3861 65642069 - 3862 .LASF20: - 3863 0069 61646472 .ascii "addr\000" - 3863 00 - 3864 .LASF58: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 93 - - - 3865 006e 696E7465 .ascii "interfaceNumber\000" - 3865 72666163 - 3865 654E756D - 3865 62657200 - 3866 .LASF62: - 3867 007e 55534246 .ascii "USBFS_tBuffer\000" - 3867 535F7442 - 3867 75666665 - 3867 7200 - 3868 .LASF6: - 3869 008c 6C6F6E67 .ascii "long long int\000" - 3869 206C6F6E - 3869 6720696E - 3869 7400 - 3870 .LASF0: - 3871 009a 7369676E .ascii "signed char\000" - 3871 65642063 - 3871 68617200 - 3872 .LASF48: - 3873 00a6 636C6561 .ascii "clearAltSetting\000" - 3873 72416C74 - 3873 53657474 - 3873 696E6700 - 3874 .LASF74: - 3875 00b6 55534246 .ascii "USBFS_deviceAddress\000" - 3875 535F6465 - 3875 76696365 - 3875 41646472 - 3875 65737300 - 3876 .LASF54: - 3877 00ca 55534246 .ascii "USBFS_ClearEndpointHalt\000" - 3877 535F436C - 3877 65617245 - 3877 6E64706F - 3877 696E7448 - 3878 .LASF71: - 3879 00e2 55534246 .ascii "USBFS_interfaceNumber\000" - 3879 535F696E - 3879 74657266 - 3879 6163654E - 3879 756D6265 - 3880 .LASF47: - 3881 00f8 55534246 .ascii "USBFS_Config\000" - 3881 535F436F - 3881 6E666967 - 3881 00 - 3882 .LASF40: - 3883 0105 55534246 .ascii "USBFS_ConfigReg\000" - 3883 535F436F - 3883 6E666967 - 3883 52656700 - 3884 .LASF4: - 3885 0115 6C6F6E67 .ascii "long int\000" - 3885 20696E74 - 3885 00 - 3886 .LASF9: - 3887 011e 75696E74 .ascii "uint8\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 94 - - - 3887 3800 - 3888 .LASF19: - 3889 0124 6570546F .ascii "epToggle\000" - 3889 67676C65 - 3889 00 - 3890 .LASF12: - 3891 012d 646F7562 .ascii "double\000" - 3891 6C6500 - 3892 .LASF29: - 3893 0134 545F5553 .ascii "T_USBFS_EP_SETTINGS_BLOCK\000" - 3893 4246535F - 3893 45505F53 - 3893 45545449 - 3893 4E47535F - 3894 .LASF52: - 3895 014e 55534246 .ascii "USBFS_SetEndpointHalt\000" - 3895 535F5365 - 3895 74456E64 - 3895 706F696E - 3895 7448616C - 3896 .LASF34: - 3897 0164 70446174 .ascii "pData\000" - 3897 6100 - 3898 .LASF64: - 3899 016a 55534246 .ascii "USBFS_configuration\000" - 3899 535F636F - 3899 6E666967 - 3899 75726174 - 3899 696F6E00 - 3900 .LASF21: - 3901 017e 65704D6F .ascii "epMode\000" - 3901 646500 - 3902 .LASF8: - 3903 0185 756E7369 .ascii "unsigned int\000" - 3903 676E6564 - 3903 20696E74 - 3903 00 - 3904 .LASF5: - 3905 0192 6C6F6E67 .ascii "long unsigned int\000" - 3905 20756E73 - 3905 69676E65 - 3905 6420696E - 3905 7400 - 3906 .LASF45: - 3907 01a4 55534246 .ascii "USBFS_GetInterfaceClassTablePtr\000" - 3907 535F4765 - 3907 74496E74 - 3907 65726661 - 3907 6365436C - 3908 .LASF3: - 3909 01c4 73686F72 .ascii "short unsigned int\000" - 3909 7420756E - 3909 7369676E - 3909 65642069 - 3909 6E7400 - 3910 .LASF49: - 3911 01d7 70446573 .ascii "pDescr\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 95 - - - 3911 637200 - 3912 .LASF24: - 3913 01de 696E7465 .ascii "interface\000" - 3913 72666163 - 3913 6500 - 3914 .LASF55: - 3915 01e8 55534246 .ascii "USBFS_ValidateAlternateSetting\000" - 3915 535F5661 - 3915 6C696461 - 3915 7465416C - 3915 7465726E - 3916 .LASF65: - 3917 0207 55534246 .ascii "USBFS_configurationChanged\000" - 3917 535F636F - 3917 6E666967 - 3917 75726174 - 3917 696F6E43 - 3918 .LASF85: - 3919 0222 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 3919 43534932 - 3919 53445C73 - 3919 6F667477 - 3919 6172655C - 3920 0251 6E00 .ascii "n\000" - 3921 .LASF76: - 3922 0253 55534246 .ascii "USBFS_interfaceClass\000" - 3922 535F696E - 3922 74657266 - 3922 61636543 - 3922 6C617373 - 3923 .LASF70: - 3924 0268 55534246 .ascii "USBFS_STRING_DESCRIPTORS\000" - 3924 535F5354 - 3924 52494E47 - 3924 5F444553 - 3924 43524950 - 3925 .LASF18: - 3926 0281 68774570 .ascii "hwEpState\000" - 3926 53746174 - 3926 6500 - 3927 .LASF61: - 3928 028b 64657363 .ascii "descrLength\000" - 3928 724C656E - 3928 67746800 - 3929 .LASF15: - 3930 0297 73697A65 .ascii "sizetype\000" - 3930 74797065 - 3930 00 - 3931 .LASF39: - 3932 02a0 70546D70 .ascii "pTmp\000" - 3932 00 - 3933 .LASF37: - 3934 02a5 705F6C69 .ascii "p_list\000" - 3934 737400 - 3935 .LASF50: - 3936 02ac 62756666 .ascii "buffCount\000" - 3936 436F756E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 96 - - - 3936 7400 - 3937 .LASF16: - 3938 02b6 61747472 .ascii "attrib\000" - 3938 696200 - 3939 .LASF68: - 3940 02bd 55534246 .ascii "USBFS_TABLE\000" - 3940 535F5441 - 3940 424C4500 - 3941 .LASF69: - 3942 02c9 55534246 .ascii "USBFS_SN_STRING_DESCRIPTOR\000" - 3942 535F534E - 3942 5F535452 - 3942 494E475F - 3942 44455343 - 3943 .LASF46: - 3944 02e4 63757272 .ascii "currentInterfacesNum\000" - 3944 656E7449 - 3944 6E746572 - 3944 66616365 - 3944 734E756D - 3945 .LASF41: - 3946 02f9 55534246 .ascii "USBFS_ConfigAltChanged\000" - 3946 535F436F - 3946 6E666967 - 3946 416C7443 - 3946 68616E67 - 3947 .LASF32: - 3948 0310 545F5553 .ascii "T_USBFS_XFER_STATUS_BLOCK\000" - 3948 4246535F - 3948 58464552 - 3948 5F535441 - 3948 5455535F - 3949 .LASF56: - 3950 032a 696E7465 .ascii "interfaceNum\000" - 3950 72666163 - 3950 654E756D - 3950 00 - 3951 .LASF67: - 3952 0337 55534246 .ascii "USBFS_DEVICE0_DESCR\000" - 3952 535F4445 - 3952 56494345 - 3952 305F4445 - 3952 53435200 - 3953 .LASF11: - 3954 034b 666C6F61 .ascii "float\000" - 3954 7400 - 3955 .LASF17: - 3956 0351 61706945 .ascii "apiEpState\000" - 3956 70537461 - 3956 746500 - 3957 .LASF77: - 3958 035c 55534246 .ascii "USBFS_EP\000" - 3958 535F4550 - 3958 00 - 3959 .LASF59: - 3960 0365 70537472 .ascii "pStr\000" - 3960 00 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 97 - - - 3961 .LASF83: - 3962 036a 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 3962 4320342E - 3962 372E3320 - 3962 32303133 - 3962 30333132 - 3963 039d 616E6368 .ascii "anch revision 196615]\000" - 3963 20726576 - 3963 6973696F - 3963 6E203139 - 3963 36363135 - 3964 .LASF14: - 3965 03b3 72656738 .ascii "reg8\000" - 3965 00 - 3966 .LASF1: - 3967 03b8 756E7369 .ascii "unsigned char\000" - 3967 676E6564 - 3967 20636861 - 3967 7200 - 3968 .LASF2: - 3969 03c6 73686F72 .ascii "short int\000" - 3969 7420696E - 3969 7400 - 3970 .LASF36: - 3971 03d0 545F5553 .ascii "T_USBFS_TD\000" - 3971 4246535F - 3971 544400 - 3972 .LASF44: - 3973 03db 55534246 .ascii "USBFS_GetConfigTablePtr\000" - 3973 535F4765 - 3973 74436F6E - 3973 66696754 - 3973 61626C65 - 3974 .LASF84: - 3975 03f3 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_std.c\000" - 3975 6E657261 - 3975 7465645F - 3975 536F7572 - 3975 63655C50 - 3976 .LASF72: - 3977 0418 55534246 .ascii "USBFS_interfaceSetting\000" - 3977 535F696E - 3977 74657266 - 3977 61636553 - 3977 65747469 - 3978 .LASF25: - 3979 042f 545F5553 .ascii "T_USBFS_EP_CTL_BLOCK\000" - 3979 4246535F - 3979 45505F43 - 3979 544C5F42 - 3979 4C4F434B - 3980 .LASF80: - 3981 0444 55534246 .ascii "USBFS_InitNoDataControlTransfer\000" - 3981 535F496E - 3981 69744E6F - 3981 44617461 - 3981 436F6E74 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 98 - - - 3982 .LASF63: - 3983 0464 55534246 .ascii "USBFS_device\000" - 3983 535F6465 - 3983 76696365 - 3983 00 - 3984 .LASF27: - 3985 0471 61747472 .ascii "attributes\000" - 3985 69627574 - 3985 657300 - 3986 .LASF26: - 3987 047c 616C7453 .ascii "altSetting\000" - 3987 65747469 - 3987 6E6700 - 3988 .LASF13: - 3989 0487 63686172 .ascii "char\000" - 3989 00 - 3990 .LASF23: - 3991 048c 62756666 .ascii "bufferSize\000" - 3991 65725369 - 3991 7A6500 - 3992 .LASF53: - 3993 0497 72657175 .ascii "requestHandled\000" - 3993 65737448 - 3993 616E646C - 3993 656400 - 3994 .LASF22: - 3995 04a6 62756666 .ascii "buffOffset\000" - 3995 4F666673 - 3995 657400 - 3996 .LASF79: - 3997 04b1 55534246 .ascii "USBFS_GetDeviceTablePtr\000" - 3997 535F4765 - 3997 74446576 - 3997 69636554 - 3997 61626C65 - 3998 .LASF66: - 3999 04c9 55534246 .ascii "USBFS_deviceStatus\000" - 3999 535F6465 - 3999 76696365 - 3999 53746174 - 3999 757300 - 4000 .LASF73: - 4001 04dc 55534246 .ascii "USBFS_interfaceSetting_last\000" - 4001 535F696E - 4001 74657266 - 4001 61636553 - 4001 65747469 - 4002 .LASF31: - 4003 04f8 6C656E67 .ascii "length\000" - 4003 746800 - 4004 .LASF60: - 4005 04ff 6E537472 .ascii "nStr\000" - 4005 00 - 4006 .LASF43: - 4007 0504 65705F74 .ascii "ep_type\000" - 4007 79706500 - 4008 .LASF42: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccZzgZB0.s page 99 - - - 4009 050c 6375725F .ascii "cur_ep\000" - 4009 657000 - 4010 .LASF30: - 4011 0513 73746174 .ascii "status\000" - 4011 757300 - 4012 .LASF82: - 4013 051a 55534246 .ascii "USBFS_DispatchClassRqst\000" - 4013 535F4469 - 4013 73706174 - 4013 6368436C - 4013 61737352 - 4014 .LASF28: - 4015 0532 624D6973 .ascii "bMisc\000" - 4015 6300 - 4016 .LASF75: - 4017 0538 55534246 .ascii "USBFS_interfaceStatus\000" - 4017 535F696E - 4017 74657266 - 4017 61636553 - 4017 74617475 - 4018 .LASF57: - 4019 054e 55534246 .ascii "USBFS_HandleStandardRqst\000" - 4019 535F4861 - 4019 6E646C65 - 4019 5374616E - 4019 64617264 - 4020 .LASF38: - 4021 0567 545F5553 .ascii "T_USBFS_LUT\000" - 4021 4246535F - 4021 4C555400 - 4022 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_std.o deleted file mode 100755 index 2717fa76e318abae0a71167d226e8de5aa3be24f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 17960 zcmcJ0dtg=7neWt<>I;>z%e!jgP*DqB7Ikj^0aTd{t*mZ>=!Z+s4Oqn4y*V{nq~WIXg$Z zGk@H>bnV~z9_#zQ^{utn+IxqycU8-khG8hD7^+kyD5dV7rzI(iG?c1^s!UZpV-%Sm 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z(EQO8^|lH23+nR{{2PV7MeugPgMyC;ep_%<@L9p13hHwc_I@Gs%Yyt775)EO@U-9u zg8JNq+`tAwy)?n8g8YpX&ntb70!xKnAjlt0QLfKZV3W{m1iOeh&q9I&g8Zkx@{elk)>hl@;|4nFpE*Il@i8Sz- z;Bmo|g0Bmn64d82^!Y<9_WM*&pU z(CY>HQ!o10=QWT&?IOKL5TMLp;(X$_C7usRf!@zbiFmHm=M(lD{ho$(TSGq9Ujq^A zsg;O%?IZ@2+De2U7M@p_evL4#?dx+9L?&tMn=q+S`-eaMJ_-zw55FaXIvyzNa}%iJ zLL7@I2kQ6`kA9B?){u|5>IHSY0i{|<19jYpvx78nh=_QP5)t1CBI4se%GY@yA|8Dn z!G9t5HTc!<8}P?(QuH@M4A?)Jqg|*fbFsXy!@iCiw2m8oYDBK%gugza2Z+c+Oz1sC s_`hH12Z=ELH$p#0L_9AEt>Z^rZwoz6M0{t2{u42P_&6@cM?}2;0rE*IZ2$lO diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.lst deleted file mode 100755 index e2a17a0..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.lst +++ /dev/null @@ -1,497 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "USBFS_vnd.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.USBFS_HandleVendorRqst,"ax",%progbits - 19 .align 1 - 20 .global USBFS_HandleVendorRqst - 21 .thumb - 22 .thumb_func - 23 .type USBFS_HandleVendorRqst, %function - 24 USBFS_HandleVendorRqst: - 25 .LFB0: - 26 .file 1 ".\\Generated_Source\\PSoC5\\USBFS_vnd.c" - 1:.\Generated_Source\PSoC5/USBFS_vnd.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/USBFS_vnd.c **** * File Name: USBFS_vnd.c - 3:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Version 2.60 - 4:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 5:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Description: - 6:.\Generated_Source\PSoC5/USBFS_vnd.c **** * USB vendor request handler. - 7:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 8:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Note: - 9:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 10:.\Generated_Source\PSoC5/USBFS_vnd.c **** ******************************************************************************** - 11:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 12:.\Generated_Source\PSoC5/USBFS_vnd.c **** * You may use this file only in accordance with the license, terms, conditions, - 13:.\Generated_Source\PSoC5/USBFS_vnd.c **** * disclaimers, and limitations in the end user license agreement accompanying - 14:.\Generated_Source\PSoC5/USBFS_vnd.c **** * the software package with which this file was provided. - 15:.\Generated_Source\PSoC5/USBFS_vnd.c **** *******************************************************************************/ - 16:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 17:.\Generated_Source\PSoC5/USBFS_vnd.c **** #include "USBFS.h" - 18:.\Generated_Source\PSoC5/USBFS_vnd.c **** #include "USBFS_pvt.h" - 19:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 20:.\Generated_Source\PSoC5/USBFS_vnd.c **** #if(USBFS_EXTERN_VND == USBFS_FALSE) - 21:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 22:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 23:.\Generated_Source\PSoC5/USBFS_vnd.c **** /*************************************** - 24:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Vendor Specific Declarations - 25:.\Generated_Source\PSoC5/USBFS_vnd.c **** ***************************************/ - 26:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 27:.\Generated_Source\PSoC5/USBFS_vnd.c **** /* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */ - 28:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 29:.\Generated_Source\PSoC5/USBFS_vnd.c **** /* `#END` */ - 30:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 31:.\Generated_Source\PSoC5/USBFS_vnd.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 2 - - - 32:.\Generated_Source\PSoC5/USBFS_vnd.c **** /******************************************************************************* - 33:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Function Name: USBFS_HandleVendorRqst - 34:.\Generated_Source\PSoC5/USBFS_vnd.c **** ******************************************************************************** - 35:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 36:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Summary: - 37:.\Generated_Source\PSoC5/USBFS_vnd.c **** * This routine provide users with a method to implement vendor specifc - 38:.\Generated_Source\PSoC5/USBFS_vnd.c **** * requests. - 39:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 40:.\Generated_Source\PSoC5/USBFS_vnd.c **** * To implement vendor specific requests, add your code in this function to - 41:.\Generated_Source\PSoC5/USBFS_vnd.c **** * decode and disposition the request. If the request is handled, your code - 42:.\Generated_Source\PSoC5/USBFS_vnd.c **** * must set the variable "requestHandled" to TRUE, indicating that the - 43:.\Generated_Source\PSoC5/USBFS_vnd.c **** * request has been handled. - 44:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 45:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Parameters: - 46:.\Generated_Source\PSoC5/USBFS_vnd.c **** * None. - 47:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 48:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Return: - 49:.\Generated_Source\PSoC5/USBFS_vnd.c **** * requestHandled. - 50:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 51:.\Generated_Source\PSoC5/USBFS_vnd.c **** * Reentrant: - 52:.\Generated_Source\PSoC5/USBFS_vnd.c **** * No. - 53:.\Generated_Source\PSoC5/USBFS_vnd.c **** * - 54:.\Generated_Source\PSoC5/USBFS_vnd.c **** *******************************************************************************/ - 55:.\Generated_Source\PSoC5/USBFS_vnd.c **** uint8 USBFS_HandleVendorRqst(void) - 56:.\Generated_Source\PSoC5/USBFS_vnd.c **** { - 27 .loc 1 56 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 32 .LVL0: - 57:.\Generated_Source\PSoC5/USBFS_vnd.c **** uint8 requestHandled = USBFS_FALSE; - 58:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 59:.\Generated_Source\PSoC5/USBFS_vnd.c **** if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - 33 .loc 1 59 0 - 34 0000 034B ldr r3, .L3 - 35 0002 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 36 0004 0106 lsls r1, r0, #24 - 60:.\Generated_Source\PSoC5/USBFS_vnd.c **** { - 61:.\Generated_Source\PSoC5/USBFS_vnd.c **** /* Control Read */ - 62:.\Generated_Source\PSoC5/USBFS_vnd.c **** switch (CY_GET_REG8(USBFS_bRequest)) - 37 .loc 1 62 0 - 38 0006 44BF itt mi - 39 0008 0249 ldrmi r1, .L3+4 - 40 000a 0978 ldrbmi r1, [r1, #0] @ zero_extendqisi2 - 63:.\Generated_Source\PSoC5/USBFS_vnd.c **** { - 64:.\Generated_Source\PSoC5/USBFS_vnd.c **** case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: - 65:.\Generated_Source\PSoC5/USBFS_vnd.c **** #if defined(USBFS_ENABLE_MSOS_STRING) - 66:.\Generated_Source\PSoC5/USBFS_vnd.c **** USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u]; - 67:.\Generated_Source\PSoC5/USBFS_vnd.c **** USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; - 68:.\Generated_Source\PSoC5/USBFS_vnd.c **** requestHandled = USBFS_InitControlRead(); - 69:.\Generated_Source\PSoC5/USBFS_vnd.c **** #endif /* End USBFS_ENABLE_MSOS_STRING */ - 70:.\Generated_Source\PSoC5/USBFS_vnd.c **** break; - 71:.\Generated_Source\PSoC5/USBFS_vnd.c **** default: - 72:.\Generated_Source\PSoC5/USBFS_vnd.c **** break; - 73:.\Generated_Source\PSoC5/USBFS_vnd.c **** } - 74:.\Generated_Source\PSoC5/USBFS_vnd.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 3 - - - 75:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 76:.\Generated_Source\PSoC5/USBFS_vnd.c **** /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */ - 77:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 78:.\Generated_Source\PSoC5/USBFS_vnd.c **** /* `#END` */ - 79:.\Generated_Source\PSoC5/USBFS_vnd.c **** - 80:.\Generated_Source\PSoC5/USBFS_vnd.c **** return(requestHandled); - 81:.\Generated_Source\PSoC5/USBFS_vnd.c **** } - 41 .loc 1 81 0 - 42 000c 0020 movs r0, #0 - 43 000e 7047 bx lr - 44 .L4: - 45 .align 2 - 46 .L3: - 47 0010 00600040 .word 1073766400 - 48 0014 01600040 .word 1073766401 - 49 .cfi_endproc - 50 .LFE0: - 51 .size USBFS_HandleVendorRqst, .-USBFS_HandleVendorRqst - 52 .text - 53 .Letext0: - 54 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 55 .section .debug_info,"",%progbits - 56 .Ldebug_info0: - 57 0000 C9000000 .4byte 0xc9 - 58 0004 0200 .2byte 0x2 - 59 0006 00000000 .4byte .Ldebug_abbrev0 - 60 000a 04 .byte 0x4 - 61 000b 01 .uleb128 0x1 - 62 000c 57000000 .4byte .LASF15 - 63 0010 01 .byte 0x1 - 64 0011 1B000000 .4byte .LASF16 - 65 0015 35010000 .4byte .LASF17 - 66 0019 00000000 .4byte .Ldebug_ranges0+0 - 67 001d 00000000 .4byte 0 - 68 0021 00000000 .4byte 0 - 69 0025 00000000 .4byte .Ldebug_line0 - 70 0029 02 .uleb128 0x2 - 71 002a 01 .byte 0x1 - 72 002b 06 .byte 0x6 - 73 002c 19010000 .4byte .LASF0 - 74 0030 02 .uleb128 0x2 - 75 0031 01 .byte 0x1 - 76 0032 08 .byte 0x8 - 77 0033 DE000000 .4byte .LASF1 - 78 0037 02 .uleb128 0x2 - 79 0038 02 .byte 0x2 - 80 0039 05 .byte 0x5 - 81 003a 2B010000 .4byte .LASF2 - 82 003e 02 .uleb128 0x2 - 83 003f 02 .byte 0x2 - 84 0040 07 .byte 0x7 - 85 0041 06010000 .4byte .LASF3 - 86 0045 02 .uleb128 0x2 - 87 0046 04 .byte 0x4 - 88 0047 05 .byte 0x5 - 89 0048 F1000000 .4byte .LASF4 - 90 004c 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 4 - - - 91 004d 04 .byte 0x4 - 92 004e 07 .byte 0x7 - 93 004f A6000000 .4byte .LASF5 - 94 0053 02 .uleb128 0x2 - 95 0054 08 .byte 0x8 - 96 0055 05 .byte 0x5 - 97 0056 00000000 .4byte .LASF6 - 98 005a 02 .uleb128 0x2 - 99 005b 08 .byte 0x8 - 100 005c 07 .byte 0x7 - 101 005d C7000000 .4byte .LASF7 - 102 0061 03 .uleb128 0x3 - 103 0062 04 .byte 0x4 - 104 0063 05 .byte 0x5 - 105 0064 696E7400 .ascii "int\000" - 106 0068 02 .uleb128 0x2 - 107 0069 04 .byte 0x4 - 108 006a 07 .byte 0x7 - 109 006b 0E000000 .4byte .LASF8 - 110 006f 04 .uleb128 0x4 - 111 0070 A0000000 .4byte .LASF12 - 112 0074 02 .byte 0x2 - 113 0075 5B .byte 0x5b - 114 0076 30000000 .4byte 0x30 - 115 007a 02 .uleb128 0x2 - 116 007b 04 .byte 0x4 - 117 007c 04 .byte 0x4 - 118 007d 25010000 .4byte .LASF9 - 119 0081 02 .uleb128 0x2 - 120 0082 08 .byte 0x8 - 121 0083 04 .byte 0x4 - 122 0084 FF000000 .4byte .LASF10 - 123 0088 02 .uleb128 0x2 - 124 0089 01 .byte 0x1 - 125 008a 08 .byte 0x8 - 126 008b EC000000 .4byte .LASF11 - 127 008f 04 .uleb128 0x4 - 128 0090 FA000000 .4byte .LASF13 - 129 0094 02 .byte 0x2 - 130 0095 F0 .byte 0xf0 - 131 0096 9A000000 .4byte 0x9a - 132 009a 05 .uleb128 0x5 - 133 009b 6F000000 .4byte 0x6f - 134 009f 02 .uleb128 0x2 - 135 00a0 04 .byte 0x4 - 136 00a1 07 .byte 0x7 - 137 00a2 66010000 .4byte .LASF14 - 138 00a6 06 .uleb128 0x6 - 139 00a7 01 .byte 0x1 - 140 00a8 40000000 .4byte .LASF18 - 141 00ac 01 .byte 0x1 - 142 00ad 37 .byte 0x37 - 143 00ae 01 .byte 0x1 - 144 00af 6F000000 .4byte 0x6f - 145 00b3 00000000 .4byte .LFB0 - 146 00b7 18000000 .4byte .LFE0 - 147 00bb 02 .byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 5 - - - 148 00bc 7D .byte 0x7d - 149 00bd 00 .sleb128 0 - 150 00be 01 .byte 0x1 - 151 00bf 07 .uleb128 0x7 - 152 00c0 B8000000 .4byte .LASF19 - 153 00c4 01 .byte 0x1 - 154 00c5 39 .byte 0x39 - 155 00c6 6F000000 .4byte 0x6f - 156 00ca 00 .byte 0 - 157 00cb 00 .byte 0 - 158 00cc 00 .byte 0 - 159 .section .debug_abbrev,"",%progbits - 160 .Ldebug_abbrev0: - 161 0000 01 .uleb128 0x1 - 162 0001 11 .uleb128 0x11 - 163 0002 01 .byte 0x1 - 164 0003 25 .uleb128 0x25 - 165 0004 0E .uleb128 0xe - 166 0005 13 .uleb128 0x13 - 167 0006 0B .uleb128 0xb - 168 0007 03 .uleb128 0x3 - 169 0008 0E .uleb128 0xe - 170 0009 1B .uleb128 0x1b - 171 000a 0E .uleb128 0xe - 172 000b 55 .uleb128 0x55 - 173 000c 06 .uleb128 0x6 - 174 000d 11 .uleb128 0x11 - 175 000e 01 .uleb128 0x1 - 176 000f 52 .uleb128 0x52 - 177 0010 01 .uleb128 0x1 - 178 0011 10 .uleb128 0x10 - 179 0012 06 .uleb128 0x6 - 180 0013 00 .byte 0 - 181 0014 00 .byte 0 - 182 0015 02 .uleb128 0x2 - 183 0016 24 .uleb128 0x24 - 184 0017 00 .byte 0 - 185 0018 0B .uleb128 0xb - 186 0019 0B .uleb128 0xb - 187 001a 3E .uleb128 0x3e - 188 001b 0B .uleb128 0xb - 189 001c 03 .uleb128 0x3 - 190 001d 0E .uleb128 0xe - 191 001e 00 .byte 0 - 192 001f 00 .byte 0 - 193 0020 03 .uleb128 0x3 - 194 0021 24 .uleb128 0x24 - 195 0022 00 .byte 0 - 196 0023 0B .uleb128 0xb - 197 0024 0B .uleb128 0xb - 198 0025 3E .uleb128 0x3e - 199 0026 0B .uleb128 0xb - 200 0027 03 .uleb128 0x3 - 201 0028 08 .uleb128 0x8 - 202 0029 00 .byte 0 - 203 002a 00 .byte 0 - 204 002b 04 .uleb128 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 6 - - - 205 002c 16 .uleb128 0x16 - 206 002d 00 .byte 0 - 207 002e 03 .uleb128 0x3 - 208 002f 0E .uleb128 0xe - 209 0030 3A .uleb128 0x3a - 210 0031 0B .uleb128 0xb - 211 0032 3B .uleb128 0x3b - 212 0033 0B .uleb128 0xb - 213 0034 49 .uleb128 0x49 - 214 0035 13 .uleb128 0x13 - 215 0036 00 .byte 0 - 216 0037 00 .byte 0 - 217 0038 05 .uleb128 0x5 - 218 0039 35 .uleb128 0x35 - 219 003a 00 .byte 0 - 220 003b 49 .uleb128 0x49 - 221 003c 13 .uleb128 0x13 - 222 003d 00 .byte 0 - 223 003e 00 .byte 0 - 224 003f 06 .uleb128 0x6 - 225 0040 2E .uleb128 0x2e - 226 0041 01 .byte 0x1 - 227 0042 3F .uleb128 0x3f - 228 0043 0C .uleb128 0xc - 229 0044 03 .uleb128 0x3 - 230 0045 0E .uleb128 0xe - 231 0046 3A .uleb128 0x3a - 232 0047 0B .uleb128 0xb - 233 0048 3B .uleb128 0x3b - 234 0049 0B .uleb128 0xb - 235 004a 27 .uleb128 0x27 - 236 004b 0C .uleb128 0xc - 237 004c 49 .uleb128 0x49 - 238 004d 13 .uleb128 0x13 - 239 004e 11 .uleb128 0x11 - 240 004f 01 .uleb128 0x1 - 241 0050 12 .uleb128 0x12 - 242 0051 01 .uleb128 0x1 - 243 0052 40 .uleb128 0x40 - 244 0053 0A .uleb128 0xa - 245 0054 9742 .uleb128 0x2117 - 246 0056 0C .uleb128 0xc - 247 0057 00 .byte 0 - 248 0058 00 .byte 0 - 249 0059 07 .uleb128 0x7 - 250 005a 34 .uleb128 0x34 - 251 005b 00 .byte 0 - 252 005c 03 .uleb128 0x3 - 253 005d 0E .uleb128 0xe - 254 005e 3A .uleb128 0x3a - 255 005f 0B .uleb128 0xb - 256 0060 3B .uleb128 0x3b - 257 0061 0B .uleb128 0xb - 258 0062 49 .uleb128 0x49 - 259 0063 13 .uleb128 0x13 - 260 0064 1C .uleb128 0x1c - 261 0065 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 7 - - - 262 0066 00 .byte 0 - 263 0067 00 .byte 0 - 264 0068 00 .byte 0 - 265 .section .debug_aranges,"",%progbits - 266 0000 1C000000 .4byte 0x1c - 267 0004 0200 .2byte 0x2 - 268 0006 00000000 .4byte .Ldebug_info0 - 269 000a 04 .byte 0x4 - 270 000b 00 .byte 0 - 271 000c 0000 .2byte 0 - 272 000e 0000 .2byte 0 - 273 0010 00000000 .4byte .LFB0 - 274 0014 18000000 .4byte .LFE0-.LFB0 - 275 0018 00000000 .4byte 0 - 276 001c 00000000 .4byte 0 - 277 .section .debug_ranges,"",%progbits - 278 .Ldebug_ranges0: - 279 0000 00000000 .4byte .LFB0 - 280 0004 18000000 .4byte .LFE0 - 281 0008 00000000 .4byte 0 - 282 000c 00000000 .4byte 0 - 283 .section .debug_line,"",%progbits - 284 .Ldebug_line0: - 285 0000 62000000 .section .debug_str,"MS",%progbits,1 - 285 02004800 - 285 00000201 - 285 FB0E0D00 - 285 01010101 - 286 .LASF6: - 287 0000 6C6F6E67 .ascii "long long int\000" - 287 206C6F6E - 287 6720696E - 287 7400 - 288 .LASF8: - 289 000e 756E7369 .ascii "unsigned int\000" - 289 676E6564 - 289 20696E74 - 289 00 - 290 .LASF16: - 291 001b 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\USBFS_vnd.c\000" - 291 6E657261 - 291 7465645F - 291 536F7572 - 291 63655C50 - 292 .LASF18: - 293 0040 55534246 .ascii "USBFS_HandleVendorRqst\000" - 293 535F4861 - 293 6E646C65 - 293 56656E64 - 293 6F725271 - 294 .LASF15: - 295 0057 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 295 4320342E - 295 372E3320 - 295 32303133 - 295 30333132 - 296 008a 616E6368 .ascii "anch revision 196615]\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 8 - - - 296 20726576 - 296 6973696F - 296 6E203139 - 296 36363135 - 297 .LASF12: - 298 00a0 75696E74 .ascii "uint8\000" - 298 3800 - 299 .LASF5: - 300 00a6 6C6F6E67 .ascii "long unsigned int\000" - 300 20756E73 - 300 69676E65 - 300 6420696E - 300 7400 - 301 .LASF19: - 302 00b8 72657175 .ascii "requestHandled\000" - 302 65737448 - 302 616E646C - 302 656400 - 303 .LASF7: - 304 00c7 6C6F6E67 .ascii "long long unsigned int\000" - 304 206C6F6E - 304 6720756E - 304 7369676E - 304 65642069 - 305 .LASF1: - 306 00de 756E7369 .ascii "unsigned char\000" - 306 676E6564 - 306 20636861 - 306 7200 - 307 .LASF11: - 308 00ec 63686172 .ascii "char\000" - 308 00 - 309 .LASF4: - 310 00f1 6C6F6E67 .ascii "long int\000" - 310 20696E74 - 310 00 - 311 .LASF13: - 312 00fa 72656738 .ascii "reg8\000" - 312 00 - 313 .LASF10: - 314 00ff 646F7562 .ascii "double\000" - 314 6C6500 - 315 .LASF3: - 316 0106 73686F72 .ascii "short unsigned int\000" - 316 7420756E - 316 7369676E - 316 65642069 - 316 6E7400 - 317 .LASF0: - 318 0119 7369676E .ascii "signed char\000" - 318 65642063 - 318 68617200 - 319 .LASF9: - 320 0125 666C6F61 .ascii "float\000" - 320 7400 - 321 .LASF2: - 322 012b 73686F72 .ascii "short int\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccwHw8QE.s page 9 - - - 322 7420696E - 322 7400 - 323 .LASF17: - 324 0135 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 324 43534932 - 324 53445C73 - 324 6F667477 - 324 6172655C - 325 0164 6E00 .ascii "n\000" - 326 .LASF14: - 327 0166 73697A65 .ascii "sizetype\000" - 327 74797065 - 327 00 - 328 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/USBFS_vnd.o deleted file mode 100755 index 74531cca2550842a1217da9b1f030a8f43902e35..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2796 zcmb_eOK%)S5U!pX?>c@ge#F5h5gL%KIA9Nc#)(11j*~bRHbh>W2*r_^-RZSgtY_?* z*Z+`J(-AFY_3>in9YpZEb zwk>pbiY_tJ^3nM=qU=Q7`$Q`;p5XKth?C4b@s`q*mJ2W#beU)IcdngqdpH$ens8R< zr7uG_mfl)EsD?$kdL%R1C79N#lHJzl!Uv_=3BCkr{3&Q2?D5m+BSL``^!kKc$?Xi*3 z@saV-F?%qS73oIulzn}6dFeU1S&*J5z2S+qso_HC`o#@9lsC&!Iq>b#v!_pwPTrs@ zc5;T24er}qD7ULJiff6zn!{nQ`jX;?8&WdW&l<}0Gvo!;LPb)v5rnZ__vX{9LL_TS zmB582abnxG>DByPeqk(sVKoX$@tbZa>k1TP?R*f#SmMdhDeiiak6^bX-vrV8+}yN1 z$mMx82r7|X3PKyjurI1&*jK`!D5EF{qf`G!{bt8-@2+$UWfFtj0&_U2+!4?!~9Th#|akE$Si6_L9*3*K}yz~$x$apK))}F{vC6sii6YXxsZh@RA4r{ofImAZi zcy8>HQ-~sRSm8XPOB^(Wr3Y4MVR1 zOZ=XfnNg%|Z$Q>Oo8EVt8K^t=tARprHb%ZH#y&>; zB^h9Z(~#10zp;H<;jF^T3SUupRpAYV{O$8PZeGUQ3g1)sfxp)EDudhAg6`0+xlCH&%szB;>;&mz@SNQoc_1}4A9QUYt%h%8Cl^L#l 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c:/program files (x86)/cypress/psoc creator/3.0/psoc creator/import/gnu_cs/arm/4.7.3/bin/../lib/gcc/arm-none-eabi/4.7.3/armv7-m/crtend.o -LOAD c:/program files (x86)/cypress/psoc creator/3.0/psoc creator/import/gnu_cs/arm/4.7.3/bin/../lib/gcc/arm-none-eabi/4.7.3/armv7-m/crtn.o -START GROUP -LOAD c:/program files (x86)/cypress/psoc creator/3.0/psoc creator/import/gnu_cs/arm/4.7.3/bin/../lib/gcc/arm-none-eabi/4.7.3/armv7-m\libgcc.a -LOAD c:/program files (x86)/cypress/psoc creator/3.0/psoc creator/import/gnu_cs/arm/4.7.3/bin/../lib/gcc/arm-none-eabi/4.7.3/../../../../arm-none-eabi/lib/armv7-m\libc.a -LOAD c:/program files (x86)/cypress/psoc creator/3.0/psoc creator/import/gnu_cs/arm/4.7.3/bin/../lib/gcc/arm-none-eabi/4.7.3/../../../../arm-none-eabi/lib/armv7-m\libnosys.a -END GROUP - 0x00000000 CY_APPL_ORIGIN = 0x0 - 0x00000100 CY_FLASH_ROW_SIZE = 0x100 - 0x00000020 CY_ECC_ROW_SIZE = 0x20 - 0x00000000 CY_EE_IN_BTLDR = 0x0 - 0x00000000 CY_APPL_LOADABLE = 0x0 - 0x00000800 CY_EE_SIZE = 0x800 - 0x00000001 CY_APPL_NUM = 0x1 - 0x00000001 CY_APPL_MAX = 0x1 - 0x00000040 CY_METADATA_SIZE = 0x40 - 0x1fffc278 PROVIDE (__cy_heap_start, _end) - 0x00000001 PROVIDE (__cy_region_num, ((__cy_regions_end - __cy_regions) / 0x10)) - 0x20004000 PROVIDE (__cy_stack, (ORIGIN (ram) + 0x8000)) - 0x20002000 PROVIDE (__cy_heap_end, (__cy_stack - 0x2000)) - -.cybootloader 0x00000000 0x0 - *(.cybootloader) - 0x00000000 appl1_start = CY_APPL_ORIGIN?CY_APPL_ORIGIN:ALIGN (CY_FLASH_ROW_SIZE) - 0x0000ff00 appl2_start = (appl1_start + ALIGN ((((0x20000 - appl1_start) - (0x2 * CY_FLASH_ROW_SIZE)) / 0x2), CY_FLASH_ROW_SIZE)) - 0x00000000 appl_start = (CY_APPL_NUM == 0x1)?appl1_start:appl2_start - 0x00000000 ecc_offset = ((appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE) - 0x00000000 ee_offset = (CY_APPL_LOADABLE && ! (CY_EE_IN_BTLDR))?((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 0x1)):0x0 - 0x00000800 ee_size = (CY_APPL_LOADABLE && ! (CY_EE_IN_BTLDR))?(CY_EE_SIZE / CY_APPL_MAX):CY_EE_SIZE - 0x00000000 PROVIDE (CY_ECC_OFFSET, ecc_offset) - -.text 0x00000000 0x2004 - CREATE_OBJECT_SYMBOLS - 0x00000000 PROVIDE (__cy_interrupt_vector, RomVectors) - *(.romvectors) - .romvectors 0x00000000 0x10 .\CortexM3\ARM_GCC_473\Release\Cm3Start.o - 0x00000000 RomVectors - 0x00000001 ASSERT ((. != __cy_interrupt_vector), No interrupt vector) - 0x00000001 ASSERT (CY_APPL_ORIGIN?(SIZEOF (.cybootloader) <= CY_APPL_ORIGIN):0x1, Wrong image location) - 0x00000010 PROVIDE (__cy_reset, Reset) - *(.text.Reset) - .text.Reset 0x00000010 0x1c .\CortexM3\ARM_GCC_473\Release\Cm3Start.o - 0x00000010 Reset - 0x00000001 ASSERT ((. != __cy_reset), No reset code) - *(.dma_init) - 0x00000001 ASSERT ((((appl_start + .) <= 0x10000) || 0x1), DMA Init must be within the first 64k of flash) - *(.text .text.* .gnu.linkonce.t.*) - .text 0x0000002c 0x54 c:/program files (x86)/cypress/psoc creator/3.0/psoc creator/import/gnu_cs/arm/4.7.3/bin/../lib/gcc/arm-none-eabi/4.7.3/armv7-m/crtbegin.o - .text.startup.main - 0x00000080 0xe0 .\CortexM3\ARM_GCC_473\Release\main.o - 0x00000080 main - .text.IntDefaultHandler - 0x00000160 0x2 .\CortexM3\ARM_GCC_473\Release\Cm3Start.o - 0x00000160 IntDefaultHandler - *fill* 0x00000162 0x2 00 - .text.Start_c 0x00000164 0x54 .\CortexM3\ARM_GCC_473\Release\Cm3Start.o - 0x00000164 Start_c - .text.startup.initialize_psoc - 0x000001b8 0x68 .\CortexM3\ARM_GCC_473\Release\Cm3Start.o - 0x000001b8 initialize_psoc - .text.cyfitter_cfg - 0x00000220 0x1d8 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(cyfitter_cfg.o) - 0x00000220 cyfitter_cfg - .text.BL_LaunchBootloadable - 0x000003f8 0x2 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(BL.o) - *fill* 0x000003fa 0x2 00 - .text.BL_GetMetadata.constprop.1 - 0x000003fc 0x8c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(BL.o) - .text.BL_ValidateBootloadable.constprop.0 - 0x00000488 0x84 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(BL.o) - .text.BL_HostLink - 0x0000050c 0x384 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(BL.o) - .text.BL_Start - 0x00000890 0x80 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(BL.o) - 0x00000890 BL_Start - .text.CyBtldr_CheckLaunch - 0x00000910 0x30 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(BL.o) - 0x00000910 CyBtldr_CheckLaunch - .text 0x00000940 0x28 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyBootAsmGnu.o) - 0x00000940 CyDelayCycles - 0x00000954 CyEnterCriticalSection - 0x0000095c CyExitCriticalSection - .text.CySetTempInt.part.0 - 0x00000968 0x54 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyFlash.o) - .text.CySetTemp - 0x000009bc 0x28 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyFlash.o) - 0x000009bc CySetTemp - .text.CySetFlashEEBuffer - 0x000009e4 0x2c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyFlash.o) - 0x000009e4 CySetFlashEEBuffer - .text.CyWriteRowFull - 0x00000a10 0xa0 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyFlash.o) - 0x00000a10 CyWriteRowFull - .text.CyEEPROM_Start - 0x00000ab0 0x18 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyFlash.o) - 0x00000ab0 CyEEPROM_Start - .text.CyHalt 0x00000ac8 0x4 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyLib.o) - 0x00000ac8 CyHalt - .text.CySoftwareReset - 0x00000acc 0x10 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyLib.o) - 0x00000acc CySoftwareReset - .text.CyDelay 0x00000adc 0x28 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyLib.o) - 0x00000adc CyDelay - .text.CyDelayUs - 0x00000b04 0x10 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyLib.o) - 0x00000b04 CyDelayUs - .text.CyIntSetVector - 0x00000b14 0x1c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyLib.o) - 0x00000b14 CyIntSetVector - .text.CyIntSetPriority - 0x00000b30 0x14 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CyLib.o) - 0x00000b30 CyIntSetPriority - .text.CySpcStart - 0x00000b44 0x24 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CySpc.o) - 0x00000b44 CySpcStart - .text.CySpcReadData - 0x00000b68 0x34 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CySpc.o) - 0x00000b68 CySpcReadData - .text.CySpcLoadRow - 0x00000b9c 0x4c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CySpc.o) - 0x00000b9c CySpcLoadRow - .text.CySpcWriteRow - 0x00000be8 0x48 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CySpc.o) - 0x00000be8 CySpcWriteRow - .text.CySpcGetTemp - 0x00000c30 0x3c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CySpc.o) - 0x00000c30 CySpcGetTemp - .text.CySpcLock - 0x00000c6c 0x40 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CySpc.o) - 0x00000c6c CySpcLock - .text.CySpcUnlock - 0x00000cac 0x34 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(CySpc.o) - 0x00000cac CySpcUnlock - .text.USBFS_CyBtldrCommStart - 0x00000ce0 0x18 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_boot.o) - 0x00000ce0 USBFS_CyBtldrCommStart - .text.USBFS_CyBtldrCommReset - 0x00000cf8 0x6 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_boot.o) - 0x00000cf8 USBFS_CyBtldrCommReset - *fill* 0x00000cfe 0x2 00 - .text.USBFS_CyBtldrCommWrite - 0x00000d00 0x54 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_boot.o) - 0x00000d00 USBFS_CyBtldrCommWrite - .text.USBFS_CyBtldrCommRead - 0x00000d54 0xb0 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_boot.o) - 0x00000d54 USBFS_CyBtldrCommRead - .text.USBFS_Init - 0x00000e04 0x114 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x00000e04 USBFS_Init - .text.USBFS_InitComponent - 0x00000f18 0x98 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x00000f18 USBFS_InitComponent - .text.USBFS_Start - 0x00000fb0 0x24 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x00000fb0 USBFS_Start - .text.USBFS_ReInitComponent - 0x00000fd4 0x58 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x00000fd4 USBFS_ReInitComponent - .text.USBFS_GetConfiguration - 0x0000102c 0xc .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x0000102c USBFS_GetConfiguration - .text.USBFS_IsConfigurationChanged - 0x00001038 0x14 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x00001038 USBFS_IsConfigurationChanged - .text.USBFS_GetEPState - 0x0000104c 0x10 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x0000104c USBFS_GetEPState - .text.USBFS_GetEPCount - 0x0000105c 0x2c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x0000105c USBFS_GetEPCount - .text.USBFS_LoadInEP - 0x00001088 0x7c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x00001088 USBFS_LoadInEP - .text.USBFS_EnableOutEP - 0x00001104 0x28 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x00001104 USBFS_EnableOutEP - .text.USBFS_ReadOutEP - 0x0000112c 0x4c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS.o) - 0x0000112c USBFS_ReadOutEP - .text.USBFS_LoadEP0 - 0x00001178 0x94 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x00001178 USBFS_LoadEP0 - .text.USBFS_InitZeroLengthControlTransfer - 0x0000120c 0x34 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x0000120c USBFS_InitZeroLengthControlTransfer - .text.USBFS_ControlWriteDataStage - 0x00001240 0x74 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x00001240 USBFS_ControlWriteDataStage - .text.USBFS_InitNoDataControlTransfer - 0x000012b4 0x2c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x000012b4 USBFS_InitNoDataControlTransfer - .text.USBFS_UpdateStatusBlock - 0x000012e0 0x20 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x000012e0 USBFS_UpdateStatusBlock - .text.USBFS_NoDataControlStatusStage - 0x00001300 0x3c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x00001300 USBFS_NoDataControlStatusStage - .text.USBFS_ControlWriteStatusStage - 0x0000133c 0x20 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x0000133c USBFS_ControlWriteStatusStage - .text.USBFS_HandleIN - 0x0000135c 0x24 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x0000135c USBFS_HandleIN - .text.USBFS_ControlReadStatusStage - 0x00001380 0x34 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x00001380 USBFS_ControlReadStatusStage - .text.USBFS_HandleOUT - 0x000013b4 0x38 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x000013b4 USBFS_HandleOUT - .text.USBFS_HandleSetup - 0x000013ec 0x54 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x000013ec USBFS_HandleSetup - .text.USBFS_EP_0_ISR - 0x00001440 0xa0 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x00001440 USBFS_EP_0_ISR - .text.USBFS_InitializeStatusBlock - 0x000014e0 0x20 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x000014e0 USBFS_InitializeStatusBlock - .text.USBFS_InitControlWrite - 0x00001500 0x48 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x00001500 USBFS_InitControlWrite - .text.USBFS_InitControlRead - 0x00001548 0x50 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_drv.o) - 0x00001548 USBFS_InitControlRead - .text.USBFS_EP_1_ISR - 0x00001598 0x34 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_episr.o) - 0x00001598 USBFS_EP_1_ISR - .text.USBFS_EP_2_ISR - 0x000015cc 0x34 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_episr.o) - 0x000015cc USBFS_EP_2_ISR - .text.USBFS_SOF_ISR - 0x00001600 0x2 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_episr.o) - 0x00001600 USBFS_SOF_ISR - .text.USBFS_BUS_RESET_ISR - 0x00001602 0x4 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_episr.o) - 0x00001602 USBFS_BUS_RESET_ISR - *fill* 0x00001606 0x2 00 - .text.USBFS_FindHidClassDecriptor - 0x00001608 0x40 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_hid.o) - 0x00001608 USBFS_FindHidClassDecriptor - .text.USBFS_FindReportDescriptor - 0x00001648 0x48 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_hid.o) - 0x00001648 USBFS_FindReportDescriptor - .text.USBFS_FindReport - 0x00001690 0x74 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_hid.o) - 0x00001690 USBFS_FindReport - .text.USBFS_DispatchHIDClassRqst - 0x00001704 0x110 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_hid.o) - 0x00001704 USBFS_DispatchHIDClassRqst - .text.USBFS_ConfigReg - 0x00001814 0xb4 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x00001814 USBFS_ConfigReg - .text.USBFS_GetConfigTablePtr - 0x000018c8 0x1c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x000018c8 USBFS_GetConfigTablePtr - .text.USBFS_ConfigAltChanged - 0x000018e4 0x128 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x000018e4 USBFS_ConfigAltChanged - .text.USBFS_GetInterfaceClassTablePtr - 0x00001a0c 0x20 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x00001a0c USBFS_GetInterfaceClassTablePtr - .text.USBFS_Config - 0x00001a2c 0x168 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x00001a2c USBFS_Config - .text.USBFS_SetEndpointHalt - 0x00001b94 0x58 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x00001b94 USBFS_SetEndpointHalt - .text.USBFS_ClearEndpointHalt - 0x00001bec 0x7c .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x00001bec USBFS_ClearEndpointHalt - .text.USBFS_ValidateAlternateSetting - 0x00001c68 0x48 .\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a(USBFS_std.o) - 0x00001c68 USBFS_ValidateAlternateSetting - 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- - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "cyPm.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.CyPmHibSlpSaveSet,"ax",%progbits - 19 .align 1 - 20 .thumb - 21 .thumb_func - 22 .type CyPmHibSlpSaveSet, %function - 23 CyPmHibSlpSaveSet: - 24 .LFB11: - 25 .file 1 ".\\Generated_Source\\PSoC5\\cyPm.c" - 1:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/cyPm.c **** * File Name: cyPm.c - 3:.\Generated_Source\PSoC5/cyPm.c **** * Version 4.0 - 4:.\Generated_Source\PSoC5/cyPm.c **** * - 5:.\Generated_Source\PSoC5/cyPm.c **** * Description: - 6:.\Generated_Source\PSoC5/cyPm.c **** * Provides an API for the power management. - 7:.\Generated_Source\PSoC5/cyPm.c **** * - 8:.\Generated_Source\PSoC5/cyPm.c **** * Note: - 9:.\Generated_Source\PSoC5/cyPm.c **** * Documentation of the API's in this file is located in the - 10:.\Generated_Source\PSoC5/cyPm.c **** * System Reference Guide provided with PSoC Creator. - 11:.\Generated_Source\PSoC5/cyPm.c **** * - 12:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** - 13:.\Generated_Source\PSoC5/cyPm.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 14:.\Generated_Source\PSoC5/cyPm.c **** * You may use this file only in accordance with the license, terms, conditions, - 15:.\Generated_Source\PSoC5/cyPm.c **** * disclaimers, and limitations in the end user license agreement accompanying - 16:.\Generated_Source\PSoC5/cyPm.c **** * the software package with which this file was provided. - 17:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - 18:.\Generated_Source\PSoC5/cyPm.c **** - 19:.\Generated_Source\PSoC5/cyPm.c **** #include "cyPm.h" - 20:.\Generated_Source\PSoC5/cyPm.c **** - 21:.\Generated_Source\PSoC5/cyPm.c **** - 22:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************* - 23:.\Generated_Source\PSoC5/cyPm.c **** * Place your includes, defines and code here. Do not use merge - 24:.\Generated_Source\PSoC5/cyPm.c **** * region below unless any component datasheet suggest to do so. - 25:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************/ - 26:.\Generated_Source\PSoC5/cyPm.c **** /* `#START CY_PM_HEADER_INCLUDE` */ - 27:.\Generated_Source\PSoC5/cyPm.c **** - 28:.\Generated_Source\PSoC5/cyPm.c **** /* `#END` */ - 29:.\Generated_Source\PSoC5/cyPm.c **** - 30:.\Generated_Source\PSoC5/cyPm.c **** - 31:.\Generated_Source\PSoC5/cyPm.c **** static CY_PM_BACKUP_STRUCT cyPmBackup; - 32:.\Generated_Source\PSoC5/cyPm.c **** static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 2 - - - 33:.\Generated_Source\PSoC5/cyPm.c **** - 34:.\Generated_Source\PSoC5/cyPm.c **** /* Convertion table between register's values and frequency in MHz */ - 35:.\Generated_Source\PSoC5/cyPm.c **** static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; - 36:.\Generated_Source\PSoC5/cyPm.c **** - 37:.\Generated_Source\PSoC5/cyPm.c **** /* Function Prototypes */ - 38:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibSaveSet(void); - 39:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibRestore(void) ; - 40:.\Generated_Source\PSoC5/cyPm.c **** - 41:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibSlpSaveSet(void) ; - 42:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibSlpRestore(void) ; - 43:.\Generated_Source\PSoC5/cyPm.c **** - 44:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHviLviSaveDisable(void) ; - 45:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHviLviRestore(void) ; - 46:.\Generated_Source\PSoC5/cyPm.c **** - 47:.\Generated_Source\PSoC5/cyPm.c **** - 48:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* - 49:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmSaveClocks - 50:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** - 51:.\Generated_Source\PSoC5/cyPm.c **** * - 52:.\Generated_Source\PSoC5/cyPm.c **** * Summary: - 53:.\Generated_Source\PSoC5/cyPm.c **** * This function is called in preparation for entering sleep or hibernate low - 54:.\Generated_Source\PSoC5/cyPm.c **** * power modes. Saves all state of the clocking system that does not persist - 55:.\Generated_Source\PSoC5/cyPm.c **** * during sleep/hibernate or that needs to be altered in preparation for - 56:.\Generated_Source\PSoC5/cyPm.c **** * sleep/hibernate. Shutdowns all the digital and analog clock dividers for the - 57:.\Generated_Source\PSoC5/cyPm.c **** * active power mode configuration. - 58:.\Generated_Source\PSoC5/cyPm.c **** * - 59:.\Generated_Source\PSoC5/cyPm.c **** * Switches the master clock over to the IMO and shuts down the PLL and MHz - 60:.\Generated_Source\PSoC5/cyPm.c **** * Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the - 61:.\Generated_Source\PSoC5/cyPm.c **** * Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. - 62:.\Generated_Source\PSoC5/cyPm.c **** * The ILO and 32 KHz oscillators are not impacted. The current Flash wait state - 63:.\Generated_Source\PSoC5/cyPm.c **** * setting is saved and the Flash wait state setting is set for the current IMO - 64:.\Generated_Source\PSoC5/cyPm.c **** * speed. - 65:.\Generated_Source\PSoC5/cyPm.c **** * - 66:.\Generated_Source\PSoC5/cyPm.c **** * Note If the Master Clock source is routed through the DSI inputs, then it - 67:.\Generated_Source\PSoC5/cyPm.c **** * must be set manually to another source before using the - 68:.\Generated_Source\PSoC5/cyPm.c **** * CyPmSaveClocks()/CyPmRestoreClocks() functions. - 69:.\Generated_Source\PSoC5/cyPm.c **** * - 70:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: - 71:.\Generated_Source\PSoC5/cyPm.c **** * None - 72:.\Generated_Source\PSoC5/cyPm.c **** * - 73:.\Generated_Source\PSoC5/cyPm.c **** * Return: - 74:.\Generated_Source\PSoC5/cyPm.c **** * None - 75:.\Generated_Source\PSoC5/cyPm.c **** * - 76:.\Generated_Source\PSoC5/cyPm.c **** * Side Effects: - 77:.\Generated_Source\PSoC5/cyPm.c **** * All peripheral clocks are going to be off after this API method call. - 78:.\Generated_Source\PSoC5/cyPm.c **** * - 79:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - 80:.\Generated_Source\PSoC5/cyPm.c **** void CyPmSaveClocks(void) - 81:.\Generated_Source\PSoC5/cyPm.c **** { - 82:.\Generated_Source\PSoC5/cyPm.c **** /* Digital and analog clocks - save enable state and disable them all */ - 83:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; - 84:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; - 85:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); - 86:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); - 87:.\Generated_Source\PSoC5/cyPm.c **** - 88:.\Generated_Source\PSoC5/cyPm.c **** /* Save current flash wait cycles and set the maximum value */ - 89:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 3 - - - 90:.\Generated_Source\PSoC5/cyPm.c **** CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); - 91:.\Generated_Source\PSoC5/cyPm.c **** - 92:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ - 93:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - 94:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; - 95:.\Generated_Source\PSoC5/cyPm.c **** - 96:.\Generated_Source\PSoC5/cyPm.c **** /* IMO doubler - save enable state */ - 97:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) - 98:.\Generated_Source\PSoC5/cyPm.c **** { - 99:.\Generated_Source\PSoC5/cyPm.c **** /* IMO doubler enabled - save and disable */ - 100:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imo2x = CY_PM_ENABLED; - 101:.\Generated_Source\PSoC5/cyPm.c **** } - 102:.\Generated_Source\PSoC5/cyPm.c **** else - 103:.\Generated_Source\PSoC5/cyPm.c **** { - 104:.\Generated_Source\PSoC5/cyPm.c **** /* IMO doubler disabled */ - 105:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imo2x = CY_PM_DISABLED; - 106:.\Generated_Source\PSoC5/cyPm.c **** } - 107:.\Generated_Source\PSoC5/cyPm.c **** - 108:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - set appropriate frequency for LPM */ - 109:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); - 110:.\Generated_Source\PSoC5/cyPm.c **** - 111:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - save enable state and enable without wait to settle */ - 112:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) - 113:.\Generated_Source\PSoC5/cyPm.c **** { - 114:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - save enabled state */ - 115:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoEnable = CY_PM_ENABLED; - 116:.\Generated_Source\PSoC5/cyPm.c **** } - 117:.\Generated_Source\PSoC5/cyPm.c **** else - 118:.\Generated_Source\PSoC5/cyPm.c **** { - 119:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - save disabled state */ - 120:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoEnable = CY_PM_DISABLED; - 121:.\Generated_Source\PSoC5/cyPm.c **** - 122:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - enable */ - 123:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); - 124:.\Generated_Source\PSoC5/cyPm.c **** } - 125:.\Generated_Source\PSoC5/cyPm.c **** - 126:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - save the current IMOCLK source and set to IMO if not yet */ - 127:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) - 128:.\Generated_Source\PSoC5/cyPm.c **** { - 129:.\Generated_Source\PSoC5/cyPm.c **** /* DSI or XTAL CLK */ - 130:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoClkSrc = - 131:.\Generated_Source\PSoC5/cyPm.c **** (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_S - 132:.\Generated_Source\PSoC5/cyPm.c **** - 133:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - set IMOCLK source to MHz OSC */ - 134:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetSource(CY_IMO_SOURCE_IMO); - 135:.\Generated_Source\PSoC5/cyPm.c **** } - 136:.\Generated_Source\PSoC5/cyPm.c **** else - 137:.\Generated_Source\PSoC5/cyPm.c **** { - 138:.\Generated_Source\PSoC5/cyPm.c **** /* IMO */ - 139:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; - 140:.\Generated_Source\PSoC5/cyPm.c **** } - 141:.\Generated_Source\PSoC5/cyPm.c **** - 142:.\Generated_Source\PSoC5/cyPm.c **** /* Save clk_imo source */ - 143:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; - 144:.\Generated_Source\PSoC5/cyPm.c **** - 145:.\Generated_Source\PSoC5/cyPm.c **** /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ - 146:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 4 - - - 147:.\Generated_Source\PSoC5/cyPm.c **** { - 148:.\Generated_Source\PSoC5/cyPm.c **** /* Set IMOCLK to source for clk_imo */ - 149:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | - 150:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CLKDIST_IMO_OUT_IMO; - 151:.\Generated_Source\PSoC5/cyPm.c **** } /* Need to change nothing if IMOCLK is source clk_imo */ - 152:.\Generated_Source\PSoC5/cyPm.c **** - 153:.\Generated_Source\PSoC5/cyPm.c **** /* IMO doubler - disable it (saved above) */ - 154:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) - 155:.\Generated_Source\PSoC5/cyPm.c **** { - 156:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_DisableDoubler(); - 157:.\Generated_Source\PSoC5/cyPm.c **** } - 158:.\Generated_Source\PSoC5/cyPm.c **** - 159:.\Generated_Source\PSoC5/cyPm.c **** /* Master clock - save divider and set it to divide-by-one (if no yet) */ - 160:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; - 161:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) - 162:.\Generated_Source\PSoC5/cyPm.c **** { - 163:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); - 164:.\Generated_Source\PSoC5/cyPm.c **** } /* Need to change nothing if master clock divider is 1 */ - 165:.\Generated_Source\PSoC5/cyPm.c **** - 166:.\Generated_Source\PSoC5/cyPm.c **** /* Master clock - save current source */ - 167:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; - 168:.\Generated_Source\PSoC5/cyPm.c **** - 169:.\Generated_Source\PSoC5/cyPm.c **** /* Master clock source - set it to IMO if not yet. */ - 170:.\Generated_Source\PSoC5/cyPm.c **** if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) - 171:.\Generated_Source\PSoC5/cyPm.c **** { - 172:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); - 173:.\Generated_Source\PSoC5/cyPm.c **** } /* Need to change nothing if master clock source is IMO */ - 174:.\Generated_Source\PSoC5/cyPm.c **** - 175:.\Generated_Source\PSoC5/cyPm.c **** /* Bus clock - save divider and set it, if needed, to divide-by-one */ - 176:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); - 177:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; - 178:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) - 179:.\Generated_Source\PSoC5/cyPm.c **** { - 180:.\Generated_Source\PSoC5/cyPm.c **** CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); - 181:.\Generated_Source\PSoC5/cyPm.c **** } /* Do nothing if saved and actual values are equal */ - 182:.\Generated_Source\PSoC5/cyPm.c **** - 183:.\Generated_Source\PSoC5/cyPm.c **** /* Set number of wait cycles for the flash according CPU frequency in MHz */ - 184:.\Generated_Source\PSoC5/cyPm.c **** CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); - 185:.\Generated_Source\PSoC5/cyPm.c **** - 186:.\Generated_Source\PSoC5/cyPm.c **** /* PLL - check enable state, disable if needed */ - 187:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) - 188:.\Generated_Source\PSoC5/cyPm.c **** { - 189:.\Generated_Source\PSoC5/cyPm.c **** /* PLL is enabled - save state and disable */ - 190:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.pllEnableState = CY_PM_ENABLED; - 191:.\Generated_Source\PSoC5/cyPm.c **** CyPLL_OUT_Stop(); - 192:.\Generated_Source\PSoC5/cyPm.c **** } - 193:.\Generated_Source\PSoC5/cyPm.c **** else - 194:.\Generated_Source\PSoC5/cyPm.c **** { - 195:.\Generated_Source\PSoC5/cyPm.c **** /* PLL is disabled - save state */ - 196:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.pllEnableState = CY_PM_DISABLED; - 197:.\Generated_Source\PSoC5/cyPm.c **** } - 198:.\Generated_Source\PSoC5/cyPm.c **** - 199:.\Generated_Source\PSoC5/cyPm.c **** /* MHz ECO - check enable state and disable if needed */ - 200:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) - 201:.\Generated_Source\PSoC5/cyPm.c **** { - 202:.\Generated_Source\PSoC5/cyPm.c **** /* MHz ECO is enabled - save state and disable */ - 203:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 5 - - - 204:.\Generated_Source\PSoC5/cyPm.c **** CyXTAL_Stop(); - 205:.\Generated_Source\PSoC5/cyPm.c **** } - 206:.\Generated_Source\PSoC5/cyPm.c **** else - 207:.\Generated_Source\PSoC5/cyPm.c **** { - 208:.\Generated_Source\PSoC5/cyPm.c **** /* MHz ECO is disabled - save state */ - 209:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; - 210:.\Generated_Source\PSoC5/cyPm.c **** } - 211:.\Generated_Source\PSoC5/cyPm.c **** - 212:.\Generated_Source\PSoC5/cyPm.c **** - 213:.\Generated_Source\PSoC5/cyPm.c **** /*************************************************************************** - 214:.\Generated_Source\PSoC5/cyPm.c **** * Save enable state of delay between the system bus clock and each of the - 215:.\Generated_Source\PSoC5/cyPm.c **** * 4 individual analog clocks. This bit non-retention and it's value should - 216:.\Generated_Source\PSoC5/cyPm.c **** * be restored on wakeup. - 217:.\Generated_Source\PSoC5/cyPm.c **** ***************************************************************************/ - 218:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) - 219:.\Generated_Source\PSoC5/cyPm.c **** { - 220:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; - 221:.\Generated_Source\PSoC5/cyPm.c **** } - 222:.\Generated_Source\PSoC5/cyPm.c **** else - 223:.\Generated_Source\PSoC5/cyPm.c **** { - 224:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; - 225:.\Generated_Source\PSoC5/cyPm.c **** } - 226:.\Generated_Source\PSoC5/cyPm.c **** } - 227:.\Generated_Source\PSoC5/cyPm.c **** - 228:.\Generated_Source\PSoC5/cyPm.c **** - 229:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* - 230:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmRestoreClocks - 231:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** - 232:.\Generated_Source\PSoC5/cyPm.c **** * - 233:.\Generated_Source\PSoC5/cyPm.c **** * Summary: - 234:.\Generated_Source\PSoC5/cyPm.c **** * Restores any state that was preserved by the last call to CyPmSaveClocks(). - 235:.\Generated_Source\PSoC5/cyPm.c **** * The Flash wait state setting is also restored. - 236:.\Generated_Source\PSoC5/cyPm.c **** * - 237:.\Generated_Source\PSoC5/cyPm.c **** * Note If the Master Clock source is routed through the DSI inputs, then it - 238:.\Generated_Source\PSoC5/cyPm.c **** * must be set manually to another source before using the - 239:.\Generated_Source\PSoC5/cyPm.c **** * CyPmSaveClocks()/CyPmRestoreClocks() functions. - 240:.\Generated_Source\PSoC5/cyPm.c **** * - 241:.\Generated_Source\PSoC5/cyPm.c **** * PSoC 3 and PSoC 5LP: - 242:.\Generated_Source\PSoC5/cyPm.c **** * The merge region could be used to process state when the megahertz crystal is - 243:.\Generated_Source\PSoC5/cyPm.c **** * not ready after the hold-off timeout. - 244:.\Generated_Source\PSoC5/cyPm.c **** * - 245:.\Generated_Source\PSoC5/cyPm.c **** * PSoC 5: - 246:.\Generated_Source\PSoC5/cyPm.c **** * The 130 ms is given for the megahertz crystal to stabilize. It's readiness is - 247:.\Generated_Source\PSoC5/cyPm.c **** * not verified after the hold-off timeout. - 248:.\Generated_Source\PSoC5/cyPm.c **** * - 249:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: - 250:.\Generated_Source\PSoC5/cyPm.c **** * None - 251:.\Generated_Source\PSoC5/cyPm.c **** * - 252:.\Generated_Source\PSoC5/cyPm.c **** * Return: - 253:.\Generated_Source\PSoC5/cyPm.c **** * None - 254:.\Generated_Source\PSoC5/cyPm.c **** * - 255:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - 256:.\Generated_Source\PSoC5/cyPm.c **** void CyPmRestoreClocks(void) - 257:.\Generated_Source\PSoC5/cyPm.c **** { - 258:.\Generated_Source\PSoC5/cyPm.c **** cystatus status = CYRET_TIMEOUT; - 259:.\Generated_Source\PSoC5/cyPm.c **** uint16 i; - 260:.\Generated_Source\PSoC5/cyPm.c **** uint16 clkBusDivTmp; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 6 - - - 261:.\Generated_Source\PSoC5/cyPm.c **** - 262:.\Generated_Source\PSoC5/cyPm.c **** - 263:.\Generated_Source\PSoC5/cyPm.c **** /* Convertion table between CyIMO_SetFreq() parameters and register's value */ - 264:.\Generated_Source\PSoC5/cyPm.c **** const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { - 265:.\Generated_Source\PSoC5/cyPm.c **** CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, - 266:.\Generated_Source\PSoC5/cyPm.c **** CY_IMO_FREQ_48MHZ, 5u, 6u}; - 267:.\Generated_Source\PSoC5/cyPm.c **** - 268:.\Generated_Source\PSoC5/cyPm.c **** /* Restore enable state of delay between the system bus clock and ACLKs. */ - 269:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) - 270:.\Generated_Source\PSoC5/cyPm.c **** { - 271:.\Generated_Source\PSoC5/cyPm.c **** /* Delay for both the bandgap and the delay line to settle out */ - 272:.\Generated_Source\PSoC5/cyPm.c **** CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) - 273:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_GET_CPU_FREQ_MHZ); - 274:.\Generated_Source\PSoC5/cyPm.c **** - 275:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; - 276:.\Generated_Source\PSoC5/cyPm.c **** } - 277:.\Generated_Source\PSoC5/cyPm.c **** - 278:.\Generated_Source\PSoC5/cyPm.c **** /* MHz ECO restore state */ - 279:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) - 280:.\Generated_Source\PSoC5/cyPm.c **** { - 281:.\Generated_Source\PSoC5/cyPm.c **** /*********************************************************************** - 282:.\Generated_Source\PSoC5/cyPm.c **** * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait - 283:.\Generated_Source\PSoC5/cyPm.c **** * period uses FTW for period measurement. This could cause a problem - 284:.\Generated_Source\PSoC5/cyPm.c **** * if CTW/FTW is used as a wake up time in the low power modes APIs. - 285:.\Generated_Source\PSoC5/cyPm.c **** * So, the XTAL wait procedure is implemented with a software delay. - 286:.\Generated_Source\PSoC5/cyPm.c **** ***********************************************************************/ - 287:.\Generated_Source\PSoC5/cyPm.c **** - 288:.\Generated_Source\PSoC5/cyPm.c **** /* Enable XMHZ XTAL with no wait */ - 289:.\Generated_Source\PSoC5/cyPm.c **** (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); - 290:.\Generated_Source\PSoC5/cyPm.c **** - 291:.\Generated_Source\PSoC5/cyPm.c **** /* Read XERR bit to clear it */ - 292:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_FASTCLK_XMHZ_CSR_REG; - 293:.\Generated_Source\PSoC5/cyPm.c **** - 294:.\Generated_Source\PSoC5/cyPm.c **** /* Wait */ - 295:.\Generated_Source\PSoC5/cyPm.c **** for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) - 296:.\Generated_Source\PSoC5/cyPm.c **** { - 297:.\Generated_Source\PSoC5/cyPm.c **** /* Make a 200 microseconds delay */ - 298:.\Generated_Source\PSoC5/cyPm.c **** CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); - 299:.\Generated_Source\PSoC5/cyPm.c **** - 300:.\Generated_Source\PSoC5/cyPm.c **** /* High output indicates oscillator failure */ - 301:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) - 302:.\Generated_Source\PSoC5/cyPm.c **** { - 303:.\Generated_Source\PSoC5/cyPm.c **** status = CYRET_SUCCESS; - 304:.\Generated_Source\PSoC5/cyPm.c **** break; - 305:.\Generated_Source\PSoC5/cyPm.c **** } - 306:.\Generated_Source\PSoC5/cyPm.c **** } - 307:.\Generated_Source\PSoC5/cyPm.c **** - 308:.\Generated_Source\PSoC5/cyPm.c **** if(CYRET_TIMEOUT == status) - 309:.\Generated_Source\PSoC5/cyPm.c **** { - 310:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************* - 311:.\Generated_Source\PSoC5/cyPm.c **** * Process the situation when megahertz crystal is not ready. - 312:.\Generated_Source\PSoC5/cyPm.c **** * Time to stabialize value is crystal specific. - 313:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************/ - 314:.\Generated_Source\PSoC5/cyPm.c **** /* `#START_MHZ_ECO_TIMEOUT` */ - 315:.\Generated_Source\PSoC5/cyPm.c **** - 316:.\Generated_Source\PSoC5/cyPm.c **** /* `#END` */ - 317:.\Generated_Source\PSoC5/cyPm.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 7 - - - 318:.\Generated_Source\PSoC5/cyPm.c **** } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ - 319:.\Generated_Source\PSoC5/cyPm.c **** - 320:.\Generated_Source\PSoC5/cyPm.c **** - 321:.\Generated_Source\PSoC5/cyPm.c **** /* Temprorary set the maximum flash wait cycles */ - 322:.\Generated_Source\PSoC5/cyPm.c **** CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); - 323:.\Generated_Source\PSoC5/cyPm.c **** - 324:.\Generated_Source\PSoC5/cyPm.c **** /* The XTAL and DSI clocks are ready to be source for Master clock. */ - 325:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || - 326:.\Generated_Source\PSoC5/cyPm.c **** (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) - 327:.\Generated_Source\PSoC5/cyPm.c **** { - 328:.\Generated_Source\PSoC5/cyPm.c **** /* Restore Master clock's divider */ - 329:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) - 330:.\Generated_Source\PSoC5/cyPm.c **** { - 331:.\Generated_Source\PSoC5/cyPm.c **** /* Restore Master clock divider */ - 332:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); - 333:.\Generated_Source\PSoC5/cyPm.c **** } - 334:.\Generated_Source\PSoC5/cyPm.c **** - 335:.\Generated_Source\PSoC5/cyPm.c **** /* Restore Master clock source */ - 336:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); - 337:.\Generated_Source\PSoC5/cyPm.c **** } - 338:.\Generated_Source\PSoC5/cyPm.c **** - 339:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - restore IMO frequency */ - 340:.\Generated_Source\PSoC5/cyPm.c **** if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && - 341:.\Generated_Source\PSoC5/cyPm.c **** (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) - 342:.\Generated_Source\PSoC5/cyPm.c **** { - 343:.\Generated_Source\PSoC5/cyPm.c **** /* Restore IMO frequency (24 MHz) and trim it for USB */ - 344:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetFreq(CY_IMO_FREQ_USB); - 345:.\Generated_Source\PSoC5/cyPm.c **** } - 346:.\Generated_Source\PSoC5/cyPm.c **** else - 347:.\Generated_Source\PSoC5/cyPm.c **** { - 348:.\Generated_Source\PSoC5/cyPm.c **** /* Restore IMO frequency */ - 349:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); - 350:.\Generated_Source\PSoC5/cyPm.c **** - 351:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) - 352:.\Generated_Source\PSoC5/cyPm.c **** { - 353:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; - 354:.\Generated_Source\PSoC5/cyPm.c **** } - 355:.\Generated_Source\PSoC5/cyPm.c **** else - 356:.\Generated_Source\PSoC5/cyPm.c **** { - 357:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); - 358:.\Generated_Source\PSoC5/cyPm.c **** } - 359:.\Generated_Source\PSoC5/cyPm.c **** } - 360:.\Generated_Source\PSoC5/cyPm.c **** - 361:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - restore enable state if needed */ - 362:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && - 363:.\Generated_Source\PSoC5/cyPm.c **** (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) - 364:.\Generated_Source\PSoC5/cyPm.c **** { - 365:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - restore enabled state */ - 366:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); - 367:.\Generated_Source\PSoC5/cyPm.c **** } - 368:.\Generated_Source\PSoC5/cyPm.c **** - 369:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - restore disable state if needed */ - 370:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && - 371:.\Generated_Source\PSoC5/cyPm.c **** (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) - 372:.\Generated_Source\PSoC5/cyPm.c **** { - 373:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_Stop(); - 374:.\Generated_Source\PSoC5/cyPm.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 8 - - - 375:.\Generated_Source\PSoC5/cyPm.c **** - 376:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - restore IMOCLK source */ - 377:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetSource(cyPmClockBackup.imoClkSrc); - 378:.\Generated_Source\PSoC5/cyPm.c **** - 379:.\Generated_Source\PSoC5/cyPm.c **** /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ - 380:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.imo2x) - 381:.\Generated_Source\PSoC5/cyPm.c **** { - 382:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_EnableDoubler(); - 383:.\Generated_Source\PSoC5/cyPm.c **** } - 384:.\Generated_Source\PSoC5/cyPm.c **** - 385:.\Generated_Source\PSoC5/cyPm.c **** /* IMO - restore clk_imo source, if needed */ - 386:.\Generated_Source\PSoC5/cyPm.c **** if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) - 387:.\Generated_Source\PSoC5/cyPm.c **** { - 388:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | - 389:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkImoSrc; - 390:.\Generated_Source\PSoC5/cyPm.c **** } - 391:.\Generated_Source\PSoC5/cyPm.c **** - 392:.\Generated_Source\PSoC5/cyPm.c **** /* PLL restore state */ - 393:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) - 394:.\Generated_Source\PSoC5/cyPm.c **** { - 395:.\Generated_Source\PSoC5/cyPm.c **** /*********************************************************************** - 396:.\Generated_Source\PSoC5/cyPm.c **** * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW - 397:.\Generated_Source\PSoC5/cyPm.c **** * for period measurement. This could cause a problem if CTW/FTW is used - 398:.\Generated_Source\PSoC5/cyPm.c **** * as a wakeup time in the low power modes APIs. To omit this issue PLL - 399:.\Generated_Source\PSoC5/cyPm.c **** * wait procedure is implemented with a software delay. - 400:.\Generated_Source\PSoC5/cyPm.c **** ***********************************************************************/ - 401:.\Generated_Source\PSoC5/cyPm.c **** - 402:.\Generated_Source\PSoC5/cyPm.c **** /* Enable PLL */ - 403:.\Generated_Source\PSoC5/cyPm.c **** (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); - 404:.\Generated_Source\PSoC5/cyPm.c **** - 405:.\Generated_Source\PSoC5/cyPm.c **** /* Make a 250 us delay */ - 406:.\Generated_Source\PSoC5/cyPm.c **** CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ); - 407:.\Generated_Source\PSoC5/cyPm.c **** } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ - 408:.\Generated_Source\PSoC5/cyPm.c **** - 409:.\Generated_Source\PSoC5/cyPm.c **** - 410:.\Generated_Source\PSoC5/cyPm.c **** /* PLL and IMO is ready to be source for Master clock */ - 411:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || - 412:.\Generated_Source\PSoC5/cyPm.c **** (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) - 413:.\Generated_Source\PSoC5/cyPm.c **** { - 414:.\Generated_Source\PSoC5/cyPm.c **** /* Restore Master clock divider */ - 415:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) - 416:.\Generated_Source\PSoC5/cyPm.c **** { - 417:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); - 418:.\Generated_Source\PSoC5/cyPm.c **** } - 419:.\Generated_Source\PSoC5/cyPm.c **** - 420:.\Generated_Source\PSoC5/cyPm.c **** /* Restore Master clock source */ - 421:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); - 422:.\Generated_Source\PSoC5/cyPm.c **** } - 423:.\Generated_Source\PSoC5/cyPm.c **** - 424:.\Generated_Source\PSoC5/cyPm.c **** /* Bus clock - restore divider, if needed */ - 425:.\Generated_Source\PSoC5/cyPm.c **** clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); - 426:.\Generated_Source\PSoC5/cyPm.c **** clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; - 427:.\Generated_Source\PSoC5/cyPm.c **** if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) - 428:.\Generated_Source\PSoC5/cyPm.c **** { - 429:.\Generated_Source\PSoC5/cyPm.c **** CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); - 430:.\Generated_Source\PSoC5/cyPm.c **** } - 431:.\Generated_Source\PSoC5/cyPm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 9 - - - 432:.\Generated_Source\PSoC5/cyPm.c **** /* Restore flash wait cycles */ - 433:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | - 434:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.flashWaitCycles); - 435:.\Generated_Source\PSoC5/cyPm.c **** - 436:.\Generated_Source\PSoC5/cyPm.c **** /* Digital and analog clocks - restore state */ - 437:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; - 438:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; - 439:.\Generated_Source\PSoC5/cyPm.c **** } - 440:.\Generated_Source\PSoC5/cyPm.c **** - 441:.\Generated_Source\PSoC5/cyPm.c **** - 442:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* - 443:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmAltAct - 444:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** - 445:.\Generated_Source\PSoC5/cyPm.c **** * - 446:.\Generated_Source\PSoC5/cyPm.c **** * Summary: - 447:.\Generated_Source\PSoC5/cyPm.c **** * Puts the part into the Alternate Active (Standby) state. The Alternate Active - 448:.\Generated_Source\PSoC5/cyPm.c **** * state can allow for any of the capabilities of the device to be active, but - 449:.\Generated_Source\PSoC5/cyPm.c **** * the operation of this function is dependent on the CPU being disabled during - 450:.\Generated_Source\PSoC5/cyPm.c **** * the Alternate Active state. The configuration code and the component APIs - 451:.\Generated_Source\PSoC5/cyPm.c **** * will configure the template for the Alternate Active state to be the same as - 452:.\Generated_Source\PSoC5/cyPm.c **** * the Active state with the exception that the CPU will be disabled during - 453:.\Generated_Source\PSoC5/cyPm.c **** * Alternate Active. - 454:.\Generated_Source\PSoC5/cyPm.c **** * - 455:.\Generated_Source\PSoC5/cyPm.c **** * Note Before calling this function, you must manually configure the power mode - 456:.\Generated_Source\PSoC5/cyPm.c **** * of the source clocks for the timer that is used as the wakeup timer. - 457:.\Generated_Source\PSoC5/cyPm.c **** * - 458:.\Generated_Source\PSoC5/cyPm.c **** * PSoC 3: - 459:.\Generated_Source\PSoC5/cyPm.c **** * Before switching to Alternate Active, if a wakeupTime other than NONE is - 460:.\Generated_Source\PSoC5/cyPm.c **** * specified, then the appropriate timer state is configured as specified with - 461:.\Generated_Source\PSoC5/cyPm.c **** * the interrupt for that timer disabled. The wakeup source will be the - 462:.\Generated_Source\PSoC5/cyPm.c **** * combination of the values specified in the wakeupSource and any timer - 463:.\Generated_Source\PSoC5/cyPm.c **** * specified in the wakeupTime argument. Once the wakeup condition is - 464:.\Generated_Source\PSoC5/cyPm.c **** * satisfied, then all saved state is restored and the function returns in the - 465:.\Generated_Source\PSoC5/cyPm.c **** * Active state. - 466:.\Generated_Source\PSoC5/cyPm.c **** * - 467:.\Generated_Source\PSoC5/cyPm.c **** * Note that if the wakeupTime is made with a different value, the period before - 468:.\Generated_Source\PSoC5/cyPm.c **** * the wakeup occurs can be significantly shorter than the specified time. If - 469:.\Generated_Source\PSoC5/cyPm.c **** * the next call is made with the same wakeupTime value, then the wakeup will - 470:.\Generated_Source\PSoC5/cyPm.c **** * occur the specified period after the previous wakeup occurred. - 471:.\Generated_Source\PSoC5/cyPm.c **** * - 472:.\Generated_Source\PSoC5/cyPm.c **** * If a wakeupTime other than NONE is specified, then upon exit the state of the - 473:.\Generated_Source\PSoC5/cyPm.c **** * specified timer will be left as specified by wakeupTime with the timer - 474:.\Generated_Source\PSoC5/cyPm.c **** * enabled and the interrupt disabled. If the CTW, FTW or One PPS is already - 475:.\Generated_Source\PSoC5/cyPm.c **** * configured for wakeup, for example with the SleepTimer or RTC components, - 476:.\Generated_Source\PSoC5/cyPm.c **** * then specify NONE for the wakeupTime and include the appropriate source for - 477:.\Generated_Source\PSoC5/cyPm.c **** * wakeupSource. - 478:.\Generated_Source\PSoC5/cyPm.c **** * - 479:.\Generated_Source\PSoC5/cyPm.c **** * PSoC 5LP: - 480:.\Generated_Source\PSoC5/cyPm.c **** * This function is used to both enter the Alternate Active mode and halt the - 481:.\Generated_Source\PSoC5/cyPm.c **** * processor. For PSoC 3 these two actions must be paired together. With PSoC - 482:.\Generated_Source\PSoC5/cyPm.c **** * 5LP the processor can be halted independently with the __WFI() function from - 483:.\Generated_Source\PSoC5/cyPm.c **** * the CMSIS library that is included in Creator. This function should be used - 484:.\Generated_Source\PSoC5/cyPm.c **** * instead when the action required is just to halt the processor until an - 485:.\Generated_Source\PSoC5/cyPm.c **** * enabled interrupt occurs. - 486:.\Generated_Source\PSoC5/cyPm.c **** * - 487:.\Generated_Source\PSoC5/cyPm.c **** * The wakeupTime parameter is not used for this device. It must be set to zero - 488:.\Generated_Source\PSoC5/cyPm.c **** * (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 10 - - - 489:.\Generated_Source\PSoC5/cyPm.c **** * separate component: the CTW wakeup interval should be configured with the - 490:.\Generated_Source\PSoC5/cyPm.c **** * Sleep Timer component and one second interval should be configured with the - 491:.\Generated_Source\PSoC5/cyPm.c **** * RTC component. - 492:.\Generated_Source\PSoC5/cyPm.c **** * - 493:.\Generated_Source\PSoC5/cyPm.c **** * The wakeup behavior depends on wakeupSource parameter in the following - 494:.\Generated_Source\PSoC5/cyPm.c **** * manner: upon function execution the device will be switched from Active to - 495:.\Generated_Source\PSoC5/cyPm.c **** * Alternate Active mode and then the CPU will be halted. When an enabled wakeup - 496:.\Generated_Source\PSoC5/cyPm.c **** * event occurs the device will return to Active mode. Similarly when an - 497:.\Generated_Source\PSoC5/cyPm.c **** * enabled interrupt occurs the CPU will be started. These two actions will - 498:.\Generated_Source\PSoC5/cyPm.c **** * occur together provided that the event that occurs is an enabled wakeup - 499:.\Generated_Source\PSoC5/cyPm.c **** * source and also generates an interrupt. If just the wakeup event occurs then - 500:.\Generated_Source\PSoC5/cyPm.c **** * the device will be in Active mode, but the CPU will remain halted waiting for - 501:.\Generated_Source\PSoC5/cyPm.c **** * an interrupt. If an interrupt occurs from something other than a wakeup - 502:.\Generated_Source\PSoC5/cyPm.c **** * source, then the CPU will restart with the device in Alternate Active mode - 503:.\Generated_Source\PSoC5/cyPm.c **** * until a wakeup event occurs. - 504:.\Generated_Source\PSoC5/cyPm.c **** * - 505:.\Generated_Source\PSoC5/cyPm.c **** * For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is - 506:.\Generated_Source\PSoC5/cyPm.c **** * called and PICU interrupt occurs, the CPU will be started and device will be - 507:.\Generated_Source\PSoC5/cyPm.c **** * switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, - 508:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be - 509:.\Generated_Source\PSoC5/cyPm.c **** * started while device remains in Alternate Active mode. - 510:.\Generated_Source\PSoC5/cyPm.c **** * - 511:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: - 512:.\Generated_Source\PSoC5/cyPm.c **** * wakeupTime: Specifies a timer wakeup source and the frequency of that - 513:.\Generated_Source\PSoC5/cyPm.c **** * source. For PSoC 5LP this parameter is ignored. - 514:.\Generated_Source\PSoC5/cyPm.c **** * - 515:.\Generated_Source\PSoC5/cyPm.c **** * Define Time - 516:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_NONE None - 517:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second - 518:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms - 519:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms - 520:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms - 521:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms - 522:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms - 523:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms - 524:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms - 525:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms - 526:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms - 527:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms - 528:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms - 529:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms - 530:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms - 531:.\Generated_Source\PSoC5/cyPm.c **** * - 532:.\Generated_Source\PSoC5/cyPm.c **** * *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that - 533:.\Generated_Source\PSoC5/cyPm.c **** * specifies how many increments of 10 us to delay. - 534:.\Generated_Source\PSoC5/cyPm.c **** For PSoC 3 silicon the valid range of values is 1 to 256. - 535:.\Generated_Source\PSoC5/cyPm.c **** * - 536:.\Generated_Source\PSoC5/cyPm.c **** * wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if - 537:.\Generated_Source\PSoC5/cyPm.c **** * a wakeupTime has been specified the associated timer will be - 538:.\Generated_Source\PSoC5/cyPm.c **** * included as a wakeup source. - 539:.\Generated_Source\PSoC5/cyPm.c **** * - 540:.\Generated_Source\PSoC5/cyPm.c **** * Define Source - 541:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_NONE None - 542:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 - 543:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 - 544:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 - 545:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 11 - - - 546:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_INTERRUPT Interrupt - 547:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_PICU PICU - 548:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_I2C I2C - 549:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter - 550:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_FTW Fast Timewheel* - 551:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* - 552:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_CTW Central Timewheel** - 553:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_ONE_PPS One PPS** - 554:.\Generated_Source\PSoC5/cyPm.c **** * PM_ALT_ACT_SRC_LCD LCD - 555:.\Generated_Source\PSoC5/cyPm.c **** * - 556:.\Generated_Source\PSoC5/cyPm.c **** * *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. - 557:.\Generated_Source\PSoC5/cyPm.c **** * **Note: CTW and One PPS wakeup signals are in the same mask bit. - 558:.\Generated_Source\PSoC5/cyPm.c **** * - 559:.\Generated_Source\PSoC5/cyPm.c **** * When specifying a Comparator as the wakeupSource an instance specific define - 560:.\Generated_Source\PSoC5/cyPm.c **** * should be used that will track with the specific comparator that the instance - 561:.\Generated_Source\PSoC5/cyPm.c **** * is placed into. As an example, for a Comparator instance named MyComp the - 562:.\Generated_Source\PSoC5/cyPm.c **** * value to OR into the mask is: MyComp_ctComp__CMP_MASK. - 563:.\Generated_Source\PSoC5/cyPm.c **** * - 564:.\Generated_Source\PSoC5/cyPm.c **** * When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() - 565:.\Generated_Source\PSoC5/cyPm.c **** * function must be called upon wakeup with corresponding parameter. Please - 566:.\Generated_Source\PSoC5/cyPm.c **** * refer to the CyPmReadStatus() API in the System Reference Guide for more - 567:.\Generated_Source\PSoC5/cyPm.c **** * information. - 568:.\Generated_Source\PSoC5/cyPm.c **** * - 569:.\Generated_Source\PSoC5/cyPm.c **** * Return: - 570:.\Generated_Source\PSoC5/cyPm.c **** * None - 571:.\Generated_Source\PSoC5/cyPm.c **** * - 572:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: - 573:.\Generated_Source\PSoC5/cyPm.c **** * No - 574:.\Generated_Source\PSoC5/cyPm.c **** * - 575:.\Generated_Source\PSoC5/cyPm.c **** * Side Effects: - 576:.\Generated_Source\PSoC5/cyPm.c **** * If a wakeupTime other than NONE is specified, then upon exit the state of the - 577:.\Generated_Source\PSoC5/cyPm.c **** * specified timer will be left as specified by wakeupTime with the timer - 578:.\Generated_Source\PSoC5/cyPm.c **** * enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is - 579:.\Generated_Source\PSoC5/cyPm.c **** * used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time) - 580:.\Generated_Source\PSoC5/cyPm.c **** * will be left started. - 581:.\Generated_Source\PSoC5/cyPm.c **** * - 582:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - 583:.\Generated_Source\PSoC5/cyPm.c **** void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) - 584:.\Generated_Source\PSoC5/cyPm.c **** { - 585:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC5) - 586:.\Generated_Source\PSoC5/cyPm.c **** - 587:.\Generated_Source\PSoC5/cyPm.c **** /* Arguments expected to be 0 */ - 588:.\Generated_Source\PSoC5/cyPm.c **** CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); - 589:.\Generated_Source\PSoC5/cyPm.c **** - 590:.\Generated_Source\PSoC5/cyPm.c **** if(0u != wakeupTime) - 591:.\Generated_Source\PSoC5/cyPm.c **** { - 592:.\Generated_Source\PSoC5/cyPm.c **** /* To remove unreferenced local variable warning */ - 593:.\Generated_Source\PSoC5/cyPm.c **** } - 594:.\Generated_Source\PSoC5/cyPm.c **** - 595:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC5) */ - 596:.\Generated_Source\PSoC5/cyPm.c **** - 597:.\Generated_Source\PSoC5/cyPm.c **** - 598:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC3) - 599:.\Generated_Source\PSoC5/cyPm.c **** - 600:.\Generated_Source\PSoC5/cyPm.c **** /* FTW - save current and set new configuration */ - 601:.\Generated_Source\PSoC5/cyPm.c **** if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) - 602:.\Generated_Source\PSoC5/cyPm.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 12 - - - 603:.\Generated_Source\PSoC5/cyPm.c **** CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); - 604:.\Generated_Source\PSoC5/cyPm.c **** - 605:.\Generated_Source\PSoC5/cyPm.c **** /* Include associated timer to the wakeupSource */ - 606:.\Generated_Source\PSoC5/cyPm.c **** wakeupSource |= PM_ALT_ACT_SRC_FTW; - 607:.\Generated_Source\PSoC5/cyPm.c **** } - 608:.\Generated_Source\PSoC5/cyPm.c **** - 609:.\Generated_Source\PSoC5/cyPm.c **** /* CTW - save current and set new configuration */ - 610:.\Generated_Source\PSoC5/cyPm.c **** if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) - 611:.\Generated_Source\PSoC5/cyPm.c **** { - 612:.\Generated_Source\PSoC5/cyPm.c **** /* Save current CTW configuration and set new one */ - 613:.\Generated_Source\PSoC5/cyPm.c **** CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); - 614:.\Generated_Source\PSoC5/cyPm.c **** - 615:.\Generated_Source\PSoC5/cyPm.c **** /* Include associated timer to the wakeupSource */ - 616:.\Generated_Source\PSoC5/cyPm.c **** wakeupSource |= PM_ALT_ACT_SRC_CTW; - 617:.\Generated_Source\PSoC5/cyPm.c **** } - 618:.\Generated_Source\PSoC5/cyPm.c **** - 619:.\Generated_Source\PSoC5/cyPm.c **** /* 1PPS - save current and set new configuration */ - 620:.\Generated_Source\PSoC5/cyPm.c **** if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) - 621:.\Generated_Source\PSoC5/cyPm.c **** { - 622:.\Generated_Source\PSoC5/cyPm.c **** /* Save current 1PPS configuration and set new one */ - 623:.\Generated_Source\PSoC5/cyPm.c **** CyPmOppsSet(); - 624:.\Generated_Source\PSoC5/cyPm.c **** - 625:.\Generated_Source\PSoC5/cyPm.c **** /* Include associated timer to the wakeupSource */ - 626:.\Generated_Source\PSoC5/cyPm.c **** wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; - 627:.\Generated_Source\PSoC5/cyPm.c **** } - 628:.\Generated_Source\PSoC5/cyPm.c **** - 629:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC3) */ - 630:.\Generated_Source\PSoC5/cyPm.c **** - 631:.\Generated_Source\PSoC5/cyPm.c **** - 632:.\Generated_Source\PSoC5/cyPm.c **** /* Save and set new wake up configuration */ - 633:.\Generated_Source\PSoC5/cyPm.c **** - 634:.\Generated_Source\PSoC5/cyPm.c **** /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ - 635:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 636:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - 637:.\Generated_Source\PSoC5/cyPm.c **** - 638:.\Generated_Source\PSoC5/cyPm.c **** /* Comparators */ - 639:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 640:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - 641:.\Generated_Source\PSoC5/cyPm.c **** - 642:.\Generated_Source\PSoC5/cyPm.c **** /* LCD */ - 643:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - 644:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - 645:.\Generated_Source\PSoC5/cyPm.c **** - 646:.\Generated_Source\PSoC5/cyPm.c **** - 647:.\Generated_Source\PSoC5/cyPm.c **** /* Switch to the Alternate Active mode */ - 648:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_A - 649:.\Generated_Source\PSoC5/cyPm.c **** - 650:.\Generated_Source\PSoC5/cyPm.c **** /* Recommended readback. */ - 651:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_MODE_CSR_REG; - 652:.\Generated_Source\PSoC5/cyPm.c **** - 653:.\Generated_Source\PSoC5/cyPm.c **** /* Two recommended NOPs to get into the mode. */ - 654:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 655:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 656:.\Generated_Source\PSoC5/cyPm.c **** - 657:.\Generated_Source\PSoC5/cyPm.c **** /* Execute WFI instruction (for ARM-based devices only) */ - 658:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; - 659:.\Generated_Source\PSoC5/cyPm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 13 - - - 660:.\Generated_Source\PSoC5/cyPm.c **** /* Point of return from Alternate Active Mode */ - 661:.\Generated_Source\PSoC5/cyPm.c **** - 662:.\Generated_Source\PSoC5/cyPm.c **** /* Restore wake up configuration */ - 663:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; - 664:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - 665:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - 666:.\Generated_Source\PSoC5/cyPm.c **** } - 667:.\Generated_Source\PSoC5/cyPm.c **** - 668:.\Generated_Source\PSoC5/cyPm.c **** - 669:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* - 670:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmSleep - 671:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** - 672:.\Generated_Source\PSoC5/cyPm.c **** * - 673:.\Generated_Source\PSoC5/cyPm.c **** * Summary: - 674:.\Generated_Source\PSoC5/cyPm.c **** * Puts the part into the Sleep state. - 675:.\Generated_Source\PSoC5/cyPm.c **** * - 676:.\Generated_Source\PSoC5/cyPm.c **** * Note Before calling this function, you must manually configure the power - 677:.\Generated_Source\PSoC5/cyPm.c **** * mode of the source clocks for the timer that is used as wakeup timer. - 678:.\Generated_Source\PSoC5/cyPm.c **** * - 679:.\Generated_Source\PSoC5/cyPm.c **** * Note Before calling this function, you must prepare clock tree configuration - 680:.\Generated_Source\PSoC5/cyPm.c **** * for the low power mode by calling CyPmSaveClocks(). And restore clock - 681:.\Generated_Source\PSoC5/cyPm.c **** * configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See - 682:.\Generated_Source\PSoC5/cyPm.c **** * Power Management section, Clock Configuration subsection of the System - 683:.\Generated_Source\PSoC5/cyPm.c **** * Reference Guide for more information. - 684:.\Generated_Source\PSoC5/cyPm.c **** * - 685:.\Generated_Source\PSoC5/cyPm.c **** * PSoC 3: - 686:.\Generated_Source\PSoC5/cyPm.c **** * Before switching to Sleep, if a wakeupTime other than NONE is specified, - 687:.\Generated_Source\PSoC5/cyPm.c **** * then the appropriate timer state is configured as specified with the - 688:.\Generated_Source\PSoC5/cyPm.c **** * interrupt for that timer disabled. The wakeup source will be the combination - 689:.\Generated_Source\PSoC5/cyPm.c **** * of the values specified in the wakeupSource and any timer specified in the - 690:.\Generated_Source\PSoC5/cyPm.c **** * wakeupTime argument. Once the wakeup condition is satisfied, then all saved - 691:.\Generated_Source\PSoC5/cyPm.c **** * state is restored and the function returns in the Active state. - 692:.\Generated_Source\PSoC5/cyPm.c **** * - 693:.\Generated_Source\PSoC5/cyPm.c **** * Note that if the wakeupTime is made with a different value, the period before - 694:.\Generated_Source\PSoC5/cyPm.c **** * the wakeup occurs can be significantly shorter than the specified time. If - 695:.\Generated_Source\PSoC5/cyPm.c **** * the next call is made with the same wakeupTime value, then the wakeup will - 696:.\Generated_Source\PSoC5/cyPm.c **** * occur the specified period after the previous wakeup occurred. - 697:.\Generated_Source\PSoC5/cyPm.c **** * - 698:.\Generated_Source\PSoC5/cyPm.c **** * If a wakeupTime other than NONE is specified, then upon exit the state of the - 699:.\Generated_Source\PSoC5/cyPm.c **** * specified timer will be left as specified by wakeupTime with the timer - 700:.\Generated_Source\PSoC5/cyPm.c **** * enabled and the interrupt disabled. If the CTW or One PPS is already - 701:.\Generated_Source\PSoC5/cyPm.c **** * configured for wakeup, for example with the SleepTimer or RTC components, - 702:.\Generated_Source\PSoC5/cyPm.c **** * then specify NONE for the wakeupTime and include the appropriate source for - 703:.\Generated_Source\PSoC5/cyPm.c **** * wakeupSource. - 704:.\Generated_Source\PSoC5/cyPm.c **** * - 705:.\Generated_Source\PSoC5/cyPm.c **** * PSoC 5LP: - 706:.\Generated_Source\PSoC5/cyPm.c **** * The wakeupTime parameter is not used and the only NONE can be specified. - 707:.\Generated_Source\PSoC5/cyPm.c **** * The wakeup time must be configured with the component, SleepTimer for CTW - 708:.\Generated_Source\PSoC5/cyPm.c **** * intervals and RTC for 1PPS interval. The component must be configured to - 709:.\Generated_Source\PSoC5/cyPm.c **** * generate an interrrupt. - 710:.\Generated_Source\PSoC5/cyPm.c **** * - 711:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: - 712:.\Generated_Source\PSoC5/cyPm.c **** * wakeupTime: Specifies a timer wakeup source and the frequency of that - 713:.\Generated_Source\PSoC5/cyPm.c **** * source. For PSoC 5LP, this parameter is ignored. - 714:.\Generated_Source\PSoC5/cyPm.c **** * - 715:.\Generated_Source\PSoC5/cyPm.c **** * Define Time - 716:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_NONE None - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 14 - - - 717:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_ONE_PPS One PPS: 1 second - 718:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_2MS CTW: 2 ms - 719:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_4MS CTW: 4 ms - 720:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_8MS CTW: 8 ms - 721:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_16MS CTW: 16 ms - 722:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_32MS CTW: 32 ms - 723:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_64MS CTW: 64 ms - 724:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_128MS CTW: 128 ms - 725:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_256MS CTW: 256 ms - 726:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_512MS CTW: 512 ms - 727:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms - 728:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms - 729:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms - 730:.\Generated_Source\PSoC5/cyPm.c **** * - 731:.\Generated_Source\PSoC5/cyPm.c **** * wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if - 732:.\Generated_Source\PSoC5/cyPm.c **** * a wakeupTime has been specified the associated timer will be - 733:.\Generated_Source\PSoC5/cyPm.c **** * included as a wakeup source. - 734:.\Generated_Source\PSoC5/cyPm.c **** * - 735:.\Generated_Source\PSoC5/cyPm.c **** * Define Source - 736:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_NONE None - 737:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_COMPARATOR0 Comparator 0 - 738:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_COMPARATOR1 Comparator 1 - 739:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_COMPARATOR2 Comparator 2 - 740:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_COMPARATOR3 Comparator 3 - 741:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_PICU PICU - 742:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_I2C I2C - 743:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter - 744:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) - 745:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_CTW Central Timewheel* - 746:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_ONE_PPS One PPS* - 747:.\Generated_Source\PSoC5/cyPm.c **** * PM_SLEEP_SRC_LCD LCD - 748:.\Generated_Source\PSoC5/cyPm.c **** * - 749:.\Generated_Source\PSoC5/cyPm.c **** * *Note: CTW and One PPS wakeup signals are in the same mask bit. - 750:.\Generated_Source\PSoC5/cyPm.c **** * - 751:.\Generated_Source\PSoC5/cyPm.c **** * When specifying a Comparator as the wakeupSource an instance specific define - 752:.\Generated_Source\PSoC5/cyPm.c **** * should be used that will track with the specific comparator that the instance - 753:.\Generated_Source\PSoC5/cyPm.c **** * is placed into. As an example for a Comparator instance named MyComp the - 754:.\Generated_Source\PSoC5/cyPm.c **** * value to OR into the mask is: MyComp_ctComp__CMP_MASK. - 755:.\Generated_Source\PSoC5/cyPm.c **** * - 756:.\Generated_Source\PSoC5/cyPm.c **** * When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() - 757:.\Generated_Source\PSoC5/cyPm.c **** * function must be called upon wakeup with corresponding parameter. Please - 758:.\Generated_Source\PSoC5/cyPm.c **** * refer to the CyPmReadStatus() API in the System Reference Guide for more - 759:.\Generated_Source\PSoC5/cyPm.c **** * information. - 760:.\Generated_Source\PSoC5/cyPm.c **** * - 761:.\Generated_Source\PSoC5/cyPm.c **** * Return: - 762:.\Generated_Source\PSoC5/cyPm.c **** * None - 763:.\Generated_Source\PSoC5/cyPm.c **** * - 764:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: - 765:.\Generated_Source\PSoC5/cyPm.c **** * No - 766:.\Generated_Source\PSoC5/cyPm.c **** * - 767:.\Generated_Source\PSoC5/cyPm.c **** * Side Effects and Restrictions: - 768:.\Generated_Source\PSoC5/cyPm.c **** * If a wakeupTime other than NONE is specified, then upon exit the state of the - 769:.\Generated_Source\PSoC5/cyPm.c **** * specified timer will be left as specified by wakeupTime with the timer - 770:.\Generated_Source\PSoC5/cyPm.c **** * enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is - 771:.\Generated_Source\PSoC5/cyPm.c **** * used as wake up time) will be left started. - 772:.\Generated_Source\PSoC5/cyPm.c **** * - 773:.\Generated_Source\PSoC5/cyPm.c **** * The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 15 - - - 774:.\Generated_Source\PSoC5/cyPm.c **** * measure Hibernate/Sleep regulator settling time after a reset. The holdoff - 775:.\Generated_Source\PSoC5/cyPm.c **** * delay is measured using rising edges of the 1 kHz ILO. - 776:.\Generated_Source\PSoC5/cyPm.c **** * - 777:.\Generated_Source\PSoC5/cyPm.c **** * For PSoC 3 silicon hardware buzz should be disabled before entering a sleep - 778:.\Generated_Source\PSoC5/cyPm.c **** * power mode. It is disabled by PSoC Creator during startup. - 779:.\Generated_Source\PSoC5/cyPm.c **** * If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out - 780:.\Generated_Source\PSoC5/cyPm.c **** * detect (power supply supervising capabilities) are required in a design - 781:.\Generated_Source\PSoC5/cyPm.c **** * during sleep, use the Central Time Wheel (CTW) to periodically wake the - 782:.\Generated_Source\PSoC5/cyPm.c **** * device, perform software buzz, and refresh the supervisory services. If LVI, - 783:.\Generated_Source\PSoC5/cyPm.c **** * HVI, or Brown Out is not required, then use of the CTW is not required. - 784:.\Generated_Source\PSoC5/cyPm.c **** * Refer to the device errata for more information. - 785:.\Generated_Source\PSoC5/cyPm.c **** * - 786:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - 787:.\Generated_Source\PSoC5/cyPm.c **** void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) - 788:.\Generated_Source\PSoC5/cyPm.c **** { - 789:.\Generated_Source\PSoC5/cyPm.c **** uint8 interruptState; - 790:.\Generated_Source\PSoC5/cyPm.c **** - 791:.\Generated_Source\PSoC5/cyPm.c **** /* Save current global interrupt enable and disable it */ - 792:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); - 793:.\Generated_Source\PSoC5/cyPm.c **** - 794:.\Generated_Source\PSoC5/cyPm.c **** - 795:.\Generated_Source\PSoC5/cyPm.c **** /*********************************************************************** - 796:.\Generated_Source\PSoC5/cyPm.c **** * The Hibernate/Sleep regulator has a settling time after a reset. - 797:.\Generated_Source\PSoC5/cyPm.c **** * During this time, the system ignores requests to enter Sleep and - 798:.\Generated_Source\PSoC5/cyPm.c **** * Hibernate modes. The holdoff delay is measured using rising edges of - 799:.\Generated_Source\PSoC5/cyPm.c **** * the 1 kHz ILO. - 800:.\Generated_Source\PSoC5/cyPm.c **** ***********************************************************************/ - 801:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) - 802:.\Generated_Source\PSoC5/cyPm.c **** { - 803:.\Generated_Source\PSoC5/cyPm.c **** /* Disable hold off - no action on restore */ - 804:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; - 805:.\Generated_Source\PSoC5/cyPm.c **** } - 806:.\Generated_Source\PSoC5/cyPm.c **** else - 807:.\Generated_Source\PSoC5/cyPm.c **** { - 808:.\Generated_Source\PSoC5/cyPm.c **** /* Abort, device is not ready for low power mode entry */ - 809:.\Generated_Source\PSoC5/cyPm.c **** - 810:.\Generated_Source\PSoC5/cyPm.c **** /* Restore global interrupt enable state */ - 811:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); - 812:.\Generated_Source\PSoC5/cyPm.c **** - 813:.\Generated_Source\PSoC5/cyPm.c **** return; - 814:.\Generated_Source\PSoC5/cyPm.c **** } - 815:.\Generated_Source\PSoC5/cyPm.c **** - 816:.\Generated_Source\PSoC5/cyPm.c **** - 817:.\Generated_Source\PSoC5/cyPm.c **** /*********************************************************************** - 818:.\Generated_Source\PSoC5/cyPm.c **** * PSoC3 < TO6: - 819:.\Generated_Source\PSoC5/cyPm.c **** * - Hardware buzz must be disabled before sleep mode entry. - 820:.\Generated_Source\PSoC5/cyPm.c **** * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must - 821:.\Generated_Source\PSoC5/cyPm.c **** * be aslo disabled. - 822:.\Generated_Source\PSoC5/cyPm.c **** * - 823:.\Generated_Source\PSoC5/cyPm.c **** * PSoC3 >= TO6: - 824:.\Generated_Source\PSoC5/cyPm.c **** * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be - 825:.\Generated_Source\PSoC5/cyPm.c **** * enabled before sleep mode entry and restored on wakeup. - 826:.\Generated_Source\PSoC5/cyPm.c **** ***********************************************************************/ - 827:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC3) - 828:.\Generated_Source\PSoC5/cyPm.c **** - 829:.\Generated_Source\PSoC5/cyPm.c **** /* Silicon Revision ID is below TO6 */ - 830:.\Generated_Source\PSoC5/cyPm.c **** if(CYDEV_CHIP_REV_ACTUAL < 5u) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 16 - - - 831:.\Generated_Source\PSoC5/cyPm.c **** { - 832:.\Generated_Source\PSoC5/cyPm.c **** /* Hardware buzz expected to be disabled in Sleep mode */ - 833:.\Generated_Source\PSoC5/cyPm.c **** CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); - 834:.\Generated_Source\PSoC5/cyPm.c **** } - 835:.\Generated_Source\PSoC5/cyPm.c **** - 836:.\Generated_Source\PSoC5/cyPm.c **** - 837:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - 838:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - 839:.\Generated_Source\PSoC5/cyPm.c **** { - 840:.\Generated_Source\PSoC5/cyPm.c **** if(CYDEV_CHIP_REV_ACTUAL < 5u) - 841:.\Generated_Source\PSoC5/cyPm.c **** { - 842:.\Generated_Source\PSoC5/cyPm.c **** /* LVI/HVI requires hardware buzz to be enabled */ - 843:.\Generated_Source\PSoC5/cyPm.c **** CYASSERT(0u != 0u); - 844:.\Generated_Source\PSoC5/cyPm.c **** } - 845:.\Generated_Source\PSoC5/cyPm.c **** else - 846:.\Generated_Source\PSoC5/cyPm.c **** { - 847:.\Generated_Source\PSoC5/cyPm.c **** if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)) - 848:.\Generated_Source\PSoC5/cyPm.c **** { - 849:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.hardwareBuzz = CY_PM_DISABLED; - 850:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; - 851:.\Generated_Source\PSoC5/cyPm.c **** } - 852:.\Generated_Source\PSoC5/cyPm.c **** else - 853:.\Generated_Source\PSoC5/cyPm.c **** { - 854:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.hardwareBuzz = CY_PM_ENABLED; - 855:.\Generated_Source\PSoC5/cyPm.c **** } - 856:.\Generated_Source\PSoC5/cyPm.c **** } - 857:.\Generated_Source\PSoC5/cyPm.c **** } - 858:.\Generated_Source\PSoC5/cyPm.c **** - 859:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC3) */ - 860:.\Generated_Source\PSoC5/cyPm.c **** - 861:.\Generated_Source\PSoC5/cyPm.c **** - 862:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* - 863:.\Generated_Source\PSoC5/cyPm.c **** * For ARM-based devices, an interrupt is required for the CPU to wake up. The - 864:.\Generated_Source\PSoC5/cyPm.c **** * Power Management implementation assumes that wakeup time is configured with a - 865:.\Generated_Source\PSoC5/cyPm.c **** * separate component (component-based wakeup time configuration) for an - 866:.\Generated_Source\PSoC5/cyPm.c **** * interrupt to be issued on terminal count. For more information, refer to the - 867:.\Generated_Source\PSoC5/cyPm.c **** * Wakeup Time Configuration section of System Reference Guide. - 868:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - 869:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC5) - 870:.\Generated_Source\PSoC5/cyPm.c **** - 871:.\Generated_Source\PSoC5/cyPm.c **** /* Arguments expected to be 0 */ - 872:.\Generated_Source\PSoC5/cyPm.c **** CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); - 873:.\Generated_Source\PSoC5/cyPm.c **** - 874:.\Generated_Source\PSoC5/cyPm.c **** if(0u != wakeupTime) - 875:.\Generated_Source\PSoC5/cyPm.c **** { - 876:.\Generated_Source\PSoC5/cyPm.c **** /* To remove unreferenced local variable warning */ - 877:.\Generated_Source\PSoC5/cyPm.c **** } - 878:.\Generated_Source\PSoC5/cyPm.c **** - 879:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC5) */ - 880:.\Generated_Source\PSoC5/cyPm.c **** - 881:.\Generated_Source\PSoC5/cyPm.c **** - 882:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpSaveSet(); - 883:.\Generated_Source\PSoC5/cyPm.c **** - 884:.\Generated_Source\PSoC5/cyPm.c **** - 885:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC3) - 886:.\Generated_Source\PSoC5/cyPm.c **** - 887:.\Generated_Source\PSoC5/cyPm.c **** /* CTW - save current and set new configuration */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 17 - - - 888:.\Generated_Source\PSoC5/cyPm.c **** if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) - 889:.\Generated_Source\PSoC5/cyPm.c **** { - 890:.\Generated_Source\PSoC5/cyPm.c **** /* Save current and set new configuration of the CTW */ - 891:.\Generated_Source\PSoC5/cyPm.c **** CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); - 892:.\Generated_Source\PSoC5/cyPm.c **** - 893:.\Generated_Source\PSoC5/cyPm.c **** /* Include associated timer to the wakeupSource */ - 894:.\Generated_Source\PSoC5/cyPm.c **** wakeupSource |= PM_SLEEP_SRC_CTW; - 895:.\Generated_Source\PSoC5/cyPm.c **** } - 896:.\Generated_Source\PSoC5/cyPm.c **** - 897:.\Generated_Source\PSoC5/cyPm.c **** /* 1PPS - save current and set new configuration */ - 898:.\Generated_Source\PSoC5/cyPm.c **** if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) - 899:.\Generated_Source\PSoC5/cyPm.c **** { - 900:.\Generated_Source\PSoC5/cyPm.c **** /* Save current and set new configuration of the 1PPS */ - 901:.\Generated_Source\PSoC5/cyPm.c **** CyPmOppsSet(); - 902:.\Generated_Source\PSoC5/cyPm.c **** - 903:.\Generated_Source\PSoC5/cyPm.c **** /* Include associated timer to the wakeupSource */ - 904:.\Generated_Source\PSoC5/cyPm.c **** wakeupSource |= PM_SLEEP_SRC_ONE_PPS; - 905:.\Generated_Source\PSoC5/cyPm.c **** } - 906:.\Generated_Source\PSoC5/cyPm.c **** - 907:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC3) */ - 908:.\Generated_Source\PSoC5/cyPm.c **** - 909:.\Generated_Source\PSoC5/cyPm.c **** - 910:.\Generated_Source\PSoC5/cyPm.c **** /* Save and set new wake up configuration */ - 911:.\Generated_Source\PSoC5/cyPm.c **** - 912:.\Generated_Source\PSoC5/cyPm.c **** /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ - 913:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 914:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - 915:.\Generated_Source\PSoC5/cyPm.c **** - 916:.\Generated_Source\PSoC5/cyPm.c **** /* Comparators */ - 917:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 918:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - 919:.\Generated_Source\PSoC5/cyPm.c **** - 920:.\Generated_Source\PSoC5/cyPm.c **** /* LCD */ - 921:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - 922:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - 923:.\Generated_Source\PSoC5/cyPm.c **** - 924:.\Generated_Source\PSoC5/cyPm.c **** - 925:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************* - 926:.\Generated_Source\PSoC5/cyPm.c **** * Do not use merge region below unless any component datasheet - 927:.\Generated_Source\PSoC5/cyPm.c **** * suggest to do so. - 928:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************/ - 929:.\Generated_Source\PSoC5/cyPm.c **** /* `#START CY_PM_JUST_BEFORE_SLEEP` */ - 930:.\Generated_Source\PSoC5/cyPm.c **** - 931:.\Generated_Source\PSoC5/cyPm.c **** /* `#END` */ - 932:.\Generated_Source\PSoC5/cyPm.c **** - 933:.\Generated_Source\PSoC5/cyPm.c **** - 934:.\Generated_Source\PSoC5/cyPm.c **** /* Last moment IMO frequency change */ - 935:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) - 936:.\Generated_Source\PSoC5/cyPm.c **** { - 937:.\Generated_Source\PSoC5/cyPm.c **** /* IMO frequency is 12 MHz */ - 938:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; - 939:.\Generated_Source\PSoC5/cyPm.c **** } - 940:.\Generated_Source\PSoC5/cyPm.c **** else - 941:.\Generated_Source\PSoC5/cyPm.c **** { - 942:.\Generated_Source\PSoC5/cyPm.c **** /* IMO frequency is not 12 MHz */ - 943:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; - 944:.\Generated_Source\PSoC5/cyPm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 18 - - - 945:.\Generated_Source\PSoC5/cyPm.c **** /* Save IMO frequency */ - 946:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - 947:.\Generated_Source\PSoC5/cyPm.c **** - 948:.\Generated_Source\PSoC5/cyPm.c **** /* Set IMO frequency to 12 MHz */ - 949:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); - 950:.\Generated_Source\PSoC5/cyPm.c **** } - 951:.\Generated_Source\PSoC5/cyPm.c **** - 952:.\Generated_Source\PSoC5/cyPm.c **** /* Switch to the Sleep mode */ - 953:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_S - 954:.\Generated_Source\PSoC5/cyPm.c **** - 955:.\Generated_Source\PSoC5/cyPm.c **** /* Recommended readback. */ - 956:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_MODE_CSR_REG; - 957:.\Generated_Source\PSoC5/cyPm.c **** - 958:.\Generated_Source\PSoC5/cyPm.c **** /* Two recommended NOPs to get into the mode. */ - 959:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 960:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 961:.\Generated_Source\PSoC5/cyPm.c **** - 962:.\Generated_Source\PSoC5/cyPm.c **** /* Execute WFI instruction (for ARM-based devices only) */ - 963:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; - 964:.\Generated_Source\PSoC5/cyPm.c **** - 965:.\Generated_Source\PSoC5/cyPm.c **** /* Point of return from Sleep Mode */ - 966:.\Generated_Source\PSoC5/cyPm.c **** - 967:.\Generated_Source\PSoC5/cyPm.c **** /* Restore last moment IMO frequency change */ - 968:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) - 969:.\Generated_Source\PSoC5/cyPm.c **** { - 970:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ - 971:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq; - 972:.\Generated_Source\PSoC5/cyPm.c **** } - 973:.\Generated_Source\PSoC5/cyPm.c **** - 974:.\Generated_Source\PSoC5/cyPm.c **** - 975:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************* - 976:.\Generated_Source\PSoC5/cyPm.c **** * Do not use merge region below unless any component datasheet - 977:.\Generated_Source\PSoC5/cyPm.c **** * suggest to do so. - 978:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************/ - 979:.\Generated_Source\PSoC5/cyPm.c **** /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ - 980:.\Generated_Source\PSoC5/cyPm.c **** - 981:.\Generated_Source\PSoC5/cyPm.c **** /* `#END` */ - 982:.\Generated_Source\PSoC5/cyPm.c **** - 983:.\Generated_Source\PSoC5/cyPm.c **** - 984:.\Generated_Source\PSoC5/cyPm.c **** /* Restore hardware configuration */ - 985:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpRestore(); - 986:.\Generated_Source\PSoC5/cyPm.c **** - 987:.\Generated_Source\PSoC5/cyPm.c **** - 988:.\Generated_Source\PSoC5/cyPm.c **** /* Disable hardware buzz, if it was previously enabled */ - 989:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC3) - 990:.\Generated_Source\PSoC5/cyPm.c **** - 991:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - 992:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - 993:.\Generated_Source\PSoC5/cyPm.c **** { - 994:.\Generated_Source\PSoC5/cyPm.c **** if(CYDEV_CHIP_REV_ACTUAL >= 5u) - 995:.\Generated_Source\PSoC5/cyPm.c **** { - 996:.\Generated_Source\PSoC5/cyPm.c **** if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz) - 997:.\Generated_Source\PSoC5/cyPm.c **** { - 998:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ); - 999:.\Generated_Source\PSoC5/cyPm.c **** } -1000:.\Generated_Source\PSoC5/cyPm.c **** } -1001:.\Generated_Source\PSoC5/cyPm.c **** } - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 19 - - -1002:.\Generated_Source\PSoC5/cyPm.c **** -1003:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC3) */ -1004:.\Generated_Source\PSoC5/cyPm.c **** -1005:.\Generated_Source\PSoC5/cyPm.c **** -1006:.\Generated_Source\PSoC5/cyPm.c **** /* Restore current wake up configuration */ -1007:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; -1008:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; -1009:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; -1010:.\Generated_Source\PSoC5/cyPm.c **** -1011:.\Generated_Source\PSoC5/cyPm.c **** /* Restore global interrupt enable state */ -1012:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); -1013:.\Generated_Source\PSoC5/cyPm.c **** } -1014:.\Generated_Source\PSoC5/cyPm.c **** -1015:.\Generated_Source\PSoC5/cyPm.c **** -1016:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1017:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHibernate -1018:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1019:.\Generated_Source\PSoC5/cyPm.c **** * -1020:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1021:.\Generated_Source\PSoC5/cyPm.c **** * Puts the part into the Hibernate state. -1022:.\Generated_Source\PSoC5/cyPm.c **** * -1023:.\Generated_Source\PSoC5/cyPm.c **** * PSoC 3 and PSoC 5LP: -1024:.\Generated_Source\PSoC5/cyPm.c **** * Before switching to Hibernate, the current status of the PICU wakeup source -1025:.\Generated_Source\PSoC5/cyPm.c **** * bit is saved and then set. This configures the device to wake up from the -1026:.\Generated_Source\PSoC5/cyPm.c **** * PICU. Make sure you have at least one pin configured to generate a PICU -1027:.\Generated_Source\PSoC5/cyPm.c **** * interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls -1028:.\Generated_Source\PSoC5/cyPm.c **** * the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." -1029:.\Generated_Source\PSoC5/cyPm.c **** * In the Pins component datasheet, this register is referred to as the IRQ -1030:.\Generated_Source\PSoC5/cyPm.c **** * option. Once the wakeup occurs, the PICU wakeup source bit is restored and -1031:.\Generated_Source\PSoC5/cyPm.c **** * the PSoC returns to the Active state. -1032:.\Generated_Source\PSoC5/cyPm.c **** * -1033:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1034:.\Generated_Source\PSoC5/cyPm.c **** * None -1035:.\Generated_Source\PSoC5/cyPm.c **** * -1036:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1037:.\Generated_Source\PSoC5/cyPm.c **** * None -1038:.\Generated_Source\PSoC5/cyPm.c **** * -1039:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: -1040:.\Generated_Source\PSoC5/cyPm.c **** * No -1041:.\Generated_Source\PSoC5/cyPm.c **** * -1042:.\Generated_Source\PSoC5/cyPm.c **** * Side Effects: -1043:.\Generated_Source\PSoC5/cyPm.c **** * Applications must wait 20 us before re-entering hibernate or sleep after -1044:.\Generated_Source\PSoC5/cyPm.c **** * waking up from hibernate. The 20 us allows the sleep regulator time to -1045:.\Generated_Source\PSoC5/cyPm.c **** * stabilize before the next hibernate / sleep event occurs. The 20 us -1046:.\Generated_Source\PSoC5/cyPm.c **** * requirement begins when the device wakes up. There is no hardware check that -1047:.\Generated_Source\PSoC5/cyPm.c **** * this requirement is met. The specified delay should be done on ISR entry. -1048:.\Generated_Source\PSoC5/cyPm.c **** * -1049:.\Generated_Source\PSoC5/cyPm.c **** * After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is -1050:.\Generated_Source\PSoC5/cyPm.c **** * instance name of the Pins component) function must be called to clear the -1051:.\Generated_Source\PSoC5/cyPm.c **** * latched pin events to allow proper Hibernate mode entry andd to enable -1052:.\Generated_Source\PSoC5/cyPm.c **** * detection of future events. -1053:.\Generated_Source\PSoC5/cyPm.c **** * -1054:.\Generated_Source\PSoC5/cyPm.c **** * The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to -1055:.\Generated_Source\PSoC5/cyPm.c **** * measure Hibernate/Sleep regulator settling time after a reset. The holdoff -1056:.\Generated_Source\PSoC5/cyPm.c **** * delay is measured using rising edges of the 1 kHz ILO. -1057:.\Generated_Source\PSoC5/cyPm.c **** * -1058:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 20 - - -1059:.\Generated_Source\PSoC5/cyPm.c **** void CyPmHibernate(void) -1060:.\Generated_Source\PSoC5/cyPm.c **** { -1061:.\Generated_Source\PSoC5/cyPm.c **** uint8 interruptState; -1062:.\Generated_Source\PSoC5/cyPm.c **** -1063:.\Generated_Source\PSoC5/cyPm.c **** /* Save current global interrupt enable and disable it */ -1064:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); -1065:.\Generated_Source\PSoC5/cyPm.c **** -1066:.\Generated_Source\PSoC5/cyPm.c **** /*********************************************************************** -1067:.\Generated_Source\PSoC5/cyPm.c **** * The Hibernate/Sleep regulator has a settling time after a reset. -1068:.\Generated_Source\PSoC5/cyPm.c **** * During this time, the system ignores requests to enter Sleep and -1069:.\Generated_Source\PSoC5/cyPm.c **** * Hibernate modes. The holdoff delay is measured using rising edges of -1070:.\Generated_Source\PSoC5/cyPm.c **** * the 1 kHz ILO. -1071:.\Generated_Source\PSoC5/cyPm.c **** ***********************************************************************/ -1072:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) -1073:.\Generated_Source\PSoC5/cyPm.c **** { -1074:.\Generated_Source\PSoC5/cyPm.c **** /* Disable hold off - no action on restore */ -1075:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; -1076:.\Generated_Source\PSoC5/cyPm.c **** } -1077:.\Generated_Source\PSoC5/cyPm.c **** else -1078:.\Generated_Source\PSoC5/cyPm.c **** { -1079:.\Generated_Source\PSoC5/cyPm.c **** /* Abort, device is not ready for low power mode entry */ -1080:.\Generated_Source\PSoC5/cyPm.c **** -1081:.\Generated_Source\PSoC5/cyPm.c **** /* Restore global interrupt enable state */ -1082:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); -1083:.\Generated_Source\PSoC5/cyPm.c **** -1084:.\Generated_Source\PSoC5/cyPm.c **** return; -1085:.\Generated_Source\PSoC5/cyPm.c **** } -1086:.\Generated_Source\PSoC5/cyPm.c **** -1087:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSaveSet(); -1088:.\Generated_Source\PSoC5/cyPm.c **** -1089:.\Generated_Source\PSoC5/cyPm.c **** -1090:.\Generated_Source\PSoC5/cyPm.c **** /* Save and enable only wakeup on PICU */ -1091:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; -1092:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; -1093:.\Generated_Source\PSoC5/cyPm.c **** -1094:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; -1095:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = 0x00u; -1096:.\Generated_Source\PSoC5/cyPm.c **** -1097:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; -1098:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = 0x00u; -1099:.\Generated_Source\PSoC5/cyPm.c **** -1100:.\Generated_Source\PSoC5/cyPm.c **** -1101:.\Generated_Source\PSoC5/cyPm.c **** /* Last moment IMO frequency change */ -1102:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) -1103:.\Generated_Source\PSoC5/cyPm.c **** { -1104:.\Generated_Source\PSoC5/cyPm.c **** /* IMO frequency is 12 MHz */ -1105:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; -1106:.\Generated_Source\PSoC5/cyPm.c **** } -1107:.\Generated_Source\PSoC5/cyPm.c **** else -1108:.\Generated_Source\PSoC5/cyPm.c **** { -1109:.\Generated_Source\PSoC5/cyPm.c **** /* IMO frequency is not 12 MHz */ -1110:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; -1111:.\Generated_Source\PSoC5/cyPm.c **** -1112:.\Generated_Source\PSoC5/cyPm.c **** /* Save IMO frequency */ -1113:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; -1114:.\Generated_Source\PSoC5/cyPm.c **** -1115:.\Generated_Source\PSoC5/cyPm.c **** /* Set IMO frequency to 12 MHz */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 21 - - -1116:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); -1117:.\Generated_Source\PSoC5/cyPm.c **** } -1118:.\Generated_Source\PSoC5/cyPm.c **** -1119:.\Generated_Source\PSoC5/cyPm.c **** -1120:.\Generated_Source\PSoC5/cyPm.c **** /* Switch to Hibernate Mode */ -1121:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_H -1122:.\Generated_Source\PSoC5/cyPm.c **** -1123:.\Generated_Source\PSoC5/cyPm.c **** /* Recommended readback. */ -1124:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_MODE_CSR_REG; -1125:.\Generated_Source\PSoC5/cyPm.c **** -1126:.\Generated_Source\PSoC5/cyPm.c **** /* Two recommended NOPs to get into the mode. */ -1127:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; -1128:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; -1129:.\Generated_Source\PSoC5/cyPm.c **** -1130:.\Generated_Source\PSoC5/cyPm.c **** /* Execute WFI instruction (for ARM-based devices only) */ -1131:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; -1132:.\Generated_Source\PSoC5/cyPm.c **** -1133:.\Generated_Source\PSoC5/cyPm.c **** -1134:.\Generated_Source\PSoC5/cyPm.c **** /* Point of return from Hibernate mode */ -1135:.\Generated_Source\PSoC5/cyPm.c **** -1136:.\Generated_Source\PSoC5/cyPm.c **** -1137:.\Generated_Source\PSoC5/cyPm.c **** /* Restore last moment IMO frequency change */ -1138:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) -1139:.\Generated_Source\PSoC5/cyPm.c **** { -1140:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ -1141:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq; -1142:.\Generated_Source\PSoC5/cyPm.c **** } -1143:.\Generated_Source\PSoC5/cyPm.c **** -1144:.\Generated_Source\PSoC5/cyPm.c **** -1145:.\Generated_Source\PSoC5/cyPm.c **** /* Restore device for proper Hibernate mode exit*/ -1146:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibRestore(); -1147:.\Generated_Source\PSoC5/cyPm.c **** -1148:.\Generated_Source\PSoC5/cyPm.c **** /* Restore current wake up configuration */ -1149:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; -1150:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; -1151:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; -1152:.\Generated_Source\PSoC5/cyPm.c **** -1153:.\Generated_Source\PSoC5/cyPm.c **** /* Restore global interrupt enable state */ -1154:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); -1155:.\Generated_Source\PSoC5/cyPm.c **** } -1156:.\Generated_Source\PSoC5/cyPm.c **** -1157:.\Generated_Source\PSoC5/cyPm.c **** -1158:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1159:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmReadStatus -1160:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1161:.\Generated_Source\PSoC5/cyPm.c **** * -1162:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1163:.\Generated_Source\PSoC5/cyPm.c **** * Manages the Power Manager Interrupt Status Register. This register has the -1164:.\Generated_Source\PSoC5/cyPm.c **** * interrupt status for the one pulse per second, central timewheel and fast -1165:.\Generated_Source\PSoC5/cyPm.c **** * timewheel timers. This hardware register clears on read. To allow for only -1166:.\Generated_Source\PSoC5/cyPm.c **** * clearing the bits of interest and preserving the other bits, this function -1167:.\Generated_Source\PSoC5/cyPm.c **** * uses a shadow register that retains the state. This function reads the -1168:.\Generated_Source\PSoC5/cyPm.c **** * status register and ORs that value with the shadow register. That is the -1169:.\Generated_Source\PSoC5/cyPm.c **** * value that is returned. Then the bits in the mask that are set are cleared -1170:.\Generated_Source\PSoC5/cyPm.c **** * from this value and written back to the shadow register. -1171:.\Generated_Source\PSoC5/cyPm.c **** * -1172:.\Generated_Source\PSoC5/cyPm.c **** * Note You must call this function within 1 ms (1 clock cycle of the ILO) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 22 - - -1173:.\Generated_Source\PSoC5/cyPm.c **** * after a CTW event has occurred. -1174:.\Generated_Source\PSoC5/cyPm.c **** * -1175:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1176:.\Generated_Source\PSoC5/cyPm.c **** * mask: Bits in the shadow register to clear. -1177:.\Generated_Source\PSoC5/cyPm.c **** * -1178:.\Generated_Source\PSoC5/cyPm.c **** * Define Source -1179:.\Generated_Source\PSoC5/cyPm.c **** * CY_PM_FTW_INT Fast Timewheel -1180:.\Generated_Source\PSoC5/cyPm.c **** * CY_PM_CTW_INT Central Timewheel -1181:.\Generated_Source\PSoC5/cyPm.c **** * CY_PM_ONEPPS_INT One Pulse Per Second -1182:.\Generated_Source\PSoC5/cyPm.c **** * -1183:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1184:.\Generated_Source\PSoC5/cyPm.c **** * Status. Same bits values as the mask parameter. -1185:.\Generated_Source\PSoC5/cyPm.c **** * -1186:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1187:.\Generated_Source\PSoC5/cyPm.c **** uint8 CyPmReadStatus(uint8 mask) -1188:.\Generated_Source\PSoC5/cyPm.c **** { -1189:.\Generated_Source\PSoC5/cyPm.c **** static uint8 interruptStatus; -1190:.\Generated_Source\PSoC5/cyPm.c **** uint8 interruptState; -1191:.\Generated_Source\PSoC5/cyPm.c **** uint8 tmpStatus; -1192:.\Generated_Source\PSoC5/cyPm.c **** -1193:.\Generated_Source\PSoC5/cyPm.c **** /* Enter critical section */ -1194:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); -1195:.\Generated_Source\PSoC5/cyPm.c **** -1196:.\Generated_Source\PSoC5/cyPm.c **** /* Save value of the register, copy it and clear desired bit */ -1197:.\Generated_Source\PSoC5/cyPm.c **** interruptStatus |= CY_PM_INT_SR_REG; -1198:.\Generated_Source\PSoC5/cyPm.c **** tmpStatus = interruptStatus; -1199:.\Generated_Source\PSoC5/cyPm.c **** interruptStatus &= ((uint8)(~mask)); -1200:.\Generated_Source\PSoC5/cyPm.c **** -1201:.\Generated_Source\PSoC5/cyPm.c **** /* Exit critical section */ -1202:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); -1203:.\Generated_Source\PSoC5/cyPm.c **** -1204:.\Generated_Source\PSoC5/cyPm.c **** return(tmpStatus); -1205:.\Generated_Source\PSoC5/cyPm.c **** } -1206:.\Generated_Source\PSoC5/cyPm.c **** -1207:.\Generated_Source\PSoC5/cyPm.c **** -1208:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1209:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHibSaveSet -1210:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1211:.\Generated_Source\PSoC5/cyPm.c **** * -1212:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1213:.\Generated_Source\PSoC5/cyPm.c **** * Prepare device for proper Hibernate low power mode entry: -1214:.\Generated_Source\PSoC5/cyPm.c **** * - Disables I2C backup regulator -1215:.\Generated_Source\PSoC5/cyPm.c **** * - Saves ILO power down mode state and enable it -1216:.\Generated_Source\PSoC5/cyPm.c **** * - Saves state of 1 kHz and 100 kHz ILO and disable them -1217:.\Generated_Source\PSoC5/cyPm.c **** * - Disables sleep regulator and shorts vccd to vpwrsleep -1218:.\Generated_Source\PSoC5/cyPm.c **** * - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() -1219:.\Generated_Source\PSoC5/cyPm.c **** * - CyPmHibSlpSaveSet() function is called -1220:.\Generated_Source\PSoC5/cyPm.c **** * -1221:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1222:.\Generated_Source\PSoC5/cyPm.c **** * None -1223:.\Generated_Source\PSoC5/cyPm.c **** * -1224:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1225:.\Generated_Source\PSoC5/cyPm.c **** * None -1226:.\Generated_Source\PSoC5/cyPm.c **** * -1227:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: -1228:.\Generated_Source\PSoC5/cyPm.c **** * No -1229:.\Generated_Source\PSoC5/cyPm.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 23 - - -1230:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1231:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibSaveSet(void) -1232:.\Generated_Source\PSoC5/cyPm.c **** { -1233:.\Generated_Source\PSoC5/cyPm.c **** /* I2C backup reg must be off when the sleep regulator is unavailable */ -1234:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) -1235:.\Generated_Source\PSoC5/cyPm.c **** { -1236:.\Generated_Source\PSoC5/cyPm.c **** /*********************************************************************** -1237:.\Generated_Source\PSoC5/cyPm.c **** * If I2C backup regulator is enabled, all the fixed-function registers -1238:.\Generated_Source\PSoC5/cyPm.c **** * store their values while device is in low power mode, otherwise their -1239:.\Generated_Source\PSoC5/cyPm.c **** * configuration is lost. The I2C API makes a decision to restore or not -1240:.\Generated_Source\PSoC5/cyPm.c **** * to restore I2C registers based on this. If this regulator will be -1241:.\Generated_Source\PSoC5/cyPm.c **** * disabled and then enabled, I2C API will suppose that I2C block -1242:.\Generated_Source\PSoC5/cyPm.c **** * registers preserved their values, while this is not true. So, the -1243:.\Generated_Source\PSoC5/cyPm.c **** * backup regulator is disabled. The I2C sleep APIs is responsible for -1244:.\Generated_Source\PSoC5/cyPm.c **** * restoration. -1245:.\Generated_Source\PSoC5/cyPm.c **** ***********************************************************************/ -1246:.\Generated_Source\PSoC5/cyPm.c **** -1247:.\Generated_Source\PSoC5/cyPm.c **** /* Disable I2C backup register */ -1248:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); -1249:.\Generated_Source\PSoC5/cyPm.c **** } -1250:.\Generated_Source\PSoC5/cyPm.c **** -1251:.\Generated_Source\PSoC5/cyPm.c **** -1252:.\Generated_Source\PSoC5/cyPm.c **** /* Save current ILO power mode and ensure low power mode */ -1253:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); -1254:.\Generated_Source\PSoC5/cyPm.c **** -1255:.\Generated_Source\PSoC5/cyPm.c **** /* Save current 1kHz ILO enable state. Disabled automatically. */ -1256:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? -1257:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_DISABLED : CY_PM_ENABLED; -1258:.\Generated_Source\PSoC5/cyPm.c **** -1259:.\Generated_Source\PSoC5/cyPm.c **** /* Save current 100kHz ILO enable state. Disabled automatically. */ -1260:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? -1261:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_DISABLED : CY_PM_ENABLED; -1262:.\Generated_Source\PSoC5/cyPm.c **** -1263:.\Generated_Source\PSoC5/cyPm.c **** -1264:.\Generated_Source\PSoC5/cyPm.c **** /* Disable the sleep regulator and shorts vccd to vpwrsleep */ -1265:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) -1266:.\Generated_Source\PSoC5/cyPm.c **** { -1267:.\Generated_Source\PSoC5/cyPm.c **** /* Save current bypass state */ -1268:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.slpTrBypass = CY_PM_DISABLED; -1269:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; -1270:.\Generated_Source\PSoC5/cyPm.c **** } -1271:.\Generated_Source\PSoC5/cyPm.c **** else -1272:.\Generated_Source\PSoC5/cyPm.c **** { -1273:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.slpTrBypass = CY_PM_ENABLED; -1274:.\Generated_Source\PSoC5/cyPm.c **** } -1275:.\Generated_Source\PSoC5/cyPm.c **** -1276:.\Generated_Source\PSoC5/cyPm.c **** /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ -1277:.\Generated_Source\PSoC5/cyPm.c **** -1278:.\Generated_Source\PSoC5/cyPm.c **** -1279:.\Generated_Source\PSoC5/cyPm.c **** /*************************************************************************** -1280:.\Generated_Source\PSoC5/cyPm.c **** * LVI/HVI must be disabled in Hibernate -1281:.\Generated_Source\PSoC5/cyPm.c **** ***************************************************************************/ -1282:.\Generated_Source\PSoC5/cyPm.c **** -1283:.\Generated_Source\PSoC5/cyPm.c **** /* Save LVI/HVI configuration and disable them */ -1284:.\Generated_Source\PSoC5/cyPm.c **** CyPmHviLviSaveDisable(); -1285:.\Generated_Source\PSoC5/cyPm.c **** -1286:.\Generated_Source\PSoC5/cyPm.c **** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 24 - - -1287:.\Generated_Source\PSoC5/cyPm.c **** /* Make the same preparations for Hibernate and Sleep modes */ -1288:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpSaveSet(); -1289:.\Generated_Source\PSoC5/cyPm.c **** -1290:.\Generated_Source\PSoC5/cyPm.c **** -1291:.\Generated_Source\PSoC5/cyPm.c **** /*************************************************************************** -1292:.\Generated_Source\PSoC5/cyPm.c **** * Save and set power mode wakeup trim registers -1293:.\Generated_Source\PSoC5/cyPm.c **** ***************************************************************************/ -1294:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; -1295:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; -1296:.\Generated_Source\PSoC5/cyPm.c **** -1297:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; -1298:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; -1299:.\Generated_Source\PSoC5/cyPm.c **** } -1300:.\Generated_Source\PSoC5/cyPm.c **** -1301:.\Generated_Source\PSoC5/cyPm.c **** -1302:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1303:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHibRestore -1304:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1305:.\Generated_Source\PSoC5/cyPm.c **** * -1306:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1307:.\Generated_Source\PSoC5/cyPm.c **** * Restore device for proper Hibernate mode exit: -1308:.\Generated_Source\PSoC5/cyPm.c **** * - Restore LVI/HVI configuration - call CyPmHviLviRestore() -1309:.\Generated_Source\PSoC5/cyPm.c **** * - CyPmHibSlpSaveRestore() function is called -1310:.\Generated_Source\PSoC5/cyPm.c **** * - Restores ILO power down mode state and enable it -1311:.\Generated_Source\PSoC5/cyPm.c **** * - Restores state of 1 kHz and 100 kHz ILO and disable them -1312:.\Generated_Source\PSoC5/cyPm.c **** * - Restores sleep regulator settings -1313:.\Generated_Source\PSoC5/cyPm.c **** * -1314:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1315:.\Generated_Source\PSoC5/cyPm.c **** * None -1316:.\Generated_Source\PSoC5/cyPm.c **** * -1317:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1318:.\Generated_Source\PSoC5/cyPm.c **** * None -1319:.\Generated_Source\PSoC5/cyPm.c **** * -1320:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1321:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibRestore(void) -1322:.\Generated_Source\PSoC5/cyPm.c **** { -1323:.\Generated_Source\PSoC5/cyPm.c **** /* Restore LVI/HVI configuration */ -1324:.\Generated_Source\PSoC5/cyPm.c **** CyPmHviLviRestore(); -1325:.\Generated_Source\PSoC5/cyPm.c **** -1326:.\Generated_Source\PSoC5/cyPm.c **** /* Restore the same configuration for Hibernate and Sleep modes */ -1327:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpRestore(); -1328:.\Generated_Source\PSoC5/cyPm.c **** -1329:.\Generated_Source\PSoC5/cyPm.c **** /* Restore 1kHz ILO enable state */ -1330:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) -1331:.\Generated_Source\PSoC5/cyPm.c **** { -1332:.\Generated_Source\PSoC5/cyPm.c **** /* Enable 1kHz ILO */ -1333:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start1K(); -1334:.\Generated_Source\PSoC5/cyPm.c **** } -1335:.\Generated_Source\PSoC5/cyPm.c **** -1336:.\Generated_Source\PSoC5/cyPm.c **** /* Restore 100kHz ILO enable state */ -1337:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) -1338:.\Generated_Source\PSoC5/cyPm.c **** { -1339:.\Generated_Source\PSoC5/cyPm.c **** /* Enable 100kHz ILO */ -1340:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start100K(); -1341:.\Generated_Source\PSoC5/cyPm.c **** } -1342:.\Generated_Source\PSoC5/cyPm.c **** -1343:.\Generated_Source\PSoC5/cyPm.c **** /* Restore ILO power mode */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 25 - - -1344:.\Generated_Source\PSoC5/cyPm.c **** (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); -1345:.\Generated_Source\PSoC5/cyPm.c **** -1346:.\Generated_Source\PSoC5/cyPm.c **** -1347:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) -1348:.\Generated_Source\PSoC5/cyPm.c **** { -1349:.\Generated_Source\PSoC5/cyPm.c **** /* Enable the sleep regulator */ -1350:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); -1351:.\Generated_Source\PSoC5/cyPm.c **** } -1352:.\Generated_Source\PSoC5/cyPm.c **** -1353:.\Generated_Source\PSoC5/cyPm.c **** -1354:.\Generated_Source\PSoC5/cyPm.c **** /*************************************************************************** -1355:.\Generated_Source\PSoC5/cyPm.c **** * Restore power mode wakeup trim registers -1356:.\Generated_Source\PSoC5/cyPm.c **** ***************************************************************************/ -1357:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; -1358:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; -1359:.\Generated_Source\PSoC5/cyPm.c **** } -1360:.\Generated_Source\PSoC5/cyPm.c **** -1361:.\Generated_Source\PSoC5/cyPm.c **** -1362:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1363:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmCtwSetInterval -1364:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1365:.\Generated_Source\PSoC5/cyPm.c **** * -1366:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1367:.\Generated_Source\PSoC5/cyPm.c **** * Performs CTW configuration: -1368:.\Generated_Source\PSoC5/cyPm.c **** * - Disables CTW interrupt -1369:.\Generated_Source\PSoC5/cyPm.c **** * - Enables 1 kHz ILO -1370:.\Generated_Source\PSoC5/cyPm.c **** * - Sets new CTW interval -1371:.\Generated_Source\PSoC5/cyPm.c **** * -1372:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1373:.\Generated_Source\PSoC5/cyPm.c **** * ctwInterval: the CTW interval to be set. -1374:.\Generated_Source\PSoC5/cyPm.c **** * -1375:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1376:.\Generated_Source\PSoC5/cyPm.c **** * None -1377:.\Generated_Source\PSoC5/cyPm.c **** * -1378:.\Generated_Source\PSoC5/cyPm.c **** * Side Effects: -1379:.\Generated_Source\PSoC5/cyPm.c **** * Enables ILO 1 KHz clock and leaves it enabled. -1380:.\Generated_Source\PSoC5/cyPm.c **** * -1381:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1382:.\Generated_Source\PSoC5/cyPm.c **** void CyPmCtwSetInterval(uint8 ctwInterval) -1383:.\Generated_Source\PSoC5/cyPm.c **** { -1384:.\Generated_Source\PSoC5/cyPm.c **** /* Disable CTW interrupt enable */ -1385:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); -1386:.\Generated_Source\PSoC5/cyPm.c **** -1387:.\Generated_Source\PSoC5/cyPm.c **** /* Enable 1kHz ILO (required for CTW operation) */ -1388:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start1K(); -1389:.\Generated_Source\PSoC5/cyPm.c **** -1390:.\Generated_Source\PSoC5/cyPm.c **** /* Interval could be set only while CTW is disabled */ -1391:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) -1392:.\Generated_Source\PSoC5/cyPm.c **** { -1393:.\Generated_Source\PSoC5/cyPm.c **** /* Set CTW interval if needed */ -1394:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG1_REG != ctwInterval) -1395:.\Generated_Source\PSoC5/cyPm.c **** { -1396:.\Generated_Source\PSoC5/cyPm.c **** /* Disable the CTW, set new CTW interval and enable it again */ -1397:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); -1398:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG1_REG = ctwInterval; -1399:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; -1400:.\Generated_Source\PSoC5/cyPm.c **** } /* Required interval is already set */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 26 - - -1401:.\Generated_Source\PSoC5/cyPm.c **** } -1402:.\Generated_Source\PSoC5/cyPm.c **** else -1403:.\Generated_Source\PSoC5/cyPm.c **** { -1404:.\Generated_Source\PSoC5/cyPm.c **** /* Set CTW interval if needed */ -1405:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG1_REG != ctwInterval) -1406:.\Generated_Source\PSoC5/cyPm.c **** { -1407:.\Generated_Source\PSoC5/cyPm.c **** /* Set the new CTW interval. Could be changed if CTW is disabled */ -1408:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG1_REG = ctwInterval; -1409:.\Generated_Source\PSoC5/cyPm.c **** } /* Required interval is already set */ -1410:.\Generated_Source\PSoC5/cyPm.c **** -1411:.\Generated_Source\PSoC5/cyPm.c **** /* Enable the CTW */ -1412:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; -1413:.\Generated_Source\PSoC5/cyPm.c **** } -1414:.\Generated_Source\PSoC5/cyPm.c **** } -1415:.\Generated_Source\PSoC5/cyPm.c **** -1416:.\Generated_Source\PSoC5/cyPm.c **** -1417:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1418:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmOppsSet -1419:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1420:.\Generated_Source\PSoC5/cyPm.c **** * -1421:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1422:.\Generated_Source\PSoC5/cyPm.c **** * Performs 1PPS configuration: -1423:.\Generated_Source\PSoC5/cyPm.c **** * - Starts 32 KHz XTAL -1424:.\Generated_Source\PSoC5/cyPm.c **** * - Disables 1PPS interupts -1425:.\Generated_Source\PSoC5/cyPm.c **** * - Enables 1PPS -1426:.\Generated_Source\PSoC5/cyPm.c **** * -1427:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1428:.\Generated_Source\PSoC5/cyPm.c **** * None -1429:.\Generated_Source\PSoC5/cyPm.c **** * -1430:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1431:.\Generated_Source\PSoC5/cyPm.c **** * None -1432:.\Generated_Source\PSoC5/cyPm.c **** * -1433:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1434:.\Generated_Source\PSoC5/cyPm.c **** void CyPmOppsSet(void) -1435:.\Generated_Source\PSoC5/cyPm.c **** { -1436:.\Generated_Source\PSoC5/cyPm.c **** /* Enable 32kHz XTAL if needed */ -1437:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) -1438:.\Generated_Source\PSoC5/cyPm.c **** { -1439:.\Generated_Source\PSoC5/cyPm.c **** /* Enable 32kHz XTAL */ -1440:.\Generated_Source\PSoC5/cyPm.c **** CyXTAL_32KHZ_Start(); -1441:.\Generated_Source\PSoC5/cyPm.c **** } -1442:.\Generated_Source\PSoC5/cyPm.c **** -1443:.\Generated_Source\PSoC5/cyPm.c **** /* Disable 1PPS interrupt enable */ -1444:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); -1445:.\Generated_Source\PSoC5/cyPm.c **** -1446:.\Generated_Source\PSoC5/cyPm.c **** /* Enable 1PPS operation */ -1447:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; -1448:.\Generated_Source\PSoC5/cyPm.c **** } -1449:.\Generated_Source\PSoC5/cyPm.c **** -1450:.\Generated_Source\PSoC5/cyPm.c **** -1451:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1452:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmFtwSetInterval -1453:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1454:.\Generated_Source\PSoC5/cyPm.c **** * -1455:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1456:.\Generated_Source\PSoC5/cyPm.c **** * Performs FTW configuration: -1457:.\Generated_Source\PSoC5/cyPm.c **** * - Disables FTW interrupt - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 27 - - -1458:.\Generated_Source\PSoC5/cyPm.c **** * - Enables 100 kHz ILO -1459:.\Generated_Source\PSoC5/cyPm.c **** * - Sets new FTW interval. -1460:.\Generated_Source\PSoC5/cyPm.c **** * -1461:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1462:.\Generated_Source\PSoC5/cyPm.c **** * ftwInterval - FTW counter interval. -1463:.\Generated_Source\PSoC5/cyPm.c **** * -1464:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1465:.\Generated_Source\PSoC5/cyPm.c **** * None -1466:.\Generated_Source\PSoC5/cyPm.c **** * -1467:.\Generated_Source\PSoC5/cyPm.c **** * Side Effects: -1468:.\Generated_Source\PSoC5/cyPm.c **** * Enables ILO 100 KHz clock and leaves it enabled. -1469:.\Generated_Source\PSoC5/cyPm.c **** * -1470:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1471:.\Generated_Source\PSoC5/cyPm.c **** void CyPmFtwSetInterval(uint8 ftwInterval) -1472:.\Generated_Source\PSoC5/cyPm.c **** { -1473:.\Generated_Source\PSoC5/cyPm.c **** /* Disable FTW interrupt enable */ -1474:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); -1475:.\Generated_Source\PSoC5/cyPm.c **** -1476:.\Generated_Source\PSoC5/cyPm.c **** /* Enable 100kHz ILO */ -1477:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start100K(); -1478:.\Generated_Source\PSoC5/cyPm.c **** -1479:.\Generated_Source\PSoC5/cyPm.c **** /* Iterval could be set only while FTW is disabled */ -1480:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) -1481:.\Generated_Source\PSoC5/cyPm.c **** { -1482:.\Generated_Source\PSoC5/cyPm.c **** /* Disable FTW, set new FTW interval if needed and enable it again */ -1483:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG0_REG != ftwInterval) -1484:.\Generated_Source\PSoC5/cyPm.c **** { -1485:.\Generated_Source\PSoC5/cyPm.c **** /* Disable the CTW, set new CTW interval and enable it again */ -1486:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); -1487:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG0_REG = ftwInterval; -1488:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; -1489:.\Generated_Source\PSoC5/cyPm.c **** } /* Required interval is already set */ -1490:.\Generated_Source\PSoC5/cyPm.c **** } -1491:.\Generated_Source\PSoC5/cyPm.c **** else -1492:.\Generated_Source\PSoC5/cyPm.c **** { -1493:.\Generated_Source\PSoC5/cyPm.c **** /* Set new FTW counter interval if needed. FTW is disabled. */ -1494:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG0_REG != ftwInterval) -1495:.\Generated_Source\PSoC5/cyPm.c **** { -1496:.\Generated_Source\PSoC5/cyPm.c **** /* Set the new CTW interval. Could be changed if CTW is disabled */ -1497:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG0_REG = ftwInterval; -1498:.\Generated_Source\PSoC5/cyPm.c **** } /* Required interval is already set */ -1499:.\Generated_Source\PSoC5/cyPm.c **** -1500:.\Generated_Source\PSoC5/cyPm.c **** /* Enable the FTW */ -1501:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; -1502:.\Generated_Source\PSoC5/cyPm.c **** } -1503:.\Generated_Source\PSoC5/cyPm.c **** } -1504:.\Generated_Source\PSoC5/cyPm.c **** -1505:.\Generated_Source\PSoC5/cyPm.c **** -1506:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1507:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHibSlpSaveSet -1508:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1509:.\Generated_Source\PSoC5/cyPm.c **** * -1510:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1511:.\Generated_Source\PSoC5/cyPm.c **** * This API is used for preparing device for Sleep and Hibernate low power -1512:.\Generated_Source\PSoC5/cyPm.c **** * modes entry: -1513:.\Generated_Source\PSoC5/cyPm.c **** * - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5) -1514:.\Generated_Source\PSoC5/cyPm.c **** * - Saves SC/CT routing connections (PSoC 3/5/5LP) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 28 - - -1515:.\Generated_Source\PSoC5/cyPm.c **** * - Disables Serial Wire Viewer (SWV) (PSoC 3) -1516:.\Generated_Source\PSoC5/cyPm.c **** * - Save boost reference selection and set it to internal -1517:.\Generated_Source\PSoC5/cyPm.c **** * -1518:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1519:.\Generated_Source\PSoC5/cyPm.c **** * None -1520:.\Generated_Source\PSoC5/cyPm.c **** * -1521:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1522:.\Generated_Source\PSoC5/cyPm.c **** * None -1523:.\Generated_Source\PSoC5/cyPm.c **** * -1524:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: -1525:.\Generated_Source\PSoC5/cyPm.c **** * No -1526:.\Generated_Source\PSoC5/cyPm.c **** * -1527:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1528:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibSlpSaveSet(void) -1529:.\Generated_Source\PSoC5/cyPm.c **** { - 26 .loc 1 1529 0 - 27 .cfi_startproc - 28 @ args = 0, pretend = 0, frame = 0 - 29 @ frame_needed = 0, uses_anonymous_args = 0 - 30 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 31 .LCFI0: - 32 .cfi_def_cfa_offset 36 - 33 .cfi_offset 4, -36 - 34 .cfi_offset 5, -32 - 35 .cfi_offset 6, -28 - 36 .cfi_offset 7, -24 - 37 .cfi_offset 8, -20 - 38 .cfi_offset 9, -16 - 39 .cfi_offset 10, -12 - 40 .cfi_offset 11, -8 - 41 .cfi_offset 14, -4 -1530:.\Generated_Source\PSoC5/cyPm.c **** /* Save SC/CT routing registers */ -1531:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); - 42 .loc 1 1531 0 - 43 0004 DFF848B1 ldr fp, .L5+32 - 44 0008 494B ldr r3, .L5 - 45 000a 9BF80020 ldrb r2, [fp, #0] @ zero_extendqisi2 -1532:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); - 46 .loc 1 1532 0 - 47 000e 4949 ldr r1, .L5+4 -1531:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); - 48 .loc 1 1531 0 - 49 0010 5A72 strb r2, [r3, #9] - 50 .loc 1 1532 0 - 51 0012 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 -1533:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); - 52 .loc 1 1533 0 - 53 0014 484F ldr r7, .L5+8 -1532:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); - 54 .loc 1 1532 0 - 55 0016 9872 strb r0, [r3, #10] - 56 .loc 1 1533 0 - 57 0018 3C78 ldrb r4, [r7, #0] @ zero_extendqisi2 -1534:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); -1535:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); -1536:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); -1537:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 29 - - -1538:.\Generated_Source\PSoC5/cyPm.c **** -1539:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); -1540:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); -1541:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); -1542:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); -1543:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); -1544:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); -1545:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); -1546:.\Generated_Source\PSoC5/cyPm.c **** -1547:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); -1548:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); -1549:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); -1550:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); -1551:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); - 58 .loc 1 1551 0 - 59 001a DFF838A1 ldr sl, .L5+36 -1533:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); - 60 .loc 1 1533 0 - 61 001e DC72 strb r4, [r3, #11] -1534:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); - 62 .loc 1 1534 0 - 63 0020 8D78 ldrb r5, [r1, #2] @ zero_extendqisi2 -1552:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); - 64 .loc 1 1552 0 - 65 0022 DFF83491 ldr r9, .L5+40 -1534:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); - 66 .loc 1 1534 0 - 67 0026 1D73 strb r5, [r3, #12] -1535:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); - 68 .loc 1 1535 0 - 69 0028 FE78 ldrb r6, [r7, #3] @ zero_extendqisi2 -1553:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); - 70 .loc 1 1553 0 - 71 002a DFF83081 ldr r8, .L5+44 -1535:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); - 72 .loc 1 1535 0 - 73 002e 5E73 strb r6, [r3, #13] -1536:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); - 74 .loc 1 1536 0 - 75 0030 8A79 ldrb r2, [r1, #6] @ zero_extendqisi2 -1554:.\Generated_Source\PSoC5/cyPm.c **** -1555:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); - 76 .loc 1 1555 0 - 77 0032 DFF82CC1 ldr ip, .L5+48 -1536:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); - 78 .loc 1 1536 0 - 79 0036 9A73 strb r2, [r3, #14] -1537:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); - 80 .loc 1 1537 0 - 81 0038 F879 ldrb r0, [r7, #7] @ zero_extendqisi2 - 82 003a D873 strb r0, [r3, #15] -1539:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); - 83 .loc 1 1539 0 - 84 003c 8C7B ldrb r4, [r1, #14] @ zero_extendqisi2 - 85 003e 1C74 strb r4, [r3, #16] -1540:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); - 86 .loc 1 1540 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 30 - - - 87 0040 FD7B ldrb r5, [r7, #15] @ zero_extendqisi2 - 88 0042 5D74 strb r5, [r3, #17] -1541:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); - 89 .loc 1 1541 0 - 90 0044 4E7C ldrb r6, [r1, #17] @ zero_extendqisi2 - 91 0046 9E74 strb r6, [r3, #18] -1542:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); - 92 .loc 1 1542 0 - 93 0048 7A7C ldrb r2, [r7, #17] @ zero_extendqisi2 - 94 004a DA74 strb r2, [r3, #19] -1543:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); - 95 .loc 1 1543 0 - 96 004c 087D ldrb r0, [r1, #20] @ zero_extendqisi2 - 97 004e 1875 strb r0, [r3, #20] -1544:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); - 98 .loc 1 1544 0 - 99 0050 7C7D ldrb r4, [r7, #21] @ zero_extendqisi2 - 100 0052 5C75 strb r4, [r3, #21] -1545:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); - 101 .loc 1 1545 0 - 102 0054 0D7E ldrb r5, [r1, #24] @ zero_extendqisi2 - 103 0056 9D75 strb r5, [r3, #22] -1547:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); - 104 .loc 1 1547 0 - 105 0058 7E7F ldrb r6, [r7, #29] @ zero_extendqisi2 - 106 005a DE75 strb r6, [r3, #23] -1548:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); - 107 .loc 1 1548 0 - 108 005c 91F82020 ldrb r2, [r1, #32] @ zero_extendqisi2 - 109 0060 1A76 strb r2, [r3, #24] -1549:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); - 110 .loc 1 1549 0 - 111 0062 97F82000 ldrb r0, [r7, #32] @ zero_extendqisi2 - 112 0066 5876 strb r0, [r3, #25] -1550:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); - 113 .loc 1 1550 0 - 114 0068 91F82240 ldrb r4, [r1, #34] @ zero_extendqisi2 - 115 006c 9C76 strb r4, [r3, #26] -1551:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); - 116 .loc 1 1551 0 - 117 006e 9AF80050 ldrb r5, [sl, #0] @ zero_extendqisi2 - 118 0072 DD76 strb r5, [r3, #27] -1552:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); - 119 .loc 1 1552 0 - 120 0074 99F80060 ldrb r6, [r9, #0] @ zero_extendqisi2 - 121 0078 1E77 strb r6, [r3, #28] -1553:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); - 122 .loc 1 1553 0 - 123 007a 98F80020 ldrb r2, [r8, #0] @ zero_extendqisi2 -1556:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); -1557:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); - 124 .loc 1 1557 0 - 125 007e 2F4E ldr r6, .L5+12 -1553:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); - 126 .loc 1 1553 0 - 127 0080 5A77 strb r2, [r3, #29] -1555:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 31 - - - 128 .loc 1 1555 0 - 129 0082 9CF80000 ldrb r0, [ip, #0] @ zero_extendqisi2 - 130 0086 9877 strb r0, [r3, #30] -1556:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); - 131 .loc 1 1556 0 - 132 0088 97F82F40 ldrb r4, [r7, #47] @ zero_extendqisi2 - 133 008c DC77 strb r4, [r3, #31] - 134 .loc 1 1557 0 - 135 008e 3578 ldrb r5, [r6, #0] @ zero_extendqisi2 -1558:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); -1559:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); - 136 .loc 1 1559 0 - 137 0090 2B4C ldr r4, .L5+16 -1557:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); - 138 .loc 1 1557 0 - 139 0092 83F82050 strb r5, [r3, #32] -1558:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); - 140 .loc 1 1558 0 - 141 0096 2B4D ldr r5, .L5+20 - 142 0098 2A78 ldrb r2, [r5, #0] @ zero_extendqisi2 - 143 009a 83F82120 strb r2, [r3, #33] - 144 .loc 1 1559 0 - 145 009e 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 146 00a0 83F82200 strb r0, [r3, #34] -1560:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); - 147 .loc 1 1560 0 - 148 00a4 2848 ldr r0, .L5+24 - 149 00a6 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 150 00a8 83F82320 strb r2, [r3, #35] -1561:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); - 151 .loc 1 1561 0 - 152 00ac 91F83820 ldrb r2, [r1, #56] @ zero_extendqisi2 - 153 00b0 83F82420 strb r2, [r3, #36] -1562:.\Generated_Source\PSoC5/cyPm.c **** -1563:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW0 , 0u); - 154 .loc 1 1563 0 - 155 00b4 0022 movs r2, #0 - 156 00b6 8BF80020 strb r2, [fp, #0] -1564:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW2 , 0u); - 157 .loc 1 1564 0 - 158 00ba 07F8012C strb r2, [r7, #-1] -1535:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); - 159 .loc 1 1535 0 - 160 00be 0337 adds r7, r7, #3 -1565:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW3 , 0u); - 161 .loc 1 1565 0 - 162 00c0 07F8032C strb r2, [r7, #-3] -1564:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW2 , 0u); - 163 .loc 1 1564 0 - 164 00c4 043F subs r7, r7, #4 -1566:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW4 , 0u); - 165 .loc 1 1566 0 - 166 00c6 0237 adds r7, r7, #2 - 167 00c8 3A70 strb r2, [r7, #0] -1567:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW6 , 0u); - 168 .loc 1 1567 0 - 169 00ca BA70 strb r2, [r7, #2] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 32 - - -1568:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW8 , 0u); - 170 .loc 1 1568 0 - 171 00cc 3A71 strb r2, [r7, #4] -1569:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW10, 0u); - 172 .loc 1 1569 0 - 173 00ce BA71 strb r2, [r7, #6] -1570:.\Generated_Source\PSoC5/cyPm.c **** -1571:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW0 , 0u); - 174 .loc 1 1571 0 - 175 00d0 3A73 strb r2, [r7, #12] -1572:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW2 , 0u); - 176 .loc 1 1572 0 - 177 00d2 BA73 strb r2, [r7, #14] -1573:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW3 , 0u); - 178 .loc 1 1573 0 - 179 00d4 FA73 strb r2, [r7, #15] -1574:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW4 , 0u); - 180 .loc 1 1574 0 - 181 00d6 3A74 strb r2, [r7, #16] -1575:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW6 , 0u); - 182 .loc 1 1575 0 - 183 00d8 BA74 strb r2, [r7, #18] -1576:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW8 , 0u); - 184 .loc 1 1576 0 - 185 00da 3A75 strb r2, [r7, #20] -1577:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW10, 0u); - 186 .loc 1 1577 0 - 187 00dc BA75 strb r2, [r7, #22] -1578:.\Generated_Source\PSoC5/cyPm.c **** -1579:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW0 , 0u); - 188 .loc 1 1579 0 - 189 00de 3A77 strb r2, [r7, #28] -1580:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW2 , 0u); - 190 .loc 1 1580 0 - 191 00e0 BA77 strb r2, [r7, #30] -1581:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW3 , 0u); - 192 .loc 1 1581 0 - 193 00e2 FA77 strb r2, [r7, #31] -1582:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW4 , 0u); - 194 .loc 1 1582 0 - 195 00e4 87F82020 strb r2, [r7, #32] -1583:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW6 , 0u); - 196 .loc 1 1583 0 - 197 00e8 8AF80020 strb r2, [sl, #0] -1584:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW8 , 0u); - 198 .loc 1 1584 0 - 199 00ec 89F80020 strb r2, [r9, #0] -1585:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW10, 0u); - 200 .loc 1 1585 0 - 201 00f0 88F80020 strb r2, [r8, #0] -1586:.\Generated_Source\PSoC5/cyPm.c **** -1587:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW0 , 0u); - 202 .loc 1 1587 0 - 203 00f4 8CF80020 strb r2, [ip, #0] -1588:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW2 , 0u); - 204 .loc 1 1588 0 - 205 00f8 87F82E20 strb r2, [r7, #46] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 33 - - -1589:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW3 , 0u); - 206 .loc 1 1589 0 - 207 00fc 3270 strb r2, [r6, #0] -1590:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW4 , 0u); - 208 .loc 1 1590 0 - 209 00fe 2A70 strb r2, [r5, #0] -1591:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW6 , 0u); - 210 .loc 1 1591 0 - 211 0100 2270 strb r2, [r4, #0] -1592:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW8 , 0u); - 212 .loc 1 1592 0 - 213 0102 0270 strb r2, [r0, #0] -1593:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW10, 0u); -1594:.\Generated_Source\PSoC5/cyPm.c **** -1595:.\Generated_Source\PSoC5/cyPm.c **** -1596:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC3) -1597:.\Generated_Source\PSoC5/cyPm.c **** -1598:.\Generated_Source\PSoC5/cyPm.c **** /* Serial Wire Viewer (SWV) workaround */ -1599:.\Generated_Source\PSoC5/cyPm.c **** -1600:.\Generated_Source\PSoC5/cyPm.c **** /* Disable SWV before entering low power mode */ -1601:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) -1602:.\Generated_Source\PSoC5/cyPm.c **** { -1603:.\Generated_Source\PSoC5/cyPm.c **** /* Save SWV clock enabled state */ -1604:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.swvClkEnabled = CY_PM_ENABLED; -1605:.\Generated_Source\PSoC5/cyPm.c **** -1606:.\Generated_Source\PSoC5/cyPm.c **** /* Save current ports drive mode settings */ -1607:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); -1608:.\Generated_Source\PSoC5/cyPm.c **** -1609:.\Generated_Source\PSoC5/cyPm.c **** /* Set drive mode to strong output */ -1610:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | -1611:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PRT1_PC3_DM_STRONG; -1612:.\Generated_Source\PSoC5/cyPm.c **** -1613:.\Generated_Source\PSoC5/cyPm.c **** /* Disable SWV clocks */ -1614:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); -1615:.\Generated_Source\PSoC5/cyPm.c **** } -1616:.\Generated_Source\PSoC5/cyPm.c **** else -1617:.\Generated_Source\PSoC5/cyPm.c **** { -1618:.\Generated_Source\PSoC5/cyPm.c **** /* Save SWV clock disabled state */ -1619:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.swvClkEnabled = CY_PM_DISABLED; -1620:.\Generated_Source\PSoC5/cyPm.c **** } -1621:.\Generated_Source\PSoC5/cyPm.c **** -1622:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC3) */ -1623:.\Generated_Source\PSoC5/cyPm.c **** -1624:.\Generated_Source\PSoC5/cyPm.c **** -1625:.\Generated_Source\PSoC5/cyPm.c **** /*************************************************************************** -1626:.\Generated_Source\PSoC5/cyPm.c **** * Save boost reference and set it to boost's internal by clearing the bit. -1627:.\Generated_Source\PSoC5/cyPm.c **** * External (chip bandgap) reference is not available in Sleep and Hibernate. -1628:.\Generated_Source\PSoC5/cyPm.c **** ***************************************************************************/ -1629:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) - 214 .loc 1 1629 0 - 215 0104 1148 ldr r0, .L5+28 -1593:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW10, 0u); - 216 .loc 1 1593 0 - 217 0106 81F83820 strb r2, [r1, #56] - 218 .loc 1 1629 0 - 219 010a 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 -1588:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW2 , 0u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 34 - - - 220 .loc 1 1588 0 - 221 010c 2E37 adds r7, r7, #46 - 222 .loc 1 1629 0 - 223 010e 11F00802 ands r2, r1, #8 - 224 0112 08D0 beq .L2 -1630:.\Generated_Source\PSoC5/cyPm.c **** { -1631:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.boostRefExt = CY_PM_ENABLED; - 225 .loc 1 1631 0 - 226 0114 0121 movs r1, #1 - 227 0116 83F82E10 strb r1, [r3, #46] -1632:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); - 228 .loc 1 1632 0 - 229 011a 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 230 011c 03F0F702 and r2, r3, #247 - 231 0120 0270 strb r2, [r0, #0] - 232 0122 BDE8F08F pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 233 .L2: -1633:.\Generated_Source\PSoC5/cyPm.c **** } -1634:.\Generated_Source\PSoC5/cyPm.c **** else -1635:.\Generated_Source\PSoC5/cyPm.c **** { -1636:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.boostRefExt = CY_PM_DISABLED; - 234 .loc 1 1636 0 - 235 0126 83F82E20 strb r2, [r3, #46] - 236 012a BDE8F08F pop {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 237 .L6: - 238 012e 00BF .align 2 - 239 .L5: - 240 0130 00000000 .word .LANCHOR0 - 241 0134 025A0040 .word 1073764866 - 242 0138 035A0040 .word 1073764867 - 243 013c 335A0040 .word 1073764915 - 244 0140 365A0040 .word 1073764918 - 245 0144 345A0040 .word 1073764916 - 246 0148 385A0040 .word 1073764920 - 247 014c 22430040 .word 1073759010 - 248 0150 005A0040 .word 1073764864 - 249 0154 265A0040 .word 1073764902 - 250 0158 285A0040 .word 1073764904 - 251 015c 2A5A0040 .word 1073764906 - 252 0160 305A0040 .word 1073764912 - 253 .cfi_endproc - 254 .LFE11: - 255 .size CyPmHibSlpSaveSet, .-CyPmHibSlpSaveSet - 256 .section .text.CyPmHibSlpRestore,"ax",%progbits - 257 .align 1 - 258 .thumb - 259 .thumb_func - 260 .type CyPmHibSlpRestore, %function - 261 CyPmHibSlpRestore: - 262 .LFB12: -1637:.\Generated_Source\PSoC5/cyPm.c **** } -1638:.\Generated_Source\PSoC5/cyPm.c **** } -1639:.\Generated_Source\PSoC5/cyPm.c **** -1640:.\Generated_Source\PSoC5/cyPm.c **** -1641:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1642:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHibSlpRestore -1643:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 35 - - -1644:.\Generated_Source\PSoC5/cyPm.c **** * -1645:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1646:.\Generated_Source\PSoC5/cyPm.c **** * This API is used for restoring device configurations after wakeup from Sleep -1647:.\Generated_Source\PSoC5/cyPm.c **** * and Hibernate low power modes: -1648:.\Generated_Source\PSoC5/cyPm.c **** * - Restores SC/CT routing connections -1649:.\Generated_Source\PSoC5/cyPm.c **** * - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3) -1650:.\Generated_Source\PSoC5/cyPm.c **** * - Restore boost reference selection -1651:.\Generated_Source\PSoC5/cyPm.c **** * -1652:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1653:.\Generated_Source\PSoC5/cyPm.c **** * None -1654:.\Generated_Source\PSoC5/cyPm.c **** * -1655:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1656:.\Generated_Source\PSoC5/cyPm.c **** * None -1657:.\Generated_Source\PSoC5/cyPm.c **** * -1658:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1659:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHibSlpRestore(void) -1660:.\Generated_Source\PSoC5/cyPm.c **** { - 263 .loc 1 1660 0 - 264 .cfi_startproc - 265 @ args = 0, pretend = 0, frame = 0 - 266 @ frame_needed = 0, uses_anonymous_args = 0 - 267 @ link register save eliminated. -1661:.\Generated_Source\PSoC5/cyPm.c **** /* Restore SC/CT routing registers */ -1662:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); - 268 .loc 1 1662 0 - 269 0000 254B ldr r3, .L9 - 270 0002 264A ldr r2, .L9+4 - 271 0004 597A ldrb r1, [r3, #9] @ zero_extendqisi2 - 272 0006 1170 strb r1, [r2, #0] -1663:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); - 273 .loc 1 1663 0 - 274 0008 987A ldrb r0, [r3, #10] @ zero_extendqisi2 - 275 000a 9070 strb r0, [r2, #2] -1664:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); - 276 .loc 1 1664 0 - 277 000c D97A ldrb r1, [r3, #11] @ zero_extendqisi2 - 278 000e D170 strb r1, [r2, #3] -1665:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); - 279 .loc 1 1665 0 - 280 0010 187B ldrb r0, [r3, #12] @ zero_extendqisi2 - 281 0012 1071 strb r0, [r2, #4] -1666:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); - 282 .loc 1 1666 0 - 283 0014 597B ldrb r1, [r3, #13] @ zero_extendqisi2 - 284 0016 9171 strb r1, [r2, #6] -1667:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); - 285 .loc 1 1667 0 - 286 0018 987B ldrb r0, [r3, #14] @ zero_extendqisi2 - 287 001a 1072 strb r0, [r2, #8] -1668:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); - 288 .loc 1 1668 0 - 289 001c D97B ldrb r1, [r3, #15] @ zero_extendqisi2 - 290 001e 9172 strb r1, [r2, #10] -1669:.\Generated_Source\PSoC5/cyPm.c **** -1670:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); - 291 .loc 1 1670 0 - 292 0020 187C ldrb r0, [r3, #16] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 36 - - - 293 0022 1074 strb r0, [r2, #16] -1671:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); - 294 .loc 1 1671 0 - 295 0024 597C ldrb r1, [r3, #17] @ zero_extendqisi2 - 296 0026 9174 strb r1, [r2, #18] -1672:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); - 297 .loc 1 1672 0 - 298 0028 987C ldrb r0, [r3, #18] @ zero_extendqisi2 - 299 002a D074 strb r0, [r2, #19] -1673:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); - 300 .loc 1 1673 0 - 301 002c D97C ldrb r1, [r3, #19] @ zero_extendqisi2 - 302 002e 1175 strb r1, [r2, #20] -1674:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); - 303 .loc 1 1674 0 - 304 0030 187D ldrb r0, [r3, #20] @ zero_extendqisi2 - 305 0032 9075 strb r0, [r2, #22] -1675:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); - 306 .loc 1 1675 0 - 307 0034 597D ldrb r1, [r3, #21] @ zero_extendqisi2 - 308 0036 1832 adds r2, r2, #24 - 309 0038 1170 strb r1, [r2, #0] -1676:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); - 310 .loc 1 1676 0 - 311 003a 987D ldrb r0, [r3, #22] @ zero_extendqisi2 - 312 003c 9070 strb r0, [r2, #2] -1677:.\Generated_Source\PSoC5/cyPm.c **** -1678:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); - 313 .loc 1 1678 0 - 314 003e D97D ldrb r1, [r3, #23] @ zero_extendqisi2 - 315 0040 1172 strb r1, [r2, #8] -1679:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); - 316 .loc 1 1679 0 - 317 0042 187E ldrb r0, [r3, #24] @ zero_extendqisi2 - 318 0044 9072 strb r0, [r2, #10] -1680:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); - 319 .loc 1 1680 0 - 320 0046 597E ldrb r1, [r3, #25] @ zero_extendqisi2 - 321 0048 D172 strb r1, [r2, #11] -1681:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); - 322 .loc 1 1681 0 - 323 004a 987E ldrb r0, [r3, #26] @ zero_extendqisi2 - 324 004c 1073 strb r0, [r2, #12] -1682:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); - 325 .loc 1 1682 0 - 326 004e D97E ldrb r1, [r3, #27] @ zero_extendqisi2 - 327 0050 9173 strb r1, [r2, #14] -1683:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); - 328 .loc 1 1683 0 - 329 0052 187F ldrb r0, [r3, #28] @ zero_extendqisi2 - 330 0054 1074 strb r0, [r2, #16] -1684:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); - 331 .loc 1 1684 0 - 332 0056 597F ldrb r1, [r3, #29] @ zero_extendqisi2 - 333 0058 9174 strb r1, [r2, #18] -1685:.\Generated_Source\PSoC5/cyPm.c **** -1686:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 37 - - - 334 .loc 1 1686 0 - 335 005a 987F ldrb r0, [r3, #30] @ zero_extendqisi2 - 336 005c 1076 strb r0, [r2, #24] -1687:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); - 337 .loc 1 1687 0 - 338 005e D97F ldrb r1, [r3, #31] @ zero_extendqisi2 - 339 0060 9176 strb r1, [r2, #26] -1688:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); - 340 .loc 1 1688 0 - 341 0062 93F82000 ldrb r0, [r3, #32] @ zero_extendqisi2 - 342 0066 D076 strb r0, [r2, #27] -1689:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); - 343 .loc 1 1689 0 - 344 0068 93F82110 ldrb r1, [r3, #33] @ zero_extendqisi2 - 345 006c 1177 strb r1, [r2, #28] -1690:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); - 346 .loc 1 1690 0 - 347 006e 93F82200 ldrb r0, [r3, #34] @ zero_extendqisi2 - 348 0072 9077 strb r0, [r2, #30] -1691:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); - 349 .loc 1 1691 0 - 350 0074 93F82310 ldrb r1, [r3, #35] @ zero_extendqisi2 - 351 0078 82F82010 strb r1, [r2, #32] -1692:.\Generated_Source\PSoC5/cyPm.c **** CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); - 352 .loc 1 1692 0 - 353 007c 93F82400 ldrb r0, [r3, #36] @ zero_extendqisi2 - 354 0080 82F82200 strb r0, [r2, #34] -1693:.\Generated_Source\PSoC5/cyPm.c **** -1694:.\Generated_Source\PSoC5/cyPm.c **** -1695:.\Generated_Source\PSoC5/cyPm.c **** #if(CY_PSOC3) -1696:.\Generated_Source\PSoC5/cyPm.c **** -1697:.\Generated_Source\PSoC5/cyPm.c **** /* Serial Wire Viewer (SWV) workaround */ -1698:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) -1699:.\Generated_Source\PSoC5/cyPm.c **** { -1700:.\Generated_Source\PSoC5/cyPm.c **** /* Restore ports drive mode */ -1701:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | -1702:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.prt1Dm; -1703:.\Generated_Source\PSoC5/cyPm.c **** -1704:.\Generated_Source\PSoC5/cyPm.c **** /* Enable SWV clocks */ -1705:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; -1706:.\Generated_Source\PSoC5/cyPm.c **** } -1707:.\Generated_Source\PSoC5/cyPm.c **** -1708:.\Generated_Source\PSoC5/cyPm.c **** #endif /* (CY_PSOC3) */ -1709:.\Generated_Source\PSoC5/cyPm.c **** -1710:.\Generated_Source\PSoC5/cyPm.c **** -1711:.\Generated_Source\PSoC5/cyPm.c **** /* Restore boost reference */ -1712:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.boostRefExt) - 355 .loc 1 1712 0 - 356 0084 93F82E30 ldrb r3, [r3, #46] @ zero_extendqisi2 - 357 0088 012B cmp r3, #1 - 358 008a 04D1 bne .L7 -1713:.\Generated_Source\PSoC5/cyPm.c **** { -1714:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; - 359 .loc 1 1714 0 - 360 008c 0449 ldr r1, .L9+8 - 361 008e 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 362 0090 42F00800 orr r0, r2, #8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 38 - - - 363 0094 0870 strb r0, [r1, #0] - 364 .L7: - 365 0096 7047 bx lr - 366 .L10: - 367 .align 2 - 368 .L9: - 369 0098 00000000 .word .LANCHOR0 - 370 009c 005A0040 .word 1073764864 - 371 00a0 22430040 .word 1073759010 - 372 .cfi_endproc - 373 .LFE12: - 374 .size CyPmHibSlpRestore, .-CyPmHibSlpRestore - 375 .section .text.CyPmSaveClocks,"ax",%progbits - 376 .align 1 - 377 .global CyPmSaveClocks - 378 .thumb - 379 .thumb_func - 380 .type CyPmSaveClocks, %function - 381 CyPmSaveClocks: - 382 .LFB0: - 81:.\Generated_Source\PSoC5/cyPm.c **** { - 383 .loc 1 81 0 - 384 .cfi_startproc - 385 @ args = 0, pretend = 0, frame = 0 - 386 @ frame_needed = 0, uses_anonymous_args = 0 - 387 0000 10B5 push {r4, lr} - 388 .LCFI1: - 389 .cfi_def_cfa_offset 8 - 390 .cfi_offset 4, -8 - 391 .cfi_offset 14, -4 - 83:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; - 392 .loc 1 83 0 - 393 0002 5E4A ldr r2, .L46 - 394 0004 5E4C ldr r4, .L46+4 - 395 0006 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 396 0008 03F00F00 and r0, r3, #15 - 84:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; - 397 .loc 1 84 0 - 398 000c 5D4B ldr r3, .L46+8 - 83:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; - 399 .loc 1 83 0 - 400 000e 84F83000 strb r0, [r4, #48] - 84:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; - 401 .loc 1 84 0 - 402 0012 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 403 0014 84F83110 strb r1, [r4, #49] - 85:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); - 404 .loc 1 85 0 - 405 0018 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 406 001a 00F0F001 and r1, r0, #240 - 407 001e 1170 strb r1, [r2, #0] - 86:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); - 408 .loc 1 86 0 - 409 0020 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 410 0022 0022 movs r2, #0 - 411 0024 1A70 strb r2, [r3, #0] - 89:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 39 - - - 412 .loc 1 89 0 - 413 0026 584B ldr r3, .L46+12 - 414 0028 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 415 002a 00F0C001 and r1, r0, #192 - 90:.\Generated_Source\PSoC5/cyPm.c **** CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); - 416 .loc 1 90 0 - 417 002e 3720 movs r0, #55 - 89:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; - 418 .loc 1 89 0 - 419 0030 84F83510 strb r1, [r4, #53] - 90:.\Generated_Source\PSoC5/cyPm.c **** CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); - 420 .loc 1 90 0 - 421 0034 FFF7FEFF bl CyFlash_SetWaitCycles - 422 .LVL0: - 93:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - 423 .loc 1 93 0 - 424 0038 544B ldr r3, .L46+16 - 425 003a 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 426 003c 02F00700 and r0, r2, #7 - 427 0040 84F83300 strb r0, [r4, #51] - 94:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; - 428 .loc 1 94 0 - 429 0044 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 430 0046 01F04002 and r2, r1, #64 - 431 004a 84F83420 strb r2, [r4, #52] - 97:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) - 432 .loc 1 97 0 - 433 004e 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 434 0050 13F01000 ands r0, r3, #16 - 100:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imo2x = CY_PM_ENABLED; - 435 .loc 1 100 0 - 436 0054 18BF it ne - 437 0056 0120 movne r0, #1 - 105:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imo2x = CY_PM_DISABLED; - 438 .loc 1 105 0 - 439 0058 84F83900 strb r0, [r4, #57] - 109:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); - 440 .loc 1 109 0 - 441 005c 0420 movs r0, #4 - 442 005e FFF7FEFF bl CyIMO_SetFreq - 443 .LVL1: - 112:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) - 444 .loc 1 112 0 - 445 0062 4B49 ldr r1, .L46+20 - 446 0064 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 447 0066 4649 ldr r1, .L46+4 - 448 0068 02F01003 and r3, r2, #16 - 449 006c 1846 mov r0, r3 - 450 006e 1BB1 cbz r3, .L14 - 115:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoEnable = CY_PM_ENABLED; - 451 .loc 1 115 0 - 452 0070 0120 movs r0, #1 - 453 0072 81F83600 strb r0, [r1, #54] - 454 0076 03E0 b .L15 - 455 .L14: - 120:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoEnable = CY_PM_DISABLED; - 456 .loc 1 120 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 40 - - - 457 0078 81F83630 strb r3, [r1, #54] - 123:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); - 458 .loc 1 123 0 - 459 007c FFF7FEFF bl CyIMO_Start - 460 .LVL2: - 461 .L15: - 127:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) - 462 .loc 1 127 0 - 463 0080 424A ldr r2, .L46+16 - 464 0082 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 465 0084 13F02001 ands r1, r3, #32 - 466 0088 10D0 beq .L16 - 131:.\Generated_Source\PSoC5/cyPm.c **** (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_S - 467 .loc 1 131 0 - 468 008a 4FF04022 mov r2, #1073758208 - 469 008e 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 130:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoClkSrc = - 470 .loc 1 130 0 - 471 0090 03F04001 and r1, r3, #64 - 472 0094 C8B2 uxtb r0, r1 - 473 0096 3A4B ldr r3, .L46+4 - 474 0098 0028 cmp r0, #0 - 475 009a 14BF ite ne - 476 009c 0122 movne r2, #1 - 477 009e 0222 moveq r2, #2 - 134:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetSource(CY_IMO_SOURCE_IMO); - 478 .loc 1 134 0 - 479 00a0 0020 movs r0, #0 - 130:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoClkSrc = - 480 .loc 1 130 0 - 481 00a2 83F83720 strb r2, [r3, #55] - 134:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetSource(CY_IMO_SOURCE_IMO); - 482 .loc 1 134 0 - 483 00a6 FFF7FEFF bl CyIMO_SetSource - 484 .LVL3: - 485 00aa 02E0 b .L18 - 486 .L16: - 139:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; - 487 .loc 1 139 0 - 488 00ac 3448 ldr r0, .L46+4 - 489 00ae 80F83710 strb r1, [r0, #55] - 490 .L18: - 143:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; - 491 .loc 1 143 0 - 492 00b2 4FF04020 mov r0, #1073758208 - 493 00b6 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 494 00b8 314B ldr r3, .L46+4 - 495 00ba 01F03002 and r2, r1, #48 - 496 00be 83F83820 strb r2, [r3, #56] - 146:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) - 497 .loc 1 146 0 - 498 00c2 1AB1 cbz r2, .L19 - 149:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | - 499 .loc 1 149 0 - 500 00c4 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 501 00c6 01F0CF02 and r2, r1, #207 - 502 00ca 0270 strb r2, [r0, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 41 - - - 503 .L19: - 154:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) - 504 .loc 1 154 0 - 505 00cc 2F48 ldr r0, .L46+16 - 506 00ce 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 507 00d0 03F01001 and r1, r3, #16 - 508 00d4 CAB2 uxtb r2, r1 - 509 00d6 0AB1 cbz r2, .L20 - 156:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_DisableDoubler(); - 510 .loc 1 156 0 - 511 00d8 FFF7FEFF bl CyIMO_DisableDoubler - 512 .LVL4: - 513 .L20: - 160:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; - 514 .loc 1 160 0 - 515 00dc 2D48 ldr r0, .L46+24 - 516 00de 2849 ldr r1, .L46+4 - 517 00e0 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 518 00e2 81F83A30 strb r3, [r1, #58] - 161:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) - 519 .loc 1 161 0 - 520 00e6 13B1 cbz r3, .L21 - 163:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); - 521 .loc 1 163 0 - 522 00e8 0020 movs r0, #0 - 523 00ea FFF7FEFF bl CyMasterClk_SetDivider - 524 .LVL5: - 525 .L21: - 167:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; - 526 .loc 1 167 0 - 527 00ee 2A4A ldr r2, .L46+28 - 528 00f0 2349 ldr r1, .L46+4 - 529 00f2 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 530 00f4 00F00303 and r3, r0, #3 - 531 00f8 81F83230 strb r3, [r1, #50] - 170:.\Generated_Source\PSoC5/cyPm.c **** if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) - 532 .loc 1 170 0 - 533 00fc 13B1 cbz r3, .L22 - 172:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); - 534 .loc 1 172 0 - 535 00fe 0020 movs r0, #0 - 536 0100 FFF7FEFF bl CyMasterClk_SetSource - 537 .LVL6: - 538 .L22: - 176:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); - 539 .loc 1 176 0 - 540 0104 254A ldr r2, .L46+32 - 177:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; - 541 .loc 1 177 0 - 542 0106 2649 ldr r1, .L46+36 - 176:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); - 543 .loc 1 176 0 - 544 0108 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 545 010a 1D4A ldr r2, .L46+4 - 546 010c 0302 lsls r3, r0, #8 - 547 010e 9387 strh r3, [r2, #60] @ movhi - 177:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 42 - - - 548 .loc 1 177 0 - 549 0110 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 550 0112 0343 orrs r3, r3, r0 - 551 0114 9387 strh r3, [r2, #60] @ movhi - 178:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) - 552 .loc 1 178 0 - 553 0116 13B1 cbz r3, .L23 - 180:.\Generated_Source\PSoC5/cyPm.c **** CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); - 554 .loc 1 180 0 - 555 0118 0020 movs r0, #0 - 556 011a FFF7FEFF bl CyBusClk_SetDivider - 557 .LVL7: - 558 .L23: - 184:.\Generated_Source\PSoC5/cyPm.c **** CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); - 559 .loc 1 184 0 - 560 011e 1B4B ldr r3, .L46+16 - 561 0120 2048 ldr r0, .L46+40 - 562 0122 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 563 0124 02F00701 and r1, r2, #7 - 564 0128 405C ldrb r0, [r0, r1] @ zero_extendqisi2 - 565 012a FFF7FEFF bl CyFlash_SetWaitCycles - 566 .LVL8: - 187:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) - 567 .loc 1 187 0 - 568 012e 1E4B ldr r3, .L46+44 - 569 0130 1348 ldr r0, .L46+4 - 570 0132 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 571 0134 12F00101 ands r1, r2, #1 - 572 0138 05D0 beq .L24 - 190:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.pllEnableState = CY_PM_ENABLED; - 573 .loc 1 190 0 - 574 013a 0123 movs r3, #1 - 575 013c 80F83E30 strb r3, [r0, #62] - 191:.\Generated_Source\PSoC5/cyPm.c **** CyPLL_OUT_Stop(); - 576 .loc 1 191 0 - 577 0140 FFF7FEFF bl CyPLL_OUT_Stop - 578 .LVL9: - 579 0144 01E0 b .L25 - 580 .L24: - 196:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.pllEnableState = CY_PM_DISABLED; - 581 .loc 1 196 0 - 582 0146 80F83E10 strb r1, [r0, #62] - 583 .L25: - 200:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) - 584 .loc 1 200 0 - 585 014a 184A ldr r2, .L46+48 - 586 014c 0C4B ldr r3, .L46+4 - 587 014e 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 588 0150 11F00100 ands r0, r1, #1 - 589 0154 05D0 beq .L26 - 203:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; - 590 .loc 1 203 0 - 591 0156 0122 movs r2, #1 - 592 0158 83F83F20 strb r2, [r3, #63] - 204:.\Generated_Source\PSoC5/cyPm.c **** CyXTAL_Stop(); - 593 .loc 1 204 0 - 594 015c FFF7FEFF bl CyXTAL_Stop - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 43 - - - 595 .LVL10: - 596 0160 01E0 b .L27 - 597 .L26: - 209:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; - 598 .loc 1 209 0 - 599 0162 83F83F00 strb r0, [r3, #63] - 600 .L27: - 218:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) - 601 .loc 1 218 0 - 602 0166 1249 ldr r1, .L46+52 - 603 0168 054B ldr r3, .L46+4 - 604 016a 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 605 016c 10F00402 ands r2, r0, #4 - 220:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; - 606 .loc 1 220 0 - 607 0170 18BF it ne - 608 0172 0122 movne r2, #1 - 224:.\Generated_Source\PSoC5/cyPm.c **** cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; - 609 .loc 1 224 0 - 610 0174 83F84020 strb r2, [r3, #64] - 611 0178 10BD pop {r4, pc} - 612 .L47: - 613 017a 00BF .align 2 - 614 .L46: - 615 017c A1430040 .word 1073759137 - 616 0180 00000000 .word .LANCHOR0 - 617 0184 A2430040 .word 1073759138 - 618 0188 00480040 .word 1073760256 - 619 018c 00420040 .word 1073758720 - 620 0190 A0430040 .word 1073759136 - 621 0194 04400040 .word 1073758212 - 622 0198 05400040 .word 1073758213 - 623 019c 07400040 .word 1073758215 - 624 01a0 06400040 .word 1073758214 - 625 01a4 00000000 .word .LANCHOR1 - 626 01a8 20420040 .word 1073758752 - 627 01ac 10420040 .word 1073758736 - 628 01b0 0B400040 .word 1073758219 - 629 .cfi_endproc - 630 .LFE0: - 631 .size CyPmSaveClocks, .-CyPmSaveClocks - 632 .section .text.CyPmRestoreClocks,"ax",%progbits - 633 .align 1 - 634 .global CyPmRestoreClocks - 635 .thumb - 636 .thumb_func - 637 .type CyPmRestoreClocks, %function - 638 CyPmRestoreClocks: - 639 .LFB1: - 257:.\Generated_Source\PSoC5/cyPm.c **** { - 640 .loc 1 257 0 - 641 .cfi_startproc - 642 @ args = 0, pretend = 0, frame = 8 - 643 @ frame_needed = 0, uses_anonymous_args = 0 - 644 .LVL11: - 264:.\Generated_Source\PSoC5/cyPm.c **** const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { - 645 .loc 1 264 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 44 - - - 646 0000 774A ldr r2, .L76 - 257:.\Generated_Source\PSoC5/cyPm.c **** { - 647 .loc 1 257 0 - 648 0002 13B5 push {r0, r1, r4, lr} - 649 .LCFI2: - 650 .cfi_def_cfa_offset 16 - 651 .cfi_offset 0, -16 - 652 .cfi_offset 1, -12 - 653 .cfi_offset 4, -8 - 654 .cfi_offset 14, -4 - 264:.\Generated_Source\PSoC5/cyPm.c **** const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { - 655 .loc 1 264 0 - 656 0004 1346 mov r3, r2 - 657 0006 53F8070F ldr r0, [r3, #7]! @ unaligned - 658 000a 9988 ldrh r1, [r3, #4] @ unaligned - 659 000c 9C79 ldrb r4, [r3, #6] @ zero_extendqisi2 - 269:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) - 660 .loc 1 269 0 - 661 000e 754B ldr r3, .L76+4 - 264:.\Generated_Source\PSoC5/cyPm.c **** const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { - 662 .loc 1 264 0 - 663 0010 0090 str r0, [sp, #0] @ unaligned - 269:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) - 664 .loc 1 269 0 - 665 0012 93F84000 ldrb r0, [r3, #64] @ zero_extendqisi2 - 264:.\Generated_Source\PSoC5/cyPm.c **** const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { - 666 .loc 1 264 0 - 667 0016 ADF80410 strh r1, [sp, #4] @ unaligned - 269:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) - 668 .loc 1 269 0 - 669 001a 0128 cmp r0, #1 - 264:.\Generated_Source\PSoC5/cyPm.c **** const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { - 670 .loc 1 264 0 - 671 001c 8DF80640 strb r4, [sp, #6] - 269:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) - 672 .loc 1 269 0 - 673 0020 0DD1 bne .L49 - 273:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_GET_CPU_FREQ_MHZ); - 674 .loc 1 273 0 - 675 0022 7149 ldr r1, .L76+8 - 272:.\Generated_Source\PSoC5/cyPm.c **** CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) - 676 .loc 1 272 0 - 677 0024 4B20 movs r0, #75 - 273:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_GET_CPU_FREQ_MHZ); - 678 .loc 1 273 0 - 679 0026 0C78 ldrb r4, [r1, #0] @ zero_extendqisi2 - 680 0028 04F00703 and r3, r4, #7 - 272:.\Generated_Source\PSoC5/cyPm.c **** CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) - 681 .loc 1 272 0 - 682 002c D25C ldrb r2, [r2, r3] @ zero_extendqisi2 - 683 002e 5043 muls r0, r2, r0 - 684 0030 FFF7FEFF bl CyDelayCycles - 685 .LVL12: - 275:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; - 686 .loc 1 275 0 - 687 0034 6D48 ldr r0, .L76+12 - 688 0036 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 45 - - - 689 0038 41F00404 orr r4, r1, #4 - 690 003c 0470 strb r4, [r0, #0] - 691 .L49: - 279:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) - 692 .loc 1 279 0 - 693 003e 694B ldr r3, .L76+4 - 694 0040 93F83F20 ldrb r2, [r3, #63] @ zero_extendqisi2 - 695 0044 012A cmp r2, #1 - 696 0046 09D0 beq .L50 - 697 .L53: - 325:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || - 698 .loc 1 325 0 - 699 0048 664C ldr r4, .L76+4 - 322:.\Generated_Source\PSoC5/cyPm.c **** CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); - 700 .loc 1 322 0 - 701 004a 3720 movs r0, #55 - 702 004c FFF7FEFF bl CyFlash_SetWaitCycles - 703 .LVL13: - 325:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || - 704 .loc 1 325 0 - 705 0050 94F83220 ldrb r2, [r4, #50] @ zero_extendqisi2 - 706 0054 911E subs r1, r2, #2 - 707 0056 0129 cmp r1, #1 - 708 0058 25D8 bhi .L52 - 709 005a 18E0 b .L75 - 710 .L50: - 289:.\Generated_Source\PSoC5/cyPm.c **** (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); - 711 .loc 1 289 0 - 712 005c 0020 movs r0, #0 - 713 005e FFF7FEFF bl CyXTAL_Start - 714 .LVL14: - 292:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_FASTCLK_XMHZ_CSR_REG; - 715 .loc 1 292 0 - 716 0062 6348 ldr r0, .L76+16 - 717 0064 0524 movs r4, #5 - 718 0066 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 719 .LVL15: - 720 .L54: - 298:.\Generated_Source\PSoC5/cyPm.c **** CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); - 721 .loc 1 298 0 - 722 0068 5F49 ldr r1, .L76+8 - 723 006a 5D4A ldr r2, .L76 - 724 006c 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 725 006e 03F00700 and r0, r3, #7 - 726 0072 115C ldrb r1, [r2, r0] @ zero_extendqisi2 - 727 0074 C820 movs r0, #200 - 728 0076 4843 muls r0, r1, r0 - 729 0078 FFF7FEFF bl CyDelayCycles - 730 .LVL16: - 301:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) - 731 .loc 1 301 0 - 732 007c 5C4B ldr r3, .L76+16 - 733 007e 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 734 0080 0306 lsls r3, r0, #24 - 735 0082 E1D5 bpl .L53 - 736 0084 013C subs r4, r4, #1 - 737 0086 A4B2 uxth r4, r4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 46 - - - 295:.\Generated_Source\PSoC5/cyPm.c **** for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) - 738 .loc 1 295 0 - 739 0088 002C cmp r4, #0 - 740 008a EDD1 bne .L54 - 741 008c DCE7 b .L53 - 742 .L75: - 329:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) - 743 .loc 1 329 0 - 744 008e 594B ldr r3, .L76+20 - 745 0090 94F83A00 ldrb r0, [r4, #58] @ zero_extendqisi2 - 746 0094 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 747 0096 8242 cmp r2, r0 - 748 0098 01D0 beq .L55 - 332:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); - 749 .loc 1 332 0 - 750 009a FFF7FEFF bl CyMasterClk_SetDivider - 751 .LVL17: - 752 .L55: - 336:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); - 753 .loc 1 336 0 - 754 009e 94F83200 ldrb r0, [r4, #50] @ zero_extendqisi2 - 755 00a2 FFF7FEFF bl CyMasterClk_SetSource - 756 .LVL18: - 757 .L52: - 340:.\Generated_Source\PSoC5/cyPm.c **** if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && - 758 .loc 1 340 0 - 759 00a6 4F48 ldr r0, .L76+4 - 760 00a8 90F83440 ldrb r4, [r0, #52] @ zero_extendqisi2 - 761 00ac 04F04001 and r1, r4, #64 - 762 00b0 CBB2 uxtb r3, r1 - 763 00b2 0446 mov r4, r0 - 764 00b4 5BB1 cbz r3, .L56 - 341:.\Generated_Source\PSoC5/cyPm.c **** (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) - 765 .loc 1 341 0 discriminator 1 - 766 00b6 90F83300 ldrb r0, [r0, #51] @ zero_extendqisi2 - 767 00ba 02AA add r2, sp, #8 - 768 00bc 1118 adds r1, r2, r0 - 340:.\Generated_Source\PSoC5/cyPm.c **** if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && - 769 .loc 1 340 0 discriminator 1 - 770 00be 11F8083C ldrb r3, [r1, #-8] @ zero_extendqisi2 - 771 00c2 032B cmp r3, #3 - 772 00c4 03D1 bne .L56 - 344:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetFreq(CY_IMO_FREQ_USB); - 773 .loc 1 344 0 - 774 00c6 0820 movs r0, #8 - 775 00c8 FFF7FEFF bl CyIMO_SetFreq - 776 .LVL19: - 777 00cc 16E0 b .L57 - 778 .L56: - 349:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); - 779 .loc 1 349 0 - 780 00ce 94F83300 ldrb r0, [r4, #51] @ zero_extendqisi2 - 781 00d2 02AA add r2, sp, #8 - 782 00d4 1118 adds r1, r2, r0 - 783 00d6 11F8080C ldrb r0, [r1, #-8] @ zero_extendqisi2 - 784 00da FFF7FEFF bl CyIMO_SetFreq - 785 .LVL20: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 47 - - - 351:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) - 786 .loc 1 351 0 - 787 00de 94F83440 ldrb r4, [r4, #52] @ zero_extendqisi2 - 788 00e2 4149 ldr r1, .L76+8 - 789 00e4 04F04003 and r3, r4, #64 - 790 00e8 D8B2 uxtb r0, r3 - 791 00ea 18B1 cbz r0, .L58 - 353:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; - 792 .loc 1 353 0 - 793 00ec 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 794 00ee 43F04004 orr r4, r3, #64 - 795 00f2 02E0 b .L74 - 796 .L58: - 357:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); - 797 .loc 1 357 0 - 798 00f4 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 799 00f6 02F0BF04 and r4, r2, #191 - 800 .L74: - 801 00fa 0C70 strb r4, [r1, #0] - 802 .L57: - 362:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && - 803 .loc 1 362 0 - 804 00fc 3948 ldr r0, .L76+4 - 805 00fe 90F83610 ldrb r1, [r0, #54] @ zero_extendqisi2 - 806 0102 0129 cmp r1, #1 - 807 0104 07D1 bne .L59 - 363:.\Generated_Source\PSoC5/cyPm.c **** (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) - 808 .loc 1 363 0 discriminator 1 - 809 0106 3C4A ldr r2, .L76+24 - 810 0108 1478 ldrb r4, [r2, #0] @ zero_extendqisi2 - 362:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && - 811 .loc 1 362 0 discriminator 1 - 812 010a 04F01003 and r3, r4, #16 - 813 010e D8B2 uxtb r0, r3 - 814 0110 08B9 cbnz r0, .L59 - 366:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); - 815 .loc 1 366 0 - 816 0112 FFF7FEFF bl CyIMO_Start - 817 .LVL21: - 818 .L59: - 370:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && - 819 .loc 1 370 0 - 820 0116 3348 ldr r0, .L76+4 - 821 0118 90F83610 ldrb r1, [r0, #54] @ zero_extendqisi2 - 822 011c 39B9 cbnz r1, .L60 - 371:.\Generated_Source\PSoC5/cyPm.c **** (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) - 823 .loc 1 371 0 discriminator 1 - 824 011e 364A ldr r2, .L76+24 - 825 0120 1478 ldrb r4, [r2, #0] @ zero_extendqisi2 - 370:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && - 826 .loc 1 370 0 discriminator 1 - 827 0122 04F01003 and r3, r4, #16 - 828 0126 D8B2 uxtb r0, r3 - 829 0128 08B1 cbz r0, .L60 - 373:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_Stop(); - 830 .loc 1 373 0 - 831 012a FFF7FEFF bl CyIMO_Stop - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 48 - - - 832 .LVL22: - 833 .L60: - 377:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_SetSource(cyPmClockBackup.imoClkSrc); - 834 .loc 1 377 0 - 835 012e 2D4C ldr r4, .L76+4 - 836 0130 94F83700 ldrb r0, [r4, #55] @ zero_extendqisi2 - 837 0134 FFF7FEFF bl CyIMO_SetSource - 838 .LVL23: - 380:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.imo2x) - 839 .loc 1 380 0 - 840 0138 94F83910 ldrb r1, [r4, #57] @ zero_extendqisi2 - 841 013c 0129 cmp r1, #1 - 842 013e 01D1 bne .L61 - 382:.\Generated_Source\PSoC5/cyPm.c **** CyIMO_EnableDoubler(); - 843 .loc 1 382 0 - 844 0140 FFF7FEFF bl CyIMO_EnableDoubler - 845 .LVL24: - 846 .L61: - 386:.\Generated_Source\PSoC5/cyPm.c **** if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) - 847 .loc 1 386 0 - 848 0144 4FF04023 mov r3, #1073758208 - 849 0148 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 850 014a 94F83820 ldrb r2, [r4, #56] @ zero_extendqisi2 - 851 014e 00F03004 and r4, r0, #48 - 852 0152 A242 cmp r2, r4 - 853 0154 04D0 beq .L62 - 388:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | - 854 .loc 1 388 0 - 855 0156 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 856 0158 21F03000 bic r0, r1, #48 - 857 015c 0243 orrs r2, r2, r0 - 858 015e 1A70 strb r2, [r3, #0] - 859 .L62: - 393:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) - 860 .loc 1 393 0 - 861 0160 204B ldr r3, .L76+4 - 862 0162 93F83E40 ldrb r4, [r3, #62] @ zero_extendqisi2 - 863 0166 012C cmp r4, #1 - 864 0168 0CD1 bne .L63 - 403:.\Generated_Source\PSoC5/cyPm.c **** (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); - 865 .loc 1 403 0 - 866 016a 0020 movs r0, #0 - 867 016c FFF7FEFF bl CyPLL_OUT_Start - 868 .LVL25: - 406:.\Generated_Source\PSoC5/cyPm.c **** CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ); - 869 .loc 1 406 0 - 870 0170 1D49 ldr r1, .L76+8 - 871 0172 1B4A ldr r2, .L76 - 872 0174 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 873 0176 00F00703 and r3, r0, #7 - 874 017a D45C ldrb r4, [r2, r3] @ zero_extendqisi2 - 875 017c FA20 movs r0, #250 - 876 017e 6043 muls r0, r4, r0 - 877 0180 FFF7FEFF bl CyDelayCycles - 878 .LVL26: - 879 .L63: - 411:.\Generated_Source\PSoC5/cyPm.c **** if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 49 - - - 880 .loc 1 411 0 - 881 0184 174C ldr r4, .L76+4 - 882 0186 94F83210 ldrb r1, [r4, #50] @ zero_extendqisi2 - 883 018a 0129 cmp r1, #1 - 884 018c 0BD8 bhi .L64 - 415:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) - 885 .loc 1 415 0 - 886 018e 1948 ldr r0, .L76+20 - 887 0190 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 888 0192 94F83A00 ldrb r0, [r4, #58] @ zero_extendqisi2 - 889 0196 8342 cmp r3, r0 - 890 0198 01D0 beq .L65 - 417:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); - 891 .loc 1 417 0 - 892 019a FFF7FEFF bl CyMasterClk_SetDivider - 893 .LVL27: - 894 .L65: - 421:.\Generated_Source\PSoC5/cyPm.c **** CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); - 895 .loc 1 421 0 - 896 019e 94F83200 ldrb r0, [r4, #50] @ zero_extendqisi2 - 897 01a2 FFF7FEFF bl CyMasterClk_SetSource - 898 .LVL28: - 899 .L64: - 425:.\Generated_Source\PSoC5/cyPm.c **** clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); - 900 .loc 1 425 0 - 901 01a6 154C ldr r4, .L76+28 - 902 01a8 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - 903 .LVL29: - 426:.\Generated_Source\PSoC5/cyPm.c **** clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; - 904 .loc 1 426 0 - 905 01aa 611E subs r1, r4, #1 - 427:.\Generated_Source\PSoC5/cyPm.c **** if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) - 906 .loc 1 427 0 - 907 01ac 0D4C ldr r4, .L76+4 - 426:.\Generated_Source\PSoC5/cyPm.c **** clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; - 908 .loc 1 426 0 - 909 01ae 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 - 910 .LVL30: - 427:.\Generated_Source\PSoC5/cyPm.c **** if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) - 911 .loc 1 427 0 - 912 01b0 A08F ldrh r0, [r4, #60] - 913 01b2 43EA0222 orr r2, r3, r2, lsl #8 - 914 .LVL31: - 915 01b6 9042 cmp r0, r2 - 916 01b8 01D0 beq .L66 - 429:.\Generated_Source\PSoC5/cyPm.c **** CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); - 917 .loc 1 429 0 - 918 01ba FFF7FEFF bl CyBusClk_SetDivider - 919 .LVL32: - 920 .L66: - 433:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | - 921 .loc 1 433 0 - 922 01be 1048 ldr r0, .L76+32 - 923 01c0 94F83520 ldrb r2, [r4, #53] @ zero_extendqisi2 - 924 01c4 0178 ldrb r1, [r0, #0] @ zero_extendqisi2 - 925 01c6 01F03F03 and r3, r1, #63 - 926 01ca 1343 orrs r3, r3, r2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 50 - - - 927 01cc 0370 strb r3, [r0, #0] - 437:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; - 928 .loc 1 437 0 - 929 01ce 94F83000 ldrb r0, [r4, #48] @ zero_extendqisi2 - 930 01d2 0C49 ldr r1, .L76+36 - 931 01d4 0870 strb r0, [r1, #0] - 438:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; - 932 .loc 1 438 0 - 933 01d6 94F83130 ldrb r3, [r4, #49] @ zero_extendqisi2 - 934 01da 4B70 strb r3, [r1, #1] - 439:.\Generated_Source\PSoC5/cyPm.c **** } - 935 .loc 1 439 0 - 936 01dc 1CBD pop {r2, r3, r4, pc} - 937 .L77: - 938 01de 00BF .align 2 - 939 .L76: - 940 01e0 00000000 .word .LANCHOR1 - 941 01e4 00000000 .word .LANCHOR0 - 942 01e8 00420040 .word 1073758720 - 943 01ec 0B400040 .word 1073758219 - 944 01f0 10420040 .word 1073758736 - 945 01f4 04400040 .word 1073758212 - 946 01f8 A0430040 .word 1073759136 - 947 01fc 07400040 .word 1073758215 - 948 0200 00480040 .word 1073760256 - 949 0204 A1430040 .word 1073759137 - 950 .cfi_endproc - 951 .LFE1: - 952 .size CyPmRestoreClocks, .-CyPmRestoreClocks - 953 .section .text.CyPmAltAct,"ax",%progbits - 954 .align 1 - 955 .global CyPmAltAct - 956 .thumb - 957 .thumb_func - 958 .type CyPmAltAct, %function - 959 CyPmAltAct: - 960 .LFB2: - 584:.\Generated_Source\PSoC5/cyPm.c **** { - 961 .loc 1 584 0 - 962 .cfi_startproc - 963 @ args = 0, pretend = 0, frame = 0 - 964 @ frame_needed = 0, uses_anonymous_args = 0 - 965 .LVL33: - 966 0000 30B5 push {r4, r5, lr} - 967 .LCFI3: - 968 .cfi_def_cfa_offset 12 - 969 .cfi_offset 4, -12 - 970 .cfi_offset 5, -8 - 971 .cfi_offset 14, -4 - 635:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 972 .loc 1 635 0 - 973 0002 124C ldr r4, .L79 - 974 0004 124B ldr r3, .L79+4 - 975 0006 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - 636:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - 976 .loc 1 636 0 - 977 0008 0809 lsrs r0, r1, #4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 51 - - - 978 .LVL34: - 635:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 979 .loc 1 635 0 - 980 000a 1A71 strb r2, [r3, #4] - 636:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - 981 .loc 1 636 0 - 982 000c 2070 strb r0, [r4, #0] - 639:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 983 .loc 1 639 0 - 984 000e 1148 ldr r0, .L79+8 - 640:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - 985 .loc 1 640 0 - 986 0010 01F00F02 and r2, r1, #15 - 639:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 987 .loc 1 639 0 - 988 0014 0578 ldrb r5, [r0, #0] @ zero_extendqisi2 - 644:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - 989 .loc 1 644 0 - 990 0016 C1F30031 ubfx r1, r1, #12, #1 - 991 .LVL35: - 639:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 992 .loc 1 639 0 - 993 001a 5D71 strb r5, [r3, #5] - 640:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - 994 .loc 1 640 0 - 995 001c 0270 strb r2, [r0, #0] - 643:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - 996 .loc 1 643 0 - 997 001e 0E4A ldr r2, .L79+12 - 998 0020 1578 ldrb r5, [r2, #0] @ zero_extendqisi2 - 999 0022 9D71 strb r5, [r3, #6] - 644:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - 1000 .loc 1 644 0 - 1001 0024 1170 strb r1, [r2, #0] - 648:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_A - 1002 .loc 1 648 0 - 1003 0026 0D49 ldr r1, .L79+16 - 1004 0028 0D78 ldrb r5, [r1, #0] @ zero_extendqisi2 - 1005 002a 05F0F805 and r5, r5, #248 - 1006 002e 45F00105 orr r5, r5, #1 - 1007 0032 0D70 strb r5, [r1, #0] - 651:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_MODE_CSR_REG; - 1008 .loc 1 651 0 - 1009 0034 0978 ldrb r1, [r1, #0] @ zero_extendqisi2 - 654:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 1010 .loc 1 654 0 - 1011 @ 654 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1012 0036 00BF NOP - 1013 - 1014 @ 0 "" 2 - 655:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 1015 .loc 1 655 0 - 1016 @ 655 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1017 0038 00BF NOP - 1018 - 1019 @ 0 "" 2 - 658:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 52 - - - 1020 .loc 1 658 0 - 1021 @ 658 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1022 003a 30BF WFI - 1023 - 1024 @ 0 "" 2 - 663:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; - 1025 .loc 1 663 0 - 1026 .thumb - 1027 003c 1979 ldrb r1, [r3, #4] @ zero_extendqisi2 - 1028 003e 2170 strb r1, [r4, #0] - 664:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - 1029 .loc 1 664 0 - 1030 0040 5979 ldrb r1, [r3, #5] @ zero_extendqisi2 - 1031 0042 0170 strb r1, [r0, #0] - 665:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - 1032 .loc 1 665 0 - 1033 0044 9B79 ldrb r3, [r3, #6] @ zero_extendqisi2 - 1034 0046 1370 strb r3, [r2, #0] - 1035 0048 30BD pop {r4, r5, pc} - 1036 .L80: - 1037 004a 00BF .align 2 - 1038 .L79: - 1039 004c 98430040 .word 1073759128 - 1040 0050 00000000 .word .LANCHOR0 - 1041 0054 99430040 .word 1073759129 - 1042 0058 9A430040 .word 1073759130 - 1043 005c 93430040 .word 1073759123 - 1044 .cfi_endproc - 1045 .LFE2: - 1046 .size CyPmAltAct, .-CyPmAltAct - 1047 .section .text.CyPmSleep,"ax",%progbits - 1048 .align 1 - 1049 .global CyPmSleep - 1050 .thumb - 1051 .thumb_func - 1052 .type CyPmSleep, %function - 1053 CyPmSleep: - 1054 .LFB3: - 788:.\Generated_Source\PSoC5/cyPm.c **** { - 1055 .loc 1 788 0 - 1056 .cfi_startproc - 1057 @ args = 0, pretend = 0, frame = 0 - 1058 @ frame_needed = 0, uses_anonymous_args = 0 - 1059 .LVL36: - 1060 0000 70B5 push {r4, r5, r6, lr} - 1061 .LCFI4: - 1062 .cfi_def_cfa_offset 16 - 1063 .cfi_offset 4, -16 - 1064 .cfi_offset 5, -12 - 1065 .cfi_offset 6, -8 - 1066 .cfi_offset 14, -4 - 788:.\Generated_Source\PSoC5/cyPm.c **** { - 1067 .loc 1 788 0 - 1068 0002 0C46 mov r4, r1 - 792:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); - 1069 .loc 1 792 0 - 1070 0004 FFF7FEFF bl CyEnterCriticalSection - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 53 - - - 1071 .LVL37: - 801:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) - 1072 .loc 1 801 0 - 1073 0008 2D4B ldr r3, .L93 - 792:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); - 1074 .loc 1 792 0 - 1075 000a 0546 mov r5, r0 - 1076 .LVL38: - 801:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) - 1077 .loc 1 801 0 - 1078 000c 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 1079 000e 11F00806 ands r6, r1, #8 - 1080 0012 50D1 bne .L91 - 804:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; - 1081 .loc 1 804 0 - 1082 0014 2B4A ldr r2, .L93+4 - 1083 0016 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 1084 .LVL39: - 1085 0018 00F01F03 and r3, r0, #31 - 1086 001c 1370 strb r3, [r2, #0] - 882:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpSaveSet(); - 1087 .loc 1 882 0 - 1088 001e FFF7FEFF bl CyPmHibSlpSaveSet - 1089 .LVL40: - 913:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 1090 .loc 1 913 0 - 1091 0022 294A ldr r2, .L93+8 - 1092 0024 2948 ldr r0, .L93+12 - 1093 0026 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 914:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - 1094 .loc 1 914 0 - 1095 0028 2309 lsrs r3, r4, #4 - 913:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 1096 .loc 1 913 0 - 1097 002a 0171 strb r1, [r0, #4] - 914:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - 1098 .loc 1 914 0 - 1099 002c 1370 strb r3, [r2, #0] - 917:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 1100 .loc 1 917 0 - 1101 002e 5178 ldrb r1, [r2, #1] @ zero_extendqisi2 - 918:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - 1102 .loc 1 918 0 - 1103 0030 04F00F03 and r3, r4, #15 - 917:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 1104 .loc 1 917 0 - 1105 0034 4171 strb r1, [r0, #5] - 918:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - 1106 .loc 1 918 0 - 1107 0036 5370 strb r3, [r2, #1] - 921:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - 1108 .loc 1 921 0 - 1109 0038 9178 ldrb r1, [r2, #2] @ zero_extendqisi2 - 922:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - 1110 .loc 1 922 0 - 1111 003a C4F30034 ubfx r4, r4, #12, #1 - 921:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 54 - - - 1112 .loc 1 921 0 - 1113 003e 8171 strb r1, [r0, #6] - 922:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - 1114 .loc 1 922 0 - 1115 0040 9470 strb r4, [r2, #2] - 921:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - 1116 .loc 1 921 0 - 1117 0042 0232 adds r2, r2, #2 - 935:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) - 1118 .loc 1 935 0 - 1119 0044 A2F5CD72 sub r2, r2, #410 - 1120 0048 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 1121 004a 5907 lsls r1, r3, #29 - 1122 004c 03D1 bne .L92 - 1123 .L83: - 938:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; - 1124 .loc 1 938 0 - 1125 004e 0122 movs r2, #1 - 1126 0050 80F82D20 strb r2, [r0, #45] - 1127 0054 0AE0 b .L85 - 1128 .L92: - 943:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; - 1129 .loc 1 943 0 - 1130 0056 80F82D60 strb r6, [r0, #45] - 946:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - 1131 .loc 1 946 0 - 1132 005a 1178 ldrb r1, [r2, #0] @ zero_extendqisi2 - 1133 005c 01F00703 and r3, r1, #7 - 1134 0060 80F82C30 strb r3, [r0, #44] - 949:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); - 1135 .loc 1 949 0 - 1136 0064 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 1137 0066 00F0F801 and r1, r0, #248 - 1138 006a 1170 strb r1, [r2, #0] - 1139 .L85: - 953:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_S - 1140 .loc 1 953 0 - 1141 006c 144B ldr r3, .L93 - 1142 006e 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1143 0070 00F0F801 and r1, r0, #248 - 1144 0074 41F00302 orr r2, r1, #3 - 1145 0078 1A70 strb r2, [r3, #0] - 956:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_MODE_CSR_REG; - 1146 .loc 1 956 0 - 1147 007a 1B78 ldrb r3, [r3, #0] @ zero_extendqisi2 - 959:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 1148 .loc 1 959 0 - 1149 @ 959 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1150 007c 00BF NOP - 1151 - 1152 @ 0 "" 2 - 960:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 1153 .loc 1 960 0 - 1154 @ 960 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1155 007e 00BF NOP - 1156 - 1157 @ 0 "" 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 55 - - - 963:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; - 1158 .loc 1 963 0 - 1159 @ 963 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1160 0080 30BF WFI - 1161 - 1162 @ 0 "" 2 - 968:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) - 1163 .loc 1 968 0 - 1164 .thumb - 1165 0082 1249 ldr r1, .L93+12 - 1166 0084 91F82D30 ldrb r3, [r1, #45] @ zero_extendqisi2 - 1167 0088 012B cmp r3, #1 - 1168 008a 08D0 beq .L86 - 970:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ - 1169 .loc 1 970 0 - 1170 008c 104B ldr r3, .L93+16 - 1171 008e 91F82C10 ldrb r1, [r1, #44] @ zero_extendqisi2 - 1172 0092 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1173 0094 20F00702 bic r2, r0, #7 - 1174 0098 42EA0100 orr r0, r2, r1 - 1175 009c 1870 strb r0, [r3, #0] - 1176 .L86: - 985:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpRestore(); - 1177 .loc 1 985 0 - 1178 009e FFF7FEFF bl CyPmHibSlpRestore - 1179 .LVL41: -1007:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; - 1180 .loc 1 1007 0 - 1181 00a2 0A4B ldr r3, .L93+12 - 1182 00a4 084A ldr r2, .L93+8 - 1183 00a6 1979 ldrb r1, [r3, #4] @ zero_extendqisi2 - 1184 00a8 1170 strb r1, [r2, #0] -1008:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - 1185 .loc 1 1008 0 - 1186 00aa 5879 ldrb r0, [r3, #5] @ zero_extendqisi2 - 1187 00ac 5070 strb r0, [r2, #1] -1009:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - 1188 .loc 1 1009 0 - 1189 00ae 9979 ldrb r1, [r3, #6] @ zero_extendqisi2 - 1190 00b0 084B ldr r3, .L93+20 -1012:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); - 1191 .loc 1 1012 0 - 1192 00b2 2846 mov r0, r5 -1009:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - 1193 .loc 1 1009 0 - 1194 00b4 1970 strb r1, [r3, #0] - 1195 .LVL42: - 1196 .L91: -1013:.\Generated_Source\PSoC5/cyPm.c **** } - 1197 .loc 1 1013 0 - 1198 00b6 BDE87040 pop {r4, r5, r6, lr} -1012:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); - 1199 .loc 1 1012 0 - 1200 00ba FFF7FEBF b CyExitCriticalSection - 1201 .LVL43: - 1202 .L94: - 1203 00be 00BF .align 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 56 - - - 1204 .L93: - 1205 00c0 93430040 .word 1073759123 - 1206 00c4 83460040 .word 1073759875 - 1207 00c8 98430040 .word 1073759128 - 1208 00cc 00000000 .word .LANCHOR0 - 1209 00d0 00420040 .word 1073758720 - 1210 00d4 9A430040 .word 1073759130 - 1211 .cfi_endproc - 1212 .LFE3: - 1213 .size CyPmSleep, .-CyPmSleep - 1214 .section .text.CyPmHibernate,"ax",%progbits - 1215 .align 1 - 1216 .global CyPmHibernate - 1217 .thumb - 1218 .thumb_func - 1219 .type CyPmHibernate, %function - 1220 CyPmHibernate: - 1221 .LFB4: -1060:.\Generated_Source\PSoC5/cyPm.c **** { - 1222 .loc 1 1060 0 - 1223 .cfi_startproc - 1224 @ args = 0, pretend = 0, frame = 0 - 1225 @ frame_needed = 0, uses_anonymous_args = 0 - 1226 0000 38B5 push {r3, r4, r5, lr} - 1227 .LCFI5: - 1228 .cfi_def_cfa_offset 16 - 1229 .cfi_offset 3, -16 - 1230 .cfi_offset 4, -12 - 1231 .cfi_offset 5, -8 - 1232 .cfi_offset 14, -4 -1064:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); - 1233 .loc 1 1064 0 - 1234 0002 FFF7FEFF bl CyEnterCriticalSection - 1235 .LVL44: -1072:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) - 1236 .loc 1 1072 0 - 1237 0006 7F4B ldr r3, .L125 -1064:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); - 1238 .loc 1 1064 0 - 1239 0008 0546 mov r5, r0 - 1240 .LVL45: -1072:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) - 1241 .loc 1 1072 0 - 1242 000a 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 1243 000c 01F00802 and r2, r1, #8 - 1244 0010 D3B2 uxtb r3, r2 - 1245 0012 002B cmp r3, #0 - 1246 0014 40F0F280 bne .L123 -1075:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; - 1247 .loc 1 1075 0 - 1248 0018 7B48 ldr r0, .L125+4 - 1249 .LVL46: - 1250 .LBB10: - 1251 .LBB11: -1234:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) - 1252 .loc 1 1234 0 - 1253 001a 7C4B ldr r3, .L125+8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 57 - - - 1254 .LBE11: - 1255 .LBE10: -1075:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; - 1256 .loc 1 1075 0 - 1257 001c 0478 ldrb r4, [r0, #0] @ zero_extendqisi2 - 1258 001e 04F01F01 and r1, r4, #31 - 1259 0022 0170 strb r1, [r0, #0] - 1260 .LBB15: - 1261 .LBB14: -1234:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) - 1262 .loc 1 1234 0 - 1263 0024 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1264 0026 02F00400 and r0, r2, #4 - 1265 002a C4B2 uxtb r4, r0 - 1266 002c 1CB1 cbz r4, .L97 -1248:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); - 1267 .loc 1 1248 0 - 1268 002e 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 1269 0030 01F0FB02 and r2, r1, #251 - 1270 0034 1A70 strb r2, [r3, #0] - 1271 .L97: -1253:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); - 1272 .loc 1 1253 0 - 1273 0036 0120 movs r0, #1 - 1274 0038 FFF7FEFF bl CyILO_SetPowerMode - 1275 .LVL47: - 1276 003c 744B ldr r3, .L125+12 - 1277 003e 1870 strb r0, [r3, #0] -1256:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? - 1278 .loc 1 1256 0 - 1279 0040 7448 ldr r0, .L125+16 - 1280 0042 0478 ldrb r4, [r0, #0] @ zero_extendqisi2 -1257:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_DISABLED : CY_PM_ENABLED; - 1281 .loc 1 1257 0 - 1282 0044 C4F34001 ubfx r1, r4, #1, #1 -1256:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? - 1283 .loc 1 1256 0 - 1284 0048 5970 strb r1, [r3, #1] -1260:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? - 1285 .loc 1 1260 0 - 1286 004a 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 -1265:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) - 1287 .loc 1 1265 0 - 1288 004c 6E4C ldr r4, .L125+4 -1261:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_DISABLED : CY_PM_ENABLED; - 1289 .loc 1 1261 0 - 1290 004e C2F38000 ubfx r0, r2, #2, #1 -1260:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? - 1291 .loc 1 1260 0 - 1292 0052 9870 strb r0, [r3, #2] -1265:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) - 1293 .loc 1 1265 0 - 1294 0054 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1295 0056 11F01002 ands r2, r1, #16 - 1296 005a 05D1 bne .L98 -1268:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.slpTrBypass = CY_PM_DISABLED; - 1297 .loc 1 1268 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 58 - - - 1298 005c DA70 strb r2, [r3, #3] -1269:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; - 1299 .loc 1 1269 0 - 1300 005e 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1301 0060 43F01001 orr r1, r3, #16 - 1302 0064 2170 strb r1, [r4, #0] - 1303 0066 01E0 b .L99 - 1304 .L98: -1273:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.slpTrBypass = CY_PM_ENABLED; - 1305 .loc 1 1273 0 - 1306 0068 0120 movs r0, #1 - 1307 006a D870 strb r0, [r3, #3] - 1308 .L99: - 1309 .LBB12: - 1310 .LBB13: -1715:.\Generated_Source\PSoC5/cyPm.c **** } -1716:.\Generated_Source\PSoC5/cyPm.c **** } -1717:.\Generated_Source\PSoC5/cyPm.c **** -1718:.\Generated_Source\PSoC5/cyPm.c **** -1719:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1720:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHviLviSaveDisable -1721:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1722:.\Generated_Source\PSoC5/cyPm.c **** * -1723:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1724:.\Generated_Source\PSoC5/cyPm.c **** * Saves analog and digital LVI and HVI configuration and disables them. -1725:.\Generated_Source\PSoC5/cyPm.c **** * -1726:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1727:.\Generated_Source\PSoC5/cyPm.c **** * None -1728:.\Generated_Source\PSoC5/cyPm.c **** * -1729:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1730:.\Generated_Source\PSoC5/cyPm.c **** * None -1731:.\Generated_Source\PSoC5/cyPm.c **** * -1732:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: -1733:.\Generated_Source\PSoC5/cyPm.c **** * No -1734:.\Generated_Source\PSoC5/cyPm.c **** * -1735:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1736:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHviLviSaveDisable(void) -1737:.\Generated_Source\PSoC5/cyPm.c **** { -1738:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) - 1311 .loc 1 1738 0 - 1312 006c 6A4C ldr r4, .L125+20 - 1313 006e 684B ldr r3, .L125+12 - 1314 0070 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - 1315 0072 12F00100 ands r0, r2, #1 - 1316 0076 11D0 beq .L100 -1739:.\Generated_Source\PSoC5/cyPm.c **** { -1740:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lvidEn = CY_PM_ENABLED; - 1317 .loc 1 1740 0 - 1318 0078 0121 movs r1, #1 -1741:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; - 1319 .loc 1 1741 0 - 1320 007a 684C ldr r4, .L125+24 -1740:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lvidEn = CY_PM_ENABLED; - 1321 .loc 1 1740 0 - 1322 007c 83F82510 strb r1, [r3, #37] - 1323 .loc 1 1741 0 - 1324 0080 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 59 - - -1742:.\Generated_Source\PSoC5/cyPm.c **** -1743:.\Generated_Source\PSoC5/cyPm.c **** /* Save state of reset device at a specified Vddd threshold */ -1744:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ - 1325 .loc 1 1744 0 - 1326 0082 6749 ldr r1, .L125+28 -1741:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; - 1327 .loc 1 1741 0 - 1328 0084 02F00F00 and r0, r2, #15 - 1329 0088 83F82600 strb r0, [r3, #38] - 1330 .loc 1 1744 0 - 1331 008c 0C78 ldrb r4, [r1, #0] @ zero_extendqisi2 -1745:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_DISABLED : CY_PM_ENABLED; - 1332 .loc 1 1745 0 - 1333 008e C4F38012 ubfx r2, r4, #6, #1 -1744:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ - 1334 .loc 1 1744 0 - 1335 0092 83F82A20 strb r2, [r3, #42] -1746:.\Generated_Source\PSoC5/cyPm.c **** -1747:.\Generated_Source\PSoC5/cyPm.c **** CyVdLvDigitDisable(); - 1336 .loc 1 1747 0 - 1337 0096 FFF7FEFF bl CyVdLvDigitDisable - 1338 .LVL48: - 1339 009a 01E0 b .L101 - 1340 .L100: -1748:.\Generated_Source\PSoC5/cyPm.c **** } -1749:.\Generated_Source\PSoC5/cyPm.c **** else -1750:.\Generated_Source\PSoC5/cyPm.c **** { -1751:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lvidEn = CY_PM_DISABLED; - 1341 .loc 1 1751 0 - 1342 009c 83F82500 strb r0, [r3, #37] - 1343 .L101: -1752:.\Generated_Source\PSoC5/cyPm.c **** } -1753:.\Generated_Source\PSoC5/cyPm.c **** -1754:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) - 1344 .loc 1 1754 0 - 1345 00a0 5D4B ldr r3, .L125+20 - 1346 00a2 5B4C ldr r4, .L125+12 - 1347 00a4 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1348 00a6 10F00201 ands r1, r0, #2 - 1349 00aa 0FD0 beq .L102 -1755:.\Generated_Source\PSoC5/cyPm.c **** { -1756:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaEn = CY_PM_ENABLED; - 1350 .loc 1 1756 0 - 1351 00ac 0122 movs r2, #1 -1757:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; - 1352 .loc 1 1757 0 - 1353 00ae 5B4B ldr r3, .L125+24 -1756:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaEn = CY_PM_ENABLED; - 1354 .loc 1 1756 0 - 1355 00b0 84F82720 strb r2, [r4, #39] - 1356 .loc 1 1757 0 - 1357 00b4 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 -1758:.\Generated_Source\PSoC5/cyPm.c **** -1759:.\Generated_Source\PSoC5/cyPm.c **** /* Save state of reset device at a specified Vdda threshold */ -1760:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ - 1358 .loc 1 1760 0 - 1359 00b6 5A4A ldr r2, .L125+28 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 60 - - -1757:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; - 1360 .loc 1 1757 0 - 1361 00b8 0109 lsrs r1, r0, #4 - 1362 00ba 84F82810 strb r1, [r4, #40] - 1363 .loc 1 1760 0 - 1364 00be 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 -1761:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_DISABLED : CY_PM_ENABLED; - 1365 .loc 1 1761 0 - 1366 00c0 D809 lsrs r0, r3, #7 -1760:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ - 1367 .loc 1 1760 0 - 1368 00c2 84F82B00 strb r0, [r4, #43] -1762:.\Generated_Source\PSoC5/cyPm.c **** -1763:.\Generated_Source\PSoC5/cyPm.c **** CyVdLvAnalogDisable(); - 1369 .loc 1 1763 0 - 1370 00c6 FFF7FEFF bl CyVdLvAnalogDisable - 1371 .LVL49: - 1372 00ca 01E0 b .L103 - 1373 .L102: -1764:.\Generated_Source\PSoC5/cyPm.c **** } -1765:.\Generated_Source\PSoC5/cyPm.c **** else -1766:.\Generated_Source\PSoC5/cyPm.c **** { -1767:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.lviaEn = CY_PM_DISABLED; - 1374 .loc 1 1767 0 - 1375 00cc 84F82710 strb r1, [r4, #39] - 1376 .L103: -1768:.\Generated_Source\PSoC5/cyPm.c **** } -1769:.\Generated_Source\PSoC5/cyPm.c **** -1770:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) - 1377 .loc 1 1770 0 - 1378 00d0 514C ldr r4, .L125+20 - 1379 00d2 4F4B ldr r3, .L125+12 - 1380 00d4 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1381 00d6 11F00402 ands r2, r1, #4 - 1382 00da 05D0 beq .L104 -1771:.\Generated_Source\PSoC5/cyPm.c **** { -1772:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.hviaEn = CY_PM_ENABLED; - 1383 .loc 1 1772 0 - 1384 00dc 0120 movs r0, #1 - 1385 00de 83F82900 strb r0, [r3, #41] -1773:.\Generated_Source\PSoC5/cyPm.c **** CyVdHvAnalogDisable(); - 1386 .loc 1 1773 0 - 1387 00e2 FFF7FEFF bl CyVdHvAnalogDisable - 1388 .LVL50: - 1389 00e6 01E0 b .L105 - 1390 .L104: -1774:.\Generated_Source\PSoC5/cyPm.c **** } -1775:.\Generated_Source\PSoC5/cyPm.c **** else -1776:.\Generated_Source\PSoC5/cyPm.c **** { -1777:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.hviaEn = CY_PM_DISABLED; - 1391 .loc 1 1777 0 - 1392 00e8 83F82920 strb r2, [r3, #41] - 1393 .L105: - 1394 .LBE13: - 1395 .LBE12: -1294:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; - 1396 .loc 1 1294 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 61 - - - 1397 00ec 4D4C ldr r4, .L125+32 -1288:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpSaveSet(); - 1398 .loc 1 1288 0 - 1399 00ee FFF7FEFF bl CyPmHibSlpSaveSet - 1400 .LVL51: -1294:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; - 1401 .loc 1 1294 0 - 1402 00f2 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1403 00f4 464B ldr r3, .L125+12 -1295:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; - 1404 .loc 1 1295 0 - 1405 00f6 4C4A ldr r2, .L125+36 -1294:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; - 1406 .loc 1 1294 0 - 1407 00f8 D971 strb r1, [r3, #7] -1295:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; - 1408 .loc 1 1295 0 - 1409 00fa 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 -1297:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; - 1410 .loc 1 1297 0 - 1411 00fc FF21 movs r1, #255 -1295:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; - 1412 .loc 1 1295 0 - 1413 00fe 1872 strb r0, [r3, #8] -1297:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; - 1414 .loc 1 1297 0 - 1415 0100 2170 strb r1, [r4, #0] -1298:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; - 1416 .loc 1 1298 0 - 1417 0102 B024 movs r4, #176 - 1418 0104 1470 strb r4, [r2, #0] - 1419 .LBE14: - 1420 .LBE15: -1091:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 1421 .loc 1 1091 0 - 1422 0106 494A ldr r2, .L125+40 -1092:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; - 1423 .loc 1 1092 0 - 1424 0108 0421 movs r1, #4 -1091:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - 1425 .loc 1 1091 0 - 1426 010a 1078 ldrb r0, [r2, #0] @ zero_extendqisi2 - 1427 010c 1871 strb r0, [r3, #4] -1092:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; - 1428 .loc 1 1092 0 - 1429 010e 1170 strb r1, [r2, #0] -1094:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 1430 .loc 1 1094 0 - 1431 0110 5478 ldrb r4, [r2, #1] @ zero_extendqisi2 -1095:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = 0x00u; - 1432 .loc 1 1095 0 - 1433 0112 0021 movs r1, #0 -1094:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - 1434 .loc 1 1094 0 - 1435 0114 5C71 strb r4, [r3, #5] -1095:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = 0x00u; - 1436 .loc 1 1095 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 62 - - - 1437 0116 5170 strb r1, [r2, #1] -1097:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - 1438 .loc 1 1097 0 - 1439 0118 9078 ldrb r0, [r2, #2] @ zero_extendqisi2 - 1440 011a 9871 strb r0, [r3, #6] -1098:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = 0x00u; - 1441 .loc 1 1098 0 - 1442 011c 9170 strb r1, [r2, #2] -1097:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - 1443 .loc 1 1097 0 - 1444 011e 0232 adds r2, r2, #2 -1102:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) - 1445 .loc 1 1102 0 - 1446 0120 A2F5CD74 sub r4, r2, #410 - 1447 0124 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 1448 0126 4007 lsls r0, r0, #29 - 1449 0128 03D1 bne .L124 - 1450 .L106: -1105:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; - 1451 .loc 1 1105 0 - 1452 012a 0124 movs r4, #1 - 1453 012c 83F82D40 strb r4, [r3, #45] - 1454 0130 0AE0 b .L108 - 1455 .L124: -1110:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; - 1456 .loc 1 1110 0 - 1457 0132 83F82D10 strb r1, [r3, #45] -1113:.\Generated_Source\PSoC5/cyPm.c **** cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - 1458 .loc 1 1113 0 - 1459 0136 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1460 0138 01F00702 and r2, r1, #7 - 1461 013c 83F82C20 strb r2, [r3, #44] -1116:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); - 1462 .loc 1 1116 0 - 1463 0140 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1464 0142 03F0F800 and r0, r3, #248 - 1465 0146 2070 strb r0, [r4, #0] - 1466 .L108: -1121:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_H - 1467 .loc 1 1121 0 - 1468 0148 2E49 ldr r1, .L125 - 1469 014a 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 1470 014c 02F0F803 and r3, r2, #248 - 1471 0150 43F00400 orr r0, r3, #4 - 1472 0154 0870 strb r0, [r1, #0] -1124:.\Generated_Source\PSoC5/cyPm.c **** (void) CY_PM_MODE_CSR_REG; - 1473 .loc 1 1124 0 - 1474 0156 0B78 ldrb r3, [r1, #0] @ zero_extendqisi2 -1127:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 1475 .loc 1 1127 0 - 1476 @ 1127 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1477 0158 00BF NOP - 1478 - 1479 @ 0 "" 2 -1128:.\Generated_Source\PSoC5/cyPm.c **** CY_NOP; - 1480 .loc 1 1128 0 - 1481 @ 1128 ".\Generated_Source\PSoC5\cyPm.c" 1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 63 - - - 1482 015a 00BF NOP - 1483 - 1484 @ 0 "" 2 -1131:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WFI; - 1485 .loc 1 1131 0 - 1486 @ 1131 ".\Generated_Source\PSoC5\cyPm.c" 1 - 1487 015c 30BF WFI - 1488 - 1489 @ 0 "" 2 -1138:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) - 1490 .loc 1 1138 0 - 1491 .thumb - 1492 015e 2C4C ldr r4, .L125+12 - 1493 0160 94F82D10 ldrb r1, [r4, #45] @ zero_extendqisi2 - 1494 0164 0129 cmp r1, #1 - 1495 0166 07D0 beq .L109 -1140:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ - 1496 .loc 1 1140 0 - 1497 0168 314A ldr r2, .L125+44 - 1498 016a 94F82C00 ldrb r0, [r4, #44] @ zero_extendqisi2 - 1499 016e 1378 ldrb r3, [r2, #0] @ zero_extendqisi2 - 1500 0170 23F00701 bic r1, r3, #7 - 1501 0174 0143 orrs r1, r1, r0 - 1502 0176 1170 strb r1, [r2, #0] - 1503 .L109: - 1504 .LBB16: - 1505 .LBB17: - 1506 .LBB18: - 1507 .LBB19: -1778:.\Generated_Source\PSoC5/cyPm.c **** } -1779:.\Generated_Source\PSoC5/cyPm.c **** } -1780:.\Generated_Source\PSoC5/cyPm.c **** -1781:.\Generated_Source\PSoC5/cyPm.c **** -1782:.\Generated_Source\PSoC5/cyPm.c **** /******************************************************************************* -1783:.\Generated_Source\PSoC5/cyPm.c **** * Function Name: CyPmHviLviRestore -1784:.\Generated_Source\PSoC5/cyPm.c **** ******************************************************************************** -1785:.\Generated_Source\PSoC5/cyPm.c **** * -1786:.\Generated_Source\PSoC5/cyPm.c **** * Summary: -1787:.\Generated_Source\PSoC5/cyPm.c **** * Restores analog and digital LVI and HVI configuration. -1788:.\Generated_Source\PSoC5/cyPm.c **** * -1789:.\Generated_Source\PSoC5/cyPm.c **** * Parameters: -1790:.\Generated_Source\PSoC5/cyPm.c **** * None -1791:.\Generated_Source\PSoC5/cyPm.c **** * -1792:.\Generated_Source\PSoC5/cyPm.c **** * Return: -1793:.\Generated_Source\PSoC5/cyPm.c **** * None -1794:.\Generated_Source\PSoC5/cyPm.c **** * -1795:.\Generated_Source\PSoC5/cyPm.c **** * Reentrant: -1796:.\Generated_Source\PSoC5/cyPm.c **** * No -1797:.\Generated_Source\PSoC5/cyPm.c **** * -1798:.\Generated_Source\PSoC5/cyPm.c **** *******************************************************************************/ -1799:.\Generated_Source\PSoC5/cyPm.c **** static void CyPmHviLviRestore(void) -1800:.\Generated_Source\PSoC5/cyPm.c **** { -1801:.\Generated_Source\PSoC5/cyPm.c **** /* Restore LVI/HVI configuration */ -1802:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.lvidEn) - 1508 .loc 1 1802 0 - 1509 0178 94F82540 ldrb r4, [r4, #37] @ zero_extendqisi2 - 1510 017c 244B ldr r3, .L125+12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 64 - - - 1511 017e 012C cmp r4, #1 - 1512 0180 05D1 bne .L110 -1803:.\Generated_Source\PSoC5/cyPm.c **** { -1804:.\Generated_Source\PSoC5/cyPm.c **** CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); - 1513 .loc 1 1804 0 - 1514 0182 93F82A00 ldrb r0, [r3, #42] @ zero_extendqisi2 - 1515 0186 93F82610 ldrb r1, [r3, #38] @ zero_extendqisi2 - 1516 018a FFF7FEFF bl CyVdLvDigitEnable - 1517 .LVL52: - 1518 .L110: -1805:.\Generated_Source\PSoC5/cyPm.c **** } -1806:.\Generated_Source\PSoC5/cyPm.c **** -1807:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.lviaEn) - 1519 .loc 1 1807 0 - 1520 018e 204C ldr r4, .L125+12 - 1521 0190 94F82720 ldrb r2, [r4, #39] @ zero_extendqisi2 - 1522 0194 012A cmp r2, #1 - 1523 0196 05D1 bne .L111 -1808:.\Generated_Source\PSoC5/cyPm.c **** { -1809:.\Generated_Source\PSoC5/cyPm.c **** CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); - 1524 .loc 1 1809 0 - 1525 0198 94F82B00 ldrb r0, [r4, #43] @ zero_extendqisi2 - 1526 019c 94F82810 ldrb r1, [r4, #40] @ zero_extendqisi2 - 1527 01a0 FFF7FEFF bl CyVdLvAnalogEnable - 1528 .LVL53: - 1529 .L111: -1810:.\Generated_Source\PSoC5/cyPm.c **** } -1811:.\Generated_Source\PSoC5/cyPm.c **** -1812:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.hviaEn) - 1530 .loc 1 1812 0 - 1531 01a4 94F82910 ldrb r1, [r4, #41] @ zero_extendqisi2 - 1532 01a8 0129 cmp r1, #1 - 1533 01aa 01D1 bne .L112 -1813:.\Generated_Source\PSoC5/cyPm.c **** { -1814:.\Generated_Source\PSoC5/cyPm.c **** CyVdHvAnalogEnable(); - 1534 .loc 1 1814 0 - 1535 01ac FFF7FEFF bl CyVdHvAnalogEnable - 1536 .LVL54: - 1537 .L112: - 1538 .LBE19: - 1539 .LBE18: -1330:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) - 1540 .loc 1 1330 0 - 1541 01b0 174C ldr r4, .L125+12 -1327:.\Generated_Source\PSoC5/cyPm.c **** CyPmHibSlpRestore(); - 1542 .loc 1 1327 0 - 1543 01b2 FFF7FEFF bl CyPmHibSlpRestore - 1544 .LVL55: -1330:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) - 1545 .loc 1 1330 0 - 1546 01b6 6078 ldrb r0, [r4, #1] @ zero_extendqisi2 - 1547 01b8 0128 cmp r0, #1 - 1548 01ba 01D1 bne .L113 -1333:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start1K(); - 1549 .loc 1 1333 0 - 1550 01bc FFF7FEFF bl CyILO_Start1K - 1551 .LVL56: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 65 - - - 1552 .L113: -1337:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) - 1553 .loc 1 1337 0 - 1554 01c0 A378 ldrb r3, [r4, #2] @ zero_extendqisi2 - 1555 01c2 012B cmp r3, #1 - 1556 01c4 01D1 bne .L114 -1340:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start100K(); - 1557 .loc 1 1340 0 - 1558 01c6 FFF7FEFF bl CyILO_Start100K - 1559 .LVL57: - 1560 .L114: -1344:.\Generated_Source\PSoC5/cyPm.c **** (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); - 1561 .loc 1 1344 0 - 1562 01ca 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 1563 01cc FFF7FEFF bl CyILO_SetPowerMode - 1564 .LVL58: -1347:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) - 1565 .loc 1 1347 0 - 1566 01d0 E278 ldrb r2, [r4, #3] @ zero_extendqisi2 - 1567 01d2 22B9 cbnz r2, .L115 -1350:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); - 1568 .loc 1 1350 0 - 1569 01d4 0C49 ldr r1, .L125+4 - 1570 01d6 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 1571 01d8 00F0EF03 and r3, r0, #239 - 1572 01dc 0B70 strb r3, [r1, #0] - 1573 .L115: -1357:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; - 1574 .loc 1 1357 0 - 1575 01de 0C48 ldr r0, .L125+12 - 1576 01e0 104A ldr r2, .L125+32 - 1577 01e2 C179 ldrb r1, [r0, #7] @ zero_extendqisi2 - 1578 01e4 1170 strb r1, [r2, #0] -1358:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; - 1579 .loc 1 1358 0 - 1580 01e6 037A ldrb r3, [r0, #8] @ zero_extendqisi2 - 1581 01e8 5370 strb r3, [r2, #1] - 1582 .LBE17: - 1583 .LBE16: -1149:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; - 1584 .loc 1 1149 0 - 1585 01ea 0179 ldrb r1, [r0, #4] @ zero_extendqisi2 - 1586 01ec 0F4A ldr r2, .L125+40 - 1587 01ee 1170 strb r1, [r2, #0] -1150:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - 1588 .loc 1 1150 0 - 1589 01f0 4379 ldrb r3, [r0, #5] @ zero_extendqisi2 -1151:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - 1590 .loc 1 1151 0 - 1591 01f2 1049 ldr r1, .L125+48 -1150:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - 1592 .loc 1 1150 0 - 1593 01f4 5370 strb r3, [r2, #1] -1151:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - 1594 .loc 1 1151 0 - 1595 01f6 8079 ldrb r0, [r0, #6] @ zero_extendqisi2 - 1596 01f8 0870 strb r0, [r1, #0] - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 66 - - -1154:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); - 1597 .loc 1 1154 0 - 1598 01fa 2846 mov r0, r5 - 1599 .LVL59: - 1600 .L123: -1155:.\Generated_Source\PSoC5/cyPm.c **** } - 1601 .loc 1 1155 0 - 1602 01fc BDE83840 pop {r3, r4, r5, lr} -1154:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); - 1603 .loc 1 1154 0 - 1604 0200 FFF7FEBF b CyExitCriticalSection - 1605 .LVL60: - 1606 .L126: - 1607 .align 2 - 1608 .L125: - 1609 0204 93430040 .word 1073759123 - 1610 0208 83460040 .word 1073759875 - 1611 020c 31430040 .word 1073759025 - 1612 0210 00000000 .word .LANCHOR0 - 1613 0214 00430040 .word 1073758976 - 1614 0218 F5460040 .word 1073759989 - 1615 021c F4460040 .word 1073759988 - 1616 0220 F7460040 .word 1073759991 - 1617 0224 85460040 .word 1073759877 - 1618 0228 86460040 .word 1073759878 - 1619 022c 98430040 .word 1073759128 - 1620 0230 00420040 .word 1073758720 - 1621 0234 9A430040 .word 1073759130 - 1622 .cfi_endproc - 1623 .LFE4: - 1624 .size CyPmHibernate, .-CyPmHibernate - 1625 .section .text.CyPmReadStatus,"ax",%progbits - 1626 .align 1 - 1627 .global CyPmReadStatus - 1628 .thumb - 1629 .thumb_func - 1630 .type CyPmReadStatus, %function - 1631 CyPmReadStatus: - 1632 .LFB5: -1188:.\Generated_Source\PSoC5/cyPm.c **** { - 1633 .loc 1 1188 0 - 1634 .cfi_startproc - 1635 @ args = 0, pretend = 0, frame = 0 - 1636 @ frame_needed = 0, uses_anonymous_args = 0 - 1637 .LVL61: - 1638 0000 38B5 push {r3, r4, r5, lr} - 1639 .LCFI6: - 1640 .cfi_def_cfa_offset 16 - 1641 .cfi_offset 3, -16 - 1642 .cfi_offset 4, -12 - 1643 .cfi_offset 5, -8 - 1644 .cfi_offset 14, -4 -1188:.\Generated_Source\PSoC5/cyPm.c **** { - 1645 .loc 1 1188 0 - 1646 0002 0546 mov r5, r0 -1194:.\Generated_Source\PSoC5/cyPm.c **** interruptState = CyEnterCriticalSection(); - 1647 .loc 1 1194 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 67 - - - 1648 0004 FFF7FEFF bl CyEnterCriticalSection - 1649 .LVL62: -1197:.\Generated_Source\PSoC5/cyPm.c **** interruptStatus |= CY_PM_INT_SR_REG; - 1650 .loc 1 1197 0 - 1651 0008 0649 ldr r1, .L128 - 1652 000a 074B ldr r3, .L128+4 - 1653 000c 91F84220 ldrb r2, [r1, #66] @ zero_extendqisi2 - 1654 0010 1C78 ldrb r4, [r3, #0] @ zero_extendqisi2 - 1655 0012 1443 orrs r4, r4, r2 - 1656 .LVL63: -1199:.\Generated_Source\PSoC5/cyPm.c **** interruptStatus &= ((uint8)(~mask)); - 1657 .loc 1 1199 0 - 1658 0014 24EA0505 bic r5, r4, r5 - 1659 0018 81F84250 strb r5, [r1, #66] -1202:.\Generated_Source\PSoC5/cyPm.c **** CyExitCriticalSection(interruptState); - 1660 .loc 1 1202 0 - 1661 001c FFF7FEFF bl CyExitCriticalSection - 1662 .LVL64: -1205:.\Generated_Source\PSoC5/cyPm.c **** } - 1663 .loc 1 1205 0 - 1664 0020 2046 mov r0, r4 - 1665 0022 38BD pop {r3, r4, r5, pc} - 1666 .L129: - 1667 .align 2 - 1668 .L128: - 1669 0024 00000000 .word .LANCHOR0 - 1670 0028 90430040 .word 1073759120 - 1671 .cfi_endproc - 1672 .LFE5: - 1673 .size CyPmReadStatus, .-CyPmReadStatus - 1674 .section .text.CyPmCtwSetInterval,"ax",%progbits - 1675 .align 1 - 1676 .global CyPmCtwSetInterval - 1677 .thumb - 1678 .thumb_func - 1679 .type CyPmCtwSetInterval, %function - 1680 CyPmCtwSetInterval: - 1681 .LFB8: -1383:.\Generated_Source\PSoC5/cyPm.c **** { - 1682 .loc 1 1383 0 - 1683 .cfi_startproc - 1684 @ args = 0, pretend = 0, frame = 0 - 1685 @ frame_needed = 0, uses_anonymous_args = 0 - 1686 .LVL65: - 1687 0000 38B5 push {r3, r4, r5, lr} - 1688 .LCFI7: - 1689 .cfi_def_cfa_offset 16 - 1690 .cfi_offset 3, -16 - 1691 .cfi_offset 4, -12 - 1692 .cfi_offset 5, -8 - 1693 .cfi_offset 14, -4 -1385:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); - 1694 .loc 1 1385 0 - 1695 0002 124C ldr r4, .L134 -1383:.\Generated_Source\PSoC5/cyPm.c **** { - 1696 .loc 1 1383 0 - 1697 0004 0546 mov r5, r0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 68 - - -1385:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); - 1698 .loc 1 1385 0 - 1699 0006 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1700 0008 03F0F700 and r0, r3, #247 - 1701 .LVL66: - 1702 000c 2070 strb r0, [r4, #0] -1388:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start1K(); - 1703 .loc 1 1388 0 - 1704 000e FFF7FEFF bl CyILO_Start1K - 1705 .LVL67: -1391:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) - 1706 .loc 1 1391 0 - 1707 0012 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1708 0014 0E4B ldr r3, .L134+4 - 1709 0016 01F00402 and r2, r1, #4 - 1710 001a D0B2 uxtb r0, r2 - 1711 001c 60B1 cbz r0, .L131 -1394:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG1_REG != ctwInterval) - 1712 .loc 1 1394 0 - 1713 001e 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1714 0020 AA42 cmp r2, r5 - 1715 0022 11D0 beq .L130 -1397:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); - 1716 .loc 1 1397 0 - 1717 0024 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1718 0026 01F0FB00 and r0, r1, #251 - 1719 002a 2070 strb r0, [r4, #0] -1398:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG1_REG = ctwInterval; - 1720 .loc 1 1398 0 - 1721 002c 1D70 strb r5, [r3, #0] -1399:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; - 1722 .loc 1 1399 0 - 1723 002e 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1724 0030 43F00402 orr r2, r3, #4 - 1725 0034 2270 strb r2, [r4, #0] - 1726 0036 38BD pop {r3, r4, r5, pc} - 1727 .L131: -1405:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG1_REG != ctwInterval) - 1728 .loc 1 1405 0 - 1729 0038 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 1730 003a A942 cmp r1, r5 -1408:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG1_REG = ctwInterval; - 1731 .loc 1 1408 0 - 1732 003c 18BF it ne - 1733 003e 1D70 strbne r5, [r3, #0] -1412:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; - 1734 .loc 1 1412 0 - 1735 0040 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 1736 0042 40F00403 orr r3, r0, #4 - 1737 0046 2370 strb r3, [r4, #0] - 1738 .L130: - 1739 0048 38BD pop {r3, r4, r5, pc} - 1740 .L135: - 1741 004a 00BF .align 2 - 1742 .L134: - 1743 004c 82430040 .word 1073759106 - 1744 0050 81430040 .word 1073759105 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 69 - - - 1745 .cfi_endproc - 1746 .LFE8: - 1747 .size CyPmCtwSetInterval, .-CyPmCtwSetInterval - 1748 .section .text.CyPmOppsSet,"ax",%progbits - 1749 .align 1 - 1750 .global CyPmOppsSet - 1751 .thumb - 1752 .thumb_func - 1753 .type CyPmOppsSet, %function - 1754 CyPmOppsSet: - 1755 .LFB9: -1435:.\Generated_Source\PSoC5/cyPm.c **** { - 1756 .loc 1 1435 0 - 1757 .cfi_startproc - 1758 @ args = 0, pretend = 0, frame = 0 - 1759 @ frame_needed = 0, uses_anonymous_args = 0 - 1760 0000 08B5 push {r3, lr} - 1761 .LCFI8: - 1762 .cfi_def_cfa_offset 8 - 1763 .cfi_offset 3, -8 - 1764 .cfi_offset 14, -4 -1437:.\Generated_Source\PSoC5/cyPm.c **** if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) - 1765 .loc 1 1437 0 - 1766 0002 084B ldr r3, .L138 - 1767 0004 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1768 0006 C307 lsls r3, r0, #31 - 1769 0008 01D4 bmi .L137 -1440:.\Generated_Source\PSoC5/cyPm.c **** CyXTAL_32KHZ_Start(); - 1770 .loc 1 1440 0 - 1771 000a FFF7FEFF bl CyXTAL_32KHZ_Start - 1772 .LVL68: - 1773 .L137: -1444:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); - 1774 .loc 1 1444 0 - 1775 000e 0649 ldr r1, .L138+4 - 1776 0010 0A78 ldrb r2, [r1, #0] @ zero_extendqisi2 - 1777 0012 02F0DF03 and r3, r2, #223 - 1778 0016 0B70 strb r3, [r1, #0] -1447:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; - 1779 .loc 1 1447 0 - 1780 0018 0878 ldrb r0, [r1, #0] @ zero_extendqisi2 - 1781 001a 40F01002 orr r2, r0, #16 - 1782 001e 0A70 strb r2, [r1, #0] - 1783 0020 08BD pop {r3, pc} - 1784 .L139: - 1785 0022 00BF .align 2 - 1786 .L138: - 1787 0024 08430040 .word 1073758984 - 1788 0028 82430040 .word 1073759106 - 1789 .cfi_endproc - 1790 .LFE9: - 1791 .size CyPmOppsSet, .-CyPmOppsSet - 1792 .section .text.CyPmFtwSetInterval,"ax",%progbits - 1793 .align 1 - 1794 .global CyPmFtwSetInterval - 1795 .thumb - 1796 .thumb_func - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 70 - - - 1797 .type CyPmFtwSetInterval, %function - 1798 CyPmFtwSetInterval: - 1799 .LFB10: -1472:.\Generated_Source\PSoC5/cyPm.c **** { - 1800 .loc 1 1472 0 - 1801 .cfi_startproc - 1802 @ args = 0, pretend = 0, frame = 0 - 1803 @ frame_needed = 0, uses_anonymous_args = 0 - 1804 .LVL69: - 1805 0000 38B5 push {r3, r4, r5, lr} - 1806 .LCFI9: - 1807 .cfi_def_cfa_offset 16 - 1808 .cfi_offset 3, -16 - 1809 .cfi_offset 4, -12 - 1810 .cfi_offset 5, -8 - 1811 .cfi_offset 14, -4 -1474:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); - 1812 .loc 1 1474 0 - 1813 0002 114C ldr r4, .L144 -1472:.\Generated_Source\PSoC5/cyPm.c **** { - 1814 .loc 1 1472 0 - 1815 0004 0546 mov r5, r0 -1474:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); - 1816 .loc 1 1474 0 - 1817 0006 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1818 0008 03F0FD00 and r0, r3, #253 - 1819 .LVL70: - 1820 000c 2070 strb r0, [r4, #0] -1477:.\Generated_Source\PSoC5/cyPm.c **** CyILO_Start100K(); - 1821 .loc 1 1477 0 - 1822 000e FFF7FEFF bl CyILO_Start100K - 1823 .LVL71: -1480:.\Generated_Source\PSoC5/cyPm.c **** if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) - 1824 .loc 1 1480 0 - 1825 0012 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1826 0014 0D4B ldr r3, .L144+4 - 1827 0016 11F0010F tst r1, #1 - 1828 001a 0CD0 beq .L141 -1483:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG0_REG != ftwInterval) - 1829 .loc 1 1483 0 - 1830 001c 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 1831 001e AA42 cmp r2, r5 - 1832 0020 11D0 beq .L140 -1486:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); - 1833 .loc 1 1486 0 - 1834 0022 2078 ldrb r0, [r4, #0] @ zero_extendqisi2 - 1835 0024 00F0FE01 and r1, r0, #254 - 1836 0028 2170 strb r1, [r4, #0] -1487:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG0_REG = ftwInterval; - 1837 .loc 1 1487 0 - 1838 002a 1D70 strb r5, [r3, #0] -1488:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; - 1839 .loc 1 1488 0 - 1840 002c 2378 ldrb r3, [r4, #0] @ zero_extendqisi2 - 1841 002e 43F00102 orr r2, r3, #1 - 1842 0032 2270 strb r2, [r4, #0] - 1843 0034 38BD pop {r3, r4, r5, pc} - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 71 - - - 1844 .L141: -1494:.\Generated_Source\PSoC5/cyPm.c **** if(CY_PM_TW_CFG0_REG != ftwInterval) - 1845 .loc 1 1494 0 - 1846 0036 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 1847 0038 A842 cmp r0, r5 -1497:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG0_REG = ftwInterval; - 1848 .loc 1 1497 0 - 1849 003a 18BF it ne - 1850 003c 1D70 strbne r5, [r3, #0] -1501:.\Generated_Source\PSoC5/cyPm.c **** CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; - 1851 .loc 1 1501 0 - 1852 003e 2178 ldrb r1, [r4, #0] @ zero_extendqisi2 - 1853 0040 41F00103 orr r3, r1, #1 - 1854 0044 2370 strb r3, [r4, #0] - 1855 .L140: - 1856 0046 38BD pop {r3, r4, r5, pc} - 1857 .L145: - 1858 .align 2 - 1859 .L144: - 1860 0048 82430040 .word 1073759106 - 1861 004c 80430040 .word 1073759104 - 1862 .cfi_endproc - 1863 .LFE10: - 1864 .size CyPmFtwSetInterval, .-CyPmFtwSetInterval - 1865 .section .rodata - 1866 .set .LANCHOR1,. + 0 - 1867 .type cyPmImoFreqReg2Mhz, %object - 1868 .size cyPmImoFreqReg2Mhz, 7 - 1869 cyPmImoFreqReg2Mhz: - 1870 0000 0C .byte 12 - 1871 0001 06 .byte 6 - 1872 0002 18 .byte 24 - 1873 0003 03 .byte 3 - 1874 0004 30 .byte 48 - 1875 0005 3E .byte 62 - 1876 0006 4A .byte 74 - 1877 .LC0: - 1878 0007 02 .byte 2 - 1879 0008 01 .byte 1 - 1880 0009 03 .byte 3 - 1881 000a 00 .byte 0 - 1882 000b 04 .byte 4 - 1883 000c 05 .byte 5 - 1884 000d 06 .byte 6 - 1885 .bss - 1886 .align 1 - 1887 .set .LANCHOR0,. + 0 - 1888 .type cyPmBackup, %object - 1889 .size cyPmBackup, 47 - 1890 cyPmBackup: - 1891 0000 00000000 .space 47 - 1891 00000000 - 1891 00000000 - 1891 00000000 - 1891 00000000 - 1892 002f 00 .space 1 - 1893 .type cyPmClockBackup, %object - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 72 - - - 1894 .size cyPmClockBackup, 18 - 1895 cyPmClockBackup: - 1896 0030 00000000 .space 18 - 1896 00000000 - 1896 00000000 - 1896 00000000 - 1896 0000 - 1897 .type interruptStatus.4773, %object - 1898 .size interruptStatus.4773, 1 - 1899 interruptStatus.4773: - 1900 0042 00 .space 1 - 1901 0043 00 .text - 1902 .Letext0: - 1903 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 1904 .file 3 ".\\Generated_Source\\PSoC5\\cyPm.h" - 1905 .file 4 ".\\Generated_Source\\PSoC5\\CyFlash.h" - 1906 .file 5 ".\\Generated_Source\\PSoC5\\CyLib.h" - 1907 .section .debug_info,"",%progbits - 1908 .Ldebug_info0: - 1909 0000 180A0000 .4byte 0xa18 - 1910 0004 0200 .2byte 0x2 - 1911 0006 00000000 .4byte .Ldebug_abbrev0 - 1912 000a 04 .byte 0x4 - 1913 000b 01 .uleb128 0x1 - 1914 000c 5B040000 .4byte .LASF111 - 1915 0010 01 .byte 0x1 - 1916 0011 A4010000 .4byte .LASF112 - 1917 0015 53030000 .4byte .LASF113 - 1918 0019 18000000 .4byte .Ldebug_ranges0+0x18 - 1919 001d 00000000 .4byte 0 - 1920 0021 00000000 .4byte 0 - 1921 0025 00000000 .4byte .Ldebug_line0 - 1922 0029 02 .uleb128 0x2 - 1923 002a 01 .byte 0x1 - 1924 002b 06 .byte 0x6 - 1925 002c 33010000 .4byte .LASF0 - 1926 0030 02 .uleb128 0x2 - 1927 0031 01 .byte 0x1 - 1928 0032 08 .byte 0x8 - 1929 0033 B5040000 .4byte .LASF1 - 1930 0037 02 .uleb128 0x2 - 1931 0038 02 .byte 0x2 - 1932 0039 05 .byte 0x5 - 1933 003a EE040000 .4byte .LASF2 - 1934 003e 02 .uleb128 0x2 - 1935 003f 02 .byte 0x2 - 1936 0040 07 .byte 0x7 - 1937 0041 B7020000 .4byte .LASF3 - 1938 0045 02 .uleb128 0x2 - 1939 0046 04 .byte 0x4 - 1940 0047 05 .byte 0x5 - 1941 0048 6C010000 .4byte .LASF4 - 1942 004c 02 .uleb128 0x2 - 1943 004d 04 .byte 0x4 - 1944 004e 07 .byte 0x7 - 1945 004f 28020000 .4byte .LASF5 - 1946 0053 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 73 - - - 1947 0054 08 .byte 0x8 - 1948 0055 05 .byte 0x5 - 1949 0056 25010000 .4byte .LASF6 - 1950 005a 02 .uleb128 0x2 - 1951 005b 08 .byte 0x8 - 1952 005c 07 .byte 0x7 - 1953 005d A2000000 .4byte .LASF7 - 1954 0061 03 .uleb128 0x3 - 1955 0062 04 .byte 0x4 - 1956 0063 05 .byte 0x5 - 1957 0064 696E7400 .ascii "int\000" - 1958 0068 02 .uleb128 0x2 - 1959 0069 04 .byte 0x4 - 1960 006a 07 .byte 0x7 - 1961 006b FA010000 .4byte .LASF8 - 1962 006f 04 .uleb128 0x4 - 1963 0070 87010000 .4byte .LASF9 - 1964 0074 02 .byte 0x2 - 1965 0075 5B .byte 0x5b - 1966 0076 30000000 .4byte 0x30 - 1967 007a 04 .uleb128 0x4 - 1968 007b 14000000 .4byte .LASF10 - 1969 007f 02 .byte 0x2 - 1970 0080 5C .byte 0x5c - 1971 0081 3E000000 .4byte 0x3e - 1972 0085 04 .uleb128 0x4 - 1973 0086 C4010000 .4byte .LASF11 - 1974 008a 02 .byte 0x2 - 1975 008b 5D .byte 0x5d - 1976 008c 4C000000 .4byte 0x4c - 1977 0090 02 .uleb128 0x2 - 1978 0091 04 .byte 0x4 - 1979 0092 04 .byte 0x4 - 1980 0093 14040000 .4byte .LASF12 - 1981 0097 02 .uleb128 0x2 - 1982 0098 08 .byte 0x8 - 1983 0099 04 .byte 0x4 - 1984 009a 9D010000 .4byte .LASF13 - 1985 009e 02 .uleb128 0x2 - 1986 009f 01 .byte 0x1 - 1987 00a0 08 .byte 0x8 - 1988 00a1 18050000 .4byte .LASF14 - 1989 00a5 04 .uleb128 0x4 - 1990 00a6 38060000 .4byte .LASF15 - 1991 00aa 02 .byte 0x2 - 1992 00ab E8 .byte 0xe8 - 1993 00ac 4C000000 .4byte 0x4c - 1994 00b0 04 .uleb128 0x4 - 1995 00b1 A4040000 .4byte .LASF16 - 1996 00b5 02 .byte 0x2 - 1997 00b6 F0 .byte 0xf0 - 1998 00b7 BB000000 .4byte 0xbb - 1999 00bb 05 .uleb128 0x5 - 2000 00bc 6F000000 .4byte 0x6f - 2001 00c0 02 .uleb128 0x2 - 2002 00c1 04 .byte 0x4 - 2003 00c2 07 .byte 0x7 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 74 - - - 2004 00c3 9D030000 .4byte .LASF17 - 2005 00c7 06 .uleb128 0x6 - 2006 00c8 41020000 .4byte .LASF34 - 2007 00cc 12 .byte 0x12 - 2008 00cd 03 .byte 0x3 - 2009 00ce F1 .byte 0xf1 - 2010 00cf A9010000 .4byte 0x1a9 - 2011 00d3 07 .uleb128 0x7 - 2012 00d4 B9030000 .4byte .LASF18 - 2013 00d8 03 .byte 0x3 - 2014 00d9 F4 .byte 0xf4 - 2015 00da 6F000000 .4byte 0x6f - 2016 00de 02 .byte 0x2 - 2017 00df 23 .byte 0x23 - 2018 00e0 00 .uleb128 0 - 2019 00e1 07 .uleb128 0x7 - 2020 00e2 C0030000 .4byte .LASF19 - 2021 00e6 03 .byte 0x3 - 2022 00e7 F5 .byte 0xf5 - 2023 00e8 6F000000 .4byte 0x6f - 2024 00ec 02 .byte 0x2 - 2025 00ed 23 .byte 0x23 - 2026 00ee 01 .uleb128 0x1 - 2027 00ef 07 .uleb128 0x7 - 2028 00f0 51000000 .4byte .LASF20 - 2029 00f4 03 .byte 0x3 - 2030 00f5 F6 .byte 0xf6 - 2031 00f6 6F000000 .4byte 0x6f - 2032 00fa 02 .byte 0x2 - 2033 00fb 23 .byte 0x23 - 2034 00fc 02 .uleb128 0x2 - 2035 00fd 07 .uleb128 0x7 - 2036 00fe 20020000 .4byte .LASF21 - 2037 0102 03 .byte 0x3 - 2038 0103 F7 .byte 0xf7 - 2039 0104 6F000000 .4byte 0x6f - 2040 0108 02 .byte 0x2 - 2041 0109 23 .byte 0x23 - 2042 010a 03 .uleb128 0x3 - 2043 010b 07 .uleb128 0x7 - 2044 010c E2000000 .4byte .LASF22 - 2045 0110 03 .byte 0x3 - 2046 0111 F8 .byte 0xf8 - 2047 0112 6F000000 .4byte 0x6f - 2048 0116 02 .byte 0x2 - 2049 0117 23 .byte 0x23 - 2050 0118 04 .uleb128 0x4 - 2051 0119 07 .uleb128 0x7 - 2052 011a 41060000 .4byte .LASF23 - 2053 011e 03 .byte 0x3 - 2054 011f F9 .byte 0xf9 - 2055 0120 6F000000 .4byte 0x6f - 2056 0124 02 .byte 0x2 - 2057 0125 23 .byte 0x23 - 2058 0126 05 .uleb128 0x5 - 2059 0127 07 .uleb128 0x7 - 2060 0128 8C060000 .4byte .LASF24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 75 - - - 2061 012c 03 .byte 0x3 - 2062 012d FA .byte 0xfa - 2063 012e 6F000000 .4byte 0x6f - 2064 0132 02 .byte 0x2 - 2065 0133 23 .byte 0x23 - 2066 0134 06 .uleb128 0x6 - 2067 0135 07 .uleb128 0x7 - 2068 0136 0A040000 .4byte .LASF25 - 2069 013a 03 .byte 0x3 - 2070 013b FB .byte 0xfb - 2071 013c 6F000000 .4byte 0x6f - 2072 0140 02 .byte 0x2 - 2073 0141 23 .byte 0x23 - 2074 0142 07 .uleb128 0x7 - 2075 0143 07 .uleb128 0x7 - 2076 0144 3A030000 .4byte .LASF26 - 2077 0148 03 .byte 0x3 - 2078 0149 FC .byte 0xfc - 2079 014a 6F000000 .4byte 0x6f - 2080 014e 02 .byte 0x2 - 2081 014f 23 .byte 0x23 - 2082 0150 08 .uleb128 0x8 - 2083 0151 07 .uleb128 0x7 - 2084 0152 66010000 .4byte .LASF27 - 2085 0156 03 .byte 0x3 - 2086 0157 FD .byte 0xfd - 2087 0158 6F000000 .4byte 0x6f - 2088 015c 02 .byte 0x2 - 2089 015d 23 .byte 0x23 - 2090 015e 09 .uleb128 0x9 - 2091 015f 07 .uleb128 0x7 - 2092 0160 85000000 .4byte .LASF28 - 2093 0164 03 .byte 0x3 - 2094 0165 FE .byte 0xfe - 2095 0166 6F000000 .4byte 0x6f - 2096 016a 02 .byte 0x2 - 2097 016b 23 .byte 0x23 - 2098 016c 0A .uleb128 0xa - 2099 016d 07 .uleb128 0x7 - 2100 016e 3F010000 .4byte .LASF29 - 2101 0172 03 .byte 0x3 - 2102 0173 FF .byte 0xff - 2103 0174 7A000000 .4byte 0x7a - 2104 0178 02 .byte 0x2 - 2105 0179 23 .byte 0x23 - 2106 017a 0C .uleb128 0xc - 2107 017b 08 .uleb128 0x8 - 2108 017c D3040000 .4byte .LASF30 - 2109 0180 03 .byte 0x3 - 2110 0181 0001 .2byte 0x100 - 2111 0183 6F000000 .4byte 0x6f - 2112 0187 02 .byte 0x2 - 2113 0188 23 .byte 0x23 - 2114 0189 0E .uleb128 0xe - 2115 018a 08 .uleb128 0x8 - 2116 018b CB010000 .4byte .LASF31 - 2117 018f 03 .byte 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 76 - - - 2118 0190 0101 .2byte 0x101 - 2119 0192 6F000000 .4byte 0x6f - 2120 0196 02 .byte 0x2 - 2121 0197 23 .byte 0x23 - 2122 0198 0F .uleb128 0xf - 2123 0199 08 .uleb128 0x8 - 2124 019a BB050000 .4byte .LASF32 - 2125 019e 03 .byte 0x3 - 2126 019f 0201 .2byte 0x102 - 2127 01a1 6F000000 .4byte 0x6f - 2128 01a5 02 .byte 0x2 - 2129 01a6 23 .byte 0x23 - 2130 01a7 10 .uleb128 0x10 - 2131 01a8 00 .byte 0 - 2132 01a9 09 .uleb128 0x9 - 2133 01aa 9D020000 .4byte .LASF33 - 2134 01ae 03 .byte 0x3 - 2135 01af 0401 .2byte 0x104 - 2136 01b1 C7000000 .4byte 0xc7 - 2137 01b5 0A .uleb128 0xa - 2138 01b6 6E020000 .4byte .LASF35 - 2139 01ba 2F .byte 0x2f - 2140 01bb 03 .byte 0x3 - 2141 01bc 0701 .2byte 0x107 - 2142 01be EF020000 .4byte 0x2ef - 2143 01c2 08 .uleb128 0x8 - 2144 01c3 18010000 .4byte .LASF36 - 2145 01c7 03 .byte 0x3 - 2146 01c8 0901 .2byte 0x109 - 2147 01ca 6F000000 .4byte 0x6f - 2148 01ce 02 .byte 0x2 - 2149 01cf 23 .byte 0x23 - 2150 01d0 00 .uleb128 0 - 2151 01d1 08 .uleb128 0x8 - 2152 01d2 E2040000 .4byte .LASF37 - 2153 01d6 03 .byte 0x3 - 2154 01d7 0A01 .2byte 0x10a - 2155 01d9 6F000000 .4byte 0x6f - 2156 01dd 02 .byte 0x2 - 2157 01de 23 .byte 0x23 - 2158 01df 01 .uleb128 0x1 - 2159 01e0 08 .uleb128 0x8 - 2160 01e1 0A050000 .4byte .LASF38 - 2161 01e5 03 .byte 0x3 - 2162 01e6 0B01 .2byte 0x10b - 2163 01e8 6F000000 .4byte 0x6f - 2164 01ec 02 .byte 0x2 - 2165 01ed 23 .byte 0x23 - 2166 01ee 02 .uleb128 0x2 - 2167 01ef 08 .uleb128 0x8 - 2168 01f0 91030000 .4byte .LASF39 - 2169 01f4 03 .byte 0x3 - 2170 01f5 0D01 .2byte 0x10d - 2171 01f7 6F000000 .4byte 0x6f - 2172 01fb 02 .byte 0x2 - 2173 01fc 23 .byte 0x23 - 2174 01fd 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 77 - - - 2175 01fe 08 .uleb128 0x8 - 2176 01ff 00030000 .4byte .LASF40 - 2177 0203 03 .byte 0x3 - 2178 0204 1701 .2byte 0x117 - 2179 0206 6F000000 .4byte 0x6f - 2180 020a 02 .byte 0x2 - 2181 020b 23 .byte 0x23 - 2182 020c 04 .uleb128 0x4 - 2183 020d 08 .uleb128 0x8 - 2184 020e 0B030000 .4byte .LASF41 - 2185 0212 03 .byte 0x3 - 2186 0213 1801 .2byte 0x118 - 2187 0215 6F000000 .4byte 0x6f - 2188 0219 02 .byte 0x2 - 2189 021a 23 .byte 0x23 - 2190 021b 05 .uleb128 0x5 - 2191 021c 08 .uleb128 0x8 - 2192 021d 16030000 .4byte .LASF42 - 2193 0221 03 .byte 0x3 - 2194 0222 1901 .2byte 0x119 - 2195 0224 6F000000 .4byte 0x6f - 2196 0228 02 .byte 0x2 - 2197 0229 23 .byte 0x23 - 2198 022a 06 .uleb128 0x6 - 2199 022b 08 .uleb128 0x8 - 2200 022c 39000000 .4byte .LASF43 - 2201 0230 03 .byte 0x3 - 2202 0231 1B01 .2byte 0x11b - 2203 0233 6F000000 .4byte 0x6f - 2204 0237 02 .byte 0x2 - 2205 0238 23 .byte 0x23 - 2206 0239 07 .uleb128 0x7 - 2207 023a 08 .uleb128 0x8 - 2208 023b 45000000 .4byte .LASF44 - 2209 023f 03 .byte 0x3 - 2210 0240 1C01 .2byte 0x11c - 2211 0242 6F000000 .4byte 0x6f - 2212 0246 02 .byte 0x2 - 2213 0247 23 .byte 0x23 - 2214 0248 08 .uleb128 0x8 - 2215 0249 08 .uleb128 0x8 - 2216 024a 07020000 .4byte .LASF45 - 2217 024e 03 .byte 0x3 - 2218 024f 1E01 .2byte 0x11e - 2219 0251 EF020000 .4byte 0x2ef - 2220 0255 02 .byte 0x2 - 2221 0256 23 .byte 0x23 - 2222 0257 09 .uleb128 0x9 - 2223 0258 08 .uleb128 0x8 - 2224 0259 3A020000 .4byte .LASF46 - 2225 025d 03 .byte 0x3 - 2226 025e 2101 .2byte 0x121 - 2227 0260 6F000000 .4byte 0x6f - 2228 0264 02 .byte 0x2 - 2229 0265 23 .byte 0x23 - 2230 0266 25 .uleb128 0x25 - 2231 0267 08 .uleb128 0x8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 78 - - - 2232 0268 83060000 .4byte .LASF47 - 2233 026c 03 .byte 0x3 - 2234 026d 2201 .2byte 0x122 - 2235 026f 6F000000 .4byte 0x6f - 2236 0273 02 .byte 0x2 - 2237 0274 23 .byte 0x23 - 2238 0275 26 .uleb128 0x26 - 2239 0276 08 .uleb128 0x8 - 2240 0277 E2050000 .4byte .LASF48 - 2241 027b 03 .byte 0x3 - 2242 027c 2301 .2byte 0x123 - 2243 027e 6F000000 .4byte 0x6f - 2244 0282 02 .byte 0x2 - 2245 0283 23 .byte 0x23 - 2246 0284 27 .uleb128 0x27 - 2247 0285 08 .uleb128 0x8 - 2248 0286 D9000000 .4byte .LASF49 - 2249 028a 03 .byte 0x3 - 2250 028b 2401 .2byte 0x124 - 2251 028d 6F000000 .4byte 0x6f - 2252 0291 02 .byte 0x2 - 2253 0292 23 .byte 0x23 - 2254 0293 28 .uleb128 0x28 - 2255 0294 08 .uleb128 0x8 - 2256 0295 FF000000 .4byte .LASF50 - 2257 0299 03 .byte 0x3 - 2258 029a 2501 .2byte 0x125 - 2259 029c 6F000000 .4byte 0x6f - 2260 02a0 02 .byte 0x2 - 2261 02a1 23 .byte 0x23 - 2262 02a2 29 .uleb128 0x29 - 2263 02a3 08 .uleb128 0x8 - 2264 02a4 3A040000 .4byte .LASF51 - 2265 02a8 03 .byte 0x3 - 2266 02a9 2601 .2byte 0x126 - 2267 02ab 6F000000 .4byte 0x6f - 2268 02af 02 .byte 0x2 - 2269 02b0 23 .byte 0x23 - 2270 02b1 2A .uleb128 0x2a - 2271 02b2 08 .uleb128 0x8 - 2272 02b3 51060000 .4byte .LASF52 - 2273 02b7 03 .byte 0x3 - 2274 02b8 2701 .2byte 0x127 - 2275 02ba 6F000000 .4byte 0x6f - 2276 02be 02 .byte 0x2 - 2277 02bf 23 .byte 0x23 - 2278 02c0 2B .uleb128 0x2b - 2279 02c1 08 .uleb128 0x8 - 2280 02c2 EF010000 .4byte .LASF53 - 2281 02c6 03 .byte 0x3 - 2282 02c7 2901 .2byte 0x129 - 2283 02c9 6F000000 .4byte 0x6f - 2284 02cd 02 .byte 0x2 - 2285 02ce 23 .byte 0x23 - 2286 02cf 2C .uleb128 0x2c - 2287 02d0 08 .uleb128 0x8 - 2288 02d1 45050000 .4byte .LASF54 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 79 - - - 2289 02d5 03 .byte 0x3 - 2290 02d6 2A01 .2byte 0x12a - 2291 02d8 6F000000 .4byte 0x6f - 2292 02dc 02 .byte 0x2 - 2293 02dd 23 .byte 0x23 - 2294 02de 2D .uleb128 0x2d - 2295 02df 08 .uleb128 0x8 - 2296 02e0 2E030000 .4byte .LASF55 - 2297 02e4 03 .byte 0x3 - 2298 02e5 2C01 .2byte 0x12c - 2299 02e7 6F000000 .4byte 0x6f - 2300 02eb 02 .byte 0x2 - 2301 02ec 23 .byte 0x23 - 2302 02ed 2E .uleb128 0x2e - 2303 02ee 00 .byte 0 - 2304 02ef 0B .uleb128 0xb - 2305 02f0 6F000000 .4byte 0x6f - 2306 02f4 FF020000 .4byte 0x2ff - 2307 02f8 0C .uleb128 0xc - 2308 02f9 C0000000 .4byte 0xc0 - 2309 02fd 1B .byte 0x1b - 2310 02fe 00 .byte 0 - 2311 02ff 09 .uleb128 0x9 - 2312 0300 5E000000 .4byte .LASF56 - 2313 0304 03 .byte 0x3 - 2314 0305 2E01 .2byte 0x12e - 2315 0307 B5010000 .4byte 0x1b5 - 2316 030b 0D .uleb128 0xd - 2317 030c F8040000 .4byte .LASF57 - 2318 0310 01 .byte 0x1 - 2319 0311 F805 .2byte 0x5f8 - 2320 0313 01 .byte 0x1 - 2321 0314 00000000 .4byte .LFB11 - 2322 0318 64010000 .4byte .LFE11 - 2323 031c 00000000 .4byte .LLST0 - 2324 0320 01 .byte 0x1 - 2325 0321 0E .uleb128 0xe - 2326 0322 27000000 .4byte .LASF58 - 2327 0326 01 .byte 0x1 - 2328 0327 7B06 .2byte 0x67b - 2329 0329 01 .byte 0x1 - 2330 032a 00000000 .4byte .LFB12 - 2331 032e A4000000 .4byte .LFE12 - 2332 0332 02 .byte 0x2 - 2333 0333 7D .byte 0x7d - 2334 0334 00 .sleb128 0 - 2335 0335 01 .byte 0x1 - 2336 0336 0F .uleb128 0xf - 2337 0337 01 .byte 0x1 - 2338 0338 44030000 .4byte .LASF59 - 2339 033c 01 .byte 0x1 - 2340 033d 50 .byte 0x50 - 2341 033e 01 .byte 0x1 - 2342 033f 00000000 .4byte .LFB0 - 2343 0343 B4010000 .4byte .LFE0 - 2344 0347 20000000 .4byte .LLST1 - 2345 034b 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 80 - - - 2346 034c F1030000 .4byte 0x3f1 - 2347 0350 10 .uleb128 0x10 - 2348 0351 38000000 .4byte .LVL0 - 2349 0355 67080000 .4byte 0x867 - 2350 0359 64030000 .4byte 0x364 - 2351 035d 11 .uleb128 0x11 - 2352 035e 01 .byte 0x1 - 2353 035f 50 .byte 0x50 - 2354 0360 02 .byte 0x2 - 2355 0361 08 .byte 0x8 - 2356 0362 37 .byte 0x37 - 2357 0363 00 .byte 0 - 2358 0364 10 .uleb128 0x10 - 2359 0365 62000000 .4byte .LVL1 - 2360 0369 7B080000 .4byte 0x87b - 2361 036d 77030000 .4byte 0x377 - 2362 0371 11 .uleb128 0x11 - 2363 0372 01 .byte 0x1 - 2364 0373 50 .byte 0x50 - 2365 0374 01 .byte 0x1 - 2366 0375 34 .byte 0x34 - 2367 0376 00 .byte 0 - 2368 0377 12 .uleb128 0x12 - 2369 0378 80000000 .4byte .LVL2 - 2370 037c 8F080000 .4byte 0x88f - 2371 0380 10 .uleb128 0x10 - 2372 0381 AA000000 .4byte .LVL3 - 2373 0385 A3080000 .4byte 0x8a3 - 2374 0389 93030000 .4byte 0x393 - 2375 038d 11 .uleb128 0x11 - 2376 038e 01 .byte 0x1 - 2377 038f 50 .byte 0x50 - 2378 0390 01 .byte 0x1 - 2379 0391 30 .byte 0x30 - 2380 0392 00 .byte 0 - 2381 0393 12 .uleb128 0x12 - 2382 0394 DC000000 .4byte .LVL4 - 2383 0398 B7080000 .4byte 0x8b7 - 2384 039c 10 .uleb128 0x10 - 2385 039d EE000000 .4byte .LVL5 - 2386 03a1 C1080000 .4byte 0x8c1 - 2387 03a5 AF030000 .4byte 0x3af - 2388 03a9 11 .uleb128 0x11 - 2389 03aa 01 .byte 0x1 - 2390 03ab 50 .byte 0x50 - 2391 03ac 01 .byte 0x1 - 2392 03ad 30 .byte 0x30 - 2393 03ae 00 .byte 0 - 2394 03af 10 .uleb128 0x10 - 2395 03b0 04010000 .4byte .LVL6 - 2396 03b4 D5080000 .4byte 0x8d5 - 2397 03b8 C2030000 .4byte 0x3c2 - 2398 03bc 11 .uleb128 0x11 - 2399 03bd 01 .byte 0x1 - 2400 03be 50 .byte 0x50 - 2401 03bf 01 .byte 0x1 - 2402 03c0 30 .byte 0x30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 81 - - - 2403 03c1 00 .byte 0 - 2404 03c2 10 .uleb128 0x10 - 2405 03c3 1E010000 .4byte .LVL7 - 2406 03c7 E9080000 .4byte 0x8e9 - 2407 03cb D5030000 .4byte 0x3d5 - 2408 03cf 11 .uleb128 0x11 - 2409 03d0 01 .byte 0x1 - 2410 03d1 50 .byte 0x50 - 2411 03d2 01 .byte 0x1 - 2412 03d3 30 .byte 0x30 - 2413 03d4 00 .byte 0 - 2414 03d5 12 .uleb128 0x12 - 2415 03d6 2E010000 .4byte .LVL8 - 2416 03da 67080000 .4byte 0x867 - 2417 03de 12 .uleb128 0x12 - 2418 03df 44010000 .4byte .LVL9 - 2419 03e3 FD080000 .4byte 0x8fd - 2420 03e7 12 .uleb128 0x12 - 2421 03e8 60010000 .4byte .LVL10 - 2422 03ec 07090000 .4byte 0x907 - 2423 03f0 00 .byte 0 - 2424 03f1 13 .uleb128 0x13 - 2425 03f2 01 .byte 0x1 - 2426 03f3 90000000 .4byte .LASF60 - 2427 03f7 01 .byte 0x1 - 2428 03f8 0001 .2byte 0x100 - 2429 03fa 01 .byte 0x1 - 2430 03fb 00000000 .4byte .LFB1 - 2431 03ff 08020000 .4byte .LFE1 - 2432 0403 40000000 .4byte .LLST2 - 2433 0407 01 .byte 0x1 - 2434 0408 3B050000 .4byte 0x53b - 2435 040c 14 .uleb128 0x14 - 2436 040d DB050000 .4byte .LASF61 - 2437 0411 01 .byte 0x1 - 2438 0412 0201 .2byte 0x102 - 2439 0414 A5000000 .4byte 0xa5 - 2440 0418 10 .byte 0x10 - 2441 0419 15 .uleb128 0x15 - 2442 041a 6900 .ascii "i\000" - 2443 041c 01 .byte 0x1 - 2444 041d 0301 .2byte 0x103 - 2445 041f 7A000000 .4byte 0x7a - 2446 0423 16 .uleb128 0x16 - 2447 0424 21030000 .4byte .LASF62 - 2448 0428 01 .byte 0x1 - 2449 0429 0401 .2byte 0x104 - 2450 042b 7A000000 .4byte 0x7a - 2451 042f 60000000 .4byte .LLST3 - 2452 0433 17 .uleb128 0x17 - 2453 0434 A6030000 .4byte .LASF63 - 2454 0438 01 .byte 0x1 - 2455 0439 0801 .2byte 0x108 - 2456 043b 4B050000 .4byte 0x54b - 2457 043f 02 .byte 0x2 - 2458 0440 91 .byte 0x91 - 2459 0441 70 .sleb128 -16 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 82 - - - 2460 0442 10 .uleb128 0x10 - 2461 0443 34000000 .4byte .LVL12 - 2462 0447 11090000 .4byte 0x911 - 2463 044b 66040000 .4byte 0x466 - 2464 044f 11 .uleb128 0x11 - 2465 0450 01 .byte 0x1 - 2466 0451 50 .byte 0x50 - 2467 0452 12 .byte 0x12 - 2468 0453 74 .byte 0x74 - 2469 0454 00 .sleb128 0 - 2470 0455 37 .byte 0x37 - 2471 0456 1A .byte 0x1a - 2472 0457 03 .byte 0x3 - 2473 0458 00000000 .4byte .LANCHOR1 - 2474 045c 22 .byte 0x22 - 2475 045d 94 .byte 0x94 - 2476 045e 01 .byte 0x1 - 2477 045f 08 .byte 0x8 - 2478 0460 FF .byte 0xff - 2479 0461 1A .byte 0x1a - 2480 0462 08 .byte 0x8 - 2481 0463 4B .byte 0x4b - 2482 0464 1E .byte 0x1e - 2483 0465 00 .byte 0 - 2484 0466 10 .uleb128 0x10 - 2485 0467 50000000 .4byte .LVL13 - 2486 046b 67080000 .4byte 0x867 - 2487 046f 7A040000 .4byte 0x47a - 2488 0473 11 .uleb128 0x11 - 2489 0474 01 .byte 0x1 - 2490 0475 50 .byte 0x50 - 2491 0476 02 .byte 0x2 - 2492 0477 08 .byte 0x8 - 2493 0478 37 .byte 0x37 - 2494 0479 00 .byte 0 - 2495 047a 10 .uleb128 0x10 - 2496 047b 62000000 .4byte .LVL14 - 2497 047f 25090000 .4byte 0x925 - 2498 0483 8D040000 .4byte 0x48d - 2499 0487 11 .uleb128 0x11 - 2500 0488 01 .byte 0x1 - 2501 0489 50 .byte 0x50 - 2502 048a 01 .byte 0x1 - 2503 048b 30 .byte 0x30 - 2504 048c 00 .byte 0 - 2505 048d 12 .uleb128 0x12 - 2506 048e 7C000000 .4byte .LVL16 - 2507 0492 11090000 .4byte 0x911 - 2508 0496 12 .uleb128 0x12 - 2509 0497 9E000000 .4byte .LVL17 - 2510 049b C1080000 .4byte 0x8c1 - 2511 049f 12 .uleb128 0x12 - 2512 04a0 A6000000 .4byte .LVL18 - 2513 04a4 D5080000 .4byte 0x8d5 - 2514 04a8 10 .uleb128 0x10 - 2515 04a9 CC000000 .4byte .LVL19 - 2516 04ad 7B080000 .4byte 0x87b - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 83 - - - 2517 04b1 BB040000 .4byte 0x4bb - 2518 04b5 11 .uleb128 0x11 - 2519 04b6 01 .byte 0x1 - 2520 04b7 50 .byte 0x50 - 2521 04b8 01 .byte 0x1 - 2522 04b9 38 .byte 0x38 - 2523 04ba 00 .byte 0 - 2524 04bb 12 .uleb128 0x12 - 2525 04bc DE000000 .4byte .LVL20 - 2526 04c0 7B080000 .4byte 0x87b - 2527 04c4 10 .uleb128 0x10 - 2528 04c5 16010000 .4byte .LVL21 - 2529 04c9 8F080000 .4byte 0x88f - 2530 04cd DA040000 .4byte 0x4da - 2531 04d1 11 .uleb128 0x11 - 2532 04d2 01 .byte 0x1 - 2533 04d3 50 .byte 0x50 - 2534 04d4 04 .byte 0x4 - 2535 04d5 74 .byte 0x74 - 2536 04d6 00 .sleb128 0 - 2537 04d7 40 .byte 0x40 - 2538 04d8 1A .byte 0x1a - 2539 04d9 00 .byte 0 - 2540 04da 12 .uleb128 0x12 - 2541 04db 2E010000 .4byte .LVL22 - 2542 04df 3D090000 .4byte 0x93d - 2543 04e3 12 .uleb128 0x12 - 2544 04e4 38010000 .4byte .LVL23 - 2545 04e8 A3080000 .4byte 0x8a3 - 2546 04ec 12 .uleb128 0x12 - 2547 04ed 44010000 .4byte .LVL24 - 2548 04f1 47090000 .4byte 0x947 - 2549 04f5 10 .uleb128 0x10 - 2550 04f6 70010000 .4byte .LVL25 - 2551 04fa 51090000 .4byte 0x951 - 2552 04fe 08050000 .4byte 0x508 - 2553 0502 11 .uleb128 0x11 - 2554 0503 01 .byte 0x1 - 2555 0504 50 .byte 0x50 - 2556 0505 01 .byte 0x1 - 2557 0506 30 .byte 0x30 - 2558 0507 00 .byte 0 - 2559 0508 10 .uleb128 0x10 - 2560 0509 84010000 .4byte .LVL26 - 2561 050d 11090000 .4byte 0x911 - 2562 0511 1F050000 .4byte 0x51f - 2563 0515 11 .uleb128 0x11 - 2564 0516 01 .byte 0x1 - 2565 0517 50 .byte 0x50 - 2566 0518 05 .byte 0x5 - 2567 0519 74 .byte 0x74 - 2568 051a 00 .sleb128 0 - 2569 051b 08 .byte 0x8 - 2570 051c FA .byte 0xfa - 2571 051d 1E .byte 0x1e - 2572 051e 00 .byte 0 - 2573 051f 12 .uleb128 0x12 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 84 - - - 2574 0520 9E010000 .4byte .LVL27 - 2575 0524 C1080000 .4byte 0x8c1 - 2576 0528 12 .uleb128 0x12 - 2577 0529 A6010000 .4byte .LVL28 - 2578 052d D5080000 .4byte 0x8d5 - 2579 0531 12 .uleb128 0x12 - 2580 0532 BE010000 .4byte .LVL32 - 2581 0536 E9080000 .4byte 0x8e9 - 2582 053a 00 .byte 0 - 2583 053b 0B .uleb128 0xb - 2584 053c 6F000000 .4byte 0x6f - 2585 0540 4B050000 .4byte 0x54b - 2586 0544 0C .uleb128 0xc - 2587 0545 C0000000 .4byte 0xc0 - 2588 0549 06 .byte 0x6 - 2589 054a 00 .byte 0 - 2590 054b 18 .uleb128 0x18 - 2591 054c 3B050000 .4byte 0x53b - 2592 0550 13 .uleb128 0x13 - 2593 0551 01 .byte 0x1 - 2594 0552 42040000 .4byte .LASF64 - 2595 0556 01 .byte 0x1 - 2596 0557 4702 .2byte 0x247 - 2597 0559 01 .byte 0x1 - 2598 055a 00000000 .4byte .LFB2 - 2599 055e 60000000 .4byte .LFE2 - 2600 0562 8C000000 .4byte .LLST4 - 2601 0566 01 .byte 0x1 - 2602 0567 8C050000 .4byte 0x58c - 2603 056b 19 .uleb128 0x19 - 2604 056c 1A060000 .4byte .LASF65 - 2605 0570 01 .byte 0x1 - 2606 0571 4702 .2byte 0x247 - 2607 0573 7A000000 .4byte 0x7a - 2608 0577 AC000000 .4byte .LLST5 - 2609 057b 19 .uleb128 0x19 - 2610 057c D7030000 .4byte .LASF66 - 2611 0580 01 .byte 0x1 - 2612 0581 4702 .2byte 0x247 - 2613 0583 7A000000 .4byte 0x7a - 2614 0587 CD000000 .4byte .LLST6 - 2615 058b 00 .byte 0 - 2616 058c 13 .uleb128 0x13 - 2617 058d 01 .byte 0x1 - 2618 058e 30040000 .4byte .LASF67 - 2619 0592 01 .byte 0x1 - 2620 0593 1303 .2byte 0x313 - 2621 0595 01 .byte 0x1 - 2622 0596 00000000 .4byte .LFB3 - 2623 059a D8000000 .4byte .LFE3 - 2624 059e EE000000 .4byte .LLST7 - 2625 05a2 01 .byte 0x1 - 2626 05a3 FD050000 .4byte 0x5fd - 2627 05a7 19 .uleb128 0x19 - 2628 05a8 1A060000 .4byte .LASF65 - 2629 05ac 01 .byte 0x1 - 2630 05ad 1303 .2byte 0x313 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 85 - - - 2631 05af 6F000000 .4byte 0x6f - 2632 05b3 0E010000 .4byte .LLST8 - 2633 05b7 19 .uleb128 0x19 - 2634 05b8 D7030000 .4byte .LASF66 - 2635 05bc 01 .byte 0x1 - 2636 05bd 1303 .2byte 0x313 - 2637 05bf 7A000000 .4byte 0x7a - 2638 05c3 2F010000 .4byte .LLST9 - 2639 05c7 16 .uleb128 0x16 - 2640 05c8 49010000 .4byte .LASF68 - 2641 05cc 01 .byte 0x1 - 2642 05cd 1503 .2byte 0x315 - 2643 05cf 6F000000 .4byte 0x6f - 2644 05d3 50010000 .4byte .LLST10 - 2645 05d7 12 .uleb128 0x12 - 2646 05d8 08000000 .4byte .LVL37 - 2647 05dc 69090000 .4byte 0x969 - 2648 05e0 12 .uleb128 0x12 - 2649 05e1 22000000 .4byte .LVL40 - 2650 05e5 0B030000 .4byte 0x30b - 2651 05e9 12 .uleb128 0x12 - 2652 05ea A2000000 .4byte .LVL41 - 2653 05ee 21030000 .4byte 0x321 - 2654 05f2 1A .uleb128 0x1a - 2655 05f3 BE000000 .4byte .LVL43 - 2656 05f7 01 .byte 0x1 - 2657 05f8 77090000 .4byte 0x977 - 2658 05fc 00 .byte 0 - 2659 05fd 1B .uleb128 0x1b - 2660 05fe 0B060000 .4byte .LASF69 - 2661 0602 01 .byte 0x1 - 2662 0603 CF04 .2byte 0x4cf - 2663 0605 01 .byte 0x1 - 2664 0606 01 .byte 0x1 - 2665 0607 1B .uleb128 0x1b - 2666 0608 B9000000 .4byte .LASF70 - 2667 060c 01 .byte 0x1 - 2668 060d C806 .2byte 0x6c8 - 2669 060f 01 .byte 0x1 - 2670 0610 01 .byte 0x1 - 2671 0611 1B .uleb128 0x1b - 2672 0612 DB010000 .4byte .LASF71 - 2673 0616 01 .byte 0x1 - 2674 0617 2905 .2byte 0x529 - 2675 0619 01 .byte 0x1 - 2676 061a 01 .byte 0x1 - 2677 061b 1B .uleb128 0x1b - 2678 061c 75010000 .4byte .LASF72 - 2679 0620 01 .byte 0x1 - 2680 0621 0707 .2byte 0x707 - 2681 0623 01 .byte 0x1 - 2682 0624 01 .byte 0x1 - 2683 0625 13 .uleb128 0x13 - 2684 0626 01 .byte 0x1 - 2685 0627 55050000 .4byte .LASF73 - 2686 062b 01 .byte 0x1 - 2687 062c 2304 .2byte 0x423 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 86 - - - 2688 062e 01 .byte 0x1 - 2689 062f 00000000 .4byte .LFB4 - 2690 0633 38020000 .4byte .LFE4 - 2691 0637 84010000 .4byte .LLST11 - 2692 063b 01 .byte 0x1 - 2693 063c 2E070000 .4byte 0x72e - 2694 0640 16 .uleb128 0x16 - 2695 0641 49010000 .4byte .LASF68 - 2696 0645 01 .byte 0x1 - 2697 0646 2504 .2byte 0x425 - 2698 0648 6F000000 .4byte 0x6f - 2699 064c A4010000 .4byte .LLST12 - 2700 0650 1C .uleb128 0x1c - 2701 0651 FD050000 .4byte 0x5fd - 2702 0655 1A000000 .4byte .LBB10 - 2703 0659 00000000 .4byte .Ldebug_ranges0+0 - 2704 065d 01 .byte 0x1 - 2705 065e 3F04 .2byte 0x43f - 2706 0660 B1060000 .4byte 0x6b1 - 2707 0664 1D .uleb128 0x1d - 2708 0665 07060000 .4byte 0x607 - 2709 0669 6C000000 .4byte .LBB12 - 2710 066d EC000000 .4byte .LBE12 - 2711 0671 01 .byte 0x1 - 2712 0672 0405 .2byte 0x504 - 2713 0674 94060000 .4byte 0x694 - 2714 0678 12 .uleb128 0x12 - 2715 0679 9A000000 .4byte .LVL48 - 2716 067d 8B090000 .4byte 0x98b - 2717 0681 12 .uleb128 0x12 - 2718 0682 CA000000 .4byte .LVL49 - 2719 0686 95090000 .4byte 0x995 - 2720 068a 12 .uleb128 0x12 - 2721 068b E6000000 .4byte .LVL50 - 2722 068f 9F090000 .4byte 0x99f - 2723 0693 00 .byte 0 - 2724 0694 10 .uleb128 0x10 - 2725 0695 3C000000 .4byte .LVL47 - 2726 0699 A9090000 .4byte 0x9a9 - 2727 069d A7060000 .4byte 0x6a7 - 2728 06a1 11 .uleb128 0x11 - 2729 06a2 01 .byte 0x1 - 2730 06a3 50 .byte 0x50 - 2731 06a4 01 .byte 0x1 - 2732 06a5 31 .byte 0x31 - 2733 06a6 00 .byte 0 - 2734 06a7 12 .uleb128 0x12 - 2735 06a8 F2000000 .4byte .LVL51 - 2736 06ac 0B030000 .4byte 0x30b - 2737 06b0 00 .byte 0 - 2738 06b1 1D .uleb128 0x1d - 2739 06b2 11060000 .4byte 0x611 - 2740 06b6 78010000 .4byte .LBB16 - 2741 06ba EA010000 .4byte .LBE16 - 2742 06be 01 .byte 0x1 - 2743 06bf 7A04 .2byte 0x47a - 2744 06c1 1A070000 .4byte 0x71a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 87 - - - 2745 06c5 1D .uleb128 0x1d - 2746 06c6 1B060000 .4byte 0x61b - 2747 06ca 78010000 .4byte .LBB18 - 2748 06ce B0010000 .4byte .LBE18 - 2749 06d2 01 .byte 0x1 - 2750 06d3 2C05 .2byte 0x52c - 2751 06d5 F5060000 .4byte 0x6f5 - 2752 06d9 12 .uleb128 0x12 - 2753 06da 8E010000 .4byte .LVL52 - 2754 06de C1090000 .4byte 0x9c1 - 2755 06e2 12 .uleb128 0x12 - 2756 06e3 A4010000 .4byte .LVL53 - 2757 06e7 DA090000 .4byte 0x9da - 2758 06eb 12 .uleb128 0x12 - 2759 06ec B0010000 .4byte .LVL54 - 2760 06f0 F3090000 .4byte 0x9f3 - 2761 06f4 00 .byte 0 - 2762 06f5 12 .uleb128 0x12 - 2763 06f6 B6010000 .4byte .LVL55 - 2764 06fa 21030000 .4byte 0x321 - 2765 06fe 12 .uleb128 0x12 - 2766 06ff C0010000 .4byte .LVL56 - 2767 0703 FD090000 .4byte 0x9fd - 2768 0707 12 .uleb128 0x12 - 2769 0708 CA010000 .4byte .LVL57 - 2770 070c 070A0000 .4byte 0xa07 - 2771 0710 12 .uleb128 0x12 - 2772 0711 D0010000 .4byte .LVL58 - 2773 0715 A9090000 .4byte 0x9a9 - 2774 0719 00 .byte 0 - 2775 071a 12 .uleb128 0x12 - 2776 071b 06000000 .4byte .LVL44 - 2777 071f 69090000 .4byte 0x969 - 2778 0723 1A .uleb128 0x1a - 2779 0724 04020000 .4byte .LVL60 - 2780 0728 01 .byte 0x1 - 2781 0729 77090000 .4byte 0x977 - 2782 072d 00 .byte 0 - 2783 072e 1E .uleb128 0x1e - 2784 072f 01 .byte 0x1 - 2785 0730 98050000 .4byte .LASF114 - 2786 0734 01 .byte 0x1 - 2787 0735 A304 .2byte 0x4a3 - 2788 0737 01 .byte 0x1 - 2789 0738 6F000000 .4byte 0x6f - 2790 073c 00000000 .4byte .LFB5 - 2791 0740 2C000000 .4byte .LFE5 - 2792 0744 D8010000 .4byte .LLST13 - 2793 0748 01 .byte 0x1 - 2794 0749 A0070000 .4byte 0x7a0 - 2795 074d 19 .uleb128 0x19 - 2796 074e EA010000 .4byte .LASF74 - 2797 0752 01 .byte 0x1 - 2798 0753 A304 .2byte 0x4a3 - 2799 0755 6F000000 .4byte 0x6f - 2800 0759 F8010000 .4byte .LLST14 - 2801 075d 17 .uleb128 0x17 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 88 - - - 2802 075e 96060000 .4byte .LASF75 - 2803 0762 01 .byte 0x1 - 2804 0763 A504 .2byte 0x4a5 - 2805 0765 6F000000 .4byte 0x6f - 2806 0769 05 .byte 0x5 - 2807 076a 03 .byte 0x3 - 2808 076b 42000000 .4byte interruptStatus.4773 - 2809 076f 16 .uleb128 0x16 - 2810 0770 49010000 .4byte .LASF68 - 2811 0774 01 .byte 0x1 - 2812 0775 A604 .2byte 0x4a6 - 2813 0777 6F000000 .4byte 0x6f - 2814 077b 19020000 .4byte .LLST15 - 2815 077f 17 .uleb128 0x17 - 2816 0780 CF000000 .4byte .LASF76 - 2817 0784 01 .byte 0x1 - 2818 0785 A704 .2byte 0x4a7 - 2819 0787 6F000000 .4byte 0x6f - 2820 078b 01 .byte 0x1 - 2821 078c 54 .byte 0x54 - 2822 078d 12 .uleb128 0x12 - 2823 078e 08000000 .4byte .LVL62 - 2824 0792 69090000 .4byte 0x969 - 2825 0796 12 .uleb128 0x12 - 2826 0797 20000000 .4byte .LVL64 - 2827 079b 77090000 .4byte 0x977 - 2828 079f 00 .byte 0 - 2829 07a0 13 .uleb128 0x13 - 2830 07a1 01 .byte 0x1 - 2831 07a2 C8050000 .4byte .LASF77 - 2832 07a6 01 .byte 0x1 - 2833 07a7 6605 .2byte 0x566 - 2834 07a9 01 .byte 0x1 - 2835 07aa 00000000 .4byte .LFB8 - 2836 07ae 54000000 .4byte .LFE8 - 2837 07b2 2C020000 .4byte .LLST16 - 2838 07b6 01 .byte 0x1 - 2839 07b7 D5070000 .4byte 0x7d5 - 2840 07bb 19 .uleb128 0x19 - 2841 07bc CA020000 .4byte .LASF78 - 2842 07c0 01 .byte 0x1 - 2843 07c1 6605 .2byte 0x566 - 2844 07c3 6F000000 .4byte 0x6f - 2845 07c7 4C020000 .4byte .LLST17 - 2846 07cb 12 .uleb128 0x12 - 2847 07cc 12000000 .4byte .LVL67 - 2848 07d0 FD090000 .4byte 0x9fd - 2849 07d4 00 .byte 0 - 2850 07d5 13 .uleb128 0x13 - 2851 07d6 01 .byte 0x1 - 2852 07d7 A9040000 .4byte .LASF79 - 2853 07db 01 .byte 0x1 - 2854 07dc 9A05 .2byte 0x59a - 2855 07de 01 .byte 0x1 - 2856 07df 00000000 .4byte .LFB9 - 2857 07e3 2C000000 .4byte .LFE9 - 2858 07e7 6D020000 .4byte .LLST18 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 89 - - - 2859 07eb 01 .byte 0x1 - 2860 07ec FA070000 .4byte 0x7fa - 2861 07f0 12 .uleb128 0x12 - 2862 07f1 0E000000 .4byte .LVL68 - 2863 07f5 110A0000 .4byte 0xa11 - 2864 07f9 00 .byte 0 - 2865 07fa 13 .uleb128 0x13 - 2866 07fb 01 .byte 0x1 - 2867 07fc EC000000 .4byte .LASF80 - 2868 0800 01 .byte 0x1 - 2869 0801 BF05 .2byte 0x5bf - 2870 0803 01 .byte 0x1 - 2871 0804 00000000 .4byte .LFB10 - 2872 0808 50000000 .4byte .LFE10 - 2873 080c 8D020000 .4byte .LLST19 - 2874 0810 01 .byte 0x1 - 2875 0811 2F080000 .4byte 0x82f - 2876 0815 19 .uleb128 0x19 - 2877 0816 79050000 .4byte .LASF81 - 2878 081a 01 .byte 0x1 - 2879 081b BF05 .2byte 0x5bf - 2880 081d 6F000000 .4byte 0x6f - 2881 0821 AD020000 .4byte .LLST20 - 2882 0825 12 .uleb128 0x12 - 2883 0826 12000000 .4byte .LVL71 - 2884 082a 070A0000 .4byte 0xa07 - 2885 082e 00 .byte 0 - 2886 082f 1F .uleb128 0x1f - 2887 0830 78060000 .4byte .LASF82 - 2888 0834 01 .byte 0x1 - 2889 0835 1F .byte 0x1f - 2890 0836 FF020000 .4byte 0x2ff - 2891 083a 05 .byte 0x5 - 2892 083b 03 .byte 0x3 - 2893 083c 00000000 .4byte cyPmBackup - 2894 0840 1F .uleb128 0x1f - 2895 0841 C3040000 .4byte .LASF83 - 2896 0845 01 .byte 0x1 - 2897 0846 20 .byte 0x20 - 2898 0847 A9010000 .4byte 0x1a9 - 2899 084b 05 .byte 0x5 - 2900 084c 03 .byte 0x3 - 2901 084d 30000000 .4byte cyPmClockBackup - 2902 0851 1F .uleb128 0x1f - 2903 0852 85050000 .4byte .LASF84 - 2904 0856 01 .byte 0x1 - 2905 0857 23 .byte 0x23 - 2906 0858 62080000 .4byte 0x862 - 2907 085c 05 .byte 0x5 - 2908 085d 03 .byte 0x3 - 2909 085e 00000000 .4byte cyPmImoFreqReg2Mhz - 2910 0862 18 .uleb128 0x18 - 2911 0863 3B050000 .4byte 0x53b - 2912 0867 20 .uleb128 0x20 - 2913 0868 01 .byte 0x1 - 2914 0869 63050000 .4byte .LASF85 - 2915 086d 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 90 - - - 2916 086e 4B .byte 0x4b - 2917 086f 01 .byte 0x1 - 2918 0870 01 .byte 0x1 - 2919 0871 7B080000 .4byte 0x87b - 2920 0875 21 .uleb128 0x21 - 2921 0876 6F000000 .4byte 0x6f - 2922 087a 00 .byte 0 - 2923 087b 20 .uleb128 0x20 - 2924 087c 01 .byte 0x1 - 2925 087d E9050000 .4byte .LASF86 - 2926 0881 05 .byte 0x5 - 2927 0882 49 .byte 0x49 - 2928 0883 01 .byte 0x1 - 2929 0884 01 .byte 0x1 - 2930 0885 8F080000 .4byte 0x88f - 2931 0889 21 .uleb128 0x21 - 2932 088a 6F000000 .4byte 0x6f - 2933 088e 00 .byte 0 - 2934 088f 20 .uleb128 0x20 - 2935 0890 01 .byte 0x1 - 2936 0891 1B000000 .4byte .LASF87 - 2937 0895 05 .byte 0x5 - 2938 0896 47 .byte 0x47 - 2939 0897 01 .byte 0x1 - 2940 0898 01 .byte 0x1 - 2941 0899 A3080000 .4byte 0x8a3 - 2942 089d 21 .uleb128 0x21 - 2943 089e 6F000000 .4byte 0x6f - 2944 08a2 00 .byte 0 - 2945 08a3 20 .uleb128 0x20 - 2946 08a4 01 .byte 0x1 - 2947 08a5 10020000 .4byte .LASF88 - 2948 08a9 05 .byte 0x5 - 2949 08aa 4A .byte 0x4a - 2950 08ab 01 .byte 0x1 - 2951 08ac 01 .byte 0x1 - 2952 08ad B7080000 .4byte 0x8b7 - 2953 08b1 21 .uleb128 0x21 - 2954 08b2 6F000000 .4byte 0x6f - 2955 08b6 00 .byte 0 - 2956 08b7 22 .uleb128 0x22 - 2957 08b8 01 .byte 0x1 - 2958 08b9 1D050000 .4byte .LASF92 - 2959 08bd 05 .byte 0x5 - 2960 08be 4C .byte 0x4c - 2961 08bf 01 .byte 0x1 - 2962 08c0 01 .byte 0x1 - 2963 08c1 20 .uleb128 0x20 - 2964 08c2 01 .byte 0x1 - 2965 08c3 F3030000 .4byte .LASF89 - 2966 08c7 05 .byte 0x5 - 2967 08c8 4F .byte 0x4f - 2968 08c9 01 .byte 0x1 - 2969 08ca 01 .byte 0x1 - 2970 08cb D5080000 .4byte 0x8d5 - 2971 08cf 21 .uleb128 0x21 - 2972 08d0 6F000000 .4byte 0x6f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 91 - - - 2973 08d4 00 .byte 0 - 2974 08d5 20 .uleb128 0x20 - 2975 08d6 01 .byte 0x1 - 2976 08d7 EA020000 .4byte .LASF90 - 2977 08db 05 .byte 0x5 - 2978 08dc 4E .byte 0x4e - 2979 08dd 01 .byte 0x1 - 2980 08de 01 .byte 0x1 - 2981 08df E9080000 .4byte 0x8e9 - 2982 08e3 21 .uleb128 0x21 - 2983 08e4 6F000000 .4byte 0x6f - 2984 08e8 00 .byte 0 - 2985 08e9 20 .uleb128 0x20 - 2986 08ea 01 .byte 0x1 - 2987 08eb A7050000 .4byte .LASF91 - 2988 08ef 05 .byte 0x5 - 2989 08f0 50 .byte 0x50 - 2990 08f1 01 .byte 0x1 - 2991 08f2 01 .byte 0x1 - 2992 08f3 FD080000 .4byte 0x8fd - 2993 08f7 21 .uleb128 0x21 - 2994 08f8 7A000000 .4byte 0x7a - 2995 08fc 00 .byte 0 - 2996 08fd 22 .uleb128 0x22 - 2997 08fe 01 .byte 0x1 - 2998 08ff E4030000 .4byte .LASF93 - 2999 0903 05 .byte 0x5 - 3000 0904 43 .byte 0x43 - 3001 0905 01 .byte 0x1 - 3002 0906 01 .byte 0x1 - 3003 0907 22 .uleb128 0x22 - 3004 0908 01 .byte 0x1 - 3005 0909 6C060000 .4byte .LASF94 - 3006 090d 05 .byte 0x5 - 3007 090e 67 .byte 0x67 - 3008 090f 01 .byte 0x1 - 3009 0910 01 .byte 0x1 - 3010 0911 20 .uleb128 0x20 - 3011 0912 01 .byte 0x1 - 3012 0913 4D040000 .4byte .LASF95 - 3013 0917 05 .byte 0x5 - 3014 0918 7A .byte 0x7a - 3015 0919 01 .byte 0x1 - 3016 091a 01 .byte 0x1 - 3017 091b 25090000 .4byte 0x925 - 3018 091f 21 .uleb128 0x21 - 3019 0920 85000000 .4byte 0x85 - 3020 0924 00 .byte 0 - 3021 0925 23 .uleb128 0x23 - 3022 0926 01 .byte 0x1 - 3023 0927 84030000 .4byte .LASF98 - 3024 092b 05 .byte 0x5 - 3025 092c 66 .byte 0x66 - 3026 092d 01 .byte 0x1 - 3027 092e A5000000 .4byte 0xa5 - 3028 0932 01 .byte 0x1 - 3029 0933 3D090000 .4byte 0x93d - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 92 - - - 3030 0937 21 .uleb128 0x21 - 3031 0938 6F000000 .4byte 0x6f - 3032 093c 00 .byte 0 - 3033 093d 22 .uleb128 0x22 - 3034 093e 01 .byte 0x1 - 3035 093f 92020000 .4byte .LASF96 - 3036 0943 05 .byte 0x5 - 3037 0944 48 .byte 0x48 - 3038 0945 01 .byte 0x1 - 3039 0946 01 .byte 0x1 - 3040 0947 22 .uleb128 0x22 - 3041 0948 01 .byte 0x1 - 3042 0949 F7050000 .4byte .LASF97 - 3043 094d 05 .byte 0x5 - 3044 094e 4B .byte 0x4b - 3045 094f 01 .byte 0x1 - 3046 0950 01 .byte 0x1 - 3047 0951 23 .uleb128 0x23 - 3048 0952 01 .byte 0x1 - 3049 0953 8D010000 .4byte .LASF99 - 3050 0957 05 .byte 0x5 - 3051 0958 42 .byte 0x42 - 3052 0959 01 .byte 0x1 - 3053 095a A5000000 .4byte 0xa5 - 3054 095e 01 .byte 0x1 - 3055 095f 69090000 .4byte 0x969 - 3056 0963 21 .uleb128 0x21 - 3057 0964 6F000000 .4byte 0x6f - 3058 0968 00 .byte 0 - 3059 0969 24 .uleb128 0x24 - 3060 096a 01 .byte 0x1 - 3061 096b 57020000 .4byte .LASF115 - 3062 096f 05 .byte 0x5 - 3063 0970 7E .byte 0x7e - 3064 0971 01 .byte 0x1 - 3065 0972 6F000000 .4byte 0x6f - 3066 0976 01 .byte 0x1 - 3067 0977 20 .uleb128 0x20 - 3068 0978 01 .byte 0x1 - 3069 0979 1A040000 .4byte .LASF100 - 3070 097d 05 .byte 0x5 - 3071 097e 7F .byte 0x7f - 3072 097f 01 .byte 0x1 - 3073 0980 01 .byte 0x1 - 3074 0981 8B090000 .4byte 0x98b - 3075 0985 21 .uleb128 0x21 - 3076 0986 6F000000 .4byte 0x6f - 3077 098a 00 .byte 0 - 3078 098b 22 .uleb128 0x22 - 3079 098c 01 .byte 0x1 - 3080 098d 32050000 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.4byte .LASF108 - 3147 0a03 05 .byte 0x5 - 3148 0a04 58 .byte 0x58 - 3149 0a05 01 .byte 0x1 - 3150 0a06 01 .byte 0x1 - 3151 0a07 22 .uleb128 0x22 - 3152 0a08 01 .byte 0x1 - 3153 0a09 C7030000 .4byte .LASF109 - 3154 0a0d 05 .byte 0x5 - 3155 0a0e 5A .byte 0x5a - 3156 0a0f 01 .byte 0x1 - 3157 0a10 01 .byte 0x1 - 3158 0a11 22 .uleb128 0x22 - 3159 0a12 01 .byte 0x1 - 3160 0a13 72000000 .4byte .LASF110 - 3161 0a17 05 .byte 0x5 - 3162 0a18 63 .byte 0x63 - 3163 0a19 01 .byte 0x1 - 3164 0a1a 01 .byte 0x1 - 3165 0a1b 00 .byte 0 - 3166 .section .debug_abbrev,"",%progbits - 3167 .Ldebug_abbrev0: - 3168 0000 01 .uleb128 0x1 - 3169 0001 11 .uleb128 0x11 - 3170 0002 01 .byte 0x1 - 3171 0003 25 .uleb128 0x25 - 3172 0004 0E .uleb128 0xe - 3173 0005 13 .uleb128 0x13 - 3174 0006 0B .uleb128 0xb - 3175 0007 03 .uleb128 0x3 - 3176 0008 0E .uleb128 0xe - 3177 0009 1B .uleb128 0x1b - 3178 000a 0E .uleb128 0xe - 3179 000b 55 .uleb128 0x55 - 3180 000c 06 .uleb128 0x6 - 3181 000d 11 .uleb128 0x11 - 3182 000e 01 .uleb128 0x1 - 3183 000f 52 .uleb128 0x52 - 3184 0010 01 .uleb128 0x1 - 3185 0011 10 .uleb128 0x10 - 3186 0012 06 .uleb128 0x6 - 3187 0013 00 .byte 0 - 3188 0014 00 .byte 0 - 3189 0015 02 .uleb128 0x2 - 3190 0016 24 .uleb128 0x24 - 3191 0017 00 .byte 0 - 3192 0018 0B .uleb128 0xb - 3193 0019 0B .uleb128 0xb - 3194 001a 3E .uleb128 0x3e - 3195 001b 0B .uleb128 0xb - 3196 001c 03 .uleb128 0x3 - 3197 001d 0E .uleb128 0xe - 3198 001e 00 .byte 0 - 3199 001f 00 .byte 0 - 3200 0020 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 95 - - - 3201 0021 24 .uleb128 0x24 - 3202 0022 00 .byte 0 - 3203 0023 0B .uleb128 0xb - 3204 0024 0B .uleb128 0xb - 3205 0025 3E .uleb128 0x3e - 3206 0026 0B .uleb128 0xb - 3207 0027 03 .uleb128 0x3 - 3208 0028 08 .uleb128 0x8 - 3209 0029 00 .byte 0 - 3210 002a 00 .byte 0 - 3211 002b 04 .uleb128 0x4 - 3212 002c 16 .uleb128 0x16 - 3213 002d 00 .byte 0 - 3214 002e 03 .uleb128 0x3 - 3215 002f 0E .uleb128 0xe - 3216 0030 3A .uleb128 0x3a - 3217 0031 0B .uleb128 0xb - 3218 0032 3B .uleb128 0x3b - 3219 0033 0B .uleb128 0xb - 3220 0034 49 .uleb128 0x49 - 3221 0035 13 .uleb128 0x13 - 3222 0036 00 .byte 0 - 3223 0037 00 .byte 0 - 3224 0038 05 .uleb128 0x5 - 3225 0039 35 .uleb128 0x35 - 3226 003a 00 .byte 0 - 3227 003b 49 .uleb128 0x49 - 3228 003c 13 .uleb128 0x13 - 3229 003d 00 .byte 0 - 3230 003e 00 .byte 0 - 3231 003f 06 .uleb128 0x6 - 3232 0040 13 .uleb128 0x13 - 3233 0041 01 .byte 0x1 - 3234 0042 03 .uleb128 0x3 - 3235 0043 0E .uleb128 0xe - 3236 0044 0B .uleb128 0xb - 3237 0045 0B .uleb128 0xb - 3238 0046 3A .uleb128 0x3a - 3239 0047 0B .uleb128 0xb - 3240 0048 3B .uleb128 0x3b - 3241 0049 0B .uleb128 0xb - 3242 004a 01 .uleb128 0x1 - 3243 004b 13 .uleb128 0x13 - 3244 004c 00 .byte 0 - 3245 004d 00 .byte 0 - 3246 004e 07 .uleb128 0x7 - 3247 004f 0D .uleb128 0xd - 3248 0050 00 .byte 0 - 3249 0051 03 .uleb128 0x3 - 3250 0052 0E .uleb128 0xe - 3251 0053 3A .uleb128 0x3a - 3252 0054 0B .uleb128 0xb - 3253 0055 3B .uleb128 0x3b - 3254 0056 0B .uleb128 0xb - 3255 0057 49 .uleb128 0x49 - 3256 0058 13 .uleb128 0x13 - 3257 0059 38 .uleb128 0x38 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 96 - - - 3258 005a 0A .uleb128 0xa - 3259 005b 00 .byte 0 - 3260 005c 00 .byte 0 - 3261 005d 08 .uleb128 0x8 - 3262 005e 0D .uleb128 0xd - 3263 005f 00 .byte 0 - 3264 0060 03 .uleb128 0x3 - 3265 0061 0E .uleb128 0xe - 3266 0062 3A .uleb128 0x3a - 3267 0063 0B .uleb128 0xb - 3268 0064 3B .uleb128 0x3b - 3269 0065 05 .uleb128 0x5 - 3270 0066 49 .uleb128 0x49 - 3271 0067 13 .uleb128 0x13 - 3272 0068 38 .uleb128 0x38 - 3273 0069 0A .uleb128 0xa - 3274 006a 00 .byte 0 - 3275 006b 00 .byte 0 - 3276 006c 09 .uleb128 0x9 - 3277 006d 16 .uleb128 0x16 - 3278 006e 00 .byte 0 - 3279 006f 03 .uleb128 0x3 - 3280 0070 0E .uleb128 0xe - 3281 0071 3A .uleb128 0x3a - 3282 0072 0B .uleb128 0xb - 3283 0073 3B .uleb128 0x3b - 3284 0074 05 .uleb128 0x5 - 3285 0075 49 .uleb128 0x49 - 3286 0076 13 .uleb128 0x13 - 3287 0077 00 .byte 0 - 3288 0078 00 .byte 0 - 3289 0079 0A .uleb128 0xa - 3290 007a 13 .uleb128 0x13 - 3291 007b 01 .byte 0x1 - 3292 007c 03 .uleb128 0x3 - 3293 007d 0E .uleb128 0xe - 3294 007e 0B .uleb128 0xb - 3295 007f 0B .uleb128 0xb - 3296 0080 3A .uleb128 0x3a - 3297 0081 0B .uleb128 0xb - 3298 0082 3B .uleb128 0x3b - 3299 0083 05 .uleb128 0x5 - 3300 0084 01 .uleb128 0x1 - 3301 0085 13 .uleb128 0x13 - 3302 0086 00 .byte 0 - 3303 0087 00 .byte 0 - 3304 0088 0B .uleb128 0xb - 3305 0089 01 .uleb128 0x1 - 3306 008a 01 .byte 0x1 - 3307 008b 49 .uleb128 0x49 - 3308 008c 13 .uleb128 0x13 - 3309 008d 01 .uleb128 0x1 - 3310 008e 13 .uleb128 0x13 - 3311 008f 00 .byte 0 - 3312 0090 00 .byte 0 - 3313 0091 0C .uleb128 0xc - 3314 0092 21 .uleb128 0x21 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 97 - - - 3315 0093 00 .byte 0 - 3316 0094 49 .uleb128 0x49 - 3317 0095 13 .uleb128 0x13 - 3318 0096 2F .uleb128 0x2f - 3319 0097 0B .uleb128 0xb - 3320 0098 00 .byte 0 - 3321 0099 00 .byte 0 - 3322 009a 0D .uleb128 0xd - 3323 009b 2E .uleb128 0x2e - 3324 009c 00 .byte 0 - 3325 009d 03 .uleb128 0x3 - 3326 009e 0E .uleb128 0xe - 3327 009f 3A .uleb128 0x3a - 3328 00a0 0B .uleb128 0xb - 3329 00a1 3B .uleb128 0x3b - 3330 00a2 05 .uleb128 0x5 - 3331 00a3 27 .uleb128 0x27 - 3332 00a4 0C .uleb128 0xc - 3333 00a5 11 .uleb128 0x11 - 3334 00a6 01 .uleb128 0x1 - 3335 00a7 12 .uleb128 0x12 - 3336 00a8 01 .uleb128 0x1 - 3337 00a9 40 .uleb128 0x40 - 3338 00aa 06 .uleb128 0x6 - 3339 00ab 9742 .uleb128 0x2117 - 3340 00ad 0C .uleb128 0xc - 3341 00ae 00 .byte 0 - 3342 00af 00 .byte 0 - 3343 00b0 0E .uleb128 0xe - 3344 00b1 2E .uleb128 0x2e - 3345 00b2 00 .byte 0 - 3346 00b3 03 .uleb128 0x3 - 3347 00b4 0E .uleb128 0xe - 3348 00b5 3A .uleb128 0x3a - 3349 00b6 0B .uleb128 0xb - 3350 00b7 3B .uleb128 0x3b - 3351 00b8 05 .uleb128 0x5 - 3352 00b9 27 .uleb128 0x27 - 3353 00ba 0C .uleb128 0xc - 3354 00bb 11 .uleb128 0x11 - 3355 00bc 01 .uleb128 0x1 - 3356 00bd 12 .uleb128 0x12 - 3357 00be 01 .uleb128 0x1 - 3358 00bf 40 .uleb128 0x40 - 3359 00c0 0A .uleb128 0xa - 3360 00c1 9742 .uleb128 0x2117 - 3361 00c3 0C .uleb128 0xc - 3362 00c4 00 .byte 0 - 3363 00c5 00 .byte 0 - 3364 00c6 0F .uleb128 0xf - 3365 00c7 2E .uleb128 0x2e - 3366 00c8 01 .byte 0x1 - 3367 00c9 3F .uleb128 0x3f - 3368 00ca 0C .uleb128 0xc - 3369 00cb 03 .uleb128 0x3 - 3370 00cc 0E .uleb128 0xe - 3371 00cd 3A .uleb128 0x3a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 98 - - - 3372 00ce 0B .uleb128 0xb - 3373 00cf 3B .uleb128 0x3b - 3374 00d0 0B .uleb128 0xb - 3375 00d1 27 .uleb128 0x27 - 3376 00d2 0C .uleb128 0xc - 3377 00d3 11 .uleb128 0x11 - 3378 00d4 01 .uleb128 0x1 - 3379 00d5 12 .uleb128 0x12 - 3380 00d6 01 .uleb128 0x1 - 3381 00d7 40 .uleb128 0x40 - 3382 00d8 06 .uleb128 0x6 - 3383 00d9 9742 .uleb128 0x2117 - 3384 00db 0C .uleb128 0xc - 3385 00dc 01 .uleb128 0x1 - 3386 00dd 13 .uleb128 0x13 - 3387 00de 00 .byte 0 - 3388 00df 00 .byte 0 - 3389 00e0 10 .uleb128 0x10 - 3390 00e1 898201 .uleb128 0x4109 - 3391 00e4 01 .byte 0x1 - 3392 00e5 11 .uleb128 0x11 - 3393 00e6 01 .uleb128 0x1 - 3394 00e7 31 .uleb128 0x31 - 3395 00e8 13 .uleb128 0x13 - 3396 00e9 01 .uleb128 0x1 - 3397 00ea 13 .uleb128 0x13 - 3398 00eb 00 .byte 0 - 3399 00ec 00 .byte 0 - 3400 00ed 11 .uleb128 0x11 - 3401 00ee 8A8201 .uleb128 0x410a - 3402 00f1 00 .byte 0 - 3403 00f2 02 .uleb128 0x2 - 3404 00f3 0A .uleb128 0xa - 3405 00f4 9142 .uleb128 0x2111 - 3406 00f6 0A .uleb128 0xa - 3407 00f7 00 .byte 0 - 3408 00f8 00 .byte 0 - 3409 00f9 12 .uleb128 0x12 - 3410 00fa 898201 .uleb128 0x4109 - 3411 00fd 00 .byte 0 - 3412 00fe 11 .uleb128 0x11 - 3413 00ff 01 .uleb128 0x1 - 3414 0100 31 .uleb128 0x31 - 3415 0101 13 .uleb128 0x13 - 3416 0102 00 .byte 0 - 3417 0103 00 .byte 0 - 3418 0104 13 .uleb128 0x13 - 3419 0105 2E .uleb128 0x2e - 3420 0106 01 .byte 0x1 - 3421 0107 3F .uleb128 0x3f - 3422 0108 0C .uleb128 0xc - 3423 0109 03 .uleb128 0x3 - 3424 010a 0E .uleb128 0xe - 3425 010b 3A .uleb128 0x3a - 3426 010c 0B .uleb128 0xb - 3427 010d 3B .uleb128 0x3b - 3428 010e 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 99 - - - 3429 010f 27 .uleb128 0x27 - 3430 0110 0C .uleb128 0xc - 3431 0111 11 .uleb128 0x11 - 3432 0112 01 .uleb128 0x1 - 3433 0113 12 .uleb128 0x12 - 3434 0114 01 .uleb128 0x1 - 3435 0115 40 .uleb128 0x40 - 3436 0116 06 .uleb128 0x6 - 3437 0117 9742 .uleb128 0x2117 - 3438 0119 0C .uleb128 0xc - 3439 011a 01 .uleb128 0x1 - 3440 011b 13 .uleb128 0x13 - 3441 011c 00 .byte 0 - 3442 011d 00 .byte 0 - 3443 011e 14 .uleb128 0x14 - 3444 011f 34 .uleb128 0x34 - 3445 0120 00 .byte 0 - 3446 0121 03 .uleb128 0x3 - 3447 0122 0E .uleb128 0xe - 3448 0123 3A .uleb128 0x3a - 3449 0124 0B .uleb128 0xb - 3450 0125 3B .uleb128 0x3b - 3451 0126 05 .uleb128 0x5 - 3452 0127 49 .uleb128 0x49 - 3453 0128 13 .uleb128 0x13 - 3454 0129 1C .uleb128 0x1c - 3455 012a 0B .uleb128 0xb - 3456 012b 00 .byte 0 - 3457 012c 00 .byte 0 - 3458 012d 15 .uleb128 0x15 - 3459 012e 34 .uleb128 0x34 - 3460 012f 00 .byte 0 - 3461 0130 03 .uleb128 0x3 - 3462 0131 08 .uleb128 0x8 - 3463 0132 3A .uleb128 0x3a - 3464 0133 0B .uleb128 0xb - 3465 0134 3B .uleb128 0x3b - 3466 0135 05 .uleb128 0x5 - 3467 0136 49 .uleb128 0x49 - 3468 0137 13 .uleb128 0x13 - 3469 0138 00 .byte 0 - 3470 0139 00 .byte 0 - 3471 013a 16 .uleb128 0x16 - 3472 013b 34 .uleb128 0x34 - 3473 013c 00 .byte 0 - 3474 013d 03 .uleb128 0x3 - 3475 013e 0E .uleb128 0xe - 3476 013f 3A .uleb128 0x3a - 3477 0140 0B .uleb128 0xb - 3478 0141 3B .uleb128 0x3b - 3479 0142 05 .uleb128 0x5 - 3480 0143 49 .uleb128 0x49 - 3481 0144 13 .uleb128 0x13 - 3482 0145 02 .uleb128 0x2 - 3483 0146 06 .uleb128 0x6 - 3484 0147 00 .byte 0 - 3485 0148 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 100 - - - 3486 0149 17 .uleb128 0x17 - 3487 014a 34 .uleb128 0x34 - 3488 014b 00 .byte 0 - 3489 014c 03 .uleb128 0x3 - 3490 014d 0E .uleb128 0xe - 3491 014e 3A .uleb128 0x3a - 3492 014f 0B .uleb128 0xb - 3493 0150 3B .uleb128 0x3b - 3494 0151 05 .uleb128 0x5 - 3495 0152 49 .uleb128 0x49 - 3496 0153 13 .uleb128 0x13 - 3497 0154 02 .uleb128 0x2 - 3498 0155 0A .uleb128 0xa - 3499 0156 00 .byte 0 - 3500 0157 00 .byte 0 - 3501 0158 18 .uleb128 0x18 - 3502 0159 26 .uleb128 0x26 - 3503 015a 00 .byte 0 - 3504 015b 49 .uleb128 0x49 - 3505 015c 13 .uleb128 0x13 - 3506 015d 00 .byte 0 - 3507 015e 00 .byte 0 - 3508 015f 19 .uleb128 0x19 - 3509 0160 05 .uleb128 0x5 - 3510 0161 00 .byte 0 - 3511 0162 03 .uleb128 0x3 - 3512 0163 0E .uleb128 0xe - 3513 0164 3A .uleb128 0x3a - 3514 0165 0B .uleb128 0xb - 3515 0166 3B .uleb128 0x3b - 3516 0167 05 .uleb128 0x5 - 3517 0168 49 .uleb128 0x49 - 3518 0169 13 .uleb128 0x13 - 3519 016a 02 .uleb128 0x2 - 3520 016b 06 .uleb128 0x6 - 3521 016c 00 .byte 0 - 3522 016d 00 .byte 0 - 3523 016e 1A .uleb128 0x1a - 3524 016f 898201 .uleb128 0x4109 - 3525 0172 00 .byte 0 - 3526 0173 11 .uleb128 0x11 - 3527 0174 01 .uleb128 0x1 - 3528 0175 9542 .uleb128 0x2115 - 3529 0177 0C .uleb128 0xc - 3530 0178 31 .uleb128 0x31 - 3531 0179 13 .uleb128 0x13 - 3532 017a 00 .byte 0 - 3533 017b 00 .byte 0 - 3534 017c 1B .uleb128 0x1b - 3535 017d 2E .uleb128 0x2e - 3536 017e 00 .byte 0 - 3537 017f 03 .uleb128 0x3 - 3538 0180 0E .uleb128 0xe - 3539 0181 3A .uleb128 0x3a - 3540 0182 0B .uleb128 0xb - 3541 0183 3B .uleb128 0x3b - 3542 0184 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 101 - - - 3543 0185 27 .uleb128 0x27 - 3544 0186 0C .uleb128 0xc - 3545 0187 20 .uleb128 0x20 - 3546 0188 0B .uleb128 0xb - 3547 0189 00 .byte 0 - 3548 018a 00 .byte 0 - 3549 018b 1C .uleb128 0x1c - 3550 018c 1D .uleb128 0x1d - 3551 018d 01 .byte 0x1 - 3552 018e 31 .uleb128 0x31 - 3553 018f 13 .uleb128 0x13 - 3554 0190 52 .uleb128 0x52 - 3555 0191 01 .uleb128 0x1 - 3556 0192 55 .uleb128 0x55 - 3557 0193 06 .uleb128 0x6 - 3558 0194 58 .uleb128 0x58 - 3559 0195 0B .uleb128 0xb - 3560 0196 59 .uleb128 0x59 - 3561 0197 05 .uleb128 0x5 - 3562 0198 01 .uleb128 0x1 - 3563 0199 13 .uleb128 0x13 - 3564 019a 00 .byte 0 - 3565 019b 00 .byte 0 - 3566 019c 1D .uleb128 0x1d - 3567 019d 1D .uleb128 0x1d - 3568 019e 01 .byte 0x1 - 3569 019f 31 .uleb128 0x31 - 3570 01a0 13 .uleb128 0x13 - 3571 01a1 11 .uleb128 0x11 - 3572 01a2 01 .uleb128 0x1 - 3573 01a3 12 .uleb128 0x12 - 3574 01a4 01 .uleb128 0x1 - 3575 01a5 58 .uleb128 0x58 - 3576 01a6 0B .uleb128 0xb - 3577 01a7 59 .uleb128 0x59 - 3578 01a8 05 .uleb128 0x5 - 3579 01a9 01 .uleb128 0x1 - 3580 01aa 13 .uleb128 0x13 - 3581 01ab 00 .byte 0 - 3582 01ac 00 .byte 0 - 3583 01ad 1E .uleb128 0x1e - 3584 01ae 2E .uleb128 0x2e - 3585 01af 01 .byte 0x1 - 3586 01b0 3F .uleb128 0x3f - 3587 01b1 0C .uleb128 0xc - 3588 01b2 03 .uleb128 0x3 - 3589 01b3 0E .uleb128 0xe - 3590 01b4 3A .uleb128 0x3a - 3591 01b5 0B .uleb128 0xb - 3592 01b6 3B .uleb128 0x3b - 3593 01b7 05 .uleb128 0x5 - 3594 01b8 27 .uleb128 0x27 - 3595 01b9 0C .uleb128 0xc - 3596 01ba 49 .uleb128 0x49 - 3597 01bb 13 .uleb128 0x13 - 3598 01bc 11 .uleb128 0x11 - 3599 01bd 01 .uleb128 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 102 - - - 3600 01be 12 .uleb128 0x12 - 3601 01bf 01 .uleb128 0x1 - 3602 01c0 40 .uleb128 0x40 - 3603 01c1 06 .uleb128 0x6 - 3604 01c2 9742 .uleb128 0x2117 - 3605 01c4 0C .uleb128 0xc - 3606 01c5 01 .uleb128 0x1 - 3607 01c6 13 .uleb128 0x13 - 3608 01c7 00 .byte 0 - 3609 01c8 00 .byte 0 - 3610 01c9 1F .uleb128 0x1f - 3611 01ca 34 .uleb128 0x34 - 3612 01cb 00 .byte 0 - 3613 01cc 03 .uleb128 0x3 - 3614 01cd 0E .uleb128 0xe - 3615 01ce 3A .uleb128 0x3a - 3616 01cf 0B .uleb128 0xb - 3617 01d0 3B .uleb128 0x3b - 3618 01d1 0B .uleb128 0xb - 3619 01d2 49 .uleb128 0x49 - 3620 01d3 13 .uleb128 0x13 - 3621 01d4 02 .uleb128 0x2 - 3622 01d5 0A .uleb128 0xa - 3623 01d6 00 .byte 0 - 3624 01d7 00 .byte 0 - 3625 01d8 20 .uleb128 0x20 - 3626 01d9 2E .uleb128 0x2e - 3627 01da 01 .byte 0x1 - 3628 01db 3F .uleb128 0x3f - 3629 01dc 0C .uleb128 0xc - 3630 01dd 03 .uleb128 0x3 - 3631 01de 0E .uleb128 0xe - 3632 01df 3A .uleb128 0x3a - 3633 01e0 0B .uleb128 0xb - 3634 01e1 3B .uleb128 0x3b - 3635 01e2 0B .uleb128 0xb - 3636 01e3 27 .uleb128 0x27 - 3637 01e4 0C .uleb128 0xc - 3638 01e5 3C .uleb128 0x3c - 3639 01e6 0C .uleb128 0xc - 3640 01e7 01 .uleb128 0x1 - 3641 01e8 13 .uleb128 0x13 - 3642 01e9 00 .byte 0 - 3643 01ea 00 .byte 0 - 3644 01eb 21 .uleb128 0x21 - 3645 01ec 05 .uleb128 0x5 - 3646 01ed 00 .byte 0 - 3647 01ee 49 .uleb128 0x49 - 3648 01ef 13 .uleb128 0x13 - 3649 01f0 00 .byte 0 - 3650 01f1 00 .byte 0 - 3651 01f2 22 .uleb128 0x22 - 3652 01f3 2E .uleb128 0x2e - 3653 01f4 00 .byte 0 - 3654 01f5 3F .uleb128 0x3f - 3655 01f6 0C .uleb128 0xc - 3656 01f7 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 103 - - - 3657 01f8 0E .uleb128 0xe - 3658 01f9 3A .uleb128 0x3a - 3659 01fa 0B .uleb128 0xb - 3660 01fb 3B .uleb128 0x3b - 3661 01fc 0B .uleb128 0xb - 3662 01fd 27 .uleb128 0x27 - 3663 01fe 0C .uleb128 0xc - 3664 01ff 3C .uleb128 0x3c - 3665 0200 0C .uleb128 0xc - 3666 0201 00 .byte 0 - 3667 0202 00 .byte 0 - 3668 0203 23 .uleb128 0x23 - 3669 0204 2E .uleb128 0x2e - 3670 0205 01 .byte 0x1 - 3671 0206 3F .uleb128 0x3f - 3672 0207 0C .uleb128 0xc - 3673 0208 03 .uleb128 0x3 - 3674 0209 0E .uleb128 0xe - 3675 020a 3A .uleb128 0x3a - 3676 020b 0B .uleb128 0xb - 3677 020c 3B .uleb128 0x3b - 3678 020d 0B .uleb128 0xb - 3679 020e 27 .uleb128 0x27 - 3680 020f 0C .uleb128 0xc - 3681 0210 49 .uleb128 0x49 - 3682 0211 13 .uleb128 0x13 - 3683 0212 3C .uleb128 0x3c - 3684 0213 0C .uleb128 0xc - 3685 0214 01 .uleb128 0x1 - 3686 0215 13 .uleb128 0x13 - 3687 0216 00 .byte 0 - 3688 0217 00 .byte 0 - 3689 0218 24 .uleb128 0x24 - 3690 0219 2E .uleb128 0x2e - 3691 021a 00 .byte 0 - 3692 021b 3F .uleb128 0x3f - 3693 021c 0C .uleb128 0xc - 3694 021d 03 .uleb128 0x3 - 3695 021e 0E .uleb128 0xe - 3696 021f 3A .uleb128 0x3a - 3697 0220 0B .uleb128 0xb - 3698 0221 3B .uleb128 0x3b - 3699 0222 0B .uleb128 0xb - 3700 0223 27 .uleb128 0x27 - 3701 0224 0C .uleb128 0xc - 3702 0225 49 .uleb128 0x49 - 3703 0226 13 .uleb128 0x13 - 3704 0227 3C .uleb128 0x3c - 3705 0228 0C .uleb128 0xc - 3706 0229 00 .byte 0 - 3707 022a 00 .byte 0 - 3708 022b 00 .byte 0 - 3709 .section .debug_loc,"",%progbits - 3710 .Ldebug_loc0: - 3711 .LLST0: - 3712 0000 00000000 .4byte .LFB11 - 3713 0004 04000000 .4byte .LCFI0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 104 - - - 3714 0008 0200 .2byte 0x2 - 3715 000a 7D .byte 0x7d - 3716 000b 00 .sleb128 0 - 3717 000c 04000000 .4byte .LCFI0 - 3718 0010 64010000 .4byte .LFE11 - 3719 0014 0200 .2byte 0x2 - 3720 0016 7D .byte 0x7d - 3721 0017 24 .sleb128 36 - 3722 0018 00000000 .4byte 0 - 3723 001c 00000000 .4byte 0 - 3724 .LLST1: - 3725 0020 00000000 .4byte .LFB0 - 3726 0024 02000000 .4byte .LCFI1 - 3727 0028 0200 .2byte 0x2 - 3728 002a 7D .byte 0x7d - 3729 002b 00 .sleb128 0 - 3730 002c 02000000 .4byte .LCFI1 - 3731 0030 B4010000 .4byte .LFE0 - 3732 0034 0200 .2byte 0x2 - 3733 0036 7D .byte 0x7d - 3734 0037 08 .sleb128 8 - 3735 0038 00000000 .4byte 0 - 3736 003c 00000000 .4byte 0 - 3737 .LLST2: - 3738 0040 00000000 .4byte .LFB1 - 3739 0044 04000000 .4byte .LCFI2 - 3740 0048 0200 .2byte 0x2 - 3741 004a 7D .byte 0x7d - 3742 004b 00 .sleb128 0 - 3743 004c 04000000 .4byte .LCFI2 - 3744 0050 08020000 .4byte .LFE1 - 3745 0054 0200 .2byte 0x2 - 3746 0056 7D .byte 0x7d - 3747 0057 10 .sleb128 16 - 3748 0058 00000000 .4byte 0 - 3749 005c 00000000 .4byte 0 - 3750 .LLST3: - 3751 0060 AA010000 .4byte .LVL29 - 3752 0064 B0010000 .4byte .LVL30 - 3753 0068 0500 .2byte 0x5 - 3754 006a 72 .byte 0x72 - 3755 006b 00 .sleb128 0 - 3756 006c 38 .byte 0x38 - 3757 006d 24 .byte 0x24 - 3758 006e 9F .byte 0x9f - 3759 006f B0010000 .4byte .LVL30 - 3760 0073 B6010000 .4byte .LVL31 - 3761 0077 0B00 .2byte 0xb - 3762 0079 72 .byte 0x72 - 3763 007a 00 .sleb128 0 - 3764 007b 38 .byte 0x38 - 3765 007c 24 .byte 0x24 - 3766 007d 73 .byte 0x73 - 3767 007e 00 .sleb128 0 - 3768 007f 08 .byte 0x8 - 3769 0080 FF .byte 0xff - 3770 0081 1A .byte 0x1a - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 105 - - - 3771 0082 21 .byte 0x21 - 3772 0083 9F .byte 0x9f - 3773 0084 00000000 .4byte 0 - 3774 0088 00000000 .4byte 0 - 3775 .LLST4: - 3776 008c 00000000 .4byte .LFB2 - 3777 0090 02000000 .4byte .LCFI3 - 3778 0094 0200 .2byte 0x2 - 3779 0096 7D .byte 0x7d - 3780 0097 00 .sleb128 0 - 3781 0098 02000000 .4byte .LCFI3 - 3782 009c 60000000 .4byte .LFE2 - 3783 00a0 0200 .2byte 0x2 - 3784 00a2 7D .byte 0x7d - 3785 00a3 0C .sleb128 12 - 3786 00a4 00000000 .4byte 0 - 3787 00a8 00000000 .4byte 0 - 3788 .LLST5: - 3789 00ac 00000000 .4byte .LVL33 - 3790 00b0 0A000000 .4byte .LVL34 - 3791 00b4 0100 .2byte 0x1 - 3792 00b6 50 .byte 0x50 - 3793 00b7 0A000000 .4byte .LVL34 - 3794 00bb 60000000 .4byte .LFE2 - 3795 00bf 0400 .2byte 0x4 - 3796 00c1 F3 .byte 0xf3 - 3797 00c2 01 .uleb128 0x1 - 3798 00c3 50 .byte 0x50 - 3799 00c4 9F .byte 0x9f - 3800 00c5 00000000 .4byte 0 - 3801 00c9 00000000 .4byte 0 - 3802 .LLST6: - 3803 00cd 00000000 .4byte .LVL33 - 3804 00d1 1A000000 .4byte .LVL35 - 3805 00d5 0100 .2byte 0x1 - 3806 00d7 51 .byte 0x51 - 3807 00d8 1A000000 .4byte .LVL35 - 3808 00dc 60000000 .4byte .LFE2 - 3809 00e0 0400 .2byte 0x4 - 3810 00e2 F3 .byte 0xf3 - 3811 00e3 01 .uleb128 0x1 - 3812 00e4 51 .byte 0x51 - 3813 00e5 9F .byte 0x9f - 3814 00e6 00000000 .4byte 0 - 3815 00ea 00000000 .4byte 0 - 3816 .LLST7: - 3817 00ee 00000000 .4byte .LFB3 - 3818 00f2 02000000 .4byte .LCFI4 - 3819 00f6 0200 .2byte 0x2 - 3820 00f8 7D .byte 0x7d - 3821 00f9 00 .sleb128 0 - 3822 00fa 02000000 .4byte .LCFI4 - 3823 00fe D8000000 .4byte .LFE3 - 3824 0102 0200 .2byte 0x2 - 3825 0104 7D .byte 0x7d - 3826 0105 10 .sleb128 16 - 3827 0106 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 106 - - - 3828 010a 00000000 .4byte 0 - 3829 .LLST8: - 3830 010e 00000000 .4byte .LVL36 - 3831 0112 07000000 .4byte .LVL37-1 - 3832 0116 0100 .2byte 0x1 - 3833 0118 50 .byte 0x50 - 3834 0119 07000000 .4byte .LVL37-1 - 3835 011d D8000000 .4byte .LFE3 - 3836 0121 0400 .2byte 0x4 - 3837 0123 F3 .byte 0xf3 - 3838 0124 01 .uleb128 0x1 - 3839 0125 50 .byte 0x50 - 3840 0126 9F .byte 0x9f - 3841 0127 00000000 .4byte 0 - 3842 012b 00000000 .4byte 0 - 3843 .LLST9: - 3844 012f 00000000 .4byte .LVL36 - 3845 0133 07000000 .4byte .LVL37-1 - 3846 0137 0100 .2byte 0x1 - 3847 0139 51 .byte 0x51 - 3848 013a 07000000 .4byte .LVL37-1 - 3849 013e D8000000 .4byte .LFE3 - 3850 0142 0400 .2byte 0x4 - 3851 0144 F3 .byte 0xf3 - 3852 0145 01 .uleb128 0x1 - 3853 0146 51 .byte 0x51 - 3854 0147 9F .byte 0x9f - 3855 0148 00000000 .4byte 0 - 3856 014c 00000000 .4byte 0 - 3857 .LLST10: - 3858 0150 0C000000 .4byte .LVL38 - 3859 0154 18000000 .4byte .LVL39 - 3860 0158 0100 .2byte 0x1 - 3861 015a 50 .byte 0x50 - 3862 015b 18000000 .4byte .LVL39 - 3863 015f B6000000 .4byte .LVL42 - 3864 0163 0100 .2byte 0x1 - 3865 0165 55 .byte 0x55 - 3866 0166 B6000000 .4byte .LVL42 - 3867 016a BD000000 .4byte .LVL43-1 - 3868 016e 0100 .2byte 0x1 - 3869 0170 50 .byte 0x50 - 3870 0171 BD000000 .4byte .LVL43-1 - 3871 0175 D8000000 .4byte .LFE3 - 3872 0179 0100 .2byte 0x1 - 3873 017b 55 .byte 0x55 - 3874 017c 00000000 .4byte 0 - 3875 0180 00000000 .4byte 0 - 3876 .LLST11: - 3877 0184 00000000 .4byte .LFB4 - 3878 0188 02000000 .4byte .LCFI5 - 3879 018c 0200 .2byte 0x2 - 3880 018e 7D .byte 0x7d - 3881 018f 00 .sleb128 0 - 3882 0190 02000000 .4byte .LCFI5 - 3883 0194 38020000 .4byte .LFE4 - 3884 0198 0200 .2byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 107 - - - 3885 019a 7D .byte 0x7d - 3886 019b 10 .sleb128 16 - 3887 019c 00000000 .4byte 0 - 3888 01a0 00000000 .4byte 0 - 3889 .LLST12: - 3890 01a4 0A000000 .4byte .LVL45 - 3891 01a8 1A000000 .4byte .LVL46 - 3892 01ac 0100 .2byte 0x1 - 3893 01ae 50 .byte 0x50 - 3894 01af 1A000000 .4byte .LVL46 - 3895 01b3 FC010000 .4byte .LVL59 - 3896 01b7 0100 .2byte 0x1 - 3897 01b9 55 .byte 0x55 - 3898 01ba FC010000 .4byte .LVL59 - 3899 01be 03020000 .4byte .LVL60-1 - 3900 01c2 0100 .2byte 0x1 - 3901 01c4 50 .byte 0x50 - 3902 01c5 03020000 .4byte .LVL60-1 - 3903 01c9 38020000 .4byte .LFE4 - 3904 01cd 0100 .2byte 0x1 - 3905 01cf 55 .byte 0x55 - 3906 01d0 00000000 .4byte 0 - 3907 01d4 00000000 .4byte 0 - 3908 .LLST13: - 3909 01d8 00000000 .4byte .LFB5 - 3910 01dc 02000000 .4byte .LCFI6 - 3911 01e0 0200 .2byte 0x2 - 3912 01e2 7D .byte 0x7d - 3913 01e3 00 .sleb128 0 - 3914 01e4 02000000 .4byte .LCFI6 - 3915 01e8 2C000000 .4byte .LFE5 - 3916 01ec 0200 .2byte 0x2 - 3917 01ee 7D .byte 0x7d - 3918 01ef 10 .sleb128 16 - 3919 01f0 00000000 .4byte 0 - 3920 01f4 00000000 .4byte 0 - 3921 .LLST14: - 3922 01f8 00000000 .4byte .LVL61 - 3923 01fc 07000000 .4byte .LVL62-1 - 3924 0200 0100 .2byte 0x1 - 3925 0202 50 .byte 0x50 - 3926 0203 07000000 .4byte .LVL62-1 - 3927 0207 2C000000 .4byte .LFE5 - 3928 020b 0400 .2byte 0x4 - 3929 020d F3 .byte 0xf3 - 3930 020e 01 .uleb128 0x1 - 3931 020f 50 .byte 0x50 - 3932 0210 9F .byte 0x9f - 3933 0211 00000000 .4byte 0 - 3934 0215 00000000 .4byte 0 - 3935 .LLST15: - 3936 0219 08000000 .4byte .LVL62 - 3937 021d 1F000000 .4byte .LVL64-1 - 3938 0221 0100 .2byte 0x1 - 3939 0223 50 .byte 0x50 - 3940 0224 00000000 .4byte 0 - 3941 0228 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 108 - - - 3942 .LLST16: - 3943 022c 00000000 .4byte .LFB8 - 3944 0230 02000000 .4byte .LCFI7 - 3945 0234 0200 .2byte 0x2 - 3946 0236 7D .byte 0x7d - 3947 0237 00 .sleb128 0 - 3948 0238 02000000 .4byte .LCFI7 - 3949 023c 54000000 .4byte .LFE8 - 3950 0240 0200 .2byte 0x2 - 3951 0242 7D .byte 0x7d - 3952 0243 10 .sleb128 16 - 3953 0244 00000000 .4byte 0 - 3954 0248 00000000 .4byte 0 - 3955 .LLST17: - 3956 024c 00000000 .4byte .LVL65 - 3957 0250 0C000000 .4byte .LVL66 - 3958 0254 0100 .2byte 0x1 - 3959 0256 50 .byte 0x50 - 3960 0257 0C000000 .4byte .LVL66 - 3961 025b 54000000 .4byte .LFE8 - 3962 025f 0400 .2byte 0x4 - 3963 0261 F3 .byte 0xf3 - 3964 0262 01 .uleb128 0x1 - 3965 0263 50 .byte 0x50 - 3966 0264 9F .byte 0x9f - 3967 0265 00000000 .4byte 0 - 3968 0269 00000000 .4byte 0 - 3969 .LLST18: - 3970 026d 00000000 .4byte .LFB9 - 3971 0271 02000000 .4byte .LCFI8 - 3972 0275 0200 .2byte 0x2 - 3973 0277 7D .byte 0x7d - 3974 0278 00 .sleb128 0 - 3975 0279 02000000 .4byte .LCFI8 - 3976 027d 2C000000 .4byte .LFE9 - 3977 0281 0200 .2byte 0x2 - 3978 0283 7D .byte 0x7d - 3979 0284 08 .sleb128 8 - 3980 0285 00000000 .4byte 0 - 3981 0289 00000000 .4byte 0 - 3982 .LLST19: - 3983 028d 00000000 .4byte .LFB10 - 3984 0291 02000000 .4byte .LCFI9 - 3985 0295 0200 .2byte 0x2 - 3986 0297 7D .byte 0x7d - 3987 0298 00 .sleb128 0 - 3988 0299 02000000 .4byte .LCFI9 - 3989 029d 50000000 .4byte .LFE10 - 3990 02a1 0200 .2byte 0x2 - 3991 02a3 7D .byte 0x7d - 3992 02a4 10 .sleb128 16 - 3993 02a5 00000000 .4byte 0 - 3994 02a9 00000000 .4byte 0 - 3995 .LLST20: - 3996 02ad 00000000 .4byte .LVL69 - 3997 02b1 0C000000 .4byte .LVL70 - 3998 02b5 0100 .2byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 109 - - - 3999 02b7 50 .byte 0x50 - 4000 02b8 0C000000 .4byte .LVL70 - 4001 02bc 50000000 .4byte .LFE10 - 4002 02c0 0400 .2byte 0x4 - 4003 02c2 F3 .byte 0xf3 - 4004 02c3 01 .uleb128 0x1 - 4005 02c4 50 .byte 0x50 - 4006 02c5 9F .byte 0x9f - 4007 02c6 00000000 .4byte 0 - 4008 02ca 00000000 .4byte 0 - 4009 .section .debug_aranges,"",%progbits - 4010 0000 6C000000 .4byte 0x6c - 4011 0004 0200 .2byte 0x2 - 4012 0006 00000000 .4byte .Ldebug_info0 - 4013 000a 04 .byte 0x4 - 4014 000b 00 .byte 0 - 4015 000c 0000 .2byte 0 - 4016 000e 0000 .2byte 0 - 4017 0010 00000000 .4byte .LFB11 - 4018 0014 64010000 .4byte .LFE11-.LFB11 - 4019 0018 00000000 .4byte .LFB12 - 4020 001c A4000000 .4byte .LFE12-.LFB12 - 4021 0020 00000000 .4byte .LFB0 - 4022 0024 B4010000 .4byte .LFE0-.LFB0 - 4023 0028 00000000 .4byte .LFB1 - 4024 002c 08020000 .4byte .LFE1-.LFB1 - 4025 0030 00000000 .4byte .LFB2 - 4026 0034 60000000 .4byte .LFE2-.LFB2 - 4027 0038 00000000 .4byte .LFB3 - 4028 003c D8000000 .4byte .LFE3-.LFB3 - 4029 0040 00000000 .4byte .LFB4 - 4030 0044 38020000 .4byte .LFE4-.LFB4 - 4031 0048 00000000 .4byte .LFB5 - 4032 004c 2C000000 .4byte .LFE5-.LFB5 - 4033 0050 00000000 .4byte .LFB8 - 4034 0054 54000000 .4byte .LFE8-.LFB8 - 4035 0058 00000000 .4byte .LFB9 - 4036 005c 2C000000 .4byte .LFE9-.LFB9 - 4037 0060 00000000 .4byte .LFB10 - 4038 0064 50000000 .4byte .LFE10-.LFB10 - 4039 0068 00000000 .4byte 0 - 4040 006c 00000000 .4byte 0 - 4041 .section .debug_ranges,"",%progbits - 4042 .Ldebug_ranges0: - 4043 0000 1A000000 .4byte .LBB10 - 4044 0004 1C000000 .4byte .LBE10 - 4045 0008 24000000 .4byte .LBB15 - 4046 000c 06010000 .4byte .LBE15 - 4047 0010 00000000 .4byte 0 - 4048 0014 00000000 .4byte 0 - 4049 0018 00000000 .4byte .LFB11 - 4050 001c 64010000 .4byte .LFE11 - 4051 0020 00000000 .4byte .LFB12 - 4052 0024 A4000000 .4byte .LFE12 - 4053 0028 00000000 .4byte .LFB0 - 4054 002c B4010000 .4byte .LFE0 - 4055 0030 00000000 .4byte .LFB1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 110 - - - 4056 0034 08020000 .4byte .LFE1 - 4057 0038 00000000 .4byte .LFB2 - 4058 003c 60000000 .4byte .LFE2 - 4059 0040 00000000 .4byte .LFB3 - 4060 0044 D8000000 .4byte .LFE3 - 4061 0048 00000000 .4byte .LFB4 - 4062 004c 38020000 .4byte .LFE4 - 4063 0050 00000000 .4byte .LFB5 - 4064 0054 2C000000 .4byte .LFE5 - 4065 0058 00000000 .4byte .LFB8 - 4066 005c 54000000 .4byte .LFE8 - 4067 0060 00000000 .4byte .LFB9 - 4068 0064 2C000000 .4byte .LFE9 - 4069 0068 00000000 .4byte .LFB10 - 4070 006c 50000000 .4byte .LFE10 - 4071 0070 00000000 .4byte 0 - 4072 0074 00000000 .4byte 0 - 4073 .section .debug_line,"",%progbits - 4074 .Ldebug_line0: - 4075 0000 46030000 .section .debug_str,"MS",%progbits,1 - 4075 02006500 - 4075 00000201 - 4075 FB0E0D00 - 4075 01010101 - 4076 .LASF102: - 4077 0000 43795664 .ascii "CyVdLvAnalogDisable\000" - 4077 4C76416E - 4077 616C6F67 - 4077 44697361 - 4077 626C6500 - 4078 .LASF10: - 4079 0014 75696E74 .ascii "uint16\000" - 4079 313600 - 4080 .LASF87: - 4081 001b 4379494D .ascii "CyIMO_Start\000" - 4081 4F5F5374 - 4081 61727400 - 4082 .LASF58: - 4083 0027 4379506D .ascii "CyPmHibSlpRestore\000" - 4083 48696253 - 4083 6C705265 - 4083 73746F72 - 4083 6500 - 4084 .LASF43: - 4085 0039 77616B65 .ascii "wakeupTrim0\000" - 4085 75705472 - 4085 696D3000 - 4086 .LASF44: - 4087 0045 77616B65 .ascii "wakeupTrim1\000" - 4087 75705472 - 4087 696D3100 - 4088 .LASF20: - 4089 0051 6D617374 .ascii "masterClkSrc\000" - 4089 6572436C - 4089 6B537263 - 4089 00 - 4090 .LASF56: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 111 - - - 4091 005e 43595F50 .ascii "CY_PM_BACKUP_STRUCT\000" - 4091 4D5F4241 - 4091 434B5550 - 4091 5F535452 - 4091 55435400 - 4092 .LASF110: - 4093 0072 43795854 .ascii "CyXTAL_32KHZ_Start\000" - 4093 414C5F33 - 4093 324B485A - 4093 5F537461 - 4093 727400 - 4094 .LASF28: - 4095 0085 636C6B53 .ascii "clkSyncDiv\000" - 4095 796E6344 - 4095 697600 - 4096 .LASF60: - 4097 0090 4379506D .ascii "CyPmRestoreClocks\000" - 4097 52657374 - 4097 6F726543 - 4097 6C6F636B - 4097 7300 - 4098 .LASF7: - 4099 00a2 6C6F6E67 .ascii "long long unsigned int\000" - 4099 206C6F6E - 4099 6720756E - 4099 7369676E - 4099 65642069 - 4100 .LASF70: - 4101 00b9 4379506D .ascii "CyPmHviLviSaveDisable\000" - 4101 4876694C - 4101 76695361 - 4101 76654469 - 4101 7361626C - 4102 .LASF76: - 4103 00cf 746D7053 .ascii "tmpStatus\000" - 4103 74617475 - 4103 7300 - 4104 .LASF49: - 4105 00d9 6C766961 .ascii "lviaTrip\000" - 4105 54726970 - 4105 00 - 4106 .LASF22: - 4107 00e2 696D6F55 .ascii "imoUsbClk\000" - 4107 7362436C - 4107 6B00 - 4108 .LASF80: - 4109 00ec 4379506D .ascii "CyPmFtwSetInterval\000" - 4109 46747753 - 4109 6574496E - 4109 74657276 - 4109 616C00 - 4110 .LASF50: - 4111 00ff 68766961 .ascii "hviaEn\000" - 4111 456E00 - 4112 .LASF105: - 4113 0106 43795664 .ascii "CyVdLvDigitEnable\000" - 4113 4C764469 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 112 - - - 4113 67697445 - 4113 6E61626C - 4113 6500 - 4114 .LASF36: - 4115 0118 696C6F50 .ascii "iloPowerMode\000" - 4115 6F776572 - 4115 4D6F6465 - 4115 00 - 4116 .LASF6: - 4117 0125 6C6F6E67 .ascii "long long int\000" - 4117 206C6F6E - 4117 6720696E - 4117 7400 - 4118 .LASF0: - 4119 0133 7369676E .ascii "signed char\000" - 4119 65642063 - 4119 68617200 - 4120 .LASF29: - 4121 013f 636C6B42 .ascii "clkBusDiv\000" - 4121 75734469 - 4121 7600 - 4122 .LASF68: - 4123 0149 696E7465 .ascii "interruptState\000" - 4123 72727570 - 4123 74537461 - 4123 746500 - 4124 .LASF108: - 4125 0158 4379494C .ascii "CyILO_Start1K\000" - 4125 4F5F5374 - 4125 61727431 - 4125 4B00 - 4126 .LASF27: - 4127 0166 696D6F32 .ascii "imo2x\000" - 4127 7800 - 4128 .LASF4: - 4129 016c 6C6F6E67 .ascii "long int\000" - 4129 20696E74 - 4129 00 - 4130 .LASF72: - 4131 0175 4379506D .ascii "CyPmHviLviRestore\000" - 4131 4876694C - 4131 76695265 - 4131 73746F72 - 4131 6500 - 4132 .LASF9: - 4133 0187 75696E74 .ascii "uint8\000" - 4133 3800 - 4134 .LASF99: - 4135 018d 4379504C .ascii "CyPLL_OUT_Start\000" - 4135 4C5F4F55 - 4135 545F5374 - 4135 61727400 - 4136 .LASF13: - 4137 019d 646F7562 .ascii "double\000" - 4137 6C6500 - 4138 .LASF112: - 4139 01a4 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\cyPm.c\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 113 - - - 4139 6E657261 - 4139 7465645F - 4139 536F7572 - 4139 63655C50 - 4140 .LASF11: - 4141 01c4 75696E74 .ascii "uint32\000" - 4141 333200 - 4142 .LASF31: - 4143 01cb 786D687A .ascii "xmhzEnableState\000" - 4143 456E6162 - 4143 6C655374 - 4143 61746500 - 4144 .LASF71: - 4145 01db 4379506D .ascii "CyPmHibRestore\000" - 4145 48696252 - 4145 6573746F - 4145 726500 - 4146 .LASF74: - 4147 01ea 6D61736B .ascii "mask\000" - 4147 00 - 4148 .LASF53: - 4149 01ef 696D6F41 .ascii "imoActFreq\000" - 4149 63744672 - 4149 657100 - 4150 .LASF8: - 4151 01fa 756E7369 .ascii "unsigned int\000" - 4151 676E6564 - 4151 20696E74 - 4151 00 - 4152 .LASF45: - 4153 0207 73636374 .ascii "scctData\000" - 4153 44617461 - 4153 00 - 4154 .LASF88: - 4155 0210 4379494D .ascii "CyIMO_SetSource\000" - 4155 4F5F5365 - 4155 74536F75 - 4155 72636500 - 4156 .LASF21: - 4157 0220 696D6F46 .ascii "imoFreq\000" - 4157 72657100 - 4158 .LASF5: - 4159 0228 6C6F6E67 .ascii "long unsigned int\000" - 4159 20756E73 - 4159 69676E65 - 4159 6420696E - 4159 7400 - 4160 .LASF46: - 4161 023a 6C766964 .ascii "lvidEn\000" - 4161 456E00 - 4162 .LASF34: - 4163 0241 6379506D .ascii "cyPmClockBackupStruct\000" - 4163 436C6F63 - 4163 6B426163 - 4163 6B757053 - 4163 74727563 - 4164 .LASF115: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccJaWbtc.s page 114 - - - 4165 0257 4379456E .ascii "CyEnterCriticalSection\000" - 4165 74657243 - 4165 72697469 - 4165 63616C53 - 4165 65637469 - 4166 .LASF35: - 4167 026e 6379506D .ascii "cyPmBackupStruct\000" - 4167 4261636B - 4167 75705374 - 4167 72756374 - 4167 00 - 4168 .LASF104: - 4169 027f 4379494C .ascii "CyILO_SetPowerMode\000" - 4169 4F5F5365 - 4169 74506F77 - 4169 65724D6F - 4169 646500 - 4170 .LASF96: - 4171 0292 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zD8|1NnqIHyY2vdP^6BEsS?#~0<(*0&>xoAr_@1iLI$E<%-R&3G%0ByW$#E3_KF3Fn z;}upN2eg?7)uSV!#Y>hfQbrxGy84^2tRpLZG8?tdk2R&g9>_d3{(ytCj00Hv7%S^I zGJR(G-UF`|$MLv2$JEEBs@^%2`9_|37MVVJvcAl)zSvOhSbfhqSjH(lx*bX%aN4Jz zA8^18_6HoAPQL0RI6SM(JoA3fnWFQ|%|2&*|6}cR)ATXhdrs?|4bxhaC&m%X|0Kop zV~*Kz2thLI=z%Qzz~Ozq(xEu(NI~wWsAZ3Bh*_wht4Vh3F=>2yqZd`%e(7(J$NM#>4x1y1!M{b1?bb zlWG4kVpxb5iSXxTjm5MJzf^zM!*9~?Pxaf19|@9fv-(x`NYfq>_RbKSgt!Q#Kfffx zKdyNq{);>~$M=9d+&CX5;z8^CT7CvNXEk)mhh8Ibtq`9i!pL`s_=)&y#C6v1FKOpv z?6*sZM~K*vzCgt9E>06+{~N@=L3`qd&>sS zd0R9MJA8_B;Rato#3b|Cn0T2+yn+Z99u%sGcsO6E`Fu{N9;Q@blSYJC(Qr*6x>R_h z#+x<9H15-QhsNU?InT8JsKzHXp3?Y&#uqjIL?h$Mb`u)k)mVUdk<2a-Rb5r@u-F66v{KU*W;S4m%^v0dXP zjr|(OG~S`{6B?h;$a@y;d`shbjTbfI!Ai*sG)^OWaDJh27O@WRky^fhh!-6G%AMG# z`74N1@TV{uuP3724VsQ>Olmx&@q|YHNd?no|EBR(jjwCuPcS*Iw~2n7-)l6G z+w6A=5%NlnwVJJ3pTl=*YsbA7>C;jtipV1EFeN}IuY`K zrsryTo#rniVmwWnUajeMn!brxjrr6xe}74P$25LM5$o|4jq3Ri^y`{VY5a>u{-Blme3vEiPcDe+z7ACPb*$q$@_~FeCi1%;BLA#{ z*r|~};U~RCBmb;|>v^}vag7Hw@-Hg5j*n@)UnBpPk9_`d1@V-|uW9^-Mr?n=6`IUn zyw$4vyh%jfRuhr0bwuO|pJzD_VItz!O2jxjiST2pN*^BYZ15aE}4K8Afi{fB=GiJ - 18:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #include - 19:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #include - 20:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #include - 21:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #include - 22:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #include - 23:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 24:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_NEED_CYCLOCKSTARTUPERROR 1 - 25:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 26:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 27:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #if defined(__GNUC__) || defined(__ARMCC_VERSION) - 28:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYPACKED - 29:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYPACKED_ATTR __attribute__ ((packed)) - 30:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYALIGNED __attribute__ ((aligned)) - 31:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_UNUSED __attribute__ ((unused)) - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 2 - - - 32:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) - 33:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 34:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #if defined(__ARMCC_VERSION) - 35:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_MEMORY_BARRIER() __memory_changed() - 36:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #else - 37:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() - 38:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #endif - 39:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 40:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #elif defined(__ICCARM__) - 41:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #include - 42:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 43:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYPACKED __packed - 44:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYPACKED_ATTR - 45:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYALIGNED _Pragma("data_alignment=4") - 46:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") - 47:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") - 48:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 49:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_MEMORY_BARRIER() __DMB() - 50:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 51:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #else - 52:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #error Unsupported toolchain - 53:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #endif - 54:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 55:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 56:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 57:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CYMEMZERO(void *s, size_t n); - 58:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 59:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CYMEMZERO(void *s, size_t n) - 60:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 61:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memset(s, 0, n); - 62:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 63:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 64:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CYCONFIGCPY(void *dest, const void *src, size_t n); - 65:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 66:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CYCONFIGCPY(void *dest, const void *src, size_t n) - 67:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 68:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 69:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 70:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 71:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); - 72:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 73:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) - 74:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 76:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 77:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 78:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 79:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 80:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Clock startup error codes */ - 81:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYCLOCKSTART_NO_ERROR 0u - 82:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYCLOCKSTART_XTAL_ERROR 1u - 83:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYCLOCKSTART_32KHZ_ERROR 2u - 84:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CYCLOCKSTART_PLL_ERROR 3u - 85:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 86:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #ifdef CY_NEED_CYCLOCKSTARTUPERROR - 87:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* - 88:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: CyClockStartupError - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 3 - - - 89:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** - 90:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Summary: - 91:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * If an error is encountered during clock configuration (crystal startup error, - 92:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * PLL lock error, etc.), the system will end up here. Unless reimplemented by - 93:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * the customer, this function will stop in an infinite loop. - 94:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 95:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Parameters: - 96:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 97:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 98:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Return: - 99:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 100:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 101:.\Generated_Source\PSoC5/cyfitter_cfg.c **** *******************************************************************************/ - 102:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 103:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CyClockStartupError(uint8 errorCode); - 104:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_CFG_UNUSED - 105:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void CyClockStartupError(uint8 errorCode) - 106:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 107:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* To remove the compiler warning if errorCode not used. */ - 108:.\Generated_Source\PSoC5/cyfitter_cfg.c **** errorCode = errorCode; - 109:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 110:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* `#START CyClockStartupError` */ - 111:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 112:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ - 113:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* we will end up here to allow the customer to implement something to */ - 114:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* deal with the clock condition. */ - 115:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 116:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* `#END` */ - 117:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 118:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* If nothing else, stop here since the clocks have not started */ - 119:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* correctly. */ - 120:.\Generated_Source\PSoC5/cyfitter_cfg.c **** while(1) {} - 121:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 122:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #endif - 123:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 124:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_CFG_BASE_ADDR_COUNT 12u - 125:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYPACKED typedef struct - 126:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 127:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 offset; - 128:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 value; - 129:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } CYPACKED_ATTR cy_cfg_addrvalue_t; - 130:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 131:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 132:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 133:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* - 134:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: cfg_write_bytes32 - 135:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** - 136:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Summary: - 137:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * This function is used for setting up the chip configuration areas that - 138:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * contain relatively sparse data. - 139:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 140:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Parameters: - 141:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 142:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 143:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Return: - 144:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 145:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 4 - - - 146:.\Generated_Source\PSoC5/cyfitter_cfg.c **** *******************************************************************************/ - 147:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); - 148:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) - 149:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 150:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* For 32-bit little-endian architectures */ - 151:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint32 i, j = 0u; - 152:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) - 153:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 154:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint32 baseAddr = addr_table[i]; - 155:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 count = (uint8)baseAddr; - 156:.\Generated_Source\PSoC5/cyfitter_cfg.c **** baseAddr &= 0xFFFFFF00u; - 157:.\Generated_Source\PSoC5/cyfitter_cfg.c **** while (count != 0u) - 158:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 159:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); - 160:.\Generated_Source\PSoC5/cyfitter_cfg.c **** j++; - 161:.\Generated_Source\PSoC5/cyfitter_cfg.c **** count--; - 162:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 163:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 164:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 165:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 166:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* - 167:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: ClockSetup - 168:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** - 169:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 170:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Summary: - 171:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Performs the initialization of all of the clocks in the device based on the - 172:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * settings in the Clock tab of the DWR. This includes enabling the requested - 173:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * clocks and setting the necessary dividers to produce the desired frequency. - 174:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 175:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Parameters: - 176:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 177:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 178:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Return: - 179:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 180:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 181:.\Generated_Source\PSoC5/cyfitter_cfg.c **** *******************************************************************************/ - 182:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void ClockSetup(void); - 183:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void ClockSetup(void) - 184:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 185:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint32 timeout; - 186:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 pllLock; - 187:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 188:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 189:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Configure ILO based on settings from Clock DWR */ - 190:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); - 191:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 192:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Configure IMO based on settings from Clock DWR */ - 193:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); - 194:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_ - 195:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 196:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Configure PLL based on settings from Clock DWR */ - 197:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); - 198:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); - 199:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Wait up to 250us for the PLL to lock */ - 200:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0u; - 201:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) - 202:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 5 - - - 203:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_ - 204:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ - 205:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 206:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* If we ran out of time the PLL didn't lock so go to the error function */ - 207:.\Generated_Source\PSoC5/cyfitter_cfg.c **** if (timeout == 0u) - 208:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 209:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CyClockStartupError(CYCLOCKSTART_PLL_ERROR); - 210:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 211:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 212:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Configure Bus/Master Clock based on settings from Clock DWR */ - 213:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); - 214:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); - 215:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); - 216:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); - 217:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); - 218:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 219:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Configure USB Clock based on settings from Clock DWR */ - 220:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); - 221:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); - 222:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 223:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 224:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 225:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Analog API Functions */ - 226:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 227:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 228:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* - 229:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: AnalogSetDefault - 230:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** - 231:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 232:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Summary: - 233:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Sets up the analog portions of the chip to default values based on chip - 234:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * configuration options from the project. - 235:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 236:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Parameters: - 237:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 238:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 239:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Return: - 240:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 241:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 242:.\Generated_Source\PSoC5/cyfitter_cfg.c **** *******************************************************************************/ - 243:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void AnalogSetDefault(void); - 244:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static void AnalogSetDefault(void) - 245:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 246:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + - 247:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - 248:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); - 249:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); - 250:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 251:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 252:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 253:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* - 254:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: SetAnalogRoutingPumps - 255:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** - 256:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 257:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Summary: - 258:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Enables or disables the analog pumps feeding analog routing switches. - 259:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Intended to be called at startup, based on the Vdda system configuration; - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 6 - - - 260:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * may be called during operation when the user informs us that the Vdda voltage - 261:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * crossed the pump threshold. - 262:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 263:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Parameters: - 264:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * enabled - 1 to enable the pumps, 0 to disable the pumps - 265:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 266:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Return: - 267:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 268:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 269:.\Generated_Source\PSoC5/cyfitter_cfg.c **** *******************************************************************************/ - 270:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void SetAnalogRoutingPumps(uint8 enabled) - 271:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 27 .loc 1 271 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 32 .LVL0: - 272:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); - 33 .loc 1 272 0 - 34 0000 014B ldr r3, .L2 - 35 0002 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 36 .LVL1: - 273:.\Generated_Source\PSoC5/cyfitter_cfg.c **** if (enabled != 0u) - 274:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 275:.\Generated_Source\PSoC5/cyfitter_cfg.c **** regValue |= 0x00u; - 276:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 277:.\Generated_Source\PSoC5/cyfitter_cfg.c **** else - 278:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 279:.\Generated_Source\PSoC5/cyfitter_cfg.c **** regValue &= (uint8)~0x00u; - 280:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 281:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); - 37 .loc 1 281 0 - 38 0004 1A70 strb r2, [r3, #0] - 39 0006 7047 bx lr - 40 .L3: - 41 .align 2 - 42 .L2: - 43 0008 76580040 .word 1073764470 - 44 .cfi_endproc - 45 .LFE7: - 46 .size SetAnalogRoutingPumps, .-SetAnalogRoutingPumps - 47 .section .text.cyfitter_cfg,"ax",%progbits - 48 .align 1 - 49 .global cyfitter_cfg - 50 .thumb - 51 .thumb_func - 52 .type cyfitter_cfg, %function - 53 cyfitter_cfg: - 54 .LFB8: - 282:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 283:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 284:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #define CY_AMUX_UNUSED CYREG_BOOST_SR - 285:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 286:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 287:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /******************************************************************************* - 288:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Function Name: cyfitter_cfg - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 7 - - - 289:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ******************************************************************************** - 290:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Summary: - 291:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * This function is called by the start-up code for the selected device. It - 292:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * performs all of the necessary device configuration based on the design - 293:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * settings. This includes settings from the Design Wide Resources (DWR) such - 294:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * as Clocks and Pins as well as any component configuration that is necessary. - 295:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 296:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Parameters: - 297:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 298:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 299:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * Return: - 300:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * void - 301:.\Generated_Source\PSoC5/cyfitter_cfg.c **** * - 302:.\Generated_Source\PSoC5/cyfitter_cfg.c **** *******************************************************************************/ - 303:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) - 305:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 55 .loc 1 305 0 - 56 .cfi_startproc - 57 @ args = 0, pretend = 0, frame = 0 - 58 @ frame_needed = 0, uses_anonymous_args = 0 - 59 0000 F8B5 push {r3, r4, r5, r6, r7, lr} - 60 .LCFI0: - 61 .cfi_def_cfa_offset 24 - 62 .cfi_offset 3, -24 - 63 .cfi_offset 4, -20 - 64 .cfi_offset 5, -16 - 65 .cfi_offset 6, -12 - 66 .cfi_offset 7, -8 - 67 .cfi_offset 14, -4 - 306:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */ - 307:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_0_VAL[] = { - 308:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - 309:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 310:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ - 311:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { - 312:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; - 313:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 314:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ - 315:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { - 316:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - 317:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 318:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ - 319:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { - 320:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - 321:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 322:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ - 323:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { - 324:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - 325:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 326:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #ifdef CYGlobalIntDisable - 327:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Disable interrupts by default. Let user enable if/when they want. */ - 328:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYGlobalIntDisable - 68 .loc 1 328 0 - 69 @ 328 ".\Generated_Source\PSoC5\cyfitter_cfg.c" 1 - 70 0002 72B6 CPSID i - 71 @ 0 "" 2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 8 - - - 329:.\Generated_Source\PSoC5/cyfitter_cfg.c **** #endif - 330:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 331:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 332:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). * - 333:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01 - 72 .loc 1 333 0 - 73 .thumb - 74 0004 5E4B ldr r3, .L23 - 75 0006 0122 movs r2, #1 - 76 .LBB32: - 77 .LBB33: - 190:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); - 78 .loc 1 190 0 - 79 0008 A3F5A061 sub r1, r3, #1280 - 193:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); - 80 .loc 1 193 0 - 81 000c A1F58075 sub r5, r1, #256 - 190:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); - 82 .loc 1 190 0 - 83 0010 0620 movs r0, #6 - 193:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); - 84 .loc 1 193 0 - 85 0012 5224 movs r4, #82 - 194:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_ - 86 .loc 1 194 0 - 87 0014 5B4E ldr r6, .L23+4 - 88 .LBE33: - 89 .LBE32: - 90 .loc 1 333 0 - 91 0016 1A70 strb r2, [r3, #0] - 92 .LBB36: - 93 .LBB34: - 190:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); - 94 .loc 1 190 0 - 95 0018 0870 strb r0, [r1, #0] - 193:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); - 96 .loc 1 193 0 - 97 001a 2C70 strb r4, [r5, #0] - 194:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_ - 98 .loc 1 194 0 - 99 001c 3778 ldrb r7, [r6, #0] @ zero_extendqisi2 - 197:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); - 100 .loc 1 197 0 - 101 001e 5A4B ldr r3, .L23+8 - 194:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_ - 102 .loc 1 194 0 - 103 0020 5A4A ldr r2, .L23+12 - 197:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); - 104 .loc 1 197 0 - 105 0022 40F61800 movw r0, #2072 - 198:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); - 106 .loc 1 198 0 - 107 0026 41F25121 movw r1, #4689 - 194:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_ - 108 .loc 1 194 0 - 109 002a 1770 strb r7, [r2, #0] - 198:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 9 - - - 110 .loc 1 198 0 - 111 002c 1925 movs r5, #25 - 197:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); - 112 .loc 1 197 0 - 113 002e 1880 strh r0, [r3, #0] @ movhi - 200:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0u; - 114 .loc 1 200 0 - 115 0030 0024 movs r4, #0 - 198:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); - 116 .loc 1 198 0 - 117 0032 23F8021C strh r1, [r3, #-2] @ movhi - 118 .LVL2: - 119 .L6: - 203:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_ - 120 .loc 1 203 0 - 121 0036 564E ldr r6, .L23+16 - 204:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ - 122 .loc 1 204 0 - 123 0038 4FF4F070 mov r0, #480 - 203:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_ - 124 .loc 1 203 0 - 125 003c 3778 ldrb r7, [r6, #0] @ zero_extendqisi2 - 126 003e 07F00102 and r2, r7, #1 - 127 0042 42EA4404 orr r4, r2, r4, lsl #1 - 204:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ - 128 .loc 1 204 0 - 129 0046 FFF7FEFF bl CyDelayCycles - 130 .LVL3: - 201:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) - 131 .loc 1 201 0 - 132 004a 013D subs r5, r5, #1 - 203:.\Generated_Source\PSoC5/cyfitter_cfg.c **** pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_ - 133 .loc 1 203 0 - 134 004c 04F00304 and r4, r4, #3 - 135 .LVL4: - 201:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) - 136 .loc 1 201 0 - 137 0050 17D0 beq .L5 - 138 0052 032C cmp r4, #3 - 139 0054 EFD1 bne .L6 - 213:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); - 140 .loc 1 213 0 - 141 0056 4F48 ldr r0, .L23+20 - 215:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); - 142 .loc 1 215 0 - 143 0058 4F4F ldr r7, .L23+24 - 144 005a 0026 movs r6, #0 - 213:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); - 145 .loc 1 213 0 - 146 005c 4FF48073 mov r3, #256 - 147 .LBE34: - 148 .LBE36: - 334:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Setup clocks based on selections from Clock DWR */ - 335:.\Generated_Source\PSoC5/cyfitter_cfg.c **** ClockSetup(); - 336:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable/Disable Debug functionality based on settings from System DWR */ - 337:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DE - 149 .loc 1 337 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 10 - - - 150 0060 4E4D ldr r5, .L23+28 - 151 .LBB37: - 152 .LBB35: - 214:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); - 153 .loc 1 214 0 - 154 0062 0721 movs r1, #7 - 216:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); - 155 .loc 1 216 0 - 156 0064 4822 movs r2, #72 - 221:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); - 157 .loc 1 221 0 - 158 0066 0224 movs r4, #2 - 159 .LVL5: - 213:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); - 160 .loc 1 213 0 - 161 0068 0380 strh r3, [r0, #0] @ movhi - 214:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); - 162 .loc 1 214 0 - 163 006a 0170 strb r1, [r0, #0] - 215:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); - 164 .loc 1 215 0 - 165 006c 3E70 strb r6, [r7, #0] - 216:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); - 166 .loc 1 216 0 - 167 006e BA70 strb r2, [r7, #2] - 217:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); - 168 .loc 1 217 0 - 169 0070 0670 strb r6, [r0, #0] - 220:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); - 170 .loc 1 220 0 - 171 0072 4671 strb r6, [r0, #5] - 221:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); - 172 .loc 1 221 0 - 173 0074 00F8034C strb r4, [r0, #-3] - 174 .LBE35: - 175 .LBE37: - 176 .loc 1 337 0 - 177 0078 2878 ldrb r0, [r5, #0] @ zero_extendqisi2 - 178 007a 40F00403 orr r3, r0, #4 - 179 007e 2B70 strb r3, [r5, #0] - 180 .LVL6: - 181 0080 00E0 b .L8 - 182 .LVL7: - 183 .L5: - 184 0082 FEE7 b .L5 - 185 .LVL8: - 186 .L8: - 187 .LBB38: - 188 .LBB39: - 338:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 339:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 340:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const uint32 CYCODE cy_cfg_addr_table[] = { - 341:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40004501u, /* Base address: 0x40004500 Count: 1 */ - 342:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40005202u, /* Base address: 0x40005200 Count: 2 */ - 343:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40011701u, /* Base address: 0x40011700 Count: 1 */ - 344:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40011901u, /* Base address: 0x40011900 Count: 1 */ - 345:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014003u, /* Base address: 0x40014000 Count: 3 */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 11 - - - 346:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014102u, /* Base address: 0x40014100 Count: 2 */ - 347:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014202u, /* Base address: 0x40014200 Count: 2 */ - 348:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014302u, /* Base address: 0x40014300 Count: 2 */ - 349:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014703u, /* Base address: 0x40014700 Count: 3 */ - 350:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014803u, /* Base address: 0x40014800 Count: 3 */ - 351:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ - 352:.\Generated_Source\PSoC5/cyfitter_cfg.c **** 0x40015101u, /* Base address: 0x40015100 Count: 1 */ - 353:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; - 354:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 355:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { - 356:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x7Eu, 0x02u}, - 357:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x1Cu, 0x3Eu}, - 358:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x7Cu, 0x40u}, - 359:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x0Au}, - 360:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x0Au}, - 361:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x33u, 0x80u}, - 362:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x36u, 0x40u}, - 363:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xCCu, 0x30u}, - 364:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, - 365:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, - 366:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, - 367:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, - 368:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA6u, 0x40u}, - 369:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xA7u, 0x80u}, - 370:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x08u, 0x08u}, - 371:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x0Fu, 0x40u}, - 372:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xC2u, 0x0Cu}, - 373:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAEu, 0x40u}, - 374:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAFu, 0x80u}, - 375:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xEEu, 0x50u}, - 376:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xACu, 0x08u}, - 377:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0xAFu, 0x40u}, - 378:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {0x00u, 0x0Au}, - 379:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; - 380:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 381:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 382:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 383:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYPACKED typedef struct { - 384:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void CYFAR *address; - 385:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint16 size; - 386:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } CYPACKED_ATTR cfg_memset_t; - 387:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 388:.\Generated_Source\PSoC5/cyfitter_cfg.c **** static const cfg_memset_t CYCODE cfg_memset_list [] = { - 389:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* address, size */ - 390:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT1_DR), 32u}, - 391:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT5_DR), 16u}, - 392:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_PRT12_DR), 16u}, - 393:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - 394:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, - 395:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, - 396:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, - 397:.\Generated_Source\PSoC5/cyfitter_cfg.c **** {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, - 398:.\Generated_Source\PSoC5/cyfitter_cfg.c **** }; - 399:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 400:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 CYDATA i; - 401:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 402:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Zero out critical memory blocks before beginning configuration */ - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 12 - - - 403:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - 404:.\Generated_Source\PSoC5/cyfitter_cfg.c **** { - 405:.\Generated_Source\PSoC5/cyfitter_cfg.c **** const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; - 189 .loc 1 405 0 discriminator 2 - 190 0084 464F ldr r7, .L23+32 - 191 0086 0621 movs r1, #6 - 192 0088 01FB0672 mla r2, r1, r6, r7 - 193 .LVL9: - 194 .LBB40: - 195 .LBB41: - 61:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memset(s, 0, n); - 196 .loc 1 61 0 discriminator 2 - 197 008c 0021 movs r1, #0 - 198 008e 1068 ldr r0, [r2, #0] @ unaligned - 199 0090 0136 adds r6, r6, #1 - 200 .LVL10: - 201 0092 9288 ldrh r2, [r2, #4] @ unaligned - 202 .LVL11: - 203 0094 FFF7FEFF bl memset - 204 .LVL12: - 205 .LBE41: - 206 .LBE40: - 207 .LBE39: - 403:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - 208 .loc 1 403 0 discriminator 2 - 209 0098 082E cmp r6, #8 - 210 009a F3D1 bne .L8 - 403:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - 211 .loc 1 403 0 is_stmt 0 - 212 009c 0023 movs r3, #0 - 213 009e 1946 mov r1, r3 - 214 .LVL13: - 215 .L11: - 216 .LBB42: - 217 .LBB43: - 218 .LBB44: - 154:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint32 baseAddr = addr_table[i]; - 219 .loc 1 154 0 is_stmt 1 - 220 00a0 404C ldr r4, .L23+36 - 221 .LBE44: - 222 .LBE43: - 223 .LBE42: - 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) - 224 .loc 1 304 0 - 225 00a2 0022 movs r2, #0 - 226 .LBB47: - 227 .LBB46: - 228 .LBB45: - 154:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint32 baseAddr = addr_table[i]; - 229 .loc 1 154 0 - 230 00a4 1859 ldr r0, [r3, r4] - 231 .LVL14: - 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) - 232 .loc 1 304 0 - 233 00a6 3034 adds r4, r4, #48 - 155:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 count = (uint8)baseAddr; - 234 .loc 1 155 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 13 - - - 235 00a8 C6B2 uxtb r6, r0 - 236 .LVL15: - 156:.\Generated_Source\PSoC5/cyfitter_cfg.c **** baseAddr &= 0xFFFFFF00u; - 237 .loc 1 156 0 - 238 00aa 20F0FF07 bic r7, r0, #255 - 239 .LVL16: - 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) - 240 .loc 1 304 0 - 241 00ae 04EB4104 add r4, r4, r1, lsl #1 - 242 .LVL17: - 243 .L9: - 157:.\Generated_Source\PSoC5/cyfitter_cfg.c **** while (count != 0u) - 244 .loc 1 157 0 - 245 00b2 D5B2 uxtb r5, r2 - 246 00b4 AE42 cmp r6, r5 - 247 00b6 09D0 beq .L22 - 248 .L10: - 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) - 249 .loc 1 304 0 - 250 00b8 04EB420C add ip, r4, r2, lsl #1 - 159:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); - 251 .loc 1 159 0 - 252 00bc 14F81250 ldrb r5, [r4, r2, lsl #1] @ zero_extendqisi2 - 253 00c0 9CF801E0 ldrb lr, [ip, #1] @ zero_extendqisi2 - 254 00c4 0132 adds r2, r2, #1 - 255 00c6 05F807E0 strb lr, [r5, r7] - 256 00ca F2E7 b .L9 - 257 .L22: - 258 00cc 0433 adds r3, r3, #4 - 304:.\Generated_Source\PSoC5/cyfitter_cfg.c **** void cyfitter_cfg(void) - 259 .loc 1 304 0 - 260 00ce C0B2 uxtb r0, r0 - 261 .LBE45: - 152:.\Generated_Source\PSoC5/cyfitter_cfg.c **** for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) - 262 .loc 1 152 0 - 263 00d0 302B cmp r3, #48 - 264 00d2 0144 add r1, r1, r0 - 265 .LVL18: - 266 00d4 E4D1 bne .L11 - 267 .LBE46: - 268 .LBE47: - 406:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYMEMZERO(ms->address, (uint32)(ms->size)); - 407:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 408:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 409:.\Generated_Source\PSoC5/cyfitter_cfg.c **** cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - 410:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 411:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable digital routing */ - 412:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_B - 269 .loc 1 412 0 - 270 00d6 344C ldr r4, .L23+40 - 271 00d8 2278 ldrb r2, [r4, #0] @ zero_extendqisi2 - 272 00da 42F00200 orr r0, r2, #2 - 273 00de 2070 strb r0, [r4, #0] - 413:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B - 274 .loc 1 413 0 - 275 00e0 217C ldrb r1, [r4, #16] @ zero_extendqisi2 - 276 .LVL19: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 14 - - - 414:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 415:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Enable UDB array */ - 416:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG - 417:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_ - 277 .loc 1 417 0 - 278 00e2 3248 ldr r0, .L23+44 - 413:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B - 279 .loc 1 413 0 - 280 00e4 41F00203 orr r3, r1, #2 - 416:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG - 281 .loc 1 416 0 - 282 00e8 3149 ldr r1, .L23+48 - 413:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_B - 283 .loc 1 413 0 - 284 00ea 2374 strb r3, [r4, #16] - 416:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG - 285 .loc 1 416 0 - 286 00ec 0C78 ldrb r4, [r1, #0] @ zero_extendqisi2 - 287 00ee 44F04002 orr r2, r4, #64 - 288 00f2 0A70 strb r2, [r1, #0] - 289 .loc 1 417 0 - 290 00f4 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 291 .loc 1 75 0 - 292 00f6 2F4A ldr r2, .L23+52 - 293 .loc 1 417 0 - 294 00f8 43F01004 orr r4, r3, #16 - 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 295 .loc 1 75 0 - 296 00fc 2E4B ldr r3, .L23+56 - 297 .loc 1 417 0 - 298 00fe 0470 strb r4, [r0, #0] - 299 .LVL20: - 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 300 .loc 1 75 0 - 301 0100 1868 ldr r0, [r3, #0] @ unaligned - 302 0102 5C68 ldr r4, [r3, #4] @ unaligned - 303 0104 1060 str r0, [r2, #0] @ unaligned - 304 0106 5460 str r4, [r2, #4] @ unaligned - 305 .LVL21: - 306 0108 1A46 mov r2, r3 - 307 010a 2C48 ldr r0, .L23+60 - 308 010c 52F8084F ldr r4, [r2, #8]! @ unaligned - 309 0110 0460 str r4, [r0, #0] @ unaligned - 310 0112 5468 ldr r4, [r2, #4] @ unaligned - 311 0114 1289 ldrh r2, [r2, #8] @ unaligned - 312 0116 4460 str r4, [r0, #4] @ unaligned - 313 0118 0281 strh r2, [r0, #8] @ unaligned - 314 .LVL22: - 315 011a 1A46 mov r2, r3 - 316 011c 52F8124F ldr r4, [r2, #18]! @ unaligned - 317 0120 5268 ldr r2, [r2, #4] @ unaligned - 318 0122 40F8BE4C str r4, [r0, #-190] @ unaligned - 319 0126 40F8BA2C str r2, [r0, #-186] @ unaligned - 320 .LVL23: - 321 012a 1A46 mov r2, r3 - 322 012c 52F81A4F ldr r4, [r2, #26]! @ unaligned - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 15 - - - 323 0130 5268 ldr r2, [r2, #4] @ unaligned - 324 0132 40F8AE4C str r4, [r0, #-174] @ unaligned - 325 0136 40F8AA2C str r2, [r0, #-170] @ unaligned - 326 .LVL24: - 327 013a 53F8220F ldr r0, [r3, #34]! @ unaligned - 328 013e 204A ldr r2, .L23+64 - 329 0140 5B68 ldr r3, [r3, #4] @ unaligned - 330 0142 1060 str r0, [r2, #0] @ unaligned - 331 .LBE38: - 418:.\Generated_Source\PSoC5/cyfitter_cfg.c **** } - 419:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 420:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Perform second pass device configuration. These items must be configured in specific order afte - 421:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); - 422:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); - 423:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); - 424:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); - 425:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); - 426:.\Generated_Source\PSoC5/cyfitter_cfg.c **** - 427:.\Generated_Source\PSoC5/cyfitter_cfg.c **** /* Switch Boost to the precision bandgap reference from its internal reference */ - 428:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u - 332 .loc 1 428 0 - 333 0144 1F48 ldr r0, .L23+68 - 334 .LBB48: - 75:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 335 .loc 1 75 0 - 336 0146 5360 str r3, [r2, #4] @ unaligned - 337 .LBE48: - 338 .loc 1 428 0 - 339 0148 0278 ldrb r2, [r0, #0] @ zero_extendqisi2 - 340 014a 42F00803 orr r3, r2, #8 - 341 014e 0370 strb r3, [r0, #0] - 342 .LBB49: - 343 .LBB50: - 246:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + - 344 .loc 1 246 0 - 345 0150 1D48 ldr r0, .L23+72 - 247:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - 346 .loc 1 247 0 - 347 0152 1E4A ldr r2, .L23+76 - 246:.\Generated_Source\PSoC5/cyfitter_cfg.c **** uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + - 348 .loc 1 246 0 - 349 0154 0378 ldrb r3, [r0, #0] @ zero_extendqisi2 - 350 .LVL25: - 247:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - 351 .loc 1 247 0 - 352 0156 03F00700 and r0, r3, #7 - 248:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); - 353 .loc 1 248 0 - 354 015a 1B09 lsrs r3, r3, #4 - 355 .LVL26: - 247:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - 356 .loc 1 247 0 - 357 015c 1070 strb r0, [r2, #0] - 248:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); - 358 .loc 1 248 0 - 359 015e 5370 strb r3, [r2, #1] - 249:.\Generated_Source\PSoC5/cyfitter_cfg.c **** CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 16 - - - 360 .loc 1 249 0 - 361 0160 1B4A ldr r2, .L23+80 - 362 0162 4420 movs r0, #68 - 363 0164 1070 strb r0, [r2, #0] - 364 .LVL27: - 365 .LBE50: - 366 .LBE49: - 367 .LBB51: - 368 .LBB52: - 68:.\Generated_Source\PSoC5/cyfitter_cfg.c **** (void)memcpy(dest, src, n); - 369 .loc 1 68 0 - 370 0166 1B4A ldr r2, .L23+84 - 371 0168 0B46 mov r3, r1 - 372 016a 0C31 adds r1, r1, #12 - 373 .L12: - 374 016c 53F8040B ldr r0, [r3], #4 @ unaligned - 375 0170 8B42 cmp r3, r1 - 376 0172 42F8040B str r0, [r2], #4 @ unaligned - 377 0176 F9D1 bne .L12 - 378 0178 1988 ldrh r1, [r3, #0] @ unaligned - 379 017a 1180 strh r1, [r2, #0] @ unaligned - 380 017c F8BD pop {r3, r4, r5, r6, r7, pc} - 381 .L24: - 382 017e 00BF .align 2 - 383 .L23: - 384 0180 00480040 .word 1073760256 - 385 0184 0F010049 .word 1224737039 - 386 0188 22420040 .word 1073758754 - 387 018c A1460040 .word 1073759905 - 388 0190 25420040 .word 1073758757 - 389 0194 04400040 .word 1073758212 - 390 0198 06400040 .word 1073758214 - 391 019c E8460040 .word 1073759976 - 392 01a0 00000000 .word .LANCHOR0 - 393 01a4 30000000 .word .LANCHOR0+48 - 394 01a8 03500140 .word 1073827843 - 395 01ac C2430040 .word 1073759170 - 396 01b0 A0430040 .word 1073759136 - 397 01b4 02510040 .word 1073762562 - 398 01b8 8E000000 .word .LANCHOR0+142 - 399 01bc F0510040 .word 1073762800 - 400 01c0 62510040 .word 1073762658 - 401 01c4 22430040 .word 1073759010 - 402 01c8 CF010049 .word 1224737231 - 403 01cc 6E580040 .word 1073764462 - 404 01d0 76580040 .word 1073764470 - 405 01d4 B0430040 .word 1073759152 - 406 .LBE52: - 407 .LBE51: - 408 .cfi_endproc - 409 .LFE8: - 410 .size cyfitter_cfg, .-cyfitter_cfg - 411 .section .rodata - 412 .align 2 - 413 .set .LANCHOR0,. + 0 - 414 .type cfg_memset_list.4819, %object - 415 .size cfg_memset_list.4819, 48 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 17 - - - 416 cfg_memset_list.4819: - 417 0000 10510040 .4byte 1073762576 - 418 0004 2000 .2byte 32 - 419 0006 50510040 .4byte 1073762640 - 420 000a 1000 .2byte 16 - 421 000c C0510040 .4byte 1073762752 - 422 0010 1000 .2byte 16 - 423 0012 00000140 .4byte 1073807360 - 424 0016 0010 .2byte 4096 - 425 0018 00140140 .4byte 1073812480 - 426 001c 0008 .2byte 2048 - 427 001e 00400140 .4byte 1073823744 - 428 0022 000A .2byte 2560 - 429 0024 004C0140 .4byte 1073826816 - 430 0028 0002 .2byte 512 - 431 002a 00500140 .4byte 1073827840 - 432 002e 2000 .2byte 32 - 433 .type cy_cfg_addr_table.4813, %object - 434 .size cy_cfg_addr_table.4813, 48 - 435 cy_cfg_addr_table.4813: - 436 0030 01450040 .word 1073759489 - 437 0034 02520040 .word 1073762818 - 438 0038 01170140 .word 1073813249 - 439 003c 01190140 .word 1073813761 - 440 0040 03400140 .word 1073823747 - 441 0044 02410140 .word 1073824002 - 442 0048 02420140 .word 1073824258 - 443 004c 02430140 .word 1073824514 - 444 0050 03470140 .word 1073825539 - 445 0054 03480140 .word 1073825795 - 446 0058 024C0140 .word 1073826818 - 447 005c 01510140 .word 1073828097 - 448 .type cy_cfg_data_table.4814, %object - 449 .size cy_cfg_data_table.4814, 46 - 450 cy_cfg_data_table.4814: - 451 0060 7E .byte 126 - 452 0061 02 .byte 2 - 453 0062 1C .byte 28 - 454 0063 3E .byte 62 - 455 0064 7C .byte 124 - 456 0065 40 .byte 64 - 457 0066 EE .byte -18 - 458 0067 0A .byte 10 - 459 0068 EE .byte -18 - 460 0069 0A .byte 10 - 461 006a 33 .byte 51 - 462 006b 80 .byte -128 - 463 006c 36 .byte 54 - 464 006d 40 .byte 64 - 465 006e CC .byte -52 - 466 006f 30 .byte 48 - 467 0070 A6 .byte -90 - 468 0071 40 .byte 64 - 469 0072 A7 .byte -89 - 470 0073 80 .byte -128 - 471 0074 A6 .byte -90 - 472 0075 40 .byte 64 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 18 - - - 473 0076 A7 .byte -89 - 474 0077 80 .byte -128 - 475 0078 A6 .byte -90 - 476 0079 40 .byte 64 - 477 007a A7 .byte -89 - 478 007b 80 .byte -128 - 479 007c 08 .byte 8 - 480 007d 08 .byte 8 - 481 007e 0F .byte 15 - 482 007f 40 .byte 64 - 483 0080 C2 .byte -62 - 484 0081 0C .byte 12 - 485 0082 AE .byte -82 - 486 0083 40 .byte 64 - 487 0084 AF .byte -81 - 488 0085 80 .byte -128 - 489 0086 EE .byte -18 - 490 0087 50 .byte 80 - 491 0088 AC .byte -84 - 492 0089 08 .byte 8 - 493 008a AF .byte -81 - 494 008b 40 .byte 64 - 495 008c 00 .byte 0 - 496 008d 0A .byte 10 - 497 .type BS_IOPINS0_0_VAL.4808, %object - 498 .size BS_IOPINS0_0_VAL.4808, 8 - 499 BS_IOPINS0_0_VAL.4808: - 500 008e 00 .byte 0 - 501 008f FF .byte -1 - 502 0090 FF .byte -1 - 503 0091 00 .byte 0 - 504 0092 00 .byte 0 - 505 0093 00 .byte 0 - 506 0094 00 .byte 0 - 507 0095 00 .byte 0 - 508 .type BS_IOPINS0_8_VAL.4809, %object - 509 .size BS_IOPINS0_8_VAL.4809, 10 - 510 BS_IOPINS0_8_VAL.4809: - 511 0096 00 .byte 0 - 512 0097 00 .byte 0 - 513 0098 00 .byte 0 - 514 0099 00 .byte 0 - 515 009a 00 .byte 0 - 516 009b 00 .byte 0 - 517 009c 00 .byte 0 - 518 009d 00 .byte 0 - 519 009e C0 .byte -64 - 520 009f 00 .byte 0 - 521 .type BS_IOPINS0_3_VAL.4810, %object - 522 .size BS_IOPINS0_3_VAL.4810, 8 - 523 BS_IOPINS0_3_VAL.4810: - 524 00a0 00 .byte 0 - 525 00a1 3E .byte 62 - 526 00a2 00 .byte 0 - 527 00a3 00 .byte 0 - 528 00a4 00 .byte 0 - 529 00a5 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 19 - - - 530 00a6 00 .byte 0 - 531 00a7 00 .byte 0 - 532 .type BS_IOPINS0_4_VAL.4811, %object - 533 .size BS_IOPINS0_4_VAL.4811, 8 - 534 BS_IOPINS0_4_VAL.4811: - 535 00a8 00 .byte 0 - 536 00a9 FC .byte -4 - 537 00aa FC .byte -4 - 538 00ab 00 .byte 0 - 539 00ac 00 .byte 0 - 540 00ad 00 .byte 0 - 541 00ae 00 .byte 0 - 542 00af 00 .byte 0 - 543 .type BS_IOPINS0_6_VAL.4812, %object - 544 .size BS_IOPINS0_6_VAL.4812, 8 - 545 BS_IOPINS0_6_VAL.4812: - 546 00b0 00 .byte 0 - 547 00b1 0F .byte 15 - 548 00b2 0F .byte 15 - 549 00b3 00 .byte 0 - 550 00b4 00 .byte 0 - 551 00b5 00 .byte 0 - 552 00b6 00 .byte 0 - 553 00b7 00 .byte 0 - 554 .text - 555 .Letext0: - 556 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\3.0\\psoc creator\\import\\gnu_cs\\arm\\4 - 557 .file 3 "./Generated_Source/PSoC5/cytypes.h" - 558 .file 4 "./Generated_Source/PSoC5/CyLib.h" - 559 .section .debug_info,"",%progbits - 560 .Ldebug_info0: - 561 0000 45050000 .4byte 0x545 - 562 0004 0200 .2byte 0x2 - 563 0006 00000000 .4byte .Ldebug_abbrev0 - 564 000a 04 .byte 0x4 - 565 000b 01 .uleb128 0x1 - 566 000c 3C020000 .4byte .LASF52 - 567 0010 01 .byte 0x1 - 568 0011 2E010000 .4byte .LASF53 - 569 0015 99010000 .4byte .LASF54 - 570 0019 A0000000 .4byte .Ldebug_ranges0+0xa0 - 571 001d 00000000 .4byte 0 - 572 0021 00000000 .4byte 0 - 573 0025 00000000 .4byte .Ldebug_line0 - 574 0029 02 .uleb128 0x2 - 575 002a 01 .byte 0x1 - 576 002b 06 .byte 0x6 - 577 002c 8F000000 .4byte .LASF0 - 578 0030 02 .uleb128 0x2 - 579 0031 01 .byte 0x1 - 580 0032 08 .byte 0x8 - 581 0033 8A020000 .4byte .LASF1 - 582 0037 02 .uleb128 0x2 - 583 0038 02 .byte 0x2 - 584 0039 05 .byte 0x5 - 585 003a 98020000 .4byte .LASF2 - 586 003e 02 .uleb128 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 20 - - - 587 003f 02 .byte 0x2 - 588 0040 07 .byte 0x7 - 589 0041 75010000 .4byte .LASF3 - 590 0045 03 .uleb128 0x3 - 591 0046 04 .byte 0x4 - 592 0047 05 .byte 0x5 - 593 0048 696E7400 .ascii "int\000" - 594 004c 02 .uleb128 0x2 - 595 004d 04 .byte 0x4 - 596 004e 07 .byte 0x7 - 597 004f 21010000 .4byte .LASF4 - 598 0053 02 .uleb128 0x2 - 599 0054 08 .byte 0x8 - 600 0055 05 .byte 0x5 - 601 0056 81000000 .4byte .LASF5 - 602 005a 02 .uleb128 0x2 - 603 005b 08 .byte 0x8 - 604 005c 07 .byte 0x7 - 605 005d 3C000000 .4byte .LASF6 - 606 0061 02 .uleb128 0x2 - 607 0062 04 .byte 0x4 - 608 0063 05 .byte 0x5 - 609 0064 E5000000 .4byte .LASF7 - 610 0068 02 .uleb128 0x2 - 611 0069 04 .byte 0x4 - 612 006a 07 .byte 0x7 - 613 006b DA010000 .4byte .LASF8 - 614 006f 04 .uleb128 0x4 - 615 0070 04 .byte 0x4 - 616 0071 02 .uleb128 0x2 - 617 0072 04 .byte 0x4 - 618 0073 07 .byte 0x7 - 619 0074 56010000 .4byte .LASF9 - 620 0078 02 .uleb128 0x2 - 621 0079 01 .byte 0x1 - 622 007a 08 .byte 0x8 - 623 007b DF020000 .4byte .LASF10 - 624 007f 05 .uleb128 0x5 - 625 0080 16000000 .4byte .LASF11 - 626 0084 02 .byte 0x2 - 627 0085 D5 .byte 0xd5 - 628 0086 4C000000 .4byte 0x4c - 629 008a 05 .uleb128 0x5 - 630 008b F4000000 .4byte .LASF12 - 631 008f 03 .byte 0x3 - 632 0090 5B .byte 0x5b - 633 0091 30000000 .4byte 0x30 - 634 0095 05 .uleb128 0x5 - 635 0096 06000000 .4byte .LASF13 - 636 009a 03 .byte 0x3 - 637 009b 5C .byte 0x5c - 638 009c 3E000000 .4byte 0x3e - 639 00a0 05 .uleb128 0x5 - 640 00a1 0B010000 .4byte .LASF14 - 641 00a5 03 .byte 0x3 - 642 00a6 5D .byte 0x5d - 643 00a7 71000000 .4byte 0x71 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 21 - - - 644 00ab 02 .uleb128 0x2 - 645 00ac 04 .byte 0x4 - 646 00ad 04 .byte 0x4 - 647 00ae 28020000 .4byte .LASF15 - 648 00b2 02 .uleb128 0x2 - 649 00b3 08 .byte 0x8 - 650 00b4 04 .byte 0x4 - 651 00b5 FA000000 .4byte .LASF16 - 652 00b9 05 .uleb128 0x5 - 653 00ba 85020000 .4byte .LASF17 - 654 00be 03 .byte 0x3 - 655 00bf F0 .byte 0xf0 - 656 00c0 C4000000 .4byte 0xc4 - 657 00c4 06 .uleb128 0x6 - 658 00c5 8A000000 .4byte 0x8a - 659 00c9 05 .uleb128 0x5 - 660 00ca EE000000 .4byte .LASF18 - 661 00ce 03 .byte 0x3 - 662 00cf F1 .byte 0xf1 - 663 00d0 D4000000 .4byte 0xd4 - 664 00d4 06 .uleb128 0x6 - 665 00d5 95000000 .4byte 0x95 - 666 00d9 07 .uleb128 0x7 - 667 00da 02 .byte 0x2 - 668 00db 01 .byte 0x1 - 669 00dc 7D .byte 0x7d - 670 00dd FE000000 .4byte 0xfe - 671 00e1 08 .uleb128 0x8 - 672 00e2 FA020000 .4byte .LASF19 - 673 00e6 01 .byte 0x1 - 674 00e7 7F .byte 0x7f - 675 00e8 8A000000 .4byte 0x8a - 676 00ec 02 .byte 0x2 - 677 00ed 23 .byte 0x23 - 678 00ee 00 .uleb128 0 - 679 00ef 08 .uleb128 0x8 - 680 00f0 1B010000 .4byte .LASF20 - 681 00f4 01 .byte 0x1 - 682 00f5 80 .byte 0x80 - 683 00f6 8A000000 .4byte 0x8a - 684 00fa 02 .byte 0x2 - 685 00fb 23 .byte 0x23 - 686 00fc 01 .uleb128 0x1 - 687 00fd 00 .byte 0 - 688 00fe 05 .uleb128 0x5 - 689 00ff CC020000 .4byte .LASF21 - 690 0103 01 .byte 0x1 - 691 0104 81 .byte 0x81 - 692 0105 D9000000 .4byte 0xd9 - 693 0109 09 .uleb128 0x9 - 694 010a 1D000000 .4byte .LASF22 - 695 010e 01 .byte 0x1 - 696 010f 69 .byte 0x69 - 697 0110 01 .byte 0x1 - 698 0111 01 .byte 0x1 - 699 0112 22010000 .4byte 0x122 - 700 0116 0A .uleb128 0xa - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 22 - - - 701 0117 CA000000 .4byte .LASF24 - 702 011b 01 .byte 0x1 - 703 011c 69 .byte 0x69 - 704 011d 8A000000 .4byte 0x8a - 705 0121 00 .byte 0 - 706 0122 09 .uleb128 0x9 - 707 0123 CA010000 .4byte .LASF23 - 708 0127 01 .byte 0x1 - 709 0128 49 .byte 0x49 - 710 0129 01 .byte 0x1 - 711 012a 01 .byte 0x1 - 712 012b 4F010000 .4byte 0x14f - 713 012f 0A .uleb128 0xa - 714 0130 23020000 .4byte .LASF25 - 715 0134 01 .byte 0x1 - 716 0135 49 .byte 0x49 - 717 0136 6F000000 .4byte 0x6f - 718 013a 0B .uleb128 0xb - 719 013b 73726300 .ascii "src\000" - 720 013f 01 .byte 0x1 - 721 0140 49 .byte 0x49 - 722 0141 4F010000 .4byte 0x14f - 723 0145 0B .uleb128 0xb - 724 0146 6E00 .ascii "n\000" - 725 0148 01 .byte 0x1 - 726 0149 49 .byte 0x49 - 727 014a 7F000000 .4byte 0x7f - 728 014e 00 .byte 0 - 729 014f 0C .uleb128 0xc - 730 0150 04 .byte 0x4 - 731 0151 55010000 .4byte 0x155 - 732 0155 0D .uleb128 0xd - 733 0156 09 .uleb128 0x9 - 734 0157 10030000 .4byte .LASF26 - 735 015b 01 .byte 0x1 - 736 015c 42 .byte 0x42 - 737 015d 01 .byte 0x1 - 738 015e 01 .byte 0x1 - 739 015f 83010000 .4byte 0x183 - 740 0163 0A .uleb128 0xa - 741 0164 23020000 .4byte .LASF25 - 742 0168 01 .byte 0x1 - 743 0169 42 .byte 0x42 - 744 016a 6F000000 .4byte 0x6f - 745 016e 0B .uleb128 0xb - 746 016f 73726300 .ascii "src\000" - 747 0173 01 .byte 0x1 - 748 0174 42 .byte 0x42 - 749 0175 4F010000 .4byte 0x14f - 750 0179 0B .uleb128 0xb - 751 017a 6E00 .ascii "n\000" - 752 017c 01 .byte 0x1 - 753 017d 42 .byte 0x42 - 754 017e 7F000000 .4byte 0x7f - 755 0182 00 .byte 0 - 756 0183 09 .uleb128 0x9 - 757 0184 AD000000 .4byte .LASF27 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 23 - - - 758 0188 01 .byte 0x1 - 759 0189 94 .byte 0x94 - 760 018a 01 .byte 0x1 - 761 018b 01 .byte 0x1 - 762 018c D1010000 .4byte 0x1d1 - 763 0190 0A .uleb128 0xa - 764 0191 53000000 .4byte .LASF28 - 765 0195 01 .byte 0x1 - 766 0196 94 .byte 0x94 - 767 0197 D1010000 .4byte 0x1d1 - 768 019b 0A .uleb128 0xa - 769 019c 31000000 .4byte .LASF29 - 770 01a0 01 .byte 0x1 - 771 01a1 94 .byte 0x94 - 772 01a2 DC010000 .4byte 0x1dc - 773 01a6 0E .uleb128 0xe - 774 01a7 6900 .ascii "i\000" - 775 01a9 01 .byte 0x1 - 776 01aa 97 .byte 0x97 - 777 01ab A0000000 .4byte 0xa0 - 778 01af 0E .uleb128 0xe - 779 01b0 6A00 .ascii "j\000" - 780 01b2 01 .byte 0x1 - 781 01b3 97 .byte 0x97 - 782 01b4 A0000000 .4byte 0xa0 - 783 01b8 0F .uleb128 0xf - 784 01b9 10 .uleb128 0x10 - 785 01ba 0D000000 .4byte .LASF30 - 786 01be 01 .byte 0x1 - 787 01bf 9A .byte 0x9a - 788 01c0 A0000000 .4byte 0xa0 - 789 01c4 10 .uleb128 0x10 - 790 01c5 00000000 .4byte .LASF31 - 791 01c9 01 .byte 0x1 - 792 01ca 9B .byte 0x9b - 793 01cb 8A000000 .4byte 0x8a - 794 01cf 00 .byte 0 - 795 01d0 00 .byte 0 - 796 01d1 0C .uleb128 0xc - 797 01d2 04 .byte 0x4 - 798 01d3 D7010000 .4byte 0x1d7 - 799 01d7 11 .uleb128 0x11 - 800 01d8 A0000000 .4byte 0xa0 - 801 01dc 0C .uleb128 0xc - 802 01dd 04 .byte 0x4 - 803 01de E2010000 .4byte 0x1e2 - 804 01e2 11 .uleb128 0x11 - 805 01e3 FE000000 .4byte 0xfe - 806 01e7 12 .uleb128 0x12 - 807 01e8 01 .byte 0x1 - 808 01e9 E4020000 .4byte .LASF38 - 809 01ed 01 .byte 0x1 - 810 01ee 0E01 .2byte 0x10e - 811 01f0 01 .byte 0x1 - 812 01f1 00000000 .4byte .LFB7 - 813 01f5 0C000000 .4byte .LFE7 - 814 01f9 02 .byte 0x2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 24 - - - 815 01fa 7D .byte 0x7d - 816 01fb 00 .sleb128 0 - 817 01fc 01 .byte 0x1 - 818 01fd 1E020000 .4byte 0x21e - 819 0201 13 .uleb128 0x13 - 820 0202 01030000 .4byte .LASF55 - 821 0206 01 .byte 0x1 - 822 0207 0E01 .2byte 0x10e - 823 0209 8A000000 .4byte 0x8a - 824 020d 01 .byte 0x1 - 825 020e 50 .byte 0x50 - 826 020f 14 .uleb128 0x14 - 827 0210 12010000 .4byte .LASF40 - 828 0214 01 .byte 0x1 - 829 0215 1001 .2byte 0x110 - 830 0217 8A000000 .4byte 0x8a - 831 021b 01 .byte 0x1 - 832 021c 52 .byte 0x52 - 833 021d 00 .byte 0 - 834 021e 09 .uleb128 0x9 - 835 021f BF000000 .4byte .LASF32 - 836 0223 01 .byte 0x1 - 837 0224 B7 .byte 0xb7 - 838 0225 01 .byte 0x1 - 839 0226 01 .byte 0x1 - 840 0227 42020000 .4byte 0x242 - 841 022b 10 .uleb128 0x10 - 842 022c 68010000 .4byte .LASF33 - 843 0230 01 .byte 0x1 - 844 0231 B9 .byte 0xb9 - 845 0232 A0000000 .4byte 0xa0 - 846 0236 10 .uleb128 0x10 - 847 0237 B3020000 .4byte .LASF34 - 848 023b 01 .byte 0x1 - 849 023c BA .byte 0xba - 850 023d 8A000000 .4byte 0x8a - 851 0241 00 .byte 0 - 852 0242 09 .uleb128 0x9 - 853 0243 01010000 .4byte .LASF35 - 854 0247 01 .byte 0x1 - 855 0248 3B .byte 0x3b - 856 0249 01 .byte 0x1 - 857 024a 01 .byte 0x1 - 858 024b 62020000 .4byte 0x262 - 859 024f 0B .uleb128 0xb - 860 0250 7300 .ascii "s\000" - 861 0252 01 .byte 0x1 - 862 0253 3B .byte 0x3b - 863 0254 6F000000 .4byte 0x6f - 864 0258 0B .uleb128 0xb - 865 0259 6E00 .ascii "n\000" - 866 025b 01 .byte 0x1 - 867 025c 3B .byte 0x3b - 868 025d 7F000000 .4byte 0x7f - 869 0261 00 .byte 0 - 870 0262 09 .uleb128 0x9 - 871 0263 70000000 .4byte .LASF36 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 25 - - - 872 0267 01 .byte 0x1 - 873 0268 F4 .byte 0xf4 - 874 0269 01 .byte 0x1 - 875 026a 01 .byte 0x1 - 876 026b 7B020000 .4byte 0x27b - 877 026f 10 .uleb128 0x10 - 878 0270 E3010000 .4byte .LASF37 - 879 0274 01 .byte 0x1 - 880 0275 F6 .byte 0xf6 - 881 0276 8A000000 .4byte 0x8a - 882 027a 00 .byte 0 - 883 027b 15 .uleb128 0x15 - 884 027c 01 .byte 0x1 - 885 027d 24030000 .4byte .LASF39 - 886 0281 01 .byte 0x1 - 887 0282 3001 .2byte 0x130 - 888 0284 01 .byte 0x1 - 889 0285 00000000 .4byte .LFB8 - 890 0289 D8010000 .4byte .LFE8 - 891 028d 00000000 .4byte .LLST0 - 892 0291 01 .byte 0x1 - 893 0292 B4040000 .4byte 0x4b4 - 894 0296 14 .uleb128 0x14 - 895 0297 A2020000 .4byte .LASF41 - 896 029b 01 .byte 0x1 - 897 029c 3301 .2byte 0x133 - 898 029e C4040000 .4byte 0x4c4 - 899 02a2 05 .byte 0x5 - 900 02a3 03 .byte 0x3 - 901 02a4 8E000000 .4byte BS_IOPINS0_0_VAL.4808 - 902 02a8 14 .uleb128 0x14 - 903 02a9 BB020000 .4byte .LASF42 - 904 02ad 01 .byte 0x1 - 905 02ae 3701 .2byte 0x137 - 906 02b0 D9040000 .4byte 0x4d9 - 907 02b4 05 .byte 0x5 - 908 02b5 03 .byte 0x3 - 909 02b6 96000000 .4byte BS_IOPINS0_8_VAL.4809 - 910 02ba 14 .uleb128 0x14 - 911 02bb 12020000 .4byte .LASF43 - 912 02bf 01 .byte 0x1 - 913 02c0 3B01 .2byte 0x13b - 914 02c2 DE040000 .4byte 0x4de - 915 02c6 05 .byte 0x5 - 916 02c7 03 .byte 0x3 - 917 02c8 A0000000 .4byte BS_IOPINS0_3_VAL.4810 - 918 02cc 14 .uleb128 0x14 - 919 02cd D4000000 .4byte .LASF44 - 920 02d1 01 .byte 0x1 - 921 02d2 3F01 .2byte 0x13f - 922 02d4 E3040000 .4byte 0x4e3 - 923 02d8 05 .byte 0x5 - 924 02d9 03 .byte 0x3 - 925 02da A8000000 .4byte BS_IOPINS0_4_VAL.4811 - 926 02de 14 .uleb128 0x14 - 927 02df 88010000 .4byte .LASF45 - 928 02e3 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 26 - - - 929 02e4 4301 .2byte 0x143 - 930 02e6 E8040000 .4byte 0x4e8 - 931 02ea 05 .byte 0x5 - 932 02eb 03 .byte 0x3 - 933 02ec B0000000 .4byte BS_IOPINS0_6_VAL.4812 - 934 02f0 16 .uleb128 0x16 - 935 02f1 1E020000 .4byte 0x21e - 936 02f5 08000000 .4byte .LBB32 - 937 02f9 00000000 .4byte .Ldebug_ranges0+0 - 938 02fd 01 .byte 0x1 - 939 02fe 4F01 .2byte 0x14f - 940 0300 2A030000 .4byte 0x32a - 941 0304 17 .uleb128 0x17 - 942 0305 20000000 .4byte .Ldebug_ranges0+0x20 - 943 0309 18 .uleb128 0x18 - 944 030a 2B020000 .4byte 0x22b - 945 030e 19 .uleb128 0x19 - 946 030f 36020000 .4byte 0x236 - 947 0313 20000000 .4byte .LLST1 - 948 0317 1A .uleb128 0x1a - 949 0318 4A000000 .4byte .LVL3 - 950 031c 17050000 .4byte 0x517 - 951 0320 1B .uleb128 0x1b - 952 0321 01 .byte 0x1 - 953 0322 50 .byte 0x50 - 954 0323 03 .byte 0x3 - 955 0324 0A .byte 0xa - 956 0325 E001 .2byte 0x1e0 - 957 0327 00 .byte 0 - 958 0328 00 .byte 0 - 959 0329 00 .byte 0 - 960 032a 1C .uleb128 0x1c - 961 032b 40000000 .4byte .Ldebug_ranges0+0x40 - 962 032f 62040000 .4byte 0x462 - 963 0333 14 .uleb128 0x14 - 964 0334 9B000000 .4byte .LASF46 - 965 0338 01 .byte 0x1 - 966 0339 5401 .2byte 0x154 - 967 033b FD040000 .4byte 0x4fd - 968 033f 05 .byte 0x5 - 969 0340 03 .byte 0x3 - 970 0341 30000000 .4byte cy_cfg_addr_table.4813 - 971 0345 14 .uleb128 0x14 - 972 0346 5E000000 .4byte .LASF47 - 973 034a 01 .byte 0x1 - 974 034b 6301 .2byte 0x163 - 975 034d 12050000 .4byte 0x512 - 976 0351 05 .byte 0x5 - 977 0352 03 .byte 0x3 - 978 0353 60000000 .4byte cy_cfg_data_table.4814 - 979 0357 1D .uleb128 0x1d - 980 0358 06 .byte 0x6 - 981 0359 01 .byte 0x1 - 982 035a 7F01 .2byte 0x17f - 983 035c 7F030000 .4byte 0x37f - 984 0360 1E .uleb128 0x1e - 985 0361 1C030000 .4byte .LASF48 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 27 - - - 986 0365 01 .byte 0x1 - 987 0366 8001 .2byte 0x180 - 988 0368 6F000000 .4byte 0x6f - 989 036c 02 .byte 0x2 - 990 036d 23 .byte 0x23 - 991 036e 00 .uleb128 0 - 992 036f 1E .uleb128 0x1e - 993 0370 70010000 .4byte .LASF49 - 994 0374 01 .byte 0x1 - 995 0375 8101 .2byte 0x181 - 996 0377 95000000 .4byte 0x95 - 997 037b 02 .byte 0x2 - 998 037c 23 .byte 0x23 - 999 037d 04 .uleb128 0x4 - 1000 037e 00 .byte 0 - 1001 037f 1F .uleb128 0x1f - 1002 0380 F5010000 .4byte .LASF50 - 1003 0384 01 .byte 0x1 - 1004 0385 8201 .2byte 0x182 - 1005 0387 57030000 .4byte 0x357 - 1006 038b 20 .uleb128 0x20 - 1007 038c 7F030000 .4byte 0x37f - 1008 0390 9B030000 .4byte 0x39b - 1009 0394 21 .uleb128 0x21 - 1010 0395 68000000 .4byte 0x68 - 1011 0399 07 .byte 0x7 - 1012 039a 00 .byte 0 - 1013 039b 14 .uleb128 0x14 - 1014 039c 02020000 .4byte .LASF51 - 1015 03a0 01 .byte 0x1 - 1016 03a1 8401 .2byte 0x184 - 1017 03a3 AD030000 .4byte 0x3ad - 1018 03a7 05 .byte 0x5 - 1019 03a8 03 .byte 0x3 - 1020 03a9 00000000 .4byte cfg_memset_list.4819 - 1021 03ad 11 .uleb128 0x11 - 1022 03ae 8B030000 .4byte 0x38b - 1023 03b2 22 .uleb128 0x22 - 1024 03b3 6900 .ascii "i\000" - 1025 03b5 01 .byte 0x1 - 1026 03b6 9001 .2byte 0x190 - 1027 03b8 8A000000 .4byte 0x8a - 1028 03bc 3E000000 .4byte .LLST2 - 1029 03c0 23 .uleb128 0x23 - 1030 03c1 84000000 .4byte .LBB39 - 1031 03c5 98000000 .4byte .LBE39 - 1032 03c9 1A040000 .4byte 0x41a - 1033 03cd 22 .uleb128 0x22 - 1034 03ce 6D7300 .ascii "ms\000" - 1035 03d1 01 .byte 0x1 - 1036 03d2 9501 .2byte 0x195 - 1037 03d4 DC030000 .4byte 0x3dc - 1038 03d8 52000000 .4byte .LLST3 - 1039 03dc 0C .uleb128 0xc - 1040 03dd 04 .byte 0x4 - 1041 03de E2030000 .4byte 0x3e2 - 1042 03e2 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 28 - - - 1043 03e3 7F030000 .4byte 0x37f - 1044 03e7 24 .uleb128 0x24 - 1045 03e8 42020000 .4byte 0x242 - 1046 03ec 8C000000 .4byte .LBB40 - 1047 03f0 98000000 .4byte .LBE40 - 1048 03f4 01 .byte 0x1 - 1049 03f5 9601 .2byte 0x196 - 1050 03f7 25 .uleb128 0x25 - 1051 03f8 58020000 .4byte 0x258 - 1052 03fc 77000000 .4byte .LLST4 - 1053 0400 25 .uleb128 0x25 - 1054 0401 4F020000 .4byte 0x24f - 1055 0405 AC000000 .4byte .LLST5 - 1056 0409 1A .uleb128 0x1a - 1057 040a 98000000 .4byte .LVL12 - 1058 040e 2B050000 .4byte 0x52b - 1059 0412 1B .uleb128 0x1b - 1060 0413 01 .byte 0x1 - 1061 0414 51 .byte 0x51 - 1062 0415 01 .byte 0x1 - 1063 0416 30 .byte 0x30 - 1064 0417 00 .byte 0 - 1065 0418 00 .byte 0 - 1066 0419 00 .byte 0 - 1067 041a 26 .uleb128 0x26 - 1068 041b 83010000 .4byte 0x183 - 1069 041f A0000000 .4byte .LBB42 - 1070 0423 58000000 .4byte .Ldebug_ranges0+0x58 - 1071 0427 01 .byte 0x1 - 1072 0428 9901 .2byte 0x199 - 1073 042a 17 .uleb128 0x17 - 1074 042b 70000000 .4byte .Ldebug_ranges0+0x70 - 1075 042f 18 .uleb128 0x18 - 1076 0430 A6010000 .4byte 0x1a6 - 1077 0434 19 .uleb128 0x19 - 1078 0435 AF010000 .4byte 0x1af - 1079 0439 DC000000 .4byte .LLST6 - 1080 043d 27 .uleb128 0x27 - 1081 043e 9B010000 .4byte 0x19b - 1082 0442 27 .uleb128 0x27 - 1083 0443 90010000 .4byte 0x190 - 1084 0447 17 .uleb128 0x17 - 1085 0448 88000000 .4byte .Ldebug_ranges0+0x88 - 1086 044c 19 .uleb128 0x19 - 1087 044d B9010000 .4byte 0x1b9 - 1088 0451 EF000000 .4byte .LLST7 - 1089 0455 19 .uleb128 0x19 - 1090 0456 C4010000 .4byte 0x1c4 - 1091 045a 0D010000 .4byte .LLST8 - 1092 045e 00 .byte 0 - 1093 045f 00 .byte 0 - 1094 0460 00 .byte 0 - 1095 0461 00 .byte 0 - 1096 0462 28 .uleb128 0x28 - 1097 0463 62020000 .4byte 0x262 - 1098 0467 50010000 .4byte .LBB49 - 1099 046b 66010000 .4byte .LBE49 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 29 - - - 1100 046f 01 .byte 0x1 - 1101 0470 AF01 .2byte 0x1af - 1102 0472 8A040000 .4byte 0x48a - 1103 0476 29 .uleb128 0x29 - 1104 0477 50010000 .4byte .LBB50 - 1105 047b 66010000 .4byte .LBE50 - 1106 047f 19 .uleb128 0x19 - 1107 0480 6F020000 .4byte 0x26f - 1108 0484 20010000 .4byte .LLST9 - 1109 0488 00 .byte 0 - 1110 0489 00 .byte 0 - 1111 048a 24 .uleb128 0x24 - 1112 048b 56010000 .4byte 0x156 - 1113 048f 66010000 .4byte .LBB51 - 1114 0493 D8010000 .4byte .LBE51 - 1115 0497 01 .byte 0x1 - 1116 0498 B201 .2byte 0x1b2 - 1117 049a 2A .uleb128 0x2a - 1118 049b 79010000 .4byte 0x179 - 1119 049f 0E .byte 0xe - 1120 04a0 2B .uleb128 0x2b - 1121 04a1 6E010000 .4byte 0x16e - 1122 04a5 A0430040 .4byte 0x400043a0 - 1123 04a9 2B .uleb128 0x2b - 1124 04aa 63010000 .4byte 0x163 - 1125 04ae B0430040 .4byte 0x400043b0 - 1126 04b2 00 .byte 0 - 1127 04b3 00 .byte 0 - 1128 04b4 20 .uleb128 0x20 - 1129 04b5 8A000000 .4byte 0x8a - 1130 04b9 C4040000 .4byte 0x4c4 - 1131 04bd 21 .uleb128 0x21 - 1132 04be 68000000 .4byte 0x68 - 1133 04c2 07 .byte 0x7 - 1134 04c3 00 .byte 0 - 1135 04c4 11 .uleb128 0x11 - 1136 04c5 B4040000 .4byte 0x4b4 - 1137 04c9 20 .uleb128 0x20 - 1138 04ca 8A000000 .4byte 0x8a - 1139 04ce D9040000 .4byte 0x4d9 - 1140 04d2 21 .uleb128 0x21 - 1141 04d3 68000000 .4byte 0x68 - 1142 04d7 09 .byte 0x9 - 1143 04d8 00 .byte 0 - 1144 04d9 11 .uleb128 0x11 - 1145 04da C9040000 .4byte 0x4c9 - 1146 04de 11 .uleb128 0x11 - 1147 04df B4040000 .4byte 0x4b4 - 1148 04e3 11 .uleb128 0x11 - 1149 04e4 B4040000 .4byte 0x4b4 - 1150 04e8 11 .uleb128 0x11 - 1151 04e9 B4040000 .4byte 0x4b4 - 1152 04ed 20 .uleb128 0x20 - 1153 04ee A0000000 .4byte 0xa0 - 1154 04f2 FD040000 .4byte 0x4fd - 1155 04f6 21 .uleb128 0x21 - 1156 04f7 68000000 .4byte 0x68 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 30 - - - 1157 04fb 0B .byte 0xb - 1158 04fc 00 .byte 0 - 1159 04fd 11 .uleb128 0x11 - 1160 04fe ED040000 .4byte 0x4ed - 1161 0502 20 .uleb128 0x20 - 1162 0503 FE000000 .4byte 0xfe - 1163 0507 12050000 .4byte 0x512 - 1164 050b 21 .uleb128 0x21 - 1165 050c 68000000 .4byte 0x68 - 1166 0510 16 .byte 0x16 - 1167 0511 00 .byte 0 - 1168 0512 11 .uleb128 0x11 - 1169 0513 02050000 .4byte 0x502 - 1170 0517 2C .uleb128 0x2c - 1171 0518 01 .byte 0x1 - 1172 0519 2E020000 .4byte .LASF56 - 1173 051d 04 .byte 0x4 - 1174 051e 7A .byte 0x7a - 1175 051f 01 .byte 0x1 - 1176 0520 01 .byte 0x1 - 1177 0521 2B050000 .4byte 0x52b - 1178 0525 2D .uleb128 0x2d - 1179 0526 A0000000 .4byte 0xa0 - 1180 052a 00 .byte 0 - 1181 052b 2E .uleb128 0x2e - 1182 052c 01 .byte 0x1 - 1183 052d 09030000 .4byte .LASF57 - 1184 0531 01 .byte 0x1 - 1185 0532 6F000000 .4byte 0x6f - 1186 0536 01 .byte 0x1 - 1187 0537 01 .byte 0x1 - 1188 0538 2D .uleb128 0x2d - 1189 0539 6F000000 .4byte 0x6f - 1190 053d 2D .uleb128 0x2d - 1191 053e 45000000 .4byte 0x45 - 1192 0542 2D .uleb128 0x2d - 1193 0543 68000000 .4byte 0x68 - 1194 0547 00 .byte 0 - 1195 0548 00 .byte 0 - 1196 .section .debug_abbrev,"",%progbits - 1197 .Ldebug_abbrev0: - 1198 0000 01 .uleb128 0x1 - 1199 0001 11 .uleb128 0x11 - 1200 0002 01 .byte 0x1 - 1201 0003 25 .uleb128 0x25 - 1202 0004 0E .uleb128 0xe - 1203 0005 13 .uleb128 0x13 - 1204 0006 0B .uleb128 0xb - 1205 0007 03 .uleb128 0x3 - 1206 0008 0E .uleb128 0xe - 1207 0009 1B .uleb128 0x1b - 1208 000a 0E .uleb128 0xe - 1209 000b 55 .uleb128 0x55 - 1210 000c 06 .uleb128 0x6 - 1211 000d 11 .uleb128 0x11 - 1212 000e 01 .uleb128 0x1 - 1213 000f 52 .uleb128 0x52 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 31 - - - 1214 0010 01 .uleb128 0x1 - 1215 0011 10 .uleb128 0x10 - 1216 0012 06 .uleb128 0x6 - 1217 0013 00 .byte 0 - 1218 0014 00 .byte 0 - 1219 0015 02 .uleb128 0x2 - 1220 0016 24 .uleb128 0x24 - 1221 0017 00 .byte 0 - 1222 0018 0B .uleb128 0xb - 1223 0019 0B .uleb128 0xb - 1224 001a 3E .uleb128 0x3e - 1225 001b 0B .uleb128 0xb - 1226 001c 03 .uleb128 0x3 - 1227 001d 0E .uleb128 0xe - 1228 001e 00 .byte 0 - 1229 001f 00 .byte 0 - 1230 0020 03 .uleb128 0x3 - 1231 0021 24 .uleb128 0x24 - 1232 0022 00 .byte 0 - 1233 0023 0B .uleb128 0xb - 1234 0024 0B .uleb128 0xb - 1235 0025 3E .uleb128 0x3e - 1236 0026 0B .uleb128 0xb - 1237 0027 03 .uleb128 0x3 - 1238 0028 08 .uleb128 0x8 - 1239 0029 00 .byte 0 - 1240 002a 00 .byte 0 - 1241 002b 04 .uleb128 0x4 - 1242 002c 0F .uleb128 0xf - 1243 002d 00 .byte 0 - 1244 002e 0B .uleb128 0xb - 1245 002f 0B .uleb128 0xb - 1246 0030 00 .byte 0 - 1247 0031 00 .byte 0 - 1248 0032 05 .uleb128 0x5 - 1249 0033 16 .uleb128 0x16 - 1250 0034 00 .byte 0 - 1251 0035 03 .uleb128 0x3 - 1252 0036 0E .uleb128 0xe - 1253 0037 3A .uleb128 0x3a - 1254 0038 0B .uleb128 0xb - 1255 0039 3B .uleb128 0x3b - 1256 003a 0B .uleb128 0xb - 1257 003b 49 .uleb128 0x49 - 1258 003c 13 .uleb128 0x13 - 1259 003d 00 .byte 0 - 1260 003e 00 .byte 0 - 1261 003f 06 .uleb128 0x6 - 1262 0040 35 .uleb128 0x35 - 1263 0041 00 .byte 0 - 1264 0042 49 .uleb128 0x49 - 1265 0043 13 .uleb128 0x13 - 1266 0044 00 .byte 0 - 1267 0045 00 .byte 0 - 1268 0046 07 .uleb128 0x7 - 1269 0047 13 .uleb128 0x13 - 1270 0048 01 .byte 0x1 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 32 - - - 1271 0049 0B .uleb128 0xb - 1272 004a 0B .uleb128 0xb - 1273 004b 3A .uleb128 0x3a - 1274 004c 0B .uleb128 0xb - 1275 004d 3B .uleb128 0x3b - 1276 004e 0B .uleb128 0xb - 1277 004f 01 .uleb128 0x1 - 1278 0050 13 .uleb128 0x13 - 1279 0051 00 .byte 0 - 1280 0052 00 .byte 0 - 1281 0053 08 .uleb128 0x8 - 1282 0054 0D .uleb128 0xd - 1283 0055 00 .byte 0 - 1284 0056 03 .uleb128 0x3 - 1285 0057 0E .uleb128 0xe - 1286 0058 3A .uleb128 0x3a - 1287 0059 0B .uleb128 0xb - 1288 005a 3B .uleb128 0x3b - 1289 005b 0B .uleb128 0xb - 1290 005c 49 .uleb128 0x49 - 1291 005d 13 .uleb128 0x13 - 1292 005e 38 .uleb128 0x38 - 1293 005f 0A .uleb128 0xa - 1294 0060 00 .byte 0 - 1295 0061 00 .byte 0 - 1296 0062 09 .uleb128 0x9 - 1297 0063 2E .uleb128 0x2e - 1298 0064 01 .byte 0x1 - 1299 0065 03 .uleb128 0x3 - 1300 0066 0E .uleb128 0xe - 1301 0067 3A .uleb128 0x3a - 1302 0068 0B .uleb128 0xb - 1303 0069 3B .uleb128 0x3b - 1304 006a 0B .uleb128 0xb - 1305 006b 27 .uleb128 0x27 - 1306 006c 0C .uleb128 0xc - 1307 006d 20 .uleb128 0x20 - 1308 006e 0B .uleb128 0xb - 1309 006f 01 .uleb128 0x1 - 1310 0070 13 .uleb128 0x13 - 1311 0071 00 .byte 0 - 1312 0072 00 .byte 0 - 1313 0073 0A .uleb128 0xa - 1314 0074 05 .uleb128 0x5 - 1315 0075 00 .byte 0 - 1316 0076 03 .uleb128 0x3 - 1317 0077 0E .uleb128 0xe - 1318 0078 3A .uleb128 0x3a - 1319 0079 0B .uleb128 0xb - 1320 007a 3B .uleb128 0x3b - 1321 007b 0B .uleb128 0xb - 1322 007c 49 .uleb128 0x49 - 1323 007d 13 .uleb128 0x13 - 1324 007e 00 .byte 0 - 1325 007f 00 .byte 0 - 1326 0080 0B .uleb128 0xb - 1327 0081 05 .uleb128 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 33 - - - 1328 0082 00 .byte 0 - 1329 0083 03 .uleb128 0x3 - 1330 0084 08 .uleb128 0x8 - 1331 0085 3A .uleb128 0x3a - 1332 0086 0B .uleb128 0xb - 1333 0087 3B .uleb128 0x3b - 1334 0088 0B .uleb128 0xb - 1335 0089 49 .uleb128 0x49 - 1336 008a 13 .uleb128 0x13 - 1337 008b 00 .byte 0 - 1338 008c 00 .byte 0 - 1339 008d 0C .uleb128 0xc - 1340 008e 0F .uleb128 0xf - 1341 008f 00 .byte 0 - 1342 0090 0B .uleb128 0xb - 1343 0091 0B .uleb128 0xb - 1344 0092 49 .uleb128 0x49 - 1345 0093 13 .uleb128 0x13 - 1346 0094 00 .byte 0 - 1347 0095 00 .byte 0 - 1348 0096 0D .uleb128 0xd - 1349 0097 26 .uleb128 0x26 - 1350 0098 00 .byte 0 - 1351 0099 00 .byte 0 - 1352 009a 00 .byte 0 - 1353 009b 0E .uleb128 0xe - 1354 009c 34 .uleb128 0x34 - 1355 009d 00 .byte 0 - 1356 009e 03 .uleb128 0x3 - 1357 009f 08 .uleb128 0x8 - 1358 00a0 3A .uleb128 0x3a - 1359 00a1 0B .uleb128 0xb - 1360 00a2 3B .uleb128 0x3b - 1361 00a3 0B .uleb128 0xb - 1362 00a4 49 .uleb128 0x49 - 1363 00a5 13 .uleb128 0x13 - 1364 00a6 00 .byte 0 - 1365 00a7 00 .byte 0 - 1366 00a8 0F .uleb128 0xf - 1367 00a9 0B .uleb128 0xb - 1368 00aa 01 .byte 0x1 - 1369 00ab 00 .byte 0 - 1370 00ac 00 .byte 0 - 1371 00ad 10 .uleb128 0x10 - 1372 00ae 34 .uleb128 0x34 - 1373 00af 00 .byte 0 - 1374 00b0 03 .uleb128 0x3 - 1375 00b1 0E .uleb128 0xe - 1376 00b2 3A .uleb128 0x3a - 1377 00b3 0B .uleb128 0xb - 1378 00b4 3B .uleb128 0x3b - 1379 00b5 0B .uleb128 0xb - 1380 00b6 49 .uleb128 0x49 - 1381 00b7 13 .uleb128 0x13 - 1382 00b8 00 .byte 0 - 1383 00b9 00 .byte 0 - 1384 00ba 11 .uleb128 0x11 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 34 - - - 1385 00bb 26 .uleb128 0x26 - 1386 00bc 00 .byte 0 - 1387 00bd 49 .uleb128 0x49 - 1388 00be 13 .uleb128 0x13 - 1389 00bf 00 .byte 0 - 1390 00c0 00 .byte 0 - 1391 00c1 12 .uleb128 0x12 - 1392 00c2 2E .uleb128 0x2e - 1393 00c3 01 .byte 0x1 - 1394 00c4 3F .uleb128 0x3f - 1395 00c5 0C .uleb128 0xc - 1396 00c6 03 .uleb128 0x3 - 1397 00c7 0E .uleb128 0xe - 1398 00c8 3A .uleb128 0x3a - 1399 00c9 0B .uleb128 0xb - 1400 00ca 3B .uleb128 0x3b - 1401 00cb 05 .uleb128 0x5 - 1402 00cc 27 .uleb128 0x27 - 1403 00cd 0C .uleb128 0xc - 1404 00ce 11 .uleb128 0x11 - 1405 00cf 01 .uleb128 0x1 - 1406 00d0 12 .uleb128 0x12 - 1407 00d1 01 .uleb128 0x1 - 1408 00d2 40 .uleb128 0x40 - 1409 00d3 0A .uleb128 0xa - 1410 00d4 9742 .uleb128 0x2117 - 1411 00d6 0C .uleb128 0xc - 1412 00d7 01 .uleb128 0x1 - 1413 00d8 13 .uleb128 0x13 - 1414 00d9 00 .byte 0 - 1415 00da 00 .byte 0 - 1416 00db 13 .uleb128 0x13 - 1417 00dc 05 .uleb128 0x5 - 1418 00dd 00 .byte 0 - 1419 00de 03 .uleb128 0x3 - 1420 00df 0E .uleb128 0xe - 1421 00e0 3A .uleb128 0x3a - 1422 00e1 0B .uleb128 0xb - 1423 00e2 3B .uleb128 0x3b - 1424 00e3 05 .uleb128 0x5 - 1425 00e4 49 .uleb128 0x49 - 1426 00e5 13 .uleb128 0x13 - 1427 00e6 02 .uleb128 0x2 - 1428 00e7 0A .uleb128 0xa - 1429 00e8 00 .byte 0 - 1430 00e9 00 .byte 0 - 1431 00ea 14 .uleb128 0x14 - 1432 00eb 34 .uleb128 0x34 - 1433 00ec 00 .byte 0 - 1434 00ed 03 .uleb128 0x3 - 1435 00ee 0E .uleb128 0xe - 1436 00ef 3A .uleb128 0x3a - 1437 00f0 0B .uleb128 0xb - 1438 00f1 3B .uleb128 0x3b - 1439 00f2 05 .uleb128 0x5 - 1440 00f3 49 .uleb128 0x49 - 1441 00f4 13 .uleb128 0x13 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 35 - - - 1442 00f5 02 .uleb128 0x2 - 1443 00f6 0A .uleb128 0xa - 1444 00f7 00 .byte 0 - 1445 00f8 00 .byte 0 - 1446 00f9 15 .uleb128 0x15 - 1447 00fa 2E .uleb128 0x2e - 1448 00fb 01 .byte 0x1 - 1449 00fc 3F .uleb128 0x3f - 1450 00fd 0C .uleb128 0xc - 1451 00fe 03 .uleb128 0x3 - 1452 00ff 0E .uleb128 0xe - 1453 0100 3A .uleb128 0x3a - 1454 0101 0B .uleb128 0xb - 1455 0102 3B .uleb128 0x3b - 1456 0103 05 .uleb128 0x5 - 1457 0104 27 .uleb128 0x27 - 1458 0105 0C .uleb128 0xc - 1459 0106 11 .uleb128 0x11 - 1460 0107 01 .uleb128 0x1 - 1461 0108 12 .uleb128 0x12 - 1462 0109 01 .uleb128 0x1 - 1463 010a 40 .uleb128 0x40 - 1464 010b 06 .uleb128 0x6 - 1465 010c 9742 .uleb128 0x2117 - 1466 010e 0C .uleb128 0xc - 1467 010f 01 .uleb128 0x1 - 1468 0110 13 .uleb128 0x13 - 1469 0111 00 .byte 0 - 1470 0112 00 .byte 0 - 1471 0113 16 .uleb128 0x16 - 1472 0114 1D .uleb128 0x1d - 1473 0115 01 .byte 0x1 - 1474 0116 31 .uleb128 0x31 - 1475 0117 13 .uleb128 0x13 - 1476 0118 52 .uleb128 0x52 - 1477 0119 01 .uleb128 0x1 - 1478 011a 55 .uleb128 0x55 - 1479 011b 06 .uleb128 0x6 - 1480 011c 58 .uleb128 0x58 - 1481 011d 0B .uleb128 0xb - 1482 011e 59 .uleb128 0x59 - 1483 011f 05 .uleb128 0x5 - 1484 0120 01 .uleb128 0x1 - 1485 0121 13 .uleb128 0x13 - 1486 0122 00 .byte 0 - 1487 0123 00 .byte 0 - 1488 0124 17 .uleb128 0x17 - 1489 0125 0B .uleb128 0xb - 1490 0126 01 .byte 0x1 - 1491 0127 55 .uleb128 0x55 - 1492 0128 06 .uleb128 0x6 - 1493 0129 00 .byte 0 - 1494 012a 00 .byte 0 - 1495 012b 18 .uleb128 0x18 - 1496 012c 34 .uleb128 0x34 - 1497 012d 00 .byte 0 - 1498 012e 31 .uleb128 0x31 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 36 - - - 1499 012f 13 .uleb128 0x13 - 1500 0130 00 .byte 0 - 1501 0131 00 .byte 0 - 1502 0132 19 .uleb128 0x19 - 1503 0133 34 .uleb128 0x34 - 1504 0134 00 .byte 0 - 1505 0135 31 .uleb128 0x31 - 1506 0136 13 .uleb128 0x13 - 1507 0137 02 .uleb128 0x2 - 1508 0138 06 .uleb128 0x6 - 1509 0139 00 .byte 0 - 1510 013a 00 .byte 0 - 1511 013b 1A .uleb128 0x1a - 1512 013c 898201 .uleb128 0x4109 - 1513 013f 01 .byte 0x1 - 1514 0140 11 .uleb128 0x11 - 1515 0141 01 .uleb128 0x1 - 1516 0142 31 .uleb128 0x31 - 1517 0143 13 .uleb128 0x13 - 1518 0144 00 .byte 0 - 1519 0145 00 .byte 0 - 1520 0146 1B .uleb128 0x1b - 1521 0147 8A8201 .uleb128 0x410a - 1522 014a 00 .byte 0 - 1523 014b 02 .uleb128 0x2 - 1524 014c 0A .uleb128 0xa - 1525 014d 9142 .uleb128 0x2111 - 1526 014f 0A .uleb128 0xa - 1527 0150 00 .byte 0 - 1528 0151 00 .byte 0 - 1529 0152 1C .uleb128 0x1c - 1530 0153 0B .uleb128 0xb - 1531 0154 01 .byte 0x1 - 1532 0155 55 .uleb128 0x55 - 1533 0156 06 .uleb128 0x6 - 1534 0157 01 .uleb128 0x1 - 1535 0158 13 .uleb128 0x13 - 1536 0159 00 .byte 0 - 1537 015a 00 .byte 0 - 1538 015b 1D .uleb128 0x1d - 1539 015c 13 .uleb128 0x13 - 1540 015d 01 .byte 0x1 - 1541 015e 0B .uleb128 0xb - 1542 015f 0B .uleb128 0xb - 1543 0160 3A .uleb128 0x3a - 1544 0161 0B .uleb128 0xb - 1545 0162 3B .uleb128 0x3b - 1546 0163 05 .uleb128 0x5 - 1547 0164 01 .uleb128 0x1 - 1548 0165 13 .uleb128 0x13 - 1549 0166 00 .byte 0 - 1550 0167 00 .byte 0 - 1551 0168 1E .uleb128 0x1e - 1552 0169 0D .uleb128 0xd - 1553 016a 00 .byte 0 - 1554 016b 03 .uleb128 0x3 - 1555 016c 0E .uleb128 0xe - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 37 - - - 1556 016d 3A .uleb128 0x3a - 1557 016e 0B .uleb128 0xb - 1558 016f 3B .uleb128 0x3b - 1559 0170 05 .uleb128 0x5 - 1560 0171 49 .uleb128 0x49 - 1561 0172 13 .uleb128 0x13 - 1562 0173 38 .uleb128 0x38 - 1563 0174 0A .uleb128 0xa - 1564 0175 00 .byte 0 - 1565 0176 00 .byte 0 - 1566 0177 1F .uleb128 0x1f - 1567 0178 16 .uleb128 0x16 - 1568 0179 00 .byte 0 - 1569 017a 03 .uleb128 0x3 - 1570 017b 0E .uleb128 0xe - 1571 017c 3A .uleb128 0x3a - 1572 017d 0B .uleb128 0xb - 1573 017e 3B .uleb128 0x3b - 1574 017f 05 .uleb128 0x5 - 1575 0180 49 .uleb128 0x49 - 1576 0181 13 .uleb128 0x13 - 1577 0182 00 .byte 0 - 1578 0183 00 .byte 0 - 1579 0184 20 .uleb128 0x20 - 1580 0185 01 .uleb128 0x1 - 1581 0186 01 .byte 0x1 - 1582 0187 49 .uleb128 0x49 - 1583 0188 13 .uleb128 0x13 - 1584 0189 01 .uleb128 0x1 - 1585 018a 13 .uleb128 0x13 - 1586 018b 00 .byte 0 - 1587 018c 00 .byte 0 - 1588 018d 21 .uleb128 0x21 - 1589 018e 21 .uleb128 0x21 - 1590 018f 00 .byte 0 - 1591 0190 49 .uleb128 0x49 - 1592 0191 13 .uleb128 0x13 - 1593 0192 2F .uleb128 0x2f - 1594 0193 0B .uleb128 0xb - 1595 0194 00 .byte 0 - 1596 0195 00 .byte 0 - 1597 0196 22 .uleb128 0x22 - 1598 0197 34 .uleb128 0x34 - 1599 0198 00 .byte 0 - 1600 0199 03 .uleb128 0x3 - 1601 019a 08 .uleb128 0x8 - 1602 019b 3A .uleb128 0x3a - 1603 019c 0B .uleb128 0xb - 1604 019d 3B .uleb128 0x3b - 1605 019e 05 .uleb128 0x5 - 1606 019f 49 .uleb128 0x49 - 1607 01a0 13 .uleb128 0x13 - 1608 01a1 02 .uleb128 0x2 - 1609 01a2 06 .uleb128 0x6 - 1610 01a3 00 .byte 0 - 1611 01a4 00 .byte 0 - 1612 01a5 23 .uleb128 0x23 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 38 - - - 1613 01a6 0B .uleb128 0xb - 1614 01a7 01 .byte 0x1 - 1615 01a8 11 .uleb128 0x11 - 1616 01a9 01 .uleb128 0x1 - 1617 01aa 12 .uleb128 0x12 - 1618 01ab 01 .uleb128 0x1 - 1619 01ac 01 .uleb128 0x1 - 1620 01ad 13 .uleb128 0x13 - 1621 01ae 00 .byte 0 - 1622 01af 00 .byte 0 - 1623 01b0 24 .uleb128 0x24 - 1624 01b1 1D .uleb128 0x1d - 1625 01b2 01 .byte 0x1 - 1626 01b3 31 .uleb128 0x31 - 1627 01b4 13 .uleb128 0x13 - 1628 01b5 11 .uleb128 0x11 - 1629 01b6 01 .uleb128 0x1 - 1630 01b7 12 .uleb128 0x12 - 1631 01b8 01 .uleb128 0x1 - 1632 01b9 58 .uleb128 0x58 - 1633 01ba 0B .uleb128 0xb - 1634 01bb 59 .uleb128 0x59 - 1635 01bc 05 .uleb128 0x5 - 1636 01bd 00 .byte 0 - 1637 01be 00 .byte 0 - 1638 01bf 25 .uleb128 0x25 - 1639 01c0 05 .uleb128 0x5 - 1640 01c1 00 .byte 0 - 1641 01c2 31 .uleb128 0x31 - 1642 01c3 13 .uleb128 0x13 - 1643 01c4 02 .uleb128 0x2 - 1644 01c5 06 .uleb128 0x6 - 1645 01c6 00 .byte 0 - 1646 01c7 00 .byte 0 - 1647 01c8 26 .uleb128 0x26 - 1648 01c9 1D .uleb128 0x1d - 1649 01ca 01 .byte 0x1 - 1650 01cb 31 .uleb128 0x31 - 1651 01cc 13 .uleb128 0x13 - 1652 01cd 52 .uleb128 0x52 - 1653 01ce 01 .uleb128 0x1 - 1654 01cf 55 .uleb128 0x55 - 1655 01d0 06 .uleb128 0x6 - 1656 01d1 58 .uleb128 0x58 - 1657 01d2 0B .uleb128 0xb - 1658 01d3 59 .uleb128 0x59 - 1659 01d4 05 .uleb128 0x5 - 1660 01d5 00 .byte 0 - 1661 01d6 00 .byte 0 - 1662 01d7 27 .uleb128 0x27 - 1663 01d8 05 .uleb128 0x5 - 1664 01d9 00 .byte 0 - 1665 01da 31 .uleb128 0x31 - 1666 01db 13 .uleb128 0x13 - 1667 01dc 00 .byte 0 - 1668 01dd 00 .byte 0 - 1669 01de 28 .uleb128 0x28 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 39 - - - 1670 01df 1D .uleb128 0x1d - 1671 01e0 01 .byte 0x1 - 1672 01e1 31 .uleb128 0x31 - 1673 01e2 13 .uleb128 0x13 - 1674 01e3 11 .uleb128 0x11 - 1675 01e4 01 .uleb128 0x1 - 1676 01e5 12 .uleb128 0x12 - 1677 01e6 01 .uleb128 0x1 - 1678 01e7 58 .uleb128 0x58 - 1679 01e8 0B .uleb128 0xb - 1680 01e9 59 .uleb128 0x59 - 1681 01ea 05 .uleb128 0x5 - 1682 01eb 01 .uleb128 0x1 - 1683 01ec 13 .uleb128 0x13 - 1684 01ed 00 .byte 0 - 1685 01ee 00 .byte 0 - 1686 01ef 29 .uleb128 0x29 - 1687 01f0 0B .uleb128 0xb - 1688 01f1 01 .byte 0x1 - 1689 01f2 11 .uleb128 0x11 - 1690 01f3 01 .uleb128 0x1 - 1691 01f4 12 .uleb128 0x12 - 1692 01f5 01 .uleb128 0x1 - 1693 01f6 00 .byte 0 - 1694 01f7 00 .byte 0 - 1695 01f8 2A .uleb128 0x2a - 1696 01f9 05 .uleb128 0x5 - 1697 01fa 00 .byte 0 - 1698 01fb 31 .uleb128 0x31 - 1699 01fc 13 .uleb128 0x13 - 1700 01fd 1C .uleb128 0x1c - 1701 01fe 0B .uleb128 0xb - 1702 01ff 00 .byte 0 - 1703 0200 00 .byte 0 - 1704 0201 2B .uleb128 0x2b - 1705 0202 05 .uleb128 0x5 - 1706 0203 00 .byte 0 - 1707 0204 31 .uleb128 0x31 - 1708 0205 13 .uleb128 0x13 - 1709 0206 1C .uleb128 0x1c - 1710 0207 06 .uleb128 0x6 - 1711 0208 00 .byte 0 - 1712 0209 00 .byte 0 - 1713 020a 2C .uleb128 0x2c - 1714 020b 2E .uleb128 0x2e - 1715 020c 01 .byte 0x1 - 1716 020d 3F .uleb128 0x3f - 1717 020e 0C .uleb128 0xc - 1718 020f 03 .uleb128 0x3 - 1719 0210 0E .uleb128 0xe - 1720 0211 3A .uleb128 0x3a - 1721 0212 0B .uleb128 0xb - 1722 0213 3B .uleb128 0x3b - 1723 0214 0B .uleb128 0xb - 1724 0215 27 .uleb128 0x27 - 1725 0216 0C .uleb128 0xc - 1726 0217 3C .uleb128 0x3c - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 40 - - - 1727 0218 0C .uleb128 0xc - 1728 0219 01 .uleb128 0x1 - 1729 021a 13 .uleb128 0x13 - 1730 021b 00 .byte 0 - 1731 021c 00 .byte 0 - 1732 021d 2D .uleb128 0x2d - 1733 021e 05 .uleb128 0x5 - 1734 021f 00 .byte 0 - 1735 0220 49 .uleb128 0x49 - 1736 0221 13 .uleb128 0x13 - 1737 0222 00 .byte 0 - 1738 0223 00 .byte 0 - 1739 0224 2E .uleb128 0x2e - 1740 0225 2E .uleb128 0x2e - 1741 0226 01 .byte 0x1 - 1742 0227 3F .uleb128 0x3f - 1743 0228 0C .uleb128 0xc - 1744 0229 03 .uleb128 0x3 - 1745 022a 0E .uleb128 0xe - 1746 022b 27 .uleb128 0x27 - 1747 022c 0C .uleb128 0xc - 1748 022d 49 .uleb128 0x49 - 1749 022e 13 .uleb128 0x13 - 1750 022f 34 .uleb128 0x34 - 1751 0230 0C .uleb128 0xc - 1752 0231 3C .uleb128 0x3c - 1753 0232 0C .uleb128 0xc - 1754 0233 00 .byte 0 - 1755 0234 00 .byte 0 - 1756 0235 00 .byte 0 - 1757 .section .debug_loc,"",%progbits - 1758 .Ldebug_loc0: - 1759 .LLST0: - 1760 0000 00000000 .4byte .LFB8 - 1761 0004 02000000 .4byte .LCFI0 - 1762 0008 0200 .2byte 0x2 - 1763 000a 7D .byte 0x7d - 1764 000b 00 .sleb128 0 - 1765 000c 02000000 .4byte .LCFI0 - 1766 0010 D8010000 .4byte .LFE8 - 1767 0014 0200 .2byte 0x2 - 1768 0016 7D .byte 0x7d - 1769 0017 18 .sleb128 24 - 1770 0018 00000000 .4byte 0 - 1771 001c 00000000 .4byte 0 - 1772 .LLST1: - 1773 0020 50000000 .4byte .LVL4 - 1774 0024 68000000 .4byte .LVL5 - 1775 0028 0100 .2byte 0x1 - 1776 002a 54 .byte 0x54 - 1777 002b 82000000 .4byte .LVL7 - 1778 002f 84000000 .4byte .LVL8 - 1779 0033 0100 .2byte 0x1 - 1780 0035 54 .byte 0x54 - 1781 0036 00000000 .4byte 0 - 1782 003a 00000000 .4byte 0 - 1783 .LLST2: - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 41 - - - 1784 003e 80000000 .4byte .LVL6 - 1785 0042 82000000 .4byte .LVL7 - 1786 0046 0200 .2byte 0x2 - 1787 0048 30 .byte 0x30 - 1788 0049 9F .byte 0x9f - 1789 004a 00000000 .4byte 0 - 1790 004e 00000000 .4byte 0 - 1791 .LLST3: - 1792 0052 8C000000 .4byte .LVL9 - 1793 0056 94000000 .4byte .LVL11 - 1794 005a 0100 .2byte 0x1 - 1795 005c 52 .byte 0x52 - 1796 005d 94000000 .4byte .LVL11 - 1797 0061 A0000000 .4byte .LVL13 - 1798 0065 0800 .2byte 0x8 - 1799 0067 76 .byte 0x76 - 1800 0068 7F .sleb128 -1 - 1801 0069 36 .byte 0x36 - 1802 006a 1E .byte 0x1e - 1803 006b 77 .byte 0x77 - 1804 006c 00 .sleb128 0 - 1805 006d 22 .byte 0x22 - 1806 006e 9F .byte 0x9f - 1807 006f 00000000 .4byte 0 - 1808 0073 00000000 .4byte 0 - 1809 .LLST4: - 1810 0077 8C000000 .4byte .LVL9 - 1811 007b 94000000 .4byte .LVL11 - 1812 007f 0900 .2byte 0x9 - 1813 0081 72 .byte 0x72 - 1814 0082 04 .sleb128 4 - 1815 0083 94 .byte 0x94 - 1816 0084 02 .byte 0x2 - 1817 0085 0A .byte 0xa - 1818 0086 FFFF .2byte 0xffff - 1819 0088 1A .byte 0x1a - 1820 0089 9F .byte 0x9f - 1821 008a 94000000 .4byte .LVL11 - 1822 008e 97000000 .4byte .LVL12-1 - 1823 0092 1000 .2byte 0x10 - 1824 0094 76 .byte 0x76 - 1825 0095 7F .sleb128 -1 - 1826 0096 36 .byte 0x36 - 1827 0097 1E .byte 0x1e - 1828 0098 77 .byte 0x77 - 1829 0099 00 .sleb128 0 - 1830 009a 22 .byte 0x22 - 1831 009b 23 .byte 0x23 - 1832 009c 04 .uleb128 0x4 - 1833 009d 94 .byte 0x94 - 1834 009e 02 .byte 0x2 - 1835 009f 0A .byte 0xa - 1836 00a0 FFFF .2byte 0xffff - 1837 00a2 1A .byte 0x1a - 1838 00a3 9F .byte 0x9f - 1839 00a4 00000000 .4byte 0 - 1840 00a8 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 42 - - - 1841 .LLST5: - 1842 00ac 8C000000 .4byte .LVL9 - 1843 00b0 92000000 .4byte .LVL10 - 1844 00b4 0A00 .2byte 0xa - 1845 00b6 76 .byte 0x76 - 1846 00b7 00 .sleb128 0 - 1847 00b8 36 .byte 0x36 - 1848 00b9 1E .byte 0x1e - 1849 00ba 03 .byte 0x3 - 1850 00bb 00000000 .4byte .LANCHOR0 - 1851 00bf 22 .byte 0x22 - 1852 00c0 92000000 .4byte .LVL10 - 1853 00c4 97000000 .4byte .LVL12-1 - 1854 00c8 0A00 .2byte 0xa - 1855 00ca 76 .byte 0x76 - 1856 00cb 7F .sleb128 -1 - 1857 00cc 36 .byte 0x36 - 1858 00cd 1E .byte 0x1e - 1859 00ce 03 .byte 0x3 - 1860 00cf 00000000 .4byte .LANCHOR0 - 1861 00d3 22 .byte 0x22 - 1862 00d4 00000000 .4byte 0 - 1863 00d8 00000000 .4byte 0 - 1864 .LLST6: - 1865 00dc D4000000 .4byte .LVL18 - 1866 00e0 E2000000 .4byte .LVL19 - 1867 00e4 0100 .2byte 0x1 - 1868 00e6 51 .byte 0x51 - 1869 00e7 00000000 .4byte 0 - 1870 00eb 00000000 .4byte 0 - 1871 .LLST7: - 1872 00ef A6000000 .4byte .LVL14 - 1873 00f3 AE000000 .4byte .LVL16 - 1874 00f7 0100 .2byte 0x1 - 1875 00f9 50 .byte 0x50 - 1876 00fa AE000000 .4byte .LVL16 - 1877 00fe D8010000 .4byte .LFE8 - 1878 0102 0100 .2byte 0x1 - 1879 0104 57 .byte 0x57 - 1880 0105 00000000 .4byte 0 - 1881 0109 00000000 .4byte 0 - 1882 .LLST8: - 1883 010d AA000000 .4byte .LVL15 - 1884 0111 B2000000 .4byte .LVL17 - 1885 0115 0100 .2byte 0x1 - 1886 0117 50 .byte 0x50 - 1887 0118 00000000 .4byte 0 - 1888 011c 00000000 .4byte 0 - 1889 .LLST9: - 1890 0120 56010000 .4byte .LVL25 - 1891 0124 5C010000 .4byte .LVL26 - 1892 0128 0100 .2byte 0x1 - 1893 012a 53 .byte 0x53 - 1894 012b 00000000 .4byte 0 - 1895 012f 00000000 .4byte 0 - 1896 .section .debug_aranges,"",%progbits - 1897 0000 24000000 .4byte 0x24 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 43 - - - 1898 0004 0200 .2byte 0x2 - 1899 0006 00000000 .4byte .Ldebug_info0 - 1900 000a 04 .byte 0x4 - 1901 000b 00 .byte 0 - 1902 000c 0000 .2byte 0 - 1903 000e 0000 .2byte 0 - 1904 0010 00000000 .4byte .LFB7 - 1905 0014 0C000000 .4byte .LFE7-.LFB7 - 1906 0018 00000000 .4byte .LFB8 - 1907 001c D8010000 .4byte .LFE8-.LFB8 - 1908 0020 00000000 .4byte 0 - 1909 0024 00000000 .4byte 0 - 1910 .section .debug_ranges,"",%progbits - 1911 .Ldebug_ranges0: - 1912 0000 08000000 .4byte .LBB32 - 1913 0004 16000000 .4byte .LBE32 - 1914 0008 18000000 .4byte .LBB36 - 1915 000c 60000000 .4byte .LBE36 - 1916 0010 62000000 .4byte .LBB37 - 1917 0014 78000000 .4byte .LBE37 - 1918 0018 00000000 .4byte 0 - 1919 001c 00000000 .4byte 0 - 1920 0020 08000000 .4byte .LBB33 - 1921 0024 16000000 .4byte .LBE33 - 1922 0028 18000000 .4byte .LBB34 - 1923 002c 60000000 .4byte .LBE34 - 1924 0030 62000000 .4byte .LBB35 - 1925 0034 78000000 .4byte .LBE35 - 1926 0038 00000000 .4byte 0 - 1927 003c 00000000 .4byte 0 - 1928 0040 84000000 .4byte .LBB38 - 1929 0044 44010000 .4byte .LBE38 - 1930 0048 46010000 .4byte .LBB48 - 1931 004c 48010000 .4byte .LBE48 - 1932 0050 00000000 .4byte 0 - 1933 0054 00000000 .4byte 0 - 1934 0058 A0000000 .4byte .LBB42 - 1935 005c A2000000 .4byte .LBE42 - 1936 0060 A4000000 .4byte .LBB47 - 1937 0064 D6000000 .4byte .LBE47 - 1938 0068 00000000 .4byte 0 - 1939 006c 00000000 .4byte 0 - 1940 0070 A0000000 .4byte .LBB43 - 1941 0074 A2000000 .4byte .LBE43 - 1942 0078 A4000000 .4byte .LBB46 - 1943 007c D6000000 .4byte .LBE46 - 1944 0080 00000000 .4byte 0 - 1945 0084 00000000 .4byte 0 - 1946 0088 A0000000 .4byte .LBB44 - 1947 008c A2000000 .4byte .LBE44 - 1948 0090 A4000000 .4byte .LBB45 - 1949 0094 D0000000 .4byte .LBE45 - 1950 0098 00000000 .4byte 0 - 1951 009c 00000000 .4byte 0 - 1952 00a0 00000000 .4byte .LFB7 - 1953 00a4 0C000000 .4byte .LFE7 - 1954 00a8 00000000 .4byte .LFB8 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 44 - - - 1955 00ac D8010000 .4byte .LFE8 - 1956 00b0 00000000 .4byte 0 - 1957 00b4 00000000 .4byte 0 - 1958 .section .debug_line,"",%progbits - 1959 .Ldebug_line0: - 1960 0000 D2010000 .section .debug_str,"MS",%progbits,1 - 1960 0200E200 - 1960 00000201 - 1960 FB0E0D00 - 1960 01010101 - 1961 .LASF31: - 1962 0000 636F756E .ascii "count\000" - 1962 7400 - 1963 .LASF13: - 1964 0006 75696E74 .ascii "uint16\000" - 1964 313600 - 1965 .LASF30: - 1966 000d 62617365 .ascii "baseAddr\000" - 1966 41646472 - 1966 00 - 1967 .LASF11: - 1968 0016 73697A65 .ascii "size_t\000" - 1968 5F7400 - 1969 .LASF22: - 1970 001d 4379436C .ascii "CyClockStartupError\000" - 1970 6F636B53 - 1970 74617274 - 1970 75704572 - 1970 726F7200 - 1971 .LASF29: - 1972 0031 64617461 .ascii "data_table\000" - 1972 5F746162 - 1972 6C6500 - 1973 .LASF6: - 1974 003c 6C6F6E67 .ascii "long long unsigned int\000" - 1974 206C6F6E - 1974 6720756E - 1974 7369676E - 1974 65642069 - 1975 .LASF28: - 1976 0053 61646472 .ascii "addr_table\000" - 1976 5F746162 - 1976 6C6500 - 1977 .LASF47: - 1978 005e 63795F63 .ascii "cy_cfg_data_table\000" - 1978 66675F64 - 1978 6174615F - 1978 7461626C - 1978 6500 - 1979 .LASF36: - 1980 0070 416E616C .ascii "AnalogSetDefault\000" - 1980 6F675365 - 1980 74446566 - 1980 61756C74 - 1980 00 - 1981 .LASF5: - 1982 0081 6C6F6E67 .ascii "long long int\000" - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 45 - - - 1982 206C6F6E - 1982 6720696E - 1982 7400 - 1983 .LASF0: - 1984 008f 7369676E .ascii "signed char\000" - 1984 65642063 - 1984 68617200 - 1985 .LASF46: - 1986 009b 63795F63 .ascii "cy_cfg_addr_table\000" - 1986 66675F61 - 1986 6464725F - 1986 7461626C - 1986 6500 - 1987 .LASF27: - 1988 00ad 6366675F .ascii "cfg_write_bytes32\000" - 1988 77726974 - 1988 655F6279 - 1988 74657333 - 1988 3200 - 1989 .LASF32: - 1990 00bf 436C6F63 .ascii "ClockSetup\000" - 1990 6B536574 - 1990 757000 - 1991 .LASF24: - 1992 00ca 6572726F .ascii "errorCode\000" - 1992 72436F64 - 1992 6500 - 1993 .LASF44: - 1994 00d4 42535F49 .ascii "BS_IOPINS0_4_VAL\000" - 1994 4F50494E - 1994 53305F34 - 1994 5F56414C - 1994 00 - 1995 .LASF7: - 1996 00e5 6C6F6E67 .ascii "long int\000" - 1996 20696E74 - 1996 00 - 1997 .LASF18: - 1998 00ee 72656731 .ascii "reg16\000" - 1998 3600 - 1999 .LASF12: - 2000 00f4 75696E74 .ascii "uint8\000" - 2000 3800 - 2001 .LASF16: - 2002 00fa 646F7562 .ascii "double\000" - 2002 6C6500 - 2003 .LASF35: - 2004 0101 43594D45 .ascii "CYMEMZERO\000" - 2004 4D5A4552 - 2004 4F00 - 2005 .LASF14: - 2006 010b 75696E74 .ascii "uint32\000" - 2006 333200 - 2007 .LASF40: - 2008 0112 72656756 .ascii "regValue\000" - 2008 616C7565 - 2008 00 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 46 - - - 2009 .LASF20: - 2010 011b 76616C75 .ascii "value\000" - 2010 6500 - 2011 .LASF4: - 2012 0121 756E7369 .ascii "unsigned int\000" - 2012 676E6564 - 2012 20696E74 - 2012 00 - 2013 .LASF53: - 2014 012e 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\cyfitter_cfg.c\000" - 2014 6E657261 - 2014 7465645F - 2014 536F7572 - 2014 63655C50 - 2015 .LASF9: - 2016 0156 6C6F6E67 .ascii "long unsigned int\000" - 2016 20756E73 - 2016 69676E65 - 2016 6420696E - 2016 7400 - 2017 .LASF33: - 2018 0168 74696D65 .ascii "timeout\000" - 2018 6F757400 - 2019 .LASF49: - 2020 0170 73697A65 .ascii "size\000" - 2020 00 - 2021 .LASF3: - 2022 0175 73686F72 .ascii "short unsigned int\000" - 2022 7420756E - 2022 7369676E - 2022 65642069 - 2022 6E7400 - 2023 .LASF45: - 2024 0188 42535F49 .ascii "BS_IOPINS0_6_VAL\000" - 2024 4F50494E - 2024 53305F36 - 2024 5F56414C - 2024 00 - 2025 .LASF54: - 2026 0199 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 2026 43534932 - 2026 53445C73 - 2026 6F667477 - 2026 6172655C - 2027 01c8 6E00 .ascii "n\000" - 2028 .LASF23: - 2029 01ca 4359434F .ascii "CYCONFIGCPYCODE\000" - 2029 4E464947 - 2029 43505943 - 2029 4F444500 - 2030 .LASF8: - 2031 01da 73697A65 .ascii "sizetype\000" - 2031 74797065 - 2031 00 - 2032 .LASF37: - 2033 01e3 62675F78 .ascii "bg_xover_inl_trim\000" - 2033 6F766572 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 47 - - - 2033 5F696E6C - 2033 5F747269 - 2033 6D00 - 2034 .LASF50: - 2035 01f5 6366675F .ascii "cfg_memset_t\000" - 2035 6D656D73 - 2035 65745F74 - 2035 00 - 2036 .LASF51: - 2037 0202 6366675F .ascii "cfg_memset_list\000" - 2037 6D656D73 - 2037 65745F6C - 2037 69737400 - 2038 .LASF43: - 2039 0212 42535F49 .ascii "BS_IOPINS0_3_VAL\000" - 2039 4F50494E - 2039 53305F33 - 2039 5F56414C - 2039 00 - 2040 .LASF25: - 2041 0223 64657374 .ascii "dest\000" - 2041 00 - 2042 .LASF15: - 2043 0228 666C6F61 .ascii "float\000" - 2043 7400 - 2044 .LASF56: - 2045 022e 43794465 .ascii "CyDelayCycles\000" - 2045 6C617943 - 2045 79636C65 - 2045 7300 - 2046 .LASF52: - 2047 023c 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 2047 4320342E - 2047 372E3320 - 2047 32303133 - 2047 30333132 - 2048 026f 616E6368 .ascii "anch revision 196615]\000" - 2048 20726576 - 2048 6973696F - 2048 6E203139 - 2048 36363135 - 2049 .LASF17: - 2050 0285 72656738 .ascii "reg8\000" - 2050 00 - 2051 .LASF1: - 2052 028a 756E7369 .ascii "unsigned char\000" - 2052 676E6564 - 2052 20636861 - 2052 7200 - 2053 .LASF2: - 2054 0298 73686F72 .ascii "short int\000" - 2054 7420696E - 2054 7400 - 2055 .LASF41: - 2056 02a2 42535F49 .ascii "BS_IOPINS0_0_VAL\000" - 2056 4F50494E - 2056 53305F30 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccYFm6IZ.s page 48 - - - 2056 5F56414C - 2056 00 - 2057 .LASF34: - 2058 02b3 706C6C4C .ascii "pllLock\000" - 2058 6F636B00 - 2059 .LASF42: - 2060 02bb 42535F49 .ascii "BS_IOPINS0_8_VAL\000" - 2060 4F50494E - 2060 53305F38 - 2060 5F56414C - 2060 00 - 2061 .LASF21: - 2062 02cc 63795F63 .ascii "cy_cfg_addrvalue_t\000" - 2062 66675F61 - 2062 64647276 - 2062 616C7565 - 2062 5F7400 - 2063 .LASF10: - 2064 02df 63686172 .ascii "char\000" - 2064 00 - 2065 .LASF38: - 2066 02e4 53657441 .ascii "SetAnalogRoutingPumps\000" - 2066 6E616C6F - 2066 67526F75 - 2066 74696E67 - 2066 50756D70 - 2067 .LASF19: - 2068 02fa 6F666673 .ascii "offset\000" - 2068 657400 - 2069 .LASF55: - 2070 0301 656E6162 .ascii "enabled\000" - 2070 6C656400 - 2071 .LASF57: - 2072 0309 6D656D73 .ascii "memset\000" - 2072 657400 - 2073 .LASF26: - 2074 0310 4359434F .ascii "CYCONFIGCPY\000" - 2074 4E464947 - 2074 43505900 - 2075 .LASF48: - 2076 031c 61646472 .ascii "address\000" - 2076 65737300 - 2077 .LASF39: - 2078 0324 63796669 .ascii "cyfitter_cfg\000" - 2078 74746572 - 2078 5F636667 - 2078 00 - 2079 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyfitter_cfg.o deleted file mode 100755 index 80b2555ee90ad30b297df417333c00f53baf6b96..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 8336 zcmb_heRNdEb)R`}S6XR>zCj;=^i~oeEa^!?vJjY(r(H=%Adrv%gDpqek0)vC)$V$C z1(Iz*Cb+>kb#Ov#r}jCPQy<519h=f7jY-qEIizje^aOeuH}P>>;-n|89or(osp7b% zzdJimdO&jAKRSn*-~F09Gk5OH8!bn>`noyi%qpDKvL%kO{Y66KY!y(;RiubKf$JPJ-=qmpM$Gqw&xuDj+cd@^xzn`t`zcQQL zwKLPxQ>E0Xvpl{velDI7@4kyIsC~85#=JwVi?d4~{k*$B!^3}@kzk(u3EuX(6XeaM z|LP*EF6%b>SXJqPrq;hZtIc1{biCc+_~F?Xyjd3p(G-8pY4*>QEcal3Cm-=Xht#7ifJ zC-O)4jFxxT_Y5w$`W>TtCJG>r#k7XGHsSU6Wte7WFX0RLS5&_Y$7 zw*7YWuIw2aRWP1QRpYCBDz>ZB>U<_!nUxspX?}cjq(@EjZi{dcA0WbFu71 z!R*4f*tb~^Gx9j=t@1MCscvSh0Xht3WT3tYp0=$CRUP2QcYMs4LsfP&;~~iAfdSMi z$bJAHQS2w}=^60(kZWuJZ9aQhw2X0s<+Eb6E@q(3W_@TC2G1JfUGO^yc?mao88=i| zC>^L?R3G?ls6C+3hwtXb5oOiZdyRLq-_35BZ8N^#^o;T4S*yBSdB%5gUNByqeRtq_ z*NZgL)vL6S#qu&^TP5@1hiM`&PhgjmVMk1So8TL>J^{}hn<8gvc^jP{Wccl`$(I9HJFhkaXg!6Q!EDR>B>hO>>+%zfa2hehg*SYBW5|c@-?OUl9zMv8-39OE2gBq^PD2 zy)nq$$wUw&N!?KpN69$Hu^0TZtb7$_Ud}(Y*vGrn$7}WRiauFiMMr*`^NVCWBp5+9 z3-WbHbHj{3ItMoQ4<(V8zl^khLc)Ah#vd26#SH!x9STUE<9LHeib5g(8BIJleRJhN zq8w(t0KCWzT+VA~=%)0Xegp*-{+ABMioZnuTljg&|F@__EaxN=|?+dkNHg zM4Sh)43$bP<;4J)F;xB{KZ%L1xA?Lcl$x-tp=*I`C=>Wue$xyvw=Rm7F5$W$2)b!u zPw7LcAp=!FDI&)G-J4Os2YEg&F{OsN-CH5V)g(z5 z+~z@wJzc@n+|BM=+`V`+WZcXMGK;v|O)?I~wQSL#JsTI1&eQhmax|gOb}s61^1!$( zZ#gsq`CGOYQ_F3&sq*MT&4*-h=z_Ik=t7-;B1cG_>v9TsAvdxg_2$q#isU%X-XaC_ zD3+ZiyZnZJ8M5Ds)x5cAknhdd?>^upMgt>O@?y1^)mB^;-f?5kJHpCsc)QS&Y1YD)v5DCGHbsM+iwYpcLfKzNC#UXWpk zw2Tx~=r(=>m9yQ%Qh5gT1ys%k2*gQew}KMoIkaa{p-l@IqdQ?3m9rsBR0D!ShI1rZ zYOGLN9}$w_pfP$~P%KAL1E|xeR{1zR#kvziccb>8T4fHzmr$QZeHGOzb09uWe!()9 z_`Bx)&lpP)fm8TzbC)svwLzn!a(#H488s9Blo=WsicKYg=J3E!%y%;jZXS*&V&e(_ zq&60gm`Sa6y1i}vaBwD`Fq6sQcrq5$f(g@~iY10y^rmYC;mLR`ks2P4PK^YU!~VqN zaI3yiZy64Rqro-%sM%op1K~zt(in~gBU2%hvEa;DIF&LJBf+t8 z9nT`hlBrP09MdOguYxnFnYft*1BGvxd*>K*EHhc)$8MFZ**HT5ToQpMFLq4^0kuN>L#sq{2fdOYes9@(O7!m5I? zDZG%U@Jw!QV*!8C>D zj%%WsiYCM3Q8T2`bK4IO(jquRfgiE;>4^FxvGE}@)oG6Try?nv6Y4A71Sk9n?2hPc zcL!gG65*6N5|~Mu$(9W)JwFq(VI-@+Zti!QLV7h&L8XMPmMtnb3nXp=1;b z@%8WO?%n1a0MXecMxyj)f$@>)*g>3ua5OTKN`xmF?a8D$nKV<_WE&F+CsX$5wTPL7 zOi0Ht79~Wd8S&5fW`a1(Y}>BAnokoaPTSDb+|tz2yg{o?m=P0sv|hWtV{m7qITRiTT7Mkv?Rl zUC}NSwuBLTM~kCGLbj#TZV)>Vj*bsZO~#WfHa3O;Ff&TI9AfEs*rO;C8Q0V`mk49q ze7?W3hyWm1{$4NV6%P7CQG9u>qTtnXZ*I=A#V-+5f~K#PRp{%~ky~nf zD#JMLH12m8f210pR*Z+p57Uz~lQ{0cR3eQN7KK@)m`;bA=>fz^CxQOEqpc$?(t7(* zVR|B#?oaBF8JHSJmX5{XRnY!G0LcQYMJ?_lJL^YAjUyFp7B@;F;izeO#N3%4j7?6O zNG%=vru$Pk6M-q*Cw4Dm_-5hz@qaEWVM+1AJ4=*Si57_O2^bG5*@-6!@OnEDbI8}B z(o5ju?CN22{kYcG8>+>(NZ)mK26+3c#Co&zK%Rwal?&x~WP&L}#dB2nqj`;>(zw>T zNeGZur5%4NHe1OEo^({{F>SXC!^vHcS;eyZHwe%@ZpmMRU5mv4 z$&SipREs7)zYwonB4nZYQF#Z|zK*!Y82*X4(CgY-2ZmWZLm=6H_@h6ptzwNuXiFn@ zss#B50n$+TC4Uqr8q*dAb^#l46*8+>{w&@?yWGJp+q=M@T}%G$Ga=qSBJmC}7t1%T z7JvGQ^O2TWQA%?vPA<)TsW^rG?BcMt0|_G)Kk|^jrIIQBVj-ULfkR&>X^Z!QA4Szs zNq+$N5GtKn;^}9JM^JGL1yAR04%O1rZ&%OS_&*1I#>RtOEUIm#BvgghMKyRFCRb>)-gM(TnZzxYcY?%SC00tTm$*@)PhwDFT;gGg^uHhq4)+5R|CkVW z>Z4NsG$Ho$E0X`Zyi9!$=@b%oDlu*lz2$uJra)-qW@s&441G!iy_*!ZIzsDoMi~s-t diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.lst deleted file mode 100755 index c49df57..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.lst +++ /dev/null @@ -1,575 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "cymetadata.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .global cy_metadata - 19 .global cy_meta_flashprotect - 20 .global cy_meta_wonvl - 21 .global cy_meta_custnvl - 22 .global cy_meta_configecc - 23 .global cy_meta_loader - 24 .section .cyconfigecc,"a",%progbits - 25 .type cy_meta_configecc, %object - 26 .size cy_meta_configecc, 1 - 27 cy_meta_configecc: - 28 0000 00 .space 1 - 29 .section .cywolatch,"a",%progbits - 30 .type cy_meta_wonvl, %object - 31 .size cy_meta_wonvl, 4 - 32 cy_meta_wonvl: - 33 0000 BC .byte -68 - 34 0001 90 .byte -112 - 35 0002 AC .byte -84 - 36 0003 AF .byte -81 - 37 .section .cyloadermeta,"a",%progbits - 38 .type cy_meta_loader, %object - 39 .size cy_meta_loader, 64 - 40 cy_meta_loader: - 41 0000 00 .byte 0 - 42 0001 00 .byte 0 - 43 0002 00 .byte 0 - 44 0003 00 .byte 0 - 45 0004 00 .byte 0 - 46 0005 00 .byte 0 - 47 0006 00 .byte 0 - 48 0007 00 .byte 0 - 49 0008 00 .byte 0 - 50 0009 00 .byte 0 - 51 000a 00 .byte 0 - 52 000b 00 .byte 0 - 53 000c 00 .byte 0 - 54 000d 00 .byte 0 - 55 000e 00 .byte 0 - 56 000f 00 .byte 0 - 57 0010 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 2 - - - 58 0011 00 .byte 0 - 59 0012 00 .byte 0 - 60 0013 00 .byte 0 - 61 0014 01 .byte 1 - 62 0015 00 .byte 0 - 63 0016 01 .byte 1 - 64 0017 00 .byte 0 - 65 0018 00 .byte 0 - 66 0019 00 .byte 0 - 67 001a 00 .byte 0 - 68 001b 00 .byte 0 - 69 001c 00 .byte 0 - 70 001d 00 .byte 0 - 71 001e 00 .byte 0 - 72 001f 00 .byte 0 - 73 0020 00 .byte 0 - 74 0021 00 .byte 0 - 75 0022 00 .byte 0 - 76 0023 00 .byte 0 - 77 0024 00 .byte 0 - 78 0025 00 .byte 0 - 79 0026 00 .byte 0 - 80 0027 00 .byte 0 - 81 0028 00 .byte 0 - 82 0029 00 .byte 0 - 83 002a 00 .byte 0 - 84 002b 00 .byte 0 - 85 002c 00 .byte 0 - 86 002d 00 .byte 0 - 87 002e 00 .byte 0 - 88 002f 00 .byte 0 - 89 0030 00 .byte 0 - 90 0031 00 .byte 0 - 91 0032 00 .byte 0 - 92 0033 00 .byte 0 - 93 0034 00 .byte 0 - 94 0035 00 .byte 0 - 95 0036 00 .byte 0 - 96 0037 00 .byte 0 - 97 0038 00 .byte 0 - 98 0039 00 .byte 0 - 99 003a 00 .byte 0 - 100 003b 00 .byte 0 - 101 003c 00 .byte 0 - 102 003d 00 .byte 0 - 103 003e 00 .byte 0 - 104 003f 00 .byte 0 - 105 .section .cycustnvl,"a",%progbits - 106 .type cy_meta_custnvl, %object - 107 .size cy_meta_custnvl, 4 - 108 cy_meta_custnvl: - 109 0000 80 .byte -128 - 110 0001 00 .byte 0 - 111 0002 40 .byte 64 - 112 0003 05 .byte 5 - 113 .section .cymeta,"a",%progbits - 114 .type cy_metadata, %object - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 3 - - - 115 .size cy_metadata, 12 - 116 cy_metadata: - 117 0000 00 .byte 0 - 118 0001 01 .byte 1 - 119 0002 2E .byte 46 - 120 0003 13 .byte 19 - 121 0004 30 .byte 48 - 122 0005 69 .byte 105 - 123 0006 00 .byte 0 - 124 0007 01 .byte 1 - 125 0008 00 .byte 0 - 126 0009 00 .byte 0 - 127 000a 00 .byte 0 - 128 000b 00 .byte 0 - 129 .section .cyflashprotect,"a",%progbits - 130 .type cy_meta_flashprotect, %object - 131 .size cy_meta_flashprotect, 128 - 132 cy_meta_flashprotect: - 133 0000 00000000 .space 128 - 133 00000000 - 133 00000000 - 133 00000000 - 133 00000000 - 134 .text - 135 .Letext0: - 136 .file 1 ".\\Generated_Source\\PSoC5\\cymetadata.c" - 137 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 138 .section .debug_info,"",%progbits - 139 .Ldebug_info0: - 140 0000 61010000 .4byte 0x161 - 141 0004 0200 .2byte 0x2 - 142 0006 00000000 .4byte .Ldebug_abbrev0 - 143 000a 04 .byte 0x4 - 144 000b 01 .uleb128 0x1 - 145 000c 47010000 .4byte .LASF19 - 146 0010 01 .byte 0x1 - 147 0011 00000000 .4byte .LASF20 - 148 0015 67000000 .4byte .LASF21 - 149 0019 00000000 .4byte .Ldebug_line0 - 150 001d 02 .uleb128 0x2 - 151 001e 01 .byte 0x1 - 152 001f 06 .byte 0x6 - 153 0020 99010000 .4byte .LASF0 - 154 0024 02 .uleb128 0x2 - 155 0025 01 .byte 0x1 - 156 0026 08 .byte 0x8 - 157 0027 47000000 .4byte .LASF1 - 158 002b 02 .uleb128 0x2 - 159 002c 02 .byte 0x2 - 160 002d 05 .byte 0x5 - 161 002e 37010000 .4byte .LASF2 - 162 0032 02 .uleb128 0x2 - 163 0033 02 .byte 0x2 - 164 0034 07 .byte 0x7 - 165 0035 98000000 .4byte .LASF3 - 166 0039 02 .uleb128 0x2 - 167 003a 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 4 - - - 168 003b 05 .byte 0x5 - 169 003c 90010000 .4byte .LASF4 - 170 0040 02 .uleb128 0x2 - 171 0041 04 .byte 0x4 - 172 0042 07 .byte 0x7 - 173 0043 55000000 .4byte .LASF5 - 174 0047 02 .uleb128 0x2 - 175 0048 08 .byte 0x8 - 176 0049 05 .byte 0x5 - 177 004a 24010000 .4byte .LASF6 - 178 004e 02 .uleb128 0x2 - 179 004f 08 .byte 0x8 - 180 0050 07 .byte 0x7 - 181 0051 E1000000 .4byte .LASF7 - 182 0055 03 .uleb128 0x3 - 183 0056 04 .byte 0x4 - 184 0057 05 .byte 0x5 - 185 0058 696E7400 .ascii "int\000" - 186 005c 02 .uleb128 0x2 - 187 005d 04 .byte 0x4 - 188 005e 07 .byte 0x7 - 189 005f D4000000 .4byte .LASF8 - 190 0063 04 .uleb128 0x4 - 191 0064 41010000 .4byte .LASF22 - 192 0068 02 .byte 0x2 - 193 0069 5B .byte 0x5b - 194 006a 24000000 .4byte 0x24 - 195 006e 02 .uleb128 0x2 - 196 006f 04 .byte 0x4 - 197 0070 04 .byte 0x4 - 198 0071 41000000 .4byte .LASF9 - 199 0075 02 .uleb128 0x2 - 200 0076 08 .byte 0x8 - 201 0077 04 .byte 0x4 - 202 0078 AB000000 .4byte .LASF10 - 203 007c 02 .uleb128 0x2 - 204 007d 01 .byte 0x1 - 205 007e 08 .byte 0x8 - 206 007f 32010000 .4byte .LASF11 - 207 0083 05 .uleb128 0x5 - 208 0084 63000000 .4byte 0x63 - 209 0088 93000000 .4byte 0x93 - 210 008c 06 .uleb128 0x6 - 211 008d 93000000 .4byte 0x93 - 212 0091 3F .byte 0x3f - 213 0092 00 .byte 0 - 214 0093 02 .uleb128 0x2 - 215 0094 04 .byte 0x4 - 216 0095 07 .byte 0x7 - 217 0096 1B010000 .4byte .LASF12 - 218 009a 07 .uleb128 0x7 - 219 009b 26000000 .4byte .LASF13 - 220 009f 01 .byte 0x1 - 221 00a0 1C .byte 0x1c - 222 00a1 AC000000 .4byte 0xac - 223 00a5 01 .byte 0x1 - 224 00a6 05 .byte 0x5 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 5 - - - 225 00a7 03 .byte 0x3 - 226 00a8 00000000 .4byte cy_meta_loader - 227 00ac 08 .uleb128 0x8 - 228 00ad 83000000 .4byte 0x83 - 229 00b1 05 .uleb128 0x5 - 230 00b2 63000000 .4byte 0x63 - 231 00b6 C1000000 .4byte 0xc1 - 232 00ba 06 .uleb128 0x6 - 233 00bb 93000000 .4byte 0x93 - 234 00bf 00 .byte 0 - 235 00c0 00 .byte 0 - 236 00c1 07 .uleb128 0x7 - 237 00c2 C2000000 .4byte .LASF14 - 238 00c6 01 .byte 0x1 - 239 00c7 2E .byte 0x2e - 240 00c8 D3000000 .4byte 0xd3 - 241 00cc 01 .byte 0x1 - 242 00cd 05 .byte 0x5 - 243 00ce 03 .byte 0x3 - 244 00cf 00000000 .4byte cy_meta_configecc - 245 00d3 08 .uleb128 0x8 - 246 00d4 B1000000 .4byte 0xb1 - 247 00d8 05 .uleb128 0x5 - 248 00d9 63000000 .4byte 0x63 - 249 00dd E8000000 .4byte 0xe8 - 250 00e1 06 .uleb128 0x6 - 251 00e2 93000000 .4byte 0x93 - 252 00e6 03 .byte 0x3 - 253 00e7 00 .byte 0 - 254 00e8 07 .uleb128 0x7 - 255 00e9 B2000000 .4byte .LASF15 - 256 00ed 01 .byte 0x1 - 257 00ee 39 .byte 0x39 - 258 00ef FA000000 .4byte 0xfa - 259 00f3 01 .byte 0x1 - 260 00f4 05 .byte 0x5 - 261 00f5 03 .byte 0x3 - 262 00f6 00000000 .4byte cy_meta_custnvl - 263 00fa 08 .uleb128 0x8 - 264 00fb D8000000 .4byte 0xd8 - 265 00ff 07 .uleb128 0x7 - 266 0100 0D010000 .4byte .LASF16 - 267 0104 01 .byte 0x1 - 268 0105 44 .byte 0x44 - 269 0106 11010000 .4byte 0x111 - 270 010a 01 .byte 0x1 - 271 010b 05 .byte 0x5 - 272 010c 03 .byte 0x3 - 273 010d 00000000 .4byte cy_meta_wonvl - 274 0111 08 .uleb128 0x8 - 275 0112 D8000000 .4byte 0xd8 - 276 0116 05 .uleb128 0x5 - 277 0117 63000000 .4byte 0x63 - 278 011b 26010000 .4byte 0x126 - 279 011f 06 .uleb128 0x6 - 280 0120 93000000 .4byte 0x93 - 281 0124 7F .byte 0x7f - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 6 - - - 282 0125 00 .byte 0 - 283 0126 07 .uleb128 0x7 - 284 0127 F8000000 .4byte .LASF17 - 285 012b 01 .byte 0x1 - 286 012c 4F .byte 0x4f - 287 012d 38010000 .4byte 0x138 - 288 0131 01 .byte 0x1 - 289 0132 05 .byte 0x5 - 290 0133 03 .byte 0x3 - 291 0134 00000000 .4byte cy_meta_flashprotect - 292 0138 08 .uleb128 0x8 - 293 0139 16010000 .4byte 0x116 - 294 013d 05 .uleb128 0x5 - 295 013e 63000000 .4byte 0x63 - 296 0142 4D010000 .4byte 0x14d - 297 0146 06 .uleb128 0x6 - 298 0147 93000000 .4byte 0x93 - 299 014b 0B .byte 0xb - 300 014c 00 .byte 0 - 301 014d 07 .uleb128 0x7 - 302 014e 35000000 .4byte .LASF18 - 303 0152 01 .byte 0x1 - 304 0153 69 .byte 0x69 - 305 0154 5F010000 .4byte 0x15f - 306 0158 01 .byte 0x1 - 307 0159 05 .byte 0x5 - 308 015a 03 .byte 0x3 - 309 015b 00000000 .4byte cy_metadata - 310 015f 08 .uleb128 0x8 - 311 0160 3D010000 .4byte 0x13d - 312 0164 00 .byte 0 - 313 .section .debug_abbrev,"",%progbits - 314 .Ldebug_abbrev0: - 315 0000 01 .uleb128 0x1 - 316 0001 11 .uleb128 0x11 - 317 0002 01 .byte 0x1 - 318 0003 25 .uleb128 0x25 - 319 0004 0E .uleb128 0xe - 320 0005 13 .uleb128 0x13 - 321 0006 0B .uleb128 0xb - 322 0007 03 .uleb128 0x3 - 323 0008 0E .uleb128 0xe - 324 0009 1B .uleb128 0x1b - 325 000a 0E .uleb128 0xe - 326 000b 10 .uleb128 0x10 - 327 000c 06 .uleb128 0x6 - 328 000d 00 .byte 0 - 329 000e 00 .byte 0 - 330 000f 02 .uleb128 0x2 - 331 0010 24 .uleb128 0x24 - 332 0011 00 .byte 0 - 333 0012 0B .uleb128 0xb - 334 0013 0B .uleb128 0xb - 335 0014 3E .uleb128 0x3e - 336 0015 0B .uleb128 0xb - 337 0016 03 .uleb128 0x3 - 338 0017 0E .uleb128 0xe - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 7 - - - 339 0018 00 .byte 0 - 340 0019 00 .byte 0 - 341 001a 03 .uleb128 0x3 - 342 001b 24 .uleb128 0x24 - 343 001c 00 .byte 0 - 344 001d 0B .uleb128 0xb - 345 001e 0B .uleb128 0xb - 346 001f 3E .uleb128 0x3e - 347 0020 0B .uleb128 0xb - 348 0021 03 .uleb128 0x3 - 349 0022 08 .uleb128 0x8 - 350 0023 00 .byte 0 - 351 0024 00 .byte 0 - 352 0025 04 .uleb128 0x4 - 353 0026 16 .uleb128 0x16 - 354 0027 00 .byte 0 - 355 0028 03 .uleb128 0x3 - 356 0029 0E .uleb128 0xe - 357 002a 3A .uleb128 0x3a - 358 002b 0B .uleb128 0xb - 359 002c 3B .uleb128 0x3b - 360 002d 0B .uleb128 0xb - 361 002e 49 .uleb128 0x49 - 362 002f 13 .uleb128 0x13 - 363 0030 00 .byte 0 - 364 0031 00 .byte 0 - 365 0032 05 .uleb128 0x5 - 366 0033 01 .uleb128 0x1 - 367 0034 01 .byte 0x1 - 368 0035 49 .uleb128 0x49 - 369 0036 13 .uleb128 0x13 - 370 0037 01 .uleb128 0x1 - 371 0038 13 .uleb128 0x13 - 372 0039 00 .byte 0 - 373 003a 00 .byte 0 - 374 003b 06 .uleb128 0x6 - 375 003c 21 .uleb128 0x21 - 376 003d 00 .byte 0 - 377 003e 49 .uleb128 0x49 - 378 003f 13 .uleb128 0x13 - 379 0040 2F .uleb128 0x2f - 380 0041 0B .uleb128 0xb - 381 0042 00 .byte 0 - 382 0043 00 .byte 0 - 383 0044 07 .uleb128 0x7 - 384 0045 34 .uleb128 0x34 - 385 0046 00 .byte 0 - 386 0047 03 .uleb128 0x3 - 387 0048 0E .uleb128 0xe - 388 0049 3A .uleb128 0x3a - 389 004a 0B .uleb128 0xb - 390 004b 3B .uleb128 0x3b - 391 004c 0B .uleb128 0xb - 392 004d 49 .uleb128 0x49 - 393 004e 13 .uleb128 0x13 - 394 004f 3F .uleb128 0x3f - 395 0050 0C .uleb128 0xc - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 8 - - - 396 0051 02 .uleb128 0x2 - 397 0052 0A .uleb128 0xa - 398 0053 00 .byte 0 - 399 0054 00 .byte 0 - 400 0055 08 .uleb128 0x8 - 401 0056 26 .uleb128 0x26 - 402 0057 00 .byte 0 - 403 0058 49 .uleb128 0x49 - 404 0059 13 .uleb128 0x13 - 405 005a 00 .byte 0 - 406 005b 00 .byte 0 - 407 005c 00 .byte 0 - 408 .section .debug_aranges,"",%progbits - 409 0000 14000000 .4byte 0x14 - 410 0004 0200 .2byte 0x2 - 411 0006 00000000 .4byte .Ldebug_info0 - 412 000a 04 .byte 0x4 - 413 000b 00 .byte 0 - 414 000c 0000 .2byte 0 - 415 000e 0000 .2byte 0 - 416 0010 00000000 .4byte 0 - 417 0014 00000000 .4byte 0 - 418 .section .debug_line,"",%progbits - 419 .Ldebug_line0: - 420 0000 4F000000 .section .debug_str,"MS",%progbits,1 - 420 02004900 - 420 00000201 - 420 FB0E0D00 - 420 01010101 - 421 .LASF20: - 422 0000 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\cymetadata.c\000" - 422 6E657261 - 422 7465645F - 422 536F7572 - 422 63655C50 - 423 .LASF13: - 424 0026 63795F6D .ascii "cy_meta_loader\000" - 424 6574615F - 424 6C6F6164 - 424 657200 - 425 .LASF18: - 426 0035 63795F6D .ascii "cy_metadata\000" - 426 65746164 - 426 61746100 - 427 .LASF9: - 428 0041 666C6F61 .ascii "float\000" - 428 7400 - 429 .LASF1: - 430 0047 756E7369 .ascii "unsigned char\000" - 430 676E6564 - 430 20636861 - 430 7200 - 431 .LASF5: - 432 0055 6C6F6E67 .ascii "long unsigned int\000" - 432 20756E73 - 432 69676E65 - 432 6420696E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 9 - - - 432 7400 - 433 .LASF21: - 434 0067 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 434 43534932 - 434 53445C73 - 434 6F667477 - 434 6172655C - 435 0096 6E00 .ascii "n\000" - 436 .LASF3: - 437 0098 73686F72 .ascii "short unsigned int\000" - 437 7420756E - 437 7369676E - 437 65642069 - 437 6E7400 - 438 .LASF10: - 439 00ab 646F7562 .ascii "double\000" - 439 6C6500 - 440 .LASF15: - 441 00b2 63795F6D .ascii "cy_meta_custnvl\000" - 441 6574615F - 441 63757374 - 441 6E766C00 - 442 .LASF14: - 443 00c2 63795F6D .ascii "cy_meta_configecc\000" - 443 6574615F - 443 636F6E66 - 443 69676563 - 443 6300 - 444 .LASF8: - 445 00d4 756E7369 .ascii "unsigned int\000" - 445 676E6564 - 445 20696E74 - 445 00 - 446 .LASF7: - 447 00e1 6C6F6E67 .ascii "long long unsigned int\000" - 447 206C6F6E - 447 6720756E - 447 7369676E - 447 65642069 - 448 .LASF17: - 449 00f8 63795F6D .ascii "cy_meta_flashprotect\000" - 449 6574615F - 449 666C6173 - 449 6870726F - 449 74656374 - 450 .LASF16: - 451 010d 63795F6D .ascii "cy_meta_wonvl\000" - 451 6574615F - 451 776F6E76 - 451 6C00 - 452 .LASF12: - 453 011b 73697A65 .ascii "sizetype\000" - 453 74797065 - 453 00 - 454 .LASF6: - 455 0124 6C6F6E67 .ascii "long long int\000" - 455 206C6F6E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cc5i4OkO.s page 10 - - - 455 6720696E - 455 7400 - 456 .LASF11: - 457 0132 63686172 .ascii "char\000" - 457 00 - 458 .LASF2: - 459 0137 73686F72 .ascii "short int\000" - 459 7420696E - 459 7400 - 460 .LASF22: - 461 0141 75696E74 .ascii "uint8\000" - 461 3800 - 462 .LASF19: - 463 0147 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 463 4320342E - 463 372E3320 - 463 32303133 - 463 30333132 - 464 017a 616E6368 .ascii "anch revision 196615]\000" - 464 20726576 - 464 6973696F - 464 6E203139 - 464 36363135 - 465 .LASF4: - 466 0190 6C6F6E67 .ascii "long int\000" - 466 20696E74 - 466 00 - 467 .LASF0: - 468 0199 7369676E .ascii "signed char\000" - 468 65642063 - 468 68617200 - 469 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cymetadata.o deleted file mode 100755 index de807a73607eb6dee44464b35aa472adb18a4393..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3292 zcmb_eO^g&p6n-^5v$HU;GAt}0Y8tcRl1Q_E{QAQ#18&x^fQ&>FmP~qjYIi1??S}3i zU`))C7!Te^Nc@QxFB%g_jGpx%2V>&FgT$EV#dy)97i09G->a^g?pY*C!b_^(-&gOw zs(M}Bt0zuAFN7dNg2pJ-h+Y{`p2DCj;M4w&1^|6_d<)UwD)^oRfjb;iYoZ<1- zeN4JL%mcHySanWC%ZoY4Y7>@q_?#Gcm;GXJ4whW5aFDfJ@g3Ikh3l;4i|1GyER3=? zSo{f^l`pjXn0EA4hrGPMC|kp@~Os@v~sz zNrSKBq0nDIP-wtzLl(}r{M4{d4D1&Jv#9tf0}lV0fqf6TxDlDe@iIU4Y&NSTyJ1vG zR;l<0&pUl60~>*?U<(FTqT+srwQ3pIvye%Y#S=rrC2MHs&?YoiZj?%;=b&Pzv^a=u z8X;@wNa^X)JX)2%M1bVF`Ec4Id@2)+eFpCF`^PD9MmJU_)> zLmLV0u4+L!&f=W(W$4DTQL6@>(36X2szC+Sd)*ZoyA3yX9glm#>&D%SGIE-#G43^Q zv2U8!t#OcAJ8&B^LDzCCgHz=4VV z7m{2YH@lxSSE(Ga$2iGLLC}uur69Bs(mtU>+GoPRlTj3e(VhoU#q1<{%$05(SK1iF zLItNGukKx#qJj0rg>|{j`7L6r*k)}PJH*4{vHatLoT$4JyLIq5OnB2sm>QF#+Qq3y z5#fxz-f2O(613geYqC9Q0&X^i(q{~ZG4&mogB^Anvff#)wfv<3Ih5?y>)2SzcwKDw zvP9+t&~EwC$S4x2f|V7CU3ajnjvL2etKNx$zYp38EWeG(XND;G&ZGg77n*37#;N-c z@>(3nV0sb*cL@C#?kQk+j)~9lObm!U`LLD^jxV-612maA$DwEA@w^$0VP zwetSHfnnxABp(annhhD>+b|fJeP08&-GDN_8<4Yk?_jZn;)Fd)Q5V?S9SnlcKw30+QbJxJka^9#-c1<1C#IJnQWNK~wm!D6B~uUE^Yq)_S-;h*HnCcL zm2kdnM%MF$PjrU3x|A%!A~R(5-sZ%JpN@=|SQ+&_s@>O=zK-~6XX2HYvECV0K#5+YGl{BpwhU`s z>oeeG-jBXNgVBchYO3q~e|%OA3Kta`;v2zcb&4 g2b!7d;9u0-2<~{TPcz42PHFu-bG$ri-Drt_0DJ13<^TWy diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.lst deleted file mode 100755 index 67d24f3..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.lst +++ /dev/null @@ -1,532 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "cyutils.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.CySetReg24,"ax",%progbits - 19 .align 1 - 20 .global CySetReg24 - 21 .thumb - 22 .thumb_func - 23 .type CySetReg24, %function - 24 CySetReg24: - 25 .LFB0: - 26 .file 1 ".\\Generated_Source\\PSoC5\\cyutils.c" - 1:.\Generated_Source\PSoC5/cyutils.c **** /******************************************************************************* - 2:.\Generated_Source\PSoC5/cyutils.c **** * FILENAME: cyutils.c - 3:.\Generated_Source\PSoC5/cyutils.c **** * Version 4.0 - 4:.\Generated_Source\PSoC5/cyutils.c **** * - 5:.\Generated_Source\PSoC5/cyutils.c **** * Description: - 6:.\Generated_Source\PSoC5/cyutils.c **** * CyUtils provides function to handle 24-bit value writes. - 7:.\Generated_Source\PSoC5/cyutils.c **** * - 8:.\Generated_Source\PSoC5/cyutils.c **** ******************************************************************************** - 9:.\Generated_Source\PSoC5/cyutils.c **** * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. - 10:.\Generated_Source\PSoC5/cyutils.c **** * You may use this file only in accordance with the license, terms, conditions, - 11:.\Generated_Source\PSoC5/cyutils.c **** * disclaimers, and limitations in the end user license agreement accompanying - 12:.\Generated_Source\PSoC5/cyutils.c **** * the software package with which this file was provided. - 13:.\Generated_Source\PSoC5/cyutils.c **** *******************************************************************************/ - 14:.\Generated_Source\PSoC5/cyutils.c **** - 15:.\Generated_Source\PSoC5/cyutils.c **** #include "cytypes.h" - 16:.\Generated_Source\PSoC5/cyutils.c **** - 17:.\Generated_Source\PSoC5/cyutils.c **** #if (!CY_PSOC3) - 18:.\Generated_Source\PSoC5/cyutils.c **** - 19:.\Generated_Source\PSoC5/cyutils.c **** /*************************************************************************** - 20:.\Generated_Source\PSoC5/cyutils.c **** * Function Name: CySetReg24 - 21:.\Generated_Source\PSoC5/cyutils.c **** **************************************************************************** - 22:.\Generated_Source\PSoC5/cyutils.c **** * - 23:.\Generated_Source\PSoC5/cyutils.c **** * Summary: - 24:.\Generated_Source\PSoC5/cyutils.c **** * Writes the 24-bit value to the specified register. - 25:.\Generated_Source\PSoC5/cyutils.c **** * - 26:.\Generated_Source\PSoC5/cyutils.c **** * Parameters: - 27:.\Generated_Source\PSoC5/cyutils.c **** * addr : adress where data must be written - 28:.\Generated_Source\PSoC5/cyutils.c **** * value: data that must be written - 29:.\Generated_Source\PSoC5/cyutils.c **** * - 30:.\Generated_Source\PSoC5/cyutils.c **** * Return: - 31:.\Generated_Source\PSoC5/cyutils.c **** * None - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 2 - - - 32:.\Generated_Source\PSoC5/cyutils.c **** * - 33:.\Generated_Source\PSoC5/cyutils.c **** * Reentrant: - 34:.\Generated_Source\PSoC5/cyutils.c **** * No - 35:.\Generated_Source\PSoC5/cyutils.c **** * - 36:.\Generated_Source\PSoC5/cyutils.c **** ***************************************************************************/ - 37:.\Generated_Source\PSoC5/cyutils.c **** void CySetReg24(uint32 volatile * addr, uint32 value) - 38:.\Generated_Source\PSoC5/cyutils.c **** { - 27 .loc 1 38 0 - 28 .cfi_startproc - 29 @ args = 0, pretend = 0, frame = 0 - 30 @ frame_needed = 0, uses_anonymous_args = 0 - 31 @ link register save eliminated. - 32 .LVL0: - 39:.\Generated_Source\PSoC5/cyutils.c **** uint8 volatile *tmpAddr; - 40:.\Generated_Source\PSoC5/cyutils.c **** - 41:.\Generated_Source\PSoC5/cyutils.c **** tmpAddr = (uint8 volatile *) addr; - 42:.\Generated_Source\PSoC5/cyutils.c **** - 43:.\Generated_Source\PSoC5/cyutils.c **** tmpAddr[0u] = (uint8) value; - 33 .loc 1 43 0 - 34 0000 CBB2 uxtb r3, r1 - 44:.\Generated_Source\PSoC5/cyutils.c **** tmpAddr[1u] = (uint8) (value >> 8u); - 35 .loc 1 44 0 - 36 0002 C1F30722 ubfx r2, r1, #8, #8 - 45:.\Generated_Source\PSoC5/cyutils.c **** tmpAddr[2u] = (uint8) (value >> 16u); - 37 .loc 1 45 0 - 38 0006 C1F30741 ubfx r1, r1, #16, #8 - 39 .LVL1: - 43:.\Generated_Source\PSoC5/cyutils.c **** tmpAddr[0u] = (uint8) value; - 40 .loc 1 43 0 - 41 000a 0370 strb r3, [r0, #0] - 44:.\Generated_Source\PSoC5/cyutils.c **** tmpAddr[1u] = (uint8) (value >> 8u); - 42 .loc 1 44 0 - 43 000c 4270 strb r2, [r0, #1] - 44 .loc 1 45 0 - 45 000e 8170 strb r1, [r0, #2] - 46 0010 7047 bx lr - 47 .cfi_endproc - 48 .LFE0: - 49 .size CySetReg24, .-CySetReg24 - 50 .text - 51 .Letext0: - 52 .file 2 ".\\Generated_Source\\PSoC5\\cytypes.h" - 53 .section .debug_info,"",%progbits - 54 .Ldebug_info0: - 55 0000 F0000000 .4byte 0xf0 - 56 0004 0200 .2byte 0x2 - 57 0006 00000000 .4byte .Ldebug_abbrev0 - 58 000a 04 .byte 0x4 - 59 000b 01 .uleb128 0x1 - 60 000c 00010000 .4byte .LASF16 - 61 0010 01 .byte 0x1 - 62 0011 06000000 .4byte .LASF17 - 63 0015 67000000 .4byte .LASF18 - 64 0019 00000000 .4byte .Ldebug_ranges0+0 - 65 001d 00000000 .4byte 0 - 66 0021 00000000 .4byte 0 - 67 0025 00000000 .4byte .Ldebug_line0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 3 - - - 68 0029 02 .uleb128 0x2 - 69 002a 01 .byte 0x1 - 70 002b 06 .byte 0x6 - 71 002c 52010000 .4byte .LASF0 - 72 0030 02 .uleb128 0x2 - 73 0031 01 .byte 0x1 - 74 0032 08 .byte 0x8 - 75 0033 3F000000 .4byte .LASF1 - 76 0037 02 .uleb128 0x2 - 77 0038 02 .byte 0x2 - 78 0039 05 .byte 0x5 - 79 003a F0000000 .4byte .LASF2 - 80 003e 02 .uleb128 0x2 - 81 003f 02 .byte 0x2 - 82 0040 07 .byte 0x7 - 83 0041 98000000 .4byte .LASF3 - 84 0045 02 .uleb128 0x2 - 85 0046 04 .byte 0x4 - 86 0047 05 .byte 0x5 - 87 0048 49010000 .4byte .LASF4 - 88 004c 02 .uleb128 0x2 - 89 004d 04 .byte 0x4 - 90 004e 07 .byte 0x7 - 91 004f 55000000 .4byte .LASF5 - 92 0053 02 .uleb128 0x2 - 93 0054 08 .byte 0x8 - 94 0055 05 .byte 0x5 - 95 0056 DD000000 .4byte .LASF6 - 96 005a 02 .uleb128 0x2 - 97 005b 08 .byte 0x8 - 98 005c 07 .byte 0x7 - 99 005d C6000000 .4byte .LASF7 - 100 0061 03 .uleb128 0x3 - 101 0062 04 .byte 0x4 - 102 0063 05 .byte 0x5 - 103 0064 696E7400 .ascii "int\000" - 104 0068 02 .uleb128 0x2 - 105 0069 04 .byte 0x4 - 106 006a 07 .byte 0x7 - 107 006b B9000000 .4byte .LASF8 - 108 006f 04 .uleb128 0x4 - 109 0070 FA000000 .4byte .LASF9 - 110 0074 02 .byte 0x2 - 111 0075 5B .byte 0x5b - 112 0076 30000000 .4byte 0x30 - 113 007a 04 .uleb128 0x4 - 114 007b B2000000 .4byte .LASF10 - 115 007f 02 .byte 0x2 - 116 0080 5D .byte 0x5d - 117 0081 4C000000 .4byte 0x4c - 118 0085 02 .uleb128 0x2 - 119 0086 04 .byte 0x4 - 120 0087 04 .byte 0x4 - 121 0088 39000000 .4byte .LASF11 - 122 008c 02 .uleb128 0x2 - 123 008d 08 .byte 0x8 - 124 008e 04 .byte 0x4 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 4 - - - 125 008f AB000000 .4byte .LASF12 - 126 0093 02 .uleb128 0x2 - 127 0094 01 .byte 0x1 - 128 0095 08 .byte 0x8 - 129 0096 EB000000 .4byte .LASF13 - 130 009a 05 .uleb128 0x5 - 131 009b 6F000000 .4byte 0x6f - 132 009f 05 .uleb128 0x5 - 133 00a0 7A000000 .4byte 0x7a - 134 00a4 06 .uleb128 0x6 - 135 00a5 01 .byte 0x1 - 136 00a6 29000000 .4byte .LASF19 - 137 00aa 01 .byte 0x1 - 138 00ab 25 .byte 0x25 - 139 00ac 01 .byte 0x1 - 140 00ad 00000000 .4byte .LFB0 - 141 00b1 12000000 .4byte .LFE0 - 142 00b5 02 .byte 0x2 - 143 00b6 7D .byte 0x7d - 144 00b7 00 .sleb128 0 - 145 00b8 01 .byte 0x1 - 146 00b9 E7000000 .4byte 0xe7 - 147 00bd 07 .uleb128 0x7 - 148 00be 34000000 .4byte .LASF14 - 149 00c2 01 .byte 0x1 - 150 00c3 25 .byte 0x25 - 151 00c4 E7000000 .4byte 0xe7 - 152 00c8 01 .byte 0x1 - 153 00c9 50 .byte 0x50 - 154 00ca 08 .uleb128 0x8 - 155 00cb 00000000 .4byte .LASF15 - 156 00cf 01 .byte 0x1 - 157 00d0 25 .byte 0x25 - 158 00d1 7A000000 .4byte 0x7a - 159 00d5 00000000 .4byte .LLST0 - 160 00d9 09 .uleb128 0x9 - 161 00da 4D000000 .4byte .LASF20 - 162 00de 01 .byte 0x1 - 163 00df 27 .byte 0x27 - 164 00e0 ED000000 .4byte 0xed - 165 00e4 01 .byte 0x1 - 166 00e5 50 .byte 0x50 - 167 00e6 00 .byte 0 - 168 00e7 0A .uleb128 0xa - 169 00e8 04 .byte 0x4 - 170 00e9 9F000000 .4byte 0x9f - 171 00ed 0A .uleb128 0xa - 172 00ee 04 .byte 0x4 - 173 00ef 9A000000 .4byte 0x9a - 174 00f3 00 .byte 0 - 175 .section .debug_abbrev,"",%progbits - 176 .Ldebug_abbrev0: - 177 0000 01 .uleb128 0x1 - 178 0001 11 .uleb128 0x11 - 179 0002 01 .byte 0x1 - 180 0003 25 .uleb128 0x25 - 181 0004 0E .uleb128 0xe - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 5 - - - 182 0005 13 .uleb128 0x13 - 183 0006 0B .uleb128 0xb - 184 0007 03 .uleb128 0x3 - 185 0008 0E .uleb128 0xe - 186 0009 1B .uleb128 0x1b - 187 000a 0E .uleb128 0xe - 188 000b 55 .uleb128 0x55 - 189 000c 06 .uleb128 0x6 - 190 000d 11 .uleb128 0x11 - 191 000e 01 .uleb128 0x1 - 192 000f 52 .uleb128 0x52 - 193 0010 01 .uleb128 0x1 - 194 0011 10 .uleb128 0x10 - 195 0012 06 .uleb128 0x6 - 196 0013 00 .byte 0 - 197 0014 00 .byte 0 - 198 0015 02 .uleb128 0x2 - 199 0016 24 .uleb128 0x24 - 200 0017 00 .byte 0 - 201 0018 0B .uleb128 0xb - 202 0019 0B .uleb128 0xb - 203 001a 3E .uleb128 0x3e - 204 001b 0B .uleb128 0xb - 205 001c 03 .uleb128 0x3 - 206 001d 0E .uleb128 0xe - 207 001e 00 .byte 0 - 208 001f 00 .byte 0 - 209 0020 03 .uleb128 0x3 - 210 0021 24 .uleb128 0x24 - 211 0022 00 .byte 0 - 212 0023 0B .uleb128 0xb - 213 0024 0B .uleb128 0xb - 214 0025 3E .uleb128 0x3e - 215 0026 0B .uleb128 0xb - 216 0027 03 .uleb128 0x3 - 217 0028 08 .uleb128 0x8 - 218 0029 00 .byte 0 - 219 002a 00 .byte 0 - 220 002b 04 .uleb128 0x4 - 221 002c 16 .uleb128 0x16 - 222 002d 00 .byte 0 - 223 002e 03 .uleb128 0x3 - 224 002f 0E .uleb128 0xe - 225 0030 3A .uleb128 0x3a - 226 0031 0B .uleb128 0xb - 227 0032 3B .uleb128 0x3b - 228 0033 0B .uleb128 0xb - 229 0034 49 .uleb128 0x49 - 230 0035 13 .uleb128 0x13 - 231 0036 00 .byte 0 - 232 0037 00 .byte 0 - 233 0038 05 .uleb128 0x5 - 234 0039 35 .uleb128 0x35 - 235 003a 00 .byte 0 - 236 003b 49 .uleb128 0x49 - 237 003c 13 .uleb128 0x13 - 238 003d 00 .byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 6 - - - 239 003e 00 .byte 0 - 240 003f 06 .uleb128 0x6 - 241 0040 2E .uleb128 0x2e - 242 0041 01 .byte 0x1 - 243 0042 3F .uleb128 0x3f - 244 0043 0C .uleb128 0xc - 245 0044 03 .uleb128 0x3 - 246 0045 0E .uleb128 0xe - 247 0046 3A .uleb128 0x3a - 248 0047 0B .uleb128 0xb - 249 0048 3B .uleb128 0x3b - 250 0049 0B .uleb128 0xb - 251 004a 27 .uleb128 0x27 - 252 004b 0C .uleb128 0xc - 253 004c 11 .uleb128 0x11 - 254 004d 01 .uleb128 0x1 - 255 004e 12 .uleb128 0x12 - 256 004f 01 .uleb128 0x1 - 257 0050 40 .uleb128 0x40 - 258 0051 0A .uleb128 0xa - 259 0052 9742 .uleb128 0x2117 - 260 0054 0C .uleb128 0xc - 261 0055 01 .uleb128 0x1 - 262 0056 13 .uleb128 0x13 - 263 0057 00 .byte 0 - 264 0058 00 .byte 0 - 265 0059 07 .uleb128 0x7 - 266 005a 05 .uleb128 0x5 - 267 005b 00 .byte 0 - 268 005c 03 .uleb128 0x3 - 269 005d 0E .uleb128 0xe - 270 005e 3A .uleb128 0x3a - 271 005f 0B .uleb128 0xb - 272 0060 3B .uleb128 0x3b - 273 0061 0B .uleb128 0xb - 274 0062 49 .uleb128 0x49 - 275 0063 13 .uleb128 0x13 - 276 0064 02 .uleb128 0x2 - 277 0065 0A .uleb128 0xa - 278 0066 00 .byte 0 - 279 0067 00 .byte 0 - 280 0068 08 .uleb128 0x8 - 281 0069 05 .uleb128 0x5 - 282 006a 00 .byte 0 - 283 006b 03 .uleb128 0x3 - 284 006c 0E .uleb128 0xe - 285 006d 3A .uleb128 0x3a - 286 006e 0B .uleb128 0xb - 287 006f 3B .uleb128 0x3b - 288 0070 0B .uleb128 0xb - 289 0071 49 .uleb128 0x49 - 290 0072 13 .uleb128 0x13 - 291 0073 02 .uleb128 0x2 - 292 0074 06 .uleb128 0x6 - 293 0075 00 .byte 0 - 294 0076 00 .byte 0 - 295 0077 09 .uleb128 0x9 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 7 - - - 296 0078 34 .uleb128 0x34 - 297 0079 00 .byte 0 - 298 007a 03 .uleb128 0x3 - 299 007b 0E .uleb128 0xe - 300 007c 3A .uleb128 0x3a - 301 007d 0B .uleb128 0xb - 302 007e 3B .uleb128 0x3b - 303 007f 0B .uleb128 0xb - 304 0080 49 .uleb128 0x49 - 305 0081 13 .uleb128 0x13 - 306 0082 02 .uleb128 0x2 - 307 0083 0A .uleb128 0xa - 308 0084 00 .byte 0 - 309 0085 00 .byte 0 - 310 0086 0A .uleb128 0xa - 311 0087 0F .uleb128 0xf - 312 0088 00 .byte 0 - 313 0089 0B .uleb128 0xb - 314 008a 0B .uleb128 0xb - 315 008b 49 .uleb128 0x49 - 316 008c 13 .uleb128 0x13 - 317 008d 00 .byte 0 - 318 008e 00 .byte 0 - 319 008f 00 .byte 0 - 320 .section .debug_loc,"",%progbits - 321 .Ldebug_loc0: - 322 .LLST0: - 323 0000 00000000 .4byte .LVL0 - 324 0004 0A000000 .4byte .LVL1 - 325 0008 0100 .2byte 0x1 - 326 000a 51 .byte 0x51 - 327 000b 0A000000 .4byte .LVL1 - 328 000f 12000000 .4byte .LFE0 - 329 0013 0400 .2byte 0x4 - 330 0015 F3 .byte 0xf3 - 331 0016 01 .uleb128 0x1 - 332 0017 51 .byte 0x51 - 333 0018 9F .byte 0x9f - 334 0019 00000000 .4byte 0 - 335 001d 00000000 .4byte 0 - 336 .section .debug_aranges,"",%progbits - 337 0000 1C000000 .4byte 0x1c - 338 0004 0200 .2byte 0x2 - 339 0006 00000000 .4byte .Ldebug_info0 - 340 000a 04 .byte 0x4 - 341 000b 00 .byte 0 - 342 000c 0000 .2byte 0 - 343 000e 0000 .2byte 0 - 344 0010 00000000 .4byte .LFB0 - 345 0014 12000000 .4byte .LFE0-.LFB0 - 346 0018 00000000 .4byte 0 - 347 001c 00000000 .4byte 0 - 348 .section .debug_ranges,"",%progbits - 349 .Ldebug_ranges0: - 350 0000 00000000 .4byte .LFB0 - 351 0004 12000000 .4byte .LFE0 - 352 0008 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 8 - - - 353 000c 00000000 .4byte 0 - 354 .section .debug_line,"",%progbits - 355 .Ldebug_line0: - 356 0000 61000000 .section .debug_str,"MS",%progbits,1 - 356 02004600 - 356 00000201 - 356 FB0E0D00 - 356 01010101 - 357 .LASF15: - 358 0000 76616C75 .ascii "value\000" - 358 6500 - 359 .LASF17: - 360 0006 2E5C4765 .ascii ".\\Generated_Source\\PSoC5\\cyutils.c\000" - 360 6E657261 - 360 7465645F - 360 536F7572 - 360 63655C50 - 361 .LASF19: - 362 0029 43795365 .ascii "CySetReg24\000" - 362 74526567 - 362 323400 - 363 .LASF14: - 364 0034 61646472 .ascii "addr\000" - 364 00 - 365 .LASF11: - 366 0039 666C6F61 .ascii "float\000" - 366 7400 - 367 .LASF1: - 368 003f 756E7369 .ascii "unsigned char\000" - 368 676E6564 - 368 20636861 - 368 7200 - 369 .LASF20: - 370 004d 746D7041 .ascii "tmpAddr\000" - 370 64647200 - 371 .LASF5: - 372 0055 6C6F6E67 .ascii "long unsigned int\000" - 372 20756E73 - 372 69676E65 - 372 6420696E - 372 7400 - 373 .LASF18: - 374 0067 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 374 43534932 - 374 53445C73 - 374 6F667477 - 374 6172655C - 375 0096 6E00 .ascii "n\000" - 376 .LASF3: - 377 0098 73686F72 .ascii "short unsigned int\000" - 377 7420756E - 377 7369676E - 377 65642069 - 377 6E7400 - 378 .LASF12: - 379 00ab 646F7562 .ascii "double\000" - 379 6C6500 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\cckTs2oT.s page 9 - - - 380 .LASF10: - 381 00b2 75696E74 .ascii "uint32\000" - 381 333200 - 382 .LASF8: - 383 00b9 756E7369 .ascii "unsigned int\000" - 383 676E6564 - 383 20696E74 - 383 00 - 384 .LASF7: - 385 00c6 6C6F6E67 .ascii "long long unsigned int\000" - 385 206C6F6E - 385 6720756E - 385 7369676E - 385 65642069 - 386 .LASF6: - 387 00dd 6C6F6E67 .ascii "long long int\000" - 387 206C6F6E - 387 6720696E - 387 7400 - 388 .LASF13: - 389 00eb 63686172 .ascii "char\000" - 389 00 - 390 .LASF2: - 391 00f0 73686F72 .ascii "short int\000" - 391 7420696E - 391 7400 - 392 .LASF9: - 393 00fa 75696E74 .ascii "uint8\000" - 393 3800 - 394 .LASF16: - 395 0100 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 395 4320342E - 395 372E3320 - 395 32303133 - 395 30333132 - 396 0133 616E6368 .ascii "anch revision 196615]\000" - 396 20726576 - 396 6973696F - 396 6E203139 - 396 36363135 - 397 .LASF4: - 398 0149 6C6F6E67 .ascii "long int\000" - 398 20696E74 - 398 00 - 399 .LASF0: - 400 0152 7369676E .ascii "signed char\000" - 400 65642063 - 400 68617200 - 401 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/cyutils.o deleted file mode 100755 index 2a296c14c336e20f98c85a26e95a318de77c1dcf..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2996 zcmb_eO=uid9Di?SHk)MAv`N3M$fPthg?5^+enqq z{yVd;ojQA3N-2y;F(lfS5SMc*k{eerBzB4I;?~Wt@8tL5nY0^Ijcbj@^dE>?D#MYS zE<0c>E62vck{xr1Te9;c0+y9iGp+plw4B@-#+>{-tVCh7NfEqa0MH>xXJx74kP=o@bMTROM_ZMi`tx z>6*bH_y5juR&+ZbLFslrz$j#&9PHg%uzUCP&Uf_5Ik^Rgw)Tla;c+;zWvznI*&*!S ziNd3WGh4BlBZAQ3$&)=T@BW@X*)N~yes8KrB9hOoXItGubY@Jf&^5jx+PxVIl1~ZJ zQU3D;p3o6@Fko4ryyVxKq4+Pp zg*IJrtrVtn;qvIX@Pi;0OSQ;PMYEn%m+N8RR#yC2q^pfd#%fW0*2X* zMoUjFB+*j(vLA=*j``Bm;#3r+APmCTtE>e{T_h_}oNnX@qGq`kiYEBRM%ycsUM+b4 zs%*u zDc#vPs)R`r#mRyHV;7U7xMx4~%T*zVc;!WuF}!?eW=wQ+=V!XCerKE9E_d3yuBBEf;u1U* z+4Ivhu9lnWMwX@6Uk%Oi9*BF8!5>YUciE;37U+R4eG%^8#w~YZb ze2W>K;qMU`prXa(U4WfkccCDJ3m@0zdS=}^bTbF4xDCUlqQ%5sfSu*L0=_Nqk&mxk z!*>n3nFCc6P%!2hF|n&~Wcl9A@bPzH_}+nT=8$6#__AGOVs9aq<@*qPJSX>ukJ36H zzY3hgZz$z;@I7xxU{mGuiAIz6D;nn|_>7pmFW^9^Vf^Q?@iAin4fS^!o#E@qbE#Gt7I~v8wAGEbUAF4X ztj*49i>*2%Yj05=)}tk?cw207ugzO%i;arX!OQ-~(Nr0s1)OxmUGe*q6| BVxRy3 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/library.deps b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/library.deps deleted file mode 100755 index 68e1bc0..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/library.deps +++ /dev/null @@ -1 +0,0 @@ -W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a : .\CortexM3\ARM_GCC_473\Release\cyfitter_cfg.o .\CortexM3\ARM_GCC_473\Release\USBFS.o .\CortexM3\ARM_GCC_473\Release\USBFS_audio.o .\CortexM3\ARM_GCC_473\Release\USBFS_boot.o .\CortexM3\ARM_GCC_473\Release\USBFS_cdc.o .\CortexM3\ARM_GCC_473\Release\USBFS_cls.o .\CortexM3\ARM_GCC_473\Release\USBFS_descr.o .\CortexM3\ARM_GCC_473\Release\USBFS_drv.o .\CortexM3\ARM_GCC_473\Release\USBFS_episr.o .\CortexM3\ARM_GCC_473\Release\USBFS_hid.o .\CortexM3\ARM_GCC_473\Release\USBFS_pm.o .\CortexM3\ARM_GCC_473\Release\USBFS_std.o .\CortexM3\ARM_GCC_473\Release\USBFS_vnd.o .\CortexM3\ARM_GCC_473\Release\USBFS_midi.o .\CortexM3\ARM_GCC_473\Release\BL.o .\CortexM3\ARM_GCC_473\Release\USBFS_Dm.o .\CortexM3\ARM_GCC_473\Release\USBFS_Dp.o .\CortexM3\ARM_GCC_473\Release\CyBootAsmGnu.o .\CortexM3\ARM_GCC_473\Release\CyDmac.o .\CortexM3\ARM_GCC_473\Release\CyFlash.o .\CortexM3\ARM_GCC_473\Release\CyLib.o .\CortexM3\ARM_GCC_473\Release\cyPm.o .\CortexM3\ARM_GCC_473\Release\CySpc.o .\CortexM3\ARM_GCC_473\Release\cyutils.o .\CortexM3\ARM_GCC_473\Release\SD_PULLUP.o diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.lst b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.lst deleted file mode 100755 index 090814a..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.lst +++ /dev/null @@ -1,669 +0,0 @@ -ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 1 - - - 1 .syntax unified - 2 .cpu cortex-m3 - 3 .fpu softvfp - 4 .eabi_attribute 20, 1 - 5 .eabi_attribute 21, 1 - 6 .eabi_attribute 23, 3 - 7 .eabi_attribute 24, 1 - 8 .eabi_attribute 25, 1 - 9 .eabi_attribute 26, 1 - 10 .eabi_attribute 30, 4 - 11 .eabi_attribute 34, 1 - 12 .eabi_attribute 18, 4 - 13 .thumb - 14 .file "main.c" - 15 .text - 16 .Ltext0: - 17 .cfi_sections .debug_frame - 18 .section .text.startup.main,"ax",%progbits - 19 .align 1 - 20 .global main - 21 .thumb - 22 .thumb_func - 23 .type main, %function - 24 main: - 25 .LFB57: - 26 .file 1 ".\\main.c" - 1:.\main.c **** // Copyright (C) 2013 Michael McMaster - 2:.\main.c **** // - 3:.\main.c **** // This file is part of SCSI2SD. - 4:.\main.c **** // - 5:.\main.c **** // SCSI2SD is free software: you can redistribute it and/or modify - 6:.\main.c **** // it under the terms of the GNU General Public License as published by - 7:.\main.c **** // the Free Software Foundation, either version 3 of the License, or - 8:.\main.c **** // (at your option) any later version. - 9:.\main.c **** // - 10:.\main.c **** // SCSI2SD is distributed in the hope that it will be useful, - 11:.\main.c **** // but WITHOUT ANY WARRANTY; without even the implied warranty of - 12:.\main.c **** // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - 13:.\main.c **** // GNU General Public License for more details. - 14:.\main.c **** // - 15:.\main.c **** // You should have received a copy of the GNU General Public License - 16:.\main.c **** // along with SCSI2SD. If not, see . - 17:.\main.c **** #include - 18:.\main.c **** - 19:.\main.c **** static void resetSCSI() - 20:.\main.c **** { - 21:.\main.c **** CyPins_ClearPin(SCSI_Out_IO_raw); - 22:.\main.c **** CyPins_ClearPin(SCSI_Out_ATN); - 23:.\main.c **** CyPins_ClearPin(SCSI_Out_BSY); - 24:.\main.c **** CyPins_ClearPin(SCSI_Out_ACK); - 25:.\main.c **** CyPins_ClearPin(SCSI_Out_RST); - 26:.\main.c **** CyPins_ClearPin(SCSI_Out_SEL); - 27:.\main.c **** CyPins_ClearPin(SCSI_Out_REQ); - 28:.\main.c **** CyPins_ClearPin(SCSI_Out_MSG); - 29:.\main.c **** CyPins_ClearPin(SCSI_Out_CD); - 30:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB0); - 31:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB1); - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 2 - - - 32:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB2); - 33:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB3); - 34:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB4); - 35:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB5); - 36:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB6); - 37:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB7); - 38:.\main.c **** CyPins_ClearPin(SCSI_Out_DBP_raw); - 39:.\main.c **** } - 40:.\main.c **** - 41:.\main.c **** void main() - 42:.\main.c **** { - 27 .loc 1 42 0 - 28 .cfi_startproc - 29 @ Volatile: function does not return. - 30 @ args = 0, pretend = 0, frame = 0 - 31 @ frame_needed = 0, uses_anonymous_args = 0 - 32 0000 08B5 push {r3, lr} - 33 .LCFI0: - 34 .cfi_def_cfa_offset 8 - 35 .cfi_offset 3, -8 - 36 .cfi_offset 14, -4 - 37 .LBB4: - 38 .LBB5: - 21:.\main.c **** CyPins_ClearPin(SCSI_Out_IO_raw); - 39 .loc 1 21 0 - 40 0002 364B ldr r3, .L4 - 41 0004 1A78 ldrb r2, [r3, #0] @ zero_extendqisi2 - 42 0006 02F0FE00 and r0, r2, #254 - 43 000a 1870 strb r0, [r3, #0] - 22:.\main.c **** CyPins_ClearPin(SCSI_Out_ATN); - 44 .loc 1 22 0 - 45 000c 93F82210 ldrb r1, [r3, #34] @ zero_extendqisi2 - 46 0010 01F0FE02 and r2, r1, #254 - 47 0014 83F82220 strb r2, [r3, #34] - 23:.\main.c **** CyPins_ClearPin(SCSI_Out_BSY); - 48 .loc 1 23 0 - 49 0018 0733 adds r3, r3, #7 - 50 001a 1878 ldrb r0, [r3, #0] @ zero_extendqisi2 - 51 001c 00F0FE01 and r1, r0, #254 - 52 0020 1970 strb r1, [r3, #0] - 24:.\main.c **** CyPins_ClearPin(SCSI_Out_ACK); - 53 .loc 1 24 0 - 54 0022 13F8012C ldrb r2, [r3, #-1] @ zero_extendqisi2 - 55 0026 02F0FE00 and r0, r2, #254 - 56 002a 03F8010C strb r0, [r3, #-1] - 25:.\main.c **** CyPins_ClearPin(SCSI_Out_RST); - 57 .loc 1 25 0 - 58 002e 13F8021C ldrb r1, [r3, #-2] @ zero_extendqisi2 - 59 0032 01F0FE02 and r2, r1, #254 - 60 0036 03F8022C strb r2, [r3, #-2] - 26:.\main.c **** CyPins_ClearPin(SCSI_Out_SEL); - 61 .loc 1 26 0 - 62 003a 13F8040C ldrb r0, [r3, #-4] @ zero_extendqisi2 - 63 003e 00F0FE01 and r1, r0, #254 - 64 0042 03F8041C strb r1, [r3, #-4] - 27:.\main.c **** CyPins_ClearPin(SCSI_Out_REQ); - 65 .loc 1 27 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 3 - - - 66 0046 13F8062C ldrb r2, [r3, #-6] @ zero_extendqisi2 - 67 004a 02F0FE00 and r0, r2, #254 - 68 004e 03F8060C strb r0, [r3, #-6] - 28:.\main.c **** CyPins_ClearPin(SCSI_Out_MSG); - 69 .loc 1 28 0 - 70 0052 13F8031C ldrb r1, [r3, #-3] @ zero_extendqisi2 - 71 0056 01F0FE02 and r2, r1, #254 - 72 005a 03F8032C strb r2, [r3, #-3] - 29:.\main.c **** CyPins_ClearPin(SCSI_Out_CD); - 73 .loc 1 29 0 - 74 005e 13F8050C ldrb r0, [r3, #-5] @ zero_extendqisi2 - 75 0062 00F0FE01 and r1, r0, #254 - 76 0066 03F8051C strb r1, [r3, #-5] - 30:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB0); - 77 .loc 1 30 0 - 78 006a 93F82C20 ldrb r2, [r3, #44] @ zero_extendqisi2 - 79 006e 02F0FE00 and r0, r2, #254 - 80 0072 83F82C00 strb r0, [r3, #44] - 31:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB1); - 81 .loc 1 31 0 - 82 0076 2B33 adds r3, r3, #43 - 83 0078 1978 ldrb r1, [r3, #0] @ zero_extendqisi2 - 84 007a 01F0FE02 and r2, r1, #254 - 85 007e 1A70 strb r2, [r3, #0] - 32:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB2); - 86 .loc 1 32 0 - 87 0080 13F8010C ldrb r0, [r3, #-1] @ zero_extendqisi2 - 88 0084 00F0FE01 and r1, r0, #254 - 89 0088 03F8011C strb r1, [r3, #-1] - 33:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB3); - 90 .loc 1 33 0 - 91 008c 13F8022C ldrb r2, [r3, #-2] @ zero_extendqisi2 - 92 0090 02F0FE00 and r0, r2, #254 - 93 0094 03F8020C strb r0, [r3, #-2] - 34:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB4); - 94 .loc 1 34 0 - 95 0098 13F80B1C ldrb r1, [r3, #-11] @ zero_extendqisi2 - 96 009c 01F0FE02 and r2, r1, #254 - 97 00a0 03F80B2C strb r2, [r3, #-11] - 35:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB5); - 98 .loc 1 35 0 - 99 00a4 13F80C0C ldrb r0, [r3, #-12] @ zero_extendqisi2 - 100 00a8 00F0FE01 and r1, r0, #254 - 101 00ac 03F80C1C strb r1, [r3, #-12] - 36:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB6); - 102 .loc 1 36 0 - 103 00b0 13F80D2C ldrb r2, [r3, #-13] @ zero_extendqisi2 - 104 00b4 02F0FE00 and r0, r2, #254 - 105 00b8 03F80D0C strb r0, [r3, #-13] - 37:.\main.c **** CyPins_ClearPin(SCSI_Out_DBx_DB7); - 106 .loc 1 37 0 - 107 00bc 13F80E1C ldrb r1, [r3, #-14] @ zero_extendqisi2 - 108 00c0 01F0FE02 and r2, r1, #254 - 109 00c4 03F80E2C strb r2, [r3, #-14] - 38:.\main.c **** CyPins_ClearPin(SCSI_Out_DBP_raw); - 110 .loc 1 38 0 - 111 00c8 13F80F0C ldrb r0, [r3, #-15] @ zero_extendqisi2 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 4 - - - 112 00cc 00F0FE01 and r1, r0, #254 - 113 00d0 03F80F1C strb r1, [r3, #-15] - 114 .LBE5: - 115 .LBE4: - 43:.\main.c **** resetSCSI(); - 44:.\main.c **** - 45:.\main.c **** // The call to the bootloader should not return - 46:.\main.c **** CyBtldr_Start(); - 116 .loc 1 46 0 - 117 00d4 FFF7FEFF bl BL_Start - 118 .LVL0: - 119 .L2: - 120 00d8 FEE7 b .L2 - 121 .L5: - 122 00da 00BF .align 2 - 123 .L4: - 124 00dc 00500040 .word 1073762304 - 125 .cfi_endproc - 126 .LFE57: - 127 .size main, .-main - 128 .text - 129 .Letext0: - 130 .file 2 "c:\\program files (x86)\\cypress\\psoc creator\\3.0\\psoc creator\\import\\gnu_cs\\arm\\4 - 131 .file 3 "./Generated_Source/PSoC5/cytypes.h" - 132 .file 4 "./Generated_Source/PSoC5/core_cm3.h" - 133 .file 5 "./Generated_Source/PSoC5/BL.h" - 134 .section .debug_info,"",%progbits - 135 .Ldebug_info0: - 136 0000 05010000 .4byte 0x105 - 137 0004 0200 .2byte 0x2 - 138 0006 00000000 .4byte .Ldebug_abbrev0 - 139 000a 04 .byte 0x4 - 140 000b 01 .uleb128 0x1 - 141 000c 33000000 .4byte .LASF16 - 142 0010 01 .byte 0x1 - 143 0011 C3000000 .4byte .LASF17 - 144 0015 0F010000 .4byte .LASF18 - 145 0019 00000000 .4byte .Ldebug_ranges0+0 - 146 001d 00000000 .4byte 0 - 147 0021 00000000 .4byte 0 - 148 0025 00000000 .4byte .Ldebug_line0 - 149 0029 02 .uleb128 0x2 - 150 002a 01 .byte 0x1 - 151 002b 06 .byte 0x6 - 152 002c E9000000 .4byte .LASF0 - 153 0030 02 .uleb128 0x2 - 154 0031 01 .byte 0x1 - 155 0032 08 .byte 0x8 - 156 0033 AB000000 .4byte .LASF1 - 157 0037 02 .uleb128 0x2 - 158 0038 02 .byte 0x2 - 159 0039 05 .byte 0x5 - 160 003a 05010000 .4byte .LASF2 - 161 003e 02 .uleb128 0x2 - 162 003f 02 .byte 0x2 - 163 0040 07 .byte 0x7 - 164 0041 0E000000 .4byte .LASF3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 5 - - - 165 0045 03 .uleb128 0x3 - 166 0046 40010000 .4byte .LASF9 - 167 004a 02 .byte 0x2 - 168 004b 4F .byte 0x4f - 169 004c 50000000 .4byte 0x50 - 170 0050 02 .uleb128 0x2 - 171 0051 04 .byte 0x4 - 172 0052 05 .byte 0x5 - 173 0053 D3000000 .4byte .LASF4 - 174 0057 02 .uleb128 0x2 - 175 0058 04 .byte 0x4 - 176 0059 07 .byte 0x7 - 177 005a 82000000 .4byte .LASF5 - 178 005e 02 .uleb128 0x2 - 179 005f 08 .byte 0x8 - 180 0060 05 .byte 0x5 - 181 0061 00000000 .4byte .LASF6 - 182 0065 02 .uleb128 0x2 - 183 0066 08 .byte 0x8 - 184 0067 07 .byte 0x7 - 185 0068 94000000 .4byte .LASF7 - 186 006c 04 .uleb128 0x4 - 187 006d 04 .byte 0x4 - 188 006e 05 .byte 0x5 - 189 006f 696E7400 .ascii "int\000" - 190 0073 02 .uleb128 0x2 - 191 0074 04 .byte 0x4 - 192 0075 07 .byte 0x7 - 193 0076 21000000 .4byte .LASF8 - 194 007a 03 .uleb128 0x3 - 195 007b 7C000000 .4byte .LASF10 - 196 007f 03 .byte 0x3 - 197 0080 5B .byte 0x5b - 198 0081 30000000 .4byte 0x30 - 199 0085 02 .uleb128 0x2 - 200 0086 04 .byte 0x4 - 201 0087 04 .byte 0x4 - 202 0088 FF000000 .4byte .LASF11 - 203 008c 02 .uleb128 0x2 - 204 008d 08 .byte 0x8 - 205 008e 04 .byte 0x4 - 206 008f CC000000 .4byte .LASF12 - 207 0093 02 .uleb128 0x2 - 208 0094 01 .byte 0x1 - 209 0095 08 .byte 0x8 - 210 0096 B9000000 .4byte .LASF13 - 211 009a 03 .uleb128 0x3 - 212 009b BE000000 .4byte .LASF14 - 213 009f 03 .byte 0x3 - 214 00a0 F0 .byte 0xf0 - 215 00a1 A5000000 .4byte 0xa5 - 216 00a5 05 .uleb128 0x5 - 217 00a6 7A000000 .4byte 0x7a - 218 00aa 02 .uleb128 0x2 - 219 00ab 04 .byte 0x4 - 220 00ac 07 .byte 0x7 - 221 00ad 51010000 .4byte .LASF15 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 6 - - - 222 00b1 06 .uleb128 0x6 - 223 00b2 F5000000 .4byte .LASF19 - 224 00b6 01 .byte 0x1 - 225 00b7 13 .byte 0x13 - 226 00b8 01 .byte 0x1 - 227 00b9 07 .uleb128 0x7 - 228 00ba 01 .byte 0x1 - 229 00bb 2E000000 .4byte .LASF20 - 230 00bf 01 .byte 0x1 - 231 00c0 29 .byte 0x29 - 232 00c1 00000000 .4byte .LFB57 - 233 00c5 E0000000 .4byte .LFE57 - 234 00c9 00000000 .4byte .LLST0 - 235 00cd 01 .byte 0x1 - 236 00ce EB000000 .4byte 0xeb - 237 00d2 08 .uleb128 0x8 - 238 00d3 B1000000 .4byte 0xb1 - 239 00d7 02000000 .4byte .LBB4 - 240 00db D4000000 .4byte .LBE4 - 241 00df 01 .byte 0x1 - 242 00e0 2B .byte 0x2b - 243 00e1 09 .uleb128 0x9 - 244 00e2 D8000000 .4byte .LVL0 - 245 00e6 FE000000 .4byte 0xfe - 246 00ea 00 .byte 0 - 247 00eb 0A .uleb128 0xa - 248 00ec DC000000 .4byte .LASF21 - 249 00f0 04 .byte 0x4 - 250 00f1 1606 .2byte 0x616 - 251 00f3 F9000000 .4byte 0xf9 - 252 00f7 01 .byte 0x1 - 253 00f8 01 .byte 0x1 - 254 00f9 05 .uleb128 0x5 - 255 00fa 45000000 .4byte 0x45 - 256 00fe 0B .uleb128 0xb - 257 00ff 01 .byte 0x1 - 258 0100 48010000 .4byte .LASF22 - 259 0104 05 .byte 0x5 - 260 0105 93 .byte 0x93 - 261 0106 01 .byte 0x1 - 262 0107 01 .byte 0x1 - 263 0108 00 .byte 0 - 264 .section .debug_abbrev,"",%progbits - 265 .Ldebug_abbrev0: - 266 0000 01 .uleb128 0x1 - 267 0001 11 .uleb128 0x11 - 268 0002 01 .byte 0x1 - 269 0003 25 .uleb128 0x25 - 270 0004 0E .uleb128 0xe - 271 0005 13 .uleb128 0x13 - 272 0006 0B .uleb128 0xb - 273 0007 03 .uleb128 0x3 - 274 0008 0E .uleb128 0xe - 275 0009 1B .uleb128 0x1b - 276 000a 0E .uleb128 0xe - 277 000b 55 .uleb128 0x55 - 278 000c 06 .uleb128 0x6 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 7 - - - 279 000d 11 .uleb128 0x11 - 280 000e 01 .uleb128 0x1 - 281 000f 52 .uleb128 0x52 - 282 0010 01 .uleb128 0x1 - 283 0011 10 .uleb128 0x10 - 284 0012 06 .uleb128 0x6 - 285 0013 00 .byte 0 - 286 0014 00 .byte 0 - 287 0015 02 .uleb128 0x2 - 288 0016 24 .uleb128 0x24 - 289 0017 00 .byte 0 - 290 0018 0B .uleb128 0xb - 291 0019 0B .uleb128 0xb - 292 001a 3E .uleb128 0x3e - 293 001b 0B .uleb128 0xb - 294 001c 03 .uleb128 0x3 - 295 001d 0E .uleb128 0xe - 296 001e 00 .byte 0 - 297 001f 00 .byte 0 - 298 0020 03 .uleb128 0x3 - 299 0021 16 .uleb128 0x16 - 300 0022 00 .byte 0 - 301 0023 03 .uleb128 0x3 - 302 0024 0E .uleb128 0xe - 303 0025 3A .uleb128 0x3a - 304 0026 0B .uleb128 0xb - 305 0027 3B .uleb128 0x3b - 306 0028 0B .uleb128 0xb - 307 0029 49 .uleb128 0x49 - 308 002a 13 .uleb128 0x13 - 309 002b 00 .byte 0 - 310 002c 00 .byte 0 - 311 002d 04 .uleb128 0x4 - 312 002e 24 .uleb128 0x24 - 313 002f 00 .byte 0 - 314 0030 0B .uleb128 0xb - 315 0031 0B .uleb128 0xb - 316 0032 3E .uleb128 0x3e - 317 0033 0B .uleb128 0xb - 318 0034 03 .uleb128 0x3 - 319 0035 08 .uleb128 0x8 - 320 0036 00 .byte 0 - 321 0037 00 .byte 0 - 322 0038 05 .uleb128 0x5 - 323 0039 35 .uleb128 0x35 - 324 003a 00 .byte 0 - 325 003b 49 .uleb128 0x49 - 326 003c 13 .uleb128 0x13 - 327 003d 00 .byte 0 - 328 003e 00 .byte 0 - 329 003f 06 .uleb128 0x6 - 330 0040 2E .uleb128 0x2e - 331 0041 00 .byte 0 - 332 0042 03 .uleb128 0x3 - 333 0043 0E .uleb128 0xe - 334 0044 3A .uleb128 0x3a - 335 0045 0B .uleb128 0xb - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 8 - - - 336 0046 3B .uleb128 0x3b - 337 0047 0B .uleb128 0xb - 338 0048 20 .uleb128 0x20 - 339 0049 0B .uleb128 0xb - 340 004a 00 .byte 0 - 341 004b 00 .byte 0 - 342 004c 07 .uleb128 0x7 - 343 004d 2E .uleb128 0x2e - 344 004e 01 .byte 0x1 - 345 004f 3F .uleb128 0x3f - 346 0050 0C .uleb128 0xc - 347 0051 03 .uleb128 0x3 - 348 0052 0E .uleb128 0xe - 349 0053 3A .uleb128 0x3a - 350 0054 0B .uleb128 0xb - 351 0055 3B .uleb128 0x3b - 352 0056 0B .uleb128 0xb - 353 0057 11 .uleb128 0x11 - 354 0058 01 .uleb128 0x1 - 355 0059 12 .uleb128 0x12 - 356 005a 01 .uleb128 0x1 - 357 005b 40 .uleb128 0x40 - 358 005c 06 .uleb128 0x6 - 359 005d 9742 .uleb128 0x2117 - 360 005f 0C .uleb128 0xc - 361 0060 01 .uleb128 0x1 - 362 0061 13 .uleb128 0x13 - 363 0062 00 .byte 0 - 364 0063 00 .byte 0 - 365 0064 08 .uleb128 0x8 - 366 0065 1D .uleb128 0x1d - 367 0066 00 .byte 0 - 368 0067 31 .uleb128 0x31 - 369 0068 13 .uleb128 0x13 - 370 0069 11 .uleb128 0x11 - 371 006a 01 .uleb128 0x1 - 372 006b 12 .uleb128 0x12 - 373 006c 01 .uleb128 0x1 - 374 006d 58 .uleb128 0x58 - 375 006e 0B .uleb128 0xb - 376 006f 59 .uleb128 0x59 - 377 0070 0B .uleb128 0xb - 378 0071 00 .byte 0 - 379 0072 00 .byte 0 - 380 0073 09 .uleb128 0x9 - 381 0074 898201 .uleb128 0x4109 - 382 0077 00 .byte 0 - 383 0078 11 .uleb128 0x11 - 384 0079 01 .uleb128 0x1 - 385 007a 31 .uleb128 0x31 - 386 007b 13 .uleb128 0x13 - 387 007c 00 .byte 0 - 388 007d 00 .byte 0 - 389 007e 0A .uleb128 0xa - 390 007f 34 .uleb128 0x34 - 391 0080 00 .byte 0 - 392 0081 03 .uleb128 0x3 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 9 - - - 393 0082 0E .uleb128 0xe - 394 0083 3A .uleb128 0x3a - 395 0084 0B .uleb128 0xb - 396 0085 3B .uleb128 0x3b - 397 0086 05 .uleb128 0x5 - 398 0087 49 .uleb128 0x49 - 399 0088 13 .uleb128 0x13 - 400 0089 3F .uleb128 0x3f - 401 008a 0C .uleb128 0xc - 402 008b 3C .uleb128 0x3c - 403 008c 0C .uleb128 0xc - 404 008d 00 .byte 0 - 405 008e 00 .byte 0 - 406 008f 0B .uleb128 0xb - 407 0090 2E .uleb128 0x2e - 408 0091 00 .byte 0 - 409 0092 3F .uleb128 0x3f - 410 0093 0C .uleb128 0xc - 411 0094 03 .uleb128 0x3 - 412 0095 0E .uleb128 0xe - 413 0096 3A .uleb128 0x3a - 414 0097 0B .uleb128 0xb - 415 0098 3B .uleb128 0x3b - 416 0099 0B .uleb128 0xb - 417 009a 27 .uleb128 0x27 - 418 009b 0C .uleb128 0xc - 419 009c 3C .uleb128 0x3c - 420 009d 0C .uleb128 0xc - 421 009e 00 .byte 0 - 422 009f 00 .byte 0 - 423 00a0 00 .byte 0 - 424 .section .debug_loc,"",%progbits - 425 .Ldebug_loc0: - 426 .LLST0: - 427 0000 00000000 .4byte .LFB57 - 428 0004 02000000 .4byte .LCFI0 - 429 0008 0200 .2byte 0x2 - 430 000a 7D .byte 0x7d - 431 000b 00 .sleb128 0 - 432 000c 02000000 .4byte .LCFI0 - 433 0010 E0000000 .4byte .LFE57 - 434 0014 0200 .2byte 0x2 - 435 0016 7D .byte 0x7d - 436 0017 08 .sleb128 8 - 437 0018 00000000 .4byte 0 - 438 001c 00000000 .4byte 0 - 439 .section .debug_aranges,"",%progbits - 440 0000 1C000000 .4byte 0x1c - 441 0004 0200 .2byte 0x2 - 442 0006 00000000 .4byte .Ldebug_info0 - 443 000a 04 .byte 0x4 - 444 000b 00 .byte 0 - 445 000c 0000 .2byte 0 - 446 000e 0000 .2byte 0 - 447 0010 00000000 .4byte .LFB57 - 448 0014 E0000000 .4byte .LFE57-.LFB57 - 449 0018 00000000 .4byte 0 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 10 - - - 450 001c 00000000 .4byte 0 - 451 .section .debug_ranges,"",%progbits - 452 .Ldebug_ranges0: - 453 0000 00000000 .4byte .LFB57 - 454 0004 E0000000 .4byte .LFE57 - 455 0008 00000000 .4byte 0 - 456 000c 00000000 .4byte 0 - 457 .section .debug_line,"",%progbits - 458 .Ldebug_line0: - 459 0000 2B010000 .section .debug_str,"MS",%progbits,1 - 459 02000101 - 459 00000201 - 459 FB0E0D00 - 459 01010101 - 460 .LASF6: - 461 0000 6C6F6E67 .ascii "long long int\000" - 461 206C6F6E - 461 6720696E - 461 7400 - 462 .LASF3: - 463 000e 73686F72 .ascii "short unsigned int\000" - 463 7420756E - 463 7369676E - 463 65642069 - 463 6E7400 - 464 .LASF8: - 465 0021 756E7369 .ascii "unsigned int\000" - 465 676E6564 - 465 20696E74 - 465 00 - 466 .LASF20: - 467 002e 6D61696E .ascii "main\000" - 467 00 - 468 .LASF16: - 469 0033 474E5520 .ascii "GNU C 4.7.3 20130312 (release) [ARM/embedded-4_7-br" - 469 4320342E - 469 372E3320 - 469 32303133 - 469 30333132 - 470 0066 616E6368 .ascii "anch revision 196615]\000" - 470 20726576 - 470 6973696F - 470 6E203139 - 470 36363135 - 471 .LASF10: - 472 007c 75696E74 .ascii "uint8\000" - 472 3800 - 473 .LASF5: - 474 0082 6C6F6E67 .ascii "long unsigned int\000" - 474 20756E73 - 474 69676E65 - 474 6420696E - 474 7400 - 475 .LASF7: - 476 0094 6C6F6E67 .ascii "long long unsigned int\000" - 476 206C6F6E - 476 6720756E - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 11 - - - 476 7369676E - 476 65642069 - 477 .LASF1: - 478 00ab 756E7369 .ascii "unsigned char\000" - 478 676E6564 - 478 20636861 - 478 7200 - 479 .LASF13: - 480 00b9 63686172 .ascii "char\000" - 480 00 - 481 .LASF14: - 482 00be 72656738 .ascii "reg8\000" - 482 00 - 483 .LASF17: - 484 00c3 2E5C6D61 .ascii ".\\main.c\000" - 484 696E2E63 - 484 00 - 485 .LASF12: - 486 00cc 646F7562 .ascii "double\000" - 486 6C6500 - 487 .LASF4: - 488 00d3 6C6F6E67 .ascii "long int\000" - 488 20696E74 - 488 00 - 489 .LASF21: - 490 00dc 49544D5F .ascii "ITM_RxBuffer\000" - 490 52784275 - 490 66666572 - 490 00 - 491 .LASF0: - 492 00e9 7369676E .ascii "signed char\000" - 492 65642063 - 492 68617200 - 493 .LASF19: - 494 00f5 72657365 .ascii "resetSCSI\000" - 494 74534353 - 494 4900 - 495 .LASF11: - 496 00ff 666C6F61 .ascii "float\000" - 496 7400 - 497 .LASF2: - 498 0105 73686F72 .ascii "short int\000" - 498 7420696E - 498 7400 - 499 .LASF18: - 500 010f 573A5C53 .ascii "W:\\SCSI2SD\\software\\SCSI2SD\\USB_Bootloader.cyds" - 500 43534932 - 500 53445C73 - 500 6F667477 - 500 6172655C - 501 013e 6E00 .ascii "n\000" - 502 .LASF9: - 503 0140 696E7433 .ascii "int32_t\000" - 503 325F7400 - 504 .LASF22: - 505 0148 424C5F53 .ascii "BL_Start\000" - 505 74617274 - ARM GAS C:\Users\MICHA_~1\AppData\Local\Temp\ccLNGxQg.s page 12 - - - 505 00 - 506 .LASF15: - 507 0151 73697A65 .ascii "sizetype\000" - 507 74797065 - 507 00 - 508 .ident "GCC: (GNU Tools for ARM Embedded Processors) 4.7.3 20130312 (release) [ARM/embedded-4_7-br diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.o b/software/SCSI2SD/USB_Bootloader.cydsn/CortexM3/ARM_GCC_473/Release/main.o deleted file mode 100755 index 90a111ee925efedddbd5409f4afbf4cde2637c6f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 3576 zcmb_eU2Gdw7QT1Je~BHpsY_`}KtokTq9)@eZc7P&X+kL#Ergm13P#p=JaMeGXUxnP z5-38V4+}5wP@ucom*s&cgaj+?1480QhzBHAS_vc&AQbTeX!oJ}u)+u_g%L?YRAL!_jyhozsR;gJIrPb4lAWD=hc@XXs3dY6Vv zuVG9+N$y1Yek_yvFLYkuX>O7-je%{_0O9|_ka-IOZRs=e>>v38u!W0_evKiqEA<4DR}%jOE?c_@1pX(P`+%h@=eLuB+|G(CBu za7XUe9PZ3yisDA$z}-gM(%92tdz-?38n+P1q_9a(L=KFbeJxVr_I^4u6apjvIX?zX zJQ}dMy-?}+UcDsMs-C<_& zxZ^s$6*~25+3WhYQ(P%~%ZC^juq+>(mW$4HVI>r{!3IGi^L_^z^Bs)2=!7x>KJ$SiNbs=3B14X86wI&7kSI z#@x+^56>NXly$*>go(w6RvFyWkh^c#YnIQ%;5&^YgA&!fZms1+gmmjC9ynD!y}s04 zU3GjWwemQGg7q2+_C`J_Wf!`SiVj-z;(ULl zhCz_{s0NC!9Jw(@axDt+sxp9zk7})S3crgygA^$$X2Bj>cPz@Ib;+;R4WX+!P}w*C zgRg^FobP?`ZHJHe@R!x+`y=!?-xl~NPl<}1ha=AS&ln%nKHs0At2xAx$3Yik4yC?~ zSe$PYBk{G!`Z9yVT7i?^ zQ~16ReA|JvW}NRF`joyLlqf!BD~$US>_7Cm))&3M`^cpa-3hH1UyP)=j`~QTWA#oH-(0f9|0nw{N10kI~;Z+hR2ob!2 z5L=?YqB!*-;ey1Y67P~&miVwlOX8Zu$0a@`@i~bvN_<7)UnIUE@oy5}k@x{2o}Z5- zQjcq+jD0TcuOxme@!y2FZz`NX>8H~t9#ID%)sJjZ9~`~1;TC?CpC=yV(P?Q&qTVO_ E7iru9+W-In diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index c15b7b6..361d24a 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -311,9 +311,9 @@ void cyfitter_cfg(void) static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; - /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { - 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + 0x3Eu, 0x00u, 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { @@ -420,7 +420,7 @@ void cyfitter_cfg(void) /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); - CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c index 00c7240..a4c9cf0 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c +++ 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b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt @@ -1,10 +1,10 @@ -Loading plugins phase: Elapsed time ==> 0s.500ms -Initializing data phase: Elapsed time ==> 3s.890ms +Loading plugins phase: Elapsed time ==> 0s.499ms +Initializing data phase: Elapsed time ==> 3s.703ms cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 7s.406ms +Elaboration phase: Elapsed time ==> 7s.531ms HDL generation phase: Elapsed time ==> 0s.109ms @@ -41,7 +41,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Sat Mar 22 22:32:47 2014 +Sun Mar 23 21:45:41 2014 ====================================================================== @@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Sat Mar 22 22:32:47 2014 +Sun Mar 23 21:45:41 2014 vpp: No errors. @@ -80,7 +80,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof ====================================================================== tovif V6.3 IR 41: High-level synthesis -Sat Mar 22 22:32:47 2014 +Sun Mar 23 21:45:42 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -104,7 +104,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Sat Mar 22 22:32:48 2014 +Sun Mar 23 21:45:42 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -204,10 +204,10 @@ CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\wa Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -Warp synthesis phase: Elapsed time ==> 1s.468ms +Warp synthesis phase: Elapsed time ==> 1s.454ms -cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Saturday, 22 March 2014 22:32:48 +cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Sunday, 23 March 2014 21:45:43 Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog @@ -951,7 +951,7 @@ Design Equations Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -989,7 +989,7 @@ Design Equations Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1027,7 +1027,7 @@ Design Equations Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1065,7 +1065,7 @@ Design Equations Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1103,7 +1103,7 @@ Design Equations Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1314,8 +1314,8 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 1 : 1 : 0.00% -Technology Mapping: Elapsed time ==> 0s.030ms -Tech mapping phase: Elapsed time ==> 0s.265ms +Technology Mapping: Elapsed time ==> 0s.031ms +Tech mapping phase: Elapsed time ==> 0s.281ms Initial Analog Placement Results: @@ -1345,7 +1345,7 @@ IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.109ms +Analog Placement phase: Elapsed time ==> 0s.156ms Analog Routing phase: Elapsed time ==> 0s.000ms @@ -1363,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 1s.000ms +Analog Code Generation phase: Elapsed time ==> 1s.187ms I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 1.2 sec. +I2076: Total run-time: 2.4 sec. @@ -1382,7 +1382,7 @@ PLD Packing: Elapsed time ==> 0s.000ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.093ms +Partitioning: Elapsed time ==> 0s.078ms Annealing: Elapsed time ==> 0s.000ms @@ -1825,7 +1825,7 @@ Pin : Name = SD_PULLUP(0) Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1864,7 +1864,7 @@ Pin : Name = SD_PULLUP(1) Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1903,7 +1903,7 @@ Pin : Name = SD_PULLUP(2) Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1942,7 +1942,7 @@ Pin : Name = SD_PULLUP(3) Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -1981,7 +1981,7 @@ Pin : Name = SD_PULLUP(4) Input Sync needed: True Output Sync needed: False SC shield enabled: False - POR State: INP_DIS_LO + POR State: ANY LCD Mode: COMMON Register Mode: RegComb CaSense Mode: NEITHER @@ -2664,32 +2664,32 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection -Digital component placer commit/Report: Elapsed time ==> 0s.014ms -Digital Placement phase: Elapsed time ==> 2s.172ms +Digital component placer commit/Report: Elapsed time ==> 0s.016ms +Digital Placement phase: Elapsed time ==> 3s.031ms Routing successful. -Digital Routing phase: Elapsed time ==> 3s.093ms +Digital Routing phase: Elapsed time ==> 3s.046ms -Bitstream and API generation phase: Elapsed time ==> 0s.702ms +Bitstream and API generation phase: Elapsed time ==> 0s.718ms -Bitstream verification phase: Elapsed time ==> 0s.140ms +Bitstream verification phase: Elapsed time ==> 0s.159ms Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.719ms +Static timing analysis phase: Elapsed time ==> 1s.074ms Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.406ms +Design database save phase: Elapsed time ==> 0s.374ms -cydsfit: Elapsed time ==> 8s.765ms +cydsfit: Elapsed time ==> 10s.140ms -Fitter phase: Elapsed time ==> 8s.859ms -API generation phase: Elapsed time ==> 3s.296ms -Dependency generation phase: Elapsed time ==> 0s.016ms -Cleanup phase: Elapsed time ==> 0s.047ms +Fitter phase: Elapsed time ==> 10s.233ms +API generation phase: Elapsed time ==> 4s.062ms +Dependency generation phase: Elapsed time ==> 0s.031ms +Cleanup phase: Elapsed time ==> 0s.046ms diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html index 83b2bc2..5617ccc 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html @@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className) Project : USB_Bootloader Build Time : - 03/22/14 22:32:57 + 03/23/14 21:45:52 Device : CY8C5267AXI-LP051 Temperature : diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL.c deleted file mode 100755 index ea1c5aa..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL.c +++ /dev/null @@ -1,1462 +0,0 @@ -/******************************************************************************* -* File Name: BL.c -* Version 1.20 -* -* Description: -* Provides an API for the Bootloader component. The API includes functions -* for starting boot loading operations, validating the application and -* jumping to the application. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "BL_PVT.h" - -#include "project.h" -#include - - -/******************************************************************************* -* The Checksum and SizeBytes are forcefully set in code. We then post process -* the hex file from the linker and inject their values then. When the hex file -* is loaded onto the device these two variables should have valid values. -* Because the compiler can do optimizations remove the constant -* accesses, these should not be accessed directly. Instead, the variables -* CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the -* proper values at runtime. -*******************************************************************************/ -#if defined(__ARMCC_VERSION) || defined (__GNUC__) - __attribute__((section (".bootloader"))) -#elif defined (__ICCARM__) - #pragma location=".bootloader" -#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ - -const uint8 CYCODE BL_Checksum = 0u; -const uint8 CYCODE *BL_ChecksumAccess = (const uint8 CYCODE *)(&BL_Checksum); - -#if defined(__ARMCC_VERSION) || defined (__GNUC__) - __attribute__((section (".bootloader"))) -#elif defined (__ICCARM__) - #pragma location=".bootloader" -#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ - -const uint32 CYCODE BL_SizeBytes = 0xFFFFFFFFu; -const uint32 CYCODE *BL_SizeBytesAccess = (const uint32 CYCODE *)(&BL_SizeBytes); - - -#if(0u != BL_DUAL_APP_BOOTLOADER) - uint8 BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; -#else - #define BL_activeApp (BL_MD_BTLDB_ACTIVE_0) -#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - -/*************************************** -* Function Prototypes -***************************************/ -static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ - ; - -static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \ - ; - -static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) CYSMALL \ - ; -#if(!CY_PSOC4) -static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) CYSMALL \ - ; -#endif /* (!CY_PSOC4) */ - -static void BL_HostLink(uint8 timeOut) \ - ; - -static void BL_LaunchApplication(void) CYSMALL \ - ; - -static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ - ; - -static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)\ - ; - -#if(!CY_PSOC3) - /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ - static void BL_LaunchBootloadable(uint32 appAddr); -#endif /* (!CY_PSOC3) */ - - -/******************************************************************************* -* Function Name: BL_CalcPacketChecksum -******************************************************************************** -* -* Summary: -* This computes the 16 bit checksum for the provided number of bytes contained -* in the provided buffer -* -* Parameters: -* buffer: -* The buffer containing the data to compute the checksum for -* size: -* The number of bytes in buffer to compute the checksum for -* -* Returns: -* 16 bit checksum for the provided data -* -*******************************************************************************/ -static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \ - CYSMALL -{ - #if(0u != BL_PACKET_CHECKSUM_CRC) - - uint16 CYDATA crc = BL_CRC_CCITT_INITIAL_VALUE; - uint16 CYDATA tmp; - uint8 CYDATA i; - uint16 CYDATA tmpIndex = size; - - if(0u == size) - { - crc = ~crc; - } - else - { - do - { - tmp = buffer[tmpIndex - size]; - - for (i = 0u; i < 8u; i++) - { - if (0u != ((crc & 0x0001u) ^ (tmp & 0x0001u))) - { - crc = (crc >> 1u) ^ BL_CRC_CCITT_POLYNOMIAL; - } - else - { - crc >>= 1u; - } - - tmp >>= 1u; - } - - size--; - } - while(0u != size); - - crc = ~crc; - tmp = crc; - crc = ( uint16 )(crc << 8u) | (tmp >> 8u); - } - - return(crc); - - #else - - uint16 CYDATA sum = 0u; - - while (size > 0u) - { - sum += buffer[size - 1u]; - size--; - } - - return(( uint16 )1u + ( uint16 )(~sum)); - - #endif /* (0u != BL_PACKET_CHECKSUM_CRC) */ -} - - -/******************************************************************************* -* Function Name: BL_Calc8BitFlashSum -******************************************************************************** -* -* Summary: -* This computes the 8 bit sum for the provided number of bytes contained in -* flash. -* -* Parameters: -* start: -* The starting address to start summing data for -* size: -* The number of bytes to read and compute the sum for -* -* Returns: -* 8 bit sum for the provided data -* -*******************************************************************************/ -static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) \ - CYSMALL -{ - uint8 CYDATA sum = 0u; - - while (size > 0u) - { - size--; - sum += BL_GET_CODE_BYTE(start + size); - } - - return(sum); -} - - -#if(!CY_PSOC4) - - /******************************************************************************* - * Function Name: BL_Calc8BitEepromSum - ******************************************************************************** - * - * Summary: - * This computes the 8 bit sum for the provided number of bytes contained in - * EEPROM. - * - * Parameters: - * start: - * The starting address to start summing data for - * size: - * The number of bytes to read and compute the sum for - * - * Returns: - * 8 bit sum for the provided data - * - *******************************************************************************/ - static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) \ - CYSMALL - { - uint8 CYDATA sum = 0u; - - while (size > 0u) - { - size--; - sum += BL_GET_EEPROM_BYTE(start + size); - } - - return(sum); - } - -#endif /* (!CY_PSOC4) */ - - -/******************************************************************************* -* Function Name: BL_Start -******************************************************************************** -* Summary: -* This function is called in order executing following algorithm: -* -* - Identify active bootloadable application (applicable only to -* Multi-application bootloader) -* -* - Validate bootloader application (desing-time configurable, Bootloader -* application validation option of the component customizer) -* -* - Validate active bootloadable application -* -* - Run communication subroutine (desing-time configurable, Wait for command -* option of the component customizer) -* -* - Schedule bootloadable and reset device -* -* Parameters: -* None -* -* Return: -* This method will never return. It will either load a new application and -* reset the device or it will jump directly to the existing application. -* -* Side Effects: -* If this method determines that the bootloader appliation itself is corrupt, -* this method will not return, instead it will simply hang the application. -* -*******************************************************************************/ -void BL_Start(void) CYSMALL -{ - #if(0u != BL_BOOTLOADER_APP_VALIDATION) - uint8 CYDATA calcedChecksum; - #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ - - #if(!CY_PSOC4) - uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE]; - #endif /* (!CY_PSOC4) */ - - cystatus tmpStatus; - - - /* Identify active bootloadable application */ - #if(0u != BL_DUAL_APP_BOOTLOADER) - - if(BL_MD_BTLDB_ACTIVE_VALUE(0u) == BL_MD_BTLDB_IS_ACTIVE) - { - BL_activeApp = BL_MD_BTLDB_ACTIVE_0; - } - else if (BL_MD_BTLDB_ACTIVE_VALUE(1u) == BL_MD_BTLDB_IS_ACTIVE) - { - BL_activeApp = BL_MD_BTLDB_ACTIVE_1; - } - else - { - BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; - } - - #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - - /* Initialize Flash subsystem for non-PSoC 4 devices */ - #if(!CY_PSOC4) - if (CYRET_SUCCESS != CySetTemp()) - { - CyHalt(0x00u); - } - - if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer)) - { - CyHalt(0x00u); - } - #endif /* (CY_PSOC4) */ - - - /*********************************************************************** - * Bootloader Application Validation - * - * Halt device if: - * - Calculated checksum does not much one stored in metadata section - * - Invalid pointer to the place where bootloader application ends - * - Flash subsystem where not initialized correctly - ***********************************************************************/ - #if(0u != BL_BOOTLOADER_APP_VALIDATION) - - /* Calculate Bootloader application checksum */ - calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR, - *BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR); - - /* we actually included the checksum, so remove it */ - calcedChecksum -= *BL_ChecksumAccess; - calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); - - /* Checksum and pointer to bootloader verification */ - if((calcedChecksum != *BL_ChecksumAccess) || - (0u == *BL_SizeBytesAccess)) - { - CyHalt(0x00u); - } - - #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ - - - /*********************************************************************** - * Active Bootloadable Application Validation - * - * If active bootloadable application is invalid or bootloader - * application is scheduled - do the following: - * - schedule bootloader application to be run after software reset - * - Go to the communication subroutine. Will wait for commands forever - ***********************************************************************/ - tmpStatus = BL_ValidateBootloadable(BL_activeApp); - - if ((BL_GET_RUN_TYPE == BL_START_BTLDR) || - (CYRET_SUCCESS != tmpStatus)) - { - BL_SET_RUN_TYPE(0u); - - BL_HostLink(BL_WAIT_FOR_COMMAND_FOREVER); - } - - - /* Go to the communication subroutine. Will wait for commands specifed time */ - #if(0u != BL_WAIT_FOR_COMMAND) - - /* Timeout is in 100s of miliseconds */ - BL_HostLink(BL_WAIT_FOR_COMMAND_TIME); - - #endif /* (0u != BL_WAIT_FOR_COMMAND) */ - - - /* Schedule bootloadable application and perform software reset */ - BL_LaunchApplication(); -} - - -/******************************************************************************* -* Function Name: BL_LaunchApplication -******************************************************************************** -* -* Summary: -* Jumps the PC to the start address of the user application in flash. -* -* Parameters: -* None -* -* Returns: -* This method will never return if it succesfully goes to the user application. -* -*******************************************************************************/ -static void BL_LaunchApplication(void) CYSMALL -{ - /* Schedule Bootloadable to start after reset */ - BL_SET_RUN_TYPE(BL_START_APP); - - CySoftwareReset(); -} - - -/******************************************************************************* -* Function Name: CyBtldr_CheckLaunch -******************************************************************************** -* -* Summary: -* This routine checks to see if the bootloader or the bootloadable application -* should be run. If the application is to be run, it will start executing. -* If the bootloader is to be run, it will return so the bootloader can -* continue starting up. -* -* Parameters: -* None -* -* Returns: -* None -* -*******************************************************************************/ -void CyBtldr_CheckLaunch(void) CYSMALL -{ - -#if(CY_PSOC4) - - /******************************************************************************* - * Set cyBtldrRunType to zero in case of non-software reset occured. This means - * that bootloader application is scheduled - that is initial clean state. The - * value of cyBtldrRunType is valid only in case of software reset. - *******************************************************************************/ - if (0u == (BL_RES_CAUSE_REG & BL_RES_CAUSE_RESET_SOFT)) - { - cyBtldrRunType = 0u; - } - -#endif /* (CY_PSOC4) */ - - - if (BL_GET_RUN_TYPE == BL_START_APP) - { - BL_SET_RUN_TYPE(0u); - - /******************************************************************************* - * Indicates that we have told ourselves to jump to the application since we have - * already told ourselves to jump, we do not do any expensive verification of the - * application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS - * is something other than 0. - *******************************************************************************/ - if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp)) - { - /* Never return from this method */ - BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, - BL_activeApp)); - } - } -} - - -/* Moves the arguement appAddr (RO) into PC, moving execution to the appAddr */ -#if defined (__ARMCC_VERSION) - - __asm static void BL_LaunchBootloadable(uint32 appAddr) - { - BX R0 - ALIGN - } - -#elif defined(__GNUC__) - - __attribute__((noinline)) /* Workaround for GCC toolchain bug with inlining */ - __attribute__((naked)) - static void BL_LaunchBootloadable(uint32 appAddr) - { - __asm volatile(" BX R0\n"); - } - -#elif defined (__ICCARM__) - - static void BL_LaunchBootloadable(uint32 appAddr) - { - __asm volatile(" BX R0\n"); - } - -#endif /* (__ARMCC_VERSION) */ - - -/******************************************************************************* -* Function Name: BL_ValidateBootloadable -******************************************************************************** -* Summary: -* This routine computes the checksum, zero check, 0xFF check of the -* application area to determine whether a valid application is loaded. -* -* Parameters: -* appId: -* The application number to verify -* -* Returns: -* CYRET_SUCCESS - if successful -* CYRET_BAD_DATA - if the bootloadable is corrupt -* -*******************************************************************************/ -static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ - - { - uint32 CYDATA idx; - - uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) + - BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH, - appId); - - CYBIT valid = 0u; /* Assume bad flash image */ - uint8 CYDATA calcedChecksum = 0u; - - - #if(0u != BL_DUAL_APP_BOOTLOADER) - - if(appId > 1u) - { - return(CYRET_BAD_DATA); - } - - #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - - #if(0u != BL_FAST_APP_VALIDATION) - - if(BL_MD_BTLDB_VERIFIED_VALUE(appId) == BL_MD_BTLDB_IS_VERIFIED) - { - return(CYRET_SUCCESS); - } - - #endif /* (0u != BL_FAST_APP_VALIDATION) */ - - - /* Calculate checksum of bootloadable image */ - for(idx = BL_FIRST_APP_BYTE(appId); idx < end; ++idx) - { - uint8 CYDATA curByte = BL_GET_CODE_BYTE(idx); - - if((curByte != 0u) && (curByte != 0xFFu)) - { - valid = 1u; - } - - calcedChecksum += curByte; - } - - - /*************************************************************************** - * We do not compute checksum over the meta data section, so no need to - * subtract off App Verified or App Active information here like we do when - * verifying a row. - ***************************************************************************/ - - - #if((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) - - /* Add ECC data to checksum */ - idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u); - - /* Flash may run into meta data, ECC does not so use full row */ - end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF)) - ? (CY_FLASH_SIZE >> 3u) - : (end >> 3u); - - for (; idx < end; ++idx) - { - calcedChecksum += CY_GET_XTND_REG8((volatile uint8 *)(CYDEV_ECC_BASE + idx)); - } - - #endif /* ((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) */ - - - calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); - - if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) || - (0u == valid)) - { - return(CYRET_BAD_DATA); - } - - - #if(0u != BL_FAST_APP_VALIDATION) - BL_SetFlashByte((uint32) BL_MD_BTLDB_VERIFIED_OFFSET(appId), - BL_MD_BTLDB_IS_VERIFIED); - #endif /* (0u != BL_FAST_APP_VALIDATION) */ - - - return(CYRET_SUCCESS); -} - - -/******************************************************************************* -* Function Name: BL_HostLink -******************************************************************************** -* -* Summary: -* Causes the bootloader to attempt to read data being transmitted by the -* host application. If data is sent from the host, this establishes the -* communication interface to process all requests. -* -* Parameters: -* timeOut: -* The amount of time to listen for data before giving up. Timeout is -* measured in 10s of ms. Use 0 for infinite wait. -* -* Return: -* None -* -*******************************************************************************/ -static void BL_HostLink(uint8 timeOut) -{ - uint16 CYDATA numberRead; - uint16 CYDATA rspSize; - uint8 CYDATA ackCode; - uint16 CYDATA pktChecksum; - cystatus CYDATA readStat; - uint16 CYDATA pktSize = 0u; - uint16 CYDATA dataOffset = 0u; - uint8 CYDATA timeOutCnt = 10u; - - #if(0u == BL_DUAL_APP_BOOTLOADER) - uint8 CYDATA clearedMetaData = 0u; - #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ - - CYBIT communicationState = BL_COMMUNICATION_STATE_IDLE; - - uint8 packetBuffer[BL_SIZEOF_COMMAND_BUFFER]; - uint8 dataBuffer [BL_SIZEOF_COMMAND_BUFFER]; - - - /* Initialize communications channel. */ - CyBtldrCommStart(); - - /* Enable global interrupts */ - CyGlobalIntEnable; - - do - { - ackCode = CYRET_SUCCESS; - - do - { - readStat = CyBtldrCommRead(packetBuffer, - BL_SIZEOF_COMMAND_BUFFER, - &numberRead, - (0u == timeOut) ? 0xFFu : timeOut); - if (0u != timeOut) - { - timeOutCnt--; - } - - } while ( (0u != timeOutCnt) && (readStat != CYRET_SUCCESS) ); - - - if( readStat != CYRET_SUCCESS ) - { - continue; - } - - if((numberRead < BL_MIN_PKT_SIZE) || - (packetBuffer[BL_SOP_ADDR] != BL_SOP)) - { - ackCode = BL_ERR_DATA; - } - else - { - pktSize = ((uint16)((uint16)packetBuffer[BL_SIZE_ADDR + 1u] << 8u)) | - packetBuffer[BL_SIZE_ADDR]; - - pktChecksum = ((uint16)((uint16)packetBuffer[BL_CHK_ADDR(pktSize) + 1u] << 8u)) | - packetBuffer[BL_CHK_ADDR(pktSize)]; - - if((pktSize + BL_MIN_PKT_SIZE) > numberRead) - { - ackCode = BL_ERR_LENGTH; - } - else if(packetBuffer[BL_EOP_ADDR(pktSize)] != BL_EOP) - { - ackCode = BL_ERR_DATA; - } - else if(pktChecksum != BL_CalcPacketChecksum(packetBuffer, - pktSize + BL_DATA_ADDR)) - { - ackCode = BL_ERR_CHECKSUM; - } - else - { - /* Empty section */ - } - } - - rspSize = 0u; - if(ackCode == CYRET_SUCCESS) - { - uint8 CYDATA btldrData = packetBuffer[BL_DATA_ADDR]; - - ackCode = BL_ERR_DATA; - switch(packetBuffer[BL_CMD_ADDR]) - { - - - /*************************************************************************** - * Get metadata - ***************************************************************************/ - #if(0u != BL_CMD_GET_METADATA) - - case BL_COMMAND_GET_METADATA: - - if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - { - if (btldrData >= BL_MAX_NUM_OF_BTLDB) - { - ackCode = BL_ERR_APP; - } - else if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) - { - #if(CY_PSOC3) - (void) memcpy(&packetBuffer[BL_DATA_ADDR], - ((uint8 CYCODE *) (BL_META_BASE(btldrData))), 56); - #else - (void) memcpy(&packetBuffer[BL_DATA_ADDR], - (uint8 *) BL_META_BASE(btldrData), 56u); - #endif /* (CY_PSOC3) */ - - rspSize = 56u; - ackCode = CYRET_SUCCESS; - } - else - { - ackCode = BL_ERR_APP; - } - } - break; - - #endif /* (0u != BL_CMD_GET_METADATA) */ - - - /*************************************************************************** - * Verify checksum - ***************************************************************************/ - case BL_COMMAND_CHECKSUM: - - if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 0u)) - { - packetBuffer[BL_DATA_ADDR] = - (uint8)(BL_ValidateBootloadable(BL_activeApp) == CYRET_SUCCESS); - - rspSize = 1u; - ackCode = CYRET_SUCCESS; - } - break; - - - /*************************************************************************** - * Get flash size - ***************************************************************************/ - #if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL) - - case BL_COMMAND_REPORT_SIZE: - - if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - { - /* btldrData holds flash array ID sent by host */ - if(btldrData < BL_NUM_OF_FLASH_ARRAYS) - { - #if (1u == BL_NUM_OF_FLASH_ARRAYS) - uint16 CYDATA startRow = (uint16)*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE; - #else - uint16 CYDATA startRow = 0u; - #endif /* (1u == BL_NUM_OF_FLASH_ARRAYS) */ - - packetBuffer[BL_DATA_ADDR] = LO8(startRow); - packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow); - packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u); - packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u); - - rspSize = 4u; - ackCode = CYRET_SUCCESS; - } - - } - break; - - #endif /* (0u != BL_CMD_GET_FLASH_SIZE_AVAIL) */ - - - /*************************************************************************** - * Get application status - ***************************************************************************/ - #if(0u != BL_DUAL_APP_BOOTLOADER) - - #if(0u != BL_CMD_GET_APP_STATUS_AVAIL) - - case BL_COMMAND_APP_STATUS: - - if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - { - - packetBuffer[BL_DATA_ADDR] = - (uint8)BL_ValidateBootloadable(btldrData); - - packetBuffer[BL_DATA_ADDR + 1u] = - (uint8)BL_MD_BTLDB_ACTIVE_VALUE(btldrData); - - rspSize = 2u; - ackCode = CYRET_SUCCESS; - } - break; - - #endif /* (0u != BL_CMD_GET_APP_STATUS_AVAIL) */ - - #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - - /*************************************************************************** - * Program / Erase row - ***************************************************************************/ - case BL_COMMAND_PROGRAM: - - /* The btldrData variable holds Flash Array ID */ - - #if (0u != BL_CMD_ERASE_ROW_AVAIL) - - case BL_COMMAND_ERASE: - if (BL_COMMAND_ERASE == packetBuffer[BL_CMD_ADDR]) - { - if ((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) - { - #if(!CY_PSOC4) - if((btldrData >= BL_FIRST_EE_ARRAYID) && - (btldrData <= BL_LAST_EE_ARRAYID)) - { - /* Size of EEPROM row */ - dataOffset = CY_EEPROM_SIZEOF_ROW; - } - else - { - /* Size of FLASH row (depends on ECC configuration) */ - dataOffset = BL_FROW_SIZE; - } - #else - /* Size of FLASH row (no ECC available) */ - dataOffset = BL_FROW_SIZE; - #endif /* (!CY_PSOC4) */ - - #if(CY_PSOC3) - (void) memset(dataBuffer, (char8) 0, (int16) dataOffset); - #else - (void) memset(dataBuffer, 0, dataOffset); - #endif /* (CY_PSOC3) */ - } - else - { - break; - } - } - - #endif /* (0u != BL_CMD_ERASE_ROW_AVAIL) */ - - - if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize >= 3u)) - { - - /* The command may be sent along with the last block of data, to program the row. */ - #if(CY_PSOC3) - (void) memcpy(&dataBuffer[dataOffset], - &packetBuffer[BL_DATA_ADDR + 3u], - ( int16 )pktSize - 3); - #else - (void) memcpy(&dataBuffer[dataOffset], - &packetBuffer[BL_DATA_ADDR + 3u], - pktSize - 3u); - #endif /* (CY_PSOC3) */ - - dataOffset += (pktSize - 3u); - - #if(!CY_PSOC4) - if((btldrData >= BL_FIRST_EE_ARRAYID) && - (btldrData <= BL_LAST_EE_ARRAYID)) - { - - CyEEPROM_Start(); - - /* Size of EEPROM row */ - pktSize = CY_EEPROM_SIZEOF_ROW; - } - else - { - /* Size of FLASH row (depends on ECC configuration) */ - pktSize = BL_FROW_SIZE; - } - #else - /* Size of FLASH row (no ECC available) */ - pktSize = BL_FROW_SIZE; - #endif /* (!CY_PSOC4) */ - - - /* Check if we have all data to program */ - if(dataOffset == pktSize) - { - /* Get FLASH/EEPROM row number */ - dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | - packetBuffer[BL_DATA_ADDR + 1u]; - - #if(!CY_PSOC4) - if(btldrData <= BL_LAST_FLASH_ARRAYID) - { - #endif /* (!CY_PSOC4) */ - - #if(0u == BL_DUAL_APP_BOOTLOADER) - - if(0u == clearedMetaData) - { - /* Metadata section must be filled with zeroes */ - - uint8 erase[BL_FROW_SIZE]; - - #if(CY_PSOC3) - (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE); - #else - (void) memset(erase, 0, BL_FROW_SIZE); - #endif /* (CY_PSOC3) */ - - #if(CY_PSOC4) - (void) CySysFlashWriteRow(BL_MD_ROW, erase); - #else - (void) CyWriteRowFull((uint8) BL_MD_FLASH_ARRAY_NUM, - (uint16) BL_MD_ROW, - erase, - BL_FROW_SIZE); - #endif /* (CY_PSOC4) */ - - /* Set up flag that metadata was cleared */ - clearedMetaData = 1u; - } - - #else - - if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE) - { - /* First active bootloadable application row */ - uint16 firstRow = (uint16) 1u + - (uint16) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, - BL_activeApp); - - #if(CY_PSOC4) - uint16 row = dataOffset; - #else - uint16 row = (uint16)(btldrData * (CYDEV_FLS_SECTOR_SIZE / CYDEV_FLS_ROW_SIZE)) + - dataOffset; - #endif /* (CY_PSOC4) */ - - - /******************************************************************************* - * Last row is equal to the first row plus the number of rows available for each - * app. To compute this, we first subtract the number of appliaction images from - * the total flash rows: (CY_FLASH_NUMBER_ROWS - 2u). - * - * Then subtract off the first row: - * App Rows = (CY_FLASH_NUMBER_ROWS - 2u - firstRow) - * Then divide that number by the number of application that must fit within the - * space, if we are app1 then that number is 2, if app2 then 1. Our divisor is - * then: (2u - BL_activeApp). - * - * Adding this number to firstRow gives the address right beyond our valid range - * so we subtract 1. - *******************************************************************************/ - uint16 lastRow = (firstRow - 1u) + - ((uint16)((CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) - 2u - firstRow) / - ((uint16)2u - (uint16)BL_activeApp)); - - - /******************************************************************************* - * Check to see if the row to program is within the range of the active - * application, or if it maches the active application's metadata row. If so, - * refuse to program as it would corrupt the active app. - *******************************************************************************/ - if(((row >= firstRow) && (row <= lastRow)) || - ((btldrData == BL_MD_FLASH_ARRAY_NUM) && - (dataOffset == BL_MD_ROW_NUM(BL_activeApp)))) - { - ackCode = BL_ERR_ACTIVE; - dataOffset = 0u; - break; - } - } - - #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ - - #if(!CY_PSOC4) - } - #endif /* (!CY_PSOC4) */ - - #if(CY_PSOC4) - - ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) dataOffset, dataBuffer)) \ - ? BL_ERR_ROW \ - : CYRET_SUCCESS; - - #else - - ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataBuffer, pktSize)) \ - ? BL_ERR_ROW \ - : CYRET_SUCCESS; - - #endif /* (CY_PSOC4) */ - - } - else - { - ackCode = BL_ERR_LENGTH; - } - - dataOffset = 0u; - } - break; - - - /*************************************************************************** - * Sync bootloader - ***************************************************************************/ - #if(0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) - - case BL_COMMAND_SYNC: - - if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) - { - /* If something failed the host would send this command to reset the bootloader. */ - dataOffset = 0u; - - /* Don't ack the packet, just get ready to accept the next one */ - continue; - } - break; - - #endif /* (0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) */ - - - /*************************************************************************** - * Set active application - ***************************************************************************/ - #if(0u != BL_DUAL_APP_BOOTLOADER) - - case BL_COMMAND_APP_ACTIVE: - - if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) - { - if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) - { - uint8 CYDATA idx; - - for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++) - { - BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx), - (uint8 )(idx == btldrData)); - } - BL_activeApp = btldrData; - ackCode = CYRET_SUCCESS; - } - else - { - ackCode = BL_ERR_APP; - } - } - break; - - #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - - /*************************************************************************** - * Send data - ***************************************************************************/ - #if (0u != BL_CMD_SEND_DATA_AVAIL) - - case BL_COMMAND_DATA: - - if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) - { - /* Make sure that dataOffset is valid before copying the data */ - if((dataOffset + pktSize) <= BL_SIZEOF_COMMAND_BUFFER) - { - ackCode = CYRET_SUCCESS; - - #if(CY_PSOC3) - (void) memcpy(&dataBuffer[dataOffset], - &packetBuffer[BL_DATA_ADDR], - ( int16 )pktSize); - #else - (void) memcpy(&dataBuffer[dataOffset], - &packetBuffer[BL_DATA_ADDR], - pktSize); - #endif /* (CY_PSOC3) */ - - dataOffset += pktSize; - } - else - { - ackCode = BL_ERR_LENGTH; - } - } - - break; - - #endif /* (0u != BL_CMD_SEND_DATA_AVAIL) */ - - - /*************************************************************************** - * Enter bootloader - ***************************************************************************/ - case BL_COMMAND_ENTER: - - if(pktSize == 0u) - { - #if(CY_PSOC3) - - BL_ENTER CYDATA BtldrVersion = - {CYSWAP_ENDIAN32(CYDEV_CHIP_JTAG_ID), CYDEV_CHIP_REV_EXPECT, BL_VERSION}; - - #else - - BL_ENTER CYDATA BtldrVersion = - {CYDEV_CHIP_JTAG_ID, CYDEV_CHIP_REV_EXPECT, BL_VERSION}; - - #endif /* (CY_PSOC3) */ - - communicationState = BL_COMMUNICATION_STATE_ACTIVE; - - rspSize = sizeof(BL_ENTER); - - #if(CY_PSOC3) - (void) memcpy(&packetBuffer[BL_DATA_ADDR], - &BtldrVersion, - ( int16 )rspSize); - #else - (void) memcpy(&packetBuffer[BL_DATA_ADDR], - &BtldrVersion, - rspSize); - #endif /* (CY_PSOC3) */ - - ackCode = CYRET_SUCCESS; - } - break; - - - /*************************************************************************** - * Verify row - ***************************************************************************/ - case BL_COMMAND_VERIFY: - - if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) - { - /* Get FLASH/EEPROM row number */ - uint16 CYDATA rowNum = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | - packetBuffer[BL_DATA_ADDR + 1u]; - - #if(!CY_PSOC4) - - uint32 CYDATA rowAddr; - uint8 CYDATA checksum; - - if((btldrData >= BL_FIRST_EE_ARRAYID) && - (btldrData <= BL_LAST_EE_ARRAYID)) - { - /* EEPROM */ - /* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */ - rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE; - - checksum = BL_Calc8BitEepromSum(rowAddr, CYDEV_EEPROM_ROW_SIZE); - } - else - { - /* FLASH */ - rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) - + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); - - checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE); - } - - #else - - uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) - + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); - - uint8 CYDATA checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE); - - #endif /* (!CY_PSOC4) */ - - - /* Calculate checksum on data from ECC */ - #if(!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) - - if(btldrData <= BL_LAST_FLASH_ARRAYID) - { - uint16 CYDATA tmpIndex; - - rowAddr = CYDEV_ECC_BASE + ((uint32)btldrData * (CYDEV_FLS_SECTOR_SIZE / 8u)) - + ((uint32)rowNum * CYDEV_ECC_ROW_SIZE); - - for(tmpIndex = 0u; tmpIndex < CYDEV_ECC_ROW_SIZE; tmpIndex++) - { - checksum += CY_GET_XTND_REG8((uint8 CYFAR *)(rowAddr + tmpIndex)); - } - } - - #endif /* (!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) */ - - - /******************************************************************************* - * App Verified & App Active are information that is updated in flash at runtime - * remove these items from the checksum to allow the host to verify everything is - * correct. - ******************************************************************************/ - if((BL_MD_FLASH_ARRAY_NUM == btldrData) && - (BL_CONTAIN_METADATA(rowNum))) - { - checksum -= BL_MD_BTLDB_ACTIVE_VALUE (BL_GET_APP_ID(rowNum)); - checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum)); - } - - packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum); - ackCode = CYRET_SUCCESS; - rspSize = 1u; - } - break; - - - /*************************************************************************** - * Exit bootloader - ***************************************************************************/ - case BL_COMMAND_EXIT: - - if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp)) - { - BL_SET_RUN_TYPE(BL_START_APP); - } - - CySoftwareReset(); - - /* Will never get here */ - break; - - - /*************************************************************************** - * Unsupported command - ***************************************************************************/ - default: - ackCode = BL_ERR_CMD; - break; - } - } - - /* ?CK the packet and function. */ - (void) BL_WritePacket(ackCode, packetBuffer, rspSize); - - } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState)); -} - - -/******************************************************************************* -* Function Name: BL_WritePacket -******************************************************************************** -* -* Summary: -* Creates a bootloader responce packet and transmits it back to the bootloader -* host application over the already established communications protocol. -* -* Parameters: -* status: -* The status code to pass back as the second byte of the packet -* buffer: -* The buffer containing the data portion of the packet -* size: -* The number of bytes contained within the buffer to pass back -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_UNKNOWN if there was an error tranmitting the packet. -* -*******************************************************************************/ -static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ - -{ - uint16 CYDATA checksum; - - /* Start of the packet. */ - buffer[BL_SOP_ADDR] = BL_SOP; - buffer[BL_CMD_ADDR] = status; - buffer[BL_SIZE_ADDR] = LO8(size); - buffer[BL_SIZE_ADDR + 1u] = HI8(size); - - /* Compute the checksum. */ - checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR); - - buffer[BL_CHK_ADDR(size)] = LO8(checksum); - buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum); - buffer[BL_EOP_ADDR(size)] = BL_EOP; - - /* Start the packet transmit. */ - return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u)); -} - - -/******************************************************************************* -* Function Name: BL_SetFlashByte -******************************************************************************** -* -* Summary: -* Writes byte a flash memory location -* -* Parameters: -* address: -* Address in Flash memory where data will be written -* -* runType: -* Byte to be written -* -* Return: -* None -* -*******************************************************************************/ -void BL_SetFlashByte(uint32 address, uint8 runType) -{ - uint32 flsAddr = address - CYDEV_FLASH_BASE; - uint8 rowData[CYDEV_FLS_ROW_SIZE]; - - #if !(CY_PSOC4) - uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); - #endif /* !(CY_PSOC4) */ - - uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); - uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); - uint16 idx; - - for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) - { - rowData[idx] = BL_GET_CODE_BYTE(baseAddr + idx); - } - - rowData[address % CYDEV_FLS_ROW_SIZE] = runType; - - #if(CY_PSOC4) - (void) CySysFlashWriteRow((uint32) rowNum, rowData); - #else - (void) CyWriteRowData(arrayId, rowNum, rowData); - #endif /* (CY_PSOC4) */ -} - - -/******************************************************************************* -* Function Name: BL_GetMetadata -******************************************************************************** -* -* Summary: -* Returns value of the multi-byte field. -* -* Parameters: -* fieldName: -* The field to get data from: -* BL_GET_METADATA_BTLDB_ADDR -* BL_GET_METADATA_BTLDR_LAST_ROW -* BL_GET_METADATA_BTLDB_LENGTH -* BL_GET_METADATA_BTLDR_APP_VERSION -* BL_GET_METADATA_BTLDB_APP_VERSION -* BL_GET_METADATA_BTLDB_APP_ID -* BL_GET_METADATA_BTLDB_APP_CUST_ID -* -* appId: -* Number of the bootlodable application. -* -* Return: -* None -* -*******************************************************************************/ -static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId) -{ - uint32 fieldPtr; - uint8 fieldSize = 2u; - uint32 result; - - switch (fieldName) - { - case BL_GET_METADATA_BTLDB_APP_CUST_ID: - fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId); - fieldSize = 4u; - break; - - case BL_GET_METADATA_BTLDR_APP_VERSION: - fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId); - break; - - case BL_GET_METADATA_BTLDB_ADDR: - fieldPtr = BL_MD_BTLDB_ADDR_OFFSET(appId); - #if(!CY_PSOC3) - fieldSize = 4u; - #endif /* (!CY_PSOC3) */ - break; - - case BL_GET_METADATA_BTLDR_LAST_ROW: - fieldPtr = BL_MD_BTLDR_LAST_ROW_OFFSET(appId); - break; - - case BL_GET_METADATA_BTLDB_LENGTH: - fieldPtr = BL_MD_BTLDB_LENGTH_OFFSET(appId); - #if(!CY_PSOC3) - fieldSize = 4u; - #endif /* (!CY_PSOC3) */ - break; - - case BL_GET_METADATA_BTLDB_APP_VERSION: - fieldPtr = BL_MD_BTLDB_APP_VERSION_OFFSET(appId); - break; - - case BL_GET_METADATA_BTLDB_APP_ID: - fieldPtr = BL_MD_BTLDB_APP_ID_OFFSET(appId); - break; - - default: - /* Should never be here */ - CYASSERT(0u != 0u); - fieldPtr = 0u; - break; - } - - - /* Read all fields as big-endian */ - if (2u == fieldSize) - { - result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)); - result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) fieldPtr ) << 8u; - } - else - { - result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)); - result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u; - result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u; - result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u; - } - - /* Following fields should be little-endian */ -#if(!CY_PSOC3) - switch (fieldName) - { - case BL_GET_METADATA_BTLDR_LAST_ROW: - result = CYSWAP_ENDIAN16(result); - break; - - case BL_GET_METADATA_BTLDB_ADDR: - case BL_GET_METADATA_BTLDB_LENGTH: - result = CYSWAP_ENDIAN32(result); - break; - - default: - break; - } - -#endif /* (!CY_PSOC3) */ - - return (result); -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL.h deleted file mode 100755 index e459c55..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL.h +++ /dev/null @@ -1,318 +0,0 @@ -/******************************************************************************* -* File Name: BL.h -* Version 1.20 -* -* Description: -* Provides an API for the Bootloader. The API includes functions for starting -* boot loading operations, validating the application and jumping to the -* application. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOTLOADER_BL_H) -#define CY_BOOTLOADER_BL_H - -#include "cytypes.h" - - -/* Check to see if required defines such as CY_PSOC5LP are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5LP) - #error Component Bootloader_v1_20 requires cy_boot v3.0 or later -#endif /* (CY_ PSOC5X) */ - - -#define BL_DUAL_APP_BOOTLOADER (0u) -#define BL_BOOTLOADER_APP_VERSION (0u) -#define BL_FAST_APP_VALIDATION (0u) -#define BL_PACKET_CHECKSUM_CRC (0u) -#define BL_WAIT_FOR_COMMAND (1u) -#define BL_WAIT_FOR_COMMAND_TIME (20u) -#define BL_BOOTLOADER_APP_VALIDATION (1u) - -#define BL_CMD_GET_FLASH_SIZE_AVAIL (1u) -#define BL_CMD_ERASE_ROW_AVAIL (1u) -#define BL_CMD_VERIFY_ROW_AVAIL (1u) -#define BL_CMD_SYNC_BOOTLOADER_AVAIL (1u) -#define BL_CMD_SEND_DATA_AVAIL (1u) -#define BL_CMD_GET_METADATA (0u) - -#if(0u != BL_DUAL_APP_BOOTLOADER) - #define BL_CMD_GET_APP_STATUS_AVAIL (1u) -#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - -/******************************************************************************* -* Bootloadable applications identification -*******************************************************************************/ -#define BL_MD_BTLDB_ACTIVE_0 (0x00u) -#if(0u != BL_DUAL_APP_BOOTLOADER) - #define BL_MD_BTLDB_ACTIVE_1 (0x01u) - #define BL_MD_BTLDB_ACTIVE_NONE (0x02u) -#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - -/* Mask used to indicate starting application */ -#define BL_SCHEDULE_BTLDB (0x80u) -#define BL_SCHEDULE_BTLDR (0x40u) -#define BL_SCHEDULE_MASK (0xC0u) - - -#if defined(__ARMCC_VERSION) || defined (__GNUC__) - __attribute__((section (".bootloader"))) -#elif defined (__ICCARM__) - #pragma location=".bootloader" -#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ -extern const uint8 CYCODE BL_Checksum; -extern const uint8 CYCODE *BL_ChecksumAccess; - - -#if defined(__ARMCC_VERSION) || defined (__GNUC__) - __attribute__((section (".bootloader"))) -#elif defined (__ICCARM__) - #pragma location=".bootloader" -#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ -extern const uint32 CYCODE BL_SizeBytes; -extern const uint32 CYCODE *BL_SizeBytesAccess; - - -/******************************************************************************* -* This variable is used by Bootloader/Bootloadable components to schedule what -* application will be started after software reset. -*******************************************************************************/ -#if (CY_PSOC4) - #if defined(__ARMCC_VERSION) - __attribute__ ((section(".bootloaderruntype"), zero_init)) - #elif defined (__GNUC__) - __attribute__ ((section(".bootloaderruntype"))) - #elif defined (__ICCARM__) - #pragma location=".bootloaderruntype" - #endif /* defined(__ARMCC_VERSION) */ - extern volatile uint32 cyBtldrRunType; -#endif /* (CY_PSOC4) */ - - -#if(0u != BL_DUAL_APP_BOOTLOADER) - extern uint8 BL_activeApp; -#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - -#if(CY_PSOC4) - /* Reset Cause Observation Register */ - #define BL_RES_CAUSE_REG (* (reg32 *) CYREG_RES_CAUSE) - #define BL_RES_CAUSE_PTR ( (reg32 *) CYREG_RES_CAUSE) -#else - #define BL_RESET_SR0_REG (* (reg8 *) CYREG_RESET_SR0) - #define BL_RESET_SR0_PTR ( (reg8 *) CYREG_RESET_SR0) -#endif /* (CY_PSOC4) */ - - -/******************************************************************************* -* Get the reason of the device reset -* Return cyBtldrRunType in case if software reset was reset reason and -* set cyBtldrRunType to zero (bootloader application is scheduled - that is -* initial clean state) and return zero. -*******************************************************************************/ -#if(CY_PSOC4) - #define BL_GET_RUN_TYPE (cyBtldrRunType) -#else - #define BL_GET_RUN_TYPE (BL_RESET_SR0_REG & BL_SCHEDULE_MASK) -#endif /* (CY_PSOC4) */ - - -/******************************************************************************* -* Schedule Bootloader/Bootloadable to be run after software reset -*******************************************************************************/ -#if(CY_PSOC4) - #define BL_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) -#else - #define BL_SET_RUN_TYPE(x) (BL_RESET_SR0_REG = (x)) -#endif /* (CY_PSOC4) */ - - -/* Returns the number of Flash arrays availalbe in the device */ -#define BL_NUM_OF_FLASH_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE) - - -/******************************************************************************* -* External References -*******************************************************************************/ -void BL_SetFlashByte(uint32 address, uint8 runType); -void CyBtldr_CheckLaunch(void) CYSMALL ; -void BL_Start(void) CYSMALL ; - -#if(CY_PSOC3) - /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ - extern void BL_LaunchBootloadable(uint32 appAddr); -#endif /* (CY_PSOC3) */ - -/* If using custom interface as the IO Component, user must provide these functions */ -#if defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) - - extern void CyBtldrCommStart(void); - extern void CyBtldrCommStop (void); - extern void CyBtldrCommReset(void); - extern cystatus CyBtldrCommWrite(uint8* buffer, uint16 size, uint16* count, uint8 timeOut); - extern cystatus CyBtldrCommRead (uint8* buffer, uint16 size, uint16* count, uint8 timeOut); - -#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) */ - - -/******************************************************************************* -* Kept for backward compatibility. -*******************************************************************************/ -#if(0u != BL_DUAL_APP_BOOTLOADER) - #define BL_ValidateApp(x) BL_ValidateBootloadable((x)) - #define BL_ValidateApplication \ - BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0) -#else - #define BL_ValidateApplication \ - BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0) - #define BL_ValidateApp(x) BL_ValidateBootloadable((x)) -#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from version 1.10 -*******************************************************************************/ -#define BL_BOOTLOADABLE_APP_VALID (BL_BOOTLOADER_APP_VALIDATION) -#define CyBtldr_Start BL_Start - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from version 1.20 -*******************************************************************************/ -#define BL_META_BASE(x) (CYDEV_FLASH_BASE + \ - (CYDEV_FLASH_SIZE - (( uint32 )(x) * CYDEV_FLS_ROW_SIZE) - \ - BL_META_DATA_SIZE)) -#define BL_META_ARRAY (BL_NUM_OF_FLASH_ARRAYS - 1u) -#define BL_META_APP_ENTRY_POINT_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_ADDR_OFFSET) -#define BL_META_APP_BYTE_LEN(x) (BL_META_BASE(x) + \ - BL_META_APP_BYTE_LEN_OFFSET) -#define BL_META_APP_RUN_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_RUN_TYPE_OFFSET) -#define BL_META_APP_ACTIVE_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_ACTIVE_OFFSET) -#define BL_META_APP_VERIFIED_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_VERIFIED_OFFSET) -#define BL_META_APP_BLDBL_VER_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_BL_BUILD_VER_OFFSET) -#define BL_META_APP_VER_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_VER_OFFSET) -#define BL_META_APP_ID_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_ID_OFFSET) -#define BL_META_APP_CUST_ID_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_CUST_ID_OFFSET) -#define BL_META_LAST_BLDR_ROW_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_BL_LAST_ROW_OFFSET) -#define BL_META_CHECKSUM_ADDR(x) (BL_META_BASE(x) + \ - BL_META_APP_CHECKSUM_OFFSET) -#if(0u == BL_DUAL_APP_BOOTLOADER) - #define BL_MD_BASE BL_META_BASE(0u) - #define BL_MD_ROW ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \ - - 1u) - #define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(0u) - #define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(0u) - #define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(0u) - #define BL_MD_APP_VERIFIED_ADDR BL_META_APP_VERIFIED_ADDR(0u) - #define BL_MD_APP_ENTRY_POINT_ADDR BL_META_APP_ENTRY_POINT_ADDR(0u) - #define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(0u) -#else - #define BL_MD_ROW(x) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \ - - 1u - ( uint32 )(x)) - #define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(appId) - #define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(appId) - #define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(appId) - #define BL_MD_APP_VERIFIED_ADDR BL_META_APP_VERIFIED_ADDR(appId) - #define BL_MD_APP_ENTRY_POINT_ADDR \ - BL_META_APP_ENTRY_POINT_ADDR(BL_activeApp) - #define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(BL_activeApp) -#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ - -#define BL_P_APP_ACTIVE(x) ((uint8 CYCODE *) BL_META_APP_ACTIVE_ADDR(x)) -#define BL_MD_PTR_CHECKSUM ((uint8 CYCODE *) BL_MD_CHECKSUM_ADDR) -#define BL_MD_PTR_APP_ENTRY_POINT ((BL_APP_ADDRESS CYCODE *) \ - BL_MD_APP_ENTRY_POINT_ADDR) -#define BL_MD_PTR_LAST_BLDR_ROW ((uint16 CYCODE *) BL_MD_LAST_BLDR_ROW_ADDR) -#define BL_MD_PTR_APP_BYTE_LEN ((BL_APP_ADDRESS CYCODE *) \ - BL_MD_APP_BYTE_LEN) -#define BL_MD_PTR_APP_RUN_ADDR ((uint8 CYCODE *) BL_MD_APP_RUN_ADDR) -#define BL_MD_PTR_APP_VERIFIED ((uint8 CYCODE *) BL_MD_APP_VERIFIED_ADDR) -#define BL_MD_PTR_APP_BLD_BL_VER ((uint16 CYCODE *) BL_MD_APP_BLDBL_VER_ADDR) -#define BL_MD_PTR_APP_VER ((uint16 CYCODE *) BL_MD_APP_VER_ADDR) -#define BL_MD_PTR_APP_ID ((uint16 CYCODE *) BL_MD_APP_ID_ADDR) -#define BL_MD_PTR_APP_CUST_ID ((uint32 CYCODE *) BL_MD_APP_CUST_ID_ADDR) -#if(CY_PSOC3) - #define BL_APP_ADDRESS uint16 - #define BL_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx))) - #define BL_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) - #define BL_META_APP_ADDR_OFFSET (3u) - #define BL_META_APP_BL_LAST_ROW_OFFSET (7u) - #define BL_META_APP_BYTE_LEN_OFFSET (11u) - #define BL_META_APP_RUN_TYPE_OFFSET (15u) -#else - #define BL_APP_ADDRESS uint32 - #define BL_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx)))) - #define BL_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx)))) - #define BL_META_APP_ADDR_OFFSET (1u) - #define BL_META_APP_BL_LAST_ROW_OFFSET (5u) - #define BL_META_APP_BYTE_LEN_OFFSET (9u) - #define BL_META_APP_RUN_TYPE_OFFSET (13u) -#endif /* (CY_PSOC3) */ -#define BL_META_APP_ACTIVE_OFFSET (16u) -#define BL_META_APP_VERIFIED_OFFSET (17u) -#define BL_META_APP_BL_BUILD_VER_OFFSET (18u) -#define BL_META_APP_ID_OFFSET (20u) -#define BL_META_APP_VER_OFFSET (22u) -#define BL_META_APP_CUST_ID_OFFSET (24u) -#if (CY_PSOC4) - #define BL_GET_REG16(x) ((uint16)( \ - (( uint16 )(( uint16 )CY_GET_XTND_REG8((x) ) )) | \ - (( uint16 )(( uint16 )CY_GET_XTND_REG8((x) + 1u) << 8u)) \ - )) - - #define BL_GET_REG32(x) ( \ - (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) ) )) | \ - (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 1u) << 8u)) | \ - (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 2u) << 16u)) | \ - (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 3u) << 24u)) \ - ) -#endif /* (CY_PSOC4) */ -#define BL_META_APP_CHECKSUM_OFFSET (0u) -#define BL_META_DATA_SIZE (64u) -#if(CY_PSOC4) - extern uint8 appRunType; -#endif /* (CY_PSOC4) */ - -#if(CY_PSOC4) - #define BL_SOFTWARE_RESET CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u) -#else - #define BL_SOFTWARE_RESET CY_SET_REG8(CYREG_RESET_CR2, 0x01u) -#endif /* (CY_PSOC4) */ - -#define BL_SetFlashRunType(runType) BL_SetFlashByte( \ - BL_MD_APP_RUN_ADDR(0), (runType)) - -#define BL_START_APP (BL_SCHEDULE_BTLDB) -#define BL_START_BTLDR (BL_SCHEDULE_BTLDR) - -/* Some PSoC Creator versions used to generate only one name types */ -#if !defined (CYDEV_FLASH_BASE) - #define CYDEV_FLASH_BASE (CYDEV_FLS_BASE) -#endif /* !defined (CYDEV_FLASH_BASE) */ - -#if !defined (CYDEV_FLASH_SIZE) - #define CYDEV_FLASH_SIZE (CYDEV_FLS_SIZE) -#endif /* CYDEV_FLASH_SIZE */ - - -#endif /* CY_BOOTLOADER_BL_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL_PVT.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL_PVT.h deleted file mode 100755 index 9d12d71..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/BL_PVT.h +++ /dev/null @@ -1,315 +0,0 @@ -/******************************************************************************* -* File Name: BL_PVT.h -* Version 1.20 -* -* Description: -* Provides an API for the Bootloader. -* -******************************************************************************** -* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOTLOADER_BL_PVT_H) -#define CY_BOOTLOADER_BL_PVT_H - -#include "BL.h" - - -typedef struct -{ - uint32 SiliconId; - uint8 Revision; - uint8 BootLoaderVersion[3u]; - -} BL_ENTER; - - -#define BL_VERSION {\ - (uint8)20, \ - (uint8)1, \ - (uint8)0x01u \ - } - -/* Packet framing constants. */ -#define BL_SOP (0x01u) /* Start of Packet */ -#define BL_EOP (0x17u) /* End of Packet */ - - -/* Bootloader command responces */ -#define BL_ERR_KEY (0x01u) /* The provided key does not match the expected value */ -#define BL_ERR_VERIFY (0x02u) /* The verification of flash failed */ -#define BL_ERR_LENGTH (0x03u) /* The amount of data available is outside the expected range */ -#define BL_ERR_DATA (0x04u) /* The data is not of the proper form */ -#define BL_ERR_CMD (0x05u) /* The command is not recognized */ -#define BL_ERR_DEVICE (0x06u) /* The expected device does not match the detected device */ -#define BL_ERR_VERSION (0x07u) /* The bootloader version detected is not supported */ -#define BL_ERR_CHECKSUM (0x08u) /* The checksum does not match the expected value */ -#define BL_ERR_ARRAY (0x09u) /* The flash array is not valid */ -#define BL_ERR_ROW (0x0Au) /* The flash row is not valid */ -#define BL_ERR_PROTECT (0x0Bu) /* The flash row is protected and can not be programmed */ -#define BL_ERR_APP (0x0Cu) /* The application is not valid and cannot be set as active */ -#define BL_ERR_ACTIVE (0x0Du) /* The application is currently marked as active */ -#define BL_ERR_UNK (0x0Fu) /* An unknown error occurred */ - - -/* Bootloader command definitions. */ -#define BL_COMMAND_CHECKSUM (0x31u) /* Verify the checksum for the bootloadable project */ -#define BL_COMMAND_REPORT_SIZE (0x32u) /* Report the programmable portions of flash */ -#define BL_COMMAND_APP_STATUS (0x33u) /* Gets status info about the provided app status */ -#define BL_COMMAND_ERASE (0x34u) /* Erase the specified flash row */ -#define BL_COMMAND_SYNC (0x35u) /* Sync the bootloader and host application */ -#define BL_COMMAND_APP_ACTIVE (0x36u) /* Sets the active application */ -#define BL_COMMAND_DATA (0x37u) /* Queue up a block of data for programming */ -#define BL_COMMAND_ENTER (0x38u) /* Enter the bootloader */ -#define BL_COMMAND_PROGRAM (0x39u) /* Program the specified row */ -#define BL_COMMAND_VERIFY (0x3Au) /* Compute flash row checksum for verification */ -#define BL_COMMAND_EXIT (0x3Bu) /* Exits the bootloader & resets the chip */ -#define BL_COMMAND_GET_METADATA (0x3Cu) /* Reports the metadata for a selected application */ - - -/******************************************************************************* -* Bootloader packet byte addresses: -* [1-byte] [1-byte ] [2-byte] [n-byte] [ 2-byte ] [1-byte] -* [ SOP ] [Command] [ Size ] [ Data ] [Checksum] [ EOP ] -*******************************************************************************/ -#define BL_SOP_ADDR (0x00u) /* Start of packet offset from beginning */ -#define BL_CMD_ADDR (0x01u) /* Command offset from beginning */ -#define BL_SIZE_ADDR (0x02u) /* Packet size offset from beginning */ -#define BL_DATA_ADDR (0x04u) /* Packet data offset from beginning */ -#define BL_CHK_ADDR(x) (0x04u + (x)) /* Packet checksum offset from end */ -#define BL_EOP_ADDR(x) (0x06u + (x)) /* End of packet offset from end */ -#define BL_MIN_PKT_SIZE (7u) /* The minimum number of bytes in a packet */ - - -/******************************************************************************* -BL_ValidateBootloadable() -*******************************************************************************/ -#define BL_FIRST_APP_BYTE(appId) ((uint32)CYDEV_FLS_ROW_SIZE * \ - ((uint32) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, appId) + \ - (uint32) 1u)) - -#define BL_MD_BTLDB_IS_VERIFIED (0x01u) - - -/******************************************************************************* -* BL_Start() -*******************************************************************************/ -#define BL_MD_BTLDB_IS_ACTIVE (0x01u) -#define BL_WAIT_FOR_COMMAND_FOREVER (0x00u) - - - /* Maximum number of bytes accepted in a packet plus some */ -#define BL_SIZEOF_COMMAND_BUFFER (300u) - - -/******************************************************************************* -* BL_HostLink() -*******************************************************************************/ -#define BL_COMMUNICATION_STATE_IDLE (0u) -#define BL_COMMUNICATION_STATE_ACTIVE (1u) - -#if(!CY_PSOC4) - - /******************************************************************************* - * The Array ID indicates the unique ID of the SONOS array being accessed: - * - 0x00-0x3E : Flash Arrays - * - 0x3F : Selects all Flash arrays simultaneously - * - 0x40-0x7F : Embedded EEPROM Arrays - *******************************************************************************/ - #define BL_FIRST_FLASH_ARRAYID (0x00u) - #define BL_LAST_FLASH_ARRAYID (0x3Fu) - #define BL_FIRST_EE_ARRAYID (0x40u) - #define BL_LAST_EE_ARRAYID (0x7Fu) - -#endif /* (!CY_PSOC4) */ - - -/******************************************************************************* -* BL_CalcPacketChecksum() -*******************************************************************************/ -#if(0u != BL_PACKET_CHECKSUM_CRC) - #define BL_CRC_CCITT_POLYNOMIAL (0x8408u) /* x^16 + x^12 + x^5 + 1 */ - #define BL_CRC_CCITT_INITIAL_VALUE (0xffffu) -#endif /* (0u != BL_PACKET_CHECKSUM_CRC) */ - - -/******************************************************************************* -* BL_GetMetadata() -*******************************************************************************/ -#define BL_GET_METADATA_BTLDB_ADDR (1u) -#define BL_GET_METADATA_BTLDR_LAST_ROW (2u) -#define BL_GET_METADATA_BTLDB_LENGTH (3u) -#define BL_GET_METADATA_BTLDR_APP_VERSION (4u) -#define BL_GET_METADATA_BTLDB_APP_VERSION (5u) -#define BL_GET_METADATA_BTLDB_APP_ID (6u) -#define BL_GET_METADATA_BTLDB_APP_CUST_ID (7u) - - -/******************************************************************************* -* CyBtldr_CheckLaunch() -*******************************************************************************/ -#define BL_RES_CAUSE_RESET_SOFT (0x10u) - - -/******************************************************************************* -* Metadata addresses and pointer defines -*******************************************************************************/ -#define BL_MD_SIZEOF (64u) - - -/******************************************************************************* -* Metadata base address. In case of bootloader application, the metadata is -* placed at row N-1; in case of multi-application bootloader, the bootloadable -* application number 1 will use row N-1, and application number 2 will use row -* N-2 to store its metadata, where N is the total number of rows for the -* selected device. -*******************************************************************************/ -#define BL_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + \ - (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \ - BL_MD_SIZEOF)) - -#define BL_MD_FLASH_ARRAY_NUM (BL_NUM_OF_FLASH_ARRAYS - 1u) - -#define BL_MD_ROW_NUM(appId) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \ - 1u - (uint32)(appId)) - -#define BL_MD_BTLDB_CHECKSUM_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 0u) -#if(CY_PSOC3) - #define BL_MD_BTLDB_ADDR_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 3u) - #define BL_MD_BTLDR_LAST_ROW_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 7u) - #define BL_MD_BTLDB_LENGTH_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 11u) -#else - #define BL_MD_BTLDB_ADDR_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 1u) - #define BL_MD_BTLDR_LAST_ROW_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 5u) - #define BL_MD_BTLDB_LENGTH_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 9u) -#endif /* (CY_PSOC3) */ -#define BL_MD_BTLDB_ACTIVE_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 16u) -#define BL_MD_BTLDB_VERIFIED_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 17u) -#define BL_MD_BTLDR_APP_VERSION_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 18u) -#define BL_MD_BTLDB_APP_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 20u) -#define BL_MD_BTLDB_APP_VERSION_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 22u) -#define BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 24u) - - -/******************************************************************************* -* Macro for 1 byte long metadata fields -*******************************************************************************/ -#define BL_MD_BTLDB_CHECKSUM_PTR (appId) \ - ((reg8 *)(BL_MD_BTLDB_CHECKSUM_OFFSET(appId))) -#define BL_MD_BTLDB_CHECKSUM_VALUE(appId) \ - (CY_GET_XTND_REG8(BL_MD_BTLDB_CHECKSUM_OFFSET(appId))) - -#define BL_MD_BTLDB_ACTIVE_PTR(appId) \ - ((reg8 *)(BL_MD_BTLDB_ACTIVE_OFFSET(appId))) -#define BL_MD_BTLDB_ACTIVE_VALUE(appId) \ - (CY_GET_XTND_REG8(BL_MD_BTLDB_ACTIVE_OFFSET(appId))) - -#define BL_MD_BTLDB_VERIFIED_PTR(appId) \ - ((reg8 *)(BL_MD_BTLDB_VERIFIED_OFFSET(appId))) -#define BL_MD_BTLDB_VERIFIED_VALUE(appId) \ - (CY_GET_XTND_REG8(BL_MD_BTLDB_VERIFIED_OFFSET(appId))) - - -/******************************************************************************* -* Macro for multiple bytes long metadata fields pointers -*******************************************************************************/ -#define BL_MD_BTLDB_ADDR_PTR (appId) \ - ((reg8 *)(BL_MD_BTLDB_ADDR_OFFSET(appId))) - -#define BL_MD_BTLDR_LAST_ROW_PTR (appId) \ - ((reg8 *)(BL_MD_BTLDR_LAST_ROW_OFFSET(appId))) - -#define BL_MD_BTLDB_LENGTH_PTR(appId) \ - ((reg8 *)(BL_MD_BTLDB_LENGTH_OFFSET(appId))) - -#define BL_MD_BTLDR_APP_VERSION_PTR(appId) \ - ((reg8 *)(BL_MD_BTLDR_APP_VERSION_OFFSET(appId))) - -#define BL_MD_BTLDB_APP_ID_PTR(appId) \ - ((reg8 *)(BL_MD_BTLDB_APP_ID_OFFSET(appId))) - -#define BL_MD_BTLDB_APP_VERSION_PTR(appId) \ - ((reg8 *)(BL_MD_BTLDB_APP_VERSION_OFFSET(appId))) - -#define BL_MD_BTLDB_APP_CUST_ID_PTR(appId) \ - ((reg8 *)(BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId))) - - -/******************************************************************************* -* Get data byte from FLASH -*******************************************************************************/ -#if(CY_PSOC3) - #define BL_GET_CODE_BYTE(addr) (*((uint8 CYCODE *) (addr))) -#else - #define BL_GET_CODE_BYTE(addr) (*((uint8 *)(CYDEV_FLASH_BASE + (addr)))) -#endif /* (CY_PSOC3) */ - - -#if(!CY_PSOC4) - #define BL_GET_EEPROM_BYTE(addr) (*((uint8 *)(CYDEV_EE_BASE + (addr)))) -#endif /* (CY_PSOC3) */ - - -/* Our definition of a row size. */ -#if((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0)) - #define BL_FROW_SIZE ((CYDEV_FLS_ROW_SIZE) + (CYDEV_ECC_ROW_SIZE)) -#else - #define BL_FROW_SIZE CYDEV_FLS_ROW_SIZE -#endif /* ((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0)) */ - - -/******************************************************************************* -* Offset of the Bootloader application in flash -*******************************************************************************/ -#if(CY_PSOC4) - #define BL_MD_BTLDR_ADDR_PTR (0xC0u) /* Exclude the vector */ -#else - #define BL_MD_BTLDR_ADDR_PTR (0x00u) -#endif /* (CY_PSOC4) */ - - -/******************************************************************************* -* Maximum number of Bootloadable applications -*******************************************************************************/ -#if(1u == BL_DUAL_APP_BOOTLOADER) - #define BL_MAX_NUM_OF_BTLDB (0x02u) -#else - #define BL_MAX_NUM_OF_BTLDB (0x01u) -#endif /* (1u == BL_DUAL_APP_BOOTLOADER) */ - - -/******************************************************************************* -* Returns TRUE if row specified as parameter contains metadata section -*******************************************************************************/ -#if(0u != BL_DUAL_APP_BOOTLOADER) - #define BL_CONTAIN_METADATA(row) \ - ((BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) || \ - (BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_1) == (row))) -#else - #define BL_CONTAIN_METADATA(row) \ - (BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) -#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - - -/******************************************************************************* -* Metadata section is located at the last flash row for the Boootloader, for the -* Multi-Application Bootloader, metadata section of the Bootloadable application -* # 0 is located at the last flash row, and metadata section of the Bootloadable -* application # 1 is located in the flash row before last. -*******************************************************************************/ -#if(0u != BL_DUAL_APP_BOOTLOADER) - #define BL_GET_APP_ID(row) \ - ((BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) ? \ - BL_MD_BTLDB_ACTIVE_0 : \ - BL_MD_BTLDB_ACTIVE_1) -#else - #define BL_GET_APP_ID(row) (BL_MD_BTLDB_ACTIVE_0) -#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ - -#endif /* CY_BOOTLOADER_BL_PVT_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3Iar.icf b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3Iar.icf deleted file mode 100755 index f5416ec..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3Iar.icf +++ /dev/null @@ -1,113 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x0; -define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2); -define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x0800; -/**** End of ICF editor section. ###ICF###*/ - - -/******** Definitions ********/ -define symbol CY_APPL_LOADABLE = 0; -define symbol CY_APPL_LOADER = 1; -define symbol CY_APPL_NUM = 1; -define symbol CY_APPL_MAX = 1; -define symbol CY_METADATA_SIZE = 64; -define symbol CY_EE_IN_BTLDR = 0x0; -define symbol CY_EE_SIZE = 2048; - -if (!CY_APPL_LOADABLE) { - define symbol CYDEV_BTLDR_SIZE = 0; -} - -define symbol CY_FLASH_SIZE = 131072; -define symbol CY_APPL_ORIGIN = 0; -define symbol CY_FLASH_ROW_SIZE = 256; -define symbol CY_ECC_ROW_SIZE = 32; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -define block HSTACK {block HEAP, last block CSTACK}; - -define block LOADER { readonly section .cybootloader }; -define block APPL with fixed order {readonly section .romvectors, readonly}; - -/* The address of Flash row next after Bootloader image */ -define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + - ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? - (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); - -/* The start address of Standard/Loader/Loadable#1 image */ -define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; - -/* The number of metadata records located at the end of Flash */ -define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); - -/* The application area size measured in rows */ -define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; - -/* The start address of Loadable#2 image if any */ -define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; - -/* The current image (Standard/Loader/Loadable) start address */ -define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; - -/* The ECC data placement address */ -define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; - -/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */ -define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; -define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; - -/* Define EEPROM region */ -define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE]; - -/* Define APPL region that will limit application size */ -define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; - - -/****** Initializations ******/ -initialize by copy { readwrite }; -do not initialize { section .noinit }; -do not initialize { readwrite section .ramvectors }; - -/******** Placements *********/ -".cybootloader" : place at start of ROM_region {block LOADER}; -"APPL" : place at start of APPL_region {block APPL}; - -"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors }; -"readwrite" : place in RAM_region { readwrite }; -"HSTACK" : place at end of RAM_region { block HSTACK}; - -keep { section .cybootloader, - section .cyloadermeta, - section .cyloadablemeta, - section .cyconfigecc, - section .cycustnvl, - section .cywolatch, - section .cyeeprom, - section .cyflashprotect, - section .cymeta }; - -".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta }; -".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta }; -".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc }; -".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl }; -".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch }; -".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom }; -".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -/* EOF */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3RealView.scat b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3RealView.scat deleted file mode 100755 index 7c39f66..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3RealView.scat +++ /dev/null @@ -1,190 +0,0 @@ -#! armcc -E -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************** -;* File Name: Cm3RealView.scat -;* Version 4.0 -;* -;* Description: -;* This Linker Descriptor file describes the memory layout of the PSoC5 -;* device. The memory layout of the final binary and hex images as well as -;* the placement in PSoC5 memory is described. -;* -;* -;* Note: -;* -;* romvectors: Cypress default Interrupt sevice routine vector table. -;* -;* This is the ISR vector table at bootup. Used only for the reset vector. -;* -;* -;* ramvectors: Cypress ram interrupt service routine vector table. -;* -;* This is the ISR vector table used by the application. -;* -;* -;******************************************************************************** -;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -;* You may use this file only in accordance with the license, terms, conditions, -;* disclaimers, and limitations in the end user license agreement accompanying -;* the software package with which this file was provided. -;********************************************************************************/ -#include "cyfitter.h" - -#define CY_FLASH_SIZE 131072 -#define CY_APPL_ORIGIN 0 -#define CY_FLASH_ROW_SIZE 256 -#define CY_ECC_ROW_SIZE 32 -#define CY_EE_SIZE 2048 -#define CY_METADATA_SIZE 64 - - -; Define application base address -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) - #define CY_APPL_NUM 1 - #define CY_APPL_MAX 1 - #define CY_EE_IN_BTLDR - - #if CY_APPL_ORIGIN - #define APPL1_START CY_APPL_ORIGIN - #else - #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) - #endif - - #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) - #define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE) - #define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) - #define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX)) - -#else - - #define APPL_START 0 - #define ECC_OFFSET 0 - #define EE_OFFSET 0 - #define EE_SIZE CY_EE_SIZE - -#endif - - -; Place Bootloader at the beginning of Flash -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) - - CYBOOTLOADER 0 - { - .cybootloader +0 - { - * (.cybootloader) - } - } - - #if CY_APPL_ORIGIN - ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER)) - #endif - -#endif - - -APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) -{ - VECTORS +0 - { - * (.romvectors) - } - - CODE +0 - { - * (+RO) - } - - ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT - { - * (.ramvectors) - } - - NOINIT_DATA +0 UNINIT - { - * (.noinit) - } - - DATA +0 - { - .ANY (+RW, +ZI) - } - - ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0800 - 0x2000) EMPTY 0x0800 - { - } - - ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000 - { - } -} - - -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER) - - CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) - { - .cyloadermeta +0 { * (.cyloadermeta) } - } - -#else - - #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) - - CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) - { - .cyloadablemeta +0 { * (.cyloadablemeta) } - } - - #endif - -#endif - -#if (CYDEV_ECC_ENABLE == 0) - - CYCONFIGECC (0x80000000 + ECC_OFFSET) - { - .cyconfigecc +0 { * (.cyconfigecc) } - } - -#endif - -CYCUSTNVL 0x90000000 -{ - .cycustnvl +0 { * (.cycustnvl) } -} - -CYWOLATCH 0x90100000 -{ - .cywolatch +0 { * (.cywolatch) } -} - -#if defined(CYDEV_ALLOCATE_EEPROM) - - CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE) - { - .cyeeprom +0 { * (.cyeeprom) } - } - -#endif - -CYFLASHPROTECT 0x90400000 -{ - .cyflashprotect +0 { * (.cyflashprotect) } -} - -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) - - CYLOADERMETA +0 - { - .cyloadermeta +0 { * (.cyloadermeta) } - } - -#endif diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3Start.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3Start.c deleted file mode 100755 index f4d6607..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/Cm3Start.c +++ /dev/null @@ -1,461 +0,0 @@ -/******************************************************************************* -* File Name: Cm3Start.c -* Version 4.0 -* -* Description: -* Startup code for the ARM CM3. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include -#include "cydevice_trm.h" -#include "cytypes.h" -#include "cyfitter_cfg.h" -#include "CyLib.h" -#include "CyDmac.h" -#include "cyfitter.h" - -#define CY_NUM_INTERRUPTS (32u) -#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) -#define CY_NUM_ROM_VECTORS (4u) -#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR) -#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL) -#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */ -#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */ -#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */ - - -/* Extern functions */ -extern void CyBtldr_CheckLaunch(void); - -/* Function prototypes */ -void initialize_psoc(void); -CY_ISR(IntDefaultHandler); -void Reset(void); -CY_ISR(IntDefaultHandler); - -#if defined(__ARMCC_VERSION) - #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) -#elif defined (__GNUC__) - #define INITIAL_STACK_POINTER (&__cy_stack) -#elif defined (__ICCARM__) - #pragma language=extended - #pragma segment="CSTACK" - #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } - - extern void __iar_program_start( void ); - extern void __iar_data_init3 (void); -#endif /* (__ARMCC_VERSION) */ - -/* Global variables */ -#if !defined (__ICCARM__) - CY_NOINIT static uint32 cySysNoInitDataValid; -#endif /* !defined (__ICCARM__) */ - - -/******************************************************************************* -* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. -*******************************************************************************/ -#if defined (__ICCARM__) - #pragma location=".ramvectors" - #pragma data_alignment=256 -#else - CY_SECTION(".ramvectors") - CY_ALIGN(256) -#endif /* defined (__ICCARM__) */ -cyisraddress CyRamVectors[CY_NUM_VECTORS]; - - -/******************************************************************************* -* Function Name: IntDefaultHandler -******************************************************************************** -* -* Summary: -* This function is called for all interrupts, other than reset, that get -* called before the system is setup. -* -* Parameters: -* None -* -* Return: -* None -* -* Theory: -* Any value other than zero is acceptable. -* -*******************************************************************************/ -CY_ISR(IntDefaultHandler) -{ - - while(1) - { - /*********************************************************************** - * We should never get here. If we do, a serious problem occured, so go - * into an infinite loop. - ***********************************************************************/ - } -} - - -#if defined(__ARMCC_VERSION) - -/* Local function for the device reset. */ -extern void Reset(void); - -/* Application entry point. */ -extern void $Super$$main(void); - -/* Linker-generated Stack Base addresses, Two Region and One Region */ -extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; - -/* RealView C Library initialization. */ -extern int __main(void); - - -/******************************************************************************* -* Function Name: Reset -******************************************************************************** -* -* Summary: -* This function handles the reset interrupt for the RVDS/MDK toolchains. -* This is the first bit of code that is executed at startup. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void Reset(void) -{ - #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) - - /* For PSoC 5LP, debugging is enabled by default */ - #if(CYDEV_DEBUGGING_ENABLE == 0) - *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; - #endif /* (CYDEV_DEBUGGING_ENABLE) */ - - /* Reset Status Register has Read-to-clear SW access mode. - * Preserve current RESET_SR0 state to make it available for next reading. - */ - *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - - #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ - - #if(CYDEV_BOOTLOADER_ENABLE) - CyBtldr_CheckLaunch(); - #endif /* (CYDEV_BOOTLOADER_ENABLE) */ - - __main(); -} - - -/******************************************************************************* -* Function Name: $Sub$$main -******************************************************************************** -* -* Summary: -* This function is called imediatly before the users main -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void $Sub$$main(void) -{ - initialize_psoc(); - - /* Call original main */ - $Super$$main(); - - while (1) - { - /* If main returns it is undefined what we should do. */ - } -} - -#elif defined(__GNUC__) - -void Start_c(void); - -/* Stack Base address */ -extern void __cy_stack(void); - -/* Application entry point. */ -extern int main(void); - -/* The static objects constructors initializer */ -extern void __libc_init_array(void); - -typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); - -struct __cy_region -{ - __cy_byte_align8 *init; /* Initial contents of this region. */ - __cy_byte_align8 *data; /* Start address of region. */ - size_t init_size; /* Size of initial data. */ - size_t zero_size; /* Additional size to be zeroed. */ -}; - -extern const struct __cy_region __cy_regions[]; -extern const char __cy_region_num __attribute__((weak)); -#define __cy_region_num ((size_t)&__cy_region_num) - - -/******************************************************************************* -* Function Name: Reset -******************************************************************************** -* -* Summary: -* This function handles the reset interrupt for the GCC toolchain. This is the -* first bit of code that is executed at startup. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void Reset(void) -{ - #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) - - /* For PSoC 5LP, debugging is enabled by default */ - #if(CYDEV_DEBUGGING_ENABLE == 0) - *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; - #endif /* (CYDEV_DEBUGGING_ENABLE) */ - - /* Reset Status Register has Read-to-clear SW access mode. - * Preserve current RESET_SR0 state to make it available for next reading. - */ - *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - - #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ - - #if(CYDEV_BOOTLOADER_ENABLE) - CyBtldr_CheckLaunch(); - #endif /* (CYDEV_BOOTLOADER_ENABLE) */ - - Start_c(); -} - -__attribute__((weak)) -void _exit(int status) -{ - /* Cause a divide by 0 exception */ - int x = status / INT_MAX; - x = 4 / x; - - while(1) - { - } -} - -/******************************************************************************* -* Function Name: Start_c -******************************************************************************** -* -* Summary: -* This function handles initializing the .data and .bss sections in -* preperation for running standard C code. Once initialization is complete -* it will call main(). This function will never return. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void Start_c(void) __attribute__ ((noreturn)); -void Start_c(void) -{ - unsigned regions = __cy_region_num; - const struct __cy_region *rptr = __cy_regions; - - /* Initialize memory */ - for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++) - { - uint32 *src = (uint32 *)rptr->init; - uint32 *dst = (uint32 *)rptr->data; - unsigned limit = rptr->init_size; - unsigned count; - - for (count = 0u; count != limit; count += sizeof (uint32)) - { - *dst++ = *src++; - } - limit = rptr->zero_size; - for (count = 0u; count != limit; count += sizeof (uint32)) - { - *dst++ = 0u; - } - } - - /* Invoke static objects constructors */ - __libc_init_array(); - (void) main(); - - while (1) - { - /* If main returns, make sure we don't return. */ - } -} - - -#elif defined (__ICCARM__) - -/******************************************************************************* -* Function Name: __low_level_init -******************************************************************************** -* -* Summary: -* This function perform early initializations for the IAR Embedded -* Workbench IDE. It is executed in the context of reset interrupt handler -* before the data sections are initialized. -* -* Parameters: -* None -* -* Return: -* The value that determines whether or not data sections should be initialized -* by the system startup code: -* 0 - skip data sections initialization; -* 1 - initialize data sections; -* -*******************************************************************************/ -int __low_level_init(void) -{ - #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) - - /* For PSoC 5LP, debugging is enabled by default */ - #if(CYDEV_DEBUGGING_ENABLE == 0) - *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; - #endif /* (CYDEV_DEBUGGING_ENABLE) */ - - /* Reset Status Register has Read-to-clear SW access mode. - * Preserve current RESET_SR0 state to make it available for next reading. - */ - *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - - #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ - - #if (CYDEV_BOOTLOADER_ENABLE) - CyBtldr_CheckLaunch(); - #endif /* CYDEV_BOOTLOADER_ENABLE */ - - /* Initialize data sections */ - __iar_data_init3(); - - initialize_psoc(); - - return 0; -} - -#endif /* __GNUC__ */ - - -/******************************************************************************* -* -* Default Rom Interrupt Vector table. -* -*******************************************************************************/ -#if defined(__ARMCC_VERSION) - /* Suppress diagnostic message 1296-D: extended constant initialiser used */ - #pragma diag_suppress 1296 -#endif /* defined(__ARMCC_VERSION) */ - -#if defined (__ICCARM__) - #pragma location=".romvectors" - const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = -#else - CY_SECTION(".romvectors") - const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = -#endif /* defined (__ICCARM__) */ -{ - INITIAL_STACK_POINTER, /* The initial stack pointer 0 */ - #if defined (__ICCARM__) /* The reset handler 1 */ - __iar_program_start, - #else - (cyisraddress)&Reset, - #endif /* defined (__ICCARM__) */ - &IntDefaultHandler, /* The NMI handler 2 */ - &IntDefaultHandler, /* The hard fault handler 3 */ -}; - -#if defined(__ARMCC_VERSION) - #pragma diag_default 1296 -#endif /* defined(__ARMCC_VERSION) */ - - -/******************************************************************************* -* Function Name: initialize_psoc -******************************************************************************** -* -* Summary: -* This function used to initialize the PSoC chip before calling main. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -#if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) -__attribute__ ((constructor(101))) -#endif -void initialize_psoc(void) -{ - uint32 i; - - /* Set Priority group 5. */ - - /* Writes to NVIC_APINT register require the VECTKEY in the upper half */ - *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5; - *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN; - - /* Set Ram interrupt vectors to default functions. */ - for (i = 0u; i < CY_NUM_VECTORS; i++) - { - #if defined (__ICCARM__) - CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler; - #else - CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; - #endif /* defined (__ICCARM__) */ - } - - /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ - CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); - - /* Point NVIC at the RAM vector table. */ - *CYINT_VECT_TABLE = CyRamVectors; - - /* Initialize the configuration registers. */ - cyfitter_cfg(); - - #if(0u != DMA_CHANNELS_USED__MASK0) - - /* Setup DMA - only necessary if the design contains a DMA component. */ - CyDmacConfigure(); - - #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ - - #if !defined (__ICCARM__) - /* Actually, no need to clean this variable, just to make compiler happy. */ - cySysNoInitDataValid = 0u; - #endif /* !defined (__ICCARM__) */ -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmGnu.s b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmGnu.s deleted file mode 100755 index a8797f7..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmGnu.s +++ /dev/null @@ -1,174 +0,0 @@ -/******************************************************************************* -* File Name: CyBootAsmGnu.s -* Version 4.0 -* -* Description: -* Assembly routines for GNU as. -* -******************************************************************************** -* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -.include "cyfittergnu.inc" - -.syntax unified -.text -.thumb - - -/******************************************************************************* -* Function Name: CyDelayCycles -******************************************************************************** -* -* Summary: -* Delays for the specified number of cycles. -* -* Parameters: -* uint32 cycles: number of cycles to delay. -* -* Return: -* None -* -*******************************************************************************/ -/* void CyDelayCycles(uint32 cycles) */ -.align 3 /* Align to 8 byte boundary (2^n) */ -.global CyDelayCycles -.func CyDelayCycles, CyDelayCycles -.type CyDelayCycles, %function -.thumb_func -CyDelayCycles: /* cycles bytes */ -/* If ICache is enabled */ -.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1 - - ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ - LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ - BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ - NOP /* 1 2 Loop alignment padding */ - -CyDelayCycles_loop: - SUBS r0, r0, #1 /* 1 2 */ - MOV r0, r0 /* 1 2 Pad loop to power of two cycles */ - BNE CyDelayCycles_loop /* 2 2 */ - -CyDelayCycles_done: - BX lr /* 3 2 */ - -.else - - CMP r0, #20 /* 1 2 If delay is short - jump to cycle */ - BLS CyDelayCycles_short /* 1 2 */ - PUSH {r1} /* 2 2 PUSH r1 to stack */ - MOVS r1, #1 /* 1 2 */ - - SUBS r0, r0, #20 /* 1 2 Subtract overhead */ - LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */ - LDRB r1, [r1, #0] /* 2 2 */ - ANDS r1, #0xC0 /* 1 2 */ - - LSRS r1, r1, #6 /* 1 2 */ - PUSH {r2} /* 1 2 PUSH r2 to stack */ - LDR r2, =cy_flash_cycles /* 2 2 */ - LDRB r1, [r2, r1] /* 2 2 */ - - POP {r2} /* 2 2 POP r2 from stack */ - NOP /* 1 2 Alignment padding */ - NOP /* 1 2 Alignment padding */ - NOP /* 1 2 Alignment padding */ - -CyDelayCycles_loop: - SBCS r0, r0, r1 /* 1 2 */ - BPL CyDelayCycles_loop /* 3 2 */ - NOP /* 1 2 Loop alignment padding */ - NOP /* 1 2 Loop alignment padding */ - - POP {r1} /* 2 2 POP r1 from stack */ -CyDelayCycles_done: - BX lr /* 3 2 */ - NOP /* 1 2 Alignment padding */ - NOP /* 1 2 Alignment padding */ - -CyDelayCycles_short: - SBCS r0, r0, #4 /* 1 2 */ - BPL CyDelayCycles_short /* 3 2 */ - BX lr /* 3 2 */ - -cy_flash_cycles: -.byte 0x0B -.byte 0x05 -.byte 0x07 -.byte 0x09 -.endif - -.endfunc - - -/******************************************************************************* -* Function Name: CyEnterCriticalSection -******************************************************************************** -* -* Summary: -* CyEnterCriticalSection disables interrupts and returns a value indicating -* whether interrupts were previously enabled (the actual value depends on -* whether the device is PSoC 3 or PSoC 5). -* -* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit -* with interrupts still enabled. The test and set of the interrupt bits is not -* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid -* corrupting processor state, it must be the policy that all interrupt routines -* restore the interrupt enable bits as they were found on entry. -* -* Parameters: -* None -* -* Return: -* uint8 -* Returns 0 if interrupts were previously enabled or 1 if interrupts -* were previously disabled. -* -*******************************************************************************/ -/* uint8 CyEnterCriticalSection(void) */ -.global CyEnterCriticalSection -.func CyEnterCriticalSection, CyEnterCriticalSection -.type CyEnterCriticalSection, %function -.thumb_func -CyEnterCriticalSection: - MRS r0, PRIMASK /* Save and return interrupt state */ - CPSID I /* Disable interrupts */ - BX lr -.endfunc - - -/******************************************************************************* -* Function Name: CyExitCriticalSection -******************************************************************************** -* -* Summary: -* CyExitCriticalSection re-enables interrupts if they were enabled before -* CyEnterCriticalSection was called. The argument should be the value returned -* from CyEnterCriticalSection. -* -* Parameters: -* uint8 savedIntrStatus: -* Saved interrupt status returned by the CyEnterCriticalSection function. -* -* Return: -* None -* -*******************************************************************************/ -/* void CyExitCriticalSection(uint8 savedIntrStatus) */ -.global CyExitCriticalSection -.func CyExitCriticalSection, CyExitCriticalSection -.type CyExitCriticalSection, %function -.thumb_func -CyExitCriticalSection: - MSR PRIMASK, r0 /* Restore interrupt state */ - BX lr -.endfunc - -.end - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmIar.s b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmIar.s deleted file mode 100755 index 166ba87..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmIar.s +++ /dev/null @@ -1,156 +0,0 @@ -;------------------------------------------------------------------------------- -; FILENAME: CyBootAsmIar.s -; Version 4.0 -; -; DESCRIPTION: -; Assembly routines for IAR Embedded Workbench IDE. -; -;------------------------------------------------------------------------------- -; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying -; the software package with which this file was provided. -;------------------------------------------------------------------------------- - - SECTION .text:CODE:ROOT(4) - PUBLIC CyDelayCycles - PUBLIC CyEnterCriticalSection - PUBLIC CyExitCriticalSection - INCLUDE cyfitteriar.inc - THUMB - - -;------------------------------------------------------------------------------- -; Function Name: CyEnterCriticalSection -;------------------------------------------------------------------------------- -; -; Summary: -; CyEnterCriticalSection disables interrupts and returns a value indicating -; whether interrupts were previously enabled. -; -; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit -; with interrupts still enabled. The test and set of the interrupt bits is not -; atomic. Therefore, to avoid corrupting processor state, it must be the policy -; that all interrupt routines restore the interrupt enable bits as they were -; found on entry. -; -; Parameters: -; None -; -; Return: -; uint8 -; Returns 0 if interrupts were previously enabled or 1 if interrupts -; were previously disabled. -; -;------------------------------------------------------------------------------- -; uint8 CyEnterCriticalSection(void) - -CyEnterCriticalSection: - MRS r0, PRIMASK ; Save and return interrupt state - CPSID I ; Disable interrupts - BX lr - - -;------------------------------------------------------------------------------- -; Function Name: CyExitCriticalSection -;------------------------------------------------------------------------------- -; -; Summary: -; CyExitCriticalSection re-enables interrupts if they were enabled before -; CyEnterCriticalSection was called. The argument should be the value returned -; from CyEnterCriticalSection. -; -; Parameters: -; uint8 savedIntrStatus: -; Saved interrupt status returned by the CyEnterCriticalSection function. -; -; Return: -; None -; -;------------------------------------------------------------------------------- -; void CyExitCriticalSection(uint8 savedIntrStatus) - -CyExitCriticalSection: - MSR PRIMASK, r0 ; Restore interrupt state - BX lr - - -;------------------------------------------------------------------------------- -; Function Name: CyDelayCycles -;------------------------------------------------------------------------------- -; -; Summary: -; Delays for the specified number of cycles. -; -; Parameters: -; uint32 cycles: number of cycles to delay. -; -; Return: -; None -; -;------------------------------------------------------------------------------- -; void CyDelayCycles(uint32 cycles) - -CyDelayCycles: - IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 - ; cycles bytes - ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 - LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags - BEQ CyDelayCycles_done ; 2 2 Skip if 0 - NOP ; 1 2 Loop alignment padding -CyDelayCycles_loop: - SUBS r0, r0, #1 ; 1 2 - MOV r0, r0 ; 1 2 Pad loop to power of two cycles - BNE CyDelayCycles_loop ; 2 2 -CyDelayCycles_done: - BX lr ; 3 2 - - ELSE - - CMP r0, #20 ; 1 2 If delay is short - jump to cycle - BLS CyDelayCycles_short ; 1 2 - PUSH {r1} ; 2 2 PUSH r1 to stack - MOVS r1, #1 ; 1 2 - - SUBS r0, r0, #20 ; 1 2 Subtract overhead - LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value - LDRB r1, [r1, #0] ; 2 2 - ANDS r1, r1, #0xC0 ; 1 2 - - LSRS r1, r1, #6 ; 1 2 - PUSH {r2} ; 1 2 PUSH r2 to stack - LDR r2, =cy_flash_cycles ; 2 2 - LDRB r1, [r2, r1] ; 2 2 - - POP {r2} ; 2 2 POP r2 from stack - NOP ; 1 2 Alignment padding - NOP ; 1 2 Alignment padding - NOP ; 1 2 Alignment padding - -CyDelayCycles_loop: - SBCS r0, r0, r1 ; 1 2 - BPL CyDelayCycles_loop ; 3 2 - NOP ; 1 2 Loop alignment padding - NOP ; 1 2 Loop alignment padding - - POP {r1} ; 2 2 POP r1 from stack -CyDelayCycles_done: - BX lr ; 3 2 - NOP ; 1 2 Alignment padding - NOP ; 1 2 Alignment padding -CyDelayCycles_short: - SBCS r0, r0, #4 ; 1 2 - BPL CyDelayCycles_short ; 3 2 - BX lr ; 3 2 - NOP ; 1 2 Loop alignment padding - - DATA -cy_flash_cycles: -byte_1 DCB 0x0B -byte_2 DCB 0x05 -byte_3 DCB 0x07 -byte_4 DCB 0x09 - - ENDIF - - END diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmRv.s b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmRv.s deleted file mode 100755 index 6c40635..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyBootAsmRv.s +++ /dev/null @@ -1,161 +0,0 @@ -;------------------------------------------------------------------------------- -; FILENAME: CyBootAsmRv.s -; Version 4.0 -; -; DESCRIPTION: -; Assembly routines for RealView. -; -;------------------------------------------------------------------------------- -; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying -; the software package with which this file was provided. -;------------------------------------------------------------------------------- - - AREA |.text|,CODE,ALIGN=3 - THUMB - EXTERN Reset - - GET cyfitterrv.inc - -;------------------------------------------------------------------------------- -; Function Name: CyDelayCycles -;------------------------------------------------------------------------------- -; -; Summary: -; Delays for the specified number of cycles. -; -; Parameters: -; uint32 cycles: number of cycles to delay. -; -; Return: -; None -; -;------------------------------------------------------------------------------- -; void CyDelayCycles(uint32 cycles) - ALIGN 8 -CyDelayCycles FUNCTION - EXPORT CyDelayCycles - IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 - ; cycles bytes - ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 - LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags - BEQ CyDelayCycles_done ; 2 2 Skip if 0 - NOP ; 1 2 Loop alignment padding -CyDelayCycles_loop - SUBS r0, r0, #1 ; 1 2 - MOV r0, r0 ; 1 2 Pad loop to power of two cycles - BNE CyDelayCycles_loop ; 2 2 - NOP ; 1 2 Loop alignment padding -CyDelayCycles_done - BX lr ; 3 2 - - ELSE - - CMP r0, #20 ; 1 2 If delay is short - jump to cycle - BLS CyDelayCycles_short ; 1 2 - PUSH {r1} ; 2 2 PUSH r1 to stack - MOVS r1, #1 ; 1 2 - - SUBS r0, r0, #20 ; 1 2 Subtract overhead - LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value - LDRB r1, [r1, #0] ; 2 2 - ANDS r1, #0xC0 ; 1 2 - - LSRS r1, r1, #6 ; 1 2 - PUSH {r2} ; 1 2 PUSH r2 to stack - LDR r2, =cy_flash_cycles ; 2 2 - LDRB r1, [r2, r1] ; 2 2 - - POP {r2} ; 2 2 POP r2 from stack - NOP ; 1 2 Alignment padding - NOP ; 1 2 Alignment padding - NOP ; 1 2 Alignment padding - -CyDelayCycles_loop - SBCS r0, r0, r1 ; 1 2 - BPL CyDelayCycles_loop ; 3 2 - NOP ; 1 2 Loop alignment padding - NOP ; 1 2 Loop alignment padding - - POP {r1} ; 2 2 POP r1 from stack -CyDelayCycles_done - BX lr ; 3 2 - NOP ; 1 2 Alignment padding - NOP ; 1 2 Alignment padding - -CyDelayCycles_short - SBCS r0, r0, #4 ; 1 2 - BPL CyDelayCycles_short ; 3 2 - BX lr ; 3 2 - -cy_flash_cycles -byte_1 DCB 0x0B -byte_2 DCB 0x05 -byte_3 DCB 0x07 -byte_4 DCB 0x09 - - ENDIF - ENDFUNC - - -;------------------------------------------------------------------------------- -; Function Name: CyEnterCriticalSection -;------------------------------------------------------------------------------- -; -; Summary: -; CyEnterCriticalSection disables interrupts and returns a value indicating -; whether interrupts were previously enabled (the actual value depends on -; whether the device is PSoC 3 or PSoC 5). -; -; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit -; with interrupts still enabled. The test and set of the interrupt bits is not -; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid -; corrupting processor state, it must be the policy that all interrupt routines -; restore the interrupt enable bits as they were found on entry. -; -; Parameters: -; None -; -; Return: -; uint8 -; Returns 0 if interrupts were previously enabled or 1 if interrupts -; were previously disabled. -; -;------------------------------------------------------------------------------- -; uint8 CyEnterCriticalSection(void) -CyEnterCriticalSection FUNCTION - EXPORT CyEnterCriticalSection - MRS r0, PRIMASK ; Save and return interrupt state - CPSID I ; Disable interrupts - BX lr - ENDFUNC - - -;------------------------------------------------------------------------------- -; Function Name: CyExitCriticalSection -;------------------------------------------------------------------------------- -; -; Summary: -; CyExitCriticalSection re-enables interrupts if they were enabled before -; CyEnterCriticalSection was called. The argument should be the value returned -; from CyEnterCriticalSection. -; -; Parameters: -; uint8 savedIntrStatus: -; Saved interrupt status returned by the CyEnterCriticalSection function. -; -; Return: -; None -; -;------------------------------------------------------------------------------- -; void CyExitCriticalSection(uint8 savedIntrStatus) -CyExitCriticalSection FUNCTION - EXPORT CyExitCriticalSection - MSR PRIMASK, r0 ; Restore interrupt state - BX lr - ENDFUNC - - END - -; [] END OF FILE diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyDmac.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyDmac.c deleted file mode 100755 index f4983c3..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyDmac.c +++ /dev/null @@ -1,1131 +0,0 @@ -/******************************************************************************* -* File Name: CyDmac.c -* Version 4.0 -* -* Description: -* Provides an API for the DMAC component. The API includes functions for the -* DMA controller, DMA channels and Transfer Descriptors. -* -* This API is the library version not the auto generated code that gets -* generated when the user places a DMA component on the schematic. -* -* The auto generated code would use the APi's in this module. -* -* Note: -* This code is endian agnostic. -* -* The Transfer Descriptor memory can be used as regular memory if the TD's are -* not being used. -* -* This code uses the first byte of each TD to manage the free list of TD's. -* The user can over write this once the TD is allocated. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "CyDmac.h" - - -/******************************************************************************* -* The following variables are initialized from CyDmacConfigure() function that -* is executed from initialize_psoc() at the early initialization stage. -* In case of IAR EW IDE, initialize_psoc() is executed before the data sections -* are initialized. To avoid zeroing, these variables should be initialized -* properly during segments initialization as well. -*******************************************************************************/ -static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */ -static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */ -static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */ - - -/******************************************************************************* -* Function Name: CyDmacConfigure -******************************************************************************** -* -* Summary: -* Creates a linked list of all the TDs to be allocated. This function is called -* by the startup code; you do not normally need to call it. You could call this -* function if all of the DMA channels are inactive. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyDmacConfigure(void) -{ - uint8 dmaIndex; - - /* Set TD list variables. */ - CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); - CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; - - /* Make TD free list. */ - for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--) - { - CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u); - } - - /* Make the last one point to zero. */ - CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u; -} - - -/******************************************************************************* -* Function Name: CyDmacError -******************************************************************************** -* -* Summary: -* Returns errors of the last failed DMA transaction. -* -* Parameters: -* None -* -* Return: -* Errors of the last failed DMA transaction. -* -* DMAC_PERIPH_ERR: -* Set to 1 when a peripheral responds to a bus transaction with an error -* response. -* -* DMAC_UNPOP_ACC: -* Set to 1 when an access is attempted to an invalid address. -* -* DMAC_BUS_TIMEOUT: -* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values -* are determined by the BUS_TIMEOUT field in the PHUBCFG register. -* -* Theory: -* Once an error occurs the error bits are sticky and are only cleared by a -* write 1 to the error register. -* -*******************************************************************************/ -uint8 CyDmacError(void) -{ - return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR)); -} - - -/******************************************************************************* -* Function Name: CyDmacClearError -******************************************************************************** -* -* Summary: -* Clears the error bits in the error register of the DMAC. -* -* Parameters: -* error: -* Clears the error bits in the DMAC error register. -* -* DMAC_PERIPH_ERR: -* Set to 1 when a peripheral responds to a bus transaction with an error -* response. -* -* DMAC_UNPOP_ACC: -* Set to 1 when an access is attempted to an invalid address. -* -* DMAC_BUS_TIMEOUT: -* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values -* are determined by the BUS_TIMEOUT field in the PHUBCFG register. -* -* Return: -* None -* -* Theory: -* Once an error occurs the error bits are sticky and are only cleared by a -* write 1 to the error register. -* -*******************************************************************************/ -void CyDmacClearError(uint8 error) -{ - *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error)); -} - - -/******************************************************************************* -* Function Name: CyDmacErrorAddress -******************************************************************************** -* -* Summary: -* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the -* address of the error is written to the error address register and can be read -* with this function. -* -* If there are multiple errors, only the address of the first is saved. -* -* Parameters: -* None -* -* Return: -* The address that caused the error. -* -*******************************************************************************/ -uint32 CyDmacErrorAddress(void) -{ - return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR)); -} - - -/******************************************************************************* -* Function Name: CyDmaChAlloc -******************************************************************************** -* -* Summary: -* Allocates a channel from the DMAC to be used in all functions that require a -* channel handle. -* -* Parameters: -* None -* -* Return: -* The allocated channel number. Zero is a valid channel number. -* DMA_INVALID_CHANNEL is returned if there are no channels available. -* -*******************************************************************************/ -uint8 CyDmaChAlloc(void) -{ - uint8 interruptState; - uint8 dmaIndex; - uint32 channel = 1u; - - - /* Enter critical section! */ - interruptState = CyEnterCriticalSection(); - - /* Look for a free channel. */ - for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) - { - if(0uL == (CyDmaChannels & channel)) - { - /* Mark the channel as used. */ - CyDmaChannels |= channel; - break; - } - - channel <<= 1u; - } - - if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS) - { - dmaIndex = CY_DMA_INVALID_CHANNEL; - } - - /* Exit critical section! */ - CyExitCriticalSection(interruptState); - - return(dmaIndex); -} - - -/******************************************************************************* -* Function Name: CyDmaChFree -******************************************************************************** -* -* Summary: -* Frees a channel allocated by DmaChAlloc(). -* -* Parameters: -* uint8 chHandle: -* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChFree(uint8 chHandle) -{ - cystatus status = CYRET_BAD_PARAM; - uint8 interruptState; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - /* Enter critical section */ - interruptState = CyEnterCriticalSection(); - - /* Clear the bit mask that keeps track of ownership. */ - CyDmaChannels &= ~(((uint32) 1u) << chHandle); - - /* Exit critical section */ - CyExitCriticalSection(interruptState); - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChEnable -******************************************************************************** -* -* Summary: -* Enables the DMA channel. A software or hardware request still must happen -* before the channel is executed. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* uint8 preserveTds: -* Preserves the original TD state when the TD has completed. This parameter -* applies to all TDs in the channel. -* -* 0 - When a TD is completed, the DMAC leaves the TD configuration values in -* their current state, and does not restore them to their original state. -* -* 1 - When a TD is completed, the DMAC restores the original configuration -* values of the TD. -* -* When preserveTds is set, the TD slot that equals the channel number becomes -* RESERVED and that becomes where the working registers exist. So, for example, -* if you are using CH06 and preserveTds is set, you are not allowed to use TD -* slot 6. That is reclaimed by the DMA engine for its private use. -* -* Note Do not chain back to a completed TD if the preserveTds for the channel -* is set to 0. When a TD has completed preserveTds for the channel set to 0, -* the transfer count will be at 0. If a TD with a transfer count of 0 is -* started, the TD will transfer an indefinite amount of data. -* -* Take extra precautions when using the hardware request (DRQ) option when the -* preserveTds is set to 0, as you might be requesting the wrong data. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - if (0u != preserveTds) - { - /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to - * preserve the original TD chain - */ - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP; - } - else - { - /* Store the intermediate and final TD states on top of the original TD chain */ - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP); - } - - /* Enable channel */ - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN; - - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChDisable -******************************************************************************** -* -* Summary: -* Disables the DMA channel. Once this function is called, CyDmaChStatus() may -* be called to determine when the channel is disabled and which TDs were being -* executed. -* -* If it is currently executing it will allow the current burst to finish -* naturally. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChDisable(uint8 chHandle) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - /*********************************************************************** - * Should not change configuration information of a DMA channel when it - * is active (or vulnerable to becoming active). - ***********************************************************************/ - - /* Disable channel */ - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN)); - - /* Store the intermediate and final TD states on top of the original TD chain */ - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP)); - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaClearPendingDrq -******************************************************************************** -* -* Summary: -* Clears pending DMA data request. -* -* Parameters: -* uint8 chHandle: -* Handle to the dma channel. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaClearPendingDrq(uint8 chHandle) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN; - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u; - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChPriority -******************************************************************************** -* -* Summary: -* Sets the priority of a DMA channel. You can use this function when you want -* to change the priority at run time. If the priority remains the same for a -* DMA channel, then you can configure the priority in the .cydwr file. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* uint8 priority: -* Priority to set the channel to, 0 - 7. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) -{ - uint8 value; - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); - - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u)); - - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChSetExtendedAddress -******************************************************************************** -* -* Summary: -* Sets the high 16 bits of the source and destination addresses for the DMA -* channel (valid for all TDs in the chain). -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* uint16 source: -* Upper 16 bit address of the DMA transfer source. -* -* uint16 destination: -* Upper 16 bit address of the DMA transfer destination. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ - -{ - cystatus status = CYRET_BAD_PARAM; - reg16 *convert; - - #if(CY_PSOC5) - - /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */ - if(source == 0x1FFFu) - { - source = 0x2000u; - } - - if(destination == 0x1FFFu) - { - destination = 0x2000u; - } - - #endif /* (CY_PSOC5) */ - - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - /* Set source address */ - convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0]; - CY_SET_REG16(convert, source); - - /* Set destination address */ - convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u]; - CY_SET_REG16(convert, destination); - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChSetInitialTd -******************************************************************************** -* -* Summary: -* Sets the initial TD to be executed for the channel when the CyDmaChEnable() -* function is called. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). -* -* uint8 startTd: -* The index of TD to set as the first TD associated with the channel. Zero is -* a valid TD index. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd; - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChSetRequest -******************************************************************************** -* -* Summary: -* Allows the caller to terminate a chain of TDs, terminate one TD, or create a -* direct request to start the DMA channel. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* uint8 request: -* One of the following constants. Each of the constants is a three-bit value. -* -* CPU_REQ - Create a direct request to start the DMA channel -* CPU_TERM_TD - Terminate one TD -* CPU_TERM_CHAIN - Terminate a chain of TDs -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN)); - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChGetRequest -******************************************************************************** -* -* Summary: -* This function allows the caller of CyDmaChSetRequest() to determine if the -* request was completed. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* Return: -* Returns a three-bit field, corresponding to the three bits of the request, -* which describes the state of the previously posted request. If the value is -* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is -* invalid. -* -*******************************************************************************/ -cystatus CyDmaChGetRequest(uint8 chHandle) -{ - cystatus status = CY_DMA_INVALID_CHANNEL; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & - (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChStatus -******************************************************************************** -* -* Summary: -* Determines the status of the DMA channel. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* uint8 * currentTd: -* The address to store the index of the current TD. Can be NULL if the value -* is not needed. -* -* uint8 * state: -* The address to store the state of the channel. Can be NULL if the value is -* not needed. -* -* STATUS_TD_ACTIVE -* 0: Channel is not currently being serviced by DMAC -* 1: Channel is currently being serviced by DMAC -* -* STATUS_CHAIN_ACTIVE -* 0: TD chain is inactive; either no DMA requests have triggered a new chain -* or the previous chain has completed. -* 1: TD chain has been triggered by a DMA request -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -* Theory: -* The caller can check on the activity of the Current TD and the Chain. -* -*******************************************************************************/ -cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - if(NULL != currentTd) - { - *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu; - } - - if(NULL != state) - { - *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; - } - - status = CYRET_SUCCESS; - } - - return (status); -} - - -/******************************************************************************* -* Function Name: CyDmaChSetConfiguration -******************************************************************************** -* -* Summary: -* Sets configuration information of the channel. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). -* -* uint8 burstCount: -* Specifies the size of bursts (1 to 127) the data transfer should be divided -* into. If this value is zero then the whole transfer is done in one burst. -* -* uint8 requestPerBurst: -* The whole of the data can be split into multiple bursts, if this is -* required to complete the transaction: -* 0: All subsequent bursts after the first burst will be automatically -* requested and carried out -* 1: All subsequent bursts after the first burst must also be individually -* requested. -* -* uint8 tdDone0: -* Selects one of the TERMOUT0 interrupt lines to signal completion. The line -* connected to the nrq terminal will determine the TERMOUT0_SEL definition and -* should be used as supplied by cyfitter.h -* -* uint8 tdDone1: -* Selects one of the TERMOUT1 interrupt lines to signal completion. The line -* connected to the nrq terminal will determine the TERMOUT1_SEL definition and -* should be used as supplied by cyfitter.h -* -* uint8 tdStop: -* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD -* should terminate. The signal connected to the trq terminal will determine -* which TERMIN (termination request) is used. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, - uint8 tdDone0, uint8 tdDone1, uint8 tdStop) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u)); - CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu); - CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; - CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */ - - status = CYRET_SUCCESS; - } - - return (status); -} - - -/******************************************************************************* -* Function Name: CyDmaTdAllocate -******************************************************************************** -* -* Summary: -* Allocates a TD for use with an allocated DMA channel. -* -* Parameters: -* None -* -* Return: -* Zero-based index of the TD to be used by the caller. Since there are 128 TDs -* minus the reserved TDs (0 to 23), the value returned would range from 24 to -* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs -* available. -* -*******************************************************************************/ -uint8 CyDmaTdAllocate(void) -{ - uint8 interruptState; - uint8 element = CY_DMA_INVALID_TD; - - /* Enter critical section! */ - interruptState = CyEnterCriticalSection(); - - if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS) - { - /* Get pointer to the Next available. */ - element = CyDmaTdFreeIndex; - - /* Decrement the count. */ - CyDmaTdCurrentNumber--; - - /* Update the next available pointer. */ - CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0]; - } - - /* Exit critical section! */ - CyExitCriticalSection(interruptState); - - return(element); -} - - -/******************************************************************************* -* Function Name: CyDmaTdFree -******************************************************************************** -* -* Summary: -* Returns a TD to the free list. -* -* Parameters: -* uint8 tdHandle: -* The TD handle returned by the CyDmaTdAllocate(). -* -* Return: -* None -* -*******************************************************************************/ -void CyDmaTdFree(uint8 tdHandle) -{ - if(tdHandle < CY_DMA_NUMBEROF_TDS) - { - /* Enter critical section! */ - uint8 interruptState = CyEnterCriticalSection(); - - /* Get pointer to the Next available. */ - CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; - - /* Set new Next Available. */ - CyDmaTdFreeIndex = tdHandle; - - /* Keep track of how many left. */ - CyDmaTdCurrentNumber++; - - /* Exit critical section! */ - CyExitCriticalSection(interruptState); - } -} - - -/******************************************************************************* -* Function Name: CyDmaTdFreeCount -******************************************************************************** -* -* Summary: -* Returns the number of free TDs available to be allocated. -* -* Parameters: -* None -* -* Return: -* The number of free TDs. -* -*******************************************************************************/ -uint8 CyDmaTdFreeCount(void) -{ - return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS); -} - - -/******************************************************************************* -* Function Name: CyDmaTdSetConfiguration -******************************************************************************** -* -* Summary: -* Configures the TD. -* -* Parameters: -* uint8 tdHandle: -* A handle previously returned by CyDmaTdAlloc(). -* -* uint16 transferCount: -* The size of the data transfer (in bytes) for this TD. A size of zero will -* cause the transfer to continue indefinitely. This parameter is limited to -* 4095 bytes; the TD is not initialized at all when a higher value is passed. -* -* uint8 nextTd: -* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a -* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. -* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No -* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and -* PSoC 5LP silicons. -* -* uint8 configuration: -* Stores the Bit field of configuration bits. -* -* CY_DMA_TD_SWAP_EN - Perform endian swap -* -* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes -* -* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger -* automatically when the current TD completes. -* -* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq -* input line occurs. The positive edge must occur -* during a burst. That is the only time the DMAC -* will listen for it. -* -* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will -* generate a pulse. Note that this option is -* instance specific with the instance name followed -* by two underscores. In this example, the instance -* name is DMA. -* -* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each -* data transaction in the burst. -* -* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each -* data transaction in the burst. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if tdHandle or transferCount is invalid. -* -*******************************************************************************/ -cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \ - -{ - cystatus status = CYRET_BAD_PARAM; - - if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount))) - { - /* Set 12 bits transfer count. */ - reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u]; - CY_SET_REG16(convert, transferCount); - - /* Set Next TD pointer. */ - CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; - - /* Configure the TD */ - CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; - - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaTdGetConfiguration -******************************************************************************** -* -* Summary: -* Retrieves the configuration of the TD. If a NULL pointer is passed as a -* parameter, that parameter is skipped. You may request only the values you are -* interested in. -* -* Parameters: -* uint8 tdHandle: -* A handle previously returned by CyDmaTdAlloc(). -* -* uint16 * transferCount: -* The address to store the size of the data transfer (in bytes) for this TD. -* A size of zero could indicate that the TD has completed its transfer, or -* that the TD is doing an indefinite transfer. -* -* uint8 * nextTd: -* The address to store the index of the next TD in the TD chain. -* -* uint8 * configuration: -* The address to store the Bit field of configuration bits. -* See CyDmaTdSetConfiguration() function description. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if tdHandle is invalid. -* -* Side Effects: -* If a TD has a transfer count of N and is executed, the transfer count becomes -* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a -* request for indefinite transfer. Be careful when requesting a TD with a -* transfer count of zero. -* -*******************************************************************************/ -cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \ - -{ - cystatus status = CYRET_BAD_PARAM; - - if(tdHandle < CY_DMA_NUMBEROF_TDS) - { - /* If we have a pointer */ - if(NULL != transferCount) - { - /* Get the 12 bits of the transfer count */ - reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0]; - *transferCount = 0x0FFFu & CY_GET_REG16(convert); - } - - /* If we have a pointer */ - if(NULL != nextTd) - { - /* Get the Next TD pointer */ - *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u]; - } - - /* If we have a pointer */ - if(NULL != configuration) - { - /* Get the configuration the TD */ - *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u]; - } - - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaTdSetAddress -******************************************************************************** -* -* Summary: -* Sets the lower 16 bits of the source and destination addresses for this TD -* only. -* -* Parameters: -* uint8 tdHandle: -* A handle previously returned by CyDmaTdAlloc(). -* -* uint16 source: -* The lower 16 address bits of the source of the data transfer. -* -* uint16 destination: -* The lower 16 address bits of the destination of the data transfer. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if tdHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) -{ - cystatus status = CYRET_BAD_PARAM; - reg16 *convert; - - if(tdHandle < CY_DMA_NUMBEROF_TDS) - { - /* Set source address */ - convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; - CY_SET_REG16(convert, source); - - /* Set destination address */ - convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; - CY_SET_REG16(convert, destination); - - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaTdGetAddress -******************************************************************************** -* -* Summary: -* Retrieves the lower 16 bits of the source and/or destination addresses for -* this TD only. If NULL is passed for a pointer parameter, that value is -* skipped. You may request only the values of interest. -* -* Parameters: -* uint8 tdHandle: -* A handle previously returned by CyDmaTdAlloc(). -* -* uint16 * source: -* The address to store the lower 16 address bits of the source of the data -* transfer. -* -* uint16 * destination: -* The address to store the lower 16 address bits of the destination of the -* data transfer. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if tdHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) -{ - cystatus status = CYRET_BAD_PARAM; - reg16 *convert; - - if(tdHandle < CY_DMA_NUMBEROF_TDS) - { - /* If we have a pointer. */ - if(NULL != source) - { - /* Get source address */ - convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; - *source = CY_GET_REG16(convert); - } - - /* If we have a pointer. */ - if(NULL != destination) - { - /* Get Destination address. */ - convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; - *destination = CY_GET_REG16(convert); - } - - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyDmaChRoundRobin -******************************************************************************** -* -* Summary: -* Either enables or disables the Round-Robin scheduling enforcement algorithm. -* Within a priority level a Round-Robin fairness algorithm is enforced. -* -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). -* -* uint8 enableRR: -* 0: Disable Round-Robin fairness algorithm -* 1: Enable Round-Robin fairness algorithm -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. -* -*******************************************************************************/ -cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) -{ - cystatus status = CYRET_BAD_PARAM; - - if(chHandle < CY_DMA_NUMBEROF_CHANNELS) - { - if (0u != enableRR) - { - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE; - } - else - { - CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE); - } - - status = CYRET_SUCCESS; - } - - return(status); -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyDmac.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyDmac.h deleted file mode 100755 index 6a3ee85..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyDmac.h +++ /dev/null @@ -1,218 +0,0 @@ -/******************************************************************************* -* File Name: CyDmac.h -* Version 4.0 -* -* Description: -* Provides the function definitions for the DMA Controller. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOT_CYDMAC_H) -#define CY_BOOT_CYDMAC_H - - -#include "cytypes.h" -#include "cyfitter.h" -#include "cydevice_trm.h" -#include "CyLib.h" - - -/*************************************** -* Function Prototypes -***************************************/ - -/* DMA Controller functions. */ -void CyDmacConfigure(void) ; -uint8 CyDmacError(void) ; -void CyDmacClearError(uint8 error) ; -uint32 CyDmacErrorAddress(void) ; - -/* Channel specific functions. */ -uint8 CyDmaChAlloc(void) ; -cystatus CyDmaChFree(uint8 chHandle) ; -cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ; -cystatus CyDmaChDisable(uint8 chHandle) ; -cystatus CyDmaClearPendingDrq(uint8 chHandle) ; -cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ; -cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\ -; -cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ; -cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ; -cystatus CyDmaChGetRequest(uint8 chHandle) ; -cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ; -cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, - uint8 tdDone1, uint8 tdStop) ; -cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ; - -/* Transfer Descriptor functions. */ -uint8 CyDmaTdAllocate(void) ; -void CyDmaTdFree(uint8 tdHandle) ; -uint8 CyDmaTdFreeCount(void) ; -cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\ -; -cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\ -; -cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ; -cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ; - - -/*************************************** -* Data Struct Definitions -***************************************/ - -typedef struct dmac_ch_struct -{ - volatile uint8 basic_cfg[4]; - volatile uint8 action[4]; - volatile uint8 basic_status[4]; - volatile uint8 reserved[4]; - -} dmac_ch; - - -typedef struct dmac_cfgmem_struct -{ - volatile uint8 CFG0[4]; - volatile uint8 CFG1[4]; - -} dmac_cfgmem; - - -typedef struct dmac_tdmem_struct -{ - volatile uint8 TD0[4]; - volatile uint8 TD1[4]; - -} dmac_tdmem; - - -typedef struct dmac_tdmem2_struct -{ - volatile uint16 xfercnt; - volatile uint8 next_td_ptr; - volatile uint8 flags; - volatile uint16 src_adr; - volatile uint16 dst_adr; -} dmac_tdmem2; - - -/*************************************** -* API Constants -***************************************/ - -#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */ -#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ -#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ -#define CY_DMA_DISABLE_TD 0xFEu - -#define CY_DMA_TD_SIZE 0x08u - -/* The "u" was removed as workaround for Keil compiler bug */ -#define CY_DMA_TD_SWAP_EN 0x80 -#define CY_DMA_TD_SWAP_SIZE4 0x40 -#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20 -#define CY_DMA_TD_TERMIN_EN 0x10 -#define CY_DMA_TD_TERMOUT1_EN 0x08 -#define CY_DMA_TD_TERMOUT0_EN 0x04 -#define CY_DMA_TD_INC_DST_ADR 0x02 -#define CY_DMA_TD_INC_SRC_ADR 0x01 - -#define CY_DMA_NUMBEROF_TDS 128u -#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE)) - -/* Action register bits */ -#define CY_DMA_CPU_REQ ((uint8)(1u << 0u)) -#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u)) -#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u)) - -/* Basic Status register bits */ -#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u)) -#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u)) - -/* DMA controller register error bits */ -#define CY_DMA_BUS_TIMEOUT (1u << 1u) -#define CY_DMA_UNPOP_ACC (1u << 2u) -#define CY_DMA_PERIPH_ERR (1u << 3u) - -/* Round robin bits */ -#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u)) - - -/******************************************************************************* -* CyDmaChEnable() / CyDmaChDisable() API constants -*******************************************************************************/ -#define CY_DMA_CH_BASIC_CFG_EN (0x01u) -#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u) - - -/*************************************** -* Registers -***************************************/ - -#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG) -#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG) - -#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR) -#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR) - -#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR) -#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR) - -#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) -#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) - -#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) -#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) - -#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) -#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 -*******************************************************************************/ -#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL) -#define DMA_INVALID_TD (CY_DMA_INVALID_TD) -#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD) -#define DMAC_TD_SIZE (CY_DMA_TD_SIZE) -#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN) -#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4) -#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT) -#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN) -#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN) -#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN) -#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR) -#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR) -#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS) -#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS) -#define CPU_REQ (CY_DMA_CPU_REQ) -#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD) -#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN) -#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE) -#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE) -#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT) -#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) -#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) -#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) -#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) - -#define DMAC_CFG (CY_DMA_CFG_PTR) -#define DMAC_ERR (CY_DMA_ERR_PTR) -#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR) -#define DMAC_CH (CY_DMA_CH_STRUCT_PTR) -#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR) -#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR) - -#endif /* (CY_BOOT_CYDMAC_H) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyFlash.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyFlash.c deleted file mode 100755 index e692e66..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyFlash.c +++ /dev/null @@ -1,694 +0,0 @@ -/******************************************************************************* -* File Name: CyFlash.c -* Version 4.0 -* -* Description: -* Provides an API for the FLASH/EEPROM. -* -* Note: -* This code is endian agnostic. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "CyFlash.h" - - -/******************************************************************************* -* Holds die temperature, updated by CySetTemp(). Used for flash writting. -* The first byte is the sign of the temperature (0 = negative, 1 = positive). -* The second byte is the magnitude. -*******************************************************************************/ -uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; - -#if(CYDEV_ECC_ENABLE == 0) - static uint8 * rowBuffer = 0; -#endif /* (CYDEV_ECC_ENABLE == 0) */ - - -static cystatus CySetTempInt(void); - - -/******************************************************************************* -* Function Name: CyFlash_Start -******************************************************************************** -* -* Summary: -* Enable the Flash. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyFlash_Start(void) -{ - /* Active Power Mode */ - *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; - - /* Standby Power Mode */ - *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK; - - CyDelayUs(CY_FLASH_EE_STARTUP_DELAY); -} - - -/******************************************************************************* -* Function Name: CyFlash_Stop -******************************************************************************** -* -* Summary: -* Disable the Flash. -* -* Parameters: -* None -* -* Return: -* None -* -* Side Effects: -* This setting is ignored as long as the CPU is currently running. This will -* only take effect when the CPU is later disabled. -* -*******************************************************************************/ -void CyFlash_Stop(void) -{ - /* Active Power Mode */ - *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); - - /* Standby Power Mode */ - *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK)); -} - - -/******************************************************************************* -* Function Name: CySetTempInt -******************************************************************************** -* -* Summary: -* Sends a command to the SPC to read the die temperature. Sets a global value -* used by the Write functions. This function must be called once before -* executing a series of Flash writing functions. -* -* Parameters: -* None -* -* Return: -* status: -* CYRET_SUCCESS - if successful -* CYRET_LOCKED - if Flash writing already in use -* CYRET_UNKNOWN - if there was an SPC error -* -*******************************************************************************/ -static cystatus CySetTempInt(void) -{ - cystatus status; - - /* Make sure SPC is powered */ - CySpcStart(); - - /* Plan for failure. */ - status = CYRET_UNKNOWN; - - if(CySpcLock() == CYRET_SUCCESS) - { - /* Write the command. */ - if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) - { - do - { - if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE) - { - status = CYRET_SUCCESS; - - while(CY_SPC_BUSY) - { - /* Spin until idle. */ - CyDelayUs(1u); - } - break; - } - - } while(CY_SPC_BUSY); - } - - CySpcUnlock(); - } - else - { - status = CYRET_LOCKED; - } - - return (status); -} - - -/******************************************************************************* -* Function Name: CySetTemp -******************************************************************************** -* -* Summary: -* This is a wraparound for CySetTempInt(). It is used to return second -* successful read of temperature value. -* -* Parameters: -* None -* -* Return: -* status: -* CYRET_SUCCESS if successful. -* CYRET_LOCKED if Flash writing already in use -* CYRET_UNKNOWN if there was an SPC error. -* -* uint8 dieTemperature[2]: -* Holds die temperature for the flash writting algorithm. The first byte is -* the sign of the temperature (0 = negative, 1 = positive). The second byte is -* the magnitude. -* -*******************************************************************************/ -cystatus CySetTemp(void) -{ - cystatus status = CySetTempInt(); - - if(status == CYRET_SUCCESS) - { - status = CySetTempInt(); - } - - return (status); -} - - -/******************************************************************************* -* Function Name: CySetFlashEEBuffer -******************************************************************************** -* -* Summary: -* Sets the user supplied temporary buffer to store SPC data while performing -* flash and EEPROM commands. This buffer is only necessary when Flash ECC is -* disabled. -* -* Parameters: -* buffer: -* Address of block of memory to store temporary memory. The size of the block -* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. -* -* Return: -* status: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if the buffer is NULL -* -*******************************************************************************/ -cystatus CySetFlashEEBuffer(uint8 * buffer) -{ - cystatus status = CYRET_SUCCESS; - - CySpcStart(); - - #if(CYDEV_ECC_ENABLE == 0) - - if(NULL == buffer) - { - status = CYRET_BAD_PARAM; - } - else if(CySpcLock() != CYRET_SUCCESS) - { - status = CYRET_LOCKED; - } - else - { - rowBuffer = buffer; - CySpcUnlock(); - } - - #else - - /* To supress the warning */ - buffer = buffer; - - #endif /* (CYDEV_ECC_ENABLE == 0u) */ - - return(status); -} - - -#if(CYDEV_ECC_ENABLE == 1) - - /******************************************************************************* - * Function Name: CyWriteRowData - ******************************************************************************** - * - * Summary: - * Sends a command to the SPC to load and program a row of data in - * Flash or EEPROM. - * - * Parameters: - * arrayID: ID of the array to write. - * The type of write, Flash or EEPROM, is determined from the array ID. - * The arrays in the part are sequential starting at the first ID for the - * specific memory type. The array ID for the Flash memory lasts from 0x00 to - * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. - * rowAddress: rowAddress of flash row to program. - * rowData: Array of bytes to write. - * - * Return: - * status: - * CYRET_SUCCESS if successful. - * CYRET_LOCKED if the SPC is already in use. - * CYRET_CANCELED if command not accepted - * CYRET_UNKNOWN if there was an SPC error. - * - *******************************************************************************/ - cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) - { - uint16 rowSize; - cystatus status; - - rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE; - status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); - - return(status); - } - -#else - - /******************************************************************************* - * Function Name: CyWriteRowData - ******************************************************************************** - * - * Summary: - * Sends a command to the SPC to load and program a row of data in - * Flash or EEPROM. - * - * Parameters: - * arrayID : ID of the array to write. - * The type of write, Flash or EEPROM, is determined from the array ID. - * The arrays in the part are sequential starting at the first ID for the - * specific memory type. The array ID for the Flash memory lasts from 0x00 to - * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. - * rowAddress : rowAddress of flash row to program. - * rowData : Array of bytes to write. - * - * Return: - * status: - * CYRET_SUCCESS if successful. - * CYRET_LOCKED if the SPC is already in use. - * CYRET_CANCELED if command not accepted - * CYRET_UNKNOWN if there was an SPC error. - * - *******************************************************************************/ - cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) - { - uint8 i; - uint32 offset; - uint16 rowSize; - cystatus status; - - /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ - if(NULL != rowBuffer) - { - if(arrayId > CY_SPC_LAST_FLASH_ARRAYID) - { - rowSize = CYDEV_EEPROM_ROW_SIZE; - } - else - { - rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE; - - /* Save the ECC area. */ - offset = CYDEV_ECC_BASE + - ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) + - ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE); - - for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) - { - *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); - } - } - - /* Copy the rowdata to the temporary buffer. */ - #if(CY_PSOC3) - (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE); - #else - (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE); - #endif /* (CY_PSOC3) */ - - status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize); - } - else - { - status = CYRET_UNKNOWN; - } - - return(status); - } - -#endif /* (CYDEV_ECC_ENABLE == 0u) */ - - -#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) - - /******************************************************************************* - * Function Name: CyWriteRowConfig - ******************************************************************************** - * - * Summary: - * Sends a command to the SPC to load and program a row of config data in flash. - * This function is only valid for Flash array IDs (not for EEPROM). - * - * Parameters: - * arrayId: ID of the array to write - * The arrays in the part are sequential starting at the first ID for the - * specific memory type. The array ID for the Flash memory lasts - * from 0x00 to 0x3F. - * rowAddress: Address of the sector to erase. - * rowECC: Array of bytes to write. - * - * Return: - * status: - * CYRET_SUCCESS if successful. - * CYRET_LOCKED if the SPC is already in use. - * CYRET_CANCELED if command not accepted - * CYRET_UNKNOWN if there was an SPC error. - * - *******************************************************************************/ - cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\ - - { - uint32 offset; - uint16 i; - cystatus status; - - /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */ - if(NULL != rowBuffer) - { - /* Read the existing flash data. */ - offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) + - ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE); - - #if (CYDEV_FLS_BASE != 0u) - offset += CYDEV_FLS_BASE; - #endif /* (CYDEV_FLS_BASE != 0u) */ - - for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) - { - rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); - } - - #if(CY_PSOC3) - (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], - (void *)(uint32)rowECC, - (int16)CYDEV_ECC_ROW_SIZE); - #else - (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE], - (const void *)rowECC, - CYDEV_ECC_ROW_SIZE); - #endif /* (CY_PSOC3) */ - - status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE); - } - else - { - status = CYRET_UNKNOWN; - } - - return (status); - } - -#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ - - - -/******************************************************************************* -* Function Name: CyWriteRowFull -******************************************************************************** -* Summary: -* Sends a command to the SPC to load and program a row of data in flash. -* rowData array is expected to contain Flash and ECC data if needed. -* -* Parameters: -* arrayId: FLASH or EEPROM array id. -* rowData: Pointer to a row of data to write. -* rowNumber: Zero based number of the row. -* rowSize: Size of the row. -* -* Return: -* CYRET_SUCCESS if successful. -* CYRET_LOCKED if the SPC is already in use. -* CYRET_CANCELED if command not accepted -* CYRET_UNKNOWN if there was an SPC error. -* -*******************************************************************************/ -cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ - -{ - cystatus status; - - if(CySpcLock() == CYRET_SUCCESS) - { - /* Load row data into SPC internal latch */ - status = CySpcLoadRow(arrayId, rowData, rowSize); - - if(CYRET_STARTED == status) - { - while(CY_SPC_BUSY) - { - /* Wait for SPC to finish and get SPC status */ - CyDelayUs(1u); - } - - /* Hide SPC status */ - if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) - { - status = CYRET_SUCCESS; - } - else - { - status = CYRET_UNKNOWN; - } - - if(CYRET_SUCCESS == status) - { - /* Erase and program flash with the data from SPC interval latch */ - status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); - - if(CYRET_STARTED == status) - { - while(CY_SPC_BUSY) - { - /* Wait for SPC to finish and get SPC status */ - CyDelayUs(1u); - } - - /* Hide SPC status */ - if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) - { - status = CYRET_SUCCESS; - } - else - { - status = CYRET_UNKNOWN; - } - } - } - - } - - CySpcUnlock(); - } - else - { - status = CYRET_LOCKED; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyFlash_SetWaitCycles -******************************************************************************** -* -* Summary: -* Sets the number of clock cycles the cache will wait before it samples data -* coming back from Flash. This function must be called before increasing CPU -* clock frequency. It can optionally be called after lowering CPU clock -* frequency in order to improve CPU performance. -* -* Parameters: -* uint8 freq: -* Frequency of operation in Megahertz. -* -* Return: -* None -* -*******************************************************************************/ -void CyFlash_SetWaitCycles(uint8 freq) -{ - uint8 interruptState; - - /* Save current global interrupt enable and disable it */ - interruptState = CyEnterCriticalSection(); - - /*************************************************************************** - * The number of clock cycles the cache will wait before it samples data - * coming back from Flash must be equal or greater to to the CPU frequency - * outlined in clock cycles. - ***************************************************************************/ - - #if (CY_PSOC3) - - if (freq <= 22u) - { - *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - } - else if (freq <= 44u) - { - *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - } - else - { - *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - } - - #endif /* (CY_PSOC3) */ - - - #if (CY_PSOC5) - - if (freq <= 16u) - { - *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - } - else if (freq <= 33u) - { - *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - } - else if (freq <= 50u) - { - *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - } - else - { - *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) | - ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT))); - } - - #endif /* (CY_PSOC5) */ - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: CyEEPROM_Start -******************************************************************************** -* -* Summary: -* Enable the EEPROM. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyEEPROM_Start(void) -{ - /* Active Power Mode */ - *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; - - /* Standby Power Mode */ - *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK; -} - - -/******************************************************************************* -* Function Name: CyEEPROM_Stop -******************************************************************************** -* -* Summary: -* Disable the EEPROM. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyEEPROM_Stop (void) -{ - /* Active Power Mode */ - *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); - - /* Standby Power Mode */ - *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK)); -} - - -/******************************************************************************* -* Function Name: CyEEPROM_ReadReserve -******************************************************************************** -* -* Summary: -* Request access to the EEPROM for reading and wait until access is available. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyEEPROM_ReadReserve(void) -{ - /* Make a request for PHUB to have access */ - *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ; - - while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK)) - { - /* Wait for acknowledgement from PHUB */ - } -} - - -/******************************************************************************* -* Function Name: CyEEPROM_ReadRelease -******************************************************************************** -* -* Summary: -* Release the read reservation of the EEPROM. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyEEPROM_ReadRelease(void) -{ - *CY_FLASH_EE_SCR_PTR |= 0x00u; -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyFlash.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyFlash.h deleted file mode 100755 index 69f8c88..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyFlash.h +++ /dev/null @@ -1,239 +0,0 @@ -/******************************************************************************* -* File Name: CyFlash.h -* Version 4.0 -* -* Description: -* Provides the function definitions for the FLASH/EEPROM. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOT_CYFLASH_H) -#define CY_BOOT_CYFLASH_H - -#include "cydevice_trm.h" -#include "cytypes.h" -#include "CyLib.h" -#include "CySpc.h" - -#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */ - -extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; - - -/*************************************** -* API Constants -***************************************/ - -#define CY_FLASH_BASE (CYDEV_FLASH_BASE) -#define CY_FLASH_SIZE (CYDEV_FLS_SIZE) -#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) -#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) -#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) -#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE) -#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE) - -#define CY_EEPROM_BASE (CYDEV_EE_BASE) -#define CY_EEPROM_SIZE (CYDEV_EE_SIZE) -#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE) -#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) -#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE) -#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) - - -#if !defined(CYDEV_FLS_BASE) - #define CYDEV_FLS_BASE CYDEV_FLASH_BASE -#endif /* !defined(CYDEV_FLS_BASE) */ - - -/*************************************** -* Function Prototypes -***************************************/ - -/* Flash Functions */ -void CyFlash_Start(void); -void CyFlash_Stop(void); -cystatus CySetTemp(void); -cystatus CySetFlashEEBuffer(uint8 * buffer); -cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \ - ; -cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); - -#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) - cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ - ; -#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ - -void CyFlash_SetWaitCycles(uint8 freq) ; - -/* EEPROM Functions */ -void CyEEPROM_Start(void) ; -void CyEEPROM_Stop(void) ; - -void CyEEPROM_ReadReserve(void) ; -void CyEEPROM_ReadRelease(void) ; - - -/*************************************** -* Registers -***************************************/ -/* Active Power Mode Configuration Register 12 */ -#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12) -#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) - -/* Alternate Active Power Mode Configuration Register 12 */ -#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12) -#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) - - -/* Cache Control Register */ -#if (CY_PSOC3) - - #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR ) - #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR ) - -#else - - #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) - #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) - -#endif /* (CY_PSOC3) */ - - -/* EEPROM Status & Control Register */ -#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR) -#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) - - - -/*************************************** -* Register Constants -***************************************/ - -/* Power Mode Masks */ -#define CY_FLASH_PM_EE_MASK (0x10u) -#define CY_FLASH_PM_FLASH_MASK (0x01u) - -/* Frequency Constants */ -#if (CY_PSOC3) - - #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u) - #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u) - #define CY_FLASH_GREATER_44MHz (0x03u) - -#endif /* (CY_PSOC3) */ - -#if (CY_PSOC5) - - #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) - #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) - #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) - #define CY_FLASH_GREATER_51MHz (0x00u) - -#endif /* (CY_PSOC5) */ - -#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u) -#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT))) -#define CY_FLASH_EE_STARTUP_DELAY (5u) - -#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u) -#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u) - - - -/* Default values for getting temperature. */ - -#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u) -#define CY_TEMP_TIMER_PERIOD (0xFFFu) -#define CY_TEMP_CLK_DIV_SELECT (0x4u) -#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES)) -#define CY_SPC_CLK_PERIOD (120u) /* nS */ -#define CY_SYS_ns_PER_TICK (1000u) -#define CY_FRM_EXEC_TIME (1000u) /* nS */ - -#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \ - (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \ - CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME) - -#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */ - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 -*******************************************************************************/ -#define FLASH_SIZE (CY_FLASH_SIZE) -#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY) -#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) -#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) -#define EEPROM_SIZE (CY_EEPROM_SIZE) -#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) -#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) -#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) -#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) -#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 -*******************************************************************************/ -#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR) - -#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES) -#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD) -#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT) -#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES) -#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD) -#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME) -#define GET_TEMP_TIME (CY_GET_TEMP_TIME) -#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT) - -#define ECC_ADDR (0x80u) - - -#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) -#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) - -#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) -#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) - -#define PM_EE_MASK (CY_FLASH_PM_EE_MASK) -#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK) - -#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT) -#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK) - - -#if (CY_PSOC3) - - #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz) - #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz) - #define GREATER_44MHz (CY_FLASH_GREATER_44MHz) - -#endif /* (CY_PSOC3) */ - -#if (CY_PSOC5) - - #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) - #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) - #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) - #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz) - #define GREATER_67MHz (CY_FLASH_GREATER_67MHz) - #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) - -#endif /* (CY_PSOC5) */ - -#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR) - - -#endif /* (CY_BOOT_CYFLASH_H) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyLib.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyLib.c deleted file mode 100755 index 206c6cb..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyLib.c +++ /dev/null @@ -1,2710 +0,0 @@ -/******************************************************************************* -* File Name: CyLib.c -* Version 4.0 -* -* Description: -* Provides system API for the clocking, interrupts and watchdog timer. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "CyLib.h" - - -/******************************************************************************* -* The CyResetStatus variable is used to obtain value of RESET_SR0 register after -* a device reset. It is set from initialize_psoc() at the early initialization -* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data -* sections are initialized. To avoid zeroing, CyResetStatus should be placed -* to the .noinit section. -*******************************************************************************/ -CY_NOINIT uint8 CYXDATA CyResetStatus; - - -/* Variable Vdda */ -#if(CYDEV_VARIABLE_VDDA == 1) - - uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700); - -#endif /* (CYDEV_VARIABLE_VDDA == 1) */ - - -/* Do not use these definitions directly in your application */ -uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ; -uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u; -uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u); -uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u); - - -/* Function Prototypes */ -static uint8 CyUSB_PowerOnCheck(void) ; -static void CyIMO_SetTrimValue(uint8 freq) ; -static void CyBusClk_Internal_SetDivider(uint16 divider); - - -/******************************************************************************* -* Function Name: CyPLL_OUT_Start -******************************************************************************** -* -* Summary: -* Enables the PLL. Optionally waits for it to become stable. -* Waits at least 250 us or until it is detected that the PLL is stable. -* -* Parameters: -* wait: -* 0: Return immediately after configuration -* 1: Wait for PLL lock or timeout. -* -* Return: -* Status -* CYRET_SUCCESS - Completed successfully -* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. -* If the input source of the clock is jittery, then the lock indication -* may not occur. However, after the timeout has expired the generated PLL -* clock can still be used. -* -* Side Effects: -* If wait is enabled: This function wses the Fast Time Wheel to time the wait. -* Any other use of the Fast Time Wheel will be stopped during the period of -* this function and then restored. This function also uses the 100 KHz ILO. -* If not enabled, this function will enable the 100 KHz ILO for the period of -* this function. -* -* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or -* Once Per Second interrupt may be made by interrupt routines during the period -* of this function execution. The current operation of the ILO, Central Time -* Wheel and Once Per Second interrupt are maintained during the operation of -* this function provided the reading of the Power Manager Interrupt Status -* Register is only done using the CyPmReadStatus() function. -* -*******************************************************************************/ -cystatus CyPLL_OUT_Start(uint8 wait) -{ - cystatus status = CYRET_SUCCESS; - - uint8 iloEnableState; - uint8 pmTwCfg0State; - uint8 pmTwCfg2State; - - - /* Enables the PLL circuit */ - CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; - - if(wait != 0u) - { - /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ - iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG; - pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; - - CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); - - status = CYRET_TIMEOUT; - - while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) - { - /* Wait for the interrupt status */ - if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) - { - if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) - { - status = CYRET_SUCCESS; - break; - } - } - } - - /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ - if(0u == iloEnableState) - { - CyILO_Stop100K(); - } - - CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State; - CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyPLL_OUT_Stop -******************************************************************************** -* -* Summary: -* Disables the PLL. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyPLL_OUT_Stop(void) -{ - CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); -} - - -/******************************************************************************* -* Function Name: CyPLL_OUT_SetPQ -******************************************************************************** -* -* Summary: -* Sets the P and Q dividers and the charge pump current. -* The Frequency Out will be P/Q * Frequency In. -* The PLL must be disabled before calling this function. -* -* Parameters: -* uint8 pDiv: -* Valid range [8 - 255]. -* -* uint8 qDiv: -* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. - -* uint8 current: -* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and -* datasheet for more information. -* -* Return: -* None -* -* Side Effects: -* If as result of this function execution the CPU clock frequency is increased -* then the number of clock cycles the cache will wait before it samples data -* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with appropriate parameter. It can be optionally called if CPU clock -* frequency is lowered in order to improve CPU performance. -* See CyFlash_SetWaitCycles() description for more information. -* -*******************************************************************************/ -void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) -{ - /* Halt CPU in debug mode if PLL is enabled */ - CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); - - if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && - (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && - (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) - { - /* Set new values */ - CY_CLK_PLL_P_REG = pDiv; - CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); - CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | - ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); - } - else - { - /*********************************************************************** - * Halt CPU in debug mode if: - * - P divider is less than required - * - Q divider is out of range - * - pump current is out of range - ***********************************************************************/ - CYASSERT(0u != 0u); - } - -} - - -/******************************************************************************* -* Function Name: CyPLL_OUT_SetSource -******************************************************************************** -* -* Summary: -* Sets the input clock source to the PLL. The PLL must be disabled before -* calling this function. -* -* Parameters: -* source: One of the three available PLL clock sources -* CY_PLL_SOURCE_IMO : IMO -* CY_PLL_SOURCE_XTAL : MHz Crystal -* CY_PLL_SOURCE_DSI : DSI -* -* Return: -* None -* -* Side Effects: -* If as result of this function execution the CPU clock frequency is increased -* then the number of clock cycles the cache will wait before it samples data -* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with appropriate parameter. It can be optionally called if CPU clock -* frequency is lowered in order to improve CPU performance. -* See CyFlash_SetWaitCycles() description for more information. -* -*******************************************************************************/ -void CyPLL_OUT_SetSource(uint8 source) -{ - /* Halt CPU in debug mode if PLL is enabled */ - CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); - - switch(source) - { - case CY_PLL_SOURCE_IMO: - case CY_PLL_SOURCE_XTAL: - case CY_PLL_SOURCE_DSI: - CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source); - break; - - default: - CYASSERT(0u != 0u); - break; - } -} - - -/******************************************************************************* -* Function Name: CyIMO_Start -******************************************************************************** -* -* Summary: -* Enables the IMO. Optionally waits at least 6 us for it to settle. -* -* Parameters: -* uint8 wait: -* 0: Return immediately after configuration -* 1: Wait for at least 6 us for the IMO to settle. -* -* Return: -* None -* -* Side Effects: -* If wait is enabled: This function wses the Fast Time Wheel to time the wait. -* Any other use of the Fast Time Wheel will be stopped during the period of -* this function and then restored. This function also uses the 100 KHz ILO. -* If not enabled, this function will enable the 100 KHz ILO for the period of -* this function. -* -* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or -* Once Per Second interrupt may be made by interrupt routines during the period -* of this function execution. The current operation of the ILO, Central Time -* Wheel and Once Per Second interrupt are maintained during the operation of -* this function provided the reading of the Power Manager Interrupt Status -* Register is only done using the CyPmReadStatus() function. -* -*******************************************************************************/ -void CyIMO_Start(uint8 wait) -{ - uint8 pmFtwCfg2Reg; - uint8 pmFtwCfg0Reg; - uint8 ilo100KhzEnable; - - - CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; - CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; - - if(0u != wait) - { - /* Need to turn on the 100KHz ILO if it happens to not already be running.*/ - ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; - pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; - pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; - - CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); - - while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) - { - /* Wait for the interrupt status */ - } - - if(0u == ilo100KhzEnable) - { - CyILO_Stop100K(); - } - - CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; - CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; - } -} - - -/******************************************************************************* -* Function Name: CyIMO_Stop -******************************************************************************** -* -* Summary: -* Disables the IMO. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyIMO_Stop(void) -{ - CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); - CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); -} - - -/******************************************************************************* -* Function Name: CyUSB_PowerOnCheck -******************************************************************************** -* -* Summary: -* Returns the USB power status value. A private function to cy_boot. -* -* Parameters: -* None -* -* Return: -* uint8: one if the USB is enabled, 0 if not enabled. -* -*******************************************************************************/ -static uint8 CyUSB_PowerOnCheck(void) -{ - uint8 poweredOn = 0u; - - /* Check whether device is in Active or AltActiv and if USB is powered on */ - if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && - (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || - (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && - (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) - { - poweredOn = 1u; - } - - return (poweredOn); -} - - -/******************************************************************************* -* Function Name: CyIMO_SetTrimValue -******************************************************************************** -* -* Summary: -* Sets the IMO factory trim values. -* -* Parameters: -* uint8 freq - frequency for which trims must be set -* -* Return: -* None -* -*******************************************************************************/ -static void CyIMO_SetTrimValue(uint8 freq) -{ - uint8 usbPowerOn = CyUSB_PowerOnCheck(); - - /* If USB is powered */ - if(usbPowerOn == 1u) - { - /* Unlock USB write */ - CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); - } - switch(freq) - { - case CY_IMO_FREQ_3MHZ: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR); - break; - - case CY_IMO_FREQ_6MHZ: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR); - break; - - case CY_IMO_FREQ_12MHZ: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR); - break; - - case CY_IMO_FREQ_24MHZ: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR); - break; - - case CY_IMO_FREQ_48MHZ: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR); - break; - - case CY_IMO_FREQ_62MHZ: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR); - break; - -#if(CY_PSOC5) - case CY_IMO_FREQ_74MHZ: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR); - break; -#endif /* (CY_PSOC5) */ - - case CY_IMO_FREQ_USB: - CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR); - - /* If USB is powered */ - if(usbPowerOn == 1u) - { - /* Lock the USB Oscillator */ - CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN; - } - break; - - default: - CYASSERT(0u != 0u); - break; - } - -} - - -/******************************************************************************* -* Function Name: CyIMO_SetFreq -******************************************************************************** -* -* Summary: -* Sets the frequency of the IMO. Changes may be made while the IMO is running. -* -* Parameters: -* freq: Frequency of IMO operation -* CY_IMO_FREQ_3MHZ to set 3 MHz -* CY_IMO_FREQ_6MHZ to set 6 MHz -* CY_IMO_FREQ_12MHZ to set 12 MHz -* CY_IMO_FREQ_24MHZ to set 24 MHz -* CY_IMO_FREQ_48MHZ to set 48 MHz -* CY_IMO_FREQ_62MHZ to set 62.6 MHz -* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) -* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) -* -* Return: -* None -* -* Side Effects: -* If as result of this function execution the CPU clock frequency is increased -* then the number of clock cycles the cache will wait before it samples data -* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with appropriate parameter. It can be optionally called if CPU clock -* frequency is lowered in order to improve CPU performance. -* See CyFlash_SetWaitCycles() description for more information. -* -* When the USB setting is chosen, the USB clock locking circuit is enabled. -* Otherwise this circuit is disabled. The USB block must be powered before -* selecting the USB setting. -* -*******************************************************************************/ -void CyIMO_SetFreq(uint8 freq) -{ - uint8 currentFreq; - uint8 nextFreq; - - /*************************************************************************** - * When changing the IMO frequency the Trim values must also be set - * accordingly.This requires reading the current frequency. If the new - * frequency is faster, then set the new trim and then change the frequency, - * otherwise change the frequency and then set the new trim values. - ***************************************************************************/ - - currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); - - /* Check if the requested frequency is USB. */ - nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; - - switch (currentFreq) - { - case 0u: - currentFreq = CY_IMO_FREQ_12MHZ; - break; - - case 1u: - currentFreq = CY_IMO_FREQ_6MHZ; - break; - - case 2u: - currentFreq = CY_IMO_FREQ_24MHZ; - break; - - case 3u: - currentFreq = CY_IMO_FREQ_3MHZ; - break; - - case 4u: - currentFreq = CY_IMO_FREQ_48MHZ; - break; - - case 5u: - currentFreq = CY_IMO_FREQ_62MHZ; - break; - -#if(CY_PSOC5) - case 6u: - currentFreq = CY_IMO_FREQ_74MHZ; - break; -#endif /* (CY_PSOC5) */ - - default: - CYASSERT(0u != 0u); - break; - } - - if (nextFreq >= currentFreq) - { - /* Set the new trim first */ - CyIMO_SetTrimValue(freq); - } - - /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ - switch(freq) - { - case CY_IMO_FREQ_3MHZ: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - break; - - case CY_IMO_FREQ_6MHZ: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - break; - - case CY_IMO_FREQ_12MHZ: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - break; - - case CY_IMO_FREQ_24MHZ: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - break; - - case CY_IMO_FREQ_48MHZ: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - break; - - case CY_IMO_FREQ_62MHZ: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - break; - -#if(CY_PSOC5) - case CY_IMO_FREQ_74MHZ: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); - break; -#endif /* (CY_PSOC5) */ - - case CY_IMO_FREQ_USB: - CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | - CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET; - break; - - default: - CYASSERT(0u != 0u); - break; - } - - /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */ - if (freq == CY_IMO_FREQ_USB) - { - CyIMO_EnableDoubler(); - } - else - { - CyIMO_DisableDoubler(); - } - - if (nextFreq < currentFreq) - { - /* Set the new trim after setting the frequency */ - CyIMO_SetTrimValue(freq); - } -} - - -/******************************************************************************* -* Function Name: CyIMO_SetSource -******************************************************************************** -* -* Summary: -* Sets the source of the clock output from the IMO block. -* -* The output from the IMO is by default the IMO itself. Optionally the MHz -* Crystal or a DSI input can be the source of the IMO output instead. -* -* Parameters: -* source: CY_IMO_SOURCE_DSI to set the DSI as source. -* CY_IMO_SOURCE_XTAL to set the MHz as source. -* CY_IMO_SOURCE_IMO to set the IMO itself. -* -* Return: -* None -* -* Side Effects: -* If as result of this function execution the CPU clock frequency is increased -* then the number of clock cycles the cache will wait before it samples data -* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with appropriate parameter. It can be optionally called if CPU clock -* frequency is lowered in order to improve CPU performance. -* See CyFlash_SetWaitCycles() description for more information. -* -*******************************************************************************/ -void CyIMO_SetSource(uint8 source) -{ - switch(source) - { - case CY_IMO_SOURCE_DSI: - CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); - CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; - break; - - case CY_IMO_SOURCE_XTAL: - CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; - CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; - break; - - case CY_IMO_SOURCE_IMO: - CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); - break; - - default: - /* Incorrect source value */ - CYASSERT(0u != 0u); - break; - } -} - - -/******************************************************************************* -* Function Name: CyIMO_EnableDoubler -******************************************************************************** -* -* Summary: -* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz -* input to a 48 MHz output for use by the USB block. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyIMO_EnableDoubler(void) -{ - /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */ - CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; -} - - -/******************************************************************************* -* Function Name: CyIMO_DisableDoubler -******************************************************************************** -* -* Summary: -* Disables the IMO doubler. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyIMO_DisableDoubler(void) -{ - CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); -} - - -/******************************************************************************* -* Function Name: CyMasterClk_SetSource -******************************************************************************** -* -* Summary: -* Sets the source of the master clock. -* -* Parameters: -* source: One of the four available Master clock sources. -* CY_MASTER_SOURCE_IMO -* CY_MASTER_SOURCE_PLL -* CY_MASTER_SOURCE_XTAL -* CY_MASTER_SOURCE_DSI -* -* Return: -* None -* -* Side Effects: -* The current source and the new source must both be running and stable before -* calling this function. -* -* If as result of this function execution the CPU clock frequency is increased -* then the number of clock cycles the cache will wait before it samples data -* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with appropriate parameter. It can be optionally called if CPU clock -* frequency is lowered in order to improve CPU performance. -* See CyFlash_SetWaitCycles() description for more information. -* -*******************************************************************************/ -void CyMasterClk_SetSource(uint8 source) -{ - CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | - (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); -} - - -/******************************************************************************* -* Function Name: CyMasterClk_SetDivider -******************************************************************************** -* -* Summary: -* Sets the divider value used to generate Master Clock. -* -* Parameters: -* uint8 divider: -* Valid range [0-255]. The clock will be divided by this value + 1. -* For example to divide by 2 this parameter should be set to 1. -* -* Return: -* None -* -* Side Effects: -* If as result of this function execution the CPU clock frequency is increased -* then the number of clock cycles the cache will wait before it samples data -* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with appropriate parameter. It can be optionally called if CPU clock -* frequency is lowered in order to improve CPU performance. -* See CyFlash_SetWaitCycles() description for more information. -* -* When changing the Master or Bus clock divider value from div-by-n to div-by-1 -* the first clock cycle output after the div-by-1 can be up to 4 ns shorter -* than the final/expected div-by-1 period. -* -*******************************************************************************/ -void CyMasterClk_SetDivider(uint8 divider) -{ - CY_LIB_CLKDIST_MSTR0_REG = divider; -} - - -/******************************************************************************* -* Function Name: CyBusClk_Internal_SetDivider -******************************************************************************** -* -* Summary: -* Function used by CyBusClk_SetDivider(). For internal use only. -* -* Parameters: -* divider: Valid range [0-65535]. -* The clock will be divided by this value + 1. -* For example to divide by 2 this parameter should be set to 1. -* -* Return: -* None -* -*******************************************************************************/ -static void CyBusClk_Internal_SetDivider(uint16 divider) -{ - /* Mask bits to enable shadow loads */ - CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; - CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; - - /* Enable mask bits to enable shadow loads */ - CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; - - /* Update Shadow Divider Value Register with the new divider */ - CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); - CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); - - - /*************************************************************************** - * Copy shadow value defined in Shadow Divider Value Register - * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all - * dividers selected in Analog and Digital Clock Mask Registers - * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). - ***************************************************************************/ - CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; -} - - -/******************************************************************************* -* Function Name: CyBusClk_SetDivider -******************************************************************************** -* -* Summary: -* Sets the divider value used to generate Bus Clock. -* -* Parameters: -* divider: Valid range [0-65535]. The clock will be divided by this value + 1. -* For example to divide by 2 this parameter should be set to 1. -* -* Return: -* None -* -* Side Effects: -* If as result of this function execution the CPU clock frequency is increased -* then the number of clock cycles the cache will wait before it samples data -* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with appropriate parameter. It can be optionally called if CPU clock -* frequency is lowered in order to improve CPU performance. -* See CyFlash_SetWaitCycles() description for more information. -* -*******************************************************************************/ -void CyBusClk_SetDivider(uint16 divider) -{ - uint8 masterClkDiv; - uint16 busClkDiv; - uint8 interruptState; - - interruptState = CyEnterCriticalSection(); - - /* Work around to set the bus clock divider value */ - busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); - busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG; - - if ((divider == 0u) || (busClkDiv == 0u)) - { - /* Save away the master clock divider value */ - masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; - - if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) - { - /* Set master clock divider to 7 */ - CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); - } - - if (divider == 0u) - { - /* Set the SSS bit and the divider register desired value */ - CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; - CyBusClk_Internal_SetDivider(divider); - } - else - { - CyBusClk_Internal_SetDivider(divider); - CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); - } - - /* Restore the master clock */ - CyMasterClk_SetDivider(masterClkDiv); - } - else - { - CyBusClk_Internal_SetDivider(divider); - } - - CyExitCriticalSection(interruptState); -} - - -#if(CY_PSOC3) - - /******************************************************************************* - * Function Name: CyCpuClk_SetDivider - ******************************************************************************** - * - * Summary: - * Sets the divider value used to generate the CPU Clock. Only applicable for - * PSoC 3 parts. - * - * Parameters: - * divider: Valid range [0-15]. The clock will be divided by this value + 1. - * For example to divide by 2 this parameter should be set to 1. - * - * Return: - * None - * - * Side Effects: - * If as result of this function execution the CPU clock frequency is increased - * then the number of clock cycles the cache will wait before it samples data - * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles() - * with appropriate parameter. It can be optionally called if CPU clock - * frequency is lowered in order to improve CPU performance. - * See CyFlash_SetWaitCycles() description for more information. - * - *******************************************************************************/ - void CyCpuClk_SetDivider(uint8 divider) - { - CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) | - ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION)); - } - -#endif /* (CY_PSOC3) */ - - -/******************************************************************************* -* Function Name: CyUsbClk_SetSource -******************************************************************************** -* -* Summary: -* Sets the source of the USB clock. -* -* Parameters: -* source: One of the four available USB clock sources -* CY_LIB_USB_CLK_IMO2X - IMO 2x -* CY_LIB_USB_CLK_IMO - IMO -* CY_LIB_USB_CLK_PLL - PLL -* CY_LIB_USB_CLK_DSI - DSI -* -* Return: -* None -* -*******************************************************************************/ -void CyUsbClk_SetSource(uint8 source) -{ - CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) | - (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source); -} - - -/******************************************************************************* -* Function Name: CyILO_Start1K -******************************************************************************** -* -* Summary: -* Enables the ILO 1 KHz oscillator. -* -* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the -* selection in the Clock Editor. Therefore, this API is only needed if the -* oscillator was turned off manually. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyILO_Start1K(void) -{ - /* Set the bit 1 of ILO RS */ - CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ; -} - - -/******************************************************************************* -* Function Name: CyILO_Stop1K -******************************************************************************** -* -* Summary: -* Disables the ILO 1 KHz oscillator. -* -* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power -* mode APIs are expected to be used. For more information, refer to the Power -* Management section of this document. -* -* Parameters: -* None -* -* Return: -* None -* -* Side Effects: -* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. -* -*******************************************************************************/ -void CyILO_Stop1K(void) -{ - /* Clear the bit 1 of ILO RS */ - CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ)); -} - - -/******************************************************************************* -* Function Name: CyILO_Start100K -******************************************************************************** -* -* Summary: -* Enables the ILO 100 KHz oscillator. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyILO_Start100K(void) -{ - CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; -} - - -/******************************************************************************* -* Function Name: CyILO_Stop100K -******************************************************************************** -* -* Summary: -* Disables the ILO 100 KHz oscillator. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyILO_Stop100K(void) -{ - CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)); -} - - -/******************************************************************************* -* Function Name: CyILO_Enable33K -******************************************************************************** -* -* Summary: -* Enables the ILO 33 KHz divider. -* -* Note that the 33 KHz clock is generated from the 100 KHz oscillator, -* so it must also be running in order to generate the 33 KHz output. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyILO_Enable33K(void) -{ - /* Set the bit 5 of ILO RS */ - CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ; -} - - -/******************************************************************************* -* Function Name: CyILO_Disable33K -******************************************************************************** -* -* Summary: -* Disables the ILO 33 KHz divider. -* -* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this -* API does not disable the 100 KHz clock. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyILO_Disable33K(void) -{ - CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ)); -} - - -/******************************************************************************* -* Function Name: CyILO_SetSource -******************************************************************************** -* -* Summary: -* Sets the source of the clock output from the ILO block. -* -* Parameters: -* source: One of the three available ILO output sources -* Value Define Source -* 0 CY_ILO_SOURCE_100K ILO 100 KHz -* 1 CY_ILO_SOURCE_33K ILO 33 KHz -* 2 CY_ILO_SOURCE_1K ILO 1 KHz -* -* Return: -* None -* -*******************************************************************************/ -void CyILO_SetSource(uint8 source) -{ - CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | - (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); -} - - -/******************************************************************************* -* Function Name: CyILO_SetPowerMode -******************************************************************************** -* -* Summary: -* Sets the power mode used by the ILO during power down. Allows for lower power -* down power usage resulting in a slower startup time. -* -* Parameters: -* uint8 mode -* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down -* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down -* -* Return: -* Prevous power mode state. -* -*******************************************************************************/ -uint8 CyILO_SetPowerMode(uint8 mode) -{ - uint8 state; - - /* Get current state. */ - state = CY_LIB_SLOWCLK_ILO_CR0_REG; - - /* Set the the oscillator power mode. */ - if(mode != CY_ILO_FAST_START) - { - CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE); - } - else - { - CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE))); - } - - /* Return the old mode. */ - return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION); -} - - -/******************************************************************************* -* Function Name: CyXTAL_32KHZ_Start -******************************************************************************** -* -* Summary: -* Enables the 32 KHz Crystal Oscillator. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_32KHZ_Start(void) -{ - volatile uint16 i; - - CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; - CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - CY_CLK_XTAL32_CFG_LP_DEFAULT; - - #if(CY_PSOC3) - CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; - #endif /* (CY_PSOC3) */ - - /* Enable operation of the 32K Crystal Oscillator */ - CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; - - for (i = 1000u; i > 0u; i--) - { - if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) - { - /* Ready - switch to the hign power mode */ - (void) CyXTAL_32KHZ_SetPowerMode(0u); - - break; - } - CyDelayUs(1u); - } -} - - -/******************************************************************************* -* Function Name: CyXTAL_32KHZ_Stop -******************************************************************************** -* -* Summary: -* Disables the 32KHz Crystal Oscillator. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_32KHZ_Stop(void) -{ - CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; - CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - CY_CLK_XTAL32_CFG_LP_DEFAULT; - CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); - - #if(CY_PSOC3) - CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); - #endif /* (CY_PSOC3) */ -} - - -/******************************************************************************* -* Function Name: CyXTAL_32KHZ_ReadStatus -******************************************************************************** -* -* Summary: -* Returns status of the 32 KHz oscillator. -* -* Parameters: -* None -* -* Return: -* Value Define Source -* 20 CY_XTAL32K_ANA_STAT Analog measurement -* 1: Stable -* 0: Not stable -* -*******************************************************************************/ -uint8 CyXTAL_32KHZ_ReadStatus(void) -{ - return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); -} - - -/******************************************************************************* -* Function Name: CyXTAL_32KHZ_SetPowerMode -******************************************************************************** -* -* Summary: -* Sets the power mode for the 32 KHz oscillator used during sleep mode. -* Allows for lower power during sleep when there are fewer sources of noise. -* During active mode the oscillator is always run in high power mode. -* -* Parameters: -* uint8 mode -* 0: High power mode -* 1: Low power mode during sleep -* -* Return: -* Previous power mode. -* -*******************************************************************************/ -uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) -{ - uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; - - CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; - - if(1u == mode) - { - /* Low power mode during Sleep */ - CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; - CyDelayUs(10u); - CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - CY_CLK_XTAL32_CFG_LP_LOWPOWER; - CyDelayUs(20u); - CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; - } - else - { - /* High power mode */ - CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; - CyDelayUs(10u); - CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | - CY_CLK_XTAL32_CFG_LP_DEFAULT; - CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); - } - - return(state); -} - - -/******************************************************************************* -* Function Name: CyXTAL_Start -******************************************************************************** -* -* Summary: -* Enables the megahertz crystal. -* -* PSoC 3: -* Waits until the XERR bit is low (no error) for a millisecond or until the -* number of milliseconds specified by the wait parameter has expired. -* -* Parameters: -* wait: Valid range [0-255]. -* This is the timeout value in milliseconds. -* The appropriate value is crystal specific. -* -* Return: -* CYRET_SUCCESS - Completed successfully -* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. -* -* Side Effects and Restrictions: -* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. -* Any other use of the Fast Timewheel (FTW) will be stopped during the period -* of this function and then restored. -* -* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz -* ILO for the period of this function. No changes to the setup of the ILO, -* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made -* by interrupt routines during the period of this function. -* -* The current operation of the ILO, Central Timewheel and Once Per Second -* interrupt are maintained during the operation of this function provided the -* reading of the Power Manager Interrupt Status Register is only done using the -* CyPmReadStatus() function. -* -*******************************************************************************/ -cystatus CyXTAL_Start(uint8 wait) -{ - cystatus status = CYRET_SUCCESS; - volatile uint8 timeout = wait; - volatile uint8 count; - uint8 iloEnableState; - uint8 pmTwCfg0Tmp; - uint8 pmTwCfg2Tmp; - - - /* Enables the MHz crystal oscillator circuit */ - CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; - - - if(wait > 0u) - { - /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ - iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; - pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; - pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; - - /* Set 250 us interval */ - CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); - status = CYRET_TIMEOUT; - - - for( ; timeout > 0u; timeout--) - { - /* Read XERR bit to clear it */ - (void) CY_CLK_XMHZ_CSR_REG; - - /* Wait for a millisecond - 4 x 250 us */ - for(count = 4u; count > 0u; count--) - { - while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) - { - /* Wait for the FTW interrupt event */ - } - } - - - /******************************************************************* - * High output indicates oscillator failure. - * Only can be used after start-up interval (1 ms) is completed. - *******************************************************************/ - if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) - { - status = CYRET_SUCCESS; - break; - } - } - - - /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ - if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)) - { - CyILO_Stop100K(); - } - CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; - CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CyXTAL_Stop -******************************************************************************** -* -* Summary: -* Disables the megahertz crystal oscillator. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_Stop(void) -{ - /* Disable the the oscillator. */ - FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); -} - - -/******************************************************************************* -* Function Name: CyXTAL_EnableErrStatus -******************************************************************************** -* -* Summary: -* Enables the generation of the XERR status bit for the megahertz crystal. -* This function is not available for PSoC5. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_EnableErrStatus(void) -{ - /* If oscillator has insufficient amplitude, XERR bit will be high. */ - CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); -} - - -/******************************************************************************* -* Function Name: CyXTAL_DisableErrStatus -******************************************************************************** -* -* Summary: -* Disables the generation of the XERR status bit for the megahertz crystal. -* This function is not available for PSoC5. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_DisableErrStatus(void) -{ - /* If oscillator has insufficient amplitude, XERR bit will be high. */ - CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; -} - - -/******************************************************************************* -* Function Name: CyXTAL_ReadStatus -******************************************************************************** -* -* Summary: -* Reads the XERR status bit for the megahertz crystal. This status bit is a -* sticky clear on read value. This function is not available for PSoC5. -* -* Parameters: -* None -* -* Return: -* Status -* 0: No error -* 1: Error -* -*******************************************************************************/ -uint8 CyXTAL_ReadStatus(void) -{ - /*************************************************************************** - * High output indicates oscillator failure. Only use this after start-up - * interval is completed. This can be used for status and failure recovery. - ***************************************************************************/ - return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); -} - - -/******************************************************************************* -* Function Name: CyXTAL_EnableFaultRecovery -******************************************************************************** -* -* Summary: -* Enables the fault recovery circuit which will switch to the IMO in the case -* of a fault in the megahertz crystal circuit. The crystal must be up and -* running with the XERR bit at 0, before calling this function to prevent -* immediate fault switchover. This function is not available for PSoC5. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_EnableFaultRecovery(void) -{ - CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; -} - - -/******************************************************************************* -* Function Name: CyXTAL_DisableFaultRecovery -******************************************************************************** -* -* Summary: -* Disables the fault recovery circuit which will switch to the IMO in the case -* of a fault in the megahertz crystal circuit. This function is not available -* for PSoC5. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_DisableFaultRecovery(void) -{ - CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); -} - - -/******************************************************************************* -* Function Name: CyXTAL_SetStartup -******************************************************************************** -* -* Summary: -* Sets the startup settings for the crystal. Logic model outputs a frequency -* (setting + 4) MHz when enabled. -* -* This is artificial as the actual frequency is determined by an attached -* external crystal. -* -* Parameters: -* setting: Valid range [0-31]. -* Value is dependent on the frequency and quality of the crystal being used. -* Refer to the device TRM and datasheet for more information. -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_SetStartup(uint8 setting) -{ - CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | - (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); -} - - - -/******************************************************************************* -* Function Name: CyXTAL_SetFbVoltage -******************************************************************************** -* -* Summary: -* Sets the feedback reference voltage to use for the crystal circuit. -* This function is only available for PSoC3 and PSoC 5LP. -* -* Parameters: -* setting: Valid range [0-15]. -* Refer to the device TRM and datasheet for more information. -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_SetFbVoltage(uint8 setting) -{ - CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | - (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); -} - - -/******************************************************************************* -* Function Name: CyXTAL_SetWdVoltage -******************************************************************************** -* -* Summary: -* Sets the reference voltage used by the watchdog to detect a failure in the -* crystal circuit. This function is only available for PSoC3 and PSoC 5LP. -* -* Parameters: -* setting: Valid range [0-7]. -* Refer to the device TRM and datasheet for more information. -* -* Return: -* None -* -*******************************************************************************/ -void CyXTAL_SetWdVoltage(uint8 setting) -{ - CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | - (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); -} - - -/******************************************************************************* -* Function Name: CyHalt -******************************************************************************** -* -* Summary: -* Halts the CPU. -* -* Parameters: -* uint8 reason: Value to be used during debugging. -* -* Return: -* None -* -*******************************************************************************/ -void CyHalt(uint8 reason) CYREENTRANT -{ - if(0u != reason) - { - /* To remove unreferenced local variable warning */ - } - - #if defined (__ARMCC_VERSION) - __breakpoint(0x0); - #elif defined(__GNUC__) || defined (__ICCARM__) - __asm(" bkpt 1"); - #elif defined(__C51__) - CYDEV_HALT_CPU; - #endif /* (__ARMCC_VERSION) */ -} - - -/******************************************************************************* -* Function Name: CySoftwareReset -******************************************************************************** -* -* Summary: -* Forces a software reset of the device. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CySoftwareReset(void) -{ - CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET; -} - - -/******************************************************************************* -* Function Name: CyDelay -******************************************************************************** -* -* Summary: -* Blocks for milliseconds. -* -* Note: -* CyDelay has been implemented with the instruction cache assumed enabled. When -* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For -* example, with instruction cache disabled CyDelay(100) would result in about -* 200 ms delay instead of 100 ms. -* -* Parameters: -* milliseconds: number of milliseconds to delay. -* -* Return: -* None -* -*******************************************************************************/ -void CyDelay(uint32 milliseconds) CYREENTRANT -{ - while (milliseconds > 32768u) - { - /*********************************************************************** - * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz - * overflows at about 42 seconds. - ***********************************************************************/ - CyDelayCycles(cydelay_32k_ms); - milliseconds = ((uint32)(milliseconds - 32768u)); - } - - CyDelayCycles(milliseconds * cydelay_freq_khz); -} - - -#if(!CY_PSOC3) - - /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ - - /******************************************************************************* - * Function Name: CyDelayUs - ******************************************************************************** - * - * Summary: - * Blocks for microseconds. - * - * Note: - * CyDelay has been implemented with the instruction cache assumed enabled. - * When instruction cache is disabled on PSoC5, CyDelayUs will be two times - * larger. Ex: With instruction cache disabled CyDelayUs(100) would result - * in about 200us delay instead of 100us. - * - * Parameters: - * uint16 microseconds: number of microseconds to delay. - * - * Return: - * None - * - * Side Effects: - * CyDelayUS has been implemented with the instruction cache assumed enabled. - * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times - * larger. For example, with instruction cache disabled CyDelayUs(100) would - * result in about 200 us delay instead of 100 us. - * - * If the bus clock frequency is a small non-integer number, the actual delay - * can be up to twice as long as the nominal value. The actual delay cannot be - * shorter than the nominal one. - *******************************************************************************/ - void CyDelayUs(uint16 microseconds) CYREENTRANT - { - CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); - } - -#endif /* (!CY_PSOC3) */ - - -/******************************************************************************* -* Function Name: CyDelayFreq -******************************************************************************** -* -* Summary: -* Sets clock frequency for CyDelay. -* -* Parameters: -* freq: Frequency of bus clock in Hertz. -* -* Return: -* None -* -*******************************************************************************/ -void CyDelayFreq(uint32 freq) CYREENTRANT -{ - if (freq != 0u) - { - cydelay_freq_hz = freq; - } - else - { - cydelay_freq_hz = BCLK__BUS_CLK__HZ; - } - - cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); - cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; - cydelay_32k_ms = 32768u * cydelay_freq_khz; -} - - -/******************************************************************************* -* Function Name: CyWdtStart -******************************************************************************** -* -* Summary: -* Enables the watchdog timer. -* -* The timer is configured for the specified count interval, the central -* timewheel is cleared, the setting for low power mode is configured and the -* watchdog timer is enabled. -* -* Once enabled the watchdog cannot be disabled. The watchdog counts each time -* the Central Time Wheel (CTW) reaches the period specified. The watchdog must -* be cleared using the CyWdtClear() function before three ticks of the watchdog -* timer occur. The CTW is free running, so this will occur after between 2 and -* 3 timer periods elapse. -* -* PSoC5: The watchdog timer should not be used during sleep modes. Since the -* WDT cannot be disabled after it is enabled, the WDT timeout period can be -* set to be greater than the sleep wakeup period, then feed the dog on each -* wakeup from Sleep. -* -* Parameters: -* ticks: One of the four available timer periods. Once WDT enabled, the - interval cannot be changed. -* CYWDT_2_TICKS - 4 - 6 ms -* CYWDT_16_TICKS - 32 - 48 ms -* CYWDT_128_TICKS - 256 - 384 ms -* CYWDT_1024_TICKS - 2.048 - 3.072 s -* -* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. -* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. -* -* CYWDT_LPMODE_NOCHANGE - No Change -* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power -* mode -* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode -* -* Return: -* None -* -* Side Effects: -* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the -* ILO 1 kHz could break the active WDT functionality. -* -*******************************************************************************/ -void CyWdtStart(uint8 ticks, uint8 lpMode) -{ - /* Set WDT interval */ - CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK); - - /* Reset CTW to ensure that first watchdog period is full */ - CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; - CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); - - /* Setting the low power mode */ - CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | - (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); - - /* Enables the watchdog reset */ - CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; -} - - -/******************************************************************************* -* Function Name: CyWdtClear -******************************************************************************** -* -* Summary: -* Clears (feeds) the watchdog timer. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyWdtClear(void) -{ - CY_WDT_CR_REG = CY_WDT_CR_FEED; -} - - - -/******************************************************************************* -* Function Name: CyVdLvDigitEnable -******************************************************************************** -* -* Summary: -* Enables the digital low voltage monitors to generate interrupt on Vddd -* archives specified threshold and optionally resets device. -* -* Parameters: -* reset: Option to reset device at a specified Vddd threshold: -* 0 - Device is not reset. -* 1 - Device is reset. -* -* threshold: Sets the trip level for the voltage monitor. -* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV -* interval. -* -* Return: -* None -* -*******************************************************************************/ -void CyVdLvDigitEnable(uint8 reset, uint8 threshold) -{ - *CY_INT_CLEAR_PTR = 0x01u; - - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - - CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | - (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); - CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; - - /* Timeout to eliminate glitches on the LVI/HVI when enabling */ - CyDelayUs(1u); - - (void)CY_VD_PERSISTENT_STATUS_REG; - - if(0u != reset) - { - CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; - } - else - { - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - } - - *CY_INT_CLR_PEND_PTR = 0x01u; - *CY_INT_ENABLE_PTR = 0x01u; -} - - -/******************************************************************************* -* Function Name: CyVdLvAnalogEnable -******************************************************************************** -* -* Summary: -* Enables the analog low voltage monitors to generate interrupt on Vdda -* archives specified threshold and optionally resets device. -* -* Parameters: -* reset: Option to reset device at a specified Vdda threshold: -* 0 - Device is not reset. -* 1 - Device is reset. -* -* threshold: Sets the trip level for the voltage monitor. -* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV -* interval. -* -* Return: -* None -* -*******************************************************************************/ -void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) -{ - *CY_INT_CLEAR_PTR = 0x01u; - - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - - CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); - CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; - - /* Timeout to eliminate glitches on the LVI/HVI when enabling */ - CyDelayUs(1u); - - (void)CY_VD_PERSISTENT_STATUS_REG; - - if(0u != reset) - { - CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; - } - else - { - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - } - - *CY_INT_CLR_PEND_PTR = 0x01u; - *CY_INT_ENABLE_PTR = 0x01u; -} - - -/******************************************************************************* -* Function Name: CyVdLvDigitDisable -******************************************************************************** -* -* Summary: -* Disables the digital low voltage monitor (interrupt and device reset are -* disabled). -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyVdLvDigitDisable(void) -{ - CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); - - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); - - while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) - { - - } -} - - -/******************************************************************************* -* Function Name: CyVdLvAnalogDisable -******************************************************************************** -* -* Summary: -* Disables the analog low voltage monitor (interrupt and device reset are -* disabled). -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyVdLvAnalogDisable(void) -{ - CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); - - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - - while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) - { - - } -} - - -/******************************************************************************* -* Function Name: CyVdHvAnalogEnable -******************************************************************************** -* -* Summary: -* Enables the analog high voltage monitors to generate interrupt on -* Vdda archives 5.75 V threshold and optionally resets device. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyVdHvAnalogEnable(void) -{ - *CY_INT_CLEAR_PTR = 0x01u; - - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - - CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; - - /* Timeout to eliminate glitches on the LVI/HVI when enabling */ - CyDelayUs(1u); - - (void) CY_VD_PERSISTENT_STATUS_REG; - - *CY_INT_CLR_PEND_PTR = 0x01u; - *CY_INT_ENABLE_PTR = 0x01u; -} - - -/******************************************************************************* -* Function Name: CyVdHvAnalogDisable -******************************************************************************** -* -* Summary: -* Disables the analog low voltage monitor -* (interrupt and device reset are disabled). -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyVdHvAnalogDisable(void) -{ - CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); -} - - -/******************************************************************************* -* Function Name: CyVdStickyStatus -******************************************************************************** -* -* Summary: -* Manages the Reset and Voltage Detection Status Register 0. -* This register has the interrupt status for the HVIA, LVID and LVIA. -* This hardware register clears on read. -* -* Parameters: -* mask: Bits in the shadow register to clear. -* Define Definition -* CY_VD_LVID Persistent status of digital LVI. -* CY_VD_LVIA Persistent status of analog LVI. -* CY_VD_HVIA Persistent status of analog HVI. -* -* Return: -* Status. Same enumerated bit values as used for the mask parameter. -* -*******************************************************************************/ -uint8 CyVdStickyStatus(uint8 mask) -{ - uint8 status; - - status = CY_VD_PERSISTENT_STATUS_REG; - CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask)); - - return(status); -} - - -/******************************************************************************* -* Function Name: CyVdRealTimeStatus -******************************************************************************** -* -* Summary: -* Returns the real time voltage detection status. -* -* Parameters: -* None -* -* Return: -* Status: -* Define Definition -* CY_VD_LVID Persistent status of digital LVI. -* CY_VD_LVIA Persistent status of analog LVI. -* CY_VD_HVIA Persistent status of analog HVI. -* -*******************************************************************************/ -uint8 CyVdRealTimeStatus(void) -{ - uint8 interruptState; - uint8 vdFlagsState; - - interruptState = CyEnterCriticalSection(); - vdFlagsState = CY_VD_RT_STATUS_REG; - CyExitCriticalSection(interruptState); - - return(vdFlagsState); -} - - -/******************************************************************************* -* Function Name: CyDisableInts -******************************************************************************** -* -* Summary: -* Disables the interrupt enable for each interrupt. -* -* Parameters: -* None -* -* Return: -* 32 bit mask of previously enabled interrupts. -* -*******************************************************************************/ -uint32 CyDisableInts(void) -{ - uint32 intState; - uint8 interruptState; - - interruptState = CyEnterCriticalSection(); - - #if(CY_PSOC3) - - /* Get the current interrupt state. */ - intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); - intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); - intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); - intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); - - - /* Disable all of the interrupts. */ - CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); - CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); - CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); - CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); - - #else - - /* Get the current interrupt state. */ - intState = CY_GET_REG32(CY_INT_CLEAR_PTR); - - /* Disable all of the interrupts. */ - CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); - - #endif /* (CY_PSOC3) */ - - CyExitCriticalSection(interruptState); - - return (intState); -} - - -/******************************************************************************* -* Function Name: CyEnableInts -******************************************************************************** -* -* Summary: -* Enables interrupts to a given state. -* -* Parameters: -* uint32 mask: 32 bit mask of interrupts to enable. -* -* Return: -* None -* -*******************************************************************************/ -void CyEnableInts(uint32 mask) -{ - - uint8 interruptState; - - interruptState = CyEnterCriticalSection(); - - #if(CY_PSOC3) - - /* Set interrupts as enabled. */ - CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); - CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); - CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); - CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); - - #else - - CY_SET_REG32(CY_INT_ENABLE_PTR, mask); - - #endif /* (CY_PSOC3) */ - - CyExitCriticalSection(interruptState); - -} - -#if(CY_PSOC5) - - /******************************************************************************* - * Function Name: CyFlushCache - ******************************************************************************** - * Summary: - * Flushes the PSoC 5/5LP cache by invalidating all entries. - * - * Parameters: - * None - * - * Return: - * None - * - *******************************************************************************/ - void CyFlushCache(void) - { - uint8 interruptState; - - /* Save current global interrupt enable and disable it */ - interruptState = CyEnterCriticalSection(); - - /* Fill instruction prefectch unit to insure data integrity */ - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - - /* All entries in the cache are invalidated on the next clock cycle. */ - CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; - - - /*********************************************************************** - * The prefetch unit could/would be filled with the instructions that - * succeed the flush. Since a flush is desired then theoretically those - * instructions might be considered stale/invalid. - ***********************************************************************/ - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - CY_NOP; - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); - } - - - /******************************************************************************* - * Function Name: CyIntSetSysVector - ******************************************************************************** - * Summary: - * Sets the interrupt vector of the specified system interrupt number. System - * interrupts are present only for the ARM platform. These interrupts are for - * SysTick, PendSV and others. - * - * Parameters: - * number: Interrupt number, valid range [0-15]. - address: Pointer to an interrupt service routine. - * - * Return: - * The old ISR vector at this location. - * - *******************************************************************************/ - cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) - { - cyisraddress oldIsr; - cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; - - CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); - - /* Save old Interrupt service routine. */ - oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; - - /* Set new Interrupt service routine. */ - ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; - - return (oldIsr); - } - - - /******************************************************************************* - * Function Name: CyIntGetSysVector - ******************************************************************************** - * - * Summary: - * Gets the interrupt vector of the specified system interrupt number. System - * interrupts are present only for the ARM platform. These interrupts are for - * SysTick, PendSV and others. - * - * Parameters: - * number: The interrupt number, valid range [0-15]. - * - * Return: - * Address of the ISR in the interrupt vector table. - * - *******************************************************************************/ - cyisraddress CyIntGetSysVector(uint8 number) - { - cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; - CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); - - return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; - } - - - /******************************************************************************* - * Function Name: CyIntSetVector - ******************************************************************************** - * - * Summary: - * Sets the interrupt vector of the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * address: Pointer to an interrupt service routine - * - * Return: - * Previous interrupt vector value. - * - *******************************************************************************/ - cyisraddress CyIntSetVector(uint8 number, cyisraddress address) - { - cyisraddress oldIsr; - cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; - - CYASSERT(number <= CY_INT_NUMBER_MAX); - - /* Save old Interrupt service routine. */ - oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]; - - /* Set new Interrupt service routine. */ - ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address; - - return (oldIsr); - } - - - /******************************************************************************* - * Function Name: CyIntGetVector - ******************************************************************************** - * - * Summary: - * Gets the interrupt vector of the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * - * Return: - * Address of the ISR in the interrupt vector table. - * - *******************************************************************************/ - cyisraddress CyIntGetVector(uint8 number) - { - cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; - CYASSERT(number <= CY_INT_NUMBER_MAX); - - return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); - } - - - /******************************************************************************* - * Function Name: CyIntSetPriority - ******************************************************************************** - * - * Summary: - * Sets the Priority of the Interrupt. - * - * Parameters: - * priority: Priority of the interrupt. 0 - 7, 0 being the highest. - * number: The number of the interrupt, 0 - 31. - * - * Return: - * None - * - *******************************************************************************/ - void CyIntSetPriority(uint8 number, uint8 priority) - { - CYASSERT(priority <= CY_INT_PRIORITY_MAX); - CYASSERT(number <= CY_INT_NUMBER_MAX); - CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; - } - - - /******************************************************************************* - * Function Name: CyIntGetPriority - ******************************************************************************** - * - * Summary: - * Gets the Priority of the Interrupt. - * - * Parameters: - * number: The number of the interrupt, 0 - 31. - * - * Return: - * Priority of the interrupt. 0 - 7, 0 being the highest. - * - *******************************************************************************/ - uint8 CyIntGetPriority(uint8 number) - { - uint8 priority; - - CYASSERT(number <= CY_INT_NUMBER_MAX); - - priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; - - return (priority); - } - - - /******************************************************************************* - * Function Name: CyIntGetState - ******************************************************************************** - * - * Summary: - * Gets the enable state of the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * Enable status: 1 if enabled, 0 if disabled - * - *******************************************************************************/ - uint8 CyIntGetState(uint8 number) - { - reg32 * stateReg; - - CYASSERT(number <= CY_INT_NUMBER_MAX); - - /* Get a pointer to the Interrupt enable register. */ - stateReg = CY_INT_ENABLE_PTR; - - /* Get the state of the interrupt. */ - return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u)); - } - - -#else /* PSoC3 */ - - - /******************************************************************************* - * Function Name: CyIntSetVector - ******************************************************************************** - * - * Summary: - * Sets the interrupt vector of the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * address: Pointer to an interrupt service routine - * - * Return: - * Previous interrupt vector value. - * - *******************************************************************************/ - cyisraddress CyIntSetVector(uint8 number, cyisraddress address) - { - cyisraddress oldIsr; - - CYASSERT(number <= CY_INT_NUMBER_MAX); - - /* Save old Interrupt service routine. */ - oldIsr = (cyisraddress) \ - CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]); - - /* Set new Interrupt service routine. */ - CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address); - - return (oldIsr); - } - - - /******************************************************************************* - * Function Name: CyIntGetVector - ******************************************************************************** - * - * Summary: - * Gets the interrupt vector of the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * - * Return: - * Address of the ISR in the interrupt vector table. - * - *******************************************************************************/ - cyisraddress CyIntGetVector(uint8 number) - { - CYASSERT(number <= CY_INT_NUMBER_MAX); - - return ((cyisraddress) \ - CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK])); - } - - - /******************************************************************************* - * Function Name: CyIntSetPriority - ******************************************************************************** - * - * Summary: - * Sets the Priority of the Interrupt. - * - * Parameters: - * priority: Priority of the interrupt. 0 - 7, 0 being the highest. - * number: The number of the interrupt, 0 - 31. - * - * Return: - * None - * - *******************************************************************************/ - void CyIntSetPriority(uint8 number, uint8 priority) - { - CYASSERT(priority <= CY_INT_PRIORITY_MAX); - - CYASSERT(number <= CY_INT_NUMBER_MAX); - - CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = - (priority & CY_INT_PRIORITY_MASK) << 5; - } - - - /******************************************************************************* - * Function Name: CyIntGetPriority - ******************************************************************************** - * - * Summary: - * Gets the Priority of the Interrupt. - * - * Parameters: - * number: The number of the interrupt, 0 - 31. - * - * Return: - * Priority of the interrupt. 0 - 7, 0 being the highest. - * - *******************************************************************************/ - uint8 CyIntGetPriority(uint8 number) - { - uint8 priority; - - CYASSERT(number <= CY_INT_NUMBER_MAX); - - priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; - - return (priority); - } - - - /******************************************************************************* - * Function Name: CyIntGetState - ******************************************************************************** - * - * Summary: - * Gets the enable state of the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * Enable status: 1 if enabled, 0 if disabled - * - *******************************************************************************/ - uint8 CyIntGetState(uint8 number) - { - reg8 * stateReg; - - CYASSERT(number <= CY_INT_NUMBER_MAX); - - /* Get a pointer to the Interrupt enable register. */ - stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u); - - /* Get the state of the interrupt. */ - return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); - } - - -#endif /* (CY_PSOC5) */ - - -#if(CYDEV_VARIABLE_VDDA == 1) - - /******************************************************************************* - * Function Name: CySetScPumps - ******************************************************************************** - * - * Summary: - * If 1 is passed as a parameter: - * - if any of the SC blocks are used - enable pumps for the SC blocks and - * start boost clock. - * - For the each enabled SC block set boost clock index and enable boost - * clock. - * - * If non-1 value is passed as a parameter: - * - If all SC blocks are not used - disable pumps for the SC blocks and - * stop boost clock. - * - For the each enabled SC block clear boost clock index and disable boost - * clock. - * - * The global variable CyScPumpEnabled is updated to be equal to passed - * parameter. - * - * Parameters: - * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block. - * 1 - Enable - * 0 - Disable - * - * Return: - * None - * - *******************************************************************************/ - void CySetScPumps(uint8 enable) - { - if(1u == enable) - { - /* The SC pumps should be enabled */ - CyScPumpEnabled = 1u; - /* Enable pumps if any of SC blocks are used */ - if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK)) - { - CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE; - CyScBoostClk_Start(); - } - /* Set positive pump for each enabled SC block: set clock index and enable it */ - if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN)) - { - CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; - CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN; - } - if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN)) - { - CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; - CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN; - } - if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN)) - { - CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; - CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN; - } - if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN)) - { - CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; - CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN; - } - } - else - { - /* The SC pumps should be disabled */ - CyScPumpEnabled = 0u; - /* Disable pumps for all SC blocks and stop boost clock */ - CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE)); - CyScBoostClk_Stop(); - /* Disable boost clock and clear clock index for each SC block */ - CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); - CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; - CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); - CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; - CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); - CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; - CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); - CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; - } - } - -#endif /* (CYDEV_VARIABLE_VDDA == 1) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyLib.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyLib.h deleted file mode 100755 index 8a69921..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CyLib.h +++ /dev/null @@ -1,1281 +0,0 @@ -/******************************************************************************* -* File Name: CyLib.h -* Version 4.0 -* -* Description: -* Provides the function definitions for the system, clocking, interrupts and -* watchdog timer API. -* -* Note: -* Documentation of the API's in this file is located in the System Reference -* Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOT_CYLIB_H) -#define CY_BOOT_CYLIB_H - -#include -#include -#include - -#include "cytypes.h" -#include "cyfitter.h" -#include "cydevice_trm.h" -#include "cyPm.h" - -#if(CY_PSOC3) - #include -#endif /* (CY_PSOC3) */ - - -#if(CYDEV_VARIABLE_VDDA == 1) - - #include "CyScBoostClk.h" - -#endif /* (CYDEV_VARIABLE_VDDA == 1) */ - - -/* Global variable with preserved reset status */ -extern uint8 CYXDATA CyResetStatus; - - -/* Variable Vdda */ -#if(CYDEV_VARIABLE_VDDA == 1) - - extern uint8 CyScPumpEnabled; - -#endif /* (CYDEV_VARIABLE_VDDA == 1) */ - - -/* Do not use these definitions directly in your application */ -extern uint32 cydelay_freq_hz; -extern uint32 cydelay_freq_khz; -extern uint8 cydelay_freq_mhz; -extern uint32 cydelay_32k_ms; - - -/*************************************** -* Function Prototypes -***************************************/ -cystatus CyPLL_OUT_Start(uint8 wait) ; -void CyPLL_OUT_Stop(void) ; -void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ; -void CyPLL_OUT_SetSource(uint8 source) ; - -void CyIMO_Start(uint8 wait) ; -void CyIMO_Stop(void) ; -void CyIMO_SetFreq(uint8 freq) ; -void CyIMO_SetSource(uint8 source) ; -void CyIMO_EnableDoubler(void) ; -void CyIMO_DisableDoubler(void) ; - -void CyMasterClk_SetSource(uint8 source) ; -void CyMasterClk_SetDivider(uint8 divider) ; -void CyBusClk_SetDivider(uint16 divider) ; - -#if(CY_PSOC3) - void CyCpuClk_SetDivider(uint8 divider) ; -#endif /* (CY_PSOC3) */ - -void CyUsbClk_SetSource(uint8 source) ; - -void CyILO_Start1K(void) ; -void CyILO_Stop1K(void) ; -void CyILO_Start100K(void) ; -void CyILO_Stop100K(void) ; -void CyILO_Enable33K(void) ; -void CyILO_Disable33K(void) ; -void CyILO_SetSource(uint8 source) ; -uint8 CyILO_SetPowerMode(uint8 mode) ; - -uint8 CyXTAL_32KHZ_ReadStatus(void) ; -uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ; -void CyXTAL_32KHZ_Start(void) ; -void CyXTAL_32KHZ_Stop(void) ; - -cystatus CyXTAL_Start(uint8 wait) ; -void CyXTAL_Stop(void) ; -void CyXTAL_SetStartup(uint8 setting) ; - -void CyXTAL_EnableErrStatus(void) ; -void CyXTAL_DisableErrStatus(void) ; -uint8 CyXTAL_ReadStatus(void) ; -void CyXTAL_EnableFaultRecovery(void) ; -void CyXTAL_DisableFaultRecovery(void) ; - -void CyXTAL_SetFbVoltage(uint8 setting) ; -void CyXTAL_SetWdVoltage(uint8 setting) ; - -void CyWdtStart(uint8 ticks, uint8 lpMode) ; -void CyWdtClear(void) ; - -/* System Function Prototypes */ -void CyDelay(uint32 milliseconds) CYREENTRANT; -void CyDelayUs(uint16 microseconds); -void CyDelayFreq(uint32 freq) CYREENTRANT; -void CyDelayCycles(uint32 cycles); - -void CySoftwareReset(void) ; - -uint8 CyEnterCriticalSection(void); -void CyExitCriticalSection(uint8 savedIntrStatus); -void CyHalt(uint8 reason) CYREENTRANT; - - -/* Interrupt Function Prototypes */ -#if(CY_PSOC5) - cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ; - cyisraddress CyIntGetSysVector(uint8 number) ; -#endif /* (CY_PSOC5) */ - -cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ; -cyisraddress CyIntGetVector(uint8 number) ; - -void CyIntSetPriority(uint8 number, uint8 priority) ; -uint8 CyIntGetPriority(uint8 number) ; - -uint8 CyIntGetState(uint8 number) ; - -uint32 CyDisableInts(void) ; -void CyEnableInts(uint32 mask) ; - - -#if(CY_PSOC5) - void CyFlushCache(void); -#endif /* (CY_PSOC5) */ - - -/* Voltage Detection Function Prototypes */ -void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ; -void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ; -void CyVdLvDigitDisable(void) ; -void CyVdLvAnalogDisable(void) ; -void CyVdHvAnalogEnable(void) ; -void CyVdHvAnalogDisable(void) ; -uint8 CyVdStickyStatus(uint8 mask) ; -uint8 CyVdRealTimeStatus(void) ; - -void CySetScPumps(uint8 enable) ; - - -/*************************************** -* API Constants -***************************************/ - - -/******************************************************************************* -* PLL API Constants -*******************************************************************************/ -#define CY_CLK_PLL_ENABLE (0x01u) -#define CY_CLK_PLL_LOCK_STATUS (0x01u) - -#define CY_CLK_PLL_FTW_INTERVAL (24u) - -#define CY_CLK_PLL_MAX_Q_VALUE (16u) -#define CY_CLK_PLL_MIN_Q_VALUE (1u) -#define CY_CLK_PLL_MIN_P_VALUE (8u) -#define CY_CLK_PLL_MIN_CUR_VALUE (1u) -#define CY_CLK_PLL_MAX_CUR_VALUE (7u) - -#define CY_CLK_PLL_CURRENT_POSITION (4u) -#define CY_CLK_PLL_CURRENT_MASK (0x8Fu) - - -/******************************************************************************* -* External 32kHz Crystal Oscillator API Constants -*******************************************************************************/ -#define CY_XTAL32K_ANA_STAT (0x20u) - -#define CY_CLK_XTAL32_CR_LPM (0x02u) -#define CY_CLK_XTAL32_CR_EN (0x01u) -#if(CY_PSOC3) - #define CY_CLK_XTAL32_CR_PDBEN (0x04u) -#endif /* (CY_PSOC3) */ - -#define CY_CLK_XTAL32_TR_MASK (0x07u) -#define CY_CLK_XTAL32_TR_STARTUP (0x03u) -#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u) -#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u) -#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u) - -#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u) - -#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u) -#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u) -#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu) - -#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u) - - -/******************************************************************************* -* External MHz Crystal Oscillator API Constants -*******************************************************************************/ -#define CY_CLK_XMHZ_FTW_INTERVAL (24u) -#define CY_CLK_XMHZ_MIN_TIMEOUT (130u) - -#define CY_CLK_XMHZ_CSR_ENABLE (0x01u) -#define CY_CLK_XMHZ_CSR_XERR (0x80u) -#define CY_CLK_XMHZ_CSR_XFB (0x04u) -#define CY_CLK_XMHZ_CSR_XPROT (0x40u) - -#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu) -#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu) -#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u) - - -/******************************************************************************* -* Watchdog Timer API Constants -*******************************************************************************/ -#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */ -#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */ -#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */ -#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */ - -#define CYWDT_LPMODE_NOCHANGE (0x00u) -#define CYWDT_LPMODE_MAXINTER (0x01u) -#define CYWDT_LPMODE_DISABLED (0x03u) - -#define CY_WDT_CFG_INTERVAL_MASK (0x03u) -#define CY_WDT_CFG_CTW_RESET (0x80u) -#define CY_WDT_CFG_LPMODE_SHIFT (5u) -#define CY_WDT_CFG_LPMODE_MASK (0x60u) -#define CY_WDT_CFG_WDR_EN (0x10u) -#define CY_WDT_CFG_CLEAR_ALL (0x00u) -#define CY_WDT_CR_FEED (0x01u) - - -/******************************************************************************* -* Voltage Detection API Constants -*******************************************************************************/ - -#define CY_VD_LVID_EN (0x01u) -#define CY_VD_LVIA_EN (0x02u) -#define CY_VD_HVIA_EN (0x04u) - -#define CY_VD_PRESD_EN (0x40u) -#define CY_VD_PRESA_EN (0x80u) - -#define CY_VD_LVID (0x01u) -#define CY_VD_LVIA (0x02u) -#define CY_VD_HVIA (0x04u) - -#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) - - -/******************************************************************************* -* Variable VDDA API Constants -*******************************************************************************/ -#if(CYDEV_VARIABLE_VDDA == 1) - - /* Active Power Mode Configuration Register 9 */ - #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u) - #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u) - #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u) - #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u) - #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu) - - /* Switched Cap Miscellaneous Control Register */ - #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u) - - /* Switched Capacitor 0 Boost Clock Selection Register */ - #define CY_LIB_SC_BST_CLK_EN (0x08u) - #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u) - -#endif /* (CYDEV_VARIABLE_VDDA == 1) */ - - -/******************************************************************************* -* Clock Distribution API Constants -*******************************************************************************/ -#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u) -#define CY_LIB_CLKDIST_DMASK_MASK (0x00u) -#define CY_LIB_CLKDIST_LD_LOAD (0x01u) -#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) -#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u) -#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) -#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu) -#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u) -#define CY_LIB_FASTCLK_IMO_IMO (0x20u) -#define CY_LIB_CLKDIST_CR_IMO2X (0x40u) -#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u) - -#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu) - - -/* CyILO_SetPowerMode() */ -#define CY_ILO_CONTROL_PD_MODE (0x10u) -#define CY_ILO_CONTROL_PD_POSITION (4u) - -#define CY_ILO_SOURCE_100K (0u) -#define CY_ILO_SOURCE_33K (1u) -#define CY_ILO_SOURCE_1K (2u) - -#define CY_ILO_FAST_START (0u) -#define CY_ILO_SLOW_START (1u) - -#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u) -#define CY_ILO_SOURCE_1K_SET (0x08u) -#define CY_ILO_SOURCE_33K_SET (0x04u) -#define CY_ILO_SOURCE_100K_SET (0x00u) - -#define CY_MASTER_SOURCE_IMO (0u) -#define CY_MASTER_SOURCE_PLL (1u) -#define CY_MASTER_SOURCE_XTAL (2u) -#define CY_MASTER_SOURCE_DSI (3u) - -#define CY_IMO_SOURCE_IMO (0u) -#define CY_IMO_SOURCE_XTAL (1u) -#define CY_IMO_SOURCE_DSI (2u) - - -/* CyIMO_Start() */ -#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u) -#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u) -#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u) - -#define CY_LIB_IMO_3MHZ_VALUE (0x03u) -#define CY_LIB_IMO_6MHZ_VALUE (0x01u) -#define CY_LIB_IMO_12MHZ_VALUE (0x00u) -#define CY_LIB_IMO_24MHZ_VALUE (0x02u) -#define CY_LIB_IMO_48MHZ_VALUE (0x04u) -#define CY_LIB_IMO_62MHZ_VALUE (0x05u) -#define CY_LIB_IMO_74MHZ_VALUE (0x06u) - - -/* CyIMO_SetFreq() */ -#define CY_IMO_FREQ_3MHZ (0u) -#define CY_IMO_FREQ_6MHZ (1u) -#define CY_IMO_FREQ_12MHZ (2u) -#define CY_IMO_FREQ_24MHZ (3u) -#define CY_IMO_FREQ_48MHZ (4u) -#define CY_IMO_FREQ_62MHZ (5u) -#if(CY_PSOC5) - #define CY_IMO_FREQ_74MHZ (6u) -#endif /* (CY_PSOC5) */ -#define CY_IMO_FREQ_USB (8u) - -#define CY_LIB_IMO_USBCLK_ON_SET (0x40u) - - -/* CyCpuClk_SetDivider() */ -#define CY_LIB_CLKDIST_DIV_POSITION (4u) -#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu) - - -/* CyIMO_SetTrimValue() */ -#define CY_LIB_USB_CLK_EN (0x02u) - - -/* CyPLL_OUT_SetSource() - parameters */ -#define CY_PLL_SOURCE_IMO (0u) -#define CY_PLL_SOURCE_XTAL (1u) -#define CY_PLL_SOURCE_DSI (2u) - - -/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */ -#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u) -#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u) -#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u) - - -/* CyUsbClk_SetSource() */ -#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u) - - -/* CyUsbClk_SetSource() - parameters */ -#define CY_LIB_USB_CLK_IMO2X (0x00u) -#define CY_LIB_USB_CLK_IMO (0x01u) -#define CY_LIB_USB_CLK_PLL (0x02u) -#define CY_LIB_USB_CLK_DSI (0x03u) - - -/* CyUSB_PowerOnCheck() */ -#define CY_ACT_USB_ENABLED (0x01u) -#define CY_ALT_ACT_USB_ENABLED (0x01u) - - -/*************************************** -* Registers -***************************************/ - - -/******************************************************************************* -* System Registers -*******************************************************************************/ - -/* Software Reset Control Register */ -#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2) -#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2) - -/* Timewheel Configuration Register 0 */ -#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0) -#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) - -/* Timewheel Configuration Register 2 */ -#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2) -#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) - -/* USB Configuration Register */ -#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG) -#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) - -/* Internal Main Oscillator Trim Register 1 */ -#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1) -#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) - -/* USB control 1 Register */ -#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 ) -#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) - -/* Active Power Mode Configuration Register 0 */ -#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0) -#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) - -/* Standby Power Mode Configuration Register 0 */ -#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0) -#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) - -/* Active Power Mode Configuration Register 5 */ -#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) -#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) - -/* Standby Power Mode Configuration Register 5 */ -#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) -#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) - -/* CyIMO_SetTrimValue() */ -#if(CY_PSOC3) - #define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) - #define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) - #define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) - #define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) - #define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) - #define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) - #define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) - #define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) - #else - #define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) - #define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) - #define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) - #define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) - #define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) - #define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) - #define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) - #define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) -#endif /* (CY_PSOC3) */ - - -/******************************************************************************* -* PLL Registers -*******************************************************************************/ - -/* PLL Configuration Register 0 */ -#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0) -#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0) - -/* PLL Configuration Register 1 */ -#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1) -#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1) - -/* PLL Status Register */ -#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR) -#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR) - -/* PLL Q-Counter Configuration Register */ -#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q) -#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q) - -/* PLL P-Counter Configuration Register */ -#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P) -#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P) - - -/******************************************************************************* -* External MHz Crystal Oscillator Registers -*******************************************************************************/ - -/* External MHz Crystal Oscillator Status and Control Register */ -#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR) -#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR) - -/* External MHz Crystal Oscillator Configuration Register 0 */ -#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0) -#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0) - -/* External MHz Crystal Oscillator Configuration Register 1 */ -#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1) -#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1) - - -/******************************************************************************* -* External 32kHz Crystal Oscillator Registers -*******************************************************************************/ - -/* 32 kHz Watch Crystal Oscillator Trim Register */ -#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR) -#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR) - -/* External 32kHz Crystal Oscillator Test Register */ -#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST) -#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST) - -/* External 32kHz Crystal Oscillator Control Register */ -#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR) -#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR) - -/* External 32kHz Crystal Oscillator Configuration Register */ -#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG) -#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG) - - -/******************************************************************************* -* Watchdog Timer Registers -*******************************************************************************/ - -/* Watchdog Timer Configuration Register */ -#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG) -#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG) - -/* Watchdog Timer Control Register */ -#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR) -#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR) - - -/******************************************************************************* -* LVI/HVI Registers -*******************************************************************************/ - -#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0) -#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0) - -#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1) -#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1) - -#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3) -#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3) - -#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0) -#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0) - -#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2) -#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2) - - -/******************************************************************************* -* Variable VDDA -*******************************************************************************/ -#if(CYDEV_VARIABLE_VDDA == 1) - - /* Active Power Mode Configuration Register 9 */ - #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 ) - #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 ) - - /* Switched Capacitor 0 Boost Clock Selection Register */ - #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST ) - #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST ) - - /* Switched Capacitor 1 Boost Clock Selection Register */ - #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST ) - #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST ) - - /* Switched Capacitor 2 Boost Clock Selection Register */ - #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST ) - #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST ) - - /* Switched Capacitor 3 Boost Clock Selection Register */ - #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST ) - #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST ) - - /* Switched Cap Miscellaneous Control Register */ - #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC ) - #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC ) - -#endif /* (CYDEV_VARIABLE_VDDA == 1) */ - - -/******************************************************************************* -* Clock Distribution Registers -*******************************************************************************/ - -/* Analog Clock Mask Register */ -#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK ) -#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK ) - -/* Digital Clock Mask Register */ -#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK) -#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) - -/* CLK_BUS Configuration Register */ -#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2) -#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) - -/* LSB Shadow Divider Value Register */ -#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0) -#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) - -/* MSB Shadow Divider Value Register */ -#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1) -#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1) - -/* LOAD Register */ -#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD) -#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) - -/* CLK_BUS LSB Divider Value Register */ -#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0) -#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) - -/* CLK_BUS MSB Divider Value Register */ -#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1) -#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1) - -/* Master clock (clk_sync_d) Divider Value Register */ -#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0) -#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) - -/* Master (clk_sync_d) Configuration Register/CPU Divider Value */ -#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1) -#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) - -/* Internal Main Oscillator Control Register */ -#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR) -#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) - -/* Configuration Register CR */ -#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR) -#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) - -/* Internal Low-speed Oscillator Control Register 0 */ -#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) -#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) - - -/******************************************************************************* -* Interrupt Registers -*******************************************************************************/ - -#if(CY_PSOC5) - - /* Interrupt Vector Table Offset */ - #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) - - /* Interrupt Priority 0-31 */ - #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0) - #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0) - - /* Interrupt Enable Set 0-31 */ - #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0) - #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0) - - /* Interrupt Enable Clear 0-31 */ - #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0) - #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0) - - /* Interrupt Pending Set 0-31 */ - #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0) - #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0) - - /* Interrupt Pending Clear 0-31 */ - #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0) - #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0) - - /* Cache Control Register */ - #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL ) - #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL ) - -#elif (CY_PSOC3) - - /* Interrupt Address Vector registers */ - #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE) - - /* Interrrupt Controller Priority Registers */ - #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0) - #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0) - - /* Interrrupt Controller Set Enable Registers */ - #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0) - #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0) - - #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0) - #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0) - - #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1) - #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1) - - #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2) - #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2) - - #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3) - #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3) - - /* Interrrupt Controller Clear Enable Registers */ - #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0) - #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) - - #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0) - #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) - - #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1) - #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1) - - #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2) - #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2) - - #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3) - #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3) - - - /* Interrrupt Controller Set Pend Registers */ - #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0) - #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0) - - /* Interrrupt Controller Clear Pend Registers */ - #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0) - #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0) - - - /* Access Interrupt Controller Registers based on interrupt number */ - #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) - #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) - #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) - #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) - -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* Macro Name: CyAssert -******************************************************************************** -* Summary: -* Macro that evaluates the expression and if it is false (evaluates to 0) then -* the processor is halted. -* -* This macro is evaluated unless NDEBUG is defined. -* -* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is -* defined by default for a Release build setting and not defined for a Debug -* build setting. -* -* Parameters: -* expr: Logical expression. Asserts if false. -* -* Return: -* None -* -*******************************************************************************/ -#if !defined(NDEBUG) - #define CYASSERT(x) { \ - if(!(x)) \ - { \ - CyHalt((uint8) 0u); \ - } \ - } -#else - #define CYASSERT(x) -#endif /* !defined(NDEBUG) */ - - -/* Reset register fields of RESET_SR0 (CyResetStatus) */ -#define CY_RESET_LVID (0x01u) -#define CY_RESET_LVIA (0x02u) -#define CY_RESET_HVIA (0x04u) -#define CY_RESET_WD (0x08u) -#define CY_RESET_SW (0x20u) -#define CY_RESET_GPIO0 (0x40u) -#define CY_RESET_GPIO1 (0x80u) - - -/* Interrrupt Controller Configuration and Status Register */ -#if(CY_PSOC3) - #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) - #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ - #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} - #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} -#endif /* (CY_PSOC3) */ - - -#if defined(__ARMCC_VERSION) - #define CyGlobalIntEnable {__enable_irq();} - #define CyGlobalIntDisable {__disable_irq();} -#elif defined(__GNUC__) || defined (__ICCARM__) - #define CyGlobalIntEnable {__asm("CPSIE i");} - #define CyGlobalIntDisable {__asm("CPSID i");} -#elif defined(__C51__) - #define CyGlobalIntEnable {\ - EA = 1u; \ - INTERRUPT_ENABLE_IRQ\ - } - - #define CyGlobalIntDisable {\ - INTERRUPT_DISABLE_IRQ; \ - CY_NOP; \ - EA = 0u;\ - } -#else - #error No compiler toolchain defined - #define CyGlobalIntEnable - #define CyGlobalIntDisable -#endif /* (__ARMCC_VERSION) */ - - -#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR - #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u) -#else - #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u) -#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */ - - -#ifdef CYREG_MLOGIC_REV_ID_REV_ID - #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID)) -#else - #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID)) -#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */ - - -/******************************************************************************* -* System API constants -*******************************************************************************/ -#define CY_CACHE_CONTROL_FLUSH (0x0004u) -#define CY_LIB_RESET_CR2_RESET (0x01u) - - -/******************************************************************************* -* Interrupt API constants -*******************************************************************************/ -#if(CY_PSOC5) - - #define CY_INT_IRQ_BASE (16u) - -#elif (CY_PSOC3) - - #define CY_INT_IRQ_BASE (0u) - -#endif /* (CY_PSOC5) */ - -/* Valid range of interrupt 0-31 */ -#define CY_INT_NUMBER_MAX (31u) - -/* Valid range of system interrupt 0-15 */ -#define CY_INT_SYS_NUMBER_MAX (15u) - -/* Valid range of system priority 0-7 */ -#define CY_INT_PRIORITY_MAX (7u) - -/* Mask to get valid range of interrupt 0-31 */ -#define CY_INT_NUMBER_MASK (0x1Fu) - -/* Mask to get valid range of system priority 0-7 */ -#define CY_INT_PRIORITY_MASK (0x7u) - -/* Mask to get valid range of system interrupt 0-15 */ -#define CY_INT_SYS_NUMBER_MASK (0xFu) - - -/******************************************************************************* -* Interrupt Macros -*******************************************************************************/ - -#if(CY_PSOC5) - - /******************************************************************************* - * Macro Name: CyIntEnable - ******************************************************************************** - * - * Summary: - * Enables the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) - - /******************************************************************************* - * Macro Name: CyIntDisable - ******************************************************************************** - * - * Summary: - * Disables the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) - - - /******************************************************************************* - * Macro Name: CyIntSetPending - ******************************************************************************** - * - * Summary: - * Forces the specified interrupt number to be pending. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) - - - /******************************************************************************* - * Macro Name: CyIntClearPending - ******************************************************************************** - * - * Summary: - * Clears any pending interrupt for the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) - - -#else /* PSoC3 */ - - - /******************************************************************************* - * Macro Name: CyIntEnable - ******************************************************************************** - * - * Summary: - * Enables the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ - ((uint8)(1u << (0x07u & (number))))) - - - /******************************************************************************* - * Macro Name: CyIntDisable - ******************************************************************************** - * - * Summary: - * Disables the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ - ((uint8)(1u << (0x07u & (number))))) - - - /******************************************************************************* - * Macro Name: CyIntSetPending - ******************************************************************************** - * - * Summary: - * Forces the specified interrupt number to be pending. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ - ((uint8)(1u << (0x07u & (number))))) - - - /******************************************************************************* - * Macro Name: CyIntClearPending - ******************************************************************************** - * Summary: - * Clears any pending interrupt for the specified interrupt number. - * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None - * - *******************************************************************************/ - #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ - ((uint8)(1u << (0x07u & (number))))) - -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used. -*******************************************************************************/ -#define CYGlobalIntEnable CyGlobalIntEnable -#define CYGlobalIntDisable CyGlobalIntDisable - -#define cymemset(s,c,n) memset((s),(c),(n)) -#define cymemcpy(d,s,n) memcpy((d),(s),(n)) - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 -*******************************************************************************/ -#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR) -#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG) -#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR) -#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG) -#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR) -#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG) -#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR) -#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG) - -#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT) -#define X32_CONTROL_DIG_STAT (0x10u) -#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM) -#define X32_CONTROL_LPM_POSITION (1u) -#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN) -#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN) -#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP) -#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN) -#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER) -#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER) -#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT) -#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK) -#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT) -#define X32_CFG_LOWPOWERMODE (0x80u) -#define X32_CFG_LP_LOWPOWER (0x8u) -#define CY_X32_HIGHPOWER_MODE (0u) -#define CY_X32_LOWPOWER_MODE (1u) -#define CY_XTAL32K_DIG_STAT (0x10u) -#define CY_XTAL32K_STAT_FIELDS (0x30u) -#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u) -#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u) -#define CY_XTAL32K_STATUS (0x20u) - -#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR) -#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG) -#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR) -#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG) -#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR) -#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG) -#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK) -#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK) -#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK) -#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE) -#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR) -#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB) -#define X32_CONTROL_XERR_POSITION (7u) -#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT) - -#define CYWDT_CFG (CY_WDT_CFG_PTR) -#define CYWDT_CR (CY_WDT_CR_PTR) - -#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK) -#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET) -#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT) -#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK) -#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN) - -#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR) -#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG) -#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR) -#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG) - -#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE) -#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE) -#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE) -#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE) -#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE) - -#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE) -#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS) -#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE) -#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION) -#define PLL_VCO_GAIN_2 (2u) - -#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR) -#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG) -#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR) -#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG) -#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG) -#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG) - -#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG) -#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR) - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.20 -*******************************************************************************/ - -#if(CY_PSOC5) - - #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) - - #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) - #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) - #define CYINT_ENABLE (CY_INT_ENABLE_PTR) - #define CYINT_CLEAR (CY_INT_CLEAR_PTR) - #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) - #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) - #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR) - -#elif (CY_PSOC3) - - #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) - - #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) - #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) - #define CYINT_ENABLE (CY_INT_ENABLE_PTR) - #define CYINT_CLEAR (CY_INT_CLEAR_PTR) - #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) - #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) - -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 -*******************************************************************************/ -#define BUS_AMASK_CLEAR (0xF0u) -#define BUS_DMASK_CLEAR (0x00u) -#define CLKDIST_LD_LOAD_SET (0x01u) -#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */ -#define MASTERCLK_DIVIDER_VALUE (7u) -#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */ -#define MASTER_CLK_SRC_CLEAR (0xFCu) -#define IMO_DOUBLER_ENABLE (0x10u) -#define CLOCK_IMO_IMO (0x20u) -#define CLOCK_IMO2X_XTAL (0x40u) -#define CLOCK_IMO_RANGE_CLEAR (0xF8u) -#define CLOCK_CONTROL_DIST_MASK (0xFCu) - - -#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK) -#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK) -#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) -#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK) -#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) -#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2) -#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) -#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0) -#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) -#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD) -#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) -#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0) -#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) -#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0) -#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) -#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR) -#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) -#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR) - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.50 -*******************************************************************************/ -#define IMO_PM_ENABLE (0x10u) -#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) -#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0) -#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) -#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) -#define ILO_CONTROL_PD_MODE (0x10u) -#define ILO_CONTROL_PD_POSITION (4u) -#define ILO_CONTROL_1KHZ_ON (0x02u) -#define ILO_CONTROL_100KHZ_ON (0x04u) -#define ILO_CONTROL_33KHZ_ON (0x20u) -#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) -#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0) -#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) -#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2) -#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2) -#define FASTCLK_IMO_USBCLK_ON_SET (0x40u) -#define CLOCK_IMO_3MHZ_VALUE (0x03u) -#define CLOCK_IMO_6MHZ_VALUE (0x01u) -#define CLOCK_IMO_12MHZ_VALUE (0x00u) -#define CLOCK_IMO_24MHZ_VALUE (0x02u) -#define CLOCK_IMO_48MHZ_VALUE (0x04u) -#define CLOCK_IMO_62MHZ_VALUE (0x05u) -#define CLOCK_IMO_74MHZ_VALUE (0x06u) -#define CLKDIST_DIV_POSITION (4u) -#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu) -#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu) -#define CLOCK_USB_ENABLE (0x02u) -#define CLOCK_IMO_OUT_X2 (0x10u) -#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2)) -#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI)) -#define USB_CLKDIST_CONFIG_MASK (0x03u) -#define USB_CLK_IMO2X (0x00u) -#define USB_CLK_IMO (0x01u) -#define USB_CLK_PLL (0x02u) -#define USB_CLK_DSI (0x03u) -#define USB_CLK_DIV2_ON (0x04u) -#define USB_CLK_STOP_FLAG (0x00u) -#define USB_CLK_START_FLAG (0x01u) -#define FTW_CLEAR_ALL_BITS (0x00u) -#define FTW_CLEAR_FTW_BITS (0xFCu) -#define FTW_ENABLE (0x01u) -#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) -#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0) -#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2) -#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2) -#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) -#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG) -#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) -#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1) -#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV) -#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) -#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1) -#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR) -#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) -#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 ) -#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) -#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG) -#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) -#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) -#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) -#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) -#if(CY_PSOC3) - #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) - #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) - #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) - #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) - #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) - #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) - #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) - #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) - #else - #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) - #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) - #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) - #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) - #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) - #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) - #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) - #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) -#endif /* (CY_PSOC3) */ - - -#endif /* (CY_BOOT_CYLIB_H) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CySpc.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CySpc.c deleted file mode 100755 index 0d2b930..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CySpc.c +++ /dev/null @@ -1,554 +0,0 @@ -/******************************************************************************* -* File Name: CySpc.c -* Version 4.0 -* -* Description: -* Provides an API for the System Performance Component. -* The SPC functions are not meant to be called directly by the user -* application. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "CySpc.h" - -#define CY_SPC_KEY_ONE (0xB6u) -#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) - -/* Command Codes */ -#define CY_SPC_CMD_LD_BYTE (0x00u) -#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) -#define CY_SPC_CMD_LD_ROW (0x02u) -#define CY_SPC_CMD_RD_BYTE (0x03u) -#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) -#define CY_SPC_CMD_WR_ROW (0x05u) -#define CY_SPC_CMD_WR_USER_NVL (0x06u) -#define CY_SPC_CMD_PRG_ROW (0x07u) -#define CY_SPC_CMD_ER_SECTOR (0x08u) -#define CY_SPC_CMD_ER_ALL (0x09u) -#define CY_SPC_CMD_RD_HIDDEN (0x0Au) -#define CY_SPC_CMD_PRG_PROTECT (0x0Bu) -#define CY_SPC_CMD_CHECKSUM (0x0Cu) -#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) -#define CY_SPC_CMD_GET_TEMP (0x0Eu) -#define CY_SPC_CMD_GET_ADC (0x0Fu) -#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) -#define CY_SPC_CMD_SETUP_TS (0x11u) -#define CY_SPC_CMD_DISABLE_TS (0x12u) -#define CY_SPC_CMD_ER_ROW (0x13u) - -/* Enable bit in Active and Alternate Active mode templates */ -#define PM_SPC_PM_EN (0x08u) - -/* Gate calls to the SPC. */ -uint8 SpcLockState = CY_SPC_UNLOCKED; - - -#if(CY_PSOC5) - - /*************************************************************************** - * The wait-state pipeline must be enabled prior to accessing the SPC - * register interface regardless of CPU frequency. The CySpcLock() saves - * current wait-state pipeline state and enables it. The CySpcUnlock() - * function, which must be called after SPC transaction, restores original - * state. - ***************************************************************************/ - static uint32 spcWaitPipeBypass = 0u; - -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* Function Name: CySpcStart -******************************************************************************** -* Summary: -* Starts the SPC. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CySpcStart(void) -{ - /* Save current global interrupt enable and disable it */ - uint8 interruptState = CyEnterCriticalSection(); - - CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; - CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: CySpcStop -******************************************************************************** -* Summary: -* Stops the SPC. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CySpcStop(void) -{ - /* Save current global interrupt enable and disable it */ - uint8 interruptState = CyEnterCriticalSection(); - - CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); - CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: CySpcReadData -******************************************************************************** -* Summary: -* Reads data from the SPC. -* -* Parameters: -* uint8 buffer: -* Address to store data read. -* -* uint8 size: -* Number of bytes to read from the SPC. -* -* Return: -* uint8: -* The number of bytes read from the SPC. -* -*******************************************************************************/ -uint8 CySpcReadData(uint8 buffer[], uint8 size) -{ - uint8 i; - - for(i = 0u; i < size; i++) - { - while(!CY_SPC_DATA_READY) - { - CyDelayUs(1u); - } - buffer[i] = CY_SPC_CPU_DATA_REG; - } - - return(i); -} - - -/******************************************************************************* -* Function Name: CySpcLoadMultiByte -******************************************************************************** -* Summary: -* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. -* -* Parameters: -* uint8 array: -* Id of the array. -* -* uint16 address: -* Flash/eeprom addrress -* -* uint8* buffer: -* Data to load to the row latch -* -* uint16 number: -* Number bytes to load. -* -* Return: -* CYRET_STARTED -* CYRET_CANCELED -* CYRET_LOCKED -* CYRET_BAD_PARAM -* -*******************************************************************************/ -cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ - -{ - cystatus status = CYRET_STARTED; - uint8 i; - - /*************************************************************************** - * Check if number is correct for array. Number must be less than - * 32 for Flash or less than 16 for EEPROM. - ***************************************************************************/ - if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || - ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) - { - if(CY_SPC_IDLE) - { - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); - CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; - - if(CY_SPC_BUSY) - { - CY_SPC_CPU_DATA_REG = array; - CY_SPC_CPU_DATA_REG = 1u & HI8(address); - CY_SPC_CPU_DATA_REG = LO8(address); - CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); - - for(i = 0u; i < size; i++) - { - CY_SPC_CPU_DATA_REG = buffer[i]; - } - } - else - { - status = CYRET_CANCELED; - } - } - else - { - status = CYRET_LOCKED; - } - } - else - { - status = CYRET_BAD_PARAM; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CySpcLoadRow -******************************************************************************** -* Summary: -* Loads a row of data into the row latch of a Flash/EEPROM array. -* -* Parameters: -* uint8 array: -* Id of the array. -* -* uint8* buffer: -* Data to be loaded to the row latch -* -* uint8 size: -* The number of data bytes that the SPC expects to be written. Depends on the -* type of the array and, if the array is Flash, whether ECC is being enabled -* or not. There are following values: flash row latch size with ECC enabled, -* flash row latch size with ECC disabled and EEPROM row latch size. -* -* Return: -* CYRET_STARTED -* CYRET_CANCELED -* CYRET_LOCKED -* -*******************************************************************************/ -cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) -{ - cystatus status = CYRET_STARTED; - uint16 i; - - /* Make sure the SPC is ready to accept command */ - if(CY_SPC_IDLE) - { - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); - CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; - - /* Make sure the command was accepted */ - if(CY_SPC_BUSY) - { - CY_SPC_CPU_DATA_REG = array; - - for(i = 0u; i < size; i++) - { - CY_SPC_CPU_DATA_REG = buffer[i]; - } - } - else - { - status = CYRET_CANCELED; - } - } - else - { - status = CYRET_LOCKED; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CySpcWriteRow -******************************************************************************** -* Summary: -* Erases then programs a row in Flash/EEPROM with data in row latch. -* -* Parameters: -* uint8 array: -* Id of the array. -* -* uint16 address: -* flash/eeprom addrress -* -* uint8 tempPolarity: -* temperature polarity. -* 1: the Temp Magnitude is interpreted as a positive value -* 0: the Temp Magnitude is interpreted as a negative value -* -* uint8 tempMagnitude: -* temperature magnitude. -* -* Return: -* CYRET_STARTED -* CYRET_CANCELED -* CYRET_LOCKED -* -*******************************************************************************/ -cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ - -{ - cystatus status = CYRET_STARTED; - - /* Make sure the SPC is ready to accept command */ - if(CY_SPC_IDLE) - { - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); - CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; - - /* Make sure the command was accepted */ - if(CY_SPC_BUSY) - { - CY_SPC_CPU_DATA_REG = array; - CY_SPC_CPU_DATA_REG = HI8(address); - CY_SPC_CPU_DATA_REG = LO8(address); - CY_SPC_CPU_DATA_REG = tempPolarity; - CY_SPC_CPU_DATA_REG = tempMagnitude; - } - else - { - status = CYRET_CANCELED; - } - } - else - { - status = CYRET_LOCKED; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CySpcEraseSector -******************************************************************************** -* Summary: -* Erases all data in the addressed sector (block of 64 rows). -* -* Parameters: -* uint8 array: -* Id of the array. -* -* uint8 sectorNumber: -* Zero based sector number within Flash/EEPROM array -* -* Return: -* CYRET_STARTED -* CYRET_CANCELED -* CYRET_LOCKED -* -*******************************************************************************/ -cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) -{ - cystatus status = CYRET_STARTED; - - /* Make sure the SPC is ready to accept command */ - if(CY_SPC_IDLE) - { - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); - CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; - - /* Make sure the command was accepted */ - if(CY_SPC_BUSY) - { - CY_SPC_CPU_DATA_REG = array; - CY_SPC_CPU_DATA_REG = sectorNumber; - } - else - { - status = CYRET_CANCELED; - } - } - else - { - status = CYRET_LOCKED; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CySpcGetTemp -******************************************************************************** -* Summary: -* Returns the internal die temperature -* -* Parameters: -* uint8 numSamples: -* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples -* respectively. -* -* uint16 timerPeriod: -* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits -* of 16 bit values are ignored. -* -* uint8 clkDivSelect: -* ADC ACLK clock divide value. Valid values are 2 - 225. -* -* Return: -* CYRET_STARTED -* CYRET_CANCELED -* CYRET_LOCKED -* -*******************************************************************************/ -cystatus CySpcGetTemp(uint8 numSamples) -{ - cystatus status = CYRET_STARTED; - - /* Make sure the SPC is ready to accept command */ - if(CY_SPC_IDLE) - { - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; - CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); - CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; - - /* Make sure the command was accepted */ - if(CY_SPC_BUSY) - { - CY_SPC_CPU_DATA_REG = numSamples; - } - else - { - status = CYRET_CANCELED; - } - } - else - { - status = CYRET_LOCKED; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: CySpcLock -******************************************************************************** -* Summary: -* Locks the SPC so it can not be used by someone else: -* - Saves wait-pipeline enable state and enable pipeline (PSoC5) -* -* Parameters: -* Note -* -* Return: -* CYRET_SUCCESS - if the resource was free. -* CYRET_LOCKED - if the SPC is in use. -* -*******************************************************************************/ -cystatus CySpcLock(void) -{ - cystatus status = CYRET_LOCKED; - uint8 interruptState; - - /* Enter critical section */ - interruptState = CyEnterCriticalSection(); - - if(CY_SPC_UNLOCKED == SpcLockState) - { - SpcLockState = CY_SPC_LOCKED; - status = CYRET_SUCCESS; - - #if(CY_PSOC5) - - if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) - { - /* Enable pipeline registers */ - CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); - - /* At least 2 NOP instructions are recommended */ - CY_NOP; - CY_NOP; - CY_NOP; - - spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; - } - - #endif /* (CY_PSOC5) */ - } - - /* Exit critical section */ - CyExitCriticalSection(interruptState); - - return(status); -} - - -/******************************************************************************* -* Function Name: CySpcUnlock -******************************************************************************** -* Summary: -* Unlocks the SPC so it can be used by someone else: -* - Restores wait-pipeline enable state (PSoC5) -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CySpcUnlock(void) -{ - uint8 interruptState; - - /* Enter critical section */ - interruptState = CyEnterCriticalSection(); - - /* Release the SPC object */ - SpcLockState = CY_SPC_UNLOCKED; - - #if(CY_PSOC5) - - if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) - { - /* Force to bypass pipeline registers */ - CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; - - /* At least 2 NOP instructions are recommended */ - CY_NOP; - CY_NOP; - CY_NOP; - - spcWaitPipeBypass = 0u; - } - - #endif /* (CY_PSOC5) */ - - /* Exit critical section */ - CyExitCriticalSection(interruptState); -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CySpc.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CySpc.h deleted file mode 100755 index 6a5828c..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/CySpc.h +++ /dev/null @@ -1,154 +0,0 @@ -/******************************************************************************* -* File Name: CySpc.c -* Version 4.0 -* -* Description: -* Provides definitions for the System Performance Component API. -* The SPC functions are not meant to be called directly by the user -* application. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOT_CYSPC_H) -#define CY_BOOT_CYSPC_H - -#include "cytypes.h" -#include "CyLib.h" -#include "cydevice_trm.h" - - -/*************************************** -* Global Variables -***************************************/ -extern uint8 SpcLockState; - - -/*************************************** -* Function Prototypes -***************************************/ -void CySpcStart(void); -void CySpcStop(void); -uint8 CySpcReadData(uint8 buffer[], uint8 size); -cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ -; -cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size); -cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ -; -cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber); -cystatus CySpcGetTemp(uint8 numSamples); -cystatus CySpcLock(void); -void CySpcUnlock(void); - - -/*************************************** -* API Constants -***************************************/ - -#define CY_SPC_LOCKED (0x01u) -#define CY_SPC_UNLOCKED (0x00u) - -/******************************************************************************* -* The Array ID indicates the unique ID of the SONOS array being accessed: -* - 0x00-0x3E : Flash Arrays -* - 0x3F : Selects all Flash arrays simultaneously -* - 0x40-0x7F : Embedded EEPROM Arrays -*******************************************************************************/ -#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u) -#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu) -#define CY_SPC_FIRST_EE_ARRAYID (0x40u) -#define CY_SPC_LAST_EE_ARRAYID (0x7Fu) - - -#define CY_SPC_STATUS_DATA_READY_MASK (0x01u) -#define CY_SPC_STATUS_IDLE_MASK (0x02u) -#define CY_SPC_STATUS_CODE_MASK (0xFCu) -#define CY_SPC_STATUS_CODE_SHIFT (0x02u) - -/* Status codes for the SPC. */ -#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */ -#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */ -#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */ -#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */ -#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */ -#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */ -#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */ -#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */ -#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */ -#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */ -#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */ -#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */ -#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */ -#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */ -#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */ - -#if(CY_PSOC5) - - /* Wait-state pipeline */ - #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u) - -#endif /* (CY_PSOC5) */ - - -/*************************************** -* Registers -***************************************/ - -/* SPC CPU Data Register */ -#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA ) -#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA ) - -/* SPC Status Register */ -#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR ) -#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR ) - -/* Active Power Mode Configuration Register 0 */ -#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) -#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) - -/* Standby Power Mode Configuration Register 0 */ -#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 ) -#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 ) - -#if(CY_PSOC5) - - /* Wait State Pipeline */ - #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE ) - #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE ) - -#endif /* (CY_PSOC5) */ - - -/*************************************** -* Macros -***************************************/ -#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) -#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) -#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK)) - -/* SPC must be in idle state in order to obtain correct status */ -#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \ - ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \ - ((uint8) CY_SPC_STATUS_BUSY)) - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.0 -*******************************************************************************/ -#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID) -#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID) -#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID) -#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID) -#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) -#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE) -#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE) - - -#endif /* (CY_BOOT_CYSPC_H) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/PSoC5_PSoC5LP_100-TQFP.xml b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/PSoC5_PSoC5LP_100-TQFP.xml deleted file mode 100755 index 0b36df4..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/PSoC5_PSoC5LP_100-TQFP.xml +++ /dev/null @@ -1,250 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/SCSI_Out_DBx_aliases.h deleted file mode 100755 index 740ea09..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/SCSI_Out_DBx_aliases.h +++ /dev/null @@ -1,48 +0,0 @@ -/******************************************************************************* -* File Name: SCSI_Out_DBx.h -* Version 1.90 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */ -#define CY_PINS_SCSI_Out_DBx_ALIASES_H - -#include "cytypes.h" -#include "cyfitter.h" - - - -/*************************************** -* Constants -***************************************/ -#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC -#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC -#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC -#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC -#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC -#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC -#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC -#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC - -#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC -#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC -#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC -#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC -#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC -#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC -#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC -#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC - -#endif /* End Pins SCSI_Out_DBx_ALIASES_H */ - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/SCSI_Out_aliases.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/SCSI_Out_aliases.h deleted file mode 100755 index e8aa91f..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/SCSI_Out_aliases.h +++ /dev/null @@ -1,52 +0,0 @@ -/******************************************************************************* -* File Name: SCSI_Out.h -* Version 1.90 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */ -#define CY_PINS_SCSI_Out_ALIASES_H - -#include "cytypes.h" -#include "cyfitter.h" - - - -/*************************************** -* Constants -***************************************/ -#define SCSI_Out_0 SCSI_Out__0__PC -#define SCSI_Out_1 SCSI_Out__1__PC -#define SCSI_Out_2 SCSI_Out__2__PC -#define SCSI_Out_3 SCSI_Out__3__PC -#define SCSI_Out_4 SCSI_Out__4__PC -#define SCSI_Out_5 SCSI_Out__5__PC -#define SCSI_Out_6 SCSI_Out__6__PC -#define SCSI_Out_7 SCSI_Out__7__PC -#define SCSI_Out_8 SCSI_Out__8__PC -#define SCSI_Out_9 SCSI_Out__9__PC - -#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC -#define SCSI_Out_ATN SCSI_Out__ATN__PC -#define SCSI_Out_BSY SCSI_Out__BSY__PC -#define SCSI_Out_ACK SCSI_Out__ACK__PC -#define SCSI_Out_RST SCSI_Out__RST__PC -#define SCSI_Out_MSG SCSI_Out__MSG__PC -#define SCSI_Out_SEL SCSI_Out__SEL__PC -#define SCSI_Out_CD SCSI_Out__CD__PC -#define SCSI_Out_REQ SCSI_Out__REQ__PC -#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC - -#endif /* End Pins SCSI_Out_ALIASES_H */ - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS.c deleted file mode 100755 index 081e687..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS.c +++ /dev/null @@ -1,1335 +0,0 @@ -/******************************************************************************* -* File Name: USBFS.c -* Version 2.60 -* -* Description: -* API for USBFS Component. -* -* Note: -* Many of the functions use endpoint number. RAM arrays are sized with 9 -* elements so they are indexed directly by epNumber. The SIE and ARB -* registers are indexed by variations of epNumber - 1. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include -#include "USBFS.h" -#include "USBFS_pvt.h" -#include "USBFS_hid.h" -#if(USBFS_DMA1_REMOVE == 0u) - #include "USBFS_ep1_dma.h" -#endif /* End USBFS_DMA1_REMOVE */ -#if(USBFS_DMA2_REMOVE == 0u) - #include "USBFS_ep2_dma.h" -#endif /* End USBFS_DMA2_REMOVE */ -#if(USBFS_DMA3_REMOVE == 0u) - #include "USBFS_ep3_dma.h" -#endif /* End USBFS_DMA3_REMOVE */ -#if(USBFS_DMA4_REMOVE == 0u) - #include "USBFS_ep4_dma.h" -#endif /* End USBFS_DMA4_REMOVE */ -#if(USBFS_DMA5_REMOVE == 0u) - #include "USBFS_ep5_dma.h" -#endif /* End USBFS_DMA5_REMOVE */ -#if(USBFS_DMA6_REMOVE == 0u) - #include "USBFS_ep6_dma.h" -#endif /* End USBFS_DMA6_REMOVE */ -#if(USBFS_DMA7_REMOVE == 0u) - #include "USBFS_ep7_dma.h" -#endif /* End USBFS_DMA7_REMOVE */ -#if(USBFS_DMA8_REMOVE == 0u) - #include "USBFS_ep8_dma.h" -#endif /* End USBFS_DMA8_REMOVE */ - - -/*************************************** -* Global data allocation -***************************************/ - -uint8 USBFS_initVar = 0u; -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - uint8 USBFS_DmaChan[USBFS_MAX_EP]; - uint8 USBFS_DmaTd[USBFS_MAX_EP]; -#endif /* End USBFS_EP_MM */ - - -/******************************************************************************* -* Function Name: USBFS_Start -******************************************************************************** -* -* Summary: -* This function initialize the USB SIE, arbiter and the -* endpoint APIs, including setting the D+ Pullup -* -* Parameters: -* device: Contains the device number of the desired device descriptor. -* The device number can be found in the Device Descriptor Tab of -* "Configure" dialog, under the settings of desired Device Descriptor, -* in the "Device Number" field. -* mode: The operating voltage. This determines whether the voltage regulator -* is enabled for 5V operation or if pass through mode is used for 3.3V -* operation. Symbolic names and their associated values are given in the -* following table. -* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru -* Vcc for pull-up -* USBFS_5V_OPERATION - Enable voltage regulator and use -* regulator for pull-up -* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage -* regulator depend on Vddd Voltage configuration in DWR. -* -* Return: -* None. -* -* Global variables: -* The USBFS_intiVar variable is used to indicate initial -* configuration of this component. The variable is initialized to zero (0u) -* and set to one (1u) the first time USBFS_Start() is called. -* This allows for component Re-Start without unnecessary re-initialization -* in all subsequent calls to the USBFS_Start() routine. -* If re-initialization of the component is required the variable should be set -* to zero before call of UART_Start() routine, or the user may call -* USBFS_Init() and USBFS_InitComponent() as done -* in the USBFS_Start() routine. -* -* Side Effects: -* This function will reset all communication states to default. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_Start(uint8 device, uint8 mode) -{ - /* If not Initialized then initialize all required hardware and software */ - if(USBFS_initVar == 0u) - { - USBFS_Init(); - USBFS_initVar = 1u; - } - USBFS_InitComponent(device, mode); -} - - -/******************************************************************************* -* Function Name: USBFS_Init -******************************************************************************** -* -* Summary: -* Initialize component's hardware. Usually called in USBFS_Start(). -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_Init(void) -{ - uint8 enableInterrupts; - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - uint16 i; - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - enableInterrupts = CyEnterCriticalSection(); - - /* Enable USB block */ - USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; - /* Enable USB block for Standby Power Mode */ - USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; - - /* Enable core clock */ - USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; - - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - - /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */ - /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ - USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN)); - CyDelayUs(0u); /*~50ns delay */ - /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) - * high. This will have been set low by the power manger out of reset. - * Also confirm USBIO pull-up disabled - */ - USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N | - USBFS_PM_USB_CR0_PD_PULLUP_N))); - - /* Select iomode to USB mode*/ - USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE)); - - /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ - USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; - /* The reference will be available 1 us after the regulator is enabled */ - CyDelayUs(1u); - /* OR 40us after power restored */ - CyDelayUs(40u); - /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ - USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK)); - USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK)); - - /* Enable USBIO */ - USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; - CyDelayUs(2u); - /* Set the USBIO pull-up enable */ - USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; - - /* Write WAx */ - CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); - CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); - - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */ - for (i = 0u; i < USBFS_MAX_EP; i++) - { - USBFS_DmaTd[i] = DMA_INVALID_TD; - } - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - CyExitCriticalSection(enableInterrupts); - - - /* Set the bus reset Interrupt. */ - (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); - CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); - - /* Set the SOF Interrupt. */ - #if(USBFS_SOF_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); - CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); - #endif /* End USBFS_SOF_ISR_REMOVE */ - - /* Set the Control Endpoint Interrupt. */ - (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); - CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); - - /* Set the Data Endpoint 1 Interrupt. */ - #if(USBFS_EP1_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); - CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); - #endif /* End USBFS_EP1_ISR_REMOVE */ - - /* Set the Data Endpoint 2 Interrupt. */ - #if(USBFS_EP2_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); - CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); - #endif /* End USBFS_EP2_ISR_REMOVE */ - - /* Set the Data Endpoint 3 Interrupt. */ - #if(USBFS_EP3_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); - CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); - #endif /* End USBFS_EP3_ISR_REMOVE */ - - /* Set the Data Endpoint 4 Interrupt. */ - #if(USBFS_EP4_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); - CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); - #endif /* End USBFS_EP4_ISR_REMOVE */ - - /* Set the Data Endpoint 5 Interrupt. */ - #if(USBFS_EP5_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); - CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); - #endif /* End USBFS_EP5_ISR_REMOVE */ - - /* Set the Data Endpoint 6 Interrupt. */ - #if(USBFS_EP6_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); - CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); - #endif /* End USBFS_EP6_ISR_REMOVE */ - - /* Set the Data Endpoint 7 Interrupt. */ - #if(USBFS_EP7_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); - CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); - #endif /* End USBFS_EP7_ISR_REMOVE */ - - /* Set the Data Endpoint 8 Interrupt. */ - #if(USBFS_EP8_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); - CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); - #endif /* End USBFS_EP8_ISR_REMOVE */ - - #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) - /* Set the ARB Interrupt. */ - (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); - CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - -} - - -/******************************************************************************* -* Function Name: USBFS_InitComponent -******************************************************************************** -* -* Summary: -* Initialize the component, except for the HW which is done one time in -* the Start function. This function pulls up D+. -* -* Parameters: -* device: Contains the device number of the desired device descriptor. -* The device number can be found in the Device Descriptor Tab of -* "Configure" dialog, under the settings of desired Device Descriptor, -* in the "Device Number" field. -* mode: The operating voltage. This determines whether the voltage regulator -* is enabled for 5V operation or if pass through mode is used for 3.3V -* operation. Symbolic names and their associated values are given in the -* following table. -* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru -* Vcc for pull-up -* USBFS_5V_OPERATION - Enable voltage regulator and use -* regulator for pull-up -* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage -* regulator depend on Vddd Voltage configuration in DWR. -* -* Return: -* None. -* -* Global variables: -* USBFS_device: Contains the device number of the desired device -* descriptor. The device number can be found in the Device Descriptor Tab -* of "Configure" dialog, under the settings of desired Device Descriptor, -* in the "Device Number" field. -* USBFS_transferState: This variable used by the communication -* functions to handle current transfer state. Initialized to -* TRANS_STATE_IDLE in this API. -* USBFS_configuration: Contains current configuration number -* which is set by the Host using SET_CONFIGURATION request. -* Initialized to zero in this API. -* USBFS_deviceAddress: Contains current device address. This -* variable is initialized to zero in this API. Host starts to communicate -* to device with address 0 and then set it to whatever value using -* SET_ADDRESS request. -* USBFS_deviceStatus: initialized to 0. -* This is two bit variable which contain power status in first bit -* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote -* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. -* USBFS_lastPacketSize initialized to 0; -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_InitComponent(uint8 device, uint8 mode) -{ - /* Initialize _hidProtocol variable to comply with - * HID 7.2.6 Set_Protocol Request: - * "When initialized, all devices default to report protocol." - */ - #if defined(USBFS_ENABLE_HID_CLASS) - uint8 i; - - for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - { - USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; - } - #endif /* USBFS_ENABLE_HID_CLASS */ - - /* Enable Interrupts. */ - CyIntEnable(USBFS_BUS_RESET_VECT_NUM); - CyIntEnable(USBFS_EP_0_VECT_NUM); - #if(USBFS_EP1_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_1_VECT_NUM); - #endif /* End USBFS_EP1_ISR_REMOVE */ - #if(USBFS_EP2_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_2_VECT_NUM); - #endif /* End USBFS_EP2_ISR_REMOVE */ - #if(USBFS_EP3_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_3_VECT_NUM); - #endif /* End USBFS_EP3_ISR_REMOVE */ - #if(USBFS_EP4_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_4_VECT_NUM); - #endif /* End USBFS_EP4_ISR_REMOVE */ - #if(USBFS_EP5_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_5_VECT_NUM); - #endif /* End USBFS_EP5_ISR_REMOVE */ - #if(USBFS_EP6_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_6_VECT_NUM); - #endif /* End USBFS_EP6_ISR_REMOVE */ - #if(USBFS_EP7_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_7_VECT_NUM); - #endif /* End USBFS_EP7_ISR_REMOVE */ - #if(USBFS_EP8_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_8_VECT_NUM); - #endif /* End USBFS_EP8_ISR_REMOVE */ - #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) - /* usb arb interrupt enable */ - USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; - CyIntEnable(USBFS_ARB_VECT_NUM); - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - /* Arbiter configuration for DMA transfers */ - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; - #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /*Set cfg cmplt this rises DMA request when the full configuration is done */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - USBFS_transferState = USBFS_TRANS_STATE_IDLE; - - /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/ - switch(mode) - { - case USBFS_3V_OPERATION: - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - break; - case USBFS_5V_OPERATION: - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; - break; - default: /*USBFS_DWR_VDDD_OPERATION */ - #if(USBFS_VDDD_MV < USBFS_3500MV) - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - #else - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; - #endif /* End USBFS_VDDD_MV < USBFS_3500MV */ - break; - } - - /* Record the descriptor selection */ - USBFS_device = device; - - /* Clear all of the component data */ - USBFS_configuration = 0u; - USBFS_interfaceNumber = 0u; - USBFS_configurationChanged = 0u; - USBFS_deviceAddress = 0u; - USBFS_deviceStatus = 0u; - - USBFS_lastPacketSize = 0u; - - /* ACK Setup, Stall IN/OUT */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - - /* Enable the SIE with an address 0 */ - CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); - - /* Workaround for PSOC5LP */ - CyDelayCycles(1u); - - /* Finally, Enable d+ pullup and select iomode to USB mode*/ - CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); -} - - -/******************************************************************************* -* Function Name: USBFS_ReInitComponent -******************************************************************************** -* -* Summary: -* This function reinitialize the component configuration and is -* intend to be called from the Reset interrupt. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_device: Contains the device number of the desired device -* descriptor. The device number can be found in the Device Descriptor Tab -* of "Configure" dialog, under the settings of desired Device Descriptor, -* in the "Device Number" field. -* USBFS_transferState: This variable used by the communication -* functions to handle current transfer state. Initialized to -* TRANS_STATE_IDLE in this API. -* USBFS_configuration: Contains current configuration number -* which is set by the Host using SET_CONFIGURATION request. -* Initialized to zero in this API. -* USBFS_deviceAddress: Contains current device address. This -* variable is initialized to zero in this API. Host starts to communicate -* to device with address 0 and then set it to whatever value using -* SET_ADDRESS request. -* USBFS_deviceStatus: initialized to 0. -* This is two bit variable which contain power status in first bit -* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote -* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. -* USBFS_lastPacketSize initialized to 0; -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_ReInitComponent(void) -{ - /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol - * Request: "When initialized, all devices default to report protocol." - */ - #if defined(USBFS_ENABLE_HID_CLASS) - uint8 i; - - for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - { - USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; - } - #endif /* USBFS_ENABLE_HID_CLASS */ - - USBFS_transferState = USBFS_TRANS_STATE_IDLE; - - /* Clear all of the component data */ - USBFS_configuration = 0u; - USBFS_interfaceNumber = 0u; - USBFS_configurationChanged = 0u; - USBFS_deviceAddress = 0u; - USBFS_deviceStatus = 0u; - - USBFS_lastPacketSize = 0u; - - - /* ACK Setup, Stall IN/OUT */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - - /* Enable the SIE with an address 0 */ - CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); - -} - - -/******************************************************************************* -* Function Name: USBFS_Stop -******************************************************************************** -* -* Summary: -* This function shuts down the USB function including to release -* the D+ Pullup and disabling the SIE. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_configuration: Contains current configuration number -* which is set by the Host using SET_CONFIGURATION request. -* Initialized to zero in this API. -* USBFS_deviceAddress: Contains current device address. This -* variable is initialized to zero in this API. Host starts to communicate -* to device with address 0 and then set it to whatever value using -* SET_ADDRESS request. -* USBFS_deviceStatus: initialized to 0. -* This is two bit variable which contain power status in first bit -* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote -* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. -* USBFS_configurationChanged: This variable is set to one after -* SET_CONFIGURATION request and cleared in this function. -* USBFS_intiVar variable is set to zero -* -*******************************************************************************/ -void USBFS_Stop(void) -{ - - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - /* Disable the SIE */ - USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE); - /* Disable the d+ pullup */ - USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN); - /* Disable USB in ACT PM */ - USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB); - /* Disable USB block for Standby Power Mode */ - USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); - - /* Disable the reset and EP interrupts */ - CyIntDisable(USBFS_BUS_RESET_VECT_NUM); - CyIntDisable(USBFS_EP_0_VECT_NUM); - #if(USBFS_EP1_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_1_VECT_NUM); - #endif /* End USBFS_EP1_ISR_REMOVE */ - #if(USBFS_EP2_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_2_VECT_NUM); - #endif /* End USBFS_EP2_ISR_REMOVE */ - #if(USBFS_EP3_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_3_VECT_NUM); - #endif /* End USBFS_EP3_ISR_REMOVE */ - #if(USBFS_EP4_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_4_VECT_NUM); - #endif /* End USBFS_EP4_ISR_REMOVE */ - #if(USBFS_EP5_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_5_VECT_NUM); - #endif /* End USBFS_EP5_ISR_REMOVE */ - #if(USBFS_EP6_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_6_VECT_NUM); - #endif /* End USBFS_EP6_ISR_REMOVE */ - #if(USBFS_EP7_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_7_VECT_NUM); - #endif /* End USBFS_EP7_ISR_REMOVE */ - #if(USBFS_EP8_ISR_REMOVE == 0u) - CyIntDisable(USBFS_EP_8_VECT_NUM); - #endif /* End USBFS_EP8_ISR_REMOVE */ - - /* Clear all of the component data */ - USBFS_configuration = 0u; - USBFS_interfaceNumber = 0u; - USBFS_configurationChanged = 0u; - USBFS_deviceAddress = 0u; - USBFS_deviceStatus = 0u; - USBFS_initVar = 0u; - -} - - -/******************************************************************************* -* Function Name: USBFS_CheckActivity -******************************************************************************** -* -* Summary: -* Returns the activity status of the bus. Clears the status hardware to -* provide fresh activity status on the next call of this routine. -* -* Parameters: -* None. -* -* Return: -* 1 - If bus activity was detected since the last call to this function -* 0 - If bus activity not was detected since the last call to this function -* -*******************************************************************************/ -uint8 USBFS_CheckActivity(void) -{ - uint8 r; - - r = CY_GET_REG8(USBFS_CR1_PTR); - CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY)))); - - return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT); -} - - -/******************************************************************************* -* Function Name: USBFS_GetConfiguration -******************************************************************************** -* -* Summary: -* Returns the current configuration setting -* -* Parameters: -* None. -* -* Return: -* configuration. -* -*******************************************************************************/ -uint8 USBFS_GetConfiguration(void) -{ - return(USBFS_configuration); -} - - -/******************************************************************************* -* Function Name: USBFS_IsConfigurationChanged -******************************************************************************** -* -* Summary: -* Returns the clear on read configuration state. It is usefull when PC send -* double SET_CONFIGURATION request with same configuration number. -* -* Parameters: -* None. -* -* Return: -* Not zero value when new configuration has been changed, otherwise zero is -* returned. -* -* Global variables: -* USBFS_configurationChanged: This variable is set to one after -* SET_CONFIGURATION request and cleared in this function. -* -*******************************************************************************/ -uint8 USBFS_IsConfigurationChanged(void) -{ - uint8 res = 0u; - - if(USBFS_configurationChanged != 0u) - { - res = USBFS_configurationChanged; - USBFS_configurationChanged = 0u; - } - - return(res); -} - - -/******************************************************************************* -* Function Name: USBFS_GetInterfaceSetting -******************************************************************************** -* -* Summary: -* Returns the alternate setting from current interface -* -* Parameters: -* uint8 interfaceNumber, interface number -* -* Return: -* Alternate setting. -* -*******************************************************************************/ -uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) - -{ - return(USBFS_interfaceSetting[interfaceNumber]); -} - - -/******************************************************************************* -* Function Name: USBFS_GetEPState -******************************************************************************** -* -* Summary: -* Returned the state of the requested endpoint. -* -* Parameters: -* epNumber: Endpoint Number -* -* Return: -* State of the requested endpoint. -* -*******************************************************************************/ -uint8 USBFS_GetEPState(uint8 epNumber) -{ - return(USBFS_EP[epNumber].apiEpState); -} - - -/******************************************************************************* -* Function Name: USBFS_GetEPCount -******************************************************************************** -* -* Summary: -* This function supports Data Endpoints only(EP1-EP8). -* Returns the transfer count for the requested endpoint. The value from -* the count registers includes 2 counts for the two byte checksum of the -* packet. This function subtracts the two counts. -* -* Parameters: -* epNumber: Data Endpoint Number. -* Valid values are between 1 and 8. -* -* Return: -* Returns the current byte count from the specified endpoint or 0 for an -* invalid endpoint. -* -*******************************************************************************/ -uint16 USBFS_GetEPCount(uint8 epNumber) -{ - uint8 ri; - uint16 result = 0u; - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - - result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & - USBFS_EPX_CNT0_MASK); - result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri)); - result -= USBFS_EPX_CNTX_CRC_COUNT; - } - return(result); -} - - -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - - - /******************************************************************************* - * Function Name: USBFS_InitEP_DMA - ******************************************************************************** - * - * Summary: - * This function allocates and initializes a DMA channel to be used by the - * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data - * transfer. - * - * Parameters: - * epNumber: Contains the data endpoint number. - * Valid values are between 1 and 8. - * *pData: Pointer to a data array that is related to the EP transfers. - * - * Return: - * None. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) - - { - uint16 src; - uint16 dst; - #if (CY_PSOC3) /* PSoC 3 */ - src = HI16(CYDEV_SRAM_BASE); - dst = HI16(CYDEV_PERIPH_BASE); - pData = pData; - #else /* PSoC 5 */ - if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u ) - { /* for the IN EP source is the SRAM memory buffer */ - src = HI16(pData); - dst = HI16(CYDEV_PERIPH_BASE); - } - else - { /* for the OUT EP source is the SIE register */ - src = HI16(CYDEV_PERIPH_BASE); - dst = HI16(pData); - } - #endif /* End C51 */ - switch(epNumber) - { - case USBFS_EP1: - #if(USBFS_DMA1_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA1_REMOVE */ - break; - case USBFS_EP2: - #if(USBFS_DMA2_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA2_REMOVE */ - break; - case USBFS_EP3: - #if(USBFS_DMA3_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA3_REMOVE */ - break; - case USBFS_EP4: - #if(USBFS_DMA4_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA4_REMOVE */ - break; - case USBFS_EP5: - #if(USBFS_DMA5_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA5_REMOVE */ - break; - case USBFS_EP6: - #if(USBFS_DMA6_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA6_REMOVE */ - break; - case USBFS_EP7: - #if(USBFS_DMA7_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA7_REMOVE */ - break; - case USBFS_EP8: - #if(USBFS_DMA8_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* End USBFS_DMA8_REMOVE */ - break; - default: - /* Do not support EP0 DMA transfers */ - break; - } - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - { - USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); - } - } - - - /******************************************************************************* - * Function Name: USBFS_Stop_DMA - ******************************************************************************** - * - * Summary: Stops and free DMA - * - * Parameters: - * epNumber: Contains the data endpoint number or - * USBFS_MAX_EP to stop all DMAs - * - * Return: - * None. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_Stop_DMA(uint8 epNumber) - { - uint8 i; - i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; - do - { - if(USBFS_DmaTd[i] != DMA_INVALID_TD) - { - (void) CyDmaChDisable(USBFS_DmaChan[i]); - CyDmaTdFree(USBFS_DmaTd[i]); - USBFS_DmaTd[i] = DMA_INVALID_TD; - } - i++; - }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); - } - -#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - -/******************************************************************************* -* Function Name: USBFS_LoadInEP -******************************************************************************** -* -* Summary: -* Loads and enables the specified USB data endpoint for an IN interrupt or bulk -* transfer. -* -* Parameters: -* epNumber: Contains the data endpoint number. -* Valid values are between 1 and 8. -* *pData: A pointer to a data array from which the data for the endpoint space -* is loaded. -* length: The number of bytes to transfer from the array and then send as a -* result of an IN request. Valid values are between 0 and 512. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) - -{ - uint8 ri; - reg8 *p; - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - uint16 i; - #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); - - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */ - if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) - { - length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; - } - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - /* Set the count and data toggle */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), - (length >> 8u) | (USBFS_EP[epNumber].epToggle)); - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu); - - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - if(pData != NULL) - { - /* Copy the data using the arbiter data register */ - for (i = 0u; i < length; i++) - { - CY_SET_REG8(p, pData[i]); - } - } - USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - #else - /* Init DMA if it was not initialized */ - if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) - { - USBFS_InitEP_DMA(epNumber, pData); - } - #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ - - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - if((pData != NULL) && (length > 0u)) - { - /* Enable DMA in mode2 for transferring data */ - (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, - TD_TERMIN_EN | TD_INC_SRC_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); - /* Enable the DMA */ - (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); - (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - /* Generate DMA request */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); - /* Mode register will be written in arb ISR after DMA transfer complete */ - } - else - { - /* When zero-length packet - write the Mode register directly */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - } - #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - if(pData != NULL) - { - /* Enable DMA in mode3 for transferring data */ - (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, - USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); - /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ - (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); - /* Enable the DMA */ - (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); - (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - } - else - { - USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - if(length > 0u) - { - /* Set Data ready status, This will generate DMA request */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; - /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */ - } - else - { - /* When zero-length packet - write the Mode register directly */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - } - } - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - - } -} - - -/******************************************************************************* -* Function Name: USBFS_ReadOutEP -******************************************************************************** -* -* Summary: -* Read data from an endpoint. The application must call -* USBFS_GetEPState to see if an event is pending. -* -* Parameters: -* epNumber: Contains the data endpoint number. -* Valid values are between 1 and 8. -* pData: A pointer to a data array from which the data for the endpoint space -* is loaded. -* length: The number of bytes to transfer from the USB Out endpoint and loads -* it into data array. Valid values are between 0 and 1023. The function -* moves fewer than the requested number of bytes if the host sends -* fewer bytes than requested. -* -* Returns: -* Number of bytes received, 0 for an invalid endpoint. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) - -{ - uint8 ri; - reg8 *p; - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - uint16 i; - #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - uint16 xferCount; - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) - { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); - - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - /* Determine which is smaller the requested data or the available data */ - xferCount = USBFS_GetEPCount(epNumber); - if (length > xferCount) - { - length = xferCount; - } - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - /* Copy the data using the arbiter data register */ - for (i = 0u; i < length; i++) - { - pData[i] = CY_GET_REG8(p); - } - - /* (re)arming of OUT endpoint */ - USBFS_EnableOutEP(epNumber); - #else - /*Init DMA if it was not initialized */ - if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) - { - USBFS_InitEP_DMA(epNumber, pData); - } - #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */ - - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - /* Enable DMA in mode2 for transferring data */ - (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, - TD_TERMIN_EN | TD_INC_DST_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); - /* Enable the DMA */ - (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); - (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - - /* Generate DMA request */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); - /* Out EP will be (re)armed in arb ISR after transfer complete */ - #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* Enable DMA in mode3 for transferring data */ - (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], - TD_TERMIN_EN | TD_INC_DST_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); - - /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ - (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); - /* Enable the DMA */ - (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); - (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - /* Out EP will be (re)armed in arb ISR after transfer complete */ - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - - } - else - { - length = 0u; - } - - return(length); -} - - -/******************************************************************************* -* Function Name: USBFS_EnableOutEP -******************************************************************************** -* -* Summary: -* This function enables an OUT endpoint. It should not be -* called for an IN endpoint. -* -* Parameters: -* epNumber: Endpoint Number -* Valid values are between 1 and 8. -* -* Return: -* None. -* -* Global variables: -* USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_EnableOutEP(uint8 epNumber) -{ - uint8 ri; - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - } -} - - -/******************************************************************************* -* Function Name: USBFS_DisableOutEP -******************************************************************************** -* -* Summary: -* This function disables an OUT endpoint. It should not be -* called for an IN endpoint. -* -* Parameters: -* epNumber: Endpoint Number -* Valid values are between 1 and 8. -* -* Return: -* None. -* -*******************************************************************************/ -void USBFS_DisableOutEP(uint8 epNumber) -{ - uint8 ri ; - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); - } -} - - -/******************************************************************************* -* Function Name: USBFS_Force -******************************************************************************** -* -* Summary: -* Forces the bus state -* -* Parameters: -* bState -* USBFS_FORCE_J -* USBFS_FORCE_K -* USBFS_FORCE_SE0 -* USBFS_FORCE_NONE -* -* Return: -* None. -* -*******************************************************************************/ -void USBFS_Force(uint8 bState) -{ - CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState); -} - - -/******************************************************************************* -* Function Name: USBFS_GetEPAckState -******************************************************************************** -* -* Summary: -* Returns the ACK of the CR0 Register (ACKD) -* -* Parameters: -* epNumber: Endpoint Number -* Valid values are between 1 and 8. -* -* Returns -* 0 if nothing has been ACKD, non-=zero something has been ACKD -* -*******************************************************************************/ -uint8 USBFS_GetEPAckState(uint8 epNumber) -{ - uint8 ri; - uint8 cr = 0u; - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) - { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD; - } - - return(cr); -} - - -/******************************************************************************* -* Function Name: USBFS_SetPowerStatus -******************************************************************************** -* -* Summary: -* Sets the device power status for reporting in the Get Device Status -* request -* -* Parameters: -* powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered, -* USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered -* -* Return: -* None. -* -* Global variables: -* USBFS_deviceStatus - set power status -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_SetPowerStatus(uint8 powerStatus) -{ - if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) - { - USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; - } - else - { - USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED)); - } -} - - -#if (USBFS_MON_VBUS == 1u) - - /******************************************************************************* - * Function Name: USBFS_VBusPresent - ******************************************************************************** - * - * Summary: - * Determines VBUS presence for Self Powered Devices. - * - * Parameters: - * None. - * - * Return: - * 1 if VBUS is present, otherwise 0. - * - *******************************************************************************/ - uint8 USBFS_VBusPresent(void) - { - return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u); - } - -#endif /* USBFS_MON_VBUS */ - - -/******************************************************************************* -* Function Name: USBFS_RWUEnabled -******************************************************************************** -* -* Summary: -* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE -* -* Parameters: -* None. -* -* Return: -* TRUE - Remote Wake Up Enabled -* FALSE - Remote Wake Up Disabled -* -* Global variables: -* USBFS_deviceStatus - checked to determine remote status -* -*******************************************************************************/ -uint8 USBFS_RWUEnabled(void) -{ - uint8 result = USBFS_FALSE; - if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u) - { - result = USBFS_TRUE; - } - - return(result); -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS.h deleted file mode 100755 index e7fd899..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS.h +++ /dev/null @@ -1,1189 +0,0 @@ -/******************************************************************************* -* File Name: USBFS.h -* Version 2.60 -* -* Description: -* Header File for the USFS component. Contains prototypes and constant values. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_USBFS_USBFS_H) -#define CY_USBFS_USBFS_H - -#include "cytypes.h" -#include "cydevice_trm.h" -#include "cyfitter.h" -#include "CyLib.h" - - -/*************************************** -* Conditional Compilation Parameters -***************************************/ - -/* Check to see if required defines such as CY_PSOC5LP are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5LP) - #error Component USBFS_v2_60 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5LP) */ - - -/*************************************** -* Memory Type Definitions -***************************************/ - -/* Renamed Type Definitions for backward compatibility. -* Should not be used in new designs. -*/ -#define USBFS_CODE CYCODE -#define USBFS_FAR CYFAR -#if defined(__C51__) || defined(__CX51__) - #define USBFS_DATA data - #define USBFS_XDATA xdata -#else - #define USBFS_DATA - #define USBFS_XDATA -#endif /* End __C51__ */ -#define USBFS_NULL NULL - - -/*************************************** -* Enumerated Types and Parameters -***************************************/ - -#define USBFS__EP_MANUAL 0 -#define USBFS__EP_DMAMANUAL 1 -#define USBFS__EP_DMAAUTO 2 - -#define USBFS__MA_STATIC 0 -#define USBFS__MA_DYNAMIC 1 - - - -/*************************************** -* Initial Parameter Constants -***************************************/ - -#define USBFS_NUM_DEVICES (1u) -#define USBFS_ENABLE_DESCRIPTOR_STRINGS -#define USBFS_ENABLE_SN_STRING -#define USBFS_ENABLE_STRINGS -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u) -#define USBFS_ENABLE_HID_CLASS -#define USBFS_HID_RPT_1_SIZE_LSB (0x24u) -#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) -#define USBFS_MAX_REPORTID_NUMBER (0u) - -#define USBFS_MON_VBUS (0u) -#define USBFS_EXTERN_VBUS (0u) -#define USBFS_EXTERN_VND (0u) -#define USBFS_EXTERN_CLS (0u) -#define USBFS_MAX_INTERFACES_NUMBER (1u) -#define USBFS_EP0_ISR_REMOVE (0u) -#define USBFS_EP1_ISR_REMOVE (0u) -#define USBFS_EP2_ISR_REMOVE (0u) -#define USBFS_EP3_ISR_REMOVE (1u) -#define USBFS_EP4_ISR_REMOVE (1u) -#define USBFS_EP5_ISR_REMOVE (1u) -#define USBFS_EP6_ISR_REMOVE (1u) -#define USBFS_EP7_ISR_REMOVE (1u) -#define USBFS_EP8_ISR_REMOVE (1u) -#define USBFS_EP_MM (0u) -#define USBFS_EP_MA (0u) -#define USBFS_DMA1_REMOVE (1u) -#define USBFS_DMA2_REMOVE (1u) -#define USBFS_DMA3_REMOVE (1u) -#define USBFS_DMA4_REMOVE (1u) -#define USBFS_DMA5_REMOVE (1u) -#define USBFS_DMA6_REMOVE (1u) -#define USBFS_DMA7_REMOVE (1u) -#define USBFS_DMA8_REMOVE (1u) -#define USBFS_SOF_ISR_REMOVE (0u) -#define USBFS_ARB_ISR_REMOVE (0u) -#define USBFS_DP_ISR_REMOVE (0u) -#define USBFS_ENABLE_CDC_CLASS_API (1u) -#define USBFS_ENABLE_MIDI_API (1u) -#define USBFS_MIDI_EXT_MODE (0u) - - -/*************************************** -* Data Struct Definition -***************************************/ - -typedef struct -{ - uint8 attrib; - uint8 apiEpState; - uint8 hwEpState; - uint8 epToggle; - uint8 addr; - uint8 epMode; - uint16 buffOffset; - uint16 bufferSize; - uint8 interface; -} T_USBFS_EP_CTL_BLOCK; - -typedef struct -{ - uint8 interface; - uint8 altSetting; - uint8 addr; - uint8 attributes; - uint16 bufferSize; - uint8 bMisc; -} T_USBFS_EP_SETTINGS_BLOCK; - -typedef struct -{ - uint8 status; - uint16 length; -} T_USBFS_XFER_STATUS_BLOCK; - -typedef struct -{ - uint16 count; - volatile uint8 *pData; - T_USBFS_XFER_STATUS_BLOCK *pStatusBlock; -} T_USBFS_TD; - - -typedef struct -{ - uint8 c; - const void *p_list; -} T_USBFS_LUT; - -/* Resume/Suspend API Support */ -typedef struct -{ - uint8 enableState; - uint8 mode; -} USBFS_BACKUP_STRUCT; - - -/* Renamed structure fields for backward compatibility. -* Should not be used in new designs. -*/ -#define wBuffOffset buffOffset -#define wBufferSize bufferSize -#define bStatus status -#define wLength length -#define wCount count - -/* Renamed global variable for backward compatibility. -* Should not be used in new designs. -*/ -#define CurrentTD USBFS_currentTD - - -/*************************************** -* Function Prototypes -***************************************/ - -void USBFS_Start(uint8 device, uint8 mode) ; -void USBFS_Init(void) ; -void USBFS_InitComponent(uint8 device, uint8 mode) ; -void USBFS_Stop(void) ; -uint8 USBFS_CheckActivity(void) ; -uint8 USBFS_GetConfiguration(void) ; -uint8 USBFS_IsConfigurationChanged(void) ; -uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) - ; -uint8 USBFS_GetEPState(uint8 epNumber) ; -uint16 USBFS_GetEPCount(uint8 epNumber) ; -void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) - ; -uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) - ; -void USBFS_EnableOutEP(uint8 epNumber) ; -void USBFS_DisableOutEP(uint8 epNumber) ; -void USBFS_Force(uint8 bState) ; -uint8 USBFS_GetEPAckState(uint8 epNumber) ; -void USBFS_SetPowerStatus(uint8 powerStatus) ; -uint8 USBFS_RWUEnabled(void) ; -void USBFS_TerminateEP(uint8 ep) ; - -void USBFS_Suspend(void) ; -void USBFS_Resume(void) ; - -#if defined(USBFS_ENABLE_FWSN_STRING) - void USBFS_SerialNumString(uint8 snString[]) ; -#endif /* USBFS_ENABLE_FWSN_STRING */ -#if (USBFS_MON_VBUS == 1u) - uint8 USBFS_VBusPresent(void) ; -#endif /* End USBFS_MON_VBUS */ - -#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ - (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) - - void USBFS_CyBtldrCommStart(void) ; - void USBFS_CyBtldrCommStop(void) ; - void USBFS_CyBtldrCommReset(void) ; - cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL - ; - cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL - ; - - #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */ - #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */ - #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER - - /* These defines active if used USBFS interface as an - * IO Component for bootloading. When Custom_Interface selected - * in Bootloder configuration as the IO Component, user must - * provide these functions - */ - #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) - #define CyBtldrCommStart USBFS_CyBtldrCommStart - #define CyBtldrCommStop USBFS_CyBtldrCommStop - #define CyBtldrCommReset USBFS_CyBtldrCommReset - #define CyBtldrCommWrite USBFS_CyBtldrCommWrite - #define CyBtldrCommRead USBFS_CyBtldrCommRead - #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ - -#endif /* End CYDEV_BOOTLOADER_IO_COMP */ - -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) - ; - void USBFS_Stop_DMA(uint8 epNumber) ; -#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */ - -#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) - void USBFS_MIDI_EP_Init(void) ; - - #if (USBFS_MIDI_IN_BUFF_SIZE > 0) - void USBFS_MIDI_IN_Service(void) ; - uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) - ; - #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ - - #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - void USBFS_MIDI_OUT_EP_Service(void) ; - #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ - -#endif /* End USBFS_ENABLE_MIDI_API != 0u */ - -/* Renamed Functions for backward compatibility. -* Should not be used in new designs. -*/ - -#define USBFS_bCheckActivity USBFS_CheckActivity -#define USBFS_bGetConfiguration USBFS_GetConfiguration -#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting -#define USBFS_bGetEPState USBFS_GetEPState -#define USBFS_wGetEPCount USBFS_GetEPCount -#define USBFS_bGetEPAckState USBFS_GetEPAckState -#define USBFS_bRWUEnabled USBFS_RWUEnabled -#define USBFS_bVBusPresent USBFS_VBusPresent - -#define USBFS_bConfiguration USBFS_configuration -#define USBFS_bInterfaceSetting USBFS_interfaceSetting -#define USBFS_bDeviceAddress USBFS_deviceAddress -#define USBFS_bDeviceStatus USBFS_deviceStatus -#define USBFS_bDevice USBFS_device -#define USBFS_bTransferState USBFS_transferState -#define USBFS_bLastPacketSize USBFS_lastPacketSize - -#define USBFS_LoadEP USBFS_LoadInEP -#define USBFS_LoadInISOCEP USBFS_LoadInEP -#define USBFS_EnableOutISOCEP USBFS_EnableOutEP - -#define USBFS_SetVector CyIntSetVector -#define USBFS_SetPriority CyIntSetPriority -#define USBFS_EnableInt CyIntEnable - - -/*************************************** -* API Constants -***************************************/ - -#define USBFS_EP0 (0u) -#define USBFS_EP1 (1u) -#define USBFS_EP2 (2u) -#define USBFS_EP3 (3u) -#define USBFS_EP4 (4u) -#define USBFS_EP5 (5u) -#define USBFS_EP6 (6u) -#define USBFS_EP7 (7u) -#define USBFS_EP8 (8u) -#define USBFS_MAX_EP (9u) - -#define USBFS_TRUE (1u) -#define USBFS_FALSE (0u) - -#define USBFS_NO_EVENT_ALLOWED (2u) -#define USBFS_EVENT_PENDING (1u) -#define USBFS_NO_EVENT_PENDING (0u) - -#define USBFS_IN_BUFFER_FULL USBFS_NO_EVENT_PENDING -#define USBFS_IN_BUFFER_EMPTY USBFS_EVENT_PENDING -#define USBFS_OUT_BUFFER_FULL USBFS_EVENT_PENDING -#define USBFS_OUT_BUFFER_EMPTY USBFS_NO_EVENT_PENDING - -#define USBFS_FORCE_J (0xA0u) -#define USBFS_FORCE_K (0x80u) -#define USBFS_FORCE_SE0 (0xC0u) -#define USBFS_FORCE_NONE (0x00u) - -#define USBFS_IDLE_TIMER_RUNNING (0x02u) -#define USBFS_IDLE_TIMER_EXPIRED (0x01u) -#define USBFS_IDLE_TIMER_INDEFINITE (0x00u) - -#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) -#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) - -#define USBFS_3V_OPERATION (0x00u) -#define USBFS_5V_OPERATION (0x01u) -#define USBFS_DWR_VDDD_OPERATION (0x02u) - -#define USBFS_MODE_DISABLE (0x00u) -#define USBFS_MODE_NAK_IN_OUT (0x01u) -#define USBFS_MODE_STATUS_OUT_ONLY (0x02u) -#define USBFS_MODE_STALL_IN_OUT (0x03u) -#define USBFS_MODE_RESERVED_0100 (0x04u) -#define USBFS_MODE_ISO_OUT (0x05u) -#define USBFS_MODE_STATUS_IN_ONLY (0x06u) -#define USBFS_MODE_ISO_IN (0x07u) -#define USBFS_MODE_NAK_OUT (0x08u) -#define USBFS_MODE_ACK_OUT (0x09u) -#define USBFS_MODE_RESERVED_1010 (0x0Au) -#define USBFS_MODE_ACK_OUT_STATUS_IN (0x0Bu) -#define USBFS_MODE_NAK_IN (0x0Cu) -#define USBFS_MODE_ACK_IN (0x0Du) -#define USBFS_MODE_RESERVED_1110 (0x0Eu) -#define USBFS_MODE_ACK_IN_STATUS_OUT (0x0Fu) -#define USBFS_MODE_MASK (0x0Fu) -#define USBFS_MODE_STALL_DATA_EP (0x80u) - -#define USBFS_MODE_ACKD (0x10u) -#define USBFS_MODE_OUT_RCVD (0x20u) -#define USBFS_MODE_IN_RCVD (0x40u) -#define USBFS_MODE_SETUP_RCVD (0x80u) - -#define USBFS_RQST_TYPE_MASK (0x60u) -#define USBFS_RQST_TYPE_STD (0x00u) -#define USBFS_RQST_TYPE_CLS (0x20u) -#define USBFS_RQST_TYPE_VND (0x40u) -#define USBFS_RQST_DIR_MASK (0x80u) -#define USBFS_RQST_DIR_D2H (0x80u) -#define USBFS_RQST_DIR_H2D (0x00u) -#define USBFS_RQST_RCPT_MASK (0x03u) -#define USBFS_RQST_RCPT_DEV (0x00u) -#define USBFS_RQST_RCPT_IFC (0x01u) -#define USBFS_RQST_RCPT_EP (0x02u) -#define USBFS_RQST_RCPT_OTHER (0x03u) - -/* USB Class Codes */ -#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */ -#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */ -#define USBFS_CLASS_CDC (0x02u) /* Communication device class */ -#define USBFS_CLASS_HID (0x03u) /* Human Interface Device */ -#define USBFS_CLASS_PDC (0x05u) /* Physical device class */ -#define USBFS_CLASS_IMAGE (0x06u) /* Still Imaging device */ -#define USBFS_CLASS_PRINTER (0x07u) /* Printer device */ -#define USBFS_CLASS_MSD (0x08u) /* Mass Storage device */ -#define USBFS_CLASS_HUB (0x09u) /* Full/Hi speed Hub */ -#define USBFS_CLASS_CDC_DATA (0x0Au) /* CDC data device */ -#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */ -#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */ -#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */ -#define USBFS_CLASS_PHD (0x0Fu) /* Personal Healthcare device */ -#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */ -#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */ -#define USBFS_CLASS_APP (0xEFu) /* Application Specific */ -#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */ - - -/* Standard Request Types (Table 9-4) */ -#define USBFS_GET_STATUS (0x00u) -#define USBFS_CLEAR_FEATURE (0x01u) -#define USBFS_SET_FEATURE (0x03u) -#define USBFS_SET_ADDRESS (0x05u) -#define USBFS_GET_DESCRIPTOR (0x06u) -#define USBFS_SET_DESCRIPTOR (0x07u) -#define USBFS_GET_CONFIGURATION (0x08u) -#define USBFS_SET_CONFIGURATION (0x09u) -#define USBFS_GET_INTERFACE (0x0Au) -#define USBFS_SET_INTERFACE (0x0Bu) -#define USBFS_SYNCH_FRAME (0x0Cu) - -/* Vendor Specific Request Types */ -/* Request for Microsoft OS String Descriptor */ -#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u) - -/* Descriptor Types (Table 9-5) */ -#define USBFS_DESCR_DEVICE (1u) -#define USBFS_DESCR_CONFIG (2u) -#define USBFS_DESCR_STRING (3u) -#define USBFS_DESCR_INTERFACE (4u) -#define USBFS_DESCR_ENDPOINT (5u) -#define USBFS_DESCR_DEVICE_QUALIFIER (6u) -#define USBFS_DESCR_OTHER_SPEED (7u) -#define USBFS_DESCR_INTERFACE_POWER (8u) - -/* Device Descriptor Defines */ -#define USBFS_DEVICE_DESCR_LENGTH (18u) -#define USBFS_DEVICE_DESCR_SN_SHIFT (16u) - -/* Config Descriptor Shifts and Masks */ -#define USBFS_CONFIG_DESCR_LENGTH (0u) -#define USBFS_CONFIG_DESCR_TYPE (1u) -#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW (2u) -#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI (3u) -#define USBFS_CONFIG_DESCR_NUM_INTERFACES (4u) -#define USBFS_CONFIG_DESCR_CONFIG_VALUE (5u) -#define USBFS_CONFIG_DESCR_CONFIGURATION (6u) -#define USBFS_CONFIG_DESCR_ATTRIB (7u) -#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u) -#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u) - -/* Feature Selectors (Table 9-6) */ -#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u) -#define USBFS_ENDPOINT_HALT (0x00u) -#define USBFS_TEST_MODE (0x02u) - -/* USB Device Status (Figure 9-4) */ -#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) -#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) -#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP (0x02u) - -/* USB Endpoint Status (Figure 9-4) */ -#define USBFS_ENDPOINT_STATUS_HALT (0x01u) - -/* USB Endpoint Directions */ -#define USBFS_DIR_IN (0x80u) -#define USBFS_DIR_OUT (0x00u) -#define USBFS_DIR_UNUSED (0x7Fu) - -/* USB Endpoint Attributes */ -#define USBFS_EP_TYPE_CTRL (0x00u) -#define USBFS_EP_TYPE_ISOC (0x01u) -#define USBFS_EP_TYPE_BULK (0x02u) -#define USBFS_EP_TYPE_INT (0x03u) -#define USBFS_EP_TYPE_MASK (0x03u) - -#define USBFS_EP_SYNC_TYPE_NO_SYNC (0x00u) -#define USBFS_EP_SYNC_TYPE_ASYNC (0x04u) -#define USBFS_EP_SYNC_TYPE_ADAPTIVE (0x08u) -#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS (0x0Cu) -#define USBFS_EP_SYNC_TYPE_MASK (0x0Cu) - -#define USBFS_EP_USAGE_TYPE_DATA (0x00u) -#define USBFS_EP_USAGE_TYPE_FEEDBACK (0x10u) -#define USBFS_EP_USAGE_TYPE_IMPLICIT (0x20u) -#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u) -#define USBFS_EP_USAGE_TYPE_MASK (0x30u) - -/* Endpoint Status defines */ -#define USBFS_EP_STATUS_LENGTH (0x02u) - -/* Endpoint Device defines */ -#define USBFS_DEVICE_STATUS_LENGTH (0x02u) - -#define USBFS_STATUS_LENGTH_MAX \ - ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ - USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH ) -/* Transfer Completion Notification */ -#define USBFS_XFER_IDLE (0x00u) -#define USBFS_XFER_STATUS_ACK (0x01u) -#define USBFS_XFER_PREMATURE (0x02u) -#define USBFS_XFER_ERROR (0x03u) - -/* Driver State defines */ -#define USBFS_TRANS_STATE_IDLE (0x00u) -#define USBFS_TRANS_STATE_CONTROL_READ (0x02u) -#define USBFS_TRANS_STATE_CONTROL_WRITE (0x04u) -#define USBFS_TRANS_STATE_NO_DATA_CONTROL (0x06u) - -/* String Descriptor defines */ -#define USBFS_STRING_MSOS (0xEEu) -#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u) -#define USBFS_MSOS_CONF_DESCR_LENGTH (40u) - -#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - /* DMA manual mode defines */ - #define USBFS_DMA_BYTES_PER_BURST (0u) - #define USBFS_DMA_REQUEST_PER_BURST (0u) -#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ -#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* DMA automatic mode defines */ - #define USBFS_DMA_BYTES_PER_BURST (32u) - /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ - #define USBFS_DMA_BUF_SIZE (0x55u) - #define USBFS_DMA_REQUEST_PER_BURST (1u) -#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - -/* DIE ID string descriptor defines */ -#if defined(USBFS_ENABLE_IDSN_STRING) - #define USBFS_IDSN_DESCR_LENGTH (0x22u) -#endif /* USBFS_ENABLE_IDSN_STRING */ - - -/*************************************** -* External data references -***************************************/ - -extern uint8 USBFS_initVar; -extern volatile uint8 USBFS_device; -extern volatile uint8 USBFS_transferState; -extern volatile uint8 USBFS_configuration; -extern volatile uint8 USBFS_configurationChanged; -extern volatile uint8 USBFS_deviceStatus; - -/* HID Variables */ -#if defined(USBFS_ENABLE_HID_CLASS) - extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; - extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; - extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; -#endif /* USBFS_ENABLE_HID_CLASS */ - - -/*************************************** -* Registers -***************************************/ - -#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) -#define USBFS_ARB_CFG_REG (* (reg8 *) USBFS_USB__ARB_CFG) - -#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) -#define USBFS_ARB_EP1_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP1_CFG) -#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG -#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) -#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN) -#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN -#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) -#define USBFS_ARB_EP1_SR_REG (* (reg8 *) USBFS_USB__ARB_EP1_SR) -#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR - -#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) -#define USBFS_ARB_EP2_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP2_CFG) -#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) -#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN) -#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) -#define USBFS_ARB_EP2_SR_REG (* (reg8 *) USBFS_USB__ARB_EP2_SR) - -#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) -#define USBFS_ARB_EP3_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP3_CFG) -#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) -#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN) -#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) -#define USBFS_ARB_EP3_SR_REG (* (reg8 *) USBFS_USB__ARB_EP3_SR) - -#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) -#define USBFS_ARB_EP4_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP4_CFG) -#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) -#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN) -#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) -#define USBFS_ARB_EP4_SR_REG (* (reg8 *) USBFS_USB__ARB_EP4_SR) - -#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) -#define USBFS_ARB_EP5_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP5_CFG) -#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) -#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN) -#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) -#define USBFS_ARB_EP5_SR_REG (* (reg8 *) USBFS_USB__ARB_EP5_SR) - -#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) -#define USBFS_ARB_EP6_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP6_CFG) -#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) -#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN) -#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) -#define USBFS_ARB_EP6_SR_REG (* (reg8 *) USBFS_USB__ARB_EP6_SR) - -#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) -#define USBFS_ARB_EP7_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP7_CFG) -#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) -#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN) -#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) -#define USBFS_ARB_EP7_SR_REG (* (reg8 *) USBFS_USB__ARB_EP7_SR) - -#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) -#define USBFS_ARB_EP8_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP8_CFG) -#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) -#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN) -#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) -#define USBFS_ARB_EP8_SR_REG (* (reg8 *) USBFS_USB__ARB_EP8_SR) - -#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) -#define USBFS_ARB_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_INT_EN) -#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) -#define USBFS_ARB_INT_SR_REG (* (reg8 *) USBFS_USB__ARB_INT_SR) - -#define USBFS_ARB_RW1_DR_PTR ((reg8 *) USBFS_USB__ARB_RW1_DR) -#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR -#define USBFS_ARB_RW1_RA_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA) -#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA -#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB) -#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB -#define USBFS_ARB_RW1_WA_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA) -#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA -#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB) -#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB - -#define USBFS_ARB_RW2_DR_PTR ((reg8 *) USBFS_USB__ARB_RW2_DR) -#define USBFS_ARB_RW2_RA_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA) -#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB) -#define USBFS_ARB_RW2_WA_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA) -#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB) - -#define USBFS_ARB_RW3_DR_PTR ((reg8 *) USBFS_USB__ARB_RW3_DR) -#define USBFS_ARB_RW3_RA_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA) -#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB) -#define USBFS_ARB_RW3_WA_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA) -#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB) - -#define USBFS_ARB_RW4_DR_PTR ((reg8 *) USBFS_USB__ARB_RW4_DR) -#define USBFS_ARB_RW4_RA_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA) -#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB) -#define USBFS_ARB_RW4_WA_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA) -#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB) - -#define USBFS_ARB_RW5_DR_PTR ((reg8 *) USBFS_USB__ARB_RW5_DR) -#define USBFS_ARB_RW5_RA_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA) -#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB) -#define USBFS_ARB_RW5_WA_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA) -#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB) - -#define USBFS_ARB_RW6_DR_PTR ((reg8 *) USBFS_USB__ARB_RW6_DR) -#define USBFS_ARB_RW6_RA_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA) -#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB) -#define USBFS_ARB_RW6_WA_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA) -#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB) - -#define USBFS_ARB_RW7_DR_PTR ((reg8 *) USBFS_USB__ARB_RW7_DR) -#define USBFS_ARB_RW7_RA_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA) -#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB) -#define USBFS_ARB_RW7_WA_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA) -#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB) - -#define USBFS_ARB_RW8_DR_PTR ((reg8 *) USBFS_USB__ARB_RW8_DR) -#define USBFS_ARB_RW8_RA_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA) -#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB) -#define USBFS_ARB_RW8_WA_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA) -#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB) - -#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) -#define USBFS_BUF_SIZE_REG (* (reg8 *) USBFS_USB__BUF_SIZE) -#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) -#define USBFS_BUS_RST_CNT_REG (* (reg8 *) USBFS_USB__BUS_RST_CNT) -#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) -#define USBFS_CWA_REG (* (reg8 *) USBFS_USB__CWA) -#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) -#define USBFS_CWA_MSB_REG (* (reg8 *) USBFS_USB__CWA_MSB) -#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) -#define USBFS_CR0_REG (* (reg8 *) USBFS_USB__CR0) -#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) -#define USBFS_CR1_REG (* (reg8 *) USBFS_USB__CR1) - -#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) -#define USBFS_DMA_THRES_REG (* (reg8 *) USBFS_USB__DMA_THRES) -#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) -#define USBFS_DMA_THRES_MSB_REG (* (reg8 *) USBFS_USB__DMA_THRES_MSB) - -#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) -#define USBFS_EP_ACTIVE_REG (* (reg8 *) USBFS_USB__EP_ACTIVE) -#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) -#define USBFS_EP_TYPE_REG (* (reg8 *) USBFS_USB__EP_TYPE) - -#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) -#define USBFS_EP0_CNT_REG (* (reg8 *) USBFS_USB__EP0_CNT) -#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) -#define USBFS_EP0_CR_REG (* (reg8 *) USBFS_USB__EP0_CR) -#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) -#define USBFS_EP0_DR0_REG (* (reg8 *) USBFS_USB__EP0_DR0) -#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0 -#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) -#define USBFS_EP0_DR1_REG (* (reg8 *) USBFS_USB__EP0_DR1) -#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) -#define USBFS_EP0_DR2_REG (* (reg8 *) USBFS_USB__EP0_DR2) -#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) -#define USBFS_EP0_DR3_REG (* (reg8 *) USBFS_USB__EP0_DR3) -#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) -#define USBFS_EP0_DR4_REG (* (reg8 *) USBFS_USB__EP0_DR4) -#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) -#define USBFS_EP0_DR5_REG (* (reg8 *) USBFS_USB__EP0_DR5) -#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) -#define USBFS_EP0_DR6_REG (* (reg8 *) USBFS_USB__EP0_DR6) -#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) -#define USBFS_EP0_DR7_REG (* (reg8 *) USBFS_USB__EP0_DR7) - -#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) -#define USBFS_OSCLK_DR0_REG (* (reg8 *) USBFS_USB__OSCLK_DR0) -#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) -#define USBFS_OSCLK_DR1_REG (* (reg8 *) USBFS_USB__OSCLK_DR1) - -#define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) -#define USBFS_PM_ACT_CFG_REG (* (reg8 *) USBFS_USB__PM_ACT_CFG) -#define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) -#define USBFS_PM_STBY_CFG_REG (* (reg8 *) USBFS_USB__PM_STBY_CFG) - -#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) -#define USBFS_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_EN) -#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) -#define USBFS_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_SR) - -#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) -#define USBFS_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT0) -#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 -#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) -#define USBFS_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT1) -#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1 -#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) -#define USBFS_SIE_EP1_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CR0) -#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0 - -#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) -#define USBFS_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT0) -#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) -#define USBFS_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT1) -#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) -#define USBFS_SIE_EP2_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CR0) - -#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) -#define USBFS_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT0) -#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) -#define USBFS_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT1) -#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) -#define USBFS_SIE_EP3_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CR0) - -#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) -#define USBFS_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT0) -#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) -#define USBFS_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT1) -#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) -#define USBFS_SIE_EP4_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CR0) - -#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) -#define USBFS_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT0) -#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) -#define USBFS_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT1) -#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) -#define USBFS_SIE_EP5_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CR0) - -#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) -#define USBFS_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT0) -#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) -#define USBFS_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT1) -#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) -#define USBFS_SIE_EP6_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CR0) - -#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) -#define USBFS_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT0) -#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) -#define USBFS_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT1) -#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) -#define USBFS_SIE_EP7_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CR0) - -#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) -#define USBFS_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT0) -#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) -#define USBFS_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT1) -#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) -#define USBFS_SIE_EP8_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CR0) - -#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) -#define USBFS_SOF0_REG (* (reg8 *) USBFS_USB__SOF0) -#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) -#define USBFS_SOF1_REG (* (reg8 *) USBFS_USB__SOF1) - -#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) -#define USBFS_USB_CLK_EN_REG (* (reg8 *) USBFS_USB__USB_CLK_EN) - -#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) -#define USBFS_USBIO_CR0_REG (* (reg8 *) USBFS_USB__USBIO_CR0) -#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) -#define USBFS_USBIO_CR1_REG (* (reg8 *) USBFS_USB__USBIO_CR1) -#if(!CY_PSOC5LP) - #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) - #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) -#endif /* End CY_PSOC5LP */ - -#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE - -#define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) -#define USBFS_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0) -#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) -#define USBFS_DYN_RECONFIG_REG (* (reg8 *) USBFS_USB__DYN_RECONFIG) - -#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) -#define USBFS_DM_INP_DIS_REG (* (reg8 *) USBFS_Dm__INP_DIS) -#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) -#define USBFS_DP_INP_DIS_REG (* (reg8 *) USBFS_Dp__INP_DIS) -#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) -#define USBFS_DP_INTSTAT_REG (* (reg8 *) USBFS_Dp__INTSTAT) - -#if (USBFS_MON_VBUS == 1u) - #if (USBFS_EXTERN_VBUS == 0u) - #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) - #define USBFS_VBUS_DR_REG (* (reg8 *) USBFS_VBUS__DR) - #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) - #define USBFS_VBUS_PS_REG (* (reg8 *) USBFS_VBUS__PS) - #define USBFS_VBUS_MASK USBFS_VBUS__MASK - #else - #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG ) - #define USBFS_VBUS_MASK (0x01u) - #endif /* End USBFS_EXTERN_VBUS == 0u */ -#endif /* End USBFS_MON_VBUS */ - -/* Renamed Registers for backward compatibility. -* Should not be used in new designs. -*/ -#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR - -#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR -#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR -#define USBFS_ARB_EP1_SR USBFS_ARB_EP1_SR_PTR - -#define USBFS_ARB_EP2_CFG USBFS_ARB_EP2_CFG_PTR -#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR -#define USBFS_ARB_EP2_SR USBFS_ARB_EP2_SR_PTR - -#define USBFS_ARB_EP3_CFG USBFS_ARB_EP3_CFG_PTR -#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR -#define USBFS_ARB_EP3_SR USBFS_ARB_EP3_SR_PTR - -#define USBFS_ARB_EP4_CFG USBFS_ARB_EP4_CFG_PTR -#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR -#define USBFS_ARB_EP4_SR USBFS_ARB_EP4_SR_PTR - -#define USBFS_ARB_EP5_CFG USBFS_ARB_EP5_CFG_PTR -#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR -#define USBFS_ARB_EP5_SR USBFS_ARB_EP5_SR_PTR - -#define USBFS_ARB_EP6_CFG USBFS_ARB_EP6_CFG_PTR -#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR -#define USBFS_ARB_EP6_SR USBFS_ARB_EP6_SR_PTR - -#define USBFS_ARB_EP7_CFG USBFS_ARB_EP7_CFG_PTR -#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR -#define USBFS_ARB_EP7_SR USBFS_ARB_EP7_SR_PTR - -#define USBFS_ARB_EP8_CFG USBFS_ARB_EP8_CFG_PTR -#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR -#define USBFS_ARB_EP8_SR USBFS_ARB_EP8_SR_PTR - -#define USBFS_ARB_INT_EN USBFS_ARB_INT_EN_PTR -#define USBFS_ARB_INT_SR USBFS_ARB_INT_SR_PTR - -#define USBFS_ARB_RW1_DR USBFS_ARB_RW1_DR_PTR -#define USBFS_ARB_RW1_RA USBFS_ARB_RW1_RA_PTR -#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR -#define USBFS_ARB_RW1_WA USBFS_ARB_RW1_WA_PTR -#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR - -#define USBFS_ARB_RW2_DR USBFS_ARB_RW2_DR_PTR -#define USBFS_ARB_RW2_RA USBFS_ARB_RW2_RA_PTR -#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR -#define USBFS_ARB_RW2_WA USBFS_ARB_RW2_WA_PTR -#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR - -#define USBFS_ARB_RW3_DR USBFS_ARB_RW3_DR_PTR -#define USBFS_ARB_RW3_RA USBFS_ARB_RW3_RA_PTR -#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR -#define USBFS_ARB_RW3_WA USBFS_ARB_RW3_WA_PTR -#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR - -#define USBFS_ARB_RW4_DR USBFS_ARB_RW4_DR_PTR -#define USBFS_ARB_RW4_RA USBFS_ARB_RW4_RA_PTR -#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR -#define USBFS_ARB_RW4_WA USBFS_ARB_RW4_WA_PTR -#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR - -#define USBFS_ARB_RW5_DR USBFS_ARB_RW5_DR_PTR -#define USBFS_ARB_RW5_RA USBFS_ARB_RW5_RA_PTR -#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR -#define USBFS_ARB_RW5_WA USBFS_ARB_RW5_WA_PTR -#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR - -#define USBFS_ARB_RW6_DR USBFS_ARB_RW6_DR_PTR -#define USBFS_ARB_RW6_RA USBFS_ARB_RW6_RA_PTR -#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR -#define USBFS_ARB_RW6_WA USBFS_ARB_RW6_WA_PTR -#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR - -#define USBFS_ARB_RW7_DR USBFS_ARB_RW7_DR_PTR -#define USBFS_ARB_RW7_RA USBFS_ARB_RW7_RA_PTR -#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR -#define USBFS_ARB_RW7_WA USBFS_ARB_RW7_WA_PTR -#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR - -#define USBFS_ARB_RW8_DR USBFS_ARB_RW8_DR_PTR -#define USBFS_ARB_RW8_RA USBFS_ARB_RW8_RA_PTR -#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR -#define USBFS_ARB_RW8_WA USBFS_ARB_RW8_WA_PTR -#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR - -#define USBFS_BUF_SIZE USBFS_BUF_SIZE_PTR -#define USBFS_BUS_RST_CNT USBFS_BUS_RST_CNT_PTR -#define USBFS_CR0 USBFS_CR0_PTR -#define USBFS_CR1 USBFS_CR1_PTR -#define USBFS_CWA USBFS_CWA_PTR -#define USBFS_CWA_MSB USBFS_CWA_MSB_PTR - -#define USBFS_DMA_THRES USBFS_DMA_THRES_PTR -#define USBFS_DMA_THRES_MSB USBFS_DMA_THRES_MSB_PTR - -#define USBFS_EP_ACTIVE USBFS_EP_ACTIVE_PTR -#define USBFS_EP_TYPE USBFS_EP_TYPE_PTR - -#define USBFS_EP0_CNT USBFS_EP0_CNT_PTR -#define USBFS_EP0_CR USBFS_EP0_CR_PTR -#define USBFS_EP0_DR0 USBFS_EP0_DR0_PTR -#define USBFS_EP0_DR1 USBFS_EP0_DR1_PTR -#define USBFS_EP0_DR2 USBFS_EP0_DR2_PTR -#define USBFS_EP0_DR3 USBFS_EP0_DR3_PTR -#define USBFS_EP0_DR4 USBFS_EP0_DR4_PTR -#define USBFS_EP0_DR5 USBFS_EP0_DR5_PTR -#define USBFS_EP0_DR6 USBFS_EP0_DR6_PTR -#define USBFS_EP0_DR7 USBFS_EP0_DR7_PTR - -#define USBFS_OSCLK_DR0 USBFS_OSCLK_DR0_PTR -#define USBFS_OSCLK_DR1 USBFS_OSCLK_DR1_PTR - -#define USBFS_PM_ACT_CFG USBFS_PM_ACT_CFG_PTR -#define USBFS_PM_STBY_CFG USBFS_PM_STBY_CFG_PTR - -#define USBFS_SIE_EP_INT_EN USBFS_SIE_EP_INT_EN_PTR -#define USBFS_SIE_EP_INT_SR USBFS_SIE_EP_INT_SR_PTR - -#define USBFS_SIE_EP1_CNT0 USBFS_SIE_EP1_CNT0_PTR -#define USBFS_SIE_EP1_CNT1 USBFS_SIE_EP1_CNT1_PTR -#define USBFS_SIE_EP1_CR0 USBFS_SIE_EP1_CR0_PTR - -#define USBFS_SIE_EP2_CNT0 USBFS_SIE_EP2_CNT0_PTR -#define USBFS_SIE_EP2_CNT1 USBFS_SIE_EP2_CNT1_PTR -#define USBFS_SIE_EP2_CR0 USBFS_SIE_EP2_CR0_PTR - -#define USBFS_SIE_EP3_CNT0 USBFS_SIE_EP3_CNT0_PTR -#define USBFS_SIE_EP3_CNT1 USBFS_SIE_EP3_CNT1_PTR -#define USBFS_SIE_EP3_CR0 USBFS_SIE_EP3_CR0_PTR - -#define USBFS_SIE_EP4_CNT0 USBFS_SIE_EP4_CNT0_PTR -#define USBFS_SIE_EP4_CNT1 USBFS_SIE_EP4_CNT1_PTR -#define USBFS_SIE_EP4_CR0 USBFS_SIE_EP4_CR0_PTR - -#define USBFS_SIE_EP5_CNT0 USBFS_SIE_EP5_CNT0_PTR -#define USBFS_SIE_EP5_CNT1 USBFS_SIE_EP5_CNT1_PTR -#define USBFS_SIE_EP5_CR0 USBFS_SIE_EP5_CR0_PTR - -#define USBFS_SIE_EP6_CNT0 USBFS_SIE_EP6_CNT0_PTR -#define USBFS_SIE_EP6_CNT1 USBFS_SIE_EP6_CNT1_PTR -#define USBFS_SIE_EP6_CR0 USBFS_SIE_EP6_CR0_PTR - -#define USBFS_SIE_EP7_CNT0 USBFS_SIE_EP7_CNT0_PTR -#define USBFS_SIE_EP7_CNT1 USBFS_SIE_EP7_CNT1_PTR -#define USBFS_SIE_EP7_CR0 USBFS_SIE_EP7_CR0_PTR - -#define USBFS_SIE_EP8_CNT0 USBFS_SIE_EP8_CNT0_PTR -#define USBFS_SIE_EP8_CNT1 USBFS_SIE_EP8_CNT1_PTR -#define USBFS_SIE_EP8_CR0 USBFS_SIE_EP8_CR0_PTR - -#define USBFS_SOF0 USBFS_SOF0_PTR -#define USBFS_SOF1 USBFS_SOF1_PTR - -#define USBFS_USB_CLK_EN USBFS_USB_CLK_EN_PTR - -#define USBFS_USBIO_CR0 USBFS_USBIO_CR0_PTR -#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR -#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR - -#define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) - -#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) - /* PSoC3 interrupt registers*/ - #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) - #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) - #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) - #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) -#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) - /* PSoC5 interrupt registers*/ - #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) - #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) - #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) - #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) -#endif /* End CYDEV_CHIP_DIE_EXPECT */ - - -/*************************************** -* Interrupt vectors, masks and priorities -***************************************/ - -#define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM -#define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK -#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER - -#define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM -#define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK -#define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER - -#define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM -#define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK -#define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER - -#define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM -#define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK -#define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER - -#define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM -#define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK -#define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER - -#define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM -#define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK -#define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER - -#define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM -#define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK -#define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER - -#define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM -#define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK -#define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER - -#define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM -#define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK -#define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER - -#define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM -#define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK -#define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER - -#define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM -#define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK -#define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER - -#define USBFS_DP_INTC_PRIOR USBFS_dp_int__INTC_PRIOR_NUM -#define USBFS_DP_INTC_MASK USBFS_dp_int__INTC_MASK -#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER - -/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */ -#define USBFS_ARB_PRIOR (0u) -#define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK -#define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER - -/*************************************** - * Endpoint 0 offsets (Table 9-2) - **************************************/ - -#define USBFS_bmRequestType USBFS_EP0_DR0_PTR -#define USBFS_bRequest USBFS_EP0_DR1_PTR -#define USBFS_wValue USBFS_EP0_DR2_PTR -#define USBFS_wValueHi USBFS_EP0_DR3_PTR -#define USBFS_wValueLo USBFS_EP0_DR2_PTR -#define USBFS_wIndex USBFS_EP0_DR4_PTR -#define USBFS_wIndexHi USBFS_EP0_DR5_PTR -#define USBFS_wIndexLo USBFS_EP0_DR4_PTR -#define USBFS_length USBFS_EP0_DR6_PTR -#define USBFS_lengthHi USBFS_EP0_DR7_PTR -#define USBFS_lengthLo USBFS_EP0_DR6_PTR - - -/*************************************** -* Register Constants -***************************************/ -#define USBFS_VDDD_MV CYDEV_VDDD_MV -#define USBFS_3500MV (3500u) - -#define USBFS_CR1_REG_ENABLE (0x01u) -#define USBFS_CR1_ENABLE_LOCK (0x02u) -#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) -#define USBFS_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT)) -#define USBFS_CR1_TRIM_MSB_EN (0x08u) - -#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) -#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) -#define USBFS_EPX_CNT0_MASK (0x0Fu) -#define USBFS_EPX_CNTX_MSB_MASK (0x07u) -#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) -#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) -#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) -#define USBFS_EPX_DATA_BUF_MAX (512u) - -#define USBFS_CR0_ENABLE (0x80u) - -/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */ -#define USBFS_BUS_RST_COUNT (0x0au) - -#define USBFS_USBIO_CR1_IOMODE (0x20u) -#define USBFS_USBIO_CR1_USBPUEN (0x04u) -#define USBFS_USBIO_CR1_DP0 (0x02u) -#define USBFS_USBIO_CR1_DM0 (0x01u) - -#define USBFS_USBIO_CR0_TEN (0x80u) -#define USBFS_USBIO_CR0_TSE0 (0x40u) -#define USBFS_USBIO_CR0_TD (0x20u) -#define USBFS_USBIO_CR0_RD (0x01u) - -#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) -#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) -#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) - -#define USBFS_ARB_EPX_CFG_RESET (0x08u) -#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u) -#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u) -#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u) - -#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) -#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) -#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) -#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) - -#define USBFS_ARB_CFG_AUTO_MEM (0x10u) -#define USBFS_ARB_CFG_MANUAL_DMA (0x20u) -#define USBFS_ARB_CFG_AUTO_DMA (0x40u) -#define USBFS_ARB_CFG_CFG_CPM (0x80u) - -#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - #define USBFS_ARB_EPX_INT_MASK (0x1Du) -#else - #define USBFS_ARB_EPX_INT_MASK (0x1Fu) -#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ -#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \ - (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \ - (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \ - (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \ - (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \ - (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \ - (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \ - (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) ) - -#define USBFS_SIE_EP_INT_EP1_MASK (0x01u) -#define USBFS_SIE_EP_INT_EP2_MASK (0x02u) -#define USBFS_SIE_EP_INT_EP3_MASK (0x04u) -#define USBFS_SIE_EP_INT_EP4_MASK (0x08u) -#define USBFS_SIE_EP_INT_EP5_MASK (0x10u) -#define USBFS_SIE_EP_INT_EP6_MASK (0x20u) -#define USBFS_SIE_EP_INT_EP7_MASK (0x40u) -#define USBFS_SIE_EP_INT_EP8_MASK (0x80u) - -#define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK -#define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK -#define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) - -#define USBFS_PM_USB_CR0_REF_EN (0x01u) -#define USBFS_PM_USB_CR0_PD_N (0x02u) -#define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) - -#define USBFS_USB_CLK_ENABLE (0x01u) - -#define USBFS_DM_MASK USBFS_Dm__0__MASK -#define USBFS_DP_MASK USBFS_Dp__0__MASK - -#define USBFS_DYN_RECONFIG_ENABLE (0x01u) -#define USBFS_DYN_RECONFIG_EP_SHIFT (0x01u) -#define USBFS_DYN_RECONFIG_RDY_STS (0x10u) - - -#endif /* End CY_USBFS_USBFS_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm.c deleted file mode 100755 index afae8fa..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm.c +++ /dev/null @@ -1,137 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_Dm.c -* Version 1.90 -* -* Description: -* This file contains API to enable firmware control of a Pins component. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "cytypes.h" -#include "USBFS_Dm.h" - -/* APIs are not generated for P15[7:6] on PSoC 5 */ -#if !(CY_PSOC5A &&\ - USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) - - -/******************************************************************************* -* Function Name: USBFS_Dm_Write -******************************************************************************** -* -* Summary: -* Assign a new value to the digital port's data output register. -* -* Parameters: -* prtValue: The value to be assigned to the Digital Port. -* -* Return: -* None -* -*******************************************************************************/ -void USBFS_Dm_Write(uint8 value) -{ - uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK)); - USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK); -} - - -/******************************************************************************* -* Function Name: USBFS_Dm_SetDriveMode -******************************************************************************** -* -* Summary: -* Change the drive mode on the pins of the port. -* -* Parameters: -* mode: Change the pins to this drive mode. -* -* Return: -* None -* -*******************************************************************************/ -void USBFS_Dm_SetDriveMode(uint8 mode) -{ - CyPins_SetPinDriveMode(USBFS_Dm_0, mode); -} - - -/******************************************************************************* -* Function Name: USBFS_Dm_Read -******************************************************************************** -* -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. -* -* Parameters: -* None -* -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro USBFS_Dm_ReadPS calls this function. -* -*******************************************************************************/ -uint8 USBFS_Dm_Read(void) -{ - return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; -} - - -/******************************************************************************* -* Function Name: USBFS_Dm_ReadDataReg -******************************************************************************** -* -* Summary: -* Read the current value assigned to a Digital Port's data output register -* -* Parameters: -* None -* -* Return: -* Returns the current value assigned to the Digital Port's data output register -* -*******************************************************************************/ -uint8 USBFS_Dm_ReadDataReg(void) -{ - return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; -} - - -/* If Interrupts Are Enabled for this Pins component */ -#if defined(USBFS_Dm_INTSTAT) - - /******************************************************************************* - * Function Name: USBFS_Dm_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. - * - * Parameters: - * None - * - * Return: - * Returns the value of the interrupt status register - * - *******************************************************************************/ - uint8 USBFS_Dm_ClearInterrupt(void) - { - return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; - } - -#endif /* If Interrupts Are Enabled for this Pins component */ - -#endif /* CY_PSOC5A... */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm.h deleted file mode 100755 index c1aa9b9..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm.h +++ /dev/null @@ -1,130 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_Dm.h -* Version 1.90 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_PINS_USBFS_Dm_H) /* Pins USBFS_Dm_H */ -#define CY_PINS_USBFS_Dm_H - -#include "cytypes.h" -#include "cyfitter.h" -#include "cypins.h" -#include "USBFS_Dm_aliases.h" - -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v1_90 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - -/* APIs are not generated for P15[7:6] */ -#if !(CY_PSOC5A &&\ - USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) - - -/*************************************** -* Function Prototypes -***************************************/ - -void USBFS_Dm_Write(uint8 value) ; -void USBFS_Dm_SetDriveMode(uint8 mode) ; -uint8 USBFS_Dm_ReadDataReg(void) ; -uint8 USBFS_Dm_Read(void) ; -uint8 USBFS_Dm_ClearInterrupt(void) ; - - -/*************************************** -* API Constants -***************************************/ - -/* Drive Modes */ -#define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP -#define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN -#define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO -#define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI -#define USBFS_Dm_DM_STRONG PIN_DM_STRONG -#define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN - -/* Digital Port Constants */ -#define USBFS_Dm_MASK USBFS_Dm__MASK -#define USBFS_Dm_SHIFT USBFS_Dm__SHIFT -#define USBFS_Dm_WIDTH 1u - - -/*************************************** -* Registers -***************************************/ - -/* Main Port Registers */ -/* Pin State */ -#define USBFS_Dm_PS (* (reg8 *) USBFS_Dm__PS) -/* Data Register */ -#define USBFS_Dm_DR (* (reg8 *) USBFS_Dm__DR) -/* Port Number */ -#define USBFS_Dm_PRT_NUM (* (reg8 *) USBFS_Dm__PRT) -/* Connect to Analog Globals */ -#define USBFS_Dm_AG (* (reg8 *) USBFS_Dm__AG) -/* Analog MUX bux enable */ -#define USBFS_Dm_AMUX (* (reg8 *) USBFS_Dm__AMUX) -/* Bidirectional Enable */ -#define USBFS_Dm_BIE (* (reg8 *) USBFS_Dm__BIE) -/* Bit-mask for Aliased Register Access */ -#define USBFS_Dm_BIT_MASK (* (reg8 *) USBFS_Dm__BIT_MASK) -/* Bypass Enable */ -#define USBFS_Dm_BYP (* (reg8 *) USBFS_Dm__BYP) -/* Port wide control signals */ -#define USBFS_Dm_CTL (* (reg8 *) USBFS_Dm__CTL) -/* Drive Modes */ -#define USBFS_Dm_DM0 (* (reg8 *) USBFS_Dm__DM0) -#define USBFS_Dm_DM1 (* (reg8 *) USBFS_Dm__DM1) -#define USBFS_Dm_DM2 (* (reg8 *) USBFS_Dm__DM2) -/* Input Buffer Disable Override */ -#define USBFS_Dm_INP_DIS (* (reg8 *) USBFS_Dm__INP_DIS) -/* LCD Common or Segment Drive */ -#define USBFS_Dm_LCD_COM_SEG (* (reg8 *) USBFS_Dm__LCD_COM_SEG) -/* Enable Segment LCD */ -#define USBFS_Dm_LCD_EN (* (reg8 *) USBFS_Dm__LCD_EN) -/* Slew Rate Control */ -#define USBFS_Dm_SLW (* (reg8 *) USBFS_Dm__SLW) - -/* DSI Port Registers */ -/* Global DSI Select Register */ -#define USBFS_Dm_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dm__PRTDSI__CAPS_SEL) -/* Double Sync Enable */ -#define USBFS_Dm_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dm__PRTDSI__DBL_SYNC_IN) -/* Output Enable Select Drive Strength */ -#define USBFS_Dm_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL0) -#define USBFS_Dm_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL1) -/* Port Pin Output Select Registers */ -#define USBFS_Dm_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL0) -#define USBFS_Dm_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL1) -/* Sync Output Enable Registers */ -#define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) - - -#if defined(USBFS_Dm__INTSTAT) /* Interrupt Registers */ - - #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT) - #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP) - -#endif /* Interrupt Registers */ - -#endif /* CY_PSOC5A... */ - -#endif /* CY_PINS_USBFS_Dm_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm_aliases.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm_aliases.h deleted file mode 100755 index bc4f686..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dm_aliases.h +++ /dev/null @@ -1,32 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_Dm.h -* Version 1.90 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_PINS_USBFS_Dm_ALIASES_H) /* Pins USBFS_Dm_ALIASES_H */ -#define CY_PINS_USBFS_Dm_ALIASES_H - -#include "cytypes.h" -#include "cyfitter.h" - - - -/*************************************** -* Constants -***************************************/ -#define USBFS_Dm_0 USBFS_Dm__0__PC - -#endif /* End Pins USBFS_Dm_ALIASES_H */ - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp.c deleted file mode 100755 index 304d5d6..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp.c +++ /dev/null @@ -1,137 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_Dp.c -* Version 1.90 -* -* Description: -* This file contains API to enable firmware control of a Pins component. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "cytypes.h" -#include "USBFS_Dp.h" - -/* APIs are not generated for P15[7:6] on PSoC 5 */ -#if !(CY_PSOC5A &&\ - USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) - - -/******************************************************************************* -* Function Name: USBFS_Dp_Write -******************************************************************************** -* -* Summary: -* Assign a new value to the digital port's data output register. -* -* Parameters: -* prtValue: The value to be assigned to the Digital Port. -* -* Return: -* None -* -*******************************************************************************/ -void USBFS_Dp_Write(uint8 value) -{ - uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK)); - USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK); -} - - -/******************************************************************************* -* Function Name: USBFS_Dp_SetDriveMode -******************************************************************************** -* -* Summary: -* Change the drive mode on the pins of the port. -* -* Parameters: -* mode: Change the pins to this drive mode. -* -* Return: -* None -* -*******************************************************************************/ -void USBFS_Dp_SetDriveMode(uint8 mode) -{ - CyPins_SetPinDriveMode(USBFS_Dp_0, mode); -} - - -/******************************************************************************* -* Function Name: USBFS_Dp_Read -******************************************************************************** -* -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. -* -* Parameters: -* None -* -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro USBFS_Dp_ReadPS calls this function. -* -*******************************************************************************/ -uint8 USBFS_Dp_Read(void) -{ - return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; -} - - -/******************************************************************************* -* Function Name: USBFS_Dp_ReadDataReg -******************************************************************************** -* -* Summary: -* Read the current value assigned to a Digital Port's data output register -* -* Parameters: -* None -* -* Return: -* Returns the current value assigned to the Digital Port's data output register -* -*******************************************************************************/ -uint8 USBFS_Dp_ReadDataReg(void) -{ - return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; -} - - -/* If Interrupts Are Enabled for this Pins component */ -#if defined(USBFS_Dp_INTSTAT) - - /******************************************************************************* - * Function Name: USBFS_Dp_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. - * - * Parameters: - * None - * - * Return: - * Returns the value of the interrupt status register - * - *******************************************************************************/ - uint8 USBFS_Dp_ClearInterrupt(void) - { - return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; - } - -#endif /* If Interrupts Are Enabled for this Pins component */ - -#endif /* CY_PSOC5A... */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp.h deleted file mode 100755 index 2d03ad9..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp.h +++ /dev/null @@ -1,130 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_Dp.h -* Version 1.90 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_PINS_USBFS_Dp_H) /* Pins USBFS_Dp_H */ -#define CY_PINS_USBFS_Dp_H - -#include "cytypes.h" -#include "cyfitter.h" -#include "cypins.h" -#include "USBFS_Dp_aliases.h" - -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v1_90 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - -/* APIs are not generated for P15[7:6] */ -#if !(CY_PSOC5A &&\ - USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) - - -/*************************************** -* Function Prototypes -***************************************/ - -void USBFS_Dp_Write(uint8 value) ; -void USBFS_Dp_SetDriveMode(uint8 mode) ; -uint8 USBFS_Dp_ReadDataReg(void) ; -uint8 USBFS_Dp_Read(void) ; -uint8 USBFS_Dp_ClearInterrupt(void) ; - - -/*************************************** -* API Constants -***************************************/ - -/* Drive Modes */ -#define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP -#define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN -#define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO -#define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI -#define USBFS_Dp_DM_STRONG PIN_DM_STRONG -#define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN - -/* Digital Port Constants */ -#define USBFS_Dp_MASK USBFS_Dp__MASK -#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT -#define USBFS_Dp_WIDTH 1u - - -/*************************************** -* Registers -***************************************/ - -/* Main Port Registers */ -/* Pin State */ -#define USBFS_Dp_PS (* (reg8 *) USBFS_Dp__PS) -/* Data Register */ -#define USBFS_Dp_DR (* (reg8 *) USBFS_Dp__DR) -/* Port Number */ -#define USBFS_Dp_PRT_NUM (* (reg8 *) USBFS_Dp__PRT) -/* Connect to Analog Globals */ -#define USBFS_Dp_AG (* (reg8 *) USBFS_Dp__AG) -/* Analog MUX bux enable */ -#define USBFS_Dp_AMUX (* (reg8 *) USBFS_Dp__AMUX) -/* Bidirectional Enable */ -#define USBFS_Dp_BIE (* (reg8 *) USBFS_Dp__BIE) -/* Bit-mask for Aliased Register Access */ -#define USBFS_Dp_BIT_MASK (* (reg8 *) USBFS_Dp__BIT_MASK) -/* Bypass Enable */ -#define USBFS_Dp_BYP (* (reg8 *) USBFS_Dp__BYP) -/* Port wide control signals */ -#define USBFS_Dp_CTL (* (reg8 *) USBFS_Dp__CTL) -/* Drive Modes */ -#define USBFS_Dp_DM0 (* (reg8 *) USBFS_Dp__DM0) -#define USBFS_Dp_DM1 (* (reg8 *) USBFS_Dp__DM1) -#define USBFS_Dp_DM2 (* (reg8 *) USBFS_Dp__DM2) -/* Input Buffer Disable Override */ -#define USBFS_Dp_INP_DIS (* (reg8 *) USBFS_Dp__INP_DIS) -/* LCD Common or Segment Drive */ -#define USBFS_Dp_LCD_COM_SEG (* (reg8 *) USBFS_Dp__LCD_COM_SEG) -/* Enable Segment LCD */ -#define USBFS_Dp_LCD_EN (* (reg8 *) USBFS_Dp__LCD_EN) -/* Slew Rate Control */ -#define USBFS_Dp_SLW (* (reg8 *) USBFS_Dp__SLW) - -/* DSI Port Registers */ -/* Global DSI Select Register */ -#define USBFS_Dp_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dp__PRTDSI__CAPS_SEL) -/* Double Sync Enable */ -#define USBFS_Dp_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dp__PRTDSI__DBL_SYNC_IN) -/* Output Enable Select Drive Strength */ -#define USBFS_Dp_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL0) -#define USBFS_Dp_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL1) -/* Port Pin Output Select Registers */ -#define USBFS_Dp_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL0) -#define USBFS_Dp_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL1) -/* Sync Output Enable Registers */ -#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) - - -#if defined(USBFS_Dp__INTSTAT) /* Interrupt Registers */ - - #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) - #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) - -#endif /* Interrupt Registers */ - -#endif /* CY_PSOC5A... */ - -#endif /* CY_PINS_USBFS_Dp_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp_aliases.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp_aliases.h deleted file mode 100755 index b77c3b9..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_Dp_aliases.h +++ /dev/null @@ -1,32 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_Dp.h -* Version 1.90 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_PINS_USBFS_Dp_ALIASES_H) /* Pins USBFS_Dp_ALIASES_H */ -#define CY_PINS_USBFS_Dp_ALIASES_H - -#include "cytypes.h" -#include "cyfitter.h" - - - -/*************************************** -* Constants -***************************************/ -#define USBFS_Dp_0 USBFS_Dp__0__PC - -#endif /* End Pins USBFS_Dp_ALIASES_H */ - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_audio.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_audio.c deleted file mode 100755 index cec388b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_audio.c +++ /dev/null @@ -1,318 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_audio.c -* Version 2.60 -* -* Description: -* USB AUDIO Class request handler. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" - -#if defined(USBFS_ENABLE_AUDIO_CLASS) - -#include "USBFS_audio.h" -#include "USBFS_pvt.h" -#if defined(USBFS_ENABLE_MIDI_STREAMING) - #include "USBFS_midi.h" -#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - - -/*************************************** -* Custom Declarations -***************************************/ - -/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -#if !defined(USER_SUPPLIED_AUDIO_HANDLER) - - -/*************************************** -* AUDIO Variables -***************************************/ - -#if defined(USBFS_ENABLE_AUDIO_STREAMING) - volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; - volatile uint8 USBFS_frequencyChanged; - volatile uint8 USBFS_currentMute; - volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; - volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB, - USBFS_VOL_MIN_MSB}; - volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MAX_LSB, - USBFS_VOL_MAX_MSB}; - volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB, - USBFS_VOL_RES_MSB}; -#endif /* End USBFS_ENABLE_AUDIO_STREAMING */ - - -/******************************************************************************* -* Function Name: USBFS_DispatchAUDIOClassRqst -******************************************************************************** -* -* Summary: -* This routine dispatches class requests -* -* Parameters: -* None. -* -* Return: -* requestHandled -* -* Global variables: -* USBFS_currentSampleFrequency: Contains the current audio Sample -* Frequency. It is set by the Host using SET_CUR request to the endpoint. -* USBFS_frequencyChanged: This variable is used as a flag for the -* user code, to be aware that Host has been sent request for changing -* Sample Frequency. Sample frequency will be sent on the next OUT -* transaction. It is contains endpoint address when set. The following -* code is recommended for detecting new Sample Frequency in main code: -* if((USBFS_frequencyChanged != 0) && -* (USBFS_transferState == USBFS_TRANS_STATE_IDLE)) -* { -* USBFS_frequencyChanged = 0; -* } -* USBFS_transferState variable is checked to be sure that -* transfer completes. -* USBFS_currentMute: Contains mute configuration set by Host. -* USBFS_currentVolume: Contains volume level set by Host. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_DispatchAUDIOClassRqst(void) -{ - uint8 requestHandled = USBFS_FALSE; - - #if defined(USBFS_ENABLE_AUDIO_STREAMING) - uint8 epNumber; - epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ - - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - { - /* Control Read */ - if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ - USBFS_RQST_RCPT_EP) - { - /* Endpoint */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_GET_CUR: - #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) - { - /* Endpoint Control Selector is Sampling Frequency */ - USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; - USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; - requestHandled = USBFS_InitControlRead(); - } - #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ - - /* `#START AUDIO_READ_REQUESTS` Place other request handler here */ - - /* `#END` */ - break; - default: - break; - } - } - else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ - USBFS_RQST_RCPT_IFC) - { - /* Interface or Entity ID */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_GET_CUR: - #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) - { - /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */ - - /* `#END` */ - - /* Entity ID Control Selector is MUTE */ - USBFS_currentTD.wCount = 1u; - USBFS_currentTD.pData = &USBFS_currentMute; - requestHandled = USBFS_InitControlRead(); - } - else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) - { - /* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */ - - /* `#END` */ - - /* Entity ID Control Selector is VOLUME, */ - USBFS_currentTD.wCount = USBFS_VOLUME_LEN; - USBFS_currentTD.pData = USBFS_currentVolume; - requestHandled = USBFS_InitControlRead(); - } - else - { - /* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */ - - /* `#END` */ - } - break; - case USBFS_GET_MIN: /* GET_MIN */ - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) - { - /* Entity ID Control Selector is VOLUME, */ - USBFS_currentTD.wCount = USBFS_VOLUME_LEN; - USBFS_currentTD.pData = &USBFS_minimumVolume[0]; - requestHandled = USBFS_InitControlRead(); - } - break; - case USBFS_GET_MAX: /* GET_MAX */ - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) - { - /* Entity ID Control Selector is VOLUME, */ - USBFS_currentTD.wCount = USBFS_VOLUME_LEN; - USBFS_currentTD.pData = &USBFS_maximumVolume[0]; - requestHandled = USBFS_InitControlRead(); - } - break; - case USBFS_GET_RES: /* GET_RES */ - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) - { - /* Entity ID Control Selector is VOLUME, */ - USBFS_currentTD.wCount = USBFS_VOLUME_LEN; - USBFS_currentTD.pData = &USBFS_resolutionVolume[0]; - requestHandled = USBFS_InitControlRead(); - } - break; - /* The contents of the status message is reserved for future use. - * For the time being, a null packet should be returned in the data stage of the - * control transfer, and the received null packet should be ACKed. - */ - case USBFS_GET_STAT: - USBFS_currentTD.wCount = 0u; - requestHandled = USBFS_InitControlWrite(); - - #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ - - /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */ - - /* `#END` */ - break; - default: - break; - } - } - else - { /* USBFS_RQST_RCPT_OTHER */ - } - } - else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ - USBFS_RQST_DIR_H2D) - { - /* Control Write */ - if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ - USBFS_RQST_RCPT_EP) - { - /* Endpoint */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_SET_CUR: - #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) - { - /* Endpoint Control Selector is Sampling Frequency */ - USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; - USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; - requestHandled = USBFS_InitControlWrite(); - USBFS_frequencyChanged = epNumber; - } - #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ - - /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */ - - /* `#END` */ - break; - default: - break; - } - } - else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \ - USBFS_RQST_RCPT_IFC) - { - /* Interface or Entity ID */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_SET_CUR: - #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) - { - /* `#START MUTE_SET_REQUEST` Place multi-channel handler here */ - - /* `#END` */ - - /* Entity ID Control Selector is MUTE */ - USBFS_currentTD.wCount = 1u; - USBFS_currentTD.pData = &USBFS_currentMute; - requestHandled = USBFS_InitControlWrite(); - } - else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) - { - /* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */ - - /* `#END` */ - - /* Entity ID Control Selector is VOLUME */ - USBFS_currentTD.wCount = USBFS_VOLUME_LEN; - USBFS_currentTD.pData = USBFS_currentVolume; - requestHandled = USBFS_InitControlWrite(); - } - else - { - /* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */ - - /* `#END` */ - } - #endif /* End USBFS_ENABLE_AUDIO_STREAMING */ - - /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */ - - /* `#END` */ - break; - default: - break; - } - } - else - { /* USBFS_RQST_RCPT_OTHER */ - } - } - else - { /* requestHandled is initialized as FALSE by default */ - } - - return(requestHandled); -} - - -#endif /* USER_SUPPLIED_AUDIO_HANDLER */ - - -/******************************************************************************* -* Additional user functions supporting AUDIO Requests -********************************************************************************/ - -/* `#START AUDIO_FUNCTIONS` Place any additional functions here */ - -/* `#END` */ - -#endif /* End USBFS_ENABLE_AUDIO_CLASS*/ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_audio.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_audio.h deleted file mode 100755 index 1e6186b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_audio.h +++ /dev/null @@ -1,95 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_audio.h -* Version 2.60 -* -* Description: -* Header File for the USFS component. Contains prototypes and constant values. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_USBFS_USBFS_audio_H) -#define CY_USBFS_USBFS_audio_H - -#include "cytypes.h" - - -/*************************************** -* Custom Declarations -***************************************/ - -/* `#START CUSTOM_CONSTANTS` Place your declaration here */ - -/* `#END` */ - - -/*************************************** -* Constants for USBFS_audio API. -***************************************/ - -/* Audio Class-Specific Request Codes (AUDIO Table A-9) */ -#define USBFS_REQUEST_CODE_UNDEFINED (0x00u) -#define USBFS_SET_CUR (0x01u) -#define USBFS_GET_CUR (0x81u) -#define USBFS_SET_MIN (0x02u) -#define USBFS_GET_MIN (0x82u) -#define USBFS_SET_MAX (0x03u) -#define USBFS_GET_MAX (0x83u) -#define USBFS_SET_RES (0x04u) -#define USBFS_GET_RES (0x84u) -#define USBFS_SET_MEM (0x05u) -#define USBFS_GET_MEM (0x85u) -#define USBFS_GET_STAT (0xFFu) - -/* Endpoint Control Selectors (AUDIO Table A-19) */ -#define USBFS_EP_CONTROL_UNDEFINED (0x00u) -#define USBFS_SAMPLING_FREQ_CONTROL (0x01u) -#define USBFS_PITCH_CONTROL (0x02u) - -/* Feature Unit Control Selectors (AUDIO Table A-11) */ -#define USBFS_FU_CONTROL_UNDEFINED (0x00u) -#define USBFS_MUTE_CONTROL (0x01u) -#define USBFS_VOLUME_CONTROL (0x02u) -#define USBFS_BASS_CONTROL (0x03u) -#define USBFS_MID_CONTROL (0x04u) -#define USBFS_TREBLE_CONTROL (0x05u) -#define USBFS_GRAPHIC_EQUALIZER_CONTROL (0x06u) -#define USBFS_AUTOMATIC_GAIN_CONTROL (0x07u) -#define USBFS_DELAY_CONTROL (0x08u) -#define USBFS_BASS_BOOST_CONTROL (0x09u) -#define USBFS_LOUDNESS_CONTROL (0x0Au) - -#define USBFS_SAMPLE_FREQ_LEN (3u) -#define USBFS_VOLUME_LEN (2u) - -#if !defined(USER_SUPPLIED_DEFAULT_VOLUME_VALUE) - #define USBFS_VOL_MIN_MSB (0x80u) - #define USBFS_VOL_MIN_LSB (0x01u) - #define USBFS_VOL_MAX_MSB (0x7Fu) - #define USBFS_VOL_MAX_LSB (0xFFu) - #define USBFS_VOL_RES_MSB (0x00u) - #define USBFS_VOL_RES_LSB (0x01u) -#endif /* USER_SUPPLIED_DEFAULT_VOLUME_VALUE */ - - -/*************************************** -* External data references -***************************************/ - -extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP] - [USBFS_SAMPLE_FREQ_LEN]; -extern volatile uint8 USBFS_frequencyChanged; -extern volatile uint8 USBFS_currentMute; -extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; -extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN]; -extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN]; -extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN]; - -#endif /* End CY_USBFS_USBFS_audio_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_boot.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_boot.c deleted file mode 100755 index 2843057..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_boot.c +++ /dev/null @@ -1,262 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_boot.c -* Version 2.60 -* -* Description: -* Boot loader API for USBFS Component. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" - -#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ - (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) - - -/*************************************** -* Bootloader defines -***************************************/ - -#define USBFS_CyBtLdrStarttimer(X, T) {USBFS_universalTime = T * 10; X = 0u;} -#define USBFS_CyBtLdrChecktimer(X) ((X++ < USBFS_universalTime) ? 1u : 0u) - -#define USBFS_BTLDR_OUT_EP (0x01u) -#define USBFS_BTLDR_IN_EP (0x02u) - - -/*************************************** -* Bootloader Variables -***************************************/ - -static uint16 USBFS_universalTime; -static uint8 USBFS_started = 0u; - - -/******************************************************************************* -* Function Name: USBFS_CyBtldrCommStart -******************************************************************************** -* -* Summary: -* Starts the component and enables the interrupt. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Side Effects: -* This function starts the USB with 3V or 5V operation. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_CyBtldrCommStart(void) -{ - CyGlobalIntEnable; /* Enable Global Interrupts */ - - /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */ - USBFS_Start(0u, USBFS_DWR_VDDD_OPERATION); - - /* USB component started, the correct enumeration will be checked in first Read operation */ - USBFS_started = 1u; - -} - - -/******************************************************************************* -* Function Name: USBFS_CyBtldrCommStop. -******************************************************************************** -* -* Summary: -* Disable the component and disable the interrupt. -* -* Parameters: -* None. -* -* Return: -* None. -* -*******************************************************************************/ -void USBFS_CyBtldrCommStop(void) -{ - USBFS_Stop(); -} - - -/******************************************************************************* -* Function Name: USBFS_CyBtldrCommReset. -******************************************************************************** -* -* Summary: -* Resets the receive and transmit communication Buffers. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_CyBtldrCommReset(void) -{ - USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); /* Enable the OUT endpoint */ -} - - -/******************************************************************************* -* Function Name: USBFS_CyBtldrCommWrite. -******************************************************************************** -* -* Summary: -* Allows the caller to write data to the boot loader host. The function will -* handle polling to allow a block of data to be completely sent to the host -* device. -* -* Parameters: -* pData: A pointer to the block of data to send to the device -* size: The number of bytes to write. -* count: Pointer to an unsigned short variable to write the number of -* bytes actually written. -* timeOut: Number of units to wait before returning because of a timeout. -* -* Return: -* Returns the value that best describes the problem. -* -* Reentrant: -* No. -* -*******************************************************************************/ -cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL - -{ - uint16 time; - cystatus status; - - /* Enable IN transfer */ - USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER); - - /* Start a timer to wait on. */ - USBFS_CyBtLdrStarttimer(time, timeOut); - - /* Wait for the master to read it. */ - while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \ - USBFS_CyBtLdrChecktimer(time)) - { - CyDelay(1u); /* 1ms delay */ - } - - if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) - { - status = CYRET_TIMEOUT; - } - else - { - *count = size; - status = CYRET_SUCCESS; - } - - return(status); -} - - -/******************************************************************************* -* Function Name: USBFS_CyBtldrCommRead. -******************************************************************************** -* -* Summary: -* Allows the caller to read data from the boot loader host. The function will -* handle polling to allow a block of data to be completely received from the -* host device. -* -* Parameters: -* pData: A pointer to the area to store the block of data received -* from the device. -* size: The number of bytes to read. -* count: Pointer to an unsigned short variable to write the number -* of bytes actually read. -* timeOut: Number of units to wait before returning because of a timeOut. -* Timeout is measured in 10s of ms. -* -* Return: -* Returns the value that best describes the problem. -* -* Reentrant: -* No. -* -*******************************************************************************/ -cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL - -{ - cystatus status; - uint16 time; - - if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER) - { - size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER; - } - /* Start a timer to wait on. */ - USBFS_CyBtLdrStarttimer(time, timeOut); - - /* Wait on enumeration in first time */ - if(USBFS_started) - { - /* Wait for Device to enumerate */ - while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time)) - { - CyDelay(1u); /* 1ms delay */ - } - /* Enable first OUT, if enumeration complete */ - if(USBFS_GetConfiguration()) - { - USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */ - USBFS_CyBtldrCommReset(); - USBFS_started = 0u; - } - } - else /* Check for configuration changes, has been done by Host */ - { - if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */ - { - if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */ - { - USBFS_CyBtldrCommReset(); - } - } - } - /* Wait on next packet */ - while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ - USBFS_CyBtLdrChecktimer(time)) - { - CyDelay(1u); /* 1ms delay */ - } - - /* OUT EP has completed */ - if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL) - { - *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size); - status = CYRET_SUCCESS; - } - else - { - *count = 0u; - status = CYRET_TIMEOUT; - } - return(status); -} - -#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.c deleted file mode 100755 index 82951c8..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.c +++ /dev/null @@ -1,706 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_cdc.c -* Version 2.60 -* -* Description: -* USB HID Class request handler. -* -* Note: -* -******************************************************************************** -* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" - -#if defined(USBFS_ENABLE_CDC_CLASS) - -#include "USBFS_cdc.h" -#include "USBFS_pvt.h" - - -/*************************************** -* CDC Variables -***************************************/ - -volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; -volatile uint8 USBFS_lineChanged; -volatile uint16 USBFS_lineControlBitmap; -volatile uint8 USBFS_cdc_data_in_ep; -volatile uint8 USBFS_cdc_data_out_ep; - - -/*************************************** -* Static Function Prototypes -***************************************/ -static uint16 USBFS_StrLen(const char8 string[]) ; - - -/*************************************** -* Custom Declarations -***************************************/ - -/* `#START CDC_CUSTOM_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -/******************************************************************************* -* Function Name: USBFS_DispatchCDCClassRqst -******************************************************************************** -* -* Summary: -* This routine dispatches CDC class requests. -* -* Parameters: -* None. -* -* Return: -* requestHandled -* -* Global variables: -* USBFS_lineCoding: Contains the current line coding structure. -* It is set by the Host using SET_LINE_CODING request and returned to the -* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(), -* USBFS_GetParityType(), USBFS_GetDataBits() APIs. -* USBFS_lineControlBitmap: Contains the current control signal -* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned -* to the user code by the USBFS_GetLineControl() API. -* USBFS_lineChanged: This variable is used as a flag for the -* USBFS_IsLineChanged() API, to be aware that Host has been sent request -* for changing Line Coding or Control Bitmap. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_DispatchCDCClassRqst(void) -{ - uint8 requestHandled = USBFS_FALSE; - - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - { /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_CDC_GET_LINE_CODING: - USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; - USBFS_currentTD.pData = USBFS_lineCoding; - requestHandled = USBFS_InitControlRead(); - break; - - /* `#START CDC_READ_REQUESTS` Place other request handler here */ - - /* `#END` */ - - default: /* requestHandled is initialized as FALSE by default */ - break; - } - } - else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ - USBFS_RQST_DIR_H2D) - { /* Control Write */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_CDC_SET_LINE_CODING: - USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; - USBFS_currentTD.pData = USBFS_lineCoding; - USBFS_lineChanged |= USBFS_LINE_CODING_CHANGED; - requestHandled = USBFS_InitControlWrite(); - break; - - case USBFS_CDC_SET_CONTROL_LINE_STATE: - USBFS_lineControlBitmap = CY_GET_REG8(USBFS_wValueLo); - USBFS_lineChanged |= USBFS_LINE_CONTROL_CHANGED; - requestHandled = USBFS_InitNoDataControlTransfer(); - break; - - /* `#START CDC_WRITE_REQUESTS` Place other request handler here */ - - /* `#END` */ - - default: /* requestHandled is initialized as FALSE by default */ - break; - } - } - else - { /* requestHandled is initialized as FALSE by default */ - } - - return(requestHandled); -} - - -/*************************************** -* Optional CDC APIs -***************************************/ -#if (USBFS_ENABLE_CDC_CLASS_API != 0u) - - - /******************************************************************************* - * Function Name: USBFS_CDC_Init - ******************************************************************************** - * - * Summary: - * This function initialize the CDC interface to be ready for the receive data - * from the PC. - * - * Parameters: - * None. - * - * Return: - * None. - * - * Global variables: - * USBFS_lineChanged: Initialized to zero. - * USBFS_cdc_data_out_ep: Used as an OUT endpoint number. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_CDC_Init(void) - { - USBFS_lineChanged = 0u; - USBFS_EnableOutEP(USBFS_cdc_data_out_ep); - } - - - /******************************************************************************* - * Function Name: USBFS_PutData - ******************************************************************************** - * - * Summary: - * Sends a specified number of bytes from the location specified by a - * pointer to the PC. - * - * Parameters: - * pData: pointer to the buffer containing data to be sent. - * length: Specifies the number of bytes to send from the pData - * buffer. Maximum length will be limited by the maximum packet - * size for the endpoint. - * - * Return: - * None. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending - * data. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_PutData(const uint8* pData, uint16 length) - { - /* Limits length to maximum packet size for the EP */ - if(length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) - { - /* Caution: Data will be lost if length is greater than Max Packet Length */ - length = USBFS_EP[USBFS_cdc_data_in_ep].bufferSize; - /* Halt CPU in debug mode */ - CYASSERT(0u != 0u); - } - USBFS_LoadInEP(USBFS_cdc_data_in_ep, pData, length); - } - - - /******************************************************************************* - * Function Name: USBFS_StrLen - ******************************************************************************** - * - * Summary: - * Calculates length of a null terminated string. - * - * Parameters: - * string: pointer to the string. - * - * Return: - * Length of the string - * - *******************************************************************************/ - static uint16 USBFS_StrLen(const char8 string[]) - { - uint16 len = 0u; - - while (string[len] != (char8)0) - { - len++; - } - - return (len); - } - - - /******************************************************************************* - * Function Name: USBFS_PutString - ******************************************************************************** - * - * Summary: - * Sends a null terminated string to the PC. - * - * Parameters: - * string: pointer to the string to be sent to the PC - * - * Return: - * None. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending - * data. - * - * Reentrant: - * No. - * - * Theory: - * This function will block if there is not enough memory to place the whole - * string, it will block until the entire string has been written to the - * transmit buffer. - * - *******************************************************************************/ - void USBFS_PutString(const char8 string[]) - { - uint16 str_length; - uint16 send_length; - uint16 buf_index = 0u; - - /* Get length of the null terminated string */ - str_length = USBFS_StrLen(string); - do - { - /* Limits length to maximum packet size for the EP */ - send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ? - USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length; - /* Enable IN transfer */ - USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length); - str_length -= send_length; - - /* If more data are present to send */ - if(str_length > 0u) - { - buf_index += send_length; - /* Wait for the Host to read it. */ - while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState == - USBFS_IN_BUFFER_FULL) - { - ; - } - } - }while(str_length > 0u); - } - - - /******************************************************************************* - * Function Name: USBFS_PutChar - ******************************************************************************** - * - * Summary: - * Writes a single character to the PC. - * - * Parameters: - * txDataByte: Character to be sent to the PC. - * - * Return: - * None. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending - * data. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_PutChar(char8 txDataByte) - { - uint8 dataByte; - dataByte = (uint8)txDataByte; - - USBFS_LoadInEP(USBFS_cdc_data_in_ep, &dataByte, 1u); - } - - - /******************************************************************************* - * Function Name: USBFS_PutCRLF - ******************************************************************************** - * - * Summary: - * Sends a carriage return (0x0D) and line feed (0x0A) to the PC - * - * Parameters: - * None. - * - * Return: - * None. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending - * data. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_PutCRLF(void) - { - const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; - - USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)txData, 2u); - } - - - /******************************************************************************* - * Function Name: USBFS_GetCount - ******************************************************************************** - * - * Summary: - * This function returns the number of bytes that were received from the PC. - * - * Parameters: - * None. - * - * Return: - * Returns the number of received bytes. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - *******************************************************************************/ - uint16 USBFS_GetCount(void) - { - uint16 bytesCount = 0u; - - if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL) - { - bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep); - } - - return(bytesCount); - } - - - /******************************************************************************* - * Function Name: USBFS_DataIsReady - ******************************************************************************** - * - * Summary: - * Returns a nonzero value if the component received data or received - * zero-length packet. The GetAll() or GetData() API should be called to read - * data from the buffer and re-init OUT endpoint even when zero-length packet - * received. - * - * Parameters: - * None. - * - * Return: - * If the OUT packet received this function returns a nonzero value. - * Otherwise zero is returned. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - *******************************************************************************/ - uint8 USBFS_DataIsReady(void) - { - return(USBFS_EP[USBFS_cdc_data_out_ep].apiEpState); - } - - - /******************************************************************************* - * Function Name: USBFS_CDCIsReady - ******************************************************************************** - * - * Summary: - * Returns a nonzero value if the component is ready to send more data to the - * PC. Otherwise returns zero. Should be called before sending new data to - * ensure the previous data has finished sending.This function returns the - * number of bytes that were received from the PC. - * - * Parameters: - * None. - * - * Return: - * If the buffer can accept new data then this function returns a nonzero value. - * Otherwise zero is returned. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used. - * - *******************************************************************************/ - uint8 USBFS_CDCIsReady(void) - { - return(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState); - } - - - /******************************************************************************* - * Function Name: USBFS_GetData - ******************************************************************************** - * - * Summary: - * Gets a specified number of bytes from the input buffer and places it in a - * data array specified by the passed pointer. - * USBFS_DataIsReady() API should be called before, to be sure - * that data is received from the Host. - * - * Parameters: - * pData: Pointer to the data array where data will be placed. - * Length: Number of bytes to read into the data array from the RX buffer. - * Maximum length is limited by the the number of received bytes. - * - * Return: - * Number of bytes received. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - * Reentrant: - * No. - * - *******************************************************************************/ - uint16 USBFS_GetData(uint8* pData, uint16 length) - { - return(USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, length)); - } - - - /******************************************************************************* - * Function Name: USBFS_GetAll - ******************************************************************************** - * - * Summary: - * Gets all bytes of received data from the input buffer and places it into a - * specified data array. USBFS_DataIsReady() API should be called - * before, to be sure that data is received from the Host. - * - * Parameters: - * pData: Pointer to the data array where data will be placed. - * - * Return: - * Number of bytes received. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * USBFS_EP[].bufferSize: EP max packet size is used as a length - * to read all data from the EP buffer. - * - * Reentrant: - * No. - * - *******************************************************************************/ - uint16 USBFS_GetAll(uint8* pData) - { - return (USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, - USBFS_EP[USBFS_cdc_data_out_ep].bufferSize)); - } - - - /******************************************************************************* - * Function Name: USBFS_GetChar - ******************************************************************************** - * - * Summary: - * Reads one byte of received data from the buffer. - * - * Parameters: - * None. - * - * Return: - * Received one character. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - * Reentrant: - * No. - * - *******************************************************************************/ - uint8 USBFS_GetChar(void) - { - uint8 rxData; - - (void) USBFS_ReadOutEP(USBFS_cdc_data_out_ep, &rxData, 1u); - - return(rxData); - } - - /******************************************************************************* - * Function Name: USBFS_IsLineChanged - ******************************************************************************** - * - * Summary: - * This function returns clear on read status of the line. - * - * Parameters: - * None. - * - * Return: - * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not - * zero value returned. Otherwise zero is returned. - * - * Global variables: - * USBFS_transferState - it is checked to be sure then OUT data - * phase has been complete, and data written to the lineCoding or Control - * Bitmap buffer. - * USBFS_lineChanged: used as a flag to be aware that Host has been - * sent request for changing Line Coding or Control Bitmap. - * - *******************************************************************************/ - uint8 USBFS_IsLineChanged(void) - { - uint8 state = 0u; - - /* transferState is checked to be sure then OUT data phase has been complete */ - if(USBFS_transferState == USBFS_TRANS_STATE_IDLE) - { - if(USBFS_lineChanged != 0u) - { - state = USBFS_lineChanged; - USBFS_lineChanged = 0u; - } - } - - return(state); - } - - - /******************************************************************************* - * Function Name: USBFS_GetDTERate - ******************************************************************************** - * - * Summary: - * Returns the data terminal rate set for this port in bits per second. - * - * Parameters: - * None. - * - * Return: - * Returns a uint32 value of the data rate in bits per second. - * - * Global variables: - * USBFS_lineCoding: First four bytes converted to uint32 - * depend on compiler, and returned as a data rate. - * - *******************************************************************************/ - uint32 USBFS_GetDTERate(void) - { - uint32 rate; - - rate = USBFS_lineCoding[USBFS_LINE_CODING_RATE + 3u]; - rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 2u]; - rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 1u]; - rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE]; - - return(rate); - } - - - /******************************************************************************* - * Function Name: USBFS_GetCharFormat - ******************************************************************************** - * - * Summary: - * Returns the number of stop bits. - * - * Parameters: - * None. - * - * Return: - * Returns the number of stop bits. - * - * Global variables: - * USBFS_lineCoding: used to get a parameter. - * - *******************************************************************************/ - uint8 USBFS_GetCharFormat(void) - { - return(USBFS_lineCoding[USBFS_LINE_CODING_STOP_BITS]); - } - - - /******************************************************************************* - * Function Name: USBFS_GetParityType - ******************************************************************************** - * - * Summary: - * Returns the parity type for the CDC port. - * - * Parameters: - * None. - * - * Return: - * Returns the parity type. - * - * Global variables: - * USBFS_lineCoding: used to get a parameter. - * - *******************************************************************************/ - uint8 USBFS_GetParityType(void) - { - return(USBFS_lineCoding[USBFS_LINE_CODING_PARITY]); - } - - - /******************************************************************************* - * Function Name: USBFS_GetDataBits - ******************************************************************************** - * - * Summary: - * Returns the number of data bits for the CDC port. - * - * Parameters: - * None. - * - * Return: - * Returns the number of data bits. - * The number of data bits can be 5, 6, 7, 8 or 16. - * - * Global variables: - * USBFS_lineCoding: used to get a parameter. - * - *******************************************************************************/ - uint8 USBFS_GetDataBits(void) - { - return(USBFS_lineCoding[USBFS_LINE_CODING_DATA_BITS]); - } - - - /******************************************************************************* - * Function Name: USBFS_GetLineControl - ******************************************************************************** - * - * Summary: - * Returns Line control bitmap. - * - * Parameters: - * None. - * - * Return: - * Returns Line control bitmap. - * - * Global variables: - * USBFS_lineControlBitmap: used to get a parameter. - * - *******************************************************************************/ - uint16 USBFS_GetLineControl(void) - { - return(USBFS_lineControlBitmap); - } - -#endif /* End USBFS_ENABLE_CDC_CLASS_API*/ - - -/******************************************************************************* -* Additional user functions supporting CDC Requests -********************************************************************************/ - -/* `#START CDC_FUNCTIONS` Place any additional functions here */ - -/* `#END` */ - -#endif /* End USBFS_ENABLE_CDC_CLASS*/ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.h deleted file mode 100755 index 334bc58..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.h +++ /dev/null @@ -1,92 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_cdc.h -* Version 2.60 -* -* Description: -* Header File for the USFS component. -* Contains CDC class prototypes and constant values. -* -******************************************************************************** -* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_USBFS_USBFS_cdc_H) -#define CY_USBFS_USBFS_cdc_H - -#include "cytypes.h" - - -/*************************************** -* Prototypes of the USBFS_cdc API. -***************************************/ - -#if (USBFS_ENABLE_CDC_CLASS_API != 0u) - void USBFS_CDC_Init(void) ; - void USBFS_PutData(const uint8* pData, uint16 length) ; - void USBFS_PutString(const char8 string[]) ; - void USBFS_PutChar(char8 txDataByte) ; - void USBFS_PutCRLF(void) ; - uint16 USBFS_GetCount(void) ; - uint8 USBFS_CDCIsReady(void) ; - uint8 USBFS_DataIsReady(void) ; - uint16 USBFS_GetData(uint8* pData, uint16 length) ; - uint16 USBFS_GetAll(uint8* pData) ; - uint8 USBFS_GetChar(void) ; - uint8 USBFS_IsLineChanged(void) ; - uint32 USBFS_GetDTERate(void) ; - uint8 USBFS_GetCharFormat(void) ; - uint8 USBFS_GetParityType(void) ; - uint8 USBFS_GetDataBits(void) ; - uint16 USBFS_GetLineControl(void) ; -#endif /* End USBFS_ENABLE_CDC_CLASS_API*/ - - -/*************************************** -* Constants for USBFS_cdc API. -***************************************/ - -/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */ -#define USBFS_CDC_SET_LINE_CODING (0x20u) -#define USBFS_CDC_GET_LINE_CODING (0x21u) -#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u) - -#define USBFS_LINE_CODING_CHANGED (0x01u) -#define USBFS_LINE_CONTROL_CHANGED (0x02u) - -#define USBFS_1_STOPBIT (0x00u) -#define USBFS_1_5_STOPBITS (0x01u) -#define USBFS_2_STOPBITS (0x02u) - -#define USBFS_PARITY_NONE (0x00u) -#define USBFS_PARITY_ODD (0x01u) -#define USBFS_PARITY_EVEN (0x02u) -#define USBFS_PARITY_MARK (0x03u) -#define USBFS_PARITY_SPACE (0x04u) - -#define USBFS_LINE_CODING_SIZE (0x07u) -#define USBFS_LINE_CODING_RATE (0x00u) -#define USBFS_LINE_CODING_STOP_BITS (0x04u) -#define USBFS_LINE_CODING_PARITY (0x05u) -#define USBFS_LINE_CODING_DATA_BITS (0x06u) - -#define USBFS_LINE_CONTROL_DTR (0x01u) -#define USBFS_LINE_CONTROL_RTS (0x02u) - - -/*************************************** -* External data references -***************************************/ - -extern volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; -extern volatile uint8 USBFS_lineChanged; -extern volatile uint16 USBFS_lineControlBitmap; -extern volatile uint8 USBFS_cdc_data_in_ep; -extern volatile uint8 USBFS_cdc_data_out_ep; - -#endif /* End CY_USBFS_USBFS_cdc_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.inf b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.inf deleted file mode 100755 index c3477c2..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cdc.inf +++ /dev/null @@ -1,122 +0,0 @@ -;****************************************************************************** -; File Name: USBFS_cdc.inf -; Version 2.60 -; -; Description: -; Windows USB CDC setup file for USBUART Device. -; -;****************************************************************************** -; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying -; the software package with which this file was provided. -;****************************************************************************** - -[Version] -Signature="$Windows NT$" -Class=Ports -ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} -Provider=%PROVIDER% -LayoutFile=layout.inf -DriverVer=03/05/2007,2.0.0000.0 - -[Manufacturer] -%MFGNAME%=DeviceList, NTx86, NTia64, NTamd64 - -[DestinationDirs] -DefaultDestDir=12 - -[SourceDisksFiles] - -[SourceDisksNames] - -[DeviceList.NTx86] -%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 - -[DeviceList.NTia64] -%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 - -[DeviceList.NTamd64] -%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 - - -;------------------------------------------------------------------------------ -; 32 bit section for Windows 2000/2003/XP/Vista -;------------------------------------------------------------------------------ - -[DriverInstall.NTx86] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles -AddReg=DriverInstall.NTx86.AddReg - -[DriverCopyFiles] -usbser.sys,,,0x20 - -[DriverInstall.NTx86.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[DriverInstall.NTx86.Services] -AddService=usbser, 0x00000002, DriverService - -;------------------------------------------------------------------------------ -; 64 bit section for Intel Itanium based systems -;------------------------------------------------------------------------------ - -[DriverInstall.NTia64] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles -AddReg=DriverInstall.NTia64.AddReg - -[DriverCopyFiles] -usbser.sys,,,0x20 - -[DriverInstall.NTia64.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[DriverInstall.NTia64.Services] -AddService=usbser, 0x00000002, DriverService - -;------------------------------------------------------------------------------ -; 64 bit section for AMD64 and Intel EM64T based systems -;------------------------------------------------------------------------------ - -[DriverInstall.NTamd64] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles -AddReg=DriverInstall.NTamd64.AddReg - -[DriverCopyFiles] -usbser.sys,,,0x20 - -[DriverInstall.NTamd64.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[DriverInstall.NTamd64.Services] -AddService=usbser, 0x00000002, DriverService - -;------------------------------------------------------------------------------ -; -;------------------------------------------------------------------------------ - -[DriverService] -DisplayName=%SERVICE% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\usbser.sys - -;------------------------------------------------------------------------------ -; String Definitions -;------------------------------------------------------------------------------ - -[Strings] -PROVIDER="Cypress" -MFGNAME="Cypress Semiconductor Corporation" -DESCRIPTION="Cypress USB UART" -SERVICE="USB UART" diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cls.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cls.c deleted file mode 100755 index 7bbd8d1..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_cls.c +++ /dev/null @@ -1,107 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_cls.c -* Version 2.60 -* -* Description: -* USB Class request handler. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" - -#if(USBFS_EXTERN_CLS == USBFS_FALSE) - -#include "USBFS_pvt.h" - - -/*************************************** -* User Implemented Class Driver Declarations. -***************************************/ -/* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -/******************************************************************************* -* Function Name: USBFS_DispatchClassRqst -******************************************************************************** -* Summary: -* This routine dispatches class specific requests depend on interface class. -* -* Parameters: -* None. -* -* Return: -* requestHandled. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_DispatchClassRqst(void) -{ - uint8 requestHandled = USBFS_FALSE; - uint8 interfaceNumber = 0u; - - switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - { - case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */ - interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */ - break; - case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */ - /* Find related interface to the endpoint, wIndexLo contain EP number */ - interfaceNumber = - USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface; - break; - default: /* RequestHandled is initialized as FALSE by default */ - break; - } - /* Handle Class request depend on interface type */ - switch(USBFS_interfaceClass[interfaceNumber]) - { - case USBFS_CLASS_HID: - #if defined(USBFS_ENABLE_HID_CLASS) - requestHandled = USBFS_DispatchHIDClassRqst(); - #endif /* USBFS_ENABLE_HID_CLASS */ - break; - case USBFS_CLASS_AUDIO: - #if defined(USBFS_ENABLE_AUDIO_CLASS) - requestHandled = USBFS_DispatchAUDIOClassRqst(); - #endif /* USBFS_ENABLE_HID_CLASS */ - break; - case USBFS_CLASS_CDC: - #if defined(USBFS_ENABLE_CDC_CLASS) - requestHandled = USBFS_DispatchCDCClassRqst(); - #endif /* USBFS_ENABLE_CDC_CLASS */ - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - - /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ - - /* `#END` */ - - return(requestHandled); -} - - -/******************************************************************************* -* Additional user functions supporting Class Specific Requests -********************************************************************************/ - -/* `#START CLASS_SPECIFIC_FUNCTIONS` Place any additional functions here */ - -/* `#END` */ - -#endif /* USBFS_EXTERN_CLS */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_descr.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_descr.c deleted file mode 100755 index da14446..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_descr.c +++ /dev/null @@ -1,323 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_descr.c -* Version 2.60 -* -* Description: -* USB descriptors and storage. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" -#include "USBFS_pvt.h" - - -/***************************************************************************** -* User supplied descriptors. If you want to specify your own descriptors, -* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and -* add your descriptors. -*****************************************************************************/ -/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -/*************************************** -* USB Customizer Generated Descriptors -***************************************/ - -#if !defined(USER_SUPPLIED_DESCRIPTORS) -/********************************************************************* -* Device Descriptors -*********************************************************************/ -const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = { -/* Descriptor Length */ 0x12u, -/* DescriptorType: DEVICE */ 0x01u, -/* bcdUSB (ver 2.0) */ 0x00u, 0x02u, -/* bDeviceClass */ 0x00u, -/* bDeviceSubClass */ 0x00u, -/* bDeviceProtocol */ 0x00u, -/* bMaxPacketSize0 */ 0x08u, -/* idVendor */ 0xB4u, 0x04u, -/* idProduct */ 0x1Du, 0xB7u, -/* bcdDevice */ 0x01u, 0x30u, -/* iManufacturer */ 0x01u, -/* iProduct */ 0x02u, -/* iSerialNumber */ 0x80u, -/* bNumConfigurations */ 0x01u -}; -/********************************************************************* -* Config Descriptor -*********************************************************************/ -const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = { -/* Config Descriptor Length */ 0x09u, -/* DescriptorType: CONFIG */ 0x02u, -/* wTotalLength */ 0x29u, 0x00u, -/* bNumInterfaces */ 0x01u, -/* bConfigurationValue */ 0x01u, -/* iConfiguration */ 0x00u, -/* bmAttributes */ 0x80u, -/* bMaxPower */ 0x00u, -/********************************************************************* -* Interface Descriptor -*********************************************************************/ -/* Interface Descriptor Length */ 0x09u, -/* DescriptorType: INTERFACE */ 0x04u, -/* bInterfaceNumber */ 0x00u, -/* bAlternateSetting */ 0x00u, -/* bNumEndpoints */ 0x02u, -/* bInterfaceClass */ 0x03u, -/* bInterfaceSubClass */ 0x00u, -/* bInterfaceProtocol */ 0x00u, -/* iInterface */ 0x02u, -/********************************************************************* -* HID Class Descriptor -*********************************************************************/ -/* HID Class Descriptor Length */ 0x09u, -/* DescriptorType: HID_CLASS */ 0x21u, -/* bcdHID */ 0x11u, 0x01u, -/* bCountryCode */ 0x00u, -/* bNumDescriptors */ 0x01u, -/* bDescriptorType */ 0x22u, -/* wDescriptorLength (LSB) */ USBFS_HID_RPT_1_SIZE_LSB, -/* wDescriptorLength (MSB) */ USBFS_HID_RPT_1_SIZE_MSB, -/********************************************************************* -* Endpoint Descriptor -*********************************************************************/ -/* Endpoint Descriptor Length */ 0x07u, -/* DescriptorType: ENDPOINT */ 0x05u, -/* bEndpointAddress */ 0x01u, -/* bmAttributes */ 0x03u, -/* wMaxPacketSize */ 0x40u, 0x00u, -/* bInterval */ 0x01u, -/********************************************************************* -* Endpoint Descriptor -*********************************************************************/ -/* Endpoint Descriptor Length */ 0x07u, -/* DescriptorType: ENDPOINT */ 0x05u, -/* bEndpointAddress */ 0x82u, -/* bmAttributes */ 0x03u, -/* wMaxPacketSize */ 0x40u, 0x00u, -/* bInterval */ 0x01u -}; - -/********************************************************************* -* String Descriptor Table -*********************************************************************/ -const uint8 CYCODE USBFS_STRING_DESCRIPTORS[83u] = { -/********************************************************************* -* Language ID Descriptor -*********************************************************************/ -/* Descriptor Length */ 0x04u, -/* DescriptorType: STRING */ 0x03u, -/* Language Id */ 0x09u, 0x04u, -/********************************************************************* -* String Descriptor: "Cypress Semiconductor" -*********************************************************************/ -/* Descriptor Length */ 0x2Cu, -/* DescriptorType: STRING */ 0x03u, - (uint8)'C', 0u,(uint8)'y', 0u,(uint8)'p', 0u,(uint8)'r', 0u,(uint8)'e', 0u, - (uint8)'s', 0u,(uint8)'s', 0u,(uint8)' ', 0u,(uint8)'S', 0u,(uint8)'e', 0u, - (uint8)'m', 0u,(uint8)'i', 0u,(uint8)'c', 0u,(uint8)'o', 0u,(uint8)'n', 0u, - (uint8)'d', 0u,(uint8)'u', 0u,(uint8)'c', 0u,(uint8)'t', 0u,(uint8)'o', 0u, - (uint8)'r', 0u, -/********************************************************************* -* String Descriptor: "PSoC3 Bootloader" -*********************************************************************/ -/* Descriptor Length */ 0x22u, -/* DescriptorType: STRING */ 0x03u, - (uint8)'P', 0u,(uint8)'S', 0u,(uint8)'o', 0u,(uint8)'C', 0u,(uint8)'3', 0u, - (uint8)' ', 0u,(uint8)'B', 0u,(uint8)'o', 0u,(uint8)'o', 0u,(uint8)'t', 0u, - (uint8)'l', 0u,(uint8)'o', 0u,(uint8)'a', 0u,(uint8)'d', 0u,(uint8)'e', 0u, - (uint8)'r', 0u, -/*********************************************************************/ -/* Marks the end of the list. */ 0x00u}; -/*********************************************************************/ - -/********************************************************************* -* Serial Number String Descriptor -*********************************************************************/ -const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10] = { -/* Descriptor Length */ 0x0Au, -/* DescriptorType: STRING */ 0x03u, -(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'1', 0u -}; - -/********************************************************************* -* HID Report Descriptor: Generic HID -*********************************************************************/ -const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u] = { -/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_1_SIZE_LSB, -USBFS_HID_RPT_1_SIZE_MSB, -/* USAGE_PAGE */ 0x05u, 0x01u, -/* USAGE */ 0x09u, 0x00u, -/* COLLECTION */ 0xA1u, 0x00u, -/* USAGE */ 0x09u, 0x00u, -/* COLLECTION */ 0xA1u, 0x00u, -/* USAGE */ 0x09u, 0x00u, -/* LOGICAL_MINIMUM */ 0x15u, 0x00u, -/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, -/* REPORT_SIZE */ 0x75u, 0x08u, -/* REPORT_COUNT */ 0x95u, 0x40u, -/* OUTPUT */ 0x91u, 0x02u, -/* USAGE */ 0x09u, 0x00u, -/* LOGICAL_MINIMUM */ 0x15u, 0x00u, -/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, -/* REPORT_SIZE */ 0x75u, 0x08u, -/* REPORT_COUNT */ 0x95u, 0x40u, -/* INPUT */ 0x81u, 0x02u, -/* END_COLLECTION */ 0xC0u, -/* END_COLLECTION */ 0xC0u, -/*********************************************************************/ -/* End of the HID Report Descriptor */ 0x00u, 0x00u}; -/*********************************************************************/ - -#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE) -/********************************************************************* -* HID Input Report Storage -*********************************************************************/ -T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; -uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ - USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; - -/********************************************************************* -* HID Input Report TD Table -*********************************************************************/ -const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u] = { - {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE, - &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[0u], - &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB}, -}; -/********************************************************************* -* HID Output Report Storage -*********************************************************************/ -T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; -uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ - USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; - -/********************************************************************* -* HID Output Report TD Table -*********************************************************************/ -const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = { - {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE, - &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[0u], - &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB}, -}; -/********************************************************************* -* HID Report Look Up Table This table has four entries: -* IN Report Table -* OUT Report Table -* Feature Report Table -* HID Report Descriptor -* HID Class Descriptor -*********************************************************************/ -const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u] = { - {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE}, - {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE}, - {0x00u, NULL}, - {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR1[0]}, - {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[18]} -}; -#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE */ - -/********************************************************************* -* Interface Dispatch Table -- Points to the Class Dispatch Tables -*********************************************************************/ -const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u] = { - {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT, - &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE} -}; -/********************************************************************* -* Endpoint Setting Table -- This table contain the endpoint setting -* for each endpoint in the configuration. It -* contains the necessary information to -* configure the endpoint hardware for each -* interface and alternate setting. -*********************************************************************/ -const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u] = { -/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/ -{0x00u, 0x00u, 0x01u, 0x03u, 0x0040u, 0x03u}, -{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u} -}; -const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = { -0x03u -}; -/********************************************************************* -* Config Dispatch Table -- Points to the Config Descriptor and each of -* and endpoint setup table and to each -* interface table if it specifies a USB Class -*********************************************************************/ -const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u] = { - {0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR}, - {0x02u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE}, - {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE}, - {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS} -}; -/********************************************************************* -* Device Dispatch Table -- Points to the Device Descriptor and each of -* and Configuration Tables for this Device -*********************************************************************/ -const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u] = { - {0x01u, &USBFS_DEVICE0_DESCR}, - {0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE} -}; -/********************************************************************* -* Device Table -- Indexed by the device number. -*********************************************************************/ -const T_USBFS_LUT CYCODE USBFS_TABLE[1u] = { - {0x01u, &USBFS_DEVICE0_TABLE} -}; - -#endif /* USER_SUPPLIED_DESCRIPTORS */ - -#if defined(USBFS_ENABLE_MSOS_STRING) - - /****************************************************************************** - * USB Microsoft OS String Descriptor - * "MSFT" identifies a Microsoft host - * "100" specifies version 1.00 - * USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR becomes the bRequest value - * in a host vendor device/class request - ******************************************************************************/ - - const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH] = { - /* Descriptor Length */ 0x12u, - /* DescriptorType: STRING */ 0x03u, - /* qwSignature - "MSFT100" */ (uint8)'M', 0u, (uint8)'S', 0u, (uint8)'F', 0u, (uint8)'T', 0u, - (uint8)'1', 0u, (uint8)'0', 0u, (uint8)'0', 0u, - /* bMS_VendorCode: */ USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR, - /* bPad */ 0x00u - }; - - /* Extended Configuration Descriptor */ - - const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH] = { - /* Length of the descriptor 4 bytes */ 0x28u, 0x00u, 0x00u, 0x00u, - /* Version of the descriptor 2 bytes */ 0x00u, 0x01u, - /* wIndex - Fixed:INDEX_CONFIG_DESCRIPTOR */ 0x04u, 0x00u, - /* bCount - Count of device functions. */ 0x01u, - /* Reserved : 7 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - /* bFirstInterfaceNumber */ 0x00u, - /* Reserved */ 0x01u, - /* compatibleID - "CYUSB\0\0" */ (uint8)'C', (uint8)'Y', (uint8)'U', (uint8)'S', (uint8)'B', - 0x00u, 0x00u, 0x00u, - /* subcompatibleID - "00001\0\0" */ (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'1', - 0x00u, 0x00u, 0x00u, - /* Reserved : 6 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u - }; - -#endif /* USBFS_ENABLE_MSOS_STRING */ - -/* DIE ID string descriptor for 8 bytes ID */ -#if defined(USBFS_ENABLE_IDSN_STRING) - uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; -#endif /* USBFS_ENABLE_IDSN_STRING */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_drv.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_drv.c deleted file mode 100755 index e78a41b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_drv.c +++ /dev/null @@ -1,781 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_drv.c -* Version 2.60 -* -* Description: -* Endpoint 0 Driver for the USBFS Component. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" -#include "USBFS_pvt.h" - - -/*************************************** -* Global data allocation -***************************************/ - -volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; -volatile uint8 USBFS_configuration; -volatile uint8 USBFS_interfaceNumber; -volatile uint8 USBFS_configurationChanged; -volatile uint8 USBFS_deviceAddress; -volatile uint8 USBFS_deviceStatus; -volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; -volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; -volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; -volatile uint8 USBFS_device; -const uint8 CYCODE *USBFS_interfaceClass; - - -/*************************************** -* Local data allocation -***************************************/ - -volatile uint8 USBFS_ep0Toggle; -volatile uint8 USBFS_lastPacketSize; -volatile uint8 USBFS_transferState; -volatile T_USBFS_TD USBFS_currentTD; -volatile uint8 USBFS_ep0Mode; -volatile uint8 USBFS_ep0Count; -volatile uint16 USBFS_transferByteCount; - - -/******************************************************************************* -* Function Name: USBFS_ep_0_Interrupt -******************************************************************************** -* -* Summary: -* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. -* It dispatches setup requests and handles the data and status stages. -* -* Parameters: -* None. -* -* Return: -* None. -* -*******************************************************************************/ -CY_ISR(USBFS_EP_0_ISR) -{ - uint8 bRegTemp; - uint8 modifyReg; - - - bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); - if ((bRegTemp & USBFS_MODE_ACKD) != 0u) - { - modifyReg = 1u; - if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u) - { - if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) - { - modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */ - } - else - { - USBFS_HandleSetup(); - if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) - { - modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */ - } - - } - } - else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u) - { - USBFS_HandleIN(); - } - else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u) - { - USBFS_HandleOUT(); - } - else - { - modifyReg = 0u; - } - if(modifyReg != 0u) - { - bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */ - { - /* Update the count register */ - bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count; - CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp); - if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was successful */ - { - do - { - modifyReg = USBFS_ep0Mode; /* Init temporary variable */ - /* Unlock registers */ - bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; - if(bRegTemp == 0u) /* Check if SETUP bit is not set */ - { - /* Set the Mode Register */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode); - /* Writing check */ - modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK; - } - }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */ - } - } - } - } -} - - -/******************************************************************************* -* Function Name: USBFS_HandleSetup -******************************************************************************** -* -* Summary: -* This Routine dispatches requests for the four USB request types -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_HandleSetup(void) -{ - uint8 requestHandled; - - requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */ - requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */ - if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) - { - USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */ - } - else - { - /* In case the previous transfer did not complete, close it out */ - USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); - - switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK) - { - case USBFS_RQST_TYPE_STD: - requestHandled = USBFS_HandleStandardRqst(); - break; - case USBFS_RQST_TYPE_CLS: - requestHandled = USBFS_DispatchClassRqst(); - break; - case USBFS_RQST_TYPE_VND: - requestHandled = USBFS_HandleVendorRqst(); - break; - default: - requestHandled = USBFS_FALSE; - break; - } - if (requestHandled == USBFS_FALSE) - { - USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - } - } -} - - -/******************************************************************************* -* Function Name: USBFS_HandleIN -******************************************************************************** -* -* Summary: -* This routine handles EP0 IN transfers. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_HandleIN(void) -{ - switch (USBFS_transferState) - { - case USBFS_TRANS_STATE_IDLE: - break; - case USBFS_TRANS_STATE_CONTROL_READ: - USBFS_ControlReadDataStage(); - break; - case USBFS_TRANS_STATE_CONTROL_WRITE: - USBFS_ControlWriteStatusStage(); - break; - case USBFS_TRANS_STATE_NO_DATA_CONTROL: - USBFS_NoDataControlStatusStage(); - break; - default: /* there are no more states */ - break; - } -} - - -/******************************************************************************* -* Function Name: USBFS_HandleOUT -******************************************************************************** -* -* Summary: -* This routine handles EP0 OUT transfers. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_HandleOUT(void) -{ - switch (USBFS_transferState) - { - case USBFS_TRANS_STATE_IDLE: - break; - case USBFS_TRANS_STATE_CONTROL_READ: - USBFS_ControlReadStatusStage(); - break; - case USBFS_TRANS_STATE_CONTROL_WRITE: - USBFS_ControlWriteDataStage(); - break; - case USBFS_TRANS_STATE_NO_DATA_CONTROL: - /* Update the completion block */ - USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); - /* We expect no more data, so stall INs and OUTs */ - USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; - break; - default: /* There are no more states */ - break; - } -} - - -/******************************************************************************* -* Function Name: USBFS_LoadEP0 -******************************************************************************** -* -* Summary: -* This routine loads the EP0 data registers for OUT transfers. It uses the -* currentTD (previously initialized by the _InitControlWrite function and -* updated for each OUT transfer, and the bLastPacketSize) to determine how -* many uint8s to transfer on the current OUT. -* -* If the number of uint8s remaining is zero and the last transfer was full, -* we need to send a zero length packet. Otherwise we send the minimum -* of the control endpoint size (8) or remaining number of uint8s for the -* transaction. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_transferByteCount - Update the transfer byte count from the -* last transaction. -* USBFS_ep0Count - counts the data loaded to the SIE memory in -* current packet. -* USBFS_lastPacketSize - remembers the USBFS_ep0Count value for the -* next packet. -* USBFS_transferByteCount - sum of the previous bytes transferred -* on previous packets(sum of USBFS_lastPacketSize) -* USBFS_ep0Toggle - inverted -* USBFS_ep0Mode - prepare for mode register content. -* USBFS_transferState - set to TRANS_STATE_CONTROL_READ -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_LoadEP0(void) -{ - uint8 ep0Count = 0u; - - /* Update the transfer byte count from the last transaction */ - USBFS_transferByteCount += USBFS_lastPacketSize; - /* Now load the next transaction */ - while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) - { - CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData); - USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; - ep0Count++; - USBFS_currentTD.count--; - } - /* Support zero-length packet*/ - if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) ) - { - /* Update the data toggle */ - USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; - /* Set the Mode Register */ - USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; - /* Update the state (or stay the same) */ - USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - } - else - { - /* Expect Status Stage Out */ - USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; - /* Update the state (or stay the same) */ - USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - } - - /* Save the packet size for next time */ - USBFS_lastPacketSize = ep0Count; - USBFS_ep0Count = ep0Count; -} - - -/******************************************************************************* -* Function Name: USBFS_InitControlRead -******************************************************************************** -* -* Summary: -* Initialize a control read transaction, usable to send data to the host. -* The following global variables should be initialized before this function -* called. To send zero length packet use InitZeroLengthControlTransfer -* function. -* -* Parameters: -* None. -* -* Return: -* requestHandled state. -* -* Global variables: -* USBFS_currentTD.count - counts of data to be sent. -* USBFS_currentTD.pData - data pointer. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_InitControlRead(void) -{ - uint16 xferCount; - if(USBFS_currentTD.count == 0u) - { - (void) USBFS_InitZeroLengthControlTransfer(); - } - else - { - /* Set up the state machine */ - USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - /* Set the toggle, it gets updated in LoadEP */ - USBFS_ep0Toggle = 0u; - /* Initialize the Status Block */ - USBFS_InitializeStatusBlock(); - xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - - if (USBFS_currentTD.count > xferCount) - { - USBFS_currentTD.count = xferCount; - } - USBFS_LoadEP0(); - } - - return(USBFS_TRUE); -} - - -/******************************************************************************* -* Function Name: USBFS_InitZeroLengthControlTransfer -******************************************************************************** -* -* Summary: -* Initialize a zero length data IN transfer. -* -* Parameters: -* None. -* -* Return: -* requestHandled state. -* -* Global variables: -* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE -* USBFS_ep0Mode - prepare for mode register content. -* USBFS_transferState - set to TRANS_STATE_CONTROL_READ -* USBFS_ep0Count - cleared, means the zero-length packet. -* USBFS_lastPacketSize - cleared. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_InitZeroLengthControlTransfer(void) - -{ - /* Update the state */ - USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; - /* Set the data toggle */ - USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - /* Set the Mode Register */ - USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; - /* Save the packet size for next time */ - USBFS_lastPacketSize = 0u; - USBFS_ep0Count = 0u; - - return(USBFS_TRUE); -} - - -/******************************************************************************* -* Function Name: USBFS_ControlReadDataStage -******************************************************************************** -* -* Summary: -* Handle the Data Stage of a control read transfer. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_ControlReadDataStage(void) - -{ - USBFS_LoadEP0(); -} - - -/******************************************************************************* -* Function Name: USBFS_ControlReadStatusStage -******************************************************************************** -* -* Summary: -* Handle the Status Stage of a control read transfer. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_USBFS_transferByteCount - updated with last packet size. -* USBFS_transferState - set to TRANS_STATE_IDLE. -* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_ControlReadStatusStage(void) -{ - /* Update the transfer byte count */ - USBFS_transferByteCount += USBFS_lastPacketSize; - /* Go Idle */ - USBFS_transferState = USBFS_TRANS_STATE_IDLE; - /* Update the completion block */ - USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - /* We expect no more data, so stall INs and OUTs */ - USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; -} - - -/******************************************************************************* -* Function Name: USBFS_InitControlWrite -******************************************************************************** -* -* Summary: -* Initialize a control write transaction -* -* Parameters: -* None. -* -* Return: -* requestHandled state. -* -* Global variables: -* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE -* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE -* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_InitControlWrite(void) -{ - uint16 xferCount; - - /* Set up the state machine */ - USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; - /* This might not be necessary */ - USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - /* Initialize the Status Block */ - USBFS_InitializeStatusBlock(); - - xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); - - if (USBFS_currentTD.count > xferCount) - { - USBFS_currentTD.count = xferCount; - } - - /* Expect Data or Status Stage */ - USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; - - return(USBFS_TRUE); -} - - -/******************************************************************************* -* Function Name: USBFS_ControlWriteDataStage -******************************************************************************** -* -* Summary: -* Handle the Data Stage of a control write transfer -* 1. Get the data (We assume the destination was validated previously) -* 2. Update the count and data toggle -* 3. Update the mode register for the next transaction -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_transferByteCount - Update the transfer byte count from the -* last transaction. -* USBFS_ep0Count - counts the data loaded from the SIE memory -* in current packet. -* USBFS_transferByteCount - sum of the previous bytes transferred -* on previous packets(sum of USBFS_lastPacketSize) -* USBFS_ep0Toggle - inverted -* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_ControlWriteDataStage(void) -{ - uint8 ep0Count; - uint8 regIndex = 0u; - - ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - - USBFS_EPX_CNTX_CRC_COUNT; - - USBFS_transferByteCount += ep0Count; - - while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) - { - *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); - USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; - regIndex++; - ep0Count--; - USBFS_currentTD.count--; - } - USBFS_ep0Count = ep0Count; - /* Update the data toggle */ - USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; - /* Expect Data or Status Stage */ - USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; -} - - -/******************************************************************************* -* Function Name: USBFS_ControlWriteStatusStage -******************************************************************************** -* -* Summary: -* Handle the Status Stage of a control write transfer -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_transferState - set to TRANS_STATE_IDLE. -* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_ControlWriteStatusStage(void) -{ - /* Go Idle */ - USBFS_transferState = USBFS_TRANS_STATE_IDLE; - /* Update the completion block */ - USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - /* We expect no more data, so stall INs and OUTs */ - USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; -} - - -/******************************************************************************* -* Function Name: USBFS_InitNoDataControlTransfer -******************************************************************************** -* -* Summary: -* Initialize a no data control transfer -* -* Parameters: -* None. -* -* Return: -* requestHandled state. -* -* Global variables: -* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. -* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. -* USBFS_ep0Count - cleared. -* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_InitNoDataControlTransfer(void) -{ - USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; - USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; - USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - USBFS_ep0Count = 0u; - - return(USBFS_TRUE); -} - - -/******************************************************************************* -* Function Name: USBFS_NoDataControlStatusStage -******************************************************************************** -* Summary: -* Handle the Status Stage of a no data control transfer. -* -* SET_ADDRESS is special, since we need to receive the status stage with -* the old address. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_transferState - set to TRANS_STATE_IDLE. -* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. -* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE -* USBFS_deviceAddress - used to set new address and cleared -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_NoDataControlStatusStage(void) -{ - /* Change the USB address register if we got a SET_ADDRESS. */ - if (USBFS_deviceAddress != 0u) - { - CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); - USBFS_deviceAddress = 0u; - } - /* Go Idle */ - USBFS_transferState = USBFS_TRANS_STATE_IDLE; - /* Update the completion block */ - USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - /* We expect no more data, so stall INs and OUTs */ - USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; -} - - -/******************************************************************************* -* Function Name: USBFS_UpdateStatusBlock -******************************************************************************** -* -* Summary: -* Update the Completion Status Block for a Request. The block is updated -* with the completion code the USBFS_transferByteCount. The -* StatusBlock Pointer is set to NULL. -* -* Parameters: -* completionCode - status. -* -* Return: -* None. -* -* Global variables: -* USBFS_currentTD.pStatusBlock->status - updated by the -* completionCode parameter. -* USBFS_currentTD.pStatusBlock->length - updated. -* USBFS_currentTD.pStatusBlock - cleared. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_UpdateStatusBlock(uint8 completionCode) -{ - if (USBFS_currentTD.pStatusBlock != NULL) - { - USBFS_currentTD.pStatusBlock->status = completionCode; - USBFS_currentTD.pStatusBlock->length = USBFS_transferByteCount; - USBFS_currentTD.pStatusBlock = NULL; - } -} - - -/******************************************************************************* -* Function Name: USBFS_InitializeStatusBlock -******************************************************************************** -* -* Summary: -* Initialize the Completion Status Block for a Request. The completion -* code is set to USB_XFER_IDLE. -* -* Also, initializes USBFS_transferByteCount. Save some space, -* this is the only consumer. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. -* USBFS_currentTD.pStatusBlock->length - cleared. -* USBFS_transferByteCount - cleared. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_InitializeStatusBlock(void) -{ - USBFS_transferByteCount = 0u; - if(USBFS_currentTD.pStatusBlock != NULL) - { - USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; - USBFS_currentTD.pStatusBlock->length = 0u; - } -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_episr.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_episr.c deleted file mode 100755 index cd88e92..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_episr.c +++ /dev/null @@ -1,658 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_episr.c -* Version 2.60 -* -* Description: -* Data endpoint Interrupt Service Routines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" -#include "USBFS_pvt.h" -#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) - #include "USBFS_midi.h" -#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - - -/*************************************** -* Custom Declarations -***************************************/ -/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -#if(USBFS_EP1_ISR_REMOVE == 0u) - - - /****************************************************************************** - * Function Name: USBFS_EP_1_ISR - ******************************************************************************* - * - * Summary: - * Endpoint 1 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - ******************************************************************************/ - CY_ISR(USBFS_EP_1_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - /* `#START EP1_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) & - (uint8)~USBFS_SIE_EP_INT_EP1_MASK); - - #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) - if(USBFS_midi_out_ep == USBFS_EP1) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP1_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) - EA = int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - } - -#endif /* End USBFS_EP1_ISR_REMOVE */ - - -#if(USBFS_EP2_ISR_REMOVE == 0u) - - /******************************************************************************* - * Function Name: USBFS_EP_2_ISR - ******************************************************************************** - * - * Summary: - * Endpoint 2 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_EP_2_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - /* `#START EP2_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 ) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP2_MASK); - - #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT ) - if(USBFS_midi_out_ep == USBFS_EP2) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP2_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - } - -#endif /* End USBFS_EP2_ISR_REMOVE */ - - -#if(USBFS_EP3_ISR_REMOVE == 0u) - - /******************************************************************************* - * Function Name: USBFS_EP_3_ISR - ******************************************************************************** - * - * Summary: - * Endpoint 3 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_EP_3_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - /* `#START EP3_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP3_MASK); - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP3) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP3_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - } - -#endif /* End USBFS_EP3_ISR_REMOVE */ - - -#if(USBFS_EP4_ISR_REMOVE == 0u) - - /******************************************************************************* - * Function Name: USBFS_EP_4_ISR - ******************************************************************************** - * - * Summary: - * Endpoint 4 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_EP_4_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP4_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP4_MASK); - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP4) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP4_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - } - -#endif /* End USBFS_EP4_ISR_REMOVE */ - - -#if(USBFS_EP5_ISR_REMOVE == 0u) - - /******************************************************************************* - * Function Name: USBFS_EP_5_ISR - ******************************************************************************** - * - * Summary: - * Endpoint 5 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_EP_5_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP5_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP5_MASK); - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP5) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP5_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - } -#endif /* End USBFS_EP5_ISR_REMOVE */ - - -#if(USBFS_EP6_ISR_REMOVE == 0u) - - /******************************************************************************* - * Function Name: USBFS_EP_6_ISR - ******************************************************************************** - * - * Summary: - * Endpoint 6 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_EP_6_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP6_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP6_MASK); - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP6) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP6_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - } - -#endif /* End USBFS_EP6_ISR_REMOVE */ - - -#if(USBFS_EP7_ISR_REMOVE == 0u) - - /******************************************************************************* - * Function Name: USBFS_EP_7_ISR - ******************************************************************************** - * - * Summary: - * Endpoint 7 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_EP_7_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP7_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP7_MASK); - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP7) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP7_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - } - -#endif /* End USBFS_EP7_ISR_REMOVE */ - - -#if(USBFS_EP8_ISR_REMOVE == 0u) - - /******************************************************************************* - * Function Name: USBFS_EP_8_ISR - ******************************************************************************** - * - * Summary: - * Endpoint 8 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_EP_8_ISR) - { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP8_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) - { - USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP8_MASK); - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP8) - { - USBFS_MIDI_OUT_EP_Service(); - } - #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */ - - /* `#START EP8_END_USER_CODE` Place your code here */ - - /* `#END` */ - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - } - -#endif /* End USBFS_EP8_ISR_REMOVE */ - - -/******************************************************************************* -* Function Name: USBFS_SOF_ISR -******************************************************************************** -* -* Summary: -* Start of Frame Interrupt Service Routine -* -* Parameters: -* None. -* -* Return: -* None. -* -*******************************************************************************/ -CY_ISR(USBFS_SOF_ISR) -{ - /* `#START SOF_USER_CODE` Place your code here */ - - /* `#END` */ -} - - -/******************************************************************************* -* Function Name: USBFS_BUS_RESET_ISR -******************************************************************************** -* -* Summary: -* USB Bus Reset Interrupt Service Routine. Calls _Start with the same -* parameters as the last USER call to _Start -* -* Parameters: -* None. -* -* Return: -* None. -* -*******************************************************************************/ -CY_ISR(USBFS_BUS_RESET_ISR) -{ - /* `#START BUS_RESET_USER_CODE` Place your code here */ - - /* `#END` */ - - USBFS_ReInitComponent(); -} - - -#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) - - - /******************************************************************************* - * Function Name: USBFS_ARB_ISR - ******************************************************************************** - * - * Summary: - * Arbiter Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. - * - * Side effect: - * Search for EP8 int_status will be much slower than search for EP1 int_status. - * - *******************************************************************************/ - CY_ISR(USBFS_ARB_ISR) - { - uint8 int_status; - uint8 ep_status; - uint8 ep = USBFS_EP1; - uint8 ptr = 0u; - - /* `#START ARB_BEGIN_USER_CODE` Place your code here */ - - /* `#END` */ - - int_status = USBFS_ARB_INT_SR_REG; /* read Arbiter Status Register */ - USBFS_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */ - - while(int_status != 0u) - { - if((int_status & 1u) != 0u) /* If EpX interrupt present */ - { /* read Endpoint Status Register */ - ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr)); - /* If In Buffer Full */ - if((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) != 0u) - { - if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - { - /* Clear Data ready status */ - *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &= - (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode); - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) - if(ep == USBFS_midi_in_ep) - { /* Clear MIDI input pointer */ - USBFS_midiInPointer = 0u; - } - #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - } - } - /* (re)arm Out EP only for mode2 */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - /* If DMA Grant */ - if((ep_status & USBFS_ARB_EPX_SR_DMA_GNT) != 0u) - { - if((USBFS_EP[ep].addr & USBFS_DIR_IN) == 0u) - { - USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), - USBFS_EP[ep].epMode); - } - } - #endif /* End USBFS_EP_MM */ - - /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */ - - /* `#END` */ - - CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */ - } - ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */ - ep++; - int_status >>= 1u; - } - - /* `#START ARB_END_USER_CODE` Place your code here */ - - /* `#END` */ - } - -#endif /* End USBFS_EP_MM */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_hid.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_hid.c deleted file mode 100755 index ba9fdf5..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_hid.c +++ /dev/null @@ -1,422 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_hid.c -* Version 2.60 -* -* Description: -* USB HID Class request handler. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" - -#if defined(USBFS_ENABLE_HID_CLASS) - -#include "USBFS_pvt.h" -#include "USBFS_hid.h" - - -/*************************************** -* HID Variables -***************************************/ - -volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; /* HID device protocol status */ -volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */ -volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */ - - -/*************************************** -* Custom Declarations -***************************************/ - -/* `#START HID_CUSTOM_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -/******************************************************************************* -* Function Name: USBFS_UpdateHIDTimer -******************************************************************************** -* -* Summary: -* Updates the HID report timer and reloads it if expired -* -* Parameters: -* interface: Interface Number. -* -* Return: -* status. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_UpdateHIDTimer(uint8 interface) -{ - uint8 stat = USBFS_IDLE_TIMER_INDEFINITE; - - if(USBFS_hidIdleRate[interface] != 0u) - { - if(USBFS_hidIdleTimer[interface] > 0u) - { - USBFS_hidIdleTimer[interface]--; - stat = USBFS_IDLE_TIMER_RUNNING; - } - else - { - USBFS_hidIdleTimer[interface] = USBFS_hidIdleRate[interface]; - stat = USBFS_IDLE_TIMER_EXPIRED; - } - } - - return(stat); -} - - -/******************************************************************************* -* Function Name: USBFS_GetProtocol -******************************************************************************** -* -* Summary: -* Returns the selected protocol value to the application -* -* Parameters: -* interface: Interface Number. -* -* Return: -* Interface protocol. -* -*******************************************************************************/ -uint8 USBFS_GetProtocol(uint8 interface) -{ - return(USBFS_hidProtocol[interface]); -} - - -/******************************************************************************* -* Function Name: USBFS_DispatchHIDClassRqst -******************************************************************************** -* -* Summary: -* This routine dispatches class requests -* -* Parameters: -* None. -* -* Return: -* requestHandled -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_DispatchHIDClassRqst(void) -{ - uint8 requestHandled = USBFS_FALSE; - uint8 interfaceNumber; - - interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - { /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_GET_DESCRIPTOR: - if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS) - { - USBFS_FindHidClassDecriptor(); - if (USBFS_currentTD.count != 0u) - { - requestHandled = USBFS_InitControlRead(); - } - } - else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT) - { - USBFS_FindReportDescriptor(); - if (USBFS_currentTD.count != 0u) - { - requestHandled = USBFS_InitControlRead(); - } - } - else - { /* requestHandled is initialezed as FALSE by default */ - } - break; - case USBFS_HID_GET_REPORT: - USBFS_FindReport(); - if (USBFS_currentTD.count != 0u) - { - requestHandled = USBFS_InitControlRead(); - } - break; - - case USBFS_HID_GET_IDLE: - /* This function does not support multiple reports per interface*/ - /* Validate interfaceNumber and Report ID (should be 0) */ - if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ - { - USBFS_currentTD.count = 1u; - USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; - requestHandled = USBFS_InitControlRead(); - } - break; - case USBFS_HID_GET_PROTOCOL: - /* Validate interfaceNumber */ - if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) - { - USBFS_currentTD.count = 1u; - USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; - requestHandled = USBFS_InitControlRead(); - } - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - } - else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == - USBFS_RQST_DIR_H2D) - { /* Control Write */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_HID_SET_REPORT: - USBFS_FindReport(); - if (USBFS_currentTD.count != 0u) - { - requestHandled = USBFS_InitControlWrite(); - } - break; - case USBFS_HID_SET_IDLE: - /* This function does not support multiple reports per interface */ - /* Validate interfaceNumber and Report ID (should be 0) */ - if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ - { - USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi); - /* With regards to HID spec: "7.2.4 Set_Idle Request" - * Latency. If the current period has gone past the - * newly proscribed time duration, then a report - * will be generated immediately. - */ - if(USBFS_hidIdleRate[interfaceNumber] < - USBFS_hidIdleTimer[interfaceNumber]) - { - /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER_EXPIRED status*/ - USBFS_hidIdleTimer[interfaceNumber] = 0u; - } - /* If the new request is received within 4 milliseconds - * (1 count) of the end of the current period, then the - * new request will have no effect until after the report. - */ - else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) - { - /* Do nothing. - * Let the UpdateHIDTimer() API continue to work and - * return IDLE_TIMER_EXPIRED status - */ - } - else - { /* Reload the timer*/ - USBFS_hidIdleTimer[interfaceNumber] = - USBFS_hidIdleRate[interfaceNumber]; - } - requestHandled = USBFS_InitNoDataControlTransfer(); - } - break; - - case USBFS_HID_SET_PROTOCOL: - /* Validate interfaceNumber and protocol (must be 0 or 1) */ - if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - (CY_GET_REG8(USBFS_wValueLo) <= 1u) ) - { - USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo); - requestHandled = USBFS_InitNoDataControlTransfer(); - } - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - } - else - { /* requestHandled is initialized as FALSE by default */ - } - - return(requestHandled); -} - - -/******************************************************************************* -* Function Name: USB_FindHidClassDescriptor -******************************************************************************** -* -* Summary: -* This routine find Hid Class Descriptor pointer based on the Interface number -* and Alternate setting then loads the currentTD structure with the address of -* the buffer and the size. -* The HID Class Descriptor resides inside the config descriptor. -* -* Parameters: -* None. -* -* Return: -* currentTD -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_FindHidClassDecriptor(void) -{ - const T_USBFS_LUT CYCODE *pTmp; - volatile uint8 *pDescr; - uint8 interfaceN; - - pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - interfaceN = CY_GET_REG8(USBFS_wIndexLo); - /* Third entry in the LUT starts the Interface Table pointers */ - /* Now use the request interface number*/ - pTmp = &pTmp[interfaceN + 2u]; - /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ - pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - /* Now use Alternate setting number */ - pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ - pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ - pTmp = &pTmp[4u]; - pDescr = (volatile uint8 *)pTmp->p_list; - /* The first byte contains the descriptor length */ - USBFS_currentTD.count = *pDescr; - USBFS_currentTD.pData = pDescr; -} - - -/******************************************************************************* -* Function Name: USB_FindReportDescriptor -******************************************************************************** -* -* Summary: -* This routine find Hid Report Descriptor pointer based on the Interface -* number, then loads the currentTD structure with the address of the buffer -* and the size. -* Hid Report Descriptor is located after IN/OUT/FEATURE reports. -* -* Parameters: -* void -* -* Return: -* currentTD -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_FindReportDescriptor(void) -{ - const T_USBFS_LUT CYCODE *pTmp; - volatile uint8 *pDescr; - uint8 interfaceN; - - pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - interfaceN = CY_GET_REG8(USBFS_wIndexLo); - /* Third entry in the LUT starts the Interface Table pointers */ - /* Now use the request interface number */ - pTmp = &pTmp[interfaceN + 2u]; - /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ - pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - /* Now use Alternate setting number */ - pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ - pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - /* Fourth entry in the LUT starts the Hid Report Descriptor */ - pTmp = &pTmp[3u]; - pDescr = (volatile uint8 *)pTmp->p_list; - /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ - USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]); - USBFS_currentTD.pData = &pDescr[2u]; -} - - -/******************************************************************************* -* Function Name: USBFS_FindReport -******************************************************************************** -* -* Summary: -* This routine sets up a transfer based on the Interface number, Report Type -* and Report ID, then loads the currentTD structure with the address of the -* buffer and the size. The caller has to decide if it is a control read or -* control write. -* -* Parameters: -* None. -* -* Return: -* currentTD -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_FindReport(void) -{ - const T_USBFS_LUT CYCODE *pTmp; - T_USBFS_TD *pTD; - uint8 interfaceN; - uint8 reportType; - - /* `#START HID_FINDREPORT` Place custom handling here */ - - /* `#END` */ - USBFS_currentTD.count = 0u; /* Init not supported condition */ - pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - reportType = CY_GET_REG8(USBFS_wValueHi); - interfaceN = CY_GET_REG8(USBFS_wIndexLo); - /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */ - /* Now use the request interface number */ - pTmp = &pTmp[interfaceN + 2u]; - /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/ - pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - if(interfaceN < USBFS_MAX_INTERFACES_NUMBER) - { - /* Now use Alternate setting number */ - pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; - /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ - pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - /* Validate reportType to comply with "7.2.1 Get_Report Request" */ - if((reportType >= USBFS_HID_GET_REPORT_INPUT) && - (reportType <= USBFS_HID_GET_REPORT_FEATURE)) - { - /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ - pTmp = &pTmp[reportType - 1u]; - reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */ - /* Validate table support by the HID descriptor, compare table count with reportID */ - if(pTmp->c >= reportType) - { - pTD = (T_USBFS_TD *) pTmp->p_list; - pTD = &pTD[reportType]; /* select entry depend on report ID*/ - USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ - USBFS_currentTD.count = pTD->count; /* Buffer Size */ - USBFS_currentTD.pStatusBlock = pTD->pStatusBlock; - } - } - } -} - - -/******************************************************************************* -* Additional user functions supporting HID Requests -********************************************************************************/ - -/* `#START HID_FUNCTIONS` Place any additional functions here */ - -/* `#END` */ - -#endif /* End USBFS_ENABLE_HID_CLASS */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_hid.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_hid.h deleted file mode 100755 index 9a6201c..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_hid.h +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_hid.h -* Version 2.60 -* -* Description: -* Header File for the USFS component. Contains prototypes and constant values. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_USBFS_USBFS_hid_H) -#define CY_USBFS_USBFS_hid_H - -#include "cytypes.h" - - -/*************************************** -* Prototypes of the USBFS_hid API. -***************************************/ - -uint8 USBFS_UpdateHIDTimer(uint8 interface) ; -uint8 USBFS_GetProtocol(uint8 interface) ; - - -/*************************************** -*Renamed Functions for backward compatible -***************************************/ - -#define USBFS_bGetProtocol USBFS_GetProtocol - - -/*************************************** -* Constants for USBFS_hid API. -***************************************/ - -#define USBFS_PROTOCOL_BOOT (0x00u) -#define USBFS_PROTOCOL_REPORT (0x01u) - -/* Request Types (HID Chapter 7.2) */ -#define USBFS_HID_GET_REPORT (0x01u) -#define USBFS_HID_GET_IDLE (0x02u) -#define USBFS_HID_GET_PROTOCOL (0x03u) -#define USBFS_HID_SET_REPORT (0x09u) -#define USBFS_HID_SET_IDLE (0x0Au) -#define USBFS_HID_SET_PROTOCOL (0x0Bu) - -/* Descriptor Types (HID Chapter 7.1) */ -#define USBFS_DESCR_HID_CLASS (0x21u) -#define USBFS_DESCR_HID_REPORT (0x22u) -#define USBFS_DESCR_HID_PHYSICAL (0x23u) - -/* Report Request Types (HID Chapter 7.2.1) */ -#define USBFS_HID_GET_REPORT_INPUT (0x01u) -#define USBFS_HID_GET_REPORT_OUTPUT (0x02u) -#define USBFS_HID_GET_REPORT_FEATURE (0x03u) - -#endif /* End CY_USBFS_USBFS_hid_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_midi.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_midi.c deleted file mode 100755 index 1f0ce51..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_midi.c +++ /dev/null @@ -1,1341 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_midi.c -* Version 2.60 -* -* Description: -* MIDI Streaming request handler. -* This file contains routines for sending and receiving MIDI -* messages, and handles running status in both directions. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" - -#if defined(USBFS_ENABLE_MIDI_STREAMING) - -#include "USBFS_midi.h" -#include "USBFS_pvt.h" - - -/*************************************** -* MIDI Constants -***************************************/ - -#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - /* The Size of the MIDI messages (MIDI Table 4-1) */ - static const uint8 CYCODE USBFS_MIDI_SIZE[] = { - /* Miscellaneous function codes(Reserved) */ 0x03u, - /* Cable events (Reserved) */ 0x03u, - /* Two-byte System Common messages */ 0x02u, - /* Three-byte System Common messages */ 0x03u, - /* SysEx starts or continues */ 0x03u, - /* Single-byte System Common Message or - SysEx ends with following single byte */ 0x01u, - /* SysEx ends with following two bytes */ 0x02u, - /* SysEx ends with following three bytes */ 0x03u, - /* Note-off */ 0x03u, - /* Note-on */ 0x03u, - /* Poly-KeyPress */ 0x03u, - /* Control Change */ 0x03u, - /* Program Change */ 0x02u, - /* Channel Pressure */ 0x02u, - /* PitchBend Change */ 0x03u, - /* Single Byte */ 0x01u - }; -#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - - - -/*************************************** -* Global variables -***************************************/ - -#if (USBFS_MIDI_IN_BUFF_SIZE > 0) - #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) - volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ - #else - volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ - #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */ - volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ - uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ -#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ - -#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ - uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ -#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ - -#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */ - static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */ - volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ - - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */ - static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */ - volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - - -/*************************************** -* Custom Declarations -***************************************/ - -/* `#START MIDI_CUSTOM_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -/*************************************** -* Optional MIDI APIs -***************************************/ -#if (USBFS_ENABLE_MIDI_API != 0u) - - -/******************************************************************************* -* Function Name: USBFS_MIDI_EP_Init -******************************************************************************** -* -* Summary: -* This function initializes the MIDI interface and UART(s) to be ready to -* receive data from the PC and MIDI ports. -* -* Parameters: -* None -* -* Return: -* None -* -* Global variables: -* USBFS_midiInBuffer: This buffer is used for saving and combining -* the received data from UART(s) and(or) generated internally by -* PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service() -* function transfers the data from this buffer to the PC. -* USBFS_midiOutBuffer: This buffer is used by the -* USBFS_MIDI_OUT_EP_Service() function for saving the received -* from the PC data, then the data are parsed and transferred to UART(s) -* buffer and to the internal processing by the -* USBFS_callbackLocalMidiEvent function. -* USBFS_midi_out_ep: Used as an OUT endpoint number. -* USBFS_midi_in_ep: Used as an IN endpoint number. -* USBFS_midiInPointer: Initialized to zero. -* -* Reentrant: -* No -* -*******************************************************************************/ -void USBFS_MIDI_EP_Init(void) -{ - #if (USBFS_MIDI_IN_BUFF_SIZE > 0) - USBFS_midiInPointer = 0u; - #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ - - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - #if (USBFS_MIDI_IN_BUFF_SIZE > 0) - /* Init DMA configurations for IN EP*/ - USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, - USBFS_MIDI_IN_BUFF_SIZE); - - #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ - #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - /* Init DMA configurations for OUT EP*/ - (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer, - USBFS_MIDI_OUT_BUFF_SIZE); - #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */ - #endif /* End USBFS__EP_DMAAUTO */ - - #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - USBFS_EnableOutEP(USBFS_midi_out_ep); - #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ - - /* Initialize the MIDI port(s) */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - USBFS_MIDI_Init(); - #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ -} - -#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - - - /******************************************************************************* - * Function Name: USBFS_MIDI_OUT_EP_Service - ******************************************************************************** - * - * Summary: - * Services the USB MIDI OUT endpoints. - * This function is called from OUT EP ISR. It transfers the received from PC - * data to the external MIDI port(UART TX buffer) and calls the - * USBFS_callbackLocalMidiEvent() function to internal process - * of the MIDI data. - * This function is blocked by UART, if not enough space is available in UART - * TX buffer. Therefore it is recommended to use large UART TX buffer size. - * - * Parameters: - * None - * - * Return: - * None - * - * Global variables: - * USBFS_midiOutBuffer: Used as temporary buffer between USB internal - * memory and UART TX buffer. - * USBFS_midi_out_ep: Used as an OUT endpoint number. - * - * Reentrant: - * No - * - *******************************************************************************/ - void USBFS_MIDI_OUT_EP_Service(void) - { - #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 - uint16 outLength; - uint16 outPointer; - #else - uint8 outLength; - uint8 outPointer; - #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */ - - uint8 dmaState = 0u; - - /* Service the USB MIDI output endpoint */ - if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL) - { - #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 - outLength = USBFS_GetEPCount(USBFS_midi_out_ep); - #else - outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep); - #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 - outLength = USBFS_ReadOutEP(USBFS_midi_out_ep, - USBFS_midiOutBuffer, outLength); - #else - outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep, - USBFS_midiOutBuffer, (uint16)outLength); - #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */ - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - do /* wait for DMA transfer complete */ - { - (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState); - }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u); - #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - if(dmaState != 0u) - { - /* Suppress compiler warning */ - } - if (outLength >= USBFS_EVENT_LENGTH) - { - outPointer = 0u; - while (outPointer < outLength) - { - /* In some OS OUT packet could be appended by nulls which could be skipped */ - if (USBFS_midiOutBuffer[outPointer] == 0u) - { - break; - } - /* Route USB MIDI to the External connection */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == - USBFS_MIDI_CABLE_00) - { - USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); - } - else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == - USBFS_MIDI_CABLE_01) - { - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ - } - else - { - /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */ - - /* `#END` */ - } - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - - /* Process any local MIDI output functions */ - USBFS_callbackLocalMidiEvent( - USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK, - &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]); - outPointer += USBFS_EVENT_LENGTH; - } - } - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* Enable Out EP*/ - USBFS_EnableOutEP(USBFS_midi_out_ep); - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - } - } - -#endif /* #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ - -#if (USBFS_MIDI_IN_BUFF_SIZE > 0) - - - /******************************************************************************* - * Function Name: USBFS_MIDI_IN_EP_Service - ******************************************************************************** - * - * Summary: - * Services the USB MIDI IN endpoint. Non-blocking. - * Checks that previous packet was processed by HOST, otherwise service the - * input endpoint on the subsequent call. It is called from the - * USBFS_MIDI_IN_Service() and from the - * USBFS_PutUsbMidiIn() function. - * - * Parameters: - * None - * - * Return: - * None - * - * Global variables: - * USBFS_midi_in_ep: Used as an IN endpoint number. - * USBFS_midiInBuffer: Function loads the data from this buffer to - * the USB IN endpoint. - * USBFS_midiInPointer: Cleared to zero when data are sent. - * - * Reentrant: - * No - * - *******************************************************************************/ - void USBFS_MIDI_IN_EP_Service(void) - { - /* Service the USB MIDI input endpoint */ - /* Check that previous packet was processed by HOST, otherwise service the USB later */ - if (USBFS_midiInPointer != 0u) - { - if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING) - { - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, - (uint16)USBFS_midiInPointer); - #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ - /* rearm IN EP */ - USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer); - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/ - - /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */ - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - USBFS_midiInPointer = 0u; - #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ - } - } - } - - - /******************************************************************************* - * Function Name: USBFS_MIDI_IN_Service - ******************************************************************************** - * - * Summary: - * Services the traffic from the MIDI input ports (RX UART) and prepare data - * in USB MIDI IN endpoint buffer. - * Calls the USBFS_MIDI_IN_EP_Service() function to sent the - * data from buffer to PC. Non-blocking. Should be called from main foreground - * task. - * This function is not protected from the reentrant calls. When it is required - * to use this function in UART RX ISR to guaranty low latency, care should be - * taken to protect from reentrant calls. - * - * Parameters: - * None - * - * Return: - * None - * - * Global variables: - * USBFS_midiInPointer: Cleared to zero when data are sent. - * - * Reentrant: - * No - * - *******************************************************************************/ - void USBFS_MIDI_IN_Service(void) - { - /* Service the MIDI UART inputs until either both receivers have no more - * events or until the input endpoint buffer fills up. - */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - uint8 m1 = 0u; - uint8 m2 = 0u; - do - { - if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) - { - /* Check MIDI1 input port for a complete event */ - m1 = USBFS_MIDI1_GetEvent(); - if (m1 != 0u) - { - USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0], - USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00); - } - } - - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) - { - /* Check MIDI2 input port for a complete event */ - m2 = USBFS_MIDI2_GetEvent(); - if (m2 != 0u) - { - USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0], - USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01); - } - } - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ - - }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) - && ((m1 != 0u) || (m2 != 0u)) ); - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - - /* Service the USB MIDI input endpoint */ - USBFS_MIDI_IN_EP_Service(); - } - - - /******************************************************************************* - * Function Name: USBFS_PutUsbMidiIn - ******************************************************************************** - * - * Summary: - * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are - * MIDI input messages to the host. This function is only used if the device - * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function - * should additionally be called to send the message from local buffer to - * IN endpoint. - * - * Parameters: - * ic: 0 = No message (should never happen) - * 1 - 3 = Complete MIDI message in midiMsg - * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in - * midiMsg. The length is limited by the max BULK EP size(64) - * MIDI_SYSEX = Start or continuation of SysEx message - * (put event bytes in midiMsg buffer) - * MIDI_EOSEX = End of SysEx message - * (put event bytes in midiMsg buffer) - * MIDI_TUNEREQ = Tune Request message (single byte system common msg) - * 0xf8 - 0xff = Single byte real-time message - * midiMsg: pointer to MIDI message. - * cable: cable number. - * - * Return: - * USBFS_TRUE if error. - * USBFS_FALSE if success. - * - * Global variables: - * USBFS_midi_in_ep: MIDI IN endpoint number used for sending data. - * USBFS_midiInPointer: Checked this variable to see if there is - * enough free space in the IN endpoint buffer. If buffer is full, initiate - * sending to PC. - * - * Reentrant: - * No - * - *******************************************************************************/ - uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) - - { - uint8 retError = USBFS_FALSE; - uint8 msgIndex; - - /* Protect PrepareInBuffer() function from concurrent calls */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - MIDI1_UART_DisableRxInt(); - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - MIDI2_UART_DisableRxInt(); - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - - if (USBFS_midiInPointer > - (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) - { - USBFS_MIDI_IN_EP_Service(); - } - if (USBFS_midiInPointer <= - (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) - { - if((ic < USBFS_EVENT_LENGTH) || (ic >= USBFS_MIDI_STATUS_MASK)) - { - USBFS_PrepareInBuffer(ic, midiMsg, ic, cable); - } - else - { /* Only SysEx message is greater than 4 bytes */ - msgIndex = 0u; - do - { - USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex], - USBFS_EVENT_BYTE3, cable); - ic -= USBFS_EVENT_BYTE3; - msgIndex += USBFS_EVENT_BYTE3; - if (USBFS_midiInPointer > - (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) - { - USBFS_MIDI_IN_EP_Service(); - if (USBFS_midiInPointer > - (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) - { - /* Error condition. HOST is not ready to receive this packet. */ - retError = USBFS_TRUE; - break; - } - } - }while(ic > USBFS_EVENT_BYTE3); - - if(retError == USBFS_FALSE) - { - USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable); - } - } - } - else - { - /* Error condition. HOST is not ready to receive this packet. */ - retError = USBFS_TRUE; - } - - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - MIDI1_UART_EnableRxInt(); - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - MIDI2_UART_EnableRxInt(); - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - - return (retError); - } - - - /******************************************************************************* - * Function Name: USBFS_PrepareInBuffer - ******************************************************************************** - * - * Summary: - * Builds a USB MIDI event in the input endpoint buffer at the current pointer. - * Puts one MIDI message into the USB MIDI In endpoint buffer. - * - * Parameters: - * ic: 0 = No message (should never happen) - * 1 - 3 = Complete MIDI message at pMdat[0] - * MIDI_SYSEX = Start or continuation of SysEx message - * (put eventLen bytes in buffer) - * MIDI_EOSEX = End of SysEx message - * (put eventLen bytes in buffer, - * and append MIDI_EOSEX) - * MIDI_TUNEREQ = Tune Request message (single byte system common msg) - * 0xf8 - 0xff = Single byte real-time message - * - * srcBuff: pointer to MIDI data - * eventLen: number of bytes in MIDI event - * cable: MIDI source port number - * - * Return: - * None - * - * Global variables: - * USBFS_midiInBuffer: This buffer is used for saving and combine the - * received from UART(s) and(or) generated internally by - * USBFS_PutUsbMidiIn() function messages. - * USBFS_midiInPointer: Used as an index for midiInBuffer to - * write data. - * - * Reentrant: - * No - * - *******************************************************************************/ - void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) - - { - uint8 srcBuffZero; - uint8 srcBuffOne; - - srcBuffZero = srcBuff[0u]; - srcBuffOne = srcBuff[1u]; - - if (ic >= (USBFS_MIDI_STATUS_MASK | USBFS_MIDI_SINGLE_BYTE_MASK)) - { - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SINGLE_BYTE | cable; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = ic; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; - USBFS_midiInPointer++; - } - else if((ic < USBFS_EVENT_LENGTH) || (ic == USBFS_MIDI_SYSEX)) - { - if(ic == USBFS_MIDI_SYSEX) - { - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SYSEX | cable; - USBFS_midiInPointer++; - } - else if (srcBuffZero < USBFS_MIDI_SYSEX) - { - USBFS_midiInBuffer[USBFS_midiInPointer] = (srcBuffZero >> 4u) | cable; - USBFS_midiInPointer++; - } - else if (srcBuffZero == USBFS_MIDI_TUNEREQ) - { - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_1BYTE_COMMON | cable; - USBFS_midiInPointer++; - } - else if ((srcBuffZero == USBFS_MIDI_QFM) || (srcBuffZero == USBFS_MIDI_SONGSEL)) - { - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_2BYTE_COMMON | cable; - USBFS_midiInPointer++; - } - else if (srcBuffZero == USBFS_MIDI_SPP) - { - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_3BYTE_COMMON | cable; - USBFS_midiInPointer++; - } - else - { - } - - USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuff[2u]; - USBFS_midiInPointer++; - } - else if (ic == USBFS_MIDI_EOSEX) - { - switch (eventLen) - { - case 0u: - USBFS_midiInBuffer[USBFS_midiInPointer] = - USBFS_SYSEX_ENDS_WITH1 | cable; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; - USBFS_midiInPointer++; - break; - case 1u: - USBFS_midiInBuffer[USBFS_midiInPointer] = - USBFS_SYSEX_ENDS_WITH2 | cable; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; - USBFS_midiInPointer++; - break; - case 2u: - USBFS_midiInBuffer[USBFS_midiInPointer] = - USBFS_SYSEX_ENDS_WITH3 | cable; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; - USBFS_midiInPointer++; - USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; - USBFS_midiInPointer++; - break; - default: - break; - } - } - else - { - } - } - -#endif /* #if (USBFS_MIDI_IN_BUFF_SIZE > 0) */ - - -/* The implementation for external serial input and output connections -* to route USB MIDI data to and from those connections. -*/ -#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - - - /******************************************************************************* - * Function Name: USBFS_MIDI_Init - ******************************************************************************** - * - * Summary: - * Initializes MIDI variables and starts the UART(s) hardware block(s). - * - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: - * Change the priority of the UART(s) TX interrupts to be higher than the - * default EP ISR priority. - * - * Global variables: - * USBFS_MIDI_Event: initialized to zero. - * USBFS_MIDI_TxRunStat: initialized to zero. - * - *******************************************************************************/ - void USBFS_MIDI_Init(void) - { - USBFS_MIDI1_Event.length = 0u; - USBFS_MIDI1_Event.count = 0u; - USBFS_MIDI1_Event.size = 0u; - USBFS_MIDI1_Event.runstat = 0u; - USBFS_MIDI1_TxRunStat = 0u; - USBFS_MIDI1_InqFlags = 0u; - /* Start UART block */ - MIDI1_UART_Start(); - /* Change the priority of the UART TX and RX interrupt */ - CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); - CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); - - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - USBFS_MIDI2_Event.length = 0u; - USBFS_MIDI2_Event.count = 0u; - USBFS_MIDI2_Event.size = 0u; - USBFS_MIDI2_Event.runstat = 0u; - USBFS_MIDI2_TxRunStat = 0u; - USBFS_MIDI2_InqFlags = 0u; - /* Start second UART block */ - MIDI2_UART_Start(); - /* Change the priority of the UART TX interrupt */ - CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); - CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/ - - /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */ - - /* `#END` */ - - } - - - /******************************************************************************* - * Function Name: USBFS_ProcessMidiIn - ******************************************************************************** - * - * Summary: - * Processes one byte of incoming MIDI data. - * - * Parameters: - * mData = current MIDI input data byte - * *rxStat = pointer to a MIDI_RX_STATUS structure - * - * Return: - * 0, if no complete message - * 1 - 4, if message complete - * MIDI_SYSEX, if start or continuation of system exclusive - * MIDI_EOSEX, if end of system exclusive - * 0xf8 - 0xff, if single byte real time message - * - *******************************************************************************/ - uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) - - { - uint8 midiReturn = 0u; - - /* Check for a MIDI status byte. All status bytes, except real time messages, - * which are a single byte, force the start of a new buffer cycle. - */ - if ((mData & USBFS_MIDI_STATUS_BYTE_MASK) != 0u) - { - if ((mData & USBFS_MIDI_STATUS_MASK) == USBFS_MIDI_STATUS_MASK) - { - if ((mData & USBFS_MIDI_SINGLE_BYTE_MASK) != 0u) /* System Real-Time Messages(single byte) */ - { - midiReturn = mData; - } - else /* System Common Messages */ - { - switch (mData) - { - case USBFS_MIDI_SYSEX: - rxStat->msgBuff[0u] = USBFS_MIDI_SYSEX; - rxStat->runstat = USBFS_MIDI_SYSEX; - rxStat->count = 1u; - rxStat->length = 3u; - break; - case USBFS_MIDI_EOSEX: - rxStat->runstat = 0u; - rxStat->size = rxStat->count; - rxStat->count = 0u; - midiReturn = USBFS_MIDI_EOSEX; - break; - case USBFS_MIDI_SPP: - rxStat->msgBuff[0u] = USBFS_MIDI_SPP; - rxStat->runstat = 0u; - rxStat->count = 1u; - rxStat->length = 3u; - break; - case USBFS_MIDI_SONGSEL: - rxStat->msgBuff[0u] = USBFS_MIDI_SONGSEL; - rxStat->runstat = 0u; - rxStat->count = 1u; - rxStat->length = 2u; - break; - case USBFS_MIDI_QFM: - rxStat->msgBuff[0u] = USBFS_MIDI_QFM; - rxStat->runstat = 0u; - rxStat->count = 1u; - rxStat->length = 2u; - break; - case USBFS_MIDI_TUNEREQ: - rxStat->msgBuff[0u] = USBFS_MIDI_TUNEREQ; - rxStat->runstat = 0u; - rxStat->size = 1u; - rxStat->count = 0u; - midiReturn = rxStat->size; - break; - default: - break; - } - } - } - else /* Channel Messages */ - { - rxStat->msgBuff[0u] = mData; - rxStat->runstat = mData; - rxStat->count = 1u; - switch (mData & USBFS_MIDI_STATUS_MASK) - { - case USBFS_MIDI_NOTE_OFF: - case USBFS_MIDI_NOTE_ON: - case USBFS_MIDI_POLY_KEY_PRESSURE: - case USBFS_MIDI_CONTROL_CHANGE: - case USBFS_MIDI_PITCH_BEND_CHANGE: - rxStat->length = 3u; - break; - case USBFS_MIDI_PROGRAM_CHANGE: - case USBFS_MIDI_CHANNEL_PRESSURE: - rxStat->length = 2u; - break; - default: - rxStat->runstat = 0u; - rxStat->count = 0u; - break; - } - } - } - - /* Otherwise, it's a data byte */ - else - { - if (rxStat->runstat == USBFS_MIDI_SYSEX) - { - rxStat->msgBuff[rxStat->count] = mData; - rxStat->count++; - if (rxStat->count >= rxStat->length) - { - rxStat->size = rxStat->count; - rxStat->count = 0u; - midiReturn = USBFS_MIDI_SYSEX; - } - } - else if (rxStat->count > 0u) - { - rxStat->msgBuff[rxStat->count] = mData; - rxStat->count++; - if (rxStat->count >= rxStat->length) - { - rxStat->size = rxStat->count; - rxStat->count = 0u; - midiReturn = rxStat->size; - } - } - else if (rxStat->runstat != 0u) - { - rxStat->msgBuff[0u] = rxStat->runstat; - rxStat->msgBuff[1u] = mData; - rxStat->count = 2u; - switch (rxStat->runstat & USBFS_MIDI_STATUS_MASK) - { - case USBFS_MIDI_NOTE_OFF: - case USBFS_MIDI_NOTE_ON: - case USBFS_MIDI_POLY_KEY_PRESSURE: - case USBFS_MIDI_CONTROL_CHANGE: - case USBFS_MIDI_PITCH_BEND_CHANGE: - rxStat->length = 3u; - break; - case USBFS_MIDI_PROGRAM_CHANGE: - case USBFS_MIDI_CHANNEL_PRESSURE: - rxStat->size =rxStat->count; - rxStat->count = 0u; - midiReturn = rxStat->size; - break; - default: - rxStat->count = 0u; - break; - } - } - else - { - } - } - return (midiReturn); - } - - - /******************************************************************************* - * Function Name: USBFS_MIDI1_GetEvent - ******************************************************************************** - * - * Summary: - * Checks for incoming MIDI data, calls the MIDI event builder if so. - * Returns either empty or with a complete event. - * - * Parameters: - * None - * - * Return: - * 0, if no complete message - * 1 - 4, if message complete - * MIDI_SYSEX, if start or continuation of system exclusive - * MIDI_EOSEX, if end of system exclusive - * 0xf8 - 0xff, if single byte real time message - * - * Global variables: - * USBFS_MIDI1_Event: RX status structure used to parse received - * data. - * - *******************************************************************************/ - uint8 USBFS_MIDI1_GetEvent(void) - { - uint8 msgRtn = 0u; - uint8 rxData; - #if (MIDI1_UART_RXBUFFERSIZE >= 256u) - uint16 rxBufferRead; - #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */ - uint16 rxBufferWrite; - #endif /* end CY_PSOC3 */ - #else - uint8 rxBufferRead; - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ - uint8 rxBufferLoopDetect; - /* Read buffer loop condition to the local variable */ - rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; - - if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) - { - /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI1_UART_RX_VECT_NUM); - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ - rxBufferRead = MIDI1_UART_rxBufferRead; - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - rxBufferWrite = MIDI1_UART_rxBufferWrite; - CyIntEnable(MIDI1_UART_RX_VECT_NUM); - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ - - /* Stay here until either the buffer is empty or we have a complete message - * in the message buffer. Note that we must use a temporary buffer pointer - * since it takes two instructions to increment with a wrap, and we can't - * risk doing that with the real pointer and getting an interrupt in between - * instructions. - */ - - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) - #else - while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */ - { - rxData = MIDI1_UART_rxBuffer[rxBufferRead]; - /* Increment pointer with a wrap */ - rxBufferRead++; - if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE) - { - rxBufferRead = 0u; - } - /* If loop condition was set - update real read buffer pointer - * to avoid overflow status - */ - if(rxBufferLoopDetect != 0u ) - { - MIDI1_UART_rxBufferLoopDetect = 0u; - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI1_UART_RX_VECT_NUM); - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ - MIDI1_UART_rxBufferRead = rxBufferRead; - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI1_UART_RX_VECT_NUM); - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ - } - - msgRtn = USBFS_ProcessMidiIn(rxData, - (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI1_Event); - - /* Read buffer loop condition to the local variable */ - rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; - } - - /* Finally, update the real output pointer, then return with - * an indication as to whether there's a complete message in the buffer. - */ - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI1_UART_RX_VECT_NUM); - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ - MIDI1_UART_rxBufferRead = rxBufferRead; - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI1_UART_RX_VECT_NUM); - #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */ - } - - return (msgRtn); - } - - - /******************************************************************************* - * Function Name: USBFS_MIDI1_ProcessUsbOut - ******************************************************************************** - * - * Summary: - * Process a USB MIDI output event. - * Puts data into the MIDI TX output buffer. - * - * Parameters: - * *epBuf: pointer on MIDI event. - * - * Return: - * None - * - * Global variables: - * USBFS_MIDI1_TxRunStat: This variable used to save the MIDI - * status byte and skip to send the repeated status byte in subsequent event. - * USBFS_MIDI1_InqFlags: The following flags are set when SysEx - * message comes. - * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. - * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. - * This bit should be cleared by user when Identity Reply message generated. - * - *******************************************************************************/ - void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) - - { - uint8 cmd; - uint8 len; - uint8 i; - - /* User code is required at the beginning of the procedure */ - /* `#START MIDI1_PROCESS_OUT_BEGIN` */ - - /* `#END` */ - - cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; - if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) - { - len = USBFS_MIDI_SIZE[cmd]; - i = USBFS_EVENT_BYTE1; - /* Universal System Exclusive message parsing */ - if(cmd == USBFS_SYSEX) - { - if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && - (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) - { /* Non-Real Time SySEx starts */ - USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG; - } - else - { - USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - } - } - else if(cmd == USBFS_SYSEX_ENDS_WITH1) - { - USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - } - else if(cmd == USBFS_SYSEX_ENDS_WITH2) - { - USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - } - else if(cmd == USBFS_SYSEX_ENDS_WITH3) - { - /* Identify Request support */ - if((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) - { - USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && - (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) - { /* Set the flag about received the Identity Request. - * The Identity Reply message may be send by user code. - */ - USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; - } - } - } - else /* Do nothing for other command */ - { - } - /* Running Status for Voice and Mode messages only. */ - if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) - { - if(USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) - { /* Skip the repeated Status byte */ - i++; - } - else - { /* Save Status byte for next event */ - USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; - } - } - else - { /* Clear Running Status */ - USBFS_MIDI1_TxRunStat = 0u; - } - /* Puts data into the MIDI TX output buffer.*/ - do - { - MIDI1_UART_PutChar(epBuf[i]); - i++; - } while (i <= len); - } - - /* User code is required at the end of the procedure */ - /* `#START MIDI1_PROCESS_OUT_END` */ - - /* `#END` */ - } - -#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - - - /******************************************************************************* - * Function Name: USBFS_MIDI2_GetEvent - ******************************************************************************** - * - * Summary: - * Checks for incoming MIDI data, calls the MIDI event builder if so. - * Returns either empty or with a complete event. - * - * Parameters: - * None - * - * Return: - * 0, if no complete message - * 1 - 4, if message complete - * MIDI_SYSEX, if start or continuation of system exclusive - * MIDI_EOSEX, if end of system exclusive - * 0xf8 - 0xff, if single byte real time message - * - * Global variables: - * USBFS_MIDI2_Event: RX status structure used to parse received - * data. - * - *******************************************************************************/ - uint8 USBFS_MIDI2_GetEvent(void) - { - uint8 msgRtn = 0u; - uint8 rxData; - #if (MIDI2_UART_RXBUFFERSIZE >= 256u) - uint16 rxBufferRead; - #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */ - uint16 rxBufferWrite; - #endif /* end CY_PSOC3 */ - #else - uint8 rxBufferRead; - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ - uint8 rxBufferLoopDetect; - /* Read buffer loop condition to the local variable */ - rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; - - if ( (MIDI2_UART_rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) - { - /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI2_UART_RX_VECT_NUM); - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ - rxBufferRead = MIDI2_UART_rxBufferRead; - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - rxBufferWrite = MIDI2_UART_rxBufferWrite; - CyIntEnable(MIDI2_UART_RX_VECT_NUM); - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ - - /* Stay here until either the buffer is empty or we have a complete message - * in the message buffer. Note that we must use a temporary output pointer to - * since it takes two instructions to increment with a wrap, and we can't - * risk doing that with the real pointer and getting an interrupt in between - * instructions. - */ - - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) - #else - while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */ - { - rxData = MIDI2_UART_rxBuffer[rxBufferRead]; - rxBufferRead++; - if(rxBufferRead >= MIDI2_UART_RXBUFFERSIZE) - { - rxBufferRead = 0u; - } - /* If loop condition was set - update real read buffer pointer - * to avoid overflow status - */ - if(rxBufferLoopDetect != 0u ) - { - MIDI2_UART_rxBufferLoopDetect = 0u; - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI2_UART_RX_VECT_NUM); - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ - MIDI2_UART_rxBufferRead = rxBufferRead; - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI2_UART_RX_VECT_NUM); - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ - } - - msgRtn = USBFS_ProcessMidiIn(rxData, - (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI2_Event); - - /* Read buffer loop condition to the local variable */ - rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; - } - - /* Finally, update the real output pointer, then return with - * an indication as to whether there's a complete message in the buffer. - */ - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI2_UART_RX_VECT_NUM); - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ - MIDI2_UART_rxBufferRead = rxBufferRead; - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI2_UART_RX_VECT_NUM); - #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */ - } - - return (msgRtn); - } - - - /******************************************************************************* - * Function Name: USBFS_MIDI2_ProcessUsbOut - ******************************************************************************** - * - * Summary: - * Process a USB MIDI output event. - * Puts data into the MIDI TX output buffer. - * - * Parameters: - * *epBuf: pointer on MIDI event. - * - * Return: - * None - * - * Global variables: - * USBFS_MIDI2_TxRunStat: This variable used to save the MIDI - * status byte and skip to send the repeated status byte in subsequent event. - * USBFS_MIDI2_InqFlags: The following flags are set when SysEx - * message comes. - * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. - * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. - * This bit should be cleared by user when Identity Reply message generated. - * - *******************************************************************************/ - void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) - - { - uint8 cmd; - uint8 len; - uint8 i; - - /* User code is required at the beginning of the procedure */ - /* `#START MIDI2_PROCESS_OUT_START` */ - - /* `#END` */ - - cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; - if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) - { - len = USBFS_MIDI_SIZE[cmd]; - i = USBFS_EVENT_BYTE1; - /* Universal System Exclusive message parsing */ - if(cmd == USBFS_SYSEX) - { - if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && - (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) - { /* SySEx starts */ - USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG; - } - else - { - USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - } - } - else if(cmd == USBFS_SYSEX_ENDS_WITH1) - { - USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - } - else if(cmd == USBFS_SYSEX_ENDS_WITH2) - { - USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - } - else if(cmd == USBFS_SYSEX_ENDS_WITH3) - { - /* Identify Request support */ - if((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) - { - USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && - (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) - { /* Set the flag about received the Identity Request. - * The Identity Reply message may be send by user code. - */ - USBFS_MIDI2_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; - } - } - } - else /* Do nothing for other command */ - { - } - /* Running Status for Voice and Mode messages only. */ - if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) - { - if(USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) - { /* Skip the repeated Status byte */ - i++; - } - else - { /* Save Status byte for next event */ - USBFS_MIDI2_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; - } - } - else - { /* Clear Running Status */ - USBFS_MIDI2_TxRunStat = 0u; - } - /* Puts data into the MIDI TX output buffer.*/ - do - { - MIDI2_UART_PutChar(epBuf[i]); - i++; - } while (i <= len); - } - - /* User code is required at the end of the procedure */ - /* `#START MIDI2_PROCESS_OUT_END` */ - - /* `#END` */ - } -#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - -#endif /* End (USBFS_ENABLE_MIDI_API != 0u) */ - - -/* `#START MIDI_FUNCTIONS` Place any additional functions here */ - -/* `#END` */ - -#endif /* End defined(USBFS_ENABLE_MIDI_STREAMING) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_midi.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_midi.h deleted file mode 100755 index 5a72034..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_midi.h +++ /dev/null @@ -1,200 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_midi.h -* Version 2.60 -* -* Description: -* Header File for the USBFS MIDI module. -* Contains prototypes and constant values. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_USBFS_USBFS_midi_H) -#define CY_USBFS_USBFS_midi_H - -#include "cytypes.h" -#include "USBFS.h" - - -/*************************************** -* Data Struct Definition -***************************************/ - -/* The following structure is used to hold status information for - building and parsing incoming MIDI messages. */ -typedef struct -{ - uint8 length; /* expected length */ - uint8 count; /* current byte count */ - uint8 size; /* complete size */ - uint8 runstat; /* running status */ - uint8 msgBuff[4]; /* message buffer */ -} USBFS_MIDI_RX_STATUS; - - -/*************************************** -* MIDI Constants. -***************************************/ - -#define USBFS_ONE_EXT_INTRF (0x01u) -#define USBFS_TWO_EXT_INTRF (0x02u) - -/* Flag definitions for use with MIDI device inquiry */ -#define USBFS_INQ_SYSEX_FLAG (0x01u) -#define USBFS_INQ_IDENTITY_REQ_FLAG (0x02u) - -/* USB-MIDI Code Index Number Classifications (MIDI Table 4-1) */ -#define USBFS_CIN_MASK (0x0Fu) -#define USBFS_RESERVED0 (0x00u) -#define USBFS_RESERVED1 (0x01u) -#define USBFS_2BYTE_COMMON (0x02u) -#define USBFS_3BYTE_COMMON (0x03u) -#define USBFS_SYSEX (0x04u) -#define USBFS_1BYTE_COMMON (0x05u) -#define USBFS_SYSEX_ENDS_WITH1 (0x05u) -#define USBFS_SYSEX_ENDS_WITH2 (0x06u) -#define USBFS_SYSEX_ENDS_WITH3 (0x07u) -#define USBFS_NOTE_OFF (0x08u) -#define USBFS_NOTE_ON (0x09u) -#define USBFS_POLY_KEY_PRESSURE (0x0Au) -#define USBFS_CONTROL_CHANGE (0x0Bu) -#define USBFS_PROGRAM_CHANGE (0x0Cu) -#define USBFS_CHANNEL_PRESSURE (0x0Du) -#define USBFS_PITCH_BEND_CHANGE (0x0Eu) -#define USBFS_SINGLE_BYTE (0x0Fu) - -#define USBFS_CABLE_MASK (0xF0u) -#define USBFS_MIDI_CABLE_00 (0x00u) -#define USBFS_MIDI_CABLE_01 (0x10u) - -#define USBFS_EVENT_BYTE0 (0x00u) -#define USBFS_EVENT_BYTE1 (0x01u) -#define USBFS_EVENT_BYTE2 (0x02u) -#define USBFS_EVENT_BYTE3 (0x03u) -#define USBFS_EVENT_LENGTH (0x04u) - -#define USBFS_MIDI_STATUS_BYTE_MASK (0x80u) -#define USBFS_MIDI_STATUS_MASK (0xF0u) -#define USBFS_MIDI_SINGLE_BYTE_MASK (0x08u) -#define USBFS_MIDI_NOTE_OFF (0x80u) -#define USBFS_MIDI_NOTE_ON (0x90u) -#define USBFS_MIDI_POLY_KEY_PRESSURE (0xA0u) -#define USBFS_MIDI_CONTROL_CHANGE (0xB0u) -#define USBFS_MIDI_PROGRAM_CHANGE (0xC0u) -#define USBFS_MIDI_CHANNEL_PRESSURE (0xD0u) -#define USBFS_MIDI_PITCH_BEND_CHANGE (0xE0u) -#define USBFS_MIDI_SYSEX (0xF0u) -#define USBFS_MIDI_EOSEX (0xF7u) -#define USBFS_MIDI_QFM (0xF1u) -#define USBFS_MIDI_SPP (0xF2u) -#define USBFS_MIDI_SONGSEL (0xF3u) -#define USBFS_MIDI_TUNEREQ (0xF6u) -#define USBFS_MIDI_ACTIVESENSE (0xFEu) - -/* MIDI Universal System Exclusive defines */ -#define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu) -#define USBFS_MIDI_SYSEX_REALTIME (0x7Fu) -/* ID of target device */ -#define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu) -/* Sub-ID#1*/ -#define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u) -#define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u) -/* Sub-ID#2*/ -#define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u) -#define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u) -#define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u) -#define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u) - -#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u) -#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u) - -#define USBFS_ISR_SERVICE_MIDI_OUT \ - ( (USBFS_ENABLE_MIDI_API != 0u) && \ - (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) ) -#define USBFS_ISR_SERVICE_MIDI_IN \ - ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) ) - -/*************************************** -* External function references -***************************************/ - -void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg) - ; - - -/*************************************** -* External references -***************************************/ - -#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - #include "MIDI1_UART.h" -#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ -#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - #include "MIDI2_UART.h" -#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - #include -#endif /* End USBFS_EP_MM */ - - -/*************************************** -* Private function prototypes -***************************************/ - -void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) - ; -#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - void USBFS_MIDI_Init(void) ; - uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) - ; - uint8 USBFS_MIDI1_GetEvent(void) ; - void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) - ; - - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - uint8 USBFS_MIDI2_GetEvent(void) ; - void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) - ; - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - - -/*************************************** -* External data references -***************************************/ - -#if defined(USBFS_ENABLE_MIDI_STREAMING) - -#if (USBFS_MIDI_IN_BUFF_SIZE > 0) - #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) - extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ - #else - extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ - #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */ - extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ - extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ -#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ - -#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ - extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ -#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ - -#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ - #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - -#endif /* USBFS_ENABLE_MIDI_STREAMING */ - - -#endif /* End CY_USBFS_USBFS_midi_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_pm.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_pm.c deleted file mode 100755 index 00c88f6..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_pm.c +++ /dev/null @@ -1,277 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_pm.c -* Version 2.60 -* -* Description: -* This file provides Suspend/Resume APIs functionality. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "project.h" -#include "USBFS.h" -#include "USBFS_pvt.h" - - -/*************************************** -* Custom Declarations -***************************************/ -/* `#START PM_CUSTOM_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -/*************************************** -* Local data allocation -***************************************/ - -static USBFS_BACKUP_STRUCT USBFS_backup; - - -#if(USBFS_DP_ISR_REMOVE == 0u) - - - /******************************************************************************* - * Function Name: USBFS_DP_Interrupt - ******************************************************************************** - * - * Summary: - * This Interrupt Service Routine handles DP pin changes for wake-up from - * the sleep mode. - * - * Parameters: - * None. - * - * Return: - * None. - * - *******************************************************************************/ - CY_ISR(USBFS_DP_ISR) - { - /* `#START DP_USER_CODE` Place your code here */ - - /* `#END` */ - - /* Clears active interrupt */ - CY_GET_REG8(USBFS_DP_INTSTAT_PTR); - } - -#endif /* (USBFS_DP_ISR_REMOVE == 0u) */ - - -/******************************************************************************* -* Function Name: USBFS_SaveConfig -******************************************************************************** -* -* Summary: -* Saves the current user configuration. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_SaveConfig(void) -{ - -} - - -/******************************************************************************* -* Function Name: USBFS_RestoreConfig -******************************************************************************** -* -* Summary: -* Restores the current user configuration. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_RestoreConfig(void) -{ - if(USBFS_configuration != 0u) - { - USBFS_ConfigReg(); - } -} - - -/******************************************************************************* -* Function Name: USBFS_Suspend -******************************************************************************** -* -* Summary: -* This function disables the USBFS block and prepares for power donwn mode. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_backup.enable: modified. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_Suspend(void) -{ - uint8 enableInterrupts; - enableInterrupts = CyEnterCriticalSection(); - - if((CY_GET_REG8(USBFS_CR0_PTR) & USBFS_CR0_ENABLE) != 0u) - { /* USB block is enabled */ - USBFS_backup.enableState = 1u; - - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ - USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN; - CyDelayUs(0u); /*~50ns delay */ - - /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */ - USBFS_PM_USB_CR0_REG &= - (uint8)~(USBFS_PM_USB_CR0_PD_N | USBFS_PM_USB_CR0_PD_PULLUP_N); - - /* Disable the SIE */ - USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE; - - CyDelayUs(0u); /*~50ns delay */ - /* Store mode and Disable VRegulator*/ - USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE; - USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE; - - CyDelayUs(1u); /* 0.5 us min delay */ - /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ - USBFS_PM_USB_CR0_REG &= (uint8)~USBFS_PM_USB_CR0_REF_EN; - - /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/ - USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE; - - /* Disable USB in ACT PM */ - USBFS_PM_ACT_CFG_REG &= (uint8)~USBFS_PM_ACT_EN_FSUSB; - /* Disable USB block for Standby Power Mode */ - USBFS_PM_STBY_CFG_REG &= (uint8)~USBFS_PM_STBY_EN_FSUSB; - CyDelayUs(1u); /* min 0.5us delay required */ - - } - else - { - USBFS_backup.enableState = 0u; - } - CyExitCriticalSection(enableInterrupts); - - /* Set the DP Interrupt for wake-up from sleep mode. */ - #if(USBFS_DP_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); - CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR); - CyIntClearPending(USBFS_DP_INTC_VECT_NUM); - CyIntEnable(USBFS_DP_INTC_VECT_NUM); - #endif /* (USBFS_DP_ISR_REMOVE == 0u) */ - -} - - -/******************************************************************************* -* Function Name: USBFS_Resume -******************************************************************************** -* -* Summary: -* This function enables the USBFS block after power down mode. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_backup - checked. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_Resume(void) -{ - uint8 enableInterrupts; - enableInterrupts = CyEnterCriticalSection(); - - if(USBFS_backup.enableState != 0u) - { - #if(USBFS_DP_ISR_REMOVE == 0u) - CyIntDisable(USBFS_DP_INTC_VECT_NUM); - #endif /* End USBFS_DP_ISR_REMOVE */ - - /* Enable USB block */ - USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; - /* Enable USB block for Standby Power Mode */ - USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; - /* Enable core clock */ - USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE; - - /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ - USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; - /* The reference will be available ~40us after power restored */ - CyDelayUs(40u); - /* Return VRegulator*/ - USBFS_CR1_REG |= USBFS_backup.mode; - CyDelayUs(0u); /*~50ns delay */ - /* Enable USBIO */ - USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; - CyDelayUs(2u); - /* Set the USBIO pull-up enable */ - USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; - - /* Reinit Arbiter configuration for DMA transfers */ - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - /* usb arb interrupt enable */ - USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; - #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /*Set cfg cmplt this rises DMA request when the full configuration is done */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - /* STALL_IN_OUT */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - /* Enable the SIE with a last address */ - USBFS_CR0_REG |= USBFS_CR0_ENABLE; - CyDelayCycles(1u); - /* Finally, Enable d+ pullup and select iomode to USB mode*/ - CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); - - /* Restore USB register settings */ - USBFS_RestoreConfig(); - - } - CyExitCriticalSection(enableInterrupts); -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_pvt.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_pvt.h deleted file mode 100755 index 499fe26..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_pvt.h +++ /dev/null @@ -1,203 +0,0 @@ -/******************************************************************************* -* File Name: .h -* Version 2.60 -* -* Description: -* This private file provides constants and parameter values for the -* USBFS Component. -* Please do not use this file or its content in your project. -* -* Note: -* -******************************************************************************** -* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_USBFS_USBFS_pvt_H) -#define CY_USBFS_USBFS_pvt_H - - -/*************************************** -* Private Variables -***************************************/ - -/* Generated external references for descriptors*/ -extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u]; -extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u]; -extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u]; -extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u]; -extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u]; -extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u]; -extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u]; -extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u]; -extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10]; -extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[83u]; -extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; -extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ - USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; -extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; -extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ - USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; -extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u]; -extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u]; -extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u]; -extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u]; - - -extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH]; -extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH]; -#if defined(USBFS_ENABLE_IDSN_STRING) - extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; -#endif /* USBFS_ENABLE_IDSN_STRING */ - -extern volatile uint8 USBFS_interfaceNumber; -extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; -extern volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; -extern volatile uint8 USBFS_deviceAddress; -extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; -extern const uint8 CYCODE *USBFS_interfaceClass; - -extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; -extern volatile T_USBFS_TD USBFS_currentTD; - -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; - extern uint8 USBFS_DmaTd[USBFS_MAX_EP]; -#endif /* End USBFS_EP_MM */ - -extern volatile uint8 USBFS_ep0Toggle; -extern volatile uint8 USBFS_lastPacketSize; -extern volatile uint8 USBFS_ep0Mode; -extern volatile uint8 USBFS_ep0Count; -extern volatile uint16 USBFS_transferByteCount; - - -/*************************************** -* Private Function Prototypes -***************************************/ -void USBFS_ReInitComponent(void) ; -void USBFS_HandleSetup(void) ; -void USBFS_HandleIN(void) ; -void USBFS_HandleOUT(void) ; -void USBFS_LoadEP0(void) ; -uint8 USBFS_InitControlRead(void) ; -uint8 USBFS_InitControlWrite(void) ; -void USBFS_ControlReadDataStage(void) ; -void USBFS_ControlReadStatusStage(void) ; -void USBFS_ControlReadPrematureStatus(void) - ; -uint8 USBFS_InitControlWrite(void) ; -uint8 USBFS_InitZeroLengthControlTransfer(void) - ; -void USBFS_ControlWriteDataStage(void) ; -void USBFS_ControlWriteStatusStage(void) ; -void USBFS_ControlWritePrematureStatus(void) - ; -uint8 USBFS_InitNoDataControlTransfer(void) ; -void USBFS_NoDataControlStatusStage(void) ; -void USBFS_InitializeStatusBlock(void) ; -void USBFS_UpdateStatusBlock(uint8 completionCode) ; -uint8 USBFS_DispatchClassRqst(void) ; - -void USBFS_Config(uint8 clearAltSetting) ; -void USBFS_ConfigAltChanged(void) ; -void USBFS_ConfigReg(void) ; - -const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c) - ; -const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) - ; -const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) - ; -uint8 USBFS_ClearEndpointHalt(void) ; -uint8 USBFS_SetEndpointHalt(void) ; -uint8 USBFS_ValidateAlternateSetting(void) ; - -void USBFS_SaveConfig(void) ; -void USBFS_RestoreConfig(void) ; - -#if defined(USBFS_ENABLE_IDSN_STRING) - void USBFS_ReadDieID(uint8 descr[]) ; -#endif /* USBFS_ENABLE_IDSN_STRING */ - -#if defined(USBFS_ENABLE_HID_CLASS) - uint8 USBFS_DispatchHIDClassRqst(void); -#endif /* End USBFS_ENABLE_HID_CLASS */ -#if defined(USBFS_ENABLE_AUDIO_CLASS) - uint8 USBFS_DispatchAUDIOClassRqst(void); -#endif /* End USBFS_ENABLE_HID_CLASS */ -#if defined(USBFS_ENABLE_CDC_CLASS) - uint8 USBFS_DispatchCDCClassRqst(void); -#endif /* End USBFS_ENABLE_CDC_CLASS */ - -CY_ISR_PROTO(USBFS_EP_0_ISR); -#if(USBFS_EP1_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_1_ISR); -#endif /* End USBFS_EP1_ISR_REMOVE */ -#if(USBFS_EP2_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_2_ISR); -#endif /* End USBFS_EP2_ISR_REMOVE */ -#if(USBFS_EP3_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_3_ISR); -#endif /* End USBFS_EP3_ISR_REMOVE */ -#if(USBFS_EP4_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_4_ISR); -#endif /* End USBFS_EP4_ISR_REMOVE */ -#if(USBFS_EP5_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_5_ISR); -#endif /* End USBFS_EP5_ISR_REMOVE */ -#if(USBFS_EP6_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_6_ISR); -#endif /* End USBFS_EP6_ISR_REMOVE */ -#if(USBFS_EP7_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_7_ISR); -#endif /* End USBFS_EP7_ISR_REMOVE */ -#if(USBFS_EP8_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_8_ISR); -#endif /* End USBFS_EP8_ISR_REMOVE */ -CY_ISR_PROTO(USBFS_BUS_RESET_ISR); -#if(USBFS_SOF_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_SOF_ISR); -#endif /* End USBFS_SOF_ISR_REMOVE */ -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - CY_ISR_PROTO(USBFS_ARB_ISR); -#endif /* End USBFS_EP_MM */ -#if(USBFS_DP_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_DP_ISR); -#endif /* End USBFS_DP_ISR_REMOVE */ - - -/*************************************** -* Request Handlers -***************************************/ - -uint8 USBFS_HandleStandardRqst(void) ; -uint8 USBFS_DispatchClassRqst(void) ; -uint8 USBFS_HandleVendorRqst(void) ; - - -/*************************************** -* HID Internal references -***************************************/ -#if defined(USBFS_ENABLE_HID_CLASS) - void USBFS_FindReport(void) ; - void USBFS_FindReportDescriptor(void) ; - void USBFS_FindHidClassDecriptor(void) ; -#endif /* USBFS_ENABLE_HID_CLASS */ - - -/*************************************** -* MIDI Internal references -***************************************/ -#if defined(USBFS_ENABLE_MIDI_STREAMING) - void USBFS_MIDI_IN_EP_Service(void) ; -#endif /* USBFS_ENABLE_MIDI_STREAMING */ - - -#endif /* CY_USBFS_USBFS_pvt_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_std.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_std.c deleted file mode 100755 index 18f0364..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_std.c +++ /dev/null @@ -1,1134 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_std.c -* Version 2.60 -* -* Description: -* USB Standard request handler. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" -#include "USBFS_cdc.h" -#include "USBFS_pvt.h" -#if defined(USBFS_ENABLE_MIDI_STREAMING) - #include "USBFS_midi.h" -#endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - - -/*************************************** -* Static data allocation -***************************************/ - -#if defined(USBFS_ENABLE_FWSN_STRING) - static volatile uint8 *USBFS_fwSerialNumberStringDescriptor; - static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; -#endif /* USBFS_ENABLE_FWSN_STRING */ - -#if defined(USBFS_ENABLE_FWSN_STRING) - - - /******************************************************************************* - * Function Name: USBFS_SerialNumString - ******************************************************************************** - * - * Summary: - * Application firmware may supply the source of the USB device descriptors - * serial number string during runtime. - * - * Parameters: - * snString: pointer to string. - * - * Return: - * None. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_SerialNumString(uint8 snString[]) - { - USBFS_snStringConfirm = USBFS_FALSE; - if(snString != NULL) - { - USBFS_fwSerialNumberStringDescriptor = snString; - /* Check descriptor validation */ - if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) ) - { - USBFS_snStringConfirm = USBFS_TRUE; - } - } - } - -#endif /* USBFS_ENABLE_FWSN_STRING */ - - -/******************************************************************************* -* Function Name: USBFS_HandleStandardRqst -******************************************************************************** -* -* Summary: -* This Routine dispatches standard requests -* -* Parameters: -* None. -* -* Return: -* TRUE if request handled. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_HandleStandardRqst(void) -{ - uint8 requestHandled = USBFS_FALSE; - uint8 interfaceNumber; - #if defined(USBFS_ENABLE_STRINGS) - volatile uint8 *pStr = 0u; - #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) - uint8 nStr; - uint8 descrLength; - #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ - #endif /* USBFS_ENABLE_STRINGS */ - static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; - const T_USBFS_LUT CYCODE *pTmp; - USBFS_currentTD.count = 0u; - - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - { - /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_GET_DESCRIPTOR: - if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE) - { - pTmp = USBFS_GetDeviceTablePtr(); - USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; - requestHandled = USBFS_InitControlRead(); - } - else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG) - { - pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo)); - USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ - USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ - (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; - requestHandled = USBFS_InitControlRead(); - } - #if defined(USBFS_ENABLE_STRINGS) - else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING) - { - /* Descriptor Strings*/ - #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) - nStr = 0u; - pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u]; - while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) - { - /* Read descriptor length from 1st byte */ - descrLength = *pStr; - /* Move to next string descriptor */ - pStr = &pStr[descrLength]; - nStr++; - } - #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */ - /* Microsoft OS String*/ - #if defined(USBFS_ENABLE_MSOS_STRING) - if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS ) - { - pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u]; - } - #endif /* End USBFS_ENABLE_MSOS_STRING*/ - /* SN string */ - #if defined(USBFS_ENABLE_SN_STRING) - if( (CY_GET_REG8(USBFS_wValueLo) != 0u) && - (CY_GET_REG8(USBFS_wValueLo) == - USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) ) - { - pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; - #if defined(USBFS_ENABLE_FWSN_STRING) - if(USBFS_snStringConfirm != USBFS_FALSE) - { - pStr = USBFS_fwSerialNumberStringDescriptor; - } - #endif /* USBFS_ENABLE_FWSN_STRING */ - #if defined(USBFS_ENABLE_IDSN_STRING) - /* Read DIE ID and generate string descriptor in RAM */ - USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); - pStr = USBFS_idSerialNumberStringDescriptor; - #endif /* End USBFS_ENABLE_IDSN_STRING */ - } - #endif /* End USBFS_ENABLE_SN_STRING */ - if (*pStr != 0u) - { - USBFS_currentTD.count = *pStr; - USBFS_currentTD.pData = pStr; - requestHandled = USBFS_InitControlRead(); - } - } - #endif /* End USBFS_ENABLE_STRINGS */ - else - { - requestHandled = USBFS_DispatchClassRqst(); - } - break; - case USBFS_GET_STATUS: - switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)) - { - case USBFS_RQST_RCPT_EP: - USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; - USBFS_tBuffer[0u] = USBFS_EP[ \ - CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; - USBFS_tBuffer[1u] = 0u; - USBFS_currentTD.pData = &USBFS_tBuffer[0u]; - requestHandled = USBFS_InitControlRead(); - break; - case USBFS_RQST_RCPT_DEV: - USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; - USBFS_tBuffer[0u] = USBFS_deviceStatus; - USBFS_tBuffer[1u] = 0u; - USBFS_currentTD.pData = &USBFS_tBuffer[0u]; - requestHandled = USBFS_InitControlRead(); - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - break; - case USBFS_GET_CONFIGURATION: - USBFS_currentTD.count = 1u; - USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration; - requestHandled = USBFS_InitControlRead(); - break; - case USBFS_GET_INTERFACE: - USBFS_currentTD.count = 1u; - USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \ - CY_GET_REG8(USBFS_wIndexLo)]; - requestHandled = USBFS_InitControlRead(); - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - } - else { - /* Control Write */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_SET_ADDRESS: - USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo); - requestHandled = USBFS_InitNoDataControlTransfer(); - break; - case USBFS_SET_CONFIGURATION: - USBFS_configuration = CY_GET_REG8(USBFS_wValueLo); - USBFS_configurationChanged = USBFS_TRUE; - USBFS_Config(USBFS_TRUE); - requestHandled = USBFS_InitNoDataControlTransfer(); - break; - case USBFS_SET_INTERFACE: - if (USBFS_ValidateAlternateSetting() != 0u) - { - interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - USBFS_interfaceNumber = interfaceNumber; - USBFS_configurationChanged = USBFS_TRUE; - #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ - (USBFS_EP_MM == USBFS__EP_MANUAL) ) - USBFS_Config(USBFS_FALSE); - #else - USBFS_ConfigAltChanged(); - #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ - /* Update handled Alt setting changes status */ - USBFS_interfaceSetting_last[interfaceNumber] = - USBFS_interfaceSetting[interfaceNumber]; - requestHandled = USBFS_InitNoDataControlTransfer(); - } - break; - case USBFS_CLEAR_FEATURE: - switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - { - case USBFS_RQST_RCPT_EP: - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) - { - requestHandled = USBFS_ClearEndpointHalt(); - } - break; - case USBFS_RQST_RCPT_DEV: - /* Clear device REMOTE_WAKEUP */ - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) - { - USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; - requestHandled = USBFS_InitNoDataControlTransfer(); - } - break; - case USBFS_RQST_RCPT_IFC: - /* Validate interfaceNumber */ - if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) - { - USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - (uint8)~(CY_GET_REG8(USBFS_wValueLo)); - requestHandled = USBFS_InitNoDataControlTransfer(); - } - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - break; - case USBFS_SET_FEATURE: - switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) - { - case USBFS_RQST_RCPT_EP: - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) - { - requestHandled = USBFS_SetEndpointHalt(); - } - break; - case USBFS_RQST_RCPT_DEV: - /* Set device REMOTE_WAKEUP */ - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) - { - USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; - requestHandled = USBFS_InitNoDataControlTransfer(); - } - break; - case USBFS_RQST_RCPT_IFC: - /* Validate interfaceNumber */ - if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) - { - USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - (uint8)~(CY_GET_REG8(USBFS_wValueLo)); - requestHandled = USBFS_InitNoDataControlTransfer(); - } - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - break; - default: /* requestHandled is initialized as FALSE by default */ - break; - } - } - return(requestHandled); -} - - -#if defined(USBFS_ENABLE_IDSN_STRING) - - /*************************************************************************** - * Function Name: USBFS_ReadDieID - **************************************************************************** - * - * Summary: - * This routine read Die ID and generate Serial Number string descriptor. - * - * Parameters: - * descr: pointer on string descriptor. - * - * Return: - * None. - * - * Reentrant: - * No. - * - ***************************************************************************/ - void USBFS_ReadDieID(uint8 descr[]) - { - uint8 i; - uint8 j = 0u; - uint8 value; - const char8 CYCODE hex[16u] = "0123456789ABCDEF"; - - - /* Check descriptor validation */ - if( descr != NULL) - { - descr[0u] = USBFS_IDSN_DESCR_LENGTH; - descr[1u] = USBFS_DESCR_STRING; - - /* fill descriptor */ - for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) - { - value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j)); - j++; - descr[i] = (uint8)hex[value >> 4u]; - descr[i + 2u] = (uint8)hex[value & 0x0Fu]; - } - } - } - -#endif /* End USBFS_ENABLE_IDSN_STRING */ - - -/******************************************************************************* -* Function Name: USBFS_ConfigReg -******************************************************************************** -* -* Summary: -* This routine configures hardware registers from the variables. -* It is called from USBFS_Config() function and from RestoreConfig -* after Wakeup. -* -* Parameters: -* None. -* -* Return: -* None. -* -*******************************************************************************/ -void USBFS_ConfigReg(void) -{ - uint8 ep; - uint8 i; - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - uint8 ep_type = 0u; - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - - /* Set the endpoint buffer addresses */ - ep = USBFS_EP1; - for (i = 0u; i < 0x80u; i+= 0x10u) - { - CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS | - USBFS_ARB_EPX_CFG_RESET); - - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */ - CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK); - #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */ - - if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) - { - if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u ) - { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN); - } - else - { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT); - /* Prepare EP type mask for automatic memory allocation */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - ep_type |= (uint8)(0x01u << (ep - USBFS_EP1)); - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - } - } - else - { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP); - } - - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u); - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu); - - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - ep++; - } - - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ - USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; - USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */ - USBFS_DMA_THRES_MSB_REG = 0u; - USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK; - USBFS_EP_TYPE_REG = ep_type; - /* Cfg_cmp bit set to 1 once configuration is complete. */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM | - USBFS_ARB_CFG_CFG_CPM; - /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - - CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu); -} - - -/******************************************************************************* -* Function Name: USBFS_Config -******************************************************************************** -* -* Summary: -* This routine configures endpoints for the entire configuration by scanning -* the configuration descriptor. -* -* Parameters: -* clearAltSetting: It configures the bAlternateSetting 0 for each interface. -* -* Return: -* None. -* -* USBFS_interfaceClass - Initialized class array for each interface. -* It is used for handling Class specific requests depend on interface class. -* Different classes in multiple Alternate settings does not supported. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_Config(uint8 clearAltSetting) -{ - uint8 ep; - uint8 cur_ep; - uint8 i; - uint8 ep_type; - const uint8 *pDescr; - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - uint16 buffCount = 0u; - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - const T_USBFS_LUT CYCODE *pTmp; - const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; - - /* Clear all of the endpoints */ - for (ep = 0u; ep < USBFS_MAX_EP; ep++) - { - USBFS_EP[ep].attrib = 0u; - USBFS_EP[ep].hwEpState = 0u; - USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[ep].epToggle = 0u; - USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; - USBFS_EP[ep].bufferSize = 0u; - USBFS_EP[ep].interface = 0u; - - } - - /* Clear Alternate settings for all interfaces */ - if(clearAltSetting != 0u) - { - for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - { - USBFS_interfaceSetting[i] = 0x00u; - USBFS_interfaceSetting_last[i] = 0x00u; - } - } - - /* Init Endpoints and Device Status if configured */ - if(USBFS_configuration > 0u) - { - pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - /* Set Power status for current configuration */ - pDescr = (const uint8 *)pTmp->p_list; - if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) - { - USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; - } - else - { - USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; - } - /* Move to next element */ - pTmp = &pTmp[1u]; - ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - - #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ - (USBFS_EP_MM == USBFS__EP_MANUAL) ) - /* Configure for dynamic EP memory allocation */ - /* p_list points the endpoint setting table. */ - pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; - for (i = 0u; i < ep; i++) - { - /* Compare current Alternate setting with EP Alt*/ - if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) - { - cur_ep = pEP->addr & USBFS_DIR_UNUSED; - ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - if (pEP->addr & USBFS_DIR_IN) - { - /* IN Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (ep_type != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_in_ep = cur_ep; - } - #endif /* End USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_IN_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (ep_type == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_in_ep = cur_ep; - } - #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - } - else - { - /* OUT Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (ep_type != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_out_ep = cur_ep; - } - #endif /* End USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (ep_type == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_out_ep = cur_ep; - } - #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - } - USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - USBFS_EP[cur_ep].addr = pEP->addr; - USBFS_EP[cur_ep].attrib = pEP->attributes; - } - pEP = &pEP[1u]; - } - #else /* Config for static EP memory allocation */ - for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) - { - /* p_list points the endpoint setting table. */ - pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; - /* Find max length for each EP and select it (length could be different in different Alt settings) */ - /* but other settings should be correct with regards to Interface alt Setting */ - for (cur_ep = 0u; cur_ep < ep; cur_ep++) - { - /* EP count is equal to EP # in table and we found larger EP length than have before*/ - if(i == (pEP->addr & USBFS_DIR_UNUSED)) - { - if(USBFS_EP[i].bufferSize < pEP->bufferSize) - { - USBFS_EP[i].bufferSize = pEP->bufferSize; - } - /* Compare current Alternate setting with EP Alt*/ - if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) - { - ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - if ((pEP->addr & USBFS_DIR_IN) != 0u) - { - /* IN Endpoint */ - USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; - USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - /* Find and init CDC IN endpoint number */ - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (ep_type != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_in_ep = i; - } - #endif /* End USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_IN_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (ep_type == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_in_ep = i; - } - #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - } - else - { - /* OUT Endpoint */ - USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - /* Find and init CDC IN endpoint number */ - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (ep_type != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_out_ep = i; - } - #endif /* End USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (ep_type == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_out_ep = i; - } - #endif /* End USBFS_ENABLE_MIDI_STREAMING*/ - } - USBFS_EP[i].addr = pEP->addr; - USBFS_EP[i].attrib = pEP->attributes; - - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - break; /* use first EP setting in Auto memory managment */ - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - } - } - pEP = &pEP[1u]; - } - } - #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ - - /* Init class array for each interface and interface number for each EP. - * It is used for handling Class specific requests directed to either an - * interface or the endpoint. - */ - /* p_list points the endpoint setting table. */ - pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; - for (i = 0u; i < ep; i++) - { - /* Configure interface number for each EP*/ - USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; - pEP = &pEP[1u]; - } - /* Init pointer on interface class table*/ - USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); - /* Set the endpoint buffer addresses */ - - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) - { - USBFS_EP[ep].buffOffset = buffCount; - buffCount += USBFS_EP[ep].bufferSize; - } - #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - /* Configure hardware registers */ - USBFS_ConfigReg(); - } /* USBFS_configuration > 0 */ -} - - -/******************************************************************************* -* Function Name: USBFS_ConfigAltChanged -******************************************************************************** -* -* Summary: -* This routine update configuration for the required endpoints only. -* It is called after SET_INTERFACE request when Static memory allocation used. -* -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_ConfigAltChanged(void) -{ - uint8 ep; - uint8 cur_ep; - uint8 i; - uint8 ep_type; - uint8 ri; - - const T_USBFS_LUT CYCODE *pTmp; - const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; - - - /* Init Endpoints and Device Status if configured */ - if(USBFS_configuration > 0u) - { - pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - pTmp = &pTmp[1u]; - ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - - /* Do not touch EP which doesn't need reconfiguration */ - /* When Alt setting changed, the only required endpoints need to be reconfigured */ - /* p_list points the endpoint setting table. */ - pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; - for (i = 0u; i < ep; i++) - { - /*If Alt setting changed and new is same with EP Alt */ - if((USBFS_interfaceSetting[pEP->interface] != - USBFS_interfaceSetting_last[pEP->interface] ) && - (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && - (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) - { - cur_ep = pEP->addr & USBFS_DIR_UNUSED; - ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - ep_type = pEP->attributes & USBFS_EP_TYPE_MASK; - if ((pEP->addr & USBFS_DIR_IN) != 0u) - { - /* IN Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - } - else - { - /* OUT Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - } - /* Change the SIE mode for the selected EP to NAK ALL */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); - USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - USBFS_EP[cur_ep].addr = pEP->addr; - USBFS_EP[cur_ep].attrib = pEP->attributes; - - /* Clear the data toggle */ - USBFS_EP[cur_ep].epToggle = 0u; - - /* Dynamic reconfiguration for mode 3 transfer */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* In_data_rdy for selected EP should be set to 0 */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; - - /* write the EP number for which reconfiguration is required */ - USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) << - USBFS_DYN_RECONFIG_EP_SHIFT; - /* Set the dyn_config_en bit in dynamic reconfiguration register */ - USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; - /* wait for the dyn_config_rdy bit to set by the block, - * this bit will be set to 1 when block is ready for reconfiguration. - */ - while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u) - { - ; - } - /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */ - /* Change EP Type with new direction */ - if((pEP->addr & USBFS_DIR_IN) == 0u) - { - USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1)); - } - else - { - USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1)); - } - /* dynamic reconfiguration enable bit cleared, pointers and control/status - * signals for the selected EP is cleared/re-initialized on negative edge - * of dynamic reconfiguration enable bit). - */ - USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE; - /* The main loop has to re-enable DMA and OUT endpoint*/ - #else - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), - USBFS_EP[cur_ep].bufferSize >> 8u); - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), - USBFS_EP[cur_ep].bufferSize & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri), - USBFS_EP[cur_ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri), - USBFS_EP[cur_ep].buffOffset >> 8u); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri), - USBFS_EP[cur_ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri), - USBFS_EP[cur_ep].buffOffset >> 8u); - #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */ - } - /* Get next EP element */ - pEP = &pEP[1u]; - } - } /* USBFS_configuration > 0 */ -} - - -/******************************************************************************* -* Function Name: USBFS_GetConfigTablePtr -******************************************************************************** -* -* Summary: -* This routine returns a pointer a configuration table entry -* -* Parameters: -* c: Configuration Index -* -* Return: -* Device Descriptor pointer. -* -*******************************************************************************/ -const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c) - -{ - /* Device Table */ - const T_USBFS_LUT CYCODE *pTmp; - - pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; - - /* The first entry points to the Device Descriptor, - * the rest configuration entries. - */ - return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list ); -} - - -/******************************************************************************* -* Function Name: USBFS_GetDeviceTablePtr -******************************************************************************** -* -* Summary: -* This routine returns a pointer to the Device table -* -* Parameters: -* None. -* -* Return: -* Device Table pointer -* -*******************************************************************************/ -const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) - -{ - /* Device Table */ - return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); -} - - -/******************************************************************************* -* Function Name: USB_GetInterfaceClassTablePtr -******************************************************************************** -* -* Summary: -* This routine returns Interface Class table pointer, which contains -* the relation between interface number and interface class. -* -* Parameters: -* None. -* -* Return: -* Interface Class table pointer. -* -*******************************************************************************/ -const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) - -{ - const T_USBFS_LUT CYCODE *pTmp; - uint8 currentInterfacesNum; - - pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; - /* Third entry in the LUT starts the Interface Table pointers */ - /* The INTERFACE_CLASS table is located after all interfaces */ - pTmp = &pTmp[currentInterfacesNum + 2u]; - return( (const uint8 CYCODE *) pTmp->p_list ); -} - - -/******************************************************************************* -* Function Name: USBFS_TerminateEP -******************************************************************************** -* -* Summary: -* This function terminates the specified USBFS endpoint. -* This function should be used before endpoint reconfiguration. -* -* Parameters: -* Endpoint number. -* -* Return: -* None. -* -* Reentrant: -* No. -* -*******************************************************************************/ -void USBFS_TerminateEP(uint8 ep) -{ - uint8 ri; - - ep &= USBFS_DIR_UNUSED; - ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - - if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) - { - /* Set the endpoint Halt */ - USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); - - /* Clear the data toggle */ - USBFS_EP[ep].epToggle = 0u; - USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED; - - if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - { - /* IN Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); - } - else - { - /* OUT Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); - } - } -} - - -/******************************************************************************* -* Function Name: USBFS_SetEndpointHalt -******************************************************************************** -* -* Summary: -* This routine handles set endpoint halt. -* -* Parameters: -* None. -* -* Return: -* requestHandled. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_SetEndpointHalt(void) -{ - uint8 ep; - uint8 ri; - uint8 requestHandled = USBFS_FALSE; - - /* Set endpoint halt */ - ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - - if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) - { - /* Set the endpoint Halt */ - USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); - - /* Clear the data toggle */ - USBFS_EP[ep].epToggle = 0u; - USBFS_EP[ep].apiEpState |= USBFS_NO_EVENT_ALLOWED; - - if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - { - /* IN Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | - USBFS_MODE_ACK_IN); - } - else - { - /* OUT Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | - USBFS_MODE_ACK_OUT); - } - requestHandled = USBFS_InitNoDataControlTransfer(); - } - - return(requestHandled); -} - - -/******************************************************************************* -* Function Name: USBFS_ClearEndpointHalt -******************************************************************************** -* -* Summary: -* This routine handles clear endpoint halt. -* -* Parameters: -* None. -* -* Return: -* requestHandled. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_ClearEndpointHalt(void) -{ - uint8 ep; - uint8 ri; - uint8 requestHandled = USBFS_FALSE; - - /* Clear endpoint halt */ - ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - - if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) - { - /* Clear the endpoint Halt */ - USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT); - - /* Clear the data toggle */ - USBFS_EP[ep].epToggle = 0u; - /* Clear toggle bit for already armed packet */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8( - (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE); - /* Return API State as it was defined before */ - USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED; - - if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - { - /* IN Endpoint */ - if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) - { /* Wait for next packet from application */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); - } - else /* Continue armed transfer */ - { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN); - } - } - else - { - /* OUT Endpoint */ - if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) - { /* Allow application to read full buffer */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); - } - else /* Mark endpoint as empty, so it will be reloaded */ - { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT); - } - } - requestHandled = USBFS_InitNoDataControlTransfer(); - } - - return(requestHandled); -} - - -/******************************************************************************* -* Function Name: USBFS_ValidateAlternateSetting -******************************************************************************** -* -* Summary: -* Validates (and records) a SET INTERFACE request. -* -* Parameters: -* None. -* -* Return: -* requestHandled. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_ValidateAlternateSetting(void) -{ - uint8 requestHandled = USBFS_TRUE; - uint8 interfaceNum; - const T_USBFS_LUT CYCODE *pTmp; - uint8 currentInterfacesNum; - - interfaceNum = CY_GET_REG8(USBFS_wIndexLo); - /* Validate interface setting, stall if invalid. */ - pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; - - if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER)) - { /* Wrong interface number */ - requestHandled = USBFS_FALSE; - } - else - { - /* Save current Alt setting to find out the difference in Config() function */ - USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; - USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo); - } - - return (requestHandled); -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_vnd.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_vnd.c deleted file mode 100755 index 15b68a5..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USBFS_vnd.c +++ /dev/null @@ -1,96 +0,0 @@ -/******************************************************************************* -* File Name: USBFS_vnd.c -* Version 2.60 -* -* Description: -* USB vendor request handler. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "USBFS.h" -#include "USBFS_pvt.h" - -#if(USBFS_EXTERN_VND == USBFS_FALSE) - - -/*************************************** -* Vendor Specific Declarations -***************************************/ - -/* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */ - -/* `#END` */ - - -/******************************************************************************* -* Function Name: USBFS_HandleVendorRqst -******************************************************************************** -* -* Summary: -* This routine provide users with a method to implement vendor specifc -* requests. -* -* To implement vendor specific requests, add your code in this function to -* decode and disposition the request. If the request is handled, your code -* must set the variable "requestHandled" to TRUE, indicating that the -* request has been handled. -* -* Parameters: -* None. -* -* Return: -* requestHandled. -* -* Reentrant: -* No. -* -*******************************************************************************/ -uint8 USBFS_HandleVendorRqst(void) -{ - uint8 requestHandled = USBFS_FALSE; - - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - { - /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) - { - case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: - #if defined(USBFS_ENABLE_MSOS_STRING) - USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u]; - USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; - requestHandled = USBFS_InitControlRead(); - #endif /* End USBFS_ENABLE_MSOS_STRING */ - break; - default: - break; - } - } - - /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */ - - /* `#END` */ - - return(requestHandled); -} - - -/******************************************************************************* -* Additional user functions supporting Vendor Specific Requests -********************************************************************************/ - -/* `#START VENDOR_SPECIFIC_FUNCTIONS` Place any additional functions here */ - -/* `#END` */ - - -#endif /* USBFS_EXTERN_VND */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.bvf b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.bvf deleted file mode 100755 index 9acffcd..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.bvf +++ /dev/null @@ -1,25 +0,0 @@ - ----------------------------------------------------------------------- - -Verifying bitstream. - ------------------------------------------------------------------------ - - ----------Mapping jacks.--------- - - ----------Processing bitstream.--------- - -Utilized "dsi_hv_a@[DSI=(0,1)][side=top]" -Utilized "dsi_hv_b@[DSI=(1,1)][side=bottom]" -Utilized "dsi_hc@[DSI=(0,2)][side=top]" -Utilized "dsi_hc@[DSI=(1,5)][side=bottom]" - - ----------------------------------------------------------------------- - -Bitstream verification passed. - ------------------------------------------------------------------------ - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl deleted file mode 100755 index 3e249a5..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.ctl +++ /dev/null @@ -1,9 +0,0 @@ --- ====================================================================== --- USB_Bootloader.ctl generated from USB_Bootloader --- 03/22/2014 at 22:32 --- This file is auto generated. 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z5ICchyc@^WTzdnKui2Ls`6S7bTLk|^BW8Ym+ME|mj-F8~r2)n#A1DFwn*LIhw}_U zKym`WKt45^e-$xJmA`?N;SeXS@GZ%p5>Kr0rbHot#`9T>fqHA1vPJa#Z9~ zCkz7v@|RwkPO>(-h6PprOvF8>|tpePU!RVy1SQ+qoVbGN^ZU6E;WF@5$c zkPrj};;M@3Dx%_ss^X$*(uxXySMhJt|A>bFQwS42-EU>7^v&4W zT+GJvZ?JaTZeu9>b0-T$`YUc4|9~Q5e*=Gu!vAB5p9$:ioport3:pin1.in_clock" - term ":ioport3:pin1.in_clock" - switch ":clockblockcell.clk_bus_glb==>:ioport3:pin2.in_clock" - term ":ioport3:pin2.in_clock" - switch ":clockblockcell.clk_bus_glb==>:ioport3:pin3.in_clock" - term ":ioport3:pin3.in_clock" - switch ":clockblockcell.clk_bus_glb==>:ioport3:pin4.in_clock" - term ":ioport3:pin4.in_clock" - switch ":clockblockcell.clk_bus_glb==>:ioport3:pin5.in_clock" - term ":ioport3:pin5.in_clock" - switch ":clockblockcell.clk_bus_glb==>:ioport15:pin6.in_clock" - term ":ioport15:pin6.in_clock" - switch ":clockblockcell.clk_bus_glb==>:interrupt_22.clock" - term ":interrupt_22.clock" - switch ":clockblockcell.clk_bus_glb==>:interrupt_23.clock" - term ":interrupt_23.clock" - switch ":clockblockcell.clk_bus_glb==>:interrupt_12.clock" - term ":interrupt_12.clock" - switch ":clockblockcell.clk_bus_glb==>:interrupt_24.clock" - term ":interrupt_24.clock" - switch ":clockblockcell.clk_bus_glb==>:interrupt_0.clock" - term ":interrupt_0.clock" - switch ":clockblockcell.clk_bus_glb==>:interrupt_1.clock" - term ":interrupt_1.clock" - switch ":clockblockcell.clk_bus_glb==>:interrupt_21.clock" - term ":interrupt_21.clock" -end ClockBlock_BUS_CLK -net Net_40 - term ":usbcell.sof_int" - switch ":usbcell.sof_int==>Stub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v4+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v6" - switch "Stub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v4+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v6==>:interrupt_idmux_21.in_0" - switch ":interrupt_idmux_21.interrupt_idmux_21__out==>:interrupt_21.interrupt" - term ":interrupt_21.interrupt" -end Net_40 -net \USBFS:Net_1010\ - term ":logicalport_15.interrupt" - switch ":logicalport_15.interrupt==>Stub-:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v36+:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v38" - switch "Stub-:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v36+:dsiswitch_bottom@[DSI=(1,2)][side=bottom]:dsihc_bottom:v38==>:interrupt_idmux_12.in_0" - switch ":interrupt_idmux_12.interrupt_idmux_12__out==>:interrupt_12.interrupt" - term ":interrupt_12.interrupt" -end \USBFS:Net_1010\ -net \USBFS:Net_79\ - term ":usbcell.arb_int" - switch ":usbcell.arb_int==>Stub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v25+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v27" - switch "Stub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v25+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v27==>:interrupt_idmux_22.in_0" - switch ":interrupt_idmux_22.interrupt_idmux_22__out==>:interrupt_22.interrupt" - term ":interrupt_22.interrupt" -end \USBFS:Net_79\ -net \USBFS:Net_81\ - term ":usbcell.usb_int" - switch ":usbcell.usb_int==>Stub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v24+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v26" - switch "Stub-:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v24+:dsiswitch_top@[DSI=(0,1)][side=top]:dsihc_top:v26==>:interrupt_idmux_23.in_0" - switch ":interrupt_idmux_23.interrupt_idmux_23__out==>:interrupt_23.interrupt" - term ":interrupt_23.interrupt" -end \USBFS:Net_81\ -net \USBFS:ept_int_0\ - term ":usbcell.ept_int_0" - switch ":usbcell.ept_int_0==>Stub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v5+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v7" - switch "Stub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v5+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v7==>:interrupt_idmux_24.in_0" - switch ":interrupt_idmux_24.interrupt_idmux_24__out==>:interrupt_24.interrupt" - term ":interrupt_24.interrupt" -end \USBFS:ept_int_0\ -net \USBFS:ept_int_1\ - term ":usbcell.ept_int_1" - switch ":usbcell.ept_int_1==>Stub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v10+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v8" - switch "OStub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v10+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v8" - switch ":dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:10,10" - switch ":hvswitch@[UDB=(0,1)][side=left]:23,10_f" - switch ":hvswitch@[UDB=(1,1)][side=left]:vseg_23_top_f" - switch ":hvswitch@[UDB=(2,1)][side=left]:vseg_23_top_f" - switch ":hvswitch@[UDB=(3,1)][side=left]:vseg_23_top_f" - switch ":hvswitch@[UDB=(3,1)][side=left]:23,95_b" - switch ":hvswitch@[UDB=(3,2)][side=left]:hseg_95_f" - switch ":hvswitch@[UDB=(3,3)][side=left]:hseg_95_f" - switch ":hvswitch@[UDB=(3,4)][side=left]:hseg_95_f" - switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:48,95_f" - switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v48+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v50" - switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v48+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v50==>:interrupt_idmux_0.in_2" - switch ":interrupt_idmux_0.interrupt_idmux_0__out==>:interrupt_0.interrupt" - term ":interrupt_0.interrupt" -end \USBFS:ept_int_1\ -net \USBFS:ept_int_2\ - term ":usbcell.ept_int_2" - switch ":usbcell.ept_int_2==>Stub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v11+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v9" - switch "OStub-:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v11+:dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:v9" - switch ":dsiswitch_top@[DSI=(0,2)][side=top]:dsihc_top:9,90" - switch ":hvswitch@[UDB=(0,1)][side=left]:21,90_f" - switch ":hvswitch@[UDB=(1,1)][side=left]:vseg_21_top_f" - switch ":hvswitch@[UDB=(2,1)][side=left]:vseg_21_top_f" - switch ":hvswitch@[UDB=(3,1)][side=left]:vseg_21_top_f" - switch ":hvswitch@[UDB=(3,1)][side=left]:21,68_b" - switch ":hvswitch@[UDB=(3,2)][side=left]:hseg_68_f" - switch ":hvswitch@[UDB=(3,3)][side=left]:hseg_68_f" - switch ":hvswitch@[UDB=(3,4)][side=left]:hseg_68_f" - switch ":dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:49,68_f" - switch "IStub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v49+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v51" - switch "Stub-:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v49+:dsiswitch_bottom@[DSI=(1,5)][side=bottom]:dsihc_bottom:v51==>:interrupt_idmux_1.in_2" - switch ":interrupt_idmux_1.interrupt_idmux_1__out==>:interrupt_1.interrupt" - term ":interrupt_1.interrupt" -end \USBFS:ept_int_2\ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt deleted file mode 100755 index 7a8943b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rpt +++ /dev/null @@ -1,2695 +0,0 @@ -Loading plugins phase: Elapsed time ==> 0s.500ms -Initializing data phase: Elapsed time ==> 3s.890ms - -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE - - -Elaboration phase: Elapsed time ==> 7s.406ms - - -HDL generation phase: Elapsed time ==> 0s.109ms - - - | | | | | | | - _________________ - -| |- - -| |- - -| |- - -| CYPRESS |- - -| |- - -| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41 - -| |- Copyright (C) 1991-2001 Cypress Semiconductor - |_______________| - | | | | | | | - -====================================================================== -Compiling: USB_Bootloader.v -Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -====================================================================== - -====================================================================== -Compiling: USB_Bootloader.v -Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -====================================================================== - -====================================================================== -Compiling: USB_Bootloader.v -Program : vlogfe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v -====================================================================== - -vlogfe V6.3 IR 41: Verilog parser -Sat Mar 22 22:32:47 2014 - - -====================================================================== -Compiling: USB_Bootloader.v -Program : vpp -Options : -yv2 -q10 USB_Bootloader.v -====================================================================== - -vpp V6.3 IR 41: Verilog Pre-Processor -Sat Mar 22 22:32:47 2014 - - -vpp: No errors. - -Library 'work' => directory 'lcpsoc3' -General_symbol_table -General_symbol_table -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Using control file 'USB_Bootloader.ctl'. - -vlogfe: No errors. - - -====================================================================== -Compiling: USB_Bootloader.v -Program : tovif -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v -====================================================================== - -tovif V6.3 IR 41: High-level synthesis -Sat Mar 22 22:32:47 2014 - -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. - -tovif: No errors. - - -====================================================================== -Compiling: USB_Bootloader.v -Program : topld -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v -====================================================================== - -topld V6.3 IR 41: Synthesis and optimization -Sat Mar 22 22:32:48 2014 - -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. - ----------------------------------------------------------- -Detecting unused logic. ----------------------------------------------------------- - - - ------------------------------------------------------- -Alias Detection ------------------------------------------------------- -Aliasing one to \USBFS:tmpOE__Dm_net_0\ -Aliasing \USBFS:tmpOE__Dp_net_0\ to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_7 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_6 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_5 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_4 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_3 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_2 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_1 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_DBx_net_0 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_9 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_8 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_7 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_6 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_5 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_4 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_3 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_2 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_1 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SCSI_Out_net_0 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SD_PULLUP_net_4 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SD_PULLUP_net_3 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SD_PULLUP_net_2 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SD_PULLUP_net_1 to \USBFS:tmpOE__Dm_net_0\ -Aliasing tmpOE__SD_PULLUP_net_0 to \USBFS:tmpOE__Dm_net_0\ -Removing Rhs of wire one[37] = \USBFS:tmpOE__Dm_net_0\[32] -Removing Lhs of wire \USBFS:tmpOE__Dp_net_0\[40] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_7[49] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_6[50] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_5[51] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_4[52] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_3[53] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_2[54] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_1[55] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_0[56] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_9[84] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_8[85] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_7[86] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_6[87] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_5[88] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_4[89] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_3[90] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_2[91] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_1[92] = one[37] -Removing Lhs of wire tmpOE__SCSI_Out_net_0[93] = one[37] -Removing Lhs of wire tmpOE__SD_PULLUP_net_4[127] = one[37] -Removing Lhs of wire tmpOE__SD_PULLUP_net_3[128] = one[37] -Removing Lhs of wire tmpOE__SD_PULLUP_net_2[129] = one[37] -Removing Lhs of wire tmpOE__SD_PULLUP_net_1[130] = one[37] -Removing Lhs of wire tmpOE__SD_PULLUP_net_0[131] = one[37] - ------------------------------------------------------- -Aliased 0 equations, 25 wires. ------------------------------------------------------- - ----------------------------------------------------------- -Circuit simplification ----------------------------------------------------------- - -Substituting virtuals - pass 1: - - ----------------------------------------------------------- -Circuit simplification results: - - Expanded 0 signals. - Turned 0 signals into soft nodes. - Maximum default expansion cost was set at 3. ----------------------------------------------------------- - -topld: No errors. - -CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp -Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog - -Warp synthesis phase: Elapsed time ==> 1s.468ms - - -cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Saturday, 22 March 2014 22:32:48 -Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog - - -Design parsing phase: Elapsed time ==> 0s.046ms - - - -Assigning clock USBFS_Clock_vbus to clock BUS_CLK because it is a pass-through - - - - - - - - - - - ------------------------------------------------------------- -Design Equations ------------------------------------------------------------- - - - ------------------------------------------------------------ - Pin listing - ------------------------------------------------------------ - - Pin : Name = SCSI_Out(0) - Attributes: - Alias: DBP_raw - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(0)__PA , - pad => SCSI_Out(0)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(1) - Attributes: - Alias: ATN - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(1)__PA , - pad => SCSI_Out(1)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(2) - Attributes: - Alias: BSY - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(2)__PA , - pad => SCSI_Out(2)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(3) - Attributes: - Alias: ACK - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(3)__PA , - pad => SCSI_Out(3)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(4) - Attributes: - Alias: RST - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(4)__PA , - pad => SCSI_Out(4)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(5) - Attributes: - Alias: MSG - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(5)__PA , - pad => SCSI_Out(5)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(6) - Attributes: - Alias: SEL - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(6)__PA , - pad => SCSI_Out(6)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(7) - Attributes: - Alias: CD - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(7)__PA , - pad => SCSI_Out(7)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(8) - Attributes: - Alias: REQ - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(8)__PA , - pad => SCSI_Out(8)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out(9) - Attributes: - Alias: IO_raw - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(9)__PA , - pad => SCSI_Out(9)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(0) - Attributes: - Alias: DB0 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(0)__PA , - pad => SCSI_Out_DBx(0)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(1) - Attributes: - Alias: DB1 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(1)__PA , - pad => SCSI_Out_DBx(1)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(2) - Attributes: - Alias: DB2 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(2)__PA , - pad => SCSI_Out_DBx(2)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(3) - Attributes: - Alias: DB3 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(3)__PA , - pad => SCSI_Out_DBx(3)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(4) - Attributes: - Alias: DB4 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(4)__PA , - pad => SCSI_Out_DBx(4)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(5) - Attributes: - Alias: DB5 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(5)__PA , - pad => SCSI_Out_DBx(5)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(6) - Attributes: - Alias: DB6 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(6)__PA , - pad => SCSI_Out_DBx(6)_PAD ); - Properties: - { - } - - Pin : Name = SCSI_Out_DBx(7) - Attributes: - Alias: DB7 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out_DBx(7)__PA , - pad => SCSI_Out_DBx(7)_PAD ); - Properties: - { - } - - Pin : Name = SD_PULLUP(0) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 3.3 - PORT MAP ( - pa_out => SD_PULLUP(0)__PA , - pad => SD_PULLUP(0)_PAD ); - Properties: - { - } - - Pin : Name = SD_PULLUP(1) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(1)__PA , - pad => SD_PULLUP(1)_PAD ); - Properties: - { - } - - Pin : Name = SD_PULLUP(2) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(2)__PA , - pad => SD_PULLUP(2)_PAD ); - Properties: - { - } - - Pin : Name = SD_PULLUP(3) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(3)__PA , - pad => SD_PULLUP(3)_PAD ); - Properties: - { - } - - Pin : Name = SD_PULLUP(4) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(4)__PA , - pad => SD_PULLUP(4)_PAD ); - Properties: - { - } - - Pin : Name = \USBFS:Dm(0)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: HI_Z_ANALOG - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: True - Can contain Digital: False - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: USB_D_MINUS - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => \USBFS:Dm(0)\__PA , - analog_term => \USBFS:Net_597\ , - pad => \USBFS:Dm(0)_PAD\ ); - Properties: - { - } - - Pin : Name = \USBFS:Dp(0)\ - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: True - Interrupt mode: FALLING - Drive mode: HI_Z_ANALOG - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: True - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: USB_D_PLUS - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => \USBFS:Dp(0)\__PA , - analog_term => \USBFS:Net_1000\ , - pad => \USBFS:Dp(0)_PAD\ ); - Properties: - { - } - - - - - - - - - - - - - - - - - - - - ------------------------------------------------------------ - Interrupt listing - ------------------------------------------------------------ - - interrupt: Name =\USBFS:arb_int\ - PORT MAP ( - interrupt => \USBFS:Net_79\ ); - Properties: - { - int_type = "10" - } - - interrupt: Name =\USBFS:bus_reset\ - PORT MAP ( - interrupt => \USBFS:Net_81\ ); - Properties: - { - int_type = "10" - } - - interrupt: Name =\USBFS:dp_int\ - PORT MAP ( - interrupt => \USBFS:Net_1010\ ); - Properties: - { - int_type = "10" - } - - interrupt: Name =\USBFS:ep_0\ - PORT MAP ( - interrupt => \USBFS:ept_int_0\ ); - Properties: - { - int_type = "10" - } - - interrupt: Name =\USBFS:ep_1\ - PORT MAP ( - interrupt => \USBFS:ept_int_1\ ); - Properties: - { - int_type = "10" - } - - interrupt: Name =\USBFS:ep_2\ - PORT MAP ( - interrupt => \USBFS:ept_int_2\ ); - Properties: - { - int_type = "10" - } - - interrupt: Name =\USBFS:sof_int\ - PORT MAP ( - interrupt => Net_40 ); - Properties: - { - int_type = "10" - } - - - - ------------------------------------------------------------- -Technology mapping summary ------------------------------------------------------------- - -Resource Type : Used : Free : Max : % Used -============================================================ -Digital clock dividers : 0 : 8 : 8 : 0.00% -Analog clock dividers : 0 : 4 : 4 : 0.00% -Pins : 28 : 44 : 72 : 38.89% -UDB Macrocells : 0 : 192 : 192 : 0.00% -UDB Unique Pterms : 0 : 384 : 384 : 0.00% -UDB Datapath Cells : 0 : 24 : 24 : 0.00% -UDB Status Cells : 0 : 24 : 24 : 0.00% -UDB Control Cells : 0 : 24 : 24 : 0.00% -DMA Channels : 0 : 24 : 24 : 0.00% -Interrupts : 7 : 25 : 32 : 21.88% -VIDAC Fixed Blocks : 0 : 1 : 1 : 0.00% -Comparator Fixed Blocks : 0 : 2 : 2 : 0.00% -CapSense Buffers : 0 : 2 : 2 : 0.00% -I2C Fixed Blocks : 0 : 1 : 1 : 0.00% -Timer Fixed Blocks : 0 : 4 : 4 : 0.00% -USB Fixed Blocks : 1 : 0 : 1 : 100.00% -LCD Fixed Blocks : 0 : 1 : 1 : 0.00% -EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% -LPF Fixed Blocks : 0 : 2 : 2 : 0.00% -SAR Fixed Blocks : 0 : 1 : 1 : 0.00% - -Technology Mapping: Elapsed time ==> 0s.030ms -Tech mapping phase: Elapsed time ==> 0s.265ms - - -Initial Analog Placement Results: -IO_3@[IOP=(4)][IoId=(3)] : SCSI_Out(0) (fixed) -IO_2@[IOP=(4)][IoId=(2)] : SCSI_Out(1) (fixed) -IO_7@[IOP=(0)][IoId=(7)] : SCSI_Out(2) (fixed) -IO_6@[IOP=(0)][IoId=(6)] : SCSI_Out(3) (fixed) -IO_5@[IOP=(0)][IoId=(5)] : SCSI_Out(4) (fixed) -IO_4@[IOP=(0)][IoId=(4)] : SCSI_Out(5) (fixed) -IO_3@[IOP=(0)][IoId=(3)] : SCSI_Out(6) (fixed) -IO_2@[IOP=(0)][IoId=(2)] : SCSI_Out(7) (fixed) -IO_1@[IOP=(0)][IoId=(1)] : SCSI_Out(8) (fixed) -IO_0@[IOP=(0)][IoId=(0)] : SCSI_Out(9) (fixed) -IO_3@[IOP=(6)][IoId=(3)] : SCSI_Out_DBx(0) (fixed) -IO_2@[IOP=(6)][IoId=(2)] : SCSI_Out_DBx(1) (fixed) -IO_1@[IOP=(6)][IoId=(1)] : SCSI_Out_DBx(2) (fixed) -IO_0@[IOP=(6)][IoId=(0)] : SCSI_Out_DBx(3) (fixed) -IO_7@[IOP=(4)][IoId=(7)] : SCSI_Out_DBx(4) (fixed) -IO_6@[IOP=(4)][IoId=(6)] : SCSI_Out_DBx(5) (fixed) -IO_5@[IOP=(4)][IoId=(5)] : SCSI_Out_DBx(6) (fixed) -IO_4@[IOP=(4)][IoId=(4)] : SCSI_Out_DBx(7) (fixed) -IO_1@[IOP=(3)][IoId=(1)] : SD_PULLUP(0) (fixed) -IO_2@[IOP=(3)][IoId=(2)] : SD_PULLUP(1) (fixed) -IO_3@[IOP=(3)][IoId=(3)] : SD_PULLUP(2) (fixed) -IO_4@[IOP=(3)][IoId=(4)] : SD_PULLUP(3) (fixed) -IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed) -IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) -IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) -USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.109ms - - -Analog Routing phase: Elapsed time ==> 0s.000ms - - -============ Analog Final Answer Routes ============ -Dump of CyAnalogRoutingResultsDB -Map of net to items { -} -Map of item to net { -} -Mux Info { -} -Dump of CyP35AnalogRoutingResultsDB -IsVddaHalfUsedForComp = False -IsVddaHalfUsedForSar0 = False -IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 1s.000ms - - - -I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 1.2 sec. - - - - -No PLDs were packed. - -PLD Packing: Elapsed time ==> 0s.000ms - - - -Initial Partitioning Summary not displayed at this verbose level. - -Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.093ms - - -Annealing: Elapsed time ==> 0s.000ms - -The seed used for moves was 114161200. -Inital cost was 120, final cost is 120 (0.00% improvement). - - - ------------------------------------------------------------- -Final Placement Summary ------------------------------------------------------------- - - Resource Type : Count : Avg Inputs : Avg Outputs - ======================================================== - UDB : 0 : 0.00 : 0.00 - - - ------------------------------------------------------------- -Component Placement Details ------------------------------------------------------------- -UDB [UDB=(0,0)] is empty. -UDB [UDB=(0,1)] is empty. -UDB [UDB=(0,2)] is empty. -UDB [UDB=(0,3)] is empty. -UDB [UDB=(0,4)] is empty. -UDB [UDB=(0,5)] is empty. -UDB [UDB=(1,0)] is empty. -UDB [UDB=(1,1)] is empty. -UDB [UDB=(1,2)] is empty. -UDB [UDB=(1,3)] is empty. -UDB [UDB=(1,4)] is empty. -UDB [UDB=(1,5)] is empty. -UDB [UDB=(2,0)] is empty. -UDB [UDB=(2,1)] is empty. -UDB [UDB=(2,2)] is empty. -UDB [UDB=(2,3)] is empty. -UDB [UDB=(2,4)] is empty. -UDB [UDB=(2,5)] is empty. -UDB [UDB=(3,0)] is empty. -UDB [UDB=(3,1)] is empty. -UDB [UDB=(3,2)] is empty. -UDB [UDB=(3,3)] is empty. -UDB [UDB=(3,4)] is empty. -UDB [UDB=(3,5)] is empty. -Intr hod @ [IntrHod=(0)]: - Intr@ [IntrHod=(0)][IntrId=(0)] - interrupt: Name =\USBFS:ep_1\ - PORT MAP ( - interrupt => \USBFS:ept_int_1\ ); - Properties: - { - int_type = "10" - } - Intr@ [IntrHod=(0)][IntrId=(1)] - interrupt: Name =\USBFS:ep_2\ - PORT MAP ( - interrupt => \USBFS:ept_int_2\ ); - Properties: - { - int_type = "10" - } - Intr@ [IntrHod=(0)][IntrId=(12)] - interrupt: Name =\USBFS:dp_int\ - PORT MAP ( - interrupt => \USBFS:Net_1010\ ); - Properties: - { - int_type = "10" - } - Intr@ [IntrHod=(0)][IntrId=(21)] - interrupt: Name =\USBFS:sof_int\ - PORT MAP ( - interrupt => Net_40 ); - Properties: - { - int_type = "10" - } - Intr@ [IntrHod=(0)][IntrId=(22)] - interrupt: Name =\USBFS:arb_int\ - PORT MAP ( - interrupt => \USBFS:Net_79\ ); - Properties: - { - int_type = "10" - } - Intr@ [IntrHod=(0)][IntrId=(23)] - interrupt: Name =\USBFS:bus_reset\ - PORT MAP ( - interrupt => \USBFS:Net_81\ ); - Properties: - { - int_type = "10" - } - Intr@ [IntrHod=(0)][IntrId=(24)] - interrupt: Name =\USBFS:ep_0\ - PORT MAP ( - interrupt => \USBFS:ept_int_0\ ); - Properties: - { - int_type = "10" - } -Drq hod @ [DrqHod=(0)]: empty -Port 0 contains the following IO cells: -[IoId=0]: -Pin : Name = SCSI_Out(9) - Attributes: - Alias: IO_raw - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(9)__PA , - pad => SCSI_Out(9)_PAD ); - Properties: - { - } - -[IoId=1]: -Pin : Name = SCSI_Out(8) - Attributes: - Alias: REQ - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(8)__PA , - pad => SCSI_Out(8)_PAD ); - Properties: - { - } - -[IoId=2]: -Pin : Name = SCSI_Out(7) - Attributes: - Alias: CD - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(7)__PA , - pad => SCSI_Out(7)_PAD ); - Properties: - { - } - -[IoId=3]: -Pin : Name = SCSI_Out(6) - Attributes: - Alias: SEL - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(6)__PA , - pad => SCSI_Out(6)_PAD ); - Properties: - { - } - -[IoId=4]: -Pin : Name = SCSI_Out(5) - Attributes: - Alias: MSG - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(5)__PA , - pad => SCSI_Out(5)_PAD ); - Properties: - { - } - -[IoId=5]: -Pin : Name = SCSI_Out(4) - Attributes: - Alias: RST - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(4)__PA , - pad => SCSI_Out(4)_PAD ); - Properties: - { - } - -[IoId=6]: -Pin : Name = SCSI_Out(3) - Attributes: - Alias: ACK - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(3)__PA , - pad => SCSI_Out(3)_PAD ); - Properties: - { - } - -[IoId=7]: -Pin : Name = SCSI_Out(2) - Attributes: - Alias: BSY - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(2)__PA , - pad => SCSI_Out(2)_PAD ); - Properties: - { - } - -Port 1 is empty -Port 2 is empty -Port 3 contains the following IO cells: -[IoId=1]: -Pin : Name = SD_PULLUP(0) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 3.3 - PORT MAP ( - pa_out => SD_PULLUP(0)__PA , - pad => SD_PULLUP(0)_PAD ); - Properties: - { - } - -[IoId=2]: -Pin : Name = SD_PULLUP(1) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(1)__PA , - pad => SD_PULLUP(1)_PAD ); - Properties: - { - } - -[IoId=3]: -Pin : Name = SD_PULLUP(2) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(2)__PA , - pad => SD_PULLUP(2)_PAD ); - Properties: - { - } - -[IoId=4]: -Pin : Name = SD_PULLUP(3) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(3)__PA , - pad => SD_PULLUP(3)_PAD ); - Properties: - { - } - -[IoId=5]: -Pin : Name = SD_PULLUP(4) - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: RES_PULL_UP - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: INP_DIS_LO - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 1 - IO Voltage: 0 - PORT MAP ( - pa_out => SD_PULLUP(4)__PA , - pad => SD_PULLUP(4)_PAD ); - Properties: - { - } - -Port 4 contains the following IO cells: -[IoId=2]: -Pin : Name = SCSI_Out(1) - Attributes: - Alias: ATN - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(1)__PA , - pad => SCSI_Out(1)_PAD ); - Properties: - { - } - -[IoId=3]: -Pin : Name = SCSI_Out(0) - Attributes: - Alias: DBP_raw - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out(0)__PA , - pad => SCSI_Out(0)_PAD ); - Properties: - { - } - -[IoId=4]: -Pin : Name = SCSI_Out_DBx(7) - Attributes: - Alias: DB7 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 5 - PORT MAP ( - pa_out => SCSI_Out_DBx(7)__PA , - pad => SCSI_Out_DBx(7)_PAD ); - Properties: - { - } - -[IoId=5]: -Pin : Name = SCSI_Out_DBx(6) - Attributes: - Alias: DB6 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(6)__PA , - pad => SCSI_Out_DBx(6)_PAD ); - Properties: - { - } - -[IoId=6]: -Pin : Name = SCSI_Out_DBx(5) - Attributes: - Alias: DB5 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(5)__PA , - pad => SCSI_Out_DBx(5)_PAD ); - Properties: - { - } - -[IoId=7]: -Pin : Name = SCSI_Out_DBx(4) - Attributes: - Alias: DB4 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(4)__PA , - pad => SCSI_Out_DBx(4)_PAD ); - Properties: - { - } - -Port 5 is empty -Port 6 contains the following IO cells: -[IoId=0]: -Pin : Name = SCSI_Out_DBx(3) - Attributes: - Alias: DB3 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(3)__PA , - pad => SCSI_Out_DBx(3)_PAD ); - Properties: - { - } - -[IoId=1]: -Pin : Name = SCSI_Out_DBx(2) - Attributes: - Alias: DB2 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(2)__PA , - pad => SCSI_Out_DBx(2)_PAD ); - Properties: - { - } - -[IoId=2]: -Pin : Name = SCSI_Out_DBx(1) - Attributes: - Alias: DB1 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(1)__PA , - pad => SCSI_Out_DBx(1)_PAD ); - Properties: - { - } - -[IoId=3]: -Pin : Name = SCSI_Out_DBx(0) - Attributes: - Alias: DB0 - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: NOSYNC - Interrupt generated: False - Interrupt mode: NONE - Drive mode: CMOS_OUT - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: False - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: DIGITAL - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => SCSI_Out_DBx(0)__PA , - pad => SCSI_Out_DBx(0)_PAD ); - Properties: - { - } - -Port 12 is empty -Port 15 generates interrupt for logical port: - logicalport: Name =\USBFS:Dp\ - PORT MAP ( - in_clock_en => one , - in_reset => zero , - out_clock_en => one , - out_reset => zero , - interrupt => \USBFS:Net_1010\ , - in_clock => ClockBlock_BUS_CLK ); - Properties: - { - drive_mode = "000" - ibuf_enabled = "0" - id = "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42" - init_dr_st = "0" - input_clk_en = 0 - input_sync = "1" - input_sync_mode = "0" - intr_mode = "10" - invert_in_clock = 0 - invert_in_clock_en = 0 - invert_in_reset = 0 - invert_out_clock = 0 - invert_out_clock_en = 0 - invert_out_reset = 0 - io_voltage = "" - layout_mode = "CONTIGUOUS" - oe_conn = "0" - oe_reset = 0 - oe_sync = "0" - output_clk_en = 0 - output_clock_mode = "0" - output_conn = "0" - output_mode = "0" - output_reset = 0 - output_sync = "0" - pa_in_clock = -1 - pa_in_clock_en = -1 - pa_in_reset = -1 - pa_out_clock = -1 - pa_out_clock_en = -1 - pa_out_reset = -1 - pin_aliases = "" - pin_mode = "I" - por_state = 4 - port_alias_group = "" - port_alias_required = 0 - sio_group_cnt = 0 - sio_hifreq = "" - sio_hyst = "0" - sio_ibuf = "00000000" - sio_info = "00" - sio_obuf = "00000000" - sio_refsel = "00000000" - sio_vtrip = "00000000" - slew_rate = "0" - spanning = 0 - sw_only = 0 - use_annotation = "0" - vtrip = "00" - width = 1 - } - and contains the following IO cells: -[IoId=6]: -Pin : Name = \USBFS:Dp(0)\ - Attributes: - In Group/Port: True - In Sync Option: SYNC - Out Sync Option: AUTO - Interrupt generated: True - Interrupt mode: FALLING - Drive mode: HI_Z_ANALOG - VTrip: CMOS - Slew: FAST - Input Sync needed: True - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: False - Is OE Registered: False - Uses Analog: True - Can contain Digital: True - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: USB_D_PLUS - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => \USBFS:Dp(0)\__PA , - analog_term => \USBFS:Net_1000\ , - pad => \USBFS:Dp(0)_PAD\ ); - Properties: - { - } - -[IoId=7]: -Pin : Name = \USBFS:Dm(0)\ - Attributes: - In Group/Port: True - In Sync Option: AUTO - Out Sync Option: AUTO - Interrupt generated: False - Interrupt mode: NONE - Drive mode: HI_Z_ANALOG - VTrip: EITHER - Slew: FAST - Input Sync needed: False - Output Sync needed: False - SC shield enabled: False - POR State: ANY - LCD Mode: COMMON - Register Mode: RegComb - CaSense Mode: NEITHER - Treat as pin: True - Is OE Registered: False - Uses Analog: True - Can contain Digital: False - Is SIO: False - SIO Output Buf: NONREGULATED - SIO Input Buf: SINGLE_ENDED - SIO HiFreq: LOW - SIO Hyst: DISABLED - SIO Vtrip: MULTIPLIER_0_5 - SIO RefSel: VCC_IO - Required Capabilitites: USB_D_MINUS - Initial Value: 0 - IO Voltage: 0 - PORT MAP ( - pa_out => \USBFS:Dm(0)\__PA , - analog_term => \USBFS:Net_597\ , - pad => \USBFS:Dm(0)_PAD\ ); - Properties: - { - } - -Fixed Function block hod @ [FFB(CAN,0)]: empty -Fixed Function block hod @ [FFB(Cache,0)]: empty -Fixed Function block hod @ [FFB(CapSense,0)]: empty -Fixed Function block hod @ [FFB(Clock,0)]: - Clock Block @ [FFB(Clock,0)]: - clockblockcell: Name =ClockBlock - PORT MAP ( - clk_bus_glb => ClockBlock_BUS_CLK , - clk_bus => ClockBlock_BUS_CLK_local , - clk_sync => ClockBlock_MASTER_CLK , - clk_32k_xtal => ClockBlock_XTAL_32KHZ , - xtal => ClockBlock_XTAL , - ilo => ClockBlock_ILO , - clk_100k => ClockBlock_100k , - clk_1k => ClockBlock_1k , - clk_32k => ClockBlock_32k , - pllout => ClockBlock_PLL_OUT , - imo => ClockBlock_IMO ); - Properties: - { - } -Fixed Function block hod @ [FFB(Comparator,0)]: empty -Fixed Function block hod @ [FFB(DFB,0)]: empty -Fixed Function block hod @ [FFB(DSM,0)]: empty -Fixed Function block hod @ [FFB(Decimator,0)]: empty -Fixed Function block hod @ [FFB(EMIF,0)]: empty -Fixed Function block hod @ [FFB(I2C,0)]: empty -Fixed Function block hod @ [FFB(LCD,0)]: empty -Fixed Function block hod @ [FFB(LVD,0)]: empty -Fixed Function block hod @ [FFB(PM,0)]: empty -Fixed Function block hod @ [FFB(SPC,0)]: empty -Fixed Function block hod @ [FFB(Timer,0)]: empty -Fixed Function block hod @ [FFB(USB,0)]: - USB Block @ [FFB(USB,0)]: - usbcell: Name =\USBFS:USB\ - PORT MAP ( - dp => \USBFS:Net_1000\ , - dm => \USBFS:Net_597\ , - sof_int => Net_40 , - arb_int => \USBFS:Net_79\ , - usb_int => \USBFS:Net_81\ , - ept_int_8 => \USBFS:ept_int_8\ , - ept_int_7 => \USBFS:ept_int_7\ , - ept_int_6 => \USBFS:ept_int_6\ , - ept_int_5 => \USBFS:ept_int_5\ , - ept_int_4 => \USBFS:ept_int_4\ , - ept_int_3 => \USBFS:ept_int_3\ , - ept_int_2 => \USBFS:ept_int_2\ , - ept_int_1 => \USBFS:ept_int_1\ , - ept_int_0 => \USBFS:ept_int_0\ , - ord_int => \USBFS:Net_95\ , - dma_req_7 => \USBFS:dma_req_7\ , - dma_req_6 => \USBFS:dma_req_6\ , - dma_req_5 => \USBFS:dma_req_5\ , - dma_req_4 => \USBFS:dma_req_4\ , - dma_req_3 => \USBFS:dma_req_3\ , - dma_req_2 => \USBFS:dma_req_2\ , - dma_req_1 => \USBFS:dma_req_1\ , - dma_req_0 => \USBFS:dma_req_0\ , - dma_termin => \USBFS:Net_824\ ); - Properties: - { - cy_registers = "" - } -Fixed Function block hod @ [FFB(VIDAC,0)]: empty -Fixed Function block hod @ [FFB(CsAbuf,0)]: empty -Fixed Function block hod @ [FFB(Vref,0)]: empty -Fixed Function block hod @ [FFB(LPF,0)]: empty -Fixed Function block hod @ [FFB(SAR,0)]: empty - - - ------------------------------------------------------------- -Port Configuration report ------------------------------------------------------------- - | | | Interrupt | | | -Port | Pin | Fixed | Type | Drive Mode | Name | Connections ------+-----+-------+-----------+------------------+-----------------+------------------------- - 0 | 0 | * | NONE | CMOS_OUT | SCSI_Out(9) | - | 1 | * | NONE | CMOS_OUT | SCSI_Out(8) | - | 2 | * | NONE | CMOS_OUT | SCSI_Out(7) | - | 3 | * | NONE | CMOS_OUT | SCSI_Out(6) | - | 4 | * | NONE | CMOS_OUT | SCSI_Out(5) | - | 5 | * | NONE | CMOS_OUT | SCSI_Out(4) | - | 6 | * | NONE | CMOS_OUT | SCSI_Out(3) | - | 7 | * | NONE | CMOS_OUT | SCSI_Out(2) | ------+-----+-------+-----------+------------------+-----------------+------------------------- - 3 | 1 | * | NONE | RES_PULL_UP | SD_PULLUP(0) | - | 2 | * | NONE | RES_PULL_UP | SD_PULLUP(1) | - | 3 | * | NONE | RES_PULL_UP | SD_PULLUP(2) | - | 4 | * | NONE | RES_PULL_UP | SD_PULLUP(3) | - | 5 | * | NONE | RES_PULL_UP | SD_PULLUP(4) | ------+-----+-------+-----------+------------------+-----------------+------------------------- - 4 | 2 | * | NONE | CMOS_OUT | SCSI_Out(1) | - | 3 | * | NONE | CMOS_OUT | SCSI_Out(0) | - | 4 | * | NONE | CMOS_OUT | SCSI_Out_DBx(7) | - | 5 | * | NONE | CMOS_OUT | SCSI_Out_DBx(6) | - | 6 | * | NONE | CMOS_OUT | SCSI_Out_DBx(5) | - | 7 | * | NONE | CMOS_OUT | SCSI_Out_DBx(4) | ------+-----+-------+-----------+------------------+-----------------+------------------------- - 6 | 0 | * | NONE | CMOS_OUT | SCSI_Out_DBx(3) | - | 1 | * | NONE | CMOS_OUT | SCSI_Out_DBx(2) | - | 2 | * | NONE | CMOS_OUT | SCSI_Out_DBx(1) | - | 3 | * | NONE | CMOS_OUT | SCSI_Out_DBx(0) | ------+-----+-------+-----------+------------------+-----------------+------------------------- - 15 | 6 | * | FALLING | HI_Z_ANALOG | \USBFS:Dp(0)\ | Analog(\USBFS:Net_1000\) - | 7 | * | NONE | HI_Z_ANALOG | \USBFS:Dm(0)\ | Analog(\USBFS:Net_597\) ----------------------------------------------------------------------------------------------- - - - -Digital component placer commit/Report: Elapsed time ==> 0s.014ms -Digital Placement phase: Elapsed time ==> 2s.172ms - - -Routing successful. -Digital Routing phase: Elapsed time ==> 3s.093ms - - -Bitstream and API generation phase: Elapsed time ==> 0s.702ms - - -Bitstream verification phase: Elapsed time ==> 0s.140ms - - -Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.719ms - - -Data reporting phase: Elapsed time ==> 0s.000ms - - -Design database save phase: Elapsed time ==> 0s.406ms - -cydsfit: Elapsed time ==> 8s.765ms - -Fitter phase: Elapsed time ==> 8s.859ms -API generation phase: Elapsed time ==> 3s.296ms -Dependency generation phase: Elapsed time ==> 0s.016ms -Cleanup phase: Elapsed time ==> 0s.047ms diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rt_log b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rt_log deleted file mode 100755 index cbf8613..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.rt_log +++ /dev/null @@ -1,22 +0,0 @@ - - SoftJin Router, Version 1.0 - -I1203: Reading Design USB_Bootloader -I1204: Reading netlist from file USB_Bootloader_r.vh2 -I1206: Completed Reading of file USB_Bootloader_r.vh2 -I1204: Reading placement from file USB_Bootloader.pco -I1206: Completed Reading of file USB_Bootloader.pco -I1204: Reading timing library from file USB_Bootloader_r.lib -I1206: Completed Reading of file USB_Bootloader_r.lib -I1204: Reading timing constraints from file USB_Bootloader.sdc -I1206: Completed Reading of file USB_Bootloader.sdc -I1204: Reading architecture from file C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc5/psoc5lp/route_arch-rrg.cydata -I1206: Completed Reading of file C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\dev/psoc5/psoc5lp/route_arch-rrg.cydata -I1209: Started routing -I1223: Total Nets : 8 -I1212: Iteration 1 : 0 unrouted : 0 seconds -I1215: Routing is successful -I1207: Completed routing -I1210: Writing routes -I1218: Exiting the router -I1224: Total Time : 2 seconds diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc deleted file mode 100755 index 9b30340..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdc +++ /dev/null @@ -1,14 +0,0 @@ -# THIS FILE IS AUTOMATICALLY GENERATED -# Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -# Date: Sat, 22 Mar 2014 12:32:56 GMT -#set_units -time ns -create_clock -name {CyIMO} -period 41.666666666666664 -waveform {0 20.8333333333333} [list [get_pins {ClockBlock/imo}]] -create_clock -name {CyPLL_OUT} -period 15.625 -waveform {0 7.8125} [list [get_pins {ClockBlock/pllout}]] -create_clock -name {CyILO} -period 10000 -waveform {0 5000} [list [get_pins {ClockBlock/ilo}] [get_pins {ClockBlock/clk_100k}] [get_pins {ClockBlock/clk_1k}] [get_pins {ClockBlock/clk_32k}]] -create_clock -name {CyMASTER_CLK} -period 15.625 -waveform {0 7.8125} [list [get_pins {ClockBlock/clk_sync}]] -create_generated_clock -name {CyBUS_CLK} -source [get_pins {ClockBlock/clk_sync}] -edges {1 2 3} [list [get_pins {ClockBlock/clk_bus_glb}]] - - -# Component constraints for W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch -# Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -# Date: Sat, 22 Mar 2014 12:32:47 GMT diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf deleted file mode 100755 index 97e1414..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.sdf +++ /dev/null @@ -1,61 +0,0 @@ -(DELAYFILE - (SDFVERSION "IEEE 1497 4.0") - (DATE "2014-03-22T12:32:56Z") - (DESIGN "USB_Bootloader") - (VENDOR "Cypress Semiconductor") - (PROGRAM "cydsfit") - (VERSION "No Version Information Found") - (DIVIDER .) - (TIMESCALE 1 ns) - (CELL - (CELLTYPE "USB_Bootloader") - (INSTANCE *) - (DELAY - (ABSOLUTE - (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(0\).in_clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:arb_int\\.clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(1\).in_clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(2\).in_clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(3\).in_clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb SD_PULLUP\(4\).in_clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:Dp\(0\)\\.in_clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:bus_reset\\.clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:dp_int\\.clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:ep_0\\.clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:ep_1\\.clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:ep_2\\.clock (0.000:0.000:0.000)) - (INTERCONNECT ClockBlock.clk_bus_glb \\USBFS\:sof_int\\.clock (0.000:0.000:0.000)) - (INTERCONNECT \\USBFS\:USB\\.sof_int \\USBFS\:sof_int\\.interrupt (1.000:1.000:1.000)) - (INTERCONNECT \\USBFS\:Dp\\.interrupt \\USBFS\:dp_int\\.interrupt (1.000:1.000:1.000)) - (INTERCONNECT \\USBFS\:USB\\.arb_int \\USBFS\:arb_int\\.interrupt (1.000:1.000:1.000)) - (INTERCONNECT \\USBFS\:USB\\.usb_int \\USBFS\:bus_reset\\.interrupt (1.000:1.000:1.000)) - (INTERCONNECT \\USBFS\:USB\\.ept_int_0 \\USBFS\:ep_0\\.interrupt (1.000:1.000:1.000)) - (INTERCONNECT \\USBFS\:USB\\.ept_int_1 \\USBFS\:ep_1\\.interrupt (9.058:9.058:9.058)) - (INTERCONNECT \\USBFS\:USB\\.ept_int_2 \\USBFS\:ep_2\\.interrupt (9.092:9.092:9.092)) - (INTERCONNECT SCSI_Out\(0\)_PAD SCSI_Out\(0\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(1\)_PAD SCSI_Out\(1\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(2\)_PAD SCSI_Out\(2\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(3\)_PAD SCSI_Out\(3\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(4\)_PAD SCSI_Out\(4\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(5\)_PAD SCSI_Out\(5\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(6\)_PAD SCSI_Out\(6\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(7\)_PAD SCSI_Out\(7\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(8\)_PAD SCSI_Out\(8\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out\(9\)_PAD SCSI_Out\(9\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(0\)_PAD SCSI_Out_DBx\(0\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(1\)_PAD SCSI_Out_DBx\(1\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(2\)_PAD SCSI_Out_DBx\(2\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(3\)_PAD SCSI_Out_DBx\(3\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(4\)_PAD SCSI_Out_DBx\(4\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(5\)_PAD SCSI_Out_DBx\(5\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(6\)_PAD SCSI_Out_DBx\(6\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SCSI_Out_DBx\(7\)_PAD SCSI_Out_DBx\(7\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SD_PULLUP\(0\)_PAD SD_PULLUP\(0\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SD_PULLUP\(1\)_PAD SD_PULLUP\(1\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SD_PULLUP\(2\)_PAD SD_PULLUP\(2\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SD_PULLUP\(3\)_PAD SD_PULLUP\(3\).pad_in (0.000:0.000:0.000)) - (INTERCONNECT SD_PULLUP\(4\)_PAD SD_PULLUP\(4\).pad_in (0.000:0.000:0.000)) - ) - ) - ) -) diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.svd b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.svd deleted file mode 100755 index 2171fc7..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.svd +++ /dev/null @@ -1,494 +0,0 @@ - - - CY8C5267AXI_LP051 - 0.1 - CY8C52LP - 8 - 32 - - - USBFS - USBFS - 0x40004394 - - 0 - 0x1D0A - registers - - - - USBFS_PM_USB_CR0 - USB Power Mode Control Register 0 - 0x0 - 8 - read-write - 0 - 0 - - - fsusbio_ref_en - No description available - 0 - 0 - read-write - - - fsusbio_pd_n - No description available - 1 - 1 - read-write - - - fsusbio_pd_pullup_n - No description available - 2 - 2 - read-write - - - - - USBFS_PM_ACT_CFG - Active Power Mode Configuration Register - 0x11 - 8 - read-write - 0 - 0 - - - USBFS_PM_STBY_CFG - Standby Power Mode Configuration Register - 0x21 - 8 - read-write - 0 - 0 - - - USBFS_PRT_PS - Port Pin State Register - 0xE5D - 8 - read-write - 0 - 0 - - - PinState_DP - No description available - 6 - 6 - read-only - - - PinState_DM - No description available - 7 - 7 - read-only - - - - - USBFS_PRT_DM0 - Port Drive Mode Register - 0xE5E - 8 - read-write - 0 - 0 - - - DriveMode_DP - No description available - 6 - 6 - read-write - - - DriveMode_DM - No description available - 7 - 7 - read-write - - - - - USBFS_PRT_DM1 - Port Drive Mode Register - 0xE5F - 8 - read-write - 0 - 0 - - - PullUp_en_DP - No description available - 6 - 6 - read-write - - - PullUp_en_DM - No description available - 7 - 7 - read-write - - - - - USBFS_PRT_INP_DIS - Input buffer disable override - 0xE64 - 8 - read-write - 0 - 0 - - - seinput_dis_dp - No description available - 6 - 6 - read-write - - - seinput_dis_dm - No description available - 7 - 7 - read-write - - - - - USBFS_EP0_DR0 - bmRequestType - 0x1C6C - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR1 - bRequest - 0x1C6D - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR2 - wValueLo - 0x1C6E - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR3 - wValueHi - 0x1C6F - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR4 - wIndexLo - 0x1C70 - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR5 - wIndexHi - 0x1C71 - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR6 - lengthLo - 0x1C72 - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR7 - lengthHi - 0x1C73 - 8 - read-write - 0 - 0 - - - USBFS_CR0 - USB Control Register 0 - 0x1C74 - 8 - read-write - 0 - 0 - - - device_address - No description available - 6 - 0 - read-only - - - usb_enable - No description available - 7 - 7 - read-write - - - - - USBFS_CR1 - USB Control Register 1 - 0x1C75 - 8 - read-write - 0 - 0 - - - reg_enable - No description available - 0 - 0 - read-write - - - enable_lock - No description available - 1 - 1 - read-write - - - bus_activity - No description available - 2 - 2 - read-write - - - trim_offset_msb - No description available - 3 - 3 - read-write - - - - - USBFS_SIE_EP1_CR0 - The Endpoint1 Control Register - 0x1C7A - 8 - read-write - 0 - 0 - - - USBFS_USBIO_CR0 - USBIO Control Register 0 - 0x1C7C - 8 - read-write - 0 - 0 - - - rd - No description available - 0 - 0 - read-only - - - td - No description available - 5 - 5 - read-write - - - tse0 - No description available - 6 - 6 - read-write - - - ten - No description available - 7 - 7 - read-write - - - - - USBFS_USBIO_CR1 - USBIO Control Register 1 - 0x1C7E - 8 - read-write - 0 - 0 - - - dmo - No description available - 0 - 0 - read-only - - - dpo - No description available - 1 - 1 - read-only - - - usbpuen - No description available - 2 - 2 - read-write - - - iomode - No description available - 5 - 5 - read-write - - - - - USBFS_SIE_EP2_CR0 - The Endpoint2 Control Register - 0x1C8A - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP3_CR0 - The Endpoint3 Control Register - 0x1C9A - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP4_CR0 - The Endpoint4 Control Register - 0x1CAA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP5_CR0 - The Endpoint5 Control Register - 0x1CBA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP6_CR0 - The Endpoint6 Control Register - 0x1CCA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP7_CR0 - The Endpoint7 Control Register - 0x1CDA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP8_CR0 - The Endpoint8 Control Register - 0x1CEA - 8 - read-write - 0 - 0 - - - USBFS_BUF_SIZE - Dedicated Endpoint Buffer Size Register - 0x1CF8 - 8 - read-write - 0 - 0 - - - USBFS_EP_ACTIVE - Endpoint Active Indication Register - 0x1CFA - 8 - read-write - 0 - 0 - - - USBFS_EP_TYPE - Endpoint Type (IN/OUT) Indication - 0x1CFB - 8 - read-write - 0 - 0 - - - USBFS_USB_CLK_EN - USB Block Clock Enable Register - 0x1D09 - 8 - read-write - 0 - 0 - - - - - \ No newline at end of file diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.tr b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.tr deleted file mode 100755 index b1f0bab..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.tr +++ /dev/null @@ -1,98 +0,0 @@ -##################################################################### - Table of Contents -===================================================================== - 1::Clock Frequency Summary - 2::Clock Relationship Summary - 3::Datasheet Report - 3.1::Setup to Clock - 3.2::Clock to Out - 3.3::Pad to Pad - 4::Path Details for Clock Frequency Summary - 5::Path Details for Clock Relationship Summary -===================================================================== - End of Table of Contents -##################################################################### - -##################################################################### - 1::Clock Frequency Summary -===================================================================== -Number of clocks: 5 -Clock: CyBUS_CLK | N/A | Target: 64.00 MHz | -Clock: CyILO | N/A | Target: 0.10 MHz | -Clock: CyIMO | N/A | Target: 24.00 MHz | -Clock: CyMASTER_CLK | N/A | Target: 64.00 MHz | -Clock: CyPLL_OUT | N/A | Target: 64.00 MHz | - - ===================================================================== - End of Clock Frequency Summary - ##################################################################### - - - ##################################################################### - 2::Clock Relationship Summary - ===================================================================== - -Launch Clock Capture Clock Constraint(R-R) Slack(R-R) Constraint(R-F) Slack(R-F) Constraint(F-F) Slack(F-F) Constraint(F-R) Slack(F-R) - - ===================================================================== - End of Clock Relationship Summary - ##################################################################### - - - ##################################################################### - 3::Datasheet Report - -All values are in Picoseconds - ===================================================================== - -3.1::Setup to Clock -------------------- - -Port Name Setup to Clk Clock Name:Phase ---------- ------------ ---------------- - - ------------------------3.2::Clock to Out ----------------------------------------- - -Port Name Clock to Out Clock Name:Phase ---------- ------------ ---------------- - - --------------------------3.3::Pad to Pad ----------------------------------------- - -Port Name (Source) Port Name (Destination) Delay ------------------- ----------------------- ----- - -===================================================================== - End of Datasheet Report -##################################################################### -##################################################################### - 4::Path Details for Clock Frequency Summary - -===================================================================== - End of Path Details for Clock Frequency Summary -##################################################################### - - -##################################################################### - 5::Path Details for Clock Relationship Summary -===================================================================== - - -===================================================================== - End of Path Details for Clock Relationship Summary -##################################################################### - -##################################################################### - Detailed Report for all timing paths -===================================================================== -===================================================================== - End of Detailed Report for all timing paths -##################################################################### - -##################################################################### - End of Timing Report -##################################################################### - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v deleted file mode 100755 index ad431b1..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.v +++ /dev/null @@ -1,539 +0,0 @@ -// ====================================================================== -// USB_Bootloader.v generated from TopDesign.cysch -// 03/22/2014 at 22:32 -// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!! -// ====================================================================== - -/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */ -`define CYDEV_CHIP_DIE_LEOPARD 1 -`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3 -`define CYDEV_CHIP_REV_LEOPARD_ES3 3 -`define CYDEV_CHIP_REV_LEOPARD_ES2 1 -`define CYDEV_CHIP_REV_LEOPARD_ES1 0 -`define CYDEV_CHIP_DIE_PSOC4A 2 -`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17 -`define CYDEV_CHIP_REV_PSOC4A_ES0 17 -`define CYDEV_CHIP_DIE_PANTHER 3 -`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1 -`define CYDEV_CHIP_REV_PANTHER_ES1 1 -`define CYDEV_CHIP_REV_PANTHER_ES0 0 -`define CYDEV_CHIP_DIE_PSOC5LP 4 -`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0 -`define CYDEV_CHIP_REV_PSOC5LP_ES0 0 -`define CYDEV_CHIP_DIE_EXPECT 4 -`define CYDEV_CHIP_REV_EXPECT 0 -`define CYDEV_CHIP_DIE_ACTUAL 4 -/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */ -`define CYDEV_CHIP_FAMILY_UNKNOWN 0 -`define CYDEV_CHIP_MEMBER_UNKNOWN 0 -`define CYDEV_CHIP_FAMILY_PSOC3 1 -`define CYDEV_CHIP_MEMBER_3A 1 -`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3 -`define CYDEV_CHIP_REVISION_3A_ES3 3 -`define CYDEV_CHIP_REVISION_3A_ES2 1 -`define CYDEV_CHIP_REVISION_3A_ES1 0 -`define CYDEV_CHIP_FAMILY_PSOC4 2 -`define CYDEV_CHIP_MEMBER_4A 2 -`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17 -`define CYDEV_CHIP_REVISION_4A_ES0 17 -`define CYDEV_CHIP_FAMILY_PSOC5 3 -`define CYDEV_CHIP_MEMBER_5A 3 -`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1 -`define CYDEV_CHIP_REVISION_5A_ES1 1 -`define CYDEV_CHIP_REVISION_5A_ES0 0 -`define CYDEV_CHIP_MEMBER_5B 4 -`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0 -`define CYDEV_CHIP_REVISION_5B_ES0 0 -`define CYDEV_CHIP_FAMILY_USED 3 -`define CYDEV_CHIP_MEMBER_USED 4 -`define CYDEV_CHIP_REVISION_USED 0 -// USBFS_v2_60(AudioDescriptors= , CDCDescriptors= , DeviceDescriptors= DEVICE 18 75 76 Cypress Semiconductor PSoC3 Bootloader 0001 0 0 0 0 1204 46877 12289 1 2 0 1 0 0 CONFIGURATION 9 0 41 1 0 0 128 0 ALTERNATE 0 INTERFACE 9 76 3 2 0 0 2 PSoC3 Bootloader ENDPOINT 7 false 1 1 3 64 HID 9 1 55 0 0 1 34 36 ENDPOINT 7 false 1 130 3 64 , EnableCDCApi=true, EnableMidiApi=true, endpointMA=0, endpointMM=0, extern_cls=false, extern_vbus=false, extern_vnd=false, extJackCount=0, HIDReportDescriptors= HID_REPORT 2 Generic HID 36 HID_REPORT_ITEM 1 (Generic Desktop Controls) 5 1 List HID_REPORT_ITEM 1 (Undefined) 9 0 List HID_REPORT_ITEM 1 (Physical) 161 0 List HID_REPORT_ITEM 1 (Undefined) 9 0 List HID_REPORT_ITEM 1 (Physical) 161 0 List HID_REPORT_ITEM 1 (Undefined) 9 0 List HID_REPORT_ITEM 1 21 0 Int HID_REPORT_ITEM 1 37 255 Int HID_REPORT_ITEM 1 117 8 Int HID_REPORT_ITEM 1 149 64 Int HID_REPORT_ITEM 1 (Var) 145 2 Bits HID_REPORT_ITEM 1 (Undefined) 9 0 List HID_REPORT_ITEM 1 21 0 Int HID_REPORT_ITEM 1 37 255 Int HID_REPORT_ITEM 1 117 8 Int HID_REPORT_ITEM 1 149 64 Int HID_REPORT_ITEM 1 (Var) 129 2 Bits HID_REPORT_ITEM 1 192 None HID_REPORT_ITEM 1 192 None , max_interfaces_num=1, MidiDescriptors= , Mode=false, mon_vbus=false, out_sof=false, Pid=F232, rm_arb_int=false, rm_dma_1=true, rm_dma_2=true, rm_dma_3=true, rm_dma_4=true, rm_dma_5=true, rm_dma_6=true, rm_dma_7=true, rm_dma_8=true, rm_dp_int=false, rm_ep_isr_0=false, rm_ep_isr_1=false, rm_ep_isr_2=false, rm_ep_isr_3=true, rm_ep_isr_4=true, rm_ep_isr_5=true, rm_ep_isr_6=true, rm_ep_isr_7=true, rm_ep_isr_8=true, rm_ord_int=true, rm_sof_int=false, rm_usb_int=false, StringDescriptors= STRING 4 1033 STRING 44 USER_ENTERED_TEXT Cypress Semiconductor false STRING 34 USER_ENTERED_TEXT PSoC3 Bootloader false STRING 10 USER_ENTERED_TEXT 0001 true STRING 16 USER_ENTERED_TEXT MSFT100 false , Vid=04B4, CY_COMPONENT_NAME=USBFS_v2_60, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=USBFS, CY_INSTANCE_SHORT_NAME=USBFS, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=60, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=USBFS, ) -module USBFS_v2_60_0 ( - sof, - vbusdet); - output sof; - input vbusdet; - - - wire [7:0] dma_req; - wire [8:0] ept_int; - wire Net_1106; - wire [7:0] Net_1105; - wire Net_1104; - wire Net_1103; - wire Net_1102; - wire Net_1101; - wire Net_1100; - wire Net_1099; - wire Net_1098; - wire Net_1097; - wire Net_1096; - wire Net_1013; - wire Net_1014; - wire Net_1015; - wire Net_1016; - wire Net_1017; - wire Net_1018; - wire Net_1019; - wire Net_1020; - wire Net_1010; - electrical Net_1000; - wire Net_79; - wire Net_81; - wire Net_95; - electrical Net_597; - wire Net_824; - - cy_psoc3_usb_v1_0 USB ( - .dp(Net_1000), - .dm(Net_597), - .sof_int(sof), - .arb_int(Net_79), - .usb_int(Net_81), - .ept_int(ept_int[8:0]), - .ord_int(Net_95), - .dma_req(dma_req[7:0]), - .dma_termin(Net_824)); - - - cy_isr_v1_0 - #(.int_type(2'b10)) - sof_int - (.int_signal(sof)); - - - - cy_isr_v1_0 - #(.int_type(2'b10)) - arb_int - (.int_signal(Net_79)); - - - - cy_isr_v1_0 - #(.int_type(2'b10)) - bus_reset - (.int_signal(Net_81)); - - - - cy_isr_v1_0 - #(.int_type(2'b10)) - ep_0 - (.int_signal(ept_int[0:0])); - - - - cy_isr_v1_0 - #(.int_type(2'b10)) - ep_1 - (.int_signal(ept_int[1:1])); - - - - cy_isr_v1_0 - #(.int_type(2'b10)) - ep_2 - (.int_signal(ept_int[2:2])); - - - wire [0:0] tmpOE__Dm_net; - wire [0:0] tmpFB_0__Dm_net; - wire [0:0] tmpIO_0__Dm_net; - wire [0:0] tmpINTERRUPT_0__Dm_net; - electrical [0:0] tmpSIOVREF__Dm_net; - - cy_psoc3_pins_v1_10 - #(.id("f9248435-5d3e-4e4d-bbae-bdae8795c3dd/8b77a6c4-10a0-4390-971c-672353e2a49c"), - .drive_mode(3'b000), - .ibuf_enabled(1'b0), - .init_dr_st(1'b0), - .input_clk_en(0), - .input_sync(1'b1), - .input_sync_mode(1'b0), - .intr_mode(2'b00), - .invert_in_clock(0), - .invert_in_clock_en(0), - .invert_in_reset(0), - .invert_out_clock(0), - .invert_out_clock_en(0), - .invert_out_reset(0), - .io_voltage(""), - .layout_mode("NONCONTIGUOUS"), - .oe_conn(1'b0), - .oe_reset(0), - .oe_sync(1'b0), - .output_clk_en(0), - .output_clock_mode(1'b0), - .output_conn(1'b0), - .output_mode(1'b0), - .output_reset(0), - .output_sync(1'b0), - .pa_in_clock(-1), - .pa_in_clock_en(-1), - .pa_in_reset(-1), - .pa_out_clock(-1), - .pa_out_clock_en(-1), - .pa_out_reset(-1), - .pin_aliases(""), - .pin_mode("A"), - .por_state(4), - .use_annotation(1'b0), - .sio_group_cnt(0), - .sio_hyst(1'b0), - .sio_ibuf(""), - .sio_info(2'b00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(1'b0), - .spanning(1), - .vtrip(2'b10), - .width(1)) - Dm - (.oe(tmpOE__Dm_net), - .y({1'b0}), - .fb({tmpFB_0__Dm_net[0:0]}), - .analog({Net_597}), - .io({tmpIO_0__Dm_net[0:0]}), - .siovref(tmpSIOVREF__Dm_net), - .interrupt({tmpINTERRUPT_0__Dm_net[0:0]}), - .in_clock({1'b0}), - .in_clock_en({1'b1}), - .in_reset({1'b0}), - .out_clock({1'b0}), - .out_clock_en({1'b1}), - .out_reset({1'b0})); - - assign tmpOE__Dm_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; - - wire [0:0] tmpOE__Dp_net; - wire [0:0] tmpFB_0__Dp_net; - wire [0:0] tmpIO_0__Dp_net; - electrical [0:0] tmpSIOVREF__Dp_net; - - cy_psoc3_pins_v1_10 - #(.id("f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42"), - .drive_mode(3'b000), - .ibuf_enabled(1'b0), - .init_dr_st(1'b0), - .input_clk_en(0), - .input_sync(1'b1), - .input_sync_mode(1'b0), - .intr_mode(2'b10), - .invert_in_clock(0), - .invert_in_clock_en(0), - .invert_in_reset(0), - .invert_out_clock(0), - .invert_out_clock_en(0), - .invert_out_reset(0), - .io_voltage(""), - .layout_mode("CONTIGUOUS"), - .oe_conn(1'b0), - .oe_reset(0), - .oe_sync(1'b0), - .output_clk_en(0), - .output_clock_mode(1'b0), - .output_conn(1'b0), - .output_mode(1'b0), - .output_reset(0), - .output_sync(1'b0), - .pa_in_clock(-1), - .pa_in_clock_en(-1), - .pa_in_reset(-1), - .pa_out_clock(-1), - .pa_out_clock_en(-1), - .pa_out_reset(-1), - .pin_aliases(""), - .pin_mode("I"), - .por_state(4), - .use_annotation(1'b0), - .sio_group_cnt(0), - .sio_hyst(1'b0), - .sio_ibuf(""), - .sio_info(2'b00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(1'b0), - .spanning(0), - .vtrip(2'b00), - .width(1)) - Dp - (.oe(tmpOE__Dp_net), - .y({1'b0}), - .fb({tmpFB_0__Dp_net[0:0]}), - .analog({Net_1000}), - .io({tmpIO_0__Dp_net[0:0]}), - .siovref(tmpSIOVREF__Dp_net), - .interrupt({Net_1010}), - .in_clock({1'b0}), - .in_clock_en({1'b1}), - .in_reset({1'b0}), - .out_clock({1'b0}), - .out_clock_en({1'b1}), - .out_reset({1'b0})); - - assign tmpOE__Dp_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1}; - - - cy_isr_v1_0 - #(.int_type(2'b10)) - dp_int - (.int_signal(Net_1010)); - - - - cy_clock_v1_0 - #(.id("f9248435-5d3e-4e4d-bbae-bdae8795c3dd/03f503a7-085a-4304-b786-de885b1c2f21"), - .source_clock_id("75C2148C-3656-4d8a-846D-0CAE99AB6FF7"), - .divisor(0), - .period("0"), - .is_direct(1), - .is_digital(1)) - Clock_vbus - (.clock_out(Net_1099)); - - - - -endmodule - -// top -module top ; - - wire Net_88; - wire Net_87; - wire Net_86; - wire Net_85; - wire Net_84; - electrical Net_36; - electrical Net_35; - electrical Net_34; - electrical Net_33; - electrical Net_32; - electrical Net_31; - electrical Net_30; - electrical Net_29; - electrical Net_28; - electrical Net_27; - electrical [7:0] Net_37; - wire Net_41; - wire Net_40; - - USBFS_v2_60_0 USBFS ( - .sof(Net_40), - .vbusdet(1'b0)); - - wire [7:0] tmpOE__SCSI_Out_DBx_net; - wire [7:0] tmpFB_7__SCSI_Out_DBx_net; - wire [7:0] tmpIO_7__SCSI_Out_DBx_net; - wire [0:0] tmpINTERRUPT_0__SCSI_Out_DBx_net; - electrical [0:0] tmpSIOVREF__SCSI_Out_DBx_net; - - cy_psoc3_pins_v1_10 - #(.id("52f31aa9-2f0a-497d-9a1f-1424095e13e6"), - .drive_mode(24'b110_110_110_110_110_110_110_110), - .ibuf_enabled(8'b1_1_1_1_1_1_1_1), - .init_dr_st(8'b0_0_0_0_0_0_0_0), - .input_clk_en(0), - .input_sync(8'b1_1_1_1_1_1_1_1), - .input_sync_mode(8'b0_0_0_0_0_0_0_0), - .intr_mode(16'b00_00_00_00_00_00_00_00), - .invert_in_clock(0), - .invert_in_clock_en(0), - .invert_in_reset(0), - .invert_out_clock(0), - .invert_out_clock_en(0), - .invert_out_reset(0), - .io_voltage(", , , , , , , 5"), - .layout_mode("NONCONTIGUOUS"), - .oe_conn(8'b0_0_0_0_0_0_0_0), - .oe_reset(0), - .oe_sync(8'b0_0_0_0_0_0_0_0), - .output_clk_en(0), - .output_clock_mode(8'b0_0_0_0_0_0_0_0), - .output_conn(8'b0_0_0_0_0_0_0_0), - .output_mode(8'b0_0_0_0_0_0_0_0), - .output_reset(0), - .output_sync(8'b0_0_0_0_0_0_0_0), - .pa_in_clock(-1), - .pa_in_clock_en(-1), - .pa_in_reset(-1), - .pa_out_clock(-1), - .pa_out_clock_en(-1), - .pa_out_reset(-1), - .pin_aliases("DB0,DB1,DB2,DB3,DB4,DB5,DB6,DB7"), - .pin_mode("OOOOOOOO"), - .por_state(4), - .use_annotation(8'b1_1_1_1_1_1_1_1), - .sio_group_cnt(0), - .sio_hyst(8'b0_0_0_0_0_0_0_0), - .sio_ibuf(""), - .sio_info(16'b00_00_00_00_00_00_00_00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(8'b0_0_0_0_0_0_0_0), - .spanning(1), - .vtrip(16'b10_10_10_10_10_10_10_10), - .width(8)) - SCSI_Out_DBx - (.oe(tmpOE__SCSI_Out_DBx_net), - .y({8'b0}), - .fb({tmpFB_7__SCSI_Out_DBx_net[7:0]}), - .io({tmpIO_7__SCSI_Out_DBx_net[7:0]}), - .siovref(tmpSIOVREF__SCSI_Out_DBx_net), - .interrupt({tmpINTERRUPT_0__SCSI_Out_DBx_net[0:0]}), - .annotation({Net_37[7:0]}), - .in_clock({1'b0}), - .in_clock_en({1'b1}), - .in_reset({1'b0}), - .out_clock({1'b0}), - .out_clock_en({1'b1}), - .out_reset({1'b0})); - - assign tmpOE__SCSI_Out_DBx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{8'b11111111} : {8'b11111111}; - - wire [9:0] tmpOE__SCSI_Out_net; - wire [9:0] tmpFB_9__SCSI_Out_net; - wire [9:0] tmpIO_9__SCSI_Out_net; - wire [0:0] tmpINTERRUPT_0__SCSI_Out_net; - electrical [0:0] tmpSIOVREF__SCSI_Out_net; - - cy_psoc3_pins_v1_10 - #(.id("11f071e8-9c92-47e0-872a-3f48765a75b8"), - .drive_mode(30'b110_110_110_110_110_110_110_110_110_110), - .ibuf_enabled(10'b1_1_1_1_1_1_1_1_1_1), - .init_dr_st(10'b0_0_0_0_0_0_0_0_0_0), - .input_clk_en(0), - .input_sync(10'b1_1_1_1_1_1_1_1_1_1), - .input_sync_mode(10'b0_0_0_0_0_0_0_0_0_0), - .intr_mode(20'b00_00_00_00_00_00_00_00_00_00), - .invert_in_clock(0), - .invert_in_clock_en(0), - .invert_in_reset(0), - .invert_out_clock(0), - .invert_out_clock_en(0), - .invert_out_reset(0), - .io_voltage("5, 5, 5, 5, 5, 5, 5, 5, 5, 5"), - .layout_mode("NONCONTIGUOUS"), - .oe_conn(10'b0_0_0_0_0_0_0_0_0_0), - .oe_reset(0), - .oe_sync(10'b0_0_0_0_0_0_0_0_0_0), - .output_clk_en(0), - .output_clock_mode(10'b0_0_0_0_0_0_0_0_0_0), - .output_conn(10'b0_0_0_0_0_0_0_0_0_0), - .output_mode(10'b0_0_0_0_0_0_0_0_0_0), - .output_reset(0), - .output_sync(10'b0_0_0_0_0_0_0_0_0_0), - .pa_in_clock(-1), - .pa_in_clock_en(-1), - .pa_in_reset(-1), - .pa_out_clock(-1), - .pa_out_clock_en(-1), - .pa_out_reset(-1), - .pin_aliases("DBP_raw,ATN,BSY,ACK,RST,MSG,SEL,CD,REQ,IO_raw"), - .pin_mode("OOOOOOOOOO"), - .por_state(4), - .use_annotation(10'b1_1_1_1_1_1_1_1_1_1), - .sio_group_cnt(0), - .sio_hyst(10'b0_0_0_0_0_0_0_0_0_0), - .sio_ibuf(""), - .sio_info(20'b00_00_00_00_00_00_00_00_00_00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(10'b0_0_0_0_0_0_0_0_0_0), - .spanning(1), - .vtrip(20'b10_10_10_10_10_10_10_10_10_10), - .width(10)) - SCSI_Out - (.oe(tmpOE__SCSI_Out_net), - .y({10'b0}), - .fb({tmpFB_9__SCSI_Out_net[9:0]}), - .io({tmpIO_9__SCSI_Out_net[9:0]}), - .siovref(tmpSIOVREF__SCSI_Out_net), - .interrupt({tmpINTERRUPT_0__SCSI_Out_net[0:0]}), - .annotation({Net_36, Net_35, Net_34, Net_33, Net_32, Net_31, Net_30, Net_29, Net_28, Net_27}), - .in_clock({1'b0}), - .in_clock_en({1'b1}), - .in_reset({1'b0}), - .out_clock({1'b0}), - .out_clock_en({1'b1}), - .out_reset({1'b0})); - - assign tmpOE__SCSI_Out_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{10'b1111111111} : {10'b1111111111}; - - wire [4:0] tmpOE__SD_PULLUP_net; - wire [4:0] tmpIO_4__SD_PULLUP_net; - wire [0:0] tmpINTERRUPT_0__SD_PULLUP_net; - electrical [0:0] tmpSIOVREF__SD_PULLUP_net; - - cy_psoc3_pins_v1_10 - #(.id("4c15b41e-e284-4978-99e7-5aaee19bd0ce"), - .drive_mode(15'b010_010_010_010_010), - .ibuf_enabled(5'b1_1_1_1_1), - .init_dr_st(5'b1_1_1_1_1), - .input_clk_en(0), - .input_sync(5'b1_1_1_1_1), - .input_sync_mode(5'b0_0_0_0_0), - .intr_mode(10'b00_00_00_00_00), - .invert_in_clock(0), - .invert_in_clock_en(0), - .invert_in_reset(0), - .invert_out_clock(0), - .invert_out_clock_en(0), - .invert_out_reset(0), - .io_voltage("3.3, , , , "), - .layout_mode("CONTIGUOUS"), - .oe_conn(5'b0_0_0_0_0), - .oe_reset(0), - .oe_sync(5'b0_0_0_0_0), - .output_clk_en(0), - .output_clock_mode(5'b0_0_0_0_0), - .output_conn(5'b0_0_0_0_0), - .output_mode(5'b0_0_0_0_0), - .output_reset(0), - .output_sync(5'b0_0_0_0_0), - .pa_in_clock(-1), - .pa_in_clock_en(-1), - .pa_in_reset(-1), - .pa_out_clock(-1), - .pa_out_clock_en(-1), - .pa_out_reset(-1), - .pin_aliases(",,,,"), - .pin_mode("IIIII"), - .por_state(2), - .use_annotation(5'b0_0_0_0_0), - .sio_group_cnt(0), - .sio_hyst(5'b0_0_0_0_0), - .sio_ibuf(""), - .sio_info(10'b00_00_00_00_00), - .sio_obuf(""), - .sio_refsel(""), - .sio_vtrip(""), - .slew_rate(5'b0_0_0_0_0), - .spanning(0), - .vtrip(10'b00_00_00_00_00), - .width(5)) - SD_PULLUP - (.oe(tmpOE__SD_PULLUP_net), - .y({5'b0}), - .fb({Net_88, Net_87, Net_86, Net_85, Net_84}), - .io({tmpIO_4__SD_PULLUP_net[4:0]}), - .siovref(tmpSIOVREF__SD_PULLUP_net), - .interrupt({tmpINTERRUPT_0__SD_PULLUP_net[0:0]}), - .in_clock({1'b0}), - .in_clock_en({1'b1}), - .in_reset({1'b0}), - .out_clock({1'b0}), - .out_clock_en({1'b1}), - .out_reset({1'b0})); - - assign tmpOE__SD_PULLUP_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{5'b11111} : {5'b11111}; - - - -endmodule - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2 deleted file mode 100755 index bf8fbe5..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.vh2 +++ /dev/null @@ -1,546 +0,0 @@ --- --- Conversion of USB_Bootloader.v to vh2: --- --- Cypress Semiconductor - WARP Version 6.3 IR 41 --- Sat Mar 22 22:32:48 2014 --- - -USE cypress.cypress.all; -USE cypress.rtlpkg.all; -ENTITY top_RTL IS -ATTRIBUTE part_name of top_RTL:TYPE IS "cpsoc3"; -END top_RTL; --------------------------------------------------------- -ARCHITECTURE R_T_L OF top_RTL IS -TERMINAL \USBFS:Net_1000\ : bit; -TERMINAL \USBFS:Net_597\ : bit; -SIGNAL Net_40 : bit; -SIGNAL \USBFS:Net_79\ : bit; -SIGNAL \USBFS:Net_81\ : bit; -SIGNAL \USBFS:ept_int_8\ : bit; -SIGNAL \USBFS:ept_int_7\ : bit; -SIGNAL \USBFS:ept_int_6\ : bit; -SIGNAL \USBFS:ept_int_5\ : bit; -SIGNAL \USBFS:ept_int_4\ : bit; -SIGNAL \USBFS:ept_int_3\ : bit; -SIGNAL \USBFS:ept_int_2\ : bit; -SIGNAL \USBFS:ept_int_1\ : bit; -SIGNAL \USBFS:ept_int_0\ : bit; -SIGNAL \USBFS:Net_95\ : bit; -SIGNAL \USBFS:dma_req_7\ : bit; -SIGNAL \USBFS:dma_req_6\ : bit; -SIGNAL \USBFS:dma_req_5\ : bit; -SIGNAL \USBFS:dma_req_4\ : bit; -SIGNAL \USBFS:dma_req_3\ : bit; -SIGNAL \USBFS:dma_req_2\ : bit; -SIGNAL \USBFS:dma_req_1\ : bit; -SIGNAL \USBFS:dma_req_0\ : bit; -SIGNAL \USBFS:Net_824\ : bit; -SIGNAL \USBFS:tmpOE__Dm_net_0\ : bit; -SIGNAL zero : bit; -SIGNAL \USBFS:tmpFB_0__Dm_net_0\ : bit; -SIGNAL \USBFS:tmpIO_0__Dm_net_0\ : bit; -TERMINAL \USBFS:tmpSIOVREF__Dm_net_0\ : bit; -SIGNAL one : bit; -SIGNAL \USBFS:tmpINTERRUPT_0__Dm_net_0\ : bit; -SIGNAL \USBFS:tmpOE__Dp_net_0\ : bit; -SIGNAL \USBFS:tmpFB_0__Dp_net_0\ : bit; -SIGNAL \USBFS:tmpIO_0__Dp_net_0\ : bit; -TERMINAL \USBFS:tmpSIOVREF__Dp_net_0\ : bit; -SIGNAL \USBFS:Net_1010\ : bit; -SIGNAL \USBFS:Net_1099\ : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_7 : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_6 : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_5 : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_4 : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_3 : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_2 : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_1 : bit; -SIGNAL tmpOE__SCSI_Out_DBx_net_0 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_7 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_6 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_5 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_4 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_3 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_2 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_1 : bit; -SIGNAL tmpFB_7__SCSI_Out_DBx_net_0 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_7 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_6 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_5 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_4 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_3 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_2 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_1 : bit; -SIGNAL tmpIO_7__SCSI_Out_DBx_net_0 : bit; -TERMINAL tmpSIOVREF__SCSI_Out_DBx_net_0 : bit; -TERMINAL Net_37_7 : bit; -TERMINAL Net_37_6 : bit; -TERMINAL Net_37_5 : bit; -TERMINAL Net_37_4 : bit; -TERMINAL Net_37_3 : bit; -TERMINAL Net_37_2 : bit; -TERMINAL Net_37_1 : bit; -TERMINAL Net_37_0 : bit; -SIGNAL tmpINTERRUPT_0__SCSI_Out_DBx_net_0 : bit; -SIGNAL tmpOE__SCSI_Out_net_9 : bit; -SIGNAL tmpOE__SCSI_Out_net_8 : bit; -SIGNAL tmpOE__SCSI_Out_net_7 : bit; -SIGNAL tmpOE__SCSI_Out_net_6 : bit; -SIGNAL tmpOE__SCSI_Out_net_5 : bit; -SIGNAL tmpOE__SCSI_Out_net_4 : bit; -SIGNAL tmpOE__SCSI_Out_net_3 : bit; -SIGNAL tmpOE__SCSI_Out_net_2 : bit; -SIGNAL tmpOE__SCSI_Out_net_1 : bit; -SIGNAL tmpOE__SCSI_Out_net_0 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_9 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_8 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_7 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_6 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_5 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_4 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_3 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_2 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_1 : bit; -SIGNAL tmpFB_9__SCSI_Out_net_0 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_9 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_8 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_7 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_6 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_5 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_4 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_3 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_2 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_1 : bit; -SIGNAL tmpIO_9__SCSI_Out_net_0 : bit; -TERMINAL tmpSIOVREF__SCSI_Out_net_0 : bit; -TERMINAL Net_36 : bit; -TERMINAL Net_35 : bit; -TERMINAL Net_34 : bit; -TERMINAL Net_33 : bit; -TERMINAL Net_32 : bit; -TERMINAL Net_31 : bit; -TERMINAL Net_30 : bit; -TERMINAL Net_29 : bit; -TERMINAL Net_28 : bit; -TERMINAL Net_27 : bit; -SIGNAL tmpINTERRUPT_0__SCSI_Out_net_0 : bit; -SIGNAL tmpOE__SD_PULLUP_net_4 : bit; -SIGNAL tmpOE__SD_PULLUP_net_3 : bit; -SIGNAL tmpOE__SD_PULLUP_net_2 : bit; -SIGNAL tmpOE__SD_PULLUP_net_1 : bit; -SIGNAL tmpOE__SD_PULLUP_net_0 : bit; -SIGNAL Net_88 : bit; -SIGNAL Net_87 : bit; -SIGNAL Net_86 : bit; -SIGNAL Net_85 : bit; -SIGNAL Net_84 : bit; -SIGNAL tmpIO_4__SD_PULLUP_net_4 : bit; -SIGNAL tmpIO_4__SD_PULLUP_net_3 : bit; -SIGNAL tmpIO_4__SD_PULLUP_net_2 : bit; -SIGNAL tmpIO_4__SD_PULLUP_net_1 : bit; -SIGNAL tmpIO_4__SD_PULLUP_net_0 : bit; -TERMINAL tmpSIOVREF__SD_PULLUP_net_0 : bit; -SIGNAL tmpINTERRUPT_0__SD_PULLUP_net_0 : bit; -BEGIN - -zero <= ('0') ; - -one <= ('1') ; - -\USBFS:USB\:cy_psoc3_usb_v1_0 - GENERIC MAP(cy_registers=>"") - PORT MAP(dp=>\USBFS:Net_1000\, - dm=>\USBFS:Net_597\, - sof_int=>Net_40, - arb_int=>\USBFS:Net_79\, - usb_int=>\USBFS:Net_81\, - ept_int=>(\USBFS:ept_int_8\, \USBFS:ept_int_7\, \USBFS:ept_int_6\, \USBFS:ept_int_5\, - \USBFS:ept_int_4\, \USBFS:ept_int_3\, \USBFS:ept_int_2\, \USBFS:ept_int_1\, - \USBFS:ept_int_0\), - ord_int=>\USBFS:Net_95\, - dma_req=>(\USBFS:dma_req_7\, \USBFS:dma_req_6\, \USBFS:dma_req_5\, \USBFS:dma_req_4\, - \USBFS:dma_req_3\, \USBFS:dma_req_2\, \USBFS:dma_req_1\, \USBFS:dma_req_0\), - dma_termin=>\USBFS:Net_824\); -\USBFS:sof_int\:cy_isr_v1_0 - GENERIC MAP(int_type=>"10") - PORT MAP(int_signal=>Net_40); -\USBFS:arb_int\:cy_isr_v1_0 - GENERIC MAP(int_type=>"10") - PORT MAP(int_signal=>\USBFS:Net_79\); -\USBFS:bus_reset\:cy_isr_v1_0 - GENERIC MAP(int_type=>"10") - PORT MAP(int_signal=>\USBFS:Net_81\); -\USBFS:ep_0\:cy_isr_v1_0 - GENERIC MAP(int_type=>"10") - PORT MAP(int_signal=>\USBFS:ept_int_0\); -\USBFS:ep_1\:cy_isr_v1_0 - GENERIC MAP(int_type=>"10") - PORT MAP(int_signal=>\USBFS:ept_int_1\); -\USBFS:ep_2\:cy_isr_v1_0 - GENERIC MAP(int_type=>"10") - PORT MAP(int_signal=>\USBFS:ept_int_2\); -\USBFS:Dm\:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"f9248435-5d3e-4e4d-bbae-bdae8795c3dd/8b77a6c4-10a0-4390-971c-672353e2a49c", - drive_mode=>"000", - ibuf_enabled=>"0", - init_dr_st=>"0", - input_sync=>"1", - input_clk_en=>'0', - input_sync_mode=>"0", - intr_mode=>"00", - invert_in_clock=>'0', - invert_in_clock_en=>'0', - invert_in_reset=>'0', - invert_out_clock=>'0', - invert_out_clock_en=>'0', - invert_out_reset=>'0', - io_voltage=>"", - layout_mode=>"NONCONTIGUOUS", - output_conn=>"0", - output_sync=>"0", - output_clk_en=>'0', - output_mode=>"0", - output_reset=>'0', - output_clock_mode=>"0", - oe_sync=>"0", - oe_conn=>"0", - oe_reset=>'0', - pin_aliases=>"", - pin_mode=>"A", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0", - sio_ibuf=>"00000000", - sio_info=>"00", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0", - spanning=>'1', - sw_only=>'0', - vtrip=>"10", - width=>1, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"0", - pa_in_clock=>-1, - pa_in_clock_en=>-1, - pa_in_reset=>-1, - pa_out_clock=>-1, - pa_out_clock_en=>-1, - pa_out_reset=>-1) - PORT MAP(oe=>(one), - y=>(zero), - fb=>(\USBFS:tmpFB_0__Dm_net_0\), - analog=>\USBFS:Net_597\, - io=>(\USBFS:tmpIO_0__Dm_net_0\), - siovref=>(\USBFS:tmpSIOVREF__Dm_net_0\), - annotation=>(open), - in_clock=>zero, - in_clock_en=>one, - in_reset=>zero, - out_clock=>zero, - out_clock_en=>one, - out_reset=>zero, - interrupt=>\USBFS:tmpINTERRUPT_0__Dm_net_0\); -\USBFS:Dp\:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42", - drive_mode=>"000", - ibuf_enabled=>"0", - init_dr_st=>"0", - input_sync=>"1", - input_clk_en=>'0', - input_sync_mode=>"0", - intr_mode=>"10", - invert_in_clock=>'0', - invert_in_clock_en=>'0', - invert_in_reset=>'0', - invert_out_clock=>'0', - invert_out_clock_en=>'0', - invert_out_reset=>'0', - io_voltage=>"", - layout_mode=>"CONTIGUOUS", - output_conn=>"0", - output_sync=>"0", - output_clk_en=>'0', - output_mode=>"0", - output_reset=>'0', - output_clock_mode=>"0", - oe_sync=>"0", - oe_conn=>"0", - oe_reset=>'0', - pin_aliases=>"", - pin_mode=>"I", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0", - sio_ibuf=>"00000000", - sio_info=>"00", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0", - spanning=>'0', - sw_only=>'0', - vtrip=>"00", - width=>1, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"0", - pa_in_clock=>-1, - pa_in_clock_en=>-1, - pa_in_reset=>-1, - pa_out_clock=>-1, - pa_out_clock_en=>-1, - pa_out_reset=>-1) - PORT MAP(oe=>(one), - y=>(zero), - fb=>(\USBFS:tmpFB_0__Dp_net_0\), - analog=>\USBFS:Net_1000\, - io=>(\USBFS:tmpIO_0__Dp_net_0\), - siovref=>(\USBFS:tmpSIOVREF__Dp_net_0\), - annotation=>(open), - in_clock=>zero, - in_clock_en=>one, - in_reset=>zero, - out_clock=>zero, - out_clock_en=>one, - out_reset=>zero, - interrupt=>\USBFS:Net_1010\); -\USBFS:dp_int\:cy_isr_v1_0 - GENERIC MAP(int_type=>"10") - PORT MAP(int_signal=>\USBFS:Net_1010\); -\USBFS:Clock_vbus\:cy_clock_v1_0 - GENERIC MAP(cy_registers=>"", - id=>"f9248435-5d3e-4e4d-bbae-bdae8795c3dd/03f503a7-085a-4304-b786-de885b1c2f21", - source_clock_id=>"75C2148C-3656-4d8a-846D-0CAE99AB6FF7", - divisor=>0, - period=>"0", - is_direct=>'1', - is_digital=>'1') - PORT MAP(clock_out=>\USBFS:Net_1099\, - dig_domain_out=>open); -SCSI_Out_DBx:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"52f31aa9-2f0a-497d-9a1f-1424095e13e6", - drive_mode=>"110110110110110110110110", - ibuf_enabled=>"11111111", - init_dr_st=>"00000000", - input_sync=>"11111111", - input_clk_en=>'0', - input_sync_mode=>"00000000", - intr_mode=>"0000000000000000", - invert_in_clock=>'0', - invert_in_clock_en=>'0', - invert_in_reset=>'0', - invert_out_clock=>'0', - invert_out_clock_en=>'0', - invert_out_reset=>'0', - io_voltage=>", , , , , , , 5", - layout_mode=>"NONCONTIGUOUS", - output_conn=>"00000000", - output_sync=>"00000000", - output_clk_en=>'0', - output_mode=>"00000000", - output_reset=>'0', - output_clock_mode=>"00000000", - oe_sync=>"00000000", - oe_conn=>"00000000", - oe_reset=>'0', - pin_aliases=>"DB0,DB1,DB2,DB3,DB4,DB5,DB6,DB7", - pin_mode=>"OOOOOOOO", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"00000000", - sio_ibuf=>"00000000", - sio_info=>"0000000000000000", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"00000000", - spanning=>'1', - sw_only=>'0', - vtrip=>"1010101010101010", - width=>8, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"11111111", - pa_in_clock=>-1, - pa_in_clock_en=>-1, - pa_in_reset=>-1, - pa_out_clock=>-1, - pa_out_clock_en=>-1, - pa_out_reset=>-1) - PORT MAP(oe=>(one, one, one, one, - one, one, one, one), - y=>(zero, zero, zero, zero, - zero, zero, zero, zero), - fb=>(tmpFB_7__SCSI_Out_DBx_net_7, tmpFB_7__SCSI_Out_DBx_net_6, tmpFB_7__SCSI_Out_DBx_net_5, tmpFB_7__SCSI_Out_DBx_net_4, - tmpFB_7__SCSI_Out_DBx_net_3, tmpFB_7__SCSI_Out_DBx_net_2, tmpFB_7__SCSI_Out_DBx_net_1, tmpFB_7__SCSI_Out_DBx_net_0), - analog=>(open, open, open, open, - open, open, open, open), - io=>(tmpIO_7__SCSI_Out_DBx_net_7, tmpIO_7__SCSI_Out_DBx_net_6, tmpIO_7__SCSI_Out_DBx_net_5, tmpIO_7__SCSI_Out_DBx_net_4, - tmpIO_7__SCSI_Out_DBx_net_3, tmpIO_7__SCSI_Out_DBx_net_2, tmpIO_7__SCSI_Out_DBx_net_1, tmpIO_7__SCSI_Out_DBx_net_0), - siovref=>(tmpSIOVREF__SCSI_Out_DBx_net_0), - annotation=>(Net_37_7, Net_37_6, Net_37_5, Net_37_4, - Net_37_3, Net_37_2, Net_37_1, Net_37_0), - in_clock=>zero, - in_clock_en=>one, - in_reset=>zero, - out_clock=>zero, - out_clock_en=>one, - out_reset=>zero, - interrupt=>tmpINTERRUPT_0__SCSI_Out_DBx_net_0); -SCSI_Out:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"11f071e8-9c92-47e0-872a-3f48765a75b8", - drive_mode=>"110110110110110110110110110110", - ibuf_enabled=>"1111111111", - init_dr_st=>"0000000000", - input_sync=>"1111111111", - input_clk_en=>'0', - input_sync_mode=>"0000000000", - intr_mode=>"00000000000000000000", - invert_in_clock=>'0', - invert_in_clock_en=>'0', - invert_in_reset=>'0', - invert_out_clock=>'0', - invert_out_clock_en=>'0', - invert_out_reset=>'0', - io_voltage=>"5, 5, 5, 5, 5, 5, 5, 5, 5, 5", - layout_mode=>"NONCONTIGUOUS", - output_conn=>"0000000000", - output_sync=>"0000000000", - output_clk_en=>'0', - output_mode=>"0000000000", - output_reset=>'0', - output_clock_mode=>"0000000000", - oe_sync=>"0000000000", - oe_conn=>"0000000000", - oe_reset=>'0', - pin_aliases=>"DBP_raw,ATN,BSY,ACK,RST,MSG,SEL,CD,REQ,IO_raw", - pin_mode=>"OOOOOOOOOO", - por_state=>4, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"0000000000", - sio_ibuf=>"00000000", - sio_info=>"00000000000000000000", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"0000000000", - spanning=>'1', - sw_only=>'0', - vtrip=>"10101010101010101010", - width=>10, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"1111111111", - pa_in_clock=>-1, - pa_in_clock_en=>-1, - pa_in_reset=>-1, - pa_out_clock=>-1, - pa_out_clock_en=>-1, - pa_out_reset=>-1) - PORT MAP(oe=>(one, one, one, one, - one, one, one, one, - one, one), - y=>(zero, zero, zero, zero, - zero, zero, zero, zero, - zero, zero), - fb=>(tmpFB_9__SCSI_Out_net_9, tmpFB_9__SCSI_Out_net_8, tmpFB_9__SCSI_Out_net_7, tmpFB_9__SCSI_Out_net_6, - tmpFB_9__SCSI_Out_net_5, tmpFB_9__SCSI_Out_net_4, tmpFB_9__SCSI_Out_net_3, tmpFB_9__SCSI_Out_net_2, - tmpFB_9__SCSI_Out_net_1, tmpFB_9__SCSI_Out_net_0), - analog=>(open, open, open, open, - open, open, open, open, - open, open), - io=>(tmpIO_9__SCSI_Out_net_9, tmpIO_9__SCSI_Out_net_8, tmpIO_9__SCSI_Out_net_7, tmpIO_9__SCSI_Out_net_6, - tmpIO_9__SCSI_Out_net_5, tmpIO_9__SCSI_Out_net_4, tmpIO_9__SCSI_Out_net_3, tmpIO_9__SCSI_Out_net_2, - tmpIO_9__SCSI_Out_net_1, tmpIO_9__SCSI_Out_net_0), - siovref=>(tmpSIOVREF__SCSI_Out_net_0), - annotation=>(Net_36, Net_35, Net_34, Net_33, - Net_32, Net_31, Net_30, Net_29, - Net_28, Net_27), - in_clock=>zero, - in_clock_en=>one, - in_reset=>zero, - out_clock=>zero, - out_clock_en=>one, - out_reset=>zero, - interrupt=>tmpINTERRUPT_0__SCSI_Out_net_0); -SD_PULLUP:cy_psoc3_pins_v1_10 - GENERIC MAP(id=>"4c15b41e-e284-4978-99e7-5aaee19bd0ce", - drive_mode=>"010010010010010", - ibuf_enabled=>"11111", - init_dr_st=>"11111", - input_sync=>"11111", - input_clk_en=>'0', - input_sync_mode=>"00000", - intr_mode=>"0000000000", - invert_in_clock=>'0', - invert_in_clock_en=>'0', - invert_in_reset=>'0', - invert_out_clock=>'0', - invert_out_clock_en=>'0', - invert_out_reset=>'0', - io_voltage=>"3.3, , , , ", - layout_mode=>"CONTIGUOUS", - output_conn=>"00000", - output_sync=>"00000", - output_clk_en=>'0', - output_mode=>"00000", - output_reset=>'0', - output_clock_mode=>"00000", - oe_sync=>"00000", - oe_conn=>"00000", - oe_reset=>'0', - pin_aliases=>",,,,", - pin_mode=>"IIIII", - por_state=>2, - sio_group_cnt=>0, - sio_hifreq=>"", - sio_hyst=>"00000", - sio_ibuf=>"00000000", - sio_info=>"0000000000", - sio_obuf=>"00000000", - sio_refsel=>"00000000", - sio_vtrip=>"00000000", - slew_rate=>"00000", - spanning=>'0', - sw_only=>'0', - vtrip=>"0000000000", - width=>5, - port_alias_required=>'0', - port_alias_group=>"", - use_annotation=>"00000", - pa_in_clock=>-1, - pa_in_clock_en=>-1, - pa_in_reset=>-1, - pa_out_clock=>-1, - pa_out_clock_en=>-1, - pa_out_reset=>-1) - PORT MAP(oe=>(one, one, one, one, - one), - y=>(zero, zero, zero, zero, - zero), - fb=>(Net_88, Net_87, Net_86, Net_85, - Net_84), - analog=>(open, open, open, open, - open), - io=>(tmpIO_4__SD_PULLUP_net_4, tmpIO_4__SD_PULLUP_net_3, tmpIO_4__SD_PULLUP_net_2, tmpIO_4__SD_PULLUP_net_1, - tmpIO_4__SD_PULLUP_net_0), - siovref=>(tmpSIOVREF__SD_PULLUP_net_0), - annotation=>(open, open, open, open, - open), - in_clock=>zero, - in_clock_en=>one, - in_reset=>zero, - out_clock=>zero, - out_clock_en=>one, - out_reset=>zero, - interrupt=>tmpINTERRUPT_0__SD_PULLUP_net_0); - -END R_T_L; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.wde b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.wde deleted file mode 100755 index 83c0e4b..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader.wde +++ /dev/null @@ -1,5 +0,0 @@ -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif -USB_Bootloader.ctl -USB_Bootloader.v -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib deleted file mode 100755 index b4f81be..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.lib +++ /dev/null @@ -1,1699 +0,0 @@ -library (timing) { - timescale : 1ns; - capacitive_load_unit (1,ff); - include_file(device.lib); - cell (iocell1) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.445; - intrinsic_fall : 16.445; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.445; - intrinsic_fall : 16.445; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.093; - intrinsic_fall : 15.093; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.033; - intrinsic_fall : 7.033; - } - } - } - cell (iocell2) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.297; - intrinsic_fall : 17.297; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.297; - intrinsic_fall : 17.297; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.111; - intrinsic_fall : 15.111; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.255; - intrinsic_fall : 7.255; - } - } - } - cell (iocell3) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.269; - intrinsic_fall : 17.269; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.269; - intrinsic_fall : 17.269; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.495; - intrinsic_fall : 15.495; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.644; - intrinsic_fall : 7.644; - } - } - } - cell (iocell4) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.371; - intrinsic_fall : 17.371; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.371; - intrinsic_fall : 17.371; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.561; - intrinsic_fall : 15.561; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.354; - intrinsic_fall : 7.354; - } - } - } - cell (iocell5) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.023; - intrinsic_fall : 15.023; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 8.264; - intrinsic_fall : 8.264; - } - } - } - cell (iocell6) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.718; - intrinsic_fall : 17.718; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.718; - intrinsic_fall : 17.718; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.880; - intrinsic_fall : 14.880; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.563; - intrinsic_fall : 7.563; - } - } - } - cell (iocell7) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.610; - intrinsic_fall : 17.610; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.610; - intrinsic_fall : 17.610; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.744; - intrinsic_fall : 15.744; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.958; - intrinsic_fall : 7.958; - } - } - } - cell (iocell8) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.428; - intrinsic_fall : 17.428; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.428; - intrinsic_fall : 17.428; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.459; - intrinsic_fall : 15.459; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.950; - intrinsic_fall : 7.950; - } - } - } - cell (iocell9) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.434; - intrinsic_fall : 17.434; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.434; - intrinsic_fall : 17.434; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.802; - intrinsic_fall : 15.802; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.962; - intrinsic_fall : 7.962; - } - } - } - cell (iocell10) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.161; - intrinsic_fall : 17.161; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.161; - intrinsic_fall : 17.161; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.251; - intrinsic_fall : 15.251; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.922; - intrinsic_fall : 7.922; - } - } - } - cell (iocell11) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.840; - intrinsic_fall : 17.840; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.840; - intrinsic_fall : 17.840; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.011; - intrinsic_fall : 15.011; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.576; - intrinsic_fall : 7.576; - } - } - } - cell (iocell12) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.165; - intrinsic_fall : 17.165; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.165; - intrinsic_fall : 17.165; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.746; - intrinsic_fall : 15.746; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.331; - intrinsic_fall : 7.331; - } - } - } - cell (iocell13) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.973; - intrinsic_fall : 16.973; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.973; - intrinsic_fall : 16.973; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.880; - intrinsic_fall : 14.880; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.065; - intrinsic_fall : 7.065; - } - } - } - cell (iocell14) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.979; - intrinsic_fall : 16.979; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.979; - intrinsic_fall : 16.979; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.914; - intrinsic_fall : 14.914; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.816; - intrinsic_fall : 7.816; - } - } - } - cell (iocell15) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.374; - intrinsic_fall : 17.374; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.374; - intrinsic_fall : 17.374; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.222; - intrinsic_fall : 15.222; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.459; - intrinsic_fall : 7.459; - } - } - } - cell (iocell16) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.157; - intrinsic_fall : 17.157; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.157; - intrinsic_fall : 17.157; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.976; - intrinsic_fall : 15.976; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.582; - intrinsic_fall : 7.582; - } - } - } - cell (iocell17) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.578; - intrinsic_fall : 16.578; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.578; - intrinsic_fall : 16.578; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.347; - intrinsic_fall : 15.347; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.368; - intrinsic_fall : 7.368; - } - } - } - cell (iocell18) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.786; - intrinsic_fall : 17.786; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.786; - intrinsic_fall : 17.786; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.004; - intrinsic_fall : 16.004; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 6.974; - intrinsic_fall : 6.974; - } - } - } - cell (iocell19) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.419; - intrinsic_fall : 16.419; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.419; - intrinsic_fall : 16.419; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.979; - intrinsic_fall : 14.979; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 1.661; - intrinsic_fall : 1.661; - } - } - } - cell (iocell20) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.643; - intrinsic_fall : 17.643; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.643; - intrinsic_fall : 17.643; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.995; - intrinsic_fall : 14.995; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 1.852; - intrinsic_fall : 1.852; - } - } - } - cell (iocell21) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.081; - intrinsic_fall : 17.081; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.081; - intrinsic_fall : 17.081; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.591; - intrinsic_fall : 14.591; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 3.163; - intrinsic_fall : 3.163; - } - } - } - cell (iocell22) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.646; - intrinsic_fall : 16.646; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.646; - intrinsic_fall : 16.646; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.987; - intrinsic_fall : 14.987; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.191; - intrinsic_fall : 2.191; - } - } - } - cell (iocell23) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.787; - intrinsic_fall : 17.787; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.787; - intrinsic_fall : 17.787; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.338; - intrinsic_fall : 15.338; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.064; - intrinsic_fall : 2.064; - } - } - } - cell (iocell24) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.053; - intrinsic_fall : 19.053; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 9.497; - intrinsic_fall : 9.497; - } - } - } - cell (iocell25) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.129; - intrinsic_fall : 19.129; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.717; - intrinsic_fall : 2.717; - } - } - } -} diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco deleted file mode 100755 index 9bc042e..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.pco +++ /dev/null @@ -1,54 +0,0 @@ -dont_use_io iocell 1 0 -dont_use_io iocell 1 1 -dont_use_io iocell 1 3 -dont_use_location comparatorcell -1 -1 1 -dont_use_location comparatorcell -1 -1 3 -dont_use_location sccell -1 -1 0 -dont_use_location sccell -1 -1 1 -dont_use_location sccell -1 -1 2 -dont_use_location sccell -1 -1 3 -dont_use_location vidaccell -1 -1 1 -dont_use_location vidaccell -1 -1 2 -dont_use_location vidaccell -1 -1 3 -dont_use_location sarcell -1 -1 1 -dont_use_location abufcell -1 -1 0 -dont_use_location abufcell -1 -1 2 -dont_use_location abufcell -1 -1 1 -dont_use_location abufcell -1 -1 3 -set_io "SCSI_Out(4)" iocell 0 5 -set_io "SCSI_Out_DBx(4)" iocell 4 7 -set_io "SD_PULLUP(2)" iocell 3 3 -set_io "SCSI_Out(7)" iocell 0 2 -set_io "SCSI_Out_DBx(7)" iocell 4 4 -set_location "\USBFS:ep_0\" interrupt -1 -1 24 -set_location "\USBFS:ep_2\" interrupt -1 -1 1 -set_location "\USBFS:ep_1\" interrupt -1 -1 0 -set_location "\USBFS:dp_int\" interrupt -1 -1 12 -set_location "\USBFS:Dp\" logicalport -1 -1 8 -set_location "\USBFS:bus_reset\" interrupt -1 -1 23 -set_io "SCSI_Out(6)" iocell 0 3 -set_io "SCSI_Out_DBx(6)" iocell 4 5 -set_io "SCSI_Out(9)" iocell 0 0 -set_io "SCSI_Out(5)" iocell 0 4 -set_io "SCSI_Out_DBx(5)" iocell 4 6 -set_io "SCSI_Out(2)" iocell 0 7 -set_io "SCSI_Out_DBx(2)" iocell 6 1 -set_io "SCSI_Out(8)" iocell 0 1 -set_location "\USBFS:USB\" usbcell -1 -1 0 -set_io "SD_PULLUP(0)" iocell 3 1 -set_io "SD_PULLUP(4)" iocell 3 5 -set_location "\USBFS:arb_int\" interrupt -1 -1 22 -set_location "\USBFS:sof_int\" interrupt -1 -1 21 -set_io "SD_PULLUP(1)" iocell 3 2 -set_io "SD_PULLUP(3)" iocell 3 4 -set_io "SCSI_Out(1)" iocell 4 2 -set_io "SCSI_Out_DBx(1)" iocell 6 2 -set_io "SCSI_Out(0)" iocell 4 3 -set_io "SCSI_Out_DBx(0)" iocell 6 3 -# Note: port 15 is the logical name for port 8 -set_io "\USBFS:Dm(0)\" iocell 15 7 -set_io "SCSI_Out(3)" iocell 0 6 -set_io "SCSI_Out_DBx(3)" iocell 6 0 -set_location "ClockBlock" clockblockcell -1 -1 0 -# Note: port 15 is the logical name for port 8 -set_io "\USBFS:Dp(0)\" iocell 15 6 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2 deleted file mode 100755 index 93f1fea..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_p.vh2 +++ /dev/null @@ -1,1990 +0,0 @@ --- Project: USB_Bootloader --- Generated: 03/22/2014 22:32:51 --- - -ENTITY USB_Bootloader IS - PORT( - SCSI_Out(0)_PAD : OUT std_ulogic; - SCSI_Out(1)_PAD : OUT std_ulogic; - SCSI_Out(2)_PAD : OUT std_ulogic; - SCSI_Out(3)_PAD : OUT std_ulogic; - SCSI_Out(4)_PAD : OUT std_ulogic; - SCSI_Out(5)_PAD : OUT std_ulogic; - SCSI_Out(6)_PAD : OUT std_ulogic; - SCSI_Out(7)_PAD : OUT std_ulogic; - SCSI_Out(8)_PAD : OUT std_ulogic; - SCSI_Out(9)_PAD : OUT std_ulogic; - SCSI_Out_DBx(0)_PAD : OUT std_ulogic; - SCSI_Out_DBx(1)_PAD : OUT std_ulogic; - SCSI_Out_DBx(2)_PAD : OUT std_ulogic; - SCSI_Out_DBx(3)_PAD : OUT std_ulogic; - SCSI_Out_DBx(4)_PAD : OUT std_ulogic; - SCSI_Out_DBx(5)_PAD : OUT std_ulogic; - SCSI_Out_DBx(6)_PAD : OUT std_ulogic; - SCSI_Out_DBx(7)_PAD : OUT std_ulogic; - SD_PULLUP(0)_PAD : IN std_ulogic; - SD_PULLUP(1)_PAD : IN std_ulogic; - SD_PULLUP(2)_PAD : IN std_ulogic; - SD_PULLUP(3)_PAD : IN std_ulogic; - SD_PULLUP(4)_PAD : IN std_ulogic); - ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio3 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vdda OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio0 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio2 OF __DEFAULT__ : ENTITY IS 5e0; -END USB_Bootloader; - -ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS - SIGNAL ClockBlock_100k : bit; - SIGNAL ClockBlock_1k : bit; - SIGNAL ClockBlock_32k : bit; - SIGNAL ClockBlock_BUS_CLK : bit; - ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; - SIGNAL ClockBlock_BUS_CLK_local : bit; - SIGNAL ClockBlock_ILO : bit; - SIGNAL ClockBlock_IMO : bit; - SIGNAL ClockBlock_MASTER_CLK : bit; - SIGNAL ClockBlock_PLL_OUT : bit; - SIGNAL ClockBlock_XTAL : bit; - SIGNAL ClockBlock_XTAL_32KHZ : bit; - SIGNAL Net_40 : bit; - SIGNAL SCSI_Out(0)__PA : bit; - SIGNAL SCSI_Out(1)__PA : bit; - SIGNAL SCSI_Out(2)__PA : bit; - SIGNAL SCSI_Out(3)__PA : bit; - SIGNAL SCSI_Out(4)__PA : bit; - SIGNAL SCSI_Out(5)__PA : bit; - SIGNAL SCSI_Out(6)__PA : bit; - SIGNAL SCSI_Out(7)__PA : bit; - SIGNAL SCSI_Out(8)__PA : bit; - SIGNAL SCSI_Out(9)__PA : bit; - SIGNAL SCSI_Out_DBx(0)__PA : bit; - SIGNAL SCSI_Out_DBx(1)__PA : bit; - SIGNAL SCSI_Out_DBx(2)__PA : bit; - SIGNAL SCSI_Out_DBx(3)__PA : bit; - SIGNAL SCSI_Out_DBx(4)__PA : bit; - SIGNAL SCSI_Out_DBx(5)__PA : bit; - SIGNAL SCSI_Out_DBx(6)__PA : bit; - SIGNAL SCSI_Out_DBx(7)__PA : bit; - SIGNAL SD_PULLUP(0)__PA : bit; - SIGNAL SD_PULLUP(1)__PA : bit; - SIGNAL SD_PULLUP(2)__PA : bit; - SIGNAL SD_PULLUP(3)__PA : bit; - SIGNAL SD_PULLUP(4)__PA : bit; - SIGNAL \\\USBFS:Dm(0)\\__PA\ : bit; - SIGNAL \\\USBFS:Dp(0)\\__PA\ : bit; - SIGNAL \USBFS:Net_1010\ : bit; - SIGNAL \USBFS:Net_79\ : bit; - SIGNAL \USBFS:Net_81\ : bit; - SIGNAL \USBFS:Net_824\ : bit; - SIGNAL \USBFS:Net_95\ : bit; - SIGNAL \USBFS:dma_req_0\ : bit; - SIGNAL \USBFS:dma_req_1\ : bit; - SIGNAL \USBFS:dma_req_2\ : bit; - SIGNAL \USBFS:dma_req_3\ : bit; - SIGNAL \USBFS:dma_req_4\ : bit; - SIGNAL \USBFS:dma_req_5\ : bit; - SIGNAL \USBFS:dma_req_6\ : bit; - SIGNAL \USBFS:dma_req_7\ : bit; - SIGNAL \USBFS:ept_int_0\ : bit; - SIGNAL \USBFS:ept_int_1\ : bit; - SIGNAL \USBFS:ept_int_2\ : bit; - SIGNAL \USBFS:ept_int_3\ : bit; - SIGNAL \USBFS:ept_int_4\ : bit; - SIGNAL \USBFS:ept_int_5\ : bit; - SIGNAL \USBFS:ept_int_6\ : bit; - SIGNAL \USBFS:ept_int_7\ : bit; - SIGNAL \USBFS:ept_int_8\ : bit; - SIGNAL __ONE__ : bit; - ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; - SIGNAL __ZERO__ : bit; - ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; - SIGNAL one : bit; - ATTRIBUTE POWER OF one : SIGNAL IS true; - SIGNAL zero : bit; - ATTRIBUTE GROUND OF zero : SIGNAL IS true; - ATTRIBUTE lib_model OF SCSI_Out(0) : LABEL IS "iocell1"; - ATTRIBUTE Location OF SCSI_Out(0) : LABEL IS "P4[3]"; - ATTRIBUTE lib_model OF SCSI_Out(1) : LABEL IS "iocell2"; - ATTRIBUTE Location OF SCSI_Out(1) : LABEL IS "P4[2]"; - ATTRIBUTE lib_model OF SCSI_Out(2) : LABEL IS "iocell3"; - ATTRIBUTE Location OF SCSI_Out(2) : LABEL IS "P0[7]"; - ATTRIBUTE lib_model OF SCSI_Out(3) : LABEL IS "iocell4"; - ATTRIBUTE Location OF SCSI_Out(3) : LABEL IS "P0[6]"; - ATTRIBUTE lib_model OF SCSI_Out(4) : LABEL IS "iocell5"; - ATTRIBUTE Location OF SCSI_Out(4) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF SCSI_Out(5) : LABEL IS "iocell6"; - ATTRIBUTE Location OF SCSI_Out(5) : LABEL IS "P0[4]"; - ATTRIBUTE lib_model OF SCSI_Out(6) : LABEL IS "iocell7"; - ATTRIBUTE Location OF SCSI_Out(6) : LABEL IS "P0[3]"; - ATTRIBUTE lib_model OF SCSI_Out(7) : LABEL IS "iocell8"; - ATTRIBUTE Location OF SCSI_Out(7) : LABEL IS "P0[2]"; - ATTRIBUTE lib_model OF SCSI_Out(8) : LABEL IS "iocell9"; - ATTRIBUTE Location OF SCSI_Out(8) : LABEL IS "P0[1]"; - ATTRIBUTE lib_model OF SCSI_Out(9) : LABEL IS "iocell10"; - ATTRIBUTE Location OF SCSI_Out(9) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(0) : LABEL IS "iocell11"; - ATTRIBUTE Location OF SCSI_Out_DBx(0) : LABEL IS "P6[3]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(1) : LABEL IS "iocell12"; - ATTRIBUTE Location OF SCSI_Out_DBx(1) : LABEL IS "P6[2]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(2) : LABEL IS "iocell13"; - ATTRIBUTE Location OF SCSI_Out_DBx(2) : LABEL IS "P6[1]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(3) : LABEL IS "iocell14"; - ATTRIBUTE Location OF SCSI_Out_DBx(3) : LABEL IS "P6[0]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(4) : LABEL IS "iocell15"; - ATTRIBUTE Location OF SCSI_Out_DBx(4) : LABEL IS "P4[7]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(5) : LABEL IS "iocell16"; - ATTRIBUTE Location OF SCSI_Out_DBx(5) : LABEL IS "P4[6]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(6) : LABEL IS "iocell17"; - ATTRIBUTE Location OF SCSI_Out_DBx(6) : LABEL IS "P4[5]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(7) : LABEL IS "iocell18"; - ATTRIBUTE Location OF SCSI_Out_DBx(7) : LABEL IS "P4[4]"; - ATTRIBUTE lib_model OF SD_PULLUP(0) : LABEL IS "iocell19"; - ATTRIBUTE Location OF SD_PULLUP(0) : LABEL IS "P3[1]"; - ATTRIBUTE lib_model OF SD_PULLUP(1) : LABEL IS "iocell20"; - ATTRIBUTE Location OF SD_PULLUP(1) : LABEL IS "P3[2]"; - ATTRIBUTE lib_model OF SD_PULLUP(2) : LABEL IS "iocell21"; - ATTRIBUTE Location OF SD_PULLUP(2) : LABEL IS "P3[3]"; - ATTRIBUTE lib_model OF SD_PULLUP(3) : LABEL IS "iocell22"; - ATTRIBUTE Location OF SD_PULLUP(3) : LABEL IS "P3[4]"; - ATTRIBUTE lib_model OF SD_PULLUP(4) : LABEL IS "iocell23"; - ATTRIBUTE Location OF SD_PULLUP(4) : LABEL IS "P3[5]"; - ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell24"; - ATTRIBUTE Location OF \USBFS:Dm(0)\ : LABEL IS "P15[7]"; - ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell25"; - ATTRIBUTE Location OF \USBFS:Dp(0)\ : LABEL IS "P15[6]"; - ATTRIBUTE Location OF \USBFS:USB\ : LABEL IS "F(USB,0)"; - COMPONENT abufcell - END COMPONENT; - COMPONENT boostcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cachecell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cancell - PORT ( - clock : IN std_ulogic; - can_rx : IN std_ulogic; - can_tx : OUT std_ulogic; - can_tx_en : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT capsensecell - PORT ( - lft : IN std_ulogic; - rt : IN std_ulogic); - END COMPONENT; - COMPONENT clockblockcell - PORT ( - dclk_0 : OUT std_ulogic; - dclk_1 : OUT std_ulogic; - dclk_2 : OUT std_ulogic; - dclk_3 : OUT std_ulogic; - dclk_4 : OUT std_ulogic; - dclk_5 : OUT std_ulogic; - dclk_6 : OUT std_ulogic; - dclk_7 : OUT std_ulogic; - dclk_glb_0 : OUT std_ulogic; - dclk_glb_1 : OUT std_ulogic; - dclk_glb_2 : OUT std_ulogic; - dclk_glb_3 : OUT std_ulogic; - dclk_glb_4 : OUT std_ulogic; - dclk_glb_5 : OUT std_ulogic; - dclk_glb_6 : OUT std_ulogic; - dclk_glb_7 : OUT std_ulogic; - aclk_0 : OUT std_ulogic; - aclk_1 : OUT std_ulogic; - aclk_2 : OUT std_ulogic; - aclk_3 : OUT std_ulogic; - aclk_glb_0 : OUT std_ulogic; - aclk_glb_1 : OUT std_ulogic; - aclk_glb_2 : OUT std_ulogic; - aclk_glb_3 : OUT std_ulogic; - clk_a_dig_0 : OUT std_ulogic; - clk_a_dig_1 : OUT std_ulogic; - clk_a_dig_2 : OUT std_ulogic; - clk_a_dig_3 : OUT std_ulogic; - clk_a_dig_glb_0 : OUT std_ulogic; - clk_a_dig_glb_1 : OUT std_ulogic; - clk_a_dig_glb_2 : OUT std_ulogic; - clk_a_dig_glb_3 : OUT std_ulogic; - clk_bus : OUT std_ulogic; - clk_bus_glb : OUT std_ulogic; - clk_sync : OUT std_ulogic; - clk_32k_xtal : OUT std_ulogic; - clk_100k : OUT std_ulogic; - clk_32k : OUT std_ulogic; - clk_1k : OUT std_ulogic; - clk_usb : OUT std_ulogic; - xmhz_xerr : OUT std_ulogic; - pll_lock_out : OUT std_ulogic; - dsi_dig_div_0 : IN std_ulogic; - dsi_dig_div_1 : IN std_ulogic; - dsi_dig_div_2 : IN std_ulogic; - dsi_dig_div_3 : IN std_ulogic; - dsi_dig_div_4 : IN std_ulogic; - dsi_dig_div_5 : IN std_ulogic; - dsi_dig_div_6 : IN std_ulogic; - dsi_dig_div_7 : IN std_ulogic; - dsi_ana_div_0 : IN std_ulogic; - dsi_ana_div_1 : IN std_ulogic; - dsi_ana_div_2 : IN std_ulogic; - dsi_ana_div_3 : IN std_ulogic; - dsi_glb_div : IN std_ulogic; - dsi_clkin_div : IN std_ulogic; - imo : OUT std_ulogic; - ilo : OUT std_ulogic; - xtal : OUT std_ulogic; - pllout : OUT std_ulogic; - clk_bus_glb_ff : OUT std_ulogic; - aclk_glb_ff_0 : OUT std_ulogic; - clk_a_dig_glb_ff_0 : OUT std_ulogic; - aclk_glb_ff_1 : OUT std_ulogic; - clk_a_dig_glb_ff_1 : OUT std_ulogic; - aclk_glb_ff_2 : OUT std_ulogic; - clk_a_dig_glb_ff_2 : OUT std_ulogic; - aclk_glb_ff_3 : OUT std_ulogic; - clk_a_dig_glb_ff_3 : OUT std_ulogic; - dclk_glb_ff_0 : OUT std_ulogic; - dclk_glb_ff_1 : OUT std_ulogic; - dclk_glb_ff_2 : OUT std_ulogic; - dclk_glb_ff_3 : OUT std_ulogic; - dclk_glb_ff_4 : OUT std_ulogic; - dclk_glb_ff_5 : OUT std_ulogic; - dclk_glb_ff_6 : OUT std_ulogic; - dclk_glb_ff_7 : OUT std_ulogic); - END COMPONENT; - COMPONENT comparatorcell - PORT ( - out : OUT std_ulogic; - clk_udb : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT controlcell - PORT ( - control_0 : OUT std_ulogic; - control_1 : OUT std_ulogic; - control_2 : OUT std_ulogic; - control_3 : OUT std_ulogic; - control_4 : OUT std_ulogic; - control_5 : OUT std_ulogic; - control_6 : OUT std_ulogic; - control_7 : OUT std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF controlcell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF controlcell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF controlcell : COMPONENT IS "reset"; - COMPONENT count7cell - PORT ( - clock : IN std_ulogic; - reset : IN std_ulogic; - load : IN std_ulogic; - enable : IN std_ulogic; - clk_en : IN std_ulogic; - count_0 : OUT std_ulogic; - count_1 : OUT std_ulogic; - count_2 : OUT std_ulogic; - count_3 : OUT std_ulogic; - count_4 : OUT std_ulogic; - count_5 : OUT std_ulogic; - count_6 : OUT std_ulogic; - tc : OUT std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF count7cell : COMPONENT IS "clock,clock_n,extclk,extclk_n"; - ATTRIBUTE udb_clken OF count7cell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF count7cell : COMPONENT IS "reset"; - COMPONENT csabufcell - PORT ( - swon : IN std_ulogic); - END COMPONENT; - COMPONENT datapathcell - PORT ( - clock : IN std_ulogic; - clk_en : IN std_ulogic; - reset : IN std_ulogic; - cs_addr_0 : IN std_ulogic; - cs_addr_1 : IN std_ulogic; - cs_addr_2 : IN std_ulogic; - route_si : IN std_ulogic; - route_ci : IN std_ulogic; - f0_load : IN std_ulogic; - f1_load : IN std_ulogic; - d0_load : IN std_ulogic; - d1_load : IN std_ulogic; - ce0_reg : OUT std_ulogic; - cl0_reg : OUT std_ulogic; - z0_reg : OUT std_ulogic; - f0_reg : OUT std_ulogic; - ce1_reg : OUT std_ulogic; - cl1_reg : OUT std_ulogic; - z1_reg : OUT std_ulogic; - f1_reg : OUT std_ulogic; - ov_msb_reg : OUT std_ulogic; - co_msb_reg : OUT std_ulogic; - cmsb_reg : OUT std_ulogic; - so_reg : OUT std_ulogic; - f0_bus_stat_reg : OUT std_ulogic; - f0_blk_stat_reg : OUT std_ulogic; - f1_bus_stat_reg : OUT std_ulogic; - f1_blk_stat_reg : OUT std_ulogic; - ce0_comb : OUT std_ulogic; - cl0_comb : OUT std_ulogic; - z0_comb : OUT std_ulogic; - f0_comb : OUT std_ulogic; - ce1_comb : OUT std_ulogic; - cl1_comb : OUT std_ulogic; - z1_comb : OUT std_ulogic; - f1_comb : OUT std_ulogic; - ov_msb_comb : OUT std_ulogic; - co_msb_comb : OUT std_ulogic; - cmsb_comb : OUT std_ulogic; - so_comb : OUT std_ulogic; - f0_bus_stat_comb : OUT std_ulogic; - f0_blk_stat_comb : OUT std_ulogic; - f1_bus_stat_comb : OUT std_ulogic; - f1_blk_stat_comb : OUT std_ulogic; - ce0 : OUT std_ulogic; - ce0i : IN std_ulogic; - p_in_0 : IN std_ulogic; - p_in_1 : IN std_ulogic; - p_in_2 : IN std_ulogic; - p_in_3 : IN std_ulogic; - p_in_4 : IN std_ulogic; - p_in_5 : IN std_ulogic; - p_in_6 : IN std_ulogic; - p_in_7 : IN std_ulogic; - p_out_0 : OUT std_ulogic; - p_out_1 : OUT std_ulogic; - p_out_2 : OUT std_ulogic; - p_out_3 : OUT std_ulogic; - p_out_4 : OUT std_ulogic; - p_out_5 : OUT std_ulogic; - p_out_6 : OUT std_ulogic; - p_out_7 : OUT std_ulogic; - cl0i : IN std_ulogic; - cl0 : OUT std_ulogic; - z0i : IN std_ulogic; - z0 : OUT std_ulogic; - ff0i : IN std_ulogic; - ff0 : OUT std_ulogic; - ce1i : IN std_ulogic; - ce1 : OUT std_ulogic; - cl1i : IN std_ulogic; - cl1 : OUT std_ulogic; - z1i : IN std_ulogic; - z1 : OUT std_ulogic; - ff1i : IN std_ulogic; - ff1 : OUT std_ulogic; - cap0i : IN std_ulogic; - cap0 : OUT std_ulogic; - cap1i : IN std_ulogic; - cap1 : OUT std_ulogic; - ci : IN std_ulogic; - co_msb : OUT std_ulogic; - sir : IN std_ulogic; - sol_msb : OUT std_ulogic; - cfbi : IN std_ulogic; - cfbo : OUT std_ulogic; - sil : IN std_ulogic; - sor : OUT std_ulogic; - cmsbi : IN std_ulogic; - cmsbo : OUT std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF datapathcell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF datapathcell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF datapathcell : COMPONENT IS "reset"; - ATTRIBUTE udb_chain OF datapathcell : COMPONENT IS "ce0i,ce0,cl0i,cl0,z0i,z0,ff0i,ff0,ce1i,ce1,cl1i,cl1,z1i,z1,ff1i,ff1,cap0i,cap0,cap1i,cap1,ci,co_msb,sir,sol_msb,cfbi,cfbo,sil,sor,cmsbi,cmsbo"; - ATTRIBUTE chain_lsb OF datapathcell : COMPONENT IS "ce0i,cl0i,z0i,ff0i,ce1i,cl1i,z1i,ff1i,cap0i,cap1i,ci,sir,cfbi,sor,cmsbo"; - ATTRIBUTE chain_msb OF datapathcell : COMPONENT IS "ce0,cl0,z0,ff0,ce1,cl1,z1,ff1,cap0,cap1,co_msb,sol_msb,cfbo,sil,cmsbi"; - COMPONENT decimatorcell - PORT ( - aclock : IN std_ulogic; - mod_dat_0 : IN std_ulogic; - mod_dat_1 : IN std_ulogic; - mod_dat_2 : IN std_ulogic; - mod_dat_3 : IN std_ulogic; - ext_start : IN std_ulogic; - modrst : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT dfbcell - PORT ( - clock : IN std_ulogic; - in_1 : IN std_ulogic; - in_2 : IN std_ulogic; - out_1 : OUT std_ulogic; - out_2 : OUT std_ulogic; - dmareq_1 : OUT std_ulogic; - dmareq_2 : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT drqcell - PORT ( - dmareq : IN std_ulogic; - termin : IN std_ulogic; - termout : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT dsmodcell - PORT ( - aclock : IN std_ulogic; - modbitin_udb : IN std_ulogic; - reset_udb : IN std_ulogic; - reset_dec : IN std_ulogic; - dec_clock : OUT std_ulogic; - mod_dat_0 : OUT std_ulogic; - mod_dat_1 : OUT std_ulogic; - mod_dat_2 : OUT std_ulogic; - mod_dat_3 : OUT std_ulogic; - dout_udb_0 : OUT std_ulogic; - dout_udb_1 : OUT std_ulogic; - dout_udb_2 : OUT std_ulogic; - dout_udb_3 : OUT std_ulogic; - dout_udb_4 : OUT std_ulogic; - dout_udb_5 : OUT std_ulogic; - dout_udb_6 : OUT std_ulogic; - dout_udb_7 : OUT std_ulogic; - extclk_cp_udb : IN std_ulogic; - clk_udb : IN std_ulogic); - END COMPONENT; - COMPONENT emifcell - PORT ( - EM_clock : OUT std_ulogic; - EM_CEn : OUT std_ulogic; - EM_OEn : OUT std_ulogic; - EM_ADSCn : OUT std_ulogic; - EM_sleep : OUT std_ulogic; - EM_WRn : OUT std_ulogic; - dataport_OE : OUT std_ulogic; - dataport_OEn : OUT std_ulogic; - wr : OUT std_ulogic; - rd : OUT std_ulogic; - udb_stall : IN std_ulogic; - udb_ready : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT i2ccell - PORT ( - clock : IN std_ulogic; - scl_in : IN std_ulogic; - sda_in : IN std_ulogic; - scl_out : OUT std_ulogic; - sda_out : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT interrupt - PORT ( - interrupt : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT iocell - PORT ( - pin_input : IN std_ulogic; - oe : IN std_ulogic; - fb : OUT std_ulogic; - pad_in : IN std_ulogic; - pa_out : OUT std_ulogic; - pad_out : OUT std_ulogic; - oe_reg : OUT std_ulogic; - oe_internal : IN std_ulogic; - in_clock : IN std_ulogic; - in_clock_en : IN std_ulogic; - in_reset : IN std_ulogic; - out_clock : IN std_ulogic; - out_clock_en : IN std_ulogic; - out_reset : IN std_ulogic); - END COMPONENT; - COMPONENT lcdctrlcell - PORT ( - drive_en : IN std_ulogic; - frame : IN std_ulogic; - data_clk : IN std_ulogic; - en_hi : IN std_ulogic; - dac_dis : IN std_ulogic; - chop_clk : IN std_ulogic; - int_clr : IN std_ulogic; - lp_ack_udb : IN std_ulogic; - mode_1 : IN std_ulogic; - mode_2 : IN std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT logicalport - PORT ( - interrupt : OUT std_ulogic; - precharge : IN std_ulogic; - in_clock : IN std_ulogic; - in_clock_en : IN std_ulogic; - in_reset : IN std_ulogic; - out_clock : IN std_ulogic; - out_clock_en : IN std_ulogic; - out_reset : IN std_ulogic); - END COMPONENT; - COMPONENT lpfcell - END COMPONENT; - COMPONENT lvdcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8clockblockcell - PORT ( - imo : OUT std_ulogic; - ext : OUT std_ulogic; - eco : OUT std_ulogic; - ilo : OUT std_ulogic; - wco : OUT std_ulogic; - dbl : OUT std_ulogic; - pll : OUT std_ulogic; - dpll : OUT std_ulogic; - dsi_out_0 : OUT std_ulogic; - dsi_out_1 : OUT std_ulogic; - dsi_out_2 : OUT std_ulogic; - dsi_out_3 : OUT std_ulogic; - lfclk : OUT std_ulogic; - hfclk : OUT std_ulogic; - sysclk : OUT std_ulogic; - halfsysclk : OUT std_ulogic; - udb_div_0 : OUT std_ulogic; - udb_div_1 : OUT std_ulogic; - udb_div_2 : OUT std_ulogic; - udb_div_3 : OUT std_ulogic; - udb_div_4 : OUT std_ulogic; - udb_div_5 : OUT std_ulogic; - udb_div_6 : OUT std_ulogic; - udb_div_7 : OUT std_ulogic; - udb_div_8 : OUT std_ulogic; - udb_div_9 : OUT std_ulogic; - udb_div_10 : OUT std_ulogic; - udb_div_11 : OUT std_ulogic; - udb_div_12 : OUT std_ulogic; - udb_div_13 : OUT std_ulogic; - udb_div_14 : OUT std_ulogic; - udb_div_15 : OUT std_ulogic; - uab_div_0 : OUT std_ulogic; - uab_div_1 : OUT std_ulogic; - uab_div_2 : OUT std_ulogic; - uab_div_3 : OUT std_ulogic; - ff_div_0 : OUT std_ulogic; - ff_div_1 : OUT std_ulogic; - ff_div_2 : OUT std_ulogic; - ff_div_3 : OUT std_ulogic; - ff_div_4 : OUT std_ulogic; - ff_div_5 : OUT std_ulogic; - ff_div_6 : OUT std_ulogic; - ff_div_7 : OUT std_ulogic; - ff_div_8 : OUT std_ulogic; - ff_div_9 : OUT std_ulogic; - ff_div_10 : OUT std_ulogic; - ff_div_11 : OUT std_ulogic; - ff_div_12 : OUT std_ulogic; - ff_div_13 : OUT std_ulogic; - ff_div_14 : OUT std_ulogic; - ff_div_15 : OUT std_ulogic; - dsi_in_0 : IN std_ulogic; - dsi_in_1 : IN std_ulogic; - dsi_in_2 : IN std_ulogic; - dsi_in_3 : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8clockgenblockcell - PORT ( - gen_clk_in_0 : IN std_ulogic; - gen_clk_in_1 : IN std_ulogic; - gen_clk_in_2 : IN std_ulogic; - gen_clk_in_3 : IN std_ulogic; - gen_clk_in_4 : IN std_ulogic; - gen_clk_in_5 : IN std_ulogic; - gen_clk_in_6 : IN std_ulogic; - gen_clk_in_7 : IN std_ulogic; - gen_clk_out_0 : OUT std_ulogic; - gen_clk_out_1 : OUT std_ulogic; - gen_clk_out_2 : OUT std_ulogic; - gen_clk_out_3 : OUT std_ulogic; - gen_clk_out_4 : OUT std_ulogic; - gen_clk_out_5 : OUT std_ulogic; - gen_clk_out_6 : OUT std_ulogic; - gen_clk_out_7 : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8lcdcell - PORT ( - common_0 : OUT std_ulogic; - common_1 : OUT std_ulogic; - common_2 : OUT std_ulogic; - common_3 : OUT std_ulogic; - common_4 : OUT std_ulogic; - common_5 : OUT std_ulogic; - common_6 : OUT std_ulogic; - common_7 : OUT std_ulogic; - common_8 : OUT std_ulogic; - common_9 : OUT std_ulogic; - common_10 : OUT std_ulogic; - common_11 : OUT std_ulogic; - common_12 : OUT std_ulogic; - common_13 : OUT std_ulogic; - common_14 : OUT std_ulogic; - common_15 : OUT std_ulogic; - segment_0 : OUT std_ulogic; - segment_1 : OUT std_ulogic; - segment_2 : OUT std_ulogic; - segment_3 : OUT std_ulogic; - segment_4 : OUT std_ulogic; - segment_5 : OUT std_ulogic; - segment_6 : OUT std_ulogic; - segment_7 : OUT std_ulogic; - segment_8 : OUT std_ulogic; - segment_9 : OUT std_ulogic; - segment_10 : OUT std_ulogic; - segment_11 : OUT std_ulogic; - segment_12 : OUT std_ulogic; - segment_13 : OUT std_ulogic; - segment_14 : OUT std_ulogic; - segment_15 : OUT std_ulogic; - segment_16 : OUT std_ulogic; - segment_17 : OUT std_ulogic; - segment_18 : OUT std_ulogic; - segment_19 : OUT std_ulogic; - segment_20 : OUT std_ulogic; - segment_21 : OUT std_ulogic; - segment_22 : OUT std_ulogic; - segment_23 : OUT std_ulogic; - segment_24 : OUT std_ulogic; - segment_25 : OUT std_ulogic; - segment_26 : OUT std_ulogic; - segment_27 : OUT std_ulogic; - segment_28 : OUT std_ulogic; - segment_29 : OUT std_ulogic; - segment_30 : OUT std_ulogic; - segment_31 : OUT std_ulogic; - segment_32 : OUT std_ulogic; - segment_33 : OUT std_ulogic; - segment_34 : OUT std_ulogic; - segment_35 : OUT std_ulogic; - segment_36 : OUT std_ulogic; - segment_37 : OUT std_ulogic; - segment_38 : OUT std_ulogic; - segment_39 : OUT std_ulogic; - segment_40 : OUT std_ulogic; - segment_41 : OUT std_ulogic; - segment_42 : OUT std_ulogic; - segment_43 : OUT std_ulogic; - segment_44 : OUT std_ulogic; - segment_45 : OUT std_ulogic; - segment_46 : OUT std_ulogic; - segment_47 : OUT std_ulogic; - segment_48 : OUT std_ulogic; - segment_49 : OUT std_ulogic; - segment_50 : OUT std_ulogic; - segment_51 : OUT std_ulogic; - segment_52 : OUT std_ulogic; - segment_53 : OUT std_ulogic; - segment_54 : OUT std_ulogic; - segment_55 : OUT std_ulogic; - segment_56 : OUT std_ulogic; - segment_57 : OUT std_ulogic; - segment_58 : OUT std_ulogic; - segment_59 : OUT std_ulogic; - segment_60 : OUT std_ulogic; - segment_61 : OUT std_ulogic; - segment_62 : OUT std_ulogic; - segment_63 : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8pmcell - PORT ( - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8scbcell - PORT ( - clock : IN std_ulogic; - interrupt : OUT std_ulogic; - rx : IN std_ulogic; - tx : OUT std_ulogic; - mosi_m : OUT std_ulogic; - miso_m : IN std_ulogic; - select_m_0 : OUT std_ulogic; - select_m_1 : OUT std_ulogic; - select_m_2 : OUT std_ulogic; - select_m_3 : OUT std_ulogic; - sclk_m : OUT std_ulogic; - mosi_s : IN std_ulogic; - miso_s : OUT std_ulogic; - select_s : IN std_ulogic; - sclk_s : IN std_ulogic; - scl : INOUT std_ulogic; - sda : INOUT std_ulogic); - END COMPONENT; - COMPONENT m0s8spcifcell - PORT ( - spcif_int : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tcpwmcell - PORT ( - clock : IN std_ulogic; - capture : IN std_ulogic; - count : IN std_ulogic; - reload : IN std_ulogic; - stop : IN std_ulogic; - start : IN std_ulogic; - tr_underflow : OUT std_ulogic; - tr_overflow : OUT std_ulogic; - tr_compare_match : OUT std_ulogic; - line_out : OUT std_ulogic; - line_out_compl : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tsscell - PORT ( - clk_seq : IN std_ulogic; - clk_adc : IN std_ulogic; - ext_reject : IN std_ulogic; - ext_sync : IN std_ulogic; - tx_sync : IN std_ulogic; - reject_in : IN std_ulogic; - start_in : IN std_ulogic; - lx_det_hi : OUT std_ulogic; - lx_det_lo : OUT std_ulogic; - rej_window : OUT std_ulogic; - tx_hilo : OUT std_ulogic; - phase_end : OUT std_ulogic; - phase_num_0 : OUT std_ulogic; - phase_num_1 : OUT std_ulogic; - phase_num_2 : OUT std_ulogic; - phase_num_3 : OUT std_ulogic; - ipq_reject : OUT std_ulogic; - ipq_start : OUT std_ulogic; - epq_reject : OUT std_ulogic; - epq_start : OUT std_ulogic; - mcs_reject : OUT std_ulogic; - mcs_start : OUT std_ulogic; - do_switch : OUT std_ulogic; - adc_start : OUT std_ulogic; - adc_done : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8wdtcell - PORT ( - wdt_int : OUT std_ulogic); - END COMPONENT; - COMPONENT macrocell - PORT ( - main_0 : IN std_ulogic; - main_1 : IN std_ulogic; - main_2 : IN std_ulogic; - main_3 : IN std_ulogic; - main_4 : IN std_ulogic; - main_5 : IN std_ulogic; - main_6 : IN std_ulogic; - main_7 : IN std_ulogic; - main_8 : IN std_ulogic; - main_9 : IN std_ulogic; - main_10 : IN std_ulogic; - main_11 : IN std_ulogic; - ar_0 : IN std_ulogic; - ap_0 : IN std_ulogic; - clock_0 : IN std_ulogic; - clk_en : IN std_ulogic; - cin : IN std_ulogic; - cpt0_0 : IN std_ulogic; - cpt0_1 : IN std_ulogic; - cpt0_2 : IN std_ulogic; - cpt0_3 : IN std_ulogic; - cpt0_4 : IN std_ulogic; - cpt0_5 : IN std_ulogic; - cpt0_6 : IN std_ulogic; - cpt0_7 : IN std_ulogic; - cpt0_8 : IN std_ulogic; - cpt0_9 : IN std_ulogic; - cpt0_10 : IN std_ulogic; - cpt0_11 : IN std_ulogic; - cpt1_0 : IN std_ulogic; - cpt1_1 : IN std_ulogic; - cpt1_2 : IN std_ulogic; - cpt1_3 : IN std_ulogic; - cpt1_4 : IN std_ulogic; - cpt1_5 : IN std_ulogic; - cpt1_6 : IN std_ulogic; - cpt1_7 : IN std_ulogic; - cpt1_8 : IN std_ulogic; - cpt1_9 : IN std_ulogic; - cpt1_10 : IN std_ulogic; - cpt1_11 : IN std_ulogic; - cout : OUT std_ulogic; - q : OUT std_ulogic; - q_fixed : OUT std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF macrocell : COMPONENT IS "clock_0"; - ATTRIBUTE udb_clken OF macrocell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF macrocell : COMPONENT IS "ar_0"; - ATTRIBUTE udb_preset OF macrocell : COMPONENT IS "ap_0"; - ATTRIBUTE udb_chain OF macrocell : COMPONENT IS "cin,cout"; - ATTRIBUTE chain_lsb OF macrocell : COMPONENT IS "cin"; - ATTRIBUTE chain_msb OF macrocell : COMPONENT IS "cout"; - COMPONENT p4abufcell - PORT ( - ctb_dsi_comp : OUT std_ulogic; - dsi_out : IN std_ulogic); - END COMPONENT; - COMPONENT p4anapumpcell - PORT ( - pump_clock : IN std_ulogic); - END COMPONENT; - COMPONENT p4csdcell - PORT ( - sense_out : OUT std_ulogic; - sample_out : OUT std_ulogic; - sense_in : IN std_ulogic; - sample_in : IN std_ulogic; - clk1 : IN std_ulogic; - clk2 : IN std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT p4csidac7cell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4csidac8cell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4ctbmblockcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT p4halfuabcell - PORT ( - clock : IN std_ulogic; - comp : OUT std_ulogic; - ctrl : IN std_ulogic); - END COMPONENT; - COMPONENT p4lpcompblockcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT p4lpcompcell - PORT ( - cmpout : OUT std_ulogic); - END COMPONENT; - COMPONENT p4rsbcell - END COMPONENT; - COMPONENT p4sarcell - PORT ( - clock : IN std_ulogic; - sample_done : OUT std_ulogic; - chan_id_valid : OUT std_ulogic; - chan_id_0 : OUT std_ulogic; - chan_id_1 : OUT std_ulogic; - chan_id_2 : OUT std_ulogic; - chan_id_3 : OUT std_ulogic; - data_valid : OUT std_ulogic; - data_0 : OUT std_ulogic; - data_1 : OUT std_ulogic; - data_2 : OUT std_ulogic; - data_3 : OUT std_ulogic; - data_4 : OUT std_ulogic; - data_5 : OUT std_ulogic; - data_6 : OUT std_ulogic; - data_7 : OUT std_ulogic; - data_8 : OUT std_ulogic; - data_9 : OUT std_ulogic; - data_10 : OUT std_ulogic; - data_11 : OUT std_ulogic; - eos_intr : OUT std_ulogic; - irq : OUT std_ulogic; - sw_negvref : IN std_ulogic; - cfg_st_sel_0 : IN std_ulogic; - cfg_st_sel_1 : IN std_ulogic; - cfg_average : IN std_ulogic; - cfg_resolution : IN std_ulogic; - cfg_differential : IN std_ulogic; - trigger : IN std_ulogic; - data_hilo_sel : IN std_ulogic; - swctrl0 : IN std_ulogic; - swctrl1 : IN std_ulogic); - END COMPONENT; - COMPONENT p4sarmuxcell - END COMPONENT; - COMPONENT p4tempcell - END COMPONENT; - COMPONENT p4vrefcell - END COMPONENT; - COMPONENT pmcell - PORT ( - ctw_int : OUT std_ulogic; - ftw_int : OUT std_ulogic; - limact_int : OUT std_ulogic; - onepps_int : OUT std_ulogic; - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - clk_udb : IN std_ulogic; - sof_udb : IN std_ulogic; - vp_ctl_udb_0 : IN std_ulogic; - vp_ctl_udb_1 : IN std_ulogic; - vp_ctl_udb_2 : IN std_ulogic; - vp_ctl_udb_3 : IN std_ulogic; - vn_ctl_udb_0 : IN std_ulogic; - vn_ctl_udb_1 : IN std_ulogic; - vn_ctl_udb_2 : IN std_ulogic; - vn_ctl_udb_3 : IN std_ulogic; - data_out_udb_0 : OUT std_ulogic; - data_out_udb_1 : OUT std_ulogic; - data_out_udb_2 : OUT std_ulogic; - data_out_udb_3 : OUT std_ulogic; - data_out_udb_4 : OUT std_ulogic; - data_out_udb_5 : OUT std_ulogic; - data_out_udb_6 : OUT std_ulogic; - data_out_udb_7 : OUT std_ulogic; - data_out_udb_8 : OUT std_ulogic; - data_out_udb_9 : OUT std_ulogic; - data_out_udb_10 : OUT std_ulogic; - data_out_udb_11 : OUT std_ulogic; - eof_udb : OUT std_ulogic; - irq : OUT std_ulogic; - next : OUT std_ulogic); - END COMPONENT; - COMPONENT sccell - PORT ( - aclk : IN std_ulogic; - bst_clk : IN std_ulogic; - clk_udb : IN std_ulogic; - modout : OUT std_ulogic; - dyn_cntl_udb : IN std_ulogic); - END COMPONENT; - COMPONENT spccell - PORT ( - data_ready : OUT std_ulogic; - eeprom_fault_int : OUT std_ulogic; - idle : OUT std_ulogic); - END COMPONENT; - COMPONENT ssccell - PORT ( - rst_n : IN std_ulogic; - scli : IN std_ulogic; - sdai : IN std_ulogic; - csel : IN std_ulogic; - sclo : OUT std_ulogic; - sdao : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT statuscell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - status_7 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF statuscell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF statuscell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF statuscell : COMPONENT IS "reset"; - COMPONENT statusicell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - interrupt : OUT std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF statusicell : COMPONENT IS "clock"; - ATTRIBUTE udb_clken OF statusicell : COMPONENT IS "clk_en"; - ATTRIBUTE udb_reset OF statusicell : COMPONENT IS "reset"; - COMPONENT synccell - PORT ( - in : IN std_ulogic; - clock : IN std_ulogic; - out : OUT std_ulogic; - clk_en : IN std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - ATTRIBUTE udb_clk OF synccell : COMPONENT IS "clock,clock_n,extclk,extclk_n"; - ATTRIBUTE udb_clken OF synccell : COMPONENT IS "clk_en"; - COMPONENT tfaultcell - PORT ( - tfault_dsi : OUT std_ulogic); - END COMPONENT; - COMPONENT timercell - PORT ( - clock : IN std_ulogic; - kill : IN std_ulogic; - enable : IN std_ulogic; - capture : IN std_ulogic; - timer_reset : IN std_ulogic; - tc : OUT std_ulogic; - cmp : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT udbclockencell - PORT ( - clock_in : IN std_ulogic; - enable : IN std_ulogic; - clock_out : OUT std_ulogic); - END COMPONENT; - COMPONENT usbcell - PORT ( - sof_int : OUT std_ulogic; - arb_int : OUT std_ulogic; - usb_int : OUT std_ulogic; - ord_int : OUT std_ulogic; - ept_int_0 : OUT std_ulogic; - ept_int_1 : OUT std_ulogic; - ept_int_2 : OUT std_ulogic; - ept_int_3 : OUT std_ulogic; - ept_int_4 : OUT std_ulogic; - ept_int_5 : OUT std_ulogic; - ept_int_6 : OUT std_ulogic; - ept_int_7 : OUT std_ulogic; - ept_int_8 : OUT std_ulogic; - dma_req_0 : OUT std_ulogic; - dma_req_1 : OUT std_ulogic; - dma_req_2 : OUT std_ulogic; - dma_req_3 : OUT std_ulogic; - dma_req_4 : OUT std_ulogic; - dma_req_5 : OUT std_ulogic; - dma_req_6 : OUT std_ulogic; - dma_req_7 : OUT std_ulogic; - dma_termin : OUT std_ulogic); - END COMPONENT; - COMPONENT vidaccell - PORT ( - data_0 : IN std_ulogic; - data_1 : IN std_ulogic; - data_2 : IN std_ulogic; - data_3 : IN std_ulogic; - data_4 : IN std_ulogic; - data_5 : IN std_ulogic; - data_6 : IN std_ulogic; - data_7 : IN std_ulogic; - strobe : IN std_ulogic; - strobe_udb : IN std_ulogic; - reset : IN std_ulogic; - idir : IN std_ulogic; - ioff : IN std_ulogic); - END COMPONENT; -BEGIN - - ClockBlock:clockblockcell - PORT MAP( - clk_bus_glb => ClockBlock_BUS_CLK, - clk_bus => ClockBlock_BUS_CLK_local, - clk_sync => ClockBlock_MASTER_CLK, - clk_32k_xtal => ClockBlock_XTAL_32KHZ, - xtal => ClockBlock_XTAL, - ilo => ClockBlock_ILO, - clk_100k => ClockBlock_100k, - clk_1k => ClockBlock_1k, - clk_32k => ClockBlock_32k, - pllout => ClockBlock_PLL_OUT, - imo => ClockBlock_IMO, - dsi_clkin_div => open, - dsi_glb_div => open); - - SCSI_Out:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110110110110", - ibuf_enabled => "1111111111", - id => "11f071e8-9c92-47e0-872a-3f48765a75b8", - init_dr_st => "0000000000", - input_clk_en => 0, - input_sync => "1111111111", - input_sync_mode => "0000000000", - intr_mode => "00000000000000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "5, 5, 5, 5, 5, 5, 5, 5, 5, 5", - layout_mode => "NONCONTIGUOUS", - oe_conn => "0000000000", - oe_reset => 0, - oe_sync => "0000000000", - output_clk_en => 0, - output_clock_mode => "0000000000", - output_conn => "0000000000", - output_mode => "0000000000", - output_reset => 0, - output_sync => "0000000000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "DBP_raw,ATN,BSY,ACK,RST,MSG,SEL,CD,REQ,IO_raw", - pin_mode => "OOOOOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0000000000", - sio_ibuf => "00000000", - sio_info => "00000000000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0000000000", - spanning => 1, - sw_only => 0, - use_annotation => "1111111111", - vtrip => "10101010101010101010", - width => 10, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - SCSI_Out(0):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(0)__PA, - oe => open, - pad_in => SCSI_Out(0)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(1):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(1)__PA, - oe => open, - pad_in => SCSI_Out(1)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(2):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(2)__PA, - oe => open, - pad_in => SCSI_Out(2)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(3):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(3)__PA, - oe => open, - pad_in => SCSI_Out(3)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(4):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(4)__PA, - oe => open, - pad_in => SCSI_Out(4)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(5):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(5)__PA, - oe => open, - pad_in => SCSI_Out(5)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(6):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(6)__PA, - oe => open, - pad_in => SCSI_Out(6)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(7):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 7, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(7)__PA, - oe => open, - pad_in => SCSI_Out(7)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(8):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 8, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(8)__PA, - oe => open, - pad_in => SCSI_Out(8)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(9):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 9, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(9)__PA, - oe => open, - pad_in => SCSI_Out(9)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110110", - ibuf_enabled => "11111111", - id => "52f31aa9-2f0a-497d-9a1f-1424095e13e6", - init_dr_st => "00000000", - input_clk_en => 0, - input_sync => "11111111", - input_sync_mode => "00000000", - intr_mode => "0000000000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => ", , , , , , , 5", - layout_mode => "NONCONTIGUOUS", - oe_conn => "00000000", - oe_reset => 0, - oe_sync => "00000000", - output_clk_en => 0, - output_clock_mode => "00000000", - output_conn => "00000000", - output_mode => "00000000", - output_reset => 0, - output_sync => "00000000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "DB0,DB1,DB2,DB3,DB4,DB5,DB6,DB7", - pin_mode => "OOOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "00000000", - sio_ibuf => "00000000", - sio_info => "0000000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "00000000", - spanning => 1, - sw_only => 0, - use_annotation => "11111111", - vtrip => "1010101010101010", - width => 8, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - SCSI_Out_DBx(0):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(0)__PA, - oe => open, - pad_in => SCSI_Out_DBx(0)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(1):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(1)__PA, - oe => open, - pad_in => SCSI_Out_DBx(1)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(2):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(2)__PA, - oe => open, - pad_in => SCSI_Out_DBx(2)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(3):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(3)__PA, - oe => open, - pad_in => SCSI_Out_DBx(3)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(4):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(4)__PA, - oe => open, - pad_in => SCSI_Out_DBx(4)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(5):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(5)__PA, - oe => open, - pad_in => SCSI_Out_DBx(5)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(6):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(6)__PA, - oe => open, - pad_in => SCSI_Out_DBx(6)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(7):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 7, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(7)__PA, - oe => open, - pad_in => SCSI_Out_DBx(7)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP:logicalport - GENERIC MAP( - drive_mode => "010010010010010", - ibuf_enabled => "11111", - id => "4c15b41e-e284-4978-99e7-5aaee19bd0ce", - init_dr_st => "11111", - input_clk_en => 0, - input_sync => "11111", - input_sync_mode => "00000", - intr_mode => "0000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "3.3, , , , ", - layout_mode => "CONTIGUOUS", - oe_conn => "00000", - oe_reset => 0, - oe_sync => "00000", - output_clk_en => 0, - output_clock_mode => "00000", - output_conn => "00000", - output_mode => "00000", - output_reset => 0, - output_sync => "00000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => ",,,,", - pin_mode => "IIIII", - por_state => 2, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "00000", - sio_ibuf => "00000000", - sio_info => "0000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "00000", - spanning => 0, - sw_only => 0, - use_annotation => "00000", - vtrip => "0000000000", - width => 5, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open, - in_clock => open); - - SD_PULLUP(0):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(0)__PA, - oe => open, - pad_in => SD_PULLUP(0)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(1):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(1)__PA, - oe => open, - pad_in => SD_PULLUP(1)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(2):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(2)__PA, - oe => open, - pad_in => SD_PULLUP(2)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(3):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(3)__PA, - oe => open, - pad_in => SD_PULLUP(3)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(4):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(4)__PA, - oe => open, - pad_in => SD_PULLUP(4)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dm(0)\:iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "\USBFS:Dm\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000010000000000000000") - PORT MAP( - pa_out => \\\USBFS:Dm(0)\\__PA\, - oe => open, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dm\:logicalport - GENERIC MAP( - drive_mode => "000", - ibuf_enabled => "0", - id => "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/8b77a6c4-10a0-4390-971c-672353e2a49c", - init_dr_st => "0", - input_clk_en => 0, - input_sync => "1", - input_sync_mode => "0", - intr_mode => "00", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "", - layout_mode => "NONCONTIGUOUS", - oe_conn => "0", - oe_reset => 0, - oe_sync => "0", - output_clk_en => 0, - output_clock_mode => "0", - output_conn => "0", - output_mode => "0", - output_reset => 0, - output_sync => "0", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "", - pin_mode => "A", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 1, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - \USBFS:Dp(0)\:iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "\USBFS:Dp\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000001000000000000000") - PORT MAP( - pa_out => \\\USBFS:Dp(0)\\__PA\, - oe => open, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dp\:logicalport - GENERIC MAP( - drive_mode => "000", - ibuf_enabled => "0", - id => "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42", - init_dr_st => "0", - input_clk_en => 0, - input_sync => "1", - input_sync_mode => "0", - intr_mode => "10", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - oe_reset => 0, - oe_sync => "0", - output_clk_en => 0, - output_clock_mode => "0", - output_conn => "0", - output_mode => "0", - output_reset => 0, - output_sync => "0", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "", - pin_mode => "I", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "00", - width => 1, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open, - interrupt => \USBFS:Net_1010\, - in_clock => open); - - \USBFS:USB\:usbcell - GENERIC MAP( - cy_registers => "") - PORT MAP( - sof_int => Net_40, - arb_int => \USBFS:Net_79\, - usb_int => \USBFS:Net_81\, - ept_int_8 => \USBFS:ept_int_8\, - ept_int_7 => \USBFS:ept_int_7\, - ept_int_6 => \USBFS:ept_int_6\, - ept_int_5 => \USBFS:ept_int_5\, - ept_int_4 => \USBFS:ept_int_4\, - ept_int_3 => \USBFS:ept_int_3\, - ept_int_2 => \USBFS:ept_int_2\, - ept_int_1 => \USBFS:ept_int_1\, - ept_int_0 => \USBFS:ept_int_0\, - ord_int => \USBFS:Net_95\, - dma_req_7 => \USBFS:dma_req_7\, - dma_req_6 => \USBFS:dma_req_6\, - dma_req_5 => \USBFS:dma_req_5\, - dma_req_4 => \USBFS:dma_req_4\, - dma_req_3 => \USBFS:dma_req_3\, - dma_req_2 => \USBFS:dma_req_2\, - dma_req_1 => \USBFS:dma_req_1\, - dma_req_0 => \USBFS:dma_req_0\, - dma_termin => \USBFS:Net_824\); - - \USBFS:arb_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_79\, - clock => ClockBlock_BUS_CLK); - - \USBFS:bus_reset\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_81\, - clock => ClockBlock_BUS_CLK); - - \USBFS:dp_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_1010\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_0\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_0\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_1\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_1\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_2\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_2\, - clock => ClockBlock_BUS_CLK); - - \USBFS:sof_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => Net_40, - clock => ClockBlock_BUS_CLK); - -END __DEFAULT__; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib deleted file mode 100755 index b4f81be..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.lib +++ /dev/null @@ -1,1699 +0,0 @@ -library (timing) { - timescale : 1ns; - capacitive_load_unit (1,ff); - include_file(device.lib); - cell (iocell1) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.445; - intrinsic_fall : 16.445; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.445; - intrinsic_fall : 16.445; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.093; - intrinsic_fall : 15.093; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.033; - intrinsic_fall : 7.033; - } - } - } - cell (iocell2) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.297; - intrinsic_fall : 17.297; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.297; - intrinsic_fall : 17.297; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.111; - intrinsic_fall : 15.111; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.255; - intrinsic_fall : 7.255; - } - } - } - cell (iocell3) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.269; - intrinsic_fall : 17.269; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.269; - intrinsic_fall : 17.269; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.495; - intrinsic_fall : 15.495; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.644; - intrinsic_fall : 7.644; - } - } - } - cell (iocell4) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.371; - intrinsic_fall : 17.371; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.371; - intrinsic_fall : 17.371; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.561; - intrinsic_fall : 15.561; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.354; - intrinsic_fall : 7.354; - } - } - } - cell (iocell5) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.023; - intrinsic_fall : 15.023; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 8.264; - intrinsic_fall : 8.264; - } - } - } - cell (iocell6) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.718; - intrinsic_fall : 17.718; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.718; - intrinsic_fall : 17.718; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.880; - intrinsic_fall : 14.880; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.563; - intrinsic_fall : 7.563; - } - } - } - cell (iocell7) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.610; - intrinsic_fall : 17.610; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.610; - intrinsic_fall : 17.610; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.744; - intrinsic_fall : 15.744; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.958; - intrinsic_fall : 7.958; - } - } - } - cell (iocell8) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.428; - intrinsic_fall : 17.428; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.428; - intrinsic_fall : 17.428; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.459; - intrinsic_fall : 15.459; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.950; - intrinsic_fall : 7.950; - } - } - } - cell (iocell9) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.434; - intrinsic_fall : 17.434; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.434; - intrinsic_fall : 17.434; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.802; - intrinsic_fall : 15.802; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.962; - intrinsic_fall : 7.962; - } - } - } - cell (iocell10) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.161; - intrinsic_fall : 17.161; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.161; - intrinsic_fall : 17.161; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.251; - intrinsic_fall : 15.251; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.922; - intrinsic_fall : 7.922; - } - } - } - cell (iocell11) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.840; - intrinsic_fall : 17.840; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.840; - intrinsic_fall : 17.840; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.011; - intrinsic_fall : 15.011; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.576; - intrinsic_fall : 7.576; - } - } - } - cell (iocell12) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.165; - intrinsic_fall : 17.165; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.165; - intrinsic_fall : 17.165; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.746; - intrinsic_fall : 15.746; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.331; - intrinsic_fall : 7.331; - } - } - } - cell (iocell13) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.973; - intrinsic_fall : 16.973; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.973; - intrinsic_fall : 16.973; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.880; - intrinsic_fall : 14.880; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.065; - intrinsic_fall : 7.065; - } - } - } - cell (iocell14) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.979; - intrinsic_fall : 16.979; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.979; - intrinsic_fall : 16.979; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.914; - intrinsic_fall : 14.914; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.816; - intrinsic_fall : 7.816; - } - } - } - cell (iocell15) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.374; - intrinsic_fall : 17.374; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.374; - intrinsic_fall : 17.374; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.222; - intrinsic_fall : 15.222; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.459; - intrinsic_fall : 7.459; - } - } - } - cell (iocell16) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.157; - intrinsic_fall : 17.157; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.157; - intrinsic_fall : 17.157; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.976; - intrinsic_fall : 15.976; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.582; - intrinsic_fall : 7.582; - } - } - } - cell (iocell17) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.578; - intrinsic_fall : 16.578; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.578; - intrinsic_fall : 16.578; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.347; - intrinsic_fall : 15.347; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.368; - intrinsic_fall : 7.368; - } - } - } - cell (iocell18) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.786; - intrinsic_fall : 17.786; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.786; - intrinsic_fall : 17.786; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.004; - intrinsic_fall : 16.004; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 6.974; - intrinsic_fall : 6.974; - } - } - } - cell (iocell19) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.419; - intrinsic_fall : 16.419; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.419; - intrinsic_fall : 16.419; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.979; - intrinsic_fall : 14.979; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 1.661; - intrinsic_fall : 1.661; - } - } - } - cell (iocell20) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.643; - intrinsic_fall : 17.643; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.643; - intrinsic_fall : 17.643; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.995; - intrinsic_fall : 14.995; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 1.852; - intrinsic_fall : 1.852; - } - } - } - cell (iocell21) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.081; - intrinsic_fall : 17.081; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.081; - intrinsic_fall : 17.081; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.591; - intrinsic_fall : 14.591; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 3.163; - intrinsic_fall : 3.163; - } - } - } - cell (iocell22) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.646; - intrinsic_fall : 16.646; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.646; - intrinsic_fall : 16.646; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.987; - intrinsic_fall : 14.987; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.191; - intrinsic_fall : 2.191; - } - } - } - cell (iocell23) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.787; - intrinsic_fall : 17.787; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.787; - intrinsic_fall : 17.787; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.338; - intrinsic_fall : 15.338; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.064; - intrinsic_fall : 2.064; - } - } - } - cell (iocell24) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.053; - intrinsic_fall : 19.053; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 9.497; - intrinsic_fall : 9.497; - } - } - } - cell (iocell25) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.129; - intrinsic_fall : 19.129; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.717; - intrinsic_fall : 2.717; - } - } - } -} diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2 deleted file mode 100755 index eb4dbe8..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_r.vh2 +++ /dev/null @@ -1,1972 +0,0 @@ --- Project: USB_Bootloader --- Generated: 03/22/2014 22:32:52 --- - -ENTITY USB_Bootloader IS - PORT( - SCSI_Out(0)_PAD : OUT std_ulogic; - SCSI_Out(1)_PAD : OUT std_ulogic; - SCSI_Out(2)_PAD : OUT std_ulogic; - SCSI_Out(3)_PAD : OUT std_ulogic; - SCSI_Out(4)_PAD : OUT std_ulogic; - SCSI_Out(5)_PAD : OUT std_ulogic; - SCSI_Out(6)_PAD : OUT std_ulogic; - SCSI_Out(7)_PAD : OUT std_ulogic; - SCSI_Out(8)_PAD : OUT std_ulogic; - SCSI_Out(9)_PAD : OUT std_ulogic; - SCSI_Out_DBx(0)_PAD : OUT std_ulogic; - SCSI_Out_DBx(1)_PAD : OUT std_ulogic; - SCSI_Out_DBx(2)_PAD : OUT std_ulogic; - SCSI_Out_DBx(3)_PAD : OUT std_ulogic; - SCSI_Out_DBx(4)_PAD : OUT std_ulogic; - SCSI_Out_DBx(5)_PAD : OUT std_ulogic; - SCSI_Out_DBx(6)_PAD : OUT std_ulogic; - SCSI_Out_DBx(7)_PAD : OUT std_ulogic; - SD_PULLUP(0)_PAD : IN std_ulogic; - SD_PULLUP(1)_PAD : IN std_ulogic; - SD_PULLUP(2)_PAD : IN std_ulogic; - SD_PULLUP(3)_PAD : IN std_ulogic; - SD_PULLUP(4)_PAD : IN std_ulogic); - ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio3 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vdda OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio0 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio2 OF __DEFAULT__ : ENTITY IS 5e0; -END USB_Bootloader; - -ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS - SIGNAL ClockBlock_100k : bit; - SIGNAL ClockBlock_1k : bit; - SIGNAL ClockBlock_32k : bit; - SIGNAL ClockBlock_BUS_CLK : bit; - ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; - SIGNAL ClockBlock_BUS_CLK_local : bit; - SIGNAL ClockBlock_ILO : bit; - SIGNAL ClockBlock_IMO : bit; - SIGNAL ClockBlock_MASTER_CLK : bit; - SIGNAL ClockBlock_PLL_OUT : bit; - SIGNAL ClockBlock_XTAL : bit; - SIGNAL ClockBlock_XTAL_32KHZ : bit; - SIGNAL Net_40 : bit; - SIGNAL SCSI_Out(0)__PA : bit; - SIGNAL SCSI_Out(1)__PA : bit; - SIGNAL SCSI_Out(2)__PA : bit; - SIGNAL SCSI_Out(3)__PA : bit; - SIGNAL SCSI_Out(4)__PA : bit; - SIGNAL SCSI_Out(5)__PA : bit; - SIGNAL SCSI_Out(6)__PA : bit; - SIGNAL SCSI_Out(7)__PA : bit; - SIGNAL SCSI_Out(8)__PA : bit; - SIGNAL SCSI_Out(9)__PA : bit; - SIGNAL SCSI_Out_DBx(0)__PA : bit; - SIGNAL SCSI_Out_DBx(1)__PA : bit; - SIGNAL SCSI_Out_DBx(2)__PA : bit; - SIGNAL SCSI_Out_DBx(3)__PA : bit; - SIGNAL SCSI_Out_DBx(4)__PA : bit; - SIGNAL SCSI_Out_DBx(5)__PA : bit; - SIGNAL SCSI_Out_DBx(6)__PA : bit; - SIGNAL SCSI_Out_DBx(7)__PA : bit; - SIGNAL SD_PULLUP(0)__PA : bit; - SIGNAL SD_PULLUP(1)__PA : bit; - SIGNAL SD_PULLUP(2)__PA : bit; - SIGNAL SD_PULLUP(3)__PA : bit; - SIGNAL SD_PULLUP(4)__PA : bit; - SIGNAL \\\USBFS:Dm(0)\\__PA\ : bit; - SIGNAL \\\USBFS:Dp(0)\\__PA\ : bit; - SIGNAL \USBFS:Net_1010\ : bit; - SIGNAL \USBFS:Net_79\ : bit; - SIGNAL \USBFS:Net_81\ : bit; - SIGNAL \USBFS:Net_824\ : bit; - SIGNAL \USBFS:Net_95\ : bit; - SIGNAL \USBFS:dma_req_0\ : bit; - SIGNAL \USBFS:dma_req_1\ : bit; - SIGNAL \USBFS:dma_req_2\ : bit; - SIGNAL \USBFS:dma_req_3\ : bit; - SIGNAL \USBFS:dma_req_4\ : bit; - SIGNAL \USBFS:dma_req_5\ : bit; - SIGNAL \USBFS:dma_req_6\ : bit; - SIGNAL \USBFS:dma_req_7\ : bit; - SIGNAL \USBFS:ept_int_0\ : bit; - SIGNAL \USBFS:ept_int_1\ : bit; - SIGNAL \USBFS:ept_int_2\ : bit; - SIGNAL \USBFS:ept_int_3\ : bit; - SIGNAL \USBFS:ept_int_4\ : bit; - SIGNAL \USBFS:ept_int_5\ : bit; - SIGNAL \USBFS:ept_int_6\ : bit; - SIGNAL \USBFS:ept_int_7\ : bit; - SIGNAL \USBFS:ept_int_8\ : bit; - SIGNAL __ONE__ : bit; - ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; - SIGNAL __ZERO__ : bit; - ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; - SIGNAL one : bit; - ATTRIBUTE POWER OF one : SIGNAL IS true; - SIGNAL zero : bit; - ATTRIBUTE GROUND OF zero : SIGNAL IS true; - ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; - ATTRIBUTE lib_model OF SCSI_Out(0) : LABEL IS "iocell1"; - ATTRIBUTE Location OF SCSI_Out(0) : LABEL IS "P4[3]"; - ATTRIBUTE lib_model OF SCSI_Out(1) : LABEL IS "iocell2"; - ATTRIBUTE Location OF SCSI_Out(1) : LABEL IS "P4[2]"; - ATTRIBUTE lib_model OF SCSI_Out(2) : LABEL IS "iocell3"; - ATTRIBUTE Location OF SCSI_Out(2) : LABEL IS "P0[7]"; - ATTRIBUTE lib_model OF SCSI_Out(3) : LABEL IS "iocell4"; - ATTRIBUTE Location OF SCSI_Out(3) : LABEL IS "P0[6]"; - ATTRIBUTE lib_model OF SCSI_Out(4) : LABEL IS "iocell5"; - ATTRIBUTE Location OF SCSI_Out(4) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF SCSI_Out(5) : LABEL IS "iocell6"; - ATTRIBUTE Location OF SCSI_Out(5) : LABEL IS "P0[4]"; - ATTRIBUTE lib_model OF SCSI_Out(6) : LABEL IS "iocell7"; - ATTRIBUTE Location OF SCSI_Out(6) : LABEL IS "P0[3]"; - ATTRIBUTE lib_model OF SCSI_Out(7) : LABEL IS "iocell8"; - ATTRIBUTE Location OF SCSI_Out(7) : LABEL IS "P0[2]"; - ATTRIBUTE lib_model OF SCSI_Out(8) : LABEL IS "iocell9"; - ATTRIBUTE Location OF SCSI_Out(8) : LABEL IS "P0[1]"; - ATTRIBUTE lib_model OF SCSI_Out(9) : LABEL IS "iocell10"; - ATTRIBUTE Location OF SCSI_Out(9) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(0) : LABEL IS "iocell11"; - ATTRIBUTE Location OF SCSI_Out_DBx(0) : LABEL IS "P6[3]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(1) : LABEL IS "iocell12"; - ATTRIBUTE Location OF SCSI_Out_DBx(1) : LABEL IS "P6[2]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(2) : LABEL IS "iocell13"; - ATTRIBUTE Location OF SCSI_Out_DBx(2) : LABEL IS "P6[1]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(3) : LABEL IS "iocell14"; - ATTRIBUTE Location OF SCSI_Out_DBx(3) : LABEL IS "P6[0]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(4) : LABEL IS "iocell15"; - ATTRIBUTE Location OF SCSI_Out_DBx(4) : LABEL IS "P4[7]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(5) : LABEL IS "iocell16"; - ATTRIBUTE Location OF SCSI_Out_DBx(5) : LABEL IS "P4[6]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(6) : LABEL IS "iocell17"; - ATTRIBUTE Location OF SCSI_Out_DBx(6) : LABEL IS "P4[5]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(7) : LABEL IS "iocell18"; - ATTRIBUTE Location OF SCSI_Out_DBx(7) : LABEL IS "P4[4]"; - ATTRIBUTE lib_model OF SD_PULLUP(0) : LABEL IS "iocell19"; - ATTRIBUTE Location OF SD_PULLUP(0) : LABEL IS "P3[1]"; - ATTRIBUTE lib_model OF SD_PULLUP(1) : LABEL IS "iocell20"; - ATTRIBUTE Location OF SD_PULLUP(1) : LABEL IS "P3[2]"; - ATTRIBUTE lib_model OF SD_PULLUP(2) : LABEL IS "iocell21"; - ATTRIBUTE Location OF SD_PULLUP(2) : LABEL IS "P3[3]"; - ATTRIBUTE lib_model OF SD_PULLUP(3) : LABEL IS "iocell22"; - ATTRIBUTE Location OF SD_PULLUP(3) : LABEL IS "P3[4]"; - ATTRIBUTE lib_model OF SD_PULLUP(4) : LABEL IS "iocell23"; - ATTRIBUTE Location OF SD_PULLUP(4) : LABEL IS "P3[5]"; - ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell24"; - ATTRIBUTE Location OF \USBFS:Dm(0)\ : LABEL IS "P15[7]"; - ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell25"; - ATTRIBUTE Location OF \USBFS:Dp(0)\ : LABEL IS "P15[6]"; - ATTRIBUTE Location OF \USBFS:Dp\ : LABEL IS "F(PICU,8)"; - ATTRIBUTE Location OF \USBFS:USB\ : LABEL IS "F(USB,0)"; - ATTRIBUTE Location OF \USBFS:arb_int\ : LABEL IS "[IntrHod=(0)][IntrId=(22)]"; - ATTRIBUTE Location OF \USBFS:bus_reset\ : LABEL IS "[IntrHod=(0)][IntrId=(23)]"; - ATTRIBUTE Location OF \USBFS:dp_int\ : LABEL IS "[IntrHod=(0)][IntrId=(12)]"; - ATTRIBUTE Location OF \USBFS:ep_0\ : LABEL IS "[IntrHod=(0)][IntrId=(24)]"; - ATTRIBUTE Location OF \USBFS:ep_1\ : LABEL IS "[IntrHod=(0)][IntrId=(0)]"; - ATTRIBUTE Location OF \USBFS:ep_2\ : LABEL IS "[IntrHod=(0)][IntrId=(1)]"; - ATTRIBUTE Location OF \USBFS:sof_int\ : LABEL IS "[IntrHod=(0)][IntrId=(21)]"; - COMPONENT abufcell - END COMPONENT; - COMPONENT boostcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cachecell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cancell - PORT ( - clock : IN std_ulogic; - can_rx : IN std_ulogic; - can_tx : OUT std_ulogic; - can_tx_en : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT capsensecell - PORT ( - lft : IN std_ulogic; - rt : IN std_ulogic); - END COMPONENT; - COMPONENT clockblockcell - PORT ( - dclk_0 : OUT std_ulogic; - dclk_1 : OUT std_ulogic; - dclk_2 : OUT std_ulogic; - dclk_3 : OUT std_ulogic; - dclk_4 : OUT std_ulogic; - dclk_5 : OUT std_ulogic; - dclk_6 : OUT std_ulogic; - dclk_7 : OUT std_ulogic; - dclk_glb_0 : OUT std_ulogic; - dclk_glb_1 : OUT std_ulogic; - dclk_glb_2 : OUT std_ulogic; - dclk_glb_3 : OUT std_ulogic; - dclk_glb_4 : OUT std_ulogic; - dclk_glb_5 : OUT std_ulogic; - dclk_glb_6 : OUT std_ulogic; - dclk_glb_7 : OUT std_ulogic; - aclk_0 : OUT std_ulogic; - aclk_1 : OUT std_ulogic; - aclk_2 : OUT std_ulogic; - aclk_3 : OUT std_ulogic; - aclk_glb_0 : OUT std_ulogic; - aclk_glb_1 : OUT std_ulogic; - aclk_glb_2 : OUT std_ulogic; - aclk_glb_3 : OUT std_ulogic; - clk_a_dig_0 : OUT std_ulogic; - clk_a_dig_1 : OUT std_ulogic; - clk_a_dig_2 : OUT std_ulogic; - clk_a_dig_3 : OUT std_ulogic; - clk_a_dig_glb_0 : OUT std_ulogic; - clk_a_dig_glb_1 : OUT std_ulogic; - clk_a_dig_glb_2 : OUT std_ulogic; - clk_a_dig_glb_3 : OUT std_ulogic; - clk_bus : OUT std_ulogic; - clk_bus_glb : OUT std_ulogic; - clk_sync : OUT std_ulogic; - clk_32k_xtal : OUT std_ulogic; - clk_100k : OUT std_ulogic; - clk_32k : OUT std_ulogic; - clk_1k : OUT std_ulogic; - clk_usb : OUT std_ulogic; - xmhz_xerr : OUT std_ulogic; - pll_lock_out : OUT std_ulogic; - dsi_dig_div_0 : IN std_ulogic; - dsi_dig_div_1 : IN std_ulogic; - dsi_dig_div_2 : IN std_ulogic; - dsi_dig_div_3 : IN std_ulogic; - dsi_dig_div_4 : IN std_ulogic; - dsi_dig_div_5 : IN std_ulogic; - dsi_dig_div_6 : IN std_ulogic; - dsi_dig_div_7 : IN std_ulogic; - dsi_ana_div_0 : IN std_ulogic; - dsi_ana_div_1 : IN std_ulogic; - dsi_ana_div_2 : IN std_ulogic; - dsi_ana_div_3 : IN std_ulogic; - dsi_glb_div : IN std_ulogic; - dsi_clkin_div : IN std_ulogic; - imo : OUT std_ulogic; - ilo : OUT std_ulogic; - xtal : OUT std_ulogic; - pllout : OUT std_ulogic; - clk_bus_glb_ff : OUT std_ulogic; - aclk_glb_ff_0 : OUT std_ulogic; - clk_a_dig_glb_ff_0 : OUT std_ulogic; - aclk_glb_ff_1 : OUT std_ulogic; - clk_a_dig_glb_ff_1 : OUT std_ulogic; - aclk_glb_ff_2 : OUT std_ulogic; - clk_a_dig_glb_ff_2 : OUT std_ulogic; - aclk_glb_ff_3 : OUT std_ulogic; - clk_a_dig_glb_ff_3 : OUT std_ulogic; - dclk_glb_ff_0 : OUT std_ulogic; - dclk_glb_ff_1 : OUT std_ulogic; - dclk_glb_ff_2 : OUT std_ulogic; - dclk_glb_ff_3 : OUT std_ulogic; - dclk_glb_ff_4 : OUT std_ulogic; - dclk_glb_ff_5 : OUT std_ulogic; - dclk_glb_ff_6 : OUT std_ulogic; - dclk_glb_ff_7 : OUT std_ulogic); - END COMPONENT; - COMPONENT comparatorcell - PORT ( - out : OUT std_ulogic; - clk_udb : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT controlcell - PORT ( - control_0 : OUT std_ulogic; - control_1 : OUT std_ulogic; - control_2 : OUT std_ulogic; - control_3 : OUT std_ulogic; - control_4 : OUT std_ulogic; - control_5 : OUT std_ulogic; - control_6 : OUT std_ulogic; - control_7 : OUT std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT count7cell - PORT ( - clock : IN std_ulogic; - reset : IN std_ulogic; - load : IN std_ulogic; - enable : IN std_ulogic; - clk_en : IN std_ulogic; - count_0 : OUT std_ulogic; - count_1 : OUT std_ulogic; - count_2 : OUT std_ulogic; - count_3 : OUT std_ulogic; - count_4 : OUT std_ulogic; - count_5 : OUT std_ulogic; - count_6 : OUT std_ulogic; - tc : OUT std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT csabufcell - PORT ( - swon : IN std_ulogic); - END COMPONENT; - COMPONENT datapathcell - PORT ( - clock : IN std_ulogic; - clk_en : IN std_ulogic; - reset : IN std_ulogic; - cs_addr_0 : IN std_ulogic; - cs_addr_1 : IN std_ulogic; - cs_addr_2 : IN std_ulogic; - route_si : IN std_ulogic; - route_ci : IN std_ulogic; - f0_load : IN std_ulogic; - f1_load : IN std_ulogic; - d0_load : IN std_ulogic; - d1_load : IN std_ulogic; - ce0_reg : OUT std_ulogic; - cl0_reg : OUT std_ulogic; - z0_reg : OUT std_ulogic; - f0_reg : OUT std_ulogic; - ce1_reg : OUT std_ulogic; - cl1_reg : OUT std_ulogic; - z1_reg : OUT std_ulogic; - f1_reg : OUT std_ulogic; - ov_msb_reg : OUT std_ulogic; - co_msb_reg : OUT std_ulogic; - cmsb_reg : OUT std_ulogic; - so_reg : OUT std_ulogic; - f0_bus_stat_reg : OUT std_ulogic; - f0_blk_stat_reg : OUT std_ulogic; - f1_bus_stat_reg : OUT std_ulogic; - f1_blk_stat_reg : OUT std_ulogic; - ce0_comb : OUT std_ulogic; - cl0_comb : OUT std_ulogic; - z0_comb : OUT std_ulogic; - f0_comb : OUT std_ulogic; - ce1_comb : OUT std_ulogic; - cl1_comb : OUT std_ulogic; - z1_comb : OUT std_ulogic; - f1_comb : OUT std_ulogic; - ov_msb_comb : OUT std_ulogic; - co_msb_comb : OUT std_ulogic; - cmsb_comb : OUT std_ulogic; - so_comb : OUT std_ulogic; - f0_bus_stat_comb : OUT std_ulogic; - f0_blk_stat_comb : OUT std_ulogic; - f1_bus_stat_comb : OUT std_ulogic; - f1_blk_stat_comb : OUT std_ulogic; - ce0 : OUT std_ulogic; - ce0i : IN std_ulogic; - p_in_0 : IN std_ulogic; - p_in_1 : IN std_ulogic; - p_in_2 : IN std_ulogic; - p_in_3 : IN std_ulogic; - p_in_4 : IN std_ulogic; - p_in_5 : IN std_ulogic; - p_in_6 : IN std_ulogic; - p_in_7 : IN std_ulogic; - p_out_0 : OUT std_ulogic; - p_out_1 : OUT std_ulogic; - p_out_2 : OUT std_ulogic; - p_out_3 : OUT std_ulogic; - p_out_4 : OUT std_ulogic; - p_out_5 : OUT std_ulogic; - p_out_6 : OUT std_ulogic; - p_out_7 : OUT std_ulogic; - cl0i : IN std_ulogic; - cl0 : OUT std_ulogic; - z0i : IN std_ulogic; - z0 : OUT std_ulogic; - ff0i : IN std_ulogic; - ff0 : OUT std_ulogic; - ce1i : IN std_ulogic; - ce1 : OUT std_ulogic; - cl1i : IN std_ulogic; - cl1 : OUT std_ulogic; - z1i : IN std_ulogic; - z1 : OUT std_ulogic; - ff1i : IN std_ulogic; - ff1 : OUT std_ulogic; - cap0i : IN std_ulogic; - cap0 : OUT std_ulogic; - cap1i : IN std_ulogic; - cap1 : OUT std_ulogic; - ci : IN std_ulogic; - co_msb : OUT std_ulogic; - sir : IN std_ulogic; - sol_msb : OUT std_ulogic; - cfbi : IN std_ulogic; - cfbo : OUT std_ulogic; - sil : IN std_ulogic; - sor : OUT std_ulogic; - cmsbi : IN std_ulogic; - cmsbo : OUT std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT decimatorcell - PORT ( - aclock : IN std_ulogic; - mod_dat_0 : IN std_ulogic; - mod_dat_1 : IN std_ulogic; - mod_dat_2 : IN std_ulogic; - mod_dat_3 : IN std_ulogic; - ext_start : IN std_ulogic; - modrst : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT dfbcell - PORT ( - clock : IN std_ulogic; - in_1 : IN std_ulogic; - in_2 : IN std_ulogic; - out_1 : OUT std_ulogic; - out_2 : OUT std_ulogic; - dmareq_1 : OUT std_ulogic; - dmareq_2 : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT drqcell - PORT ( - dmareq : IN std_ulogic; - termin : IN std_ulogic; - termout : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT dsmodcell - PORT ( - aclock : IN std_ulogic; - modbitin_udb : IN std_ulogic; - reset_udb : IN std_ulogic; - reset_dec : IN std_ulogic; - dec_clock : OUT std_ulogic; - mod_dat_0 : OUT std_ulogic; - mod_dat_1 : OUT std_ulogic; - mod_dat_2 : OUT std_ulogic; - mod_dat_3 : OUT std_ulogic; - dout_udb_0 : OUT std_ulogic; - dout_udb_1 : OUT std_ulogic; - dout_udb_2 : OUT std_ulogic; - dout_udb_3 : OUT std_ulogic; - dout_udb_4 : OUT std_ulogic; - dout_udb_5 : OUT std_ulogic; - dout_udb_6 : OUT std_ulogic; - dout_udb_7 : OUT std_ulogic; - extclk_cp_udb : IN std_ulogic; - clk_udb : IN std_ulogic); - END COMPONENT; - COMPONENT emifcell - PORT ( - EM_clock : OUT std_ulogic; - EM_CEn : OUT std_ulogic; - EM_OEn : OUT std_ulogic; - EM_ADSCn : OUT std_ulogic; - EM_sleep : OUT std_ulogic; - EM_WRn : OUT std_ulogic; - dataport_OE : OUT std_ulogic; - dataport_OEn : OUT std_ulogic; - wr : OUT std_ulogic; - rd : OUT std_ulogic; - udb_stall : IN std_ulogic; - udb_ready : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT i2ccell - PORT ( - clock : IN std_ulogic; - scl_in : IN std_ulogic; - sda_in : IN std_ulogic; - scl_out : OUT std_ulogic; - sda_out : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT interrupt - PORT ( - interrupt : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT iocell - PORT ( - pin_input : IN std_ulogic; - oe : IN std_ulogic; - fb : OUT std_ulogic; - pad_in : IN std_ulogic; - pa_out : OUT std_ulogic; - pad_out : OUT std_ulogic; - oe_reg : OUT std_ulogic; - oe_internal : IN std_ulogic; - in_clock : IN std_ulogic; - in_clock_en : IN std_ulogic; - in_reset : IN std_ulogic; - out_clock : IN std_ulogic; - out_clock_en : IN std_ulogic; - out_reset : IN std_ulogic); - END COMPONENT; - COMPONENT lcdctrlcell - PORT ( - drive_en : IN std_ulogic; - frame : IN std_ulogic; - data_clk : IN std_ulogic; - en_hi : IN std_ulogic; - dac_dis : IN std_ulogic; - chop_clk : IN std_ulogic; - int_clr : IN std_ulogic; - lp_ack_udb : IN std_ulogic; - mode_1 : IN std_ulogic; - mode_2 : IN std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT logicalport - PORT ( - interrupt : OUT std_ulogic; - precharge : IN std_ulogic; - in_clock : IN std_ulogic; - in_clock_en : IN std_ulogic; - in_reset : IN std_ulogic; - out_clock : IN std_ulogic; - out_clock_en : IN std_ulogic; - out_reset : IN std_ulogic); - END COMPONENT; - COMPONENT lpfcell - END COMPONENT; - COMPONENT lvdcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8clockblockcell - PORT ( - imo : OUT std_ulogic; - ext : OUT std_ulogic; - eco : OUT std_ulogic; - ilo : OUT std_ulogic; - wco : OUT std_ulogic; - dbl : OUT std_ulogic; - pll : OUT std_ulogic; - dpll : OUT std_ulogic; - dsi_out_0 : OUT std_ulogic; - dsi_out_1 : OUT std_ulogic; - dsi_out_2 : OUT std_ulogic; - dsi_out_3 : OUT std_ulogic; - lfclk : OUT std_ulogic; - hfclk : OUT std_ulogic; - sysclk : OUT std_ulogic; - halfsysclk : OUT std_ulogic; - udb_div_0 : OUT std_ulogic; - udb_div_1 : OUT std_ulogic; - udb_div_2 : OUT std_ulogic; - udb_div_3 : OUT std_ulogic; - udb_div_4 : OUT std_ulogic; - udb_div_5 : OUT std_ulogic; - udb_div_6 : OUT std_ulogic; - udb_div_7 : OUT std_ulogic; - udb_div_8 : OUT std_ulogic; - udb_div_9 : OUT std_ulogic; - udb_div_10 : OUT std_ulogic; - udb_div_11 : OUT std_ulogic; - udb_div_12 : OUT std_ulogic; - udb_div_13 : OUT std_ulogic; - udb_div_14 : OUT std_ulogic; - udb_div_15 : OUT std_ulogic; - uab_div_0 : OUT std_ulogic; - uab_div_1 : OUT std_ulogic; - uab_div_2 : OUT std_ulogic; - uab_div_3 : OUT std_ulogic; - ff_div_0 : OUT std_ulogic; - ff_div_1 : OUT std_ulogic; - ff_div_2 : OUT std_ulogic; - ff_div_3 : OUT std_ulogic; - ff_div_4 : OUT std_ulogic; - ff_div_5 : OUT std_ulogic; - ff_div_6 : OUT std_ulogic; - ff_div_7 : OUT std_ulogic; - ff_div_8 : OUT std_ulogic; - ff_div_9 : OUT std_ulogic; - ff_div_10 : OUT std_ulogic; - ff_div_11 : OUT std_ulogic; - ff_div_12 : OUT std_ulogic; - ff_div_13 : OUT std_ulogic; - ff_div_14 : OUT std_ulogic; - ff_div_15 : OUT std_ulogic; - dsi_in_0 : IN std_ulogic; - dsi_in_1 : IN std_ulogic; - dsi_in_2 : IN std_ulogic; - dsi_in_3 : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8clockgenblockcell - PORT ( - gen_clk_in_0 : IN std_ulogic; - gen_clk_in_1 : IN std_ulogic; - gen_clk_in_2 : IN std_ulogic; - gen_clk_in_3 : IN std_ulogic; - gen_clk_in_4 : IN std_ulogic; - gen_clk_in_5 : IN std_ulogic; - gen_clk_in_6 : IN std_ulogic; - gen_clk_in_7 : IN std_ulogic; - gen_clk_out_0 : OUT std_ulogic; - gen_clk_out_1 : OUT std_ulogic; - gen_clk_out_2 : OUT std_ulogic; - gen_clk_out_3 : OUT std_ulogic; - gen_clk_out_4 : OUT std_ulogic; - gen_clk_out_5 : OUT std_ulogic; - gen_clk_out_6 : OUT std_ulogic; - gen_clk_out_7 : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8lcdcell - PORT ( - common_0 : OUT std_ulogic; - common_1 : OUT std_ulogic; - common_2 : OUT std_ulogic; - common_3 : OUT std_ulogic; - common_4 : OUT std_ulogic; - common_5 : OUT std_ulogic; - common_6 : OUT std_ulogic; - common_7 : OUT std_ulogic; - common_8 : OUT std_ulogic; - common_9 : OUT std_ulogic; - common_10 : OUT std_ulogic; - common_11 : OUT std_ulogic; - common_12 : OUT std_ulogic; - common_13 : OUT std_ulogic; - common_14 : OUT std_ulogic; - common_15 : OUT std_ulogic; - segment_0 : OUT std_ulogic; - segment_1 : OUT std_ulogic; - segment_2 : OUT std_ulogic; - segment_3 : OUT std_ulogic; - segment_4 : OUT std_ulogic; - segment_5 : OUT std_ulogic; - segment_6 : OUT std_ulogic; - segment_7 : OUT std_ulogic; - segment_8 : OUT std_ulogic; - segment_9 : OUT std_ulogic; - segment_10 : OUT std_ulogic; - segment_11 : OUT std_ulogic; - segment_12 : OUT std_ulogic; - segment_13 : OUT std_ulogic; - segment_14 : OUT std_ulogic; - segment_15 : OUT std_ulogic; - segment_16 : OUT std_ulogic; - segment_17 : OUT std_ulogic; - segment_18 : OUT std_ulogic; - segment_19 : OUT std_ulogic; - segment_20 : OUT std_ulogic; - segment_21 : OUT std_ulogic; - segment_22 : OUT std_ulogic; - segment_23 : OUT std_ulogic; - segment_24 : OUT std_ulogic; - segment_25 : OUT std_ulogic; - segment_26 : OUT std_ulogic; - segment_27 : OUT std_ulogic; - segment_28 : OUT std_ulogic; - segment_29 : OUT std_ulogic; - segment_30 : OUT std_ulogic; - segment_31 : OUT std_ulogic; - segment_32 : OUT std_ulogic; - segment_33 : OUT std_ulogic; - segment_34 : OUT std_ulogic; - segment_35 : OUT std_ulogic; - segment_36 : OUT std_ulogic; - segment_37 : OUT std_ulogic; - segment_38 : OUT std_ulogic; - segment_39 : OUT std_ulogic; - segment_40 : OUT std_ulogic; - segment_41 : OUT std_ulogic; - segment_42 : OUT std_ulogic; - segment_43 : OUT std_ulogic; - segment_44 : OUT std_ulogic; - segment_45 : OUT std_ulogic; - segment_46 : OUT std_ulogic; - segment_47 : OUT std_ulogic; - segment_48 : OUT std_ulogic; - segment_49 : OUT std_ulogic; - segment_50 : OUT std_ulogic; - segment_51 : OUT std_ulogic; - segment_52 : OUT std_ulogic; - segment_53 : OUT std_ulogic; - segment_54 : OUT std_ulogic; - segment_55 : OUT std_ulogic; - segment_56 : OUT std_ulogic; - segment_57 : OUT std_ulogic; - segment_58 : OUT std_ulogic; - segment_59 : OUT std_ulogic; - segment_60 : OUT std_ulogic; - segment_61 : OUT std_ulogic; - segment_62 : OUT std_ulogic; - segment_63 : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8pmcell - PORT ( - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8scbcell - PORT ( - clock : IN std_ulogic; - interrupt : OUT std_ulogic; - rx : IN std_ulogic; - tx : OUT std_ulogic; - mosi_m : OUT std_ulogic; - miso_m : IN std_ulogic; - select_m_0 : OUT std_ulogic; - select_m_1 : OUT std_ulogic; - select_m_2 : OUT std_ulogic; - select_m_3 : OUT std_ulogic; - sclk_m : OUT std_ulogic; - mosi_s : IN std_ulogic; - miso_s : OUT std_ulogic; - select_s : IN std_ulogic; - sclk_s : IN std_ulogic; - scl : INOUT std_ulogic; - sda : INOUT std_ulogic); - END COMPONENT; - COMPONENT m0s8spcifcell - PORT ( - spcif_int : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tcpwmcell - PORT ( - clock : IN std_ulogic; - capture : IN std_ulogic; - count : IN std_ulogic; - reload : IN std_ulogic; - stop : IN std_ulogic; - start : IN std_ulogic; - tr_underflow : OUT std_ulogic; - tr_overflow : OUT std_ulogic; - tr_compare_match : OUT std_ulogic; - line_out : OUT std_ulogic; - line_out_compl : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tsscell - PORT ( - clk_seq : IN std_ulogic; - clk_adc : IN std_ulogic; - ext_reject : IN std_ulogic; - ext_sync : IN std_ulogic; - tx_sync : IN std_ulogic; - reject_in : IN std_ulogic; - start_in : IN std_ulogic; - lx_det_hi : OUT std_ulogic; - lx_det_lo : OUT std_ulogic; - rej_window : OUT std_ulogic; - tx_hilo : OUT std_ulogic; - phase_end : OUT std_ulogic; - phase_num_0 : OUT std_ulogic; - phase_num_1 : OUT std_ulogic; - phase_num_2 : OUT std_ulogic; - phase_num_3 : OUT std_ulogic; - ipq_reject : OUT std_ulogic; - ipq_start : OUT std_ulogic; - epq_reject : OUT std_ulogic; - epq_start : OUT std_ulogic; - mcs_reject : OUT std_ulogic; - mcs_start : OUT std_ulogic; - do_switch : OUT std_ulogic; - adc_start : OUT std_ulogic; - adc_done : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8wdtcell - PORT ( - wdt_int : OUT std_ulogic); - END COMPONENT; - COMPONENT macrocell - PORT ( - main_0 : IN std_ulogic; - main_1 : IN std_ulogic; - main_2 : IN std_ulogic; - main_3 : IN std_ulogic; - main_4 : IN std_ulogic; - main_5 : IN std_ulogic; - main_6 : IN std_ulogic; - main_7 : IN std_ulogic; - main_8 : IN std_ulogic; - main_9 : IN std_ulogic; - main_10 : IN std_ulogic; - main_11 : IN std_ulogic; - ar_0 : IN std_ulogic; - ap_0 : IN std_ulogic; - clock_0 : IN std_ulogic; - clk_en : IN std_ulogic; - cin : IN std_ulogic; - cpt0_0 : IN std_ulogic; - cpt0_1 : IN std_ulogic; - cpt0_2 : IN std_ulogic; - cpt0_3 : IN std_ulogic; - cpt0_4 : IN std_ulogic; - cpt0_5 : IN std_ulogic; - cpt0_6 : IN std_ulogic; - cpt0_7 : IN std_ulogic; - cpt0_8 : IN std_ulogic; - cpt0_9 : IN std_ulogic; - cpt0_10 : IN std_ulogic; - cpt0_11 : IN std_ulogic; - cpt1_0 : IN std_ulogic; - cpt1_1 : IN std_ulogic; - cpt1_2 : IN std_ulogic; - cpt1_3 : IN std_ulogic; - cpt1_4 : IN std_ulogic; - cpt1_5 : IN std_ulogic; - cpt1_6 : IN std_ulogic; - cpt1_7 : IN std_ulogic; - cpt1_8 : IN std_ulogic; - cpt1_9 : IN std_ulogic; - cpt1_10 : IN std_ulogic; - cpt1_11 : IN std_ulogic; - cout : OUT std_ulogic; - q : OUT std_ulogic; - q_fixed : OUT std_ulogic); - END COMPONENT; - COMPONENT p4abufcell - PORT ( - ctb_dsi_comp : OUT std_ulogic; - dsi_out : IN std_ulogic); - END COMPONENT; - COMPONENT p4anapumpcell - PORT ( - pump_clock : IN std_ulogic); - END COMPONENT; - COMPONENT p4csdcell - PORT ( - sense_out : OUT std_ulogic; - sample_out : OUT std_ulogic; - sense_in : IN std_ulogic; - sample_in : IN std_ulogic; - clk1 : IN std_ulogic; - clk2 : IN std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT p4csidac7cell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4csidac8cell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4ctbmblockcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT p4halfuabcell - PORT ( - clock : IN std_ulogic; - comp : OUT std_ulogic; - ctrl : IN std_ulogic); - END COMPONENT; - COMPONENT p4lpcompblockcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT p4lpcompcell - PORT ( - cmpout : OUT std_ulogic); - END COMPONENT; - COMPONENT p4rsbcell - END COMPONENT; - COMPONENT p4sarcell - PORT ( - clock : IN std_ulogic; - sample_done : OUT std_ulogic; - chan_id_valid : OUT std_ulogic; - chan_id_0 : OUT std_ulogic; - chan_id_1 : OUT std_ulogic; - chan_id_2 : OUT std_ulogic; - chan_id_3 : OUT std_ulogic; - data_valid : OUT std_ulogic; - data_0 : OUT std_ulogic; - data_1 : OUT std_ulogic; - data_2 : OUT std_ulogic; - data_3 : OUT std_ulogic; - data_4 : OUT std_ulogic; - data_5 : OUT std_ulogic; - data_6 : OUT std_ulogic; - data_7 : OUT std_ulogic; - data_8 : OUT std_ulogic; - data_9 : OUT std_ulogic; - data_10 : OUT std_ulogic; - data_11 : OUT std_ulogic; - eos_intr : OUT std_ulogic; - irq : OUT std_ulogic; - sw_negvref : IN std_ulogic; - cfg_st_sel_0 : IN std_ulogic; - cfg_st_sel_1 : IN std_ulogic; - cfg_average : IN std_ulogic; - cfg_resolution : IN std_ulogic; - cfg_differential : IN std_ulogic; - trigger : IN std_ulogic; - data_hilo_sel : IN std_ulogic; - swctrl0 : IN std_ulogic; - swctrl1 : IN std_ulogic); - END COMPONENT; - COMPONENT p4sarmuxcell - END COMPONENT; - COMPONENT p4tempcell - END COMPONENT; - COMPONENT p4vrefcell - END COMPONENT; - COMPONENT pmcell - PORT ( - ctw_int : OUT std_ulogic; - ftw_int : OUT std_ulogic; - limact_int : OUT std_ulogic; - onepps_int : OUT std_ulogic; - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - clk_udb : IN std_ulogic; - sof_udb : IN std_ulogic; - vp_ctl_udb_0 : IN std_ulogic; - vp_ctl_udb_1 : IN std_ulogic; - vp_ctl_udb_2 : IN std_ulogic; - vp_ctl_udb_3 : IN std_ulogic; - vn_ctl_udb_0 : IN std_ulogic; - vn_ctl_udb_1 : IN std_ulogic; - vn_ctl_udb_2 : IN std_ulogic; - vn_ctl_udb_3 : IN std_ulogic; - data_out_udb_0 : OUT std_ulogic; - data_out_udb_1 : OUT std_ulogic; - data_out_udb_2 : OUT std_ulogic; - data_out_udb_3 : OUT std_ulogic; - data_out_udb_4 : OUT std_ulogic; - data_out_udb_5 : OUT std_ulogic; - data_out_udb_6 : OUT std_ulogic; - data_out_udb_7 : OUT std_ulogic; - data_out_udb_8 : OUT std_ulogic; - data_out_udb_9 : OUT std_ulogic; - data_out_udb_10 : OUT std_ulogic; - data_out_udb_11 : OUT std_ulogic; - eof_udb : OUT std_ulogic; - irq : OUT std_ulogic; - next : OUT std_ulogic); - END COMPONENT; - COMPONENT sccell - PORT ( - aclk : IN std_ulogic; - bst_clk : IN std_ulogic; - clk_udb : IN std_ulogic; - modout : OUT std_ulogic; - dyn_cntl_udb : IN std_ulogic); - END COMPONENT; - COMPONENT spccell - PORT ( - data_ready : OUT std_ulogic; - eeprom_fault_int : OUT std_ulogic; - idle : OUT std_ulogic); - END COMPONENT; - COMPONENT ssccell - PORT ( - rst_n : IN std_ulogic; - scli : IN std_ulogic; - sdai : IN std_ulogic; - csel : IN std_ulogic; - sclo : OUT std_ulogic; - sdao : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT statuscell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - status_7 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT statusicell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - interrupt : OUT std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT synccell - PORT ( - in : IN std_ulogic; - clock : IN std_ulogic; - out : OUT std_ulogic; - clk_en : IN std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT tfaultcell - PORT ( - tfault_dsi : OUT std_ulogic); - END COMPONENT; - COMPONENT timercell - PORT ( - clock : IN std_ulogic; - kill : IN std_ulogic; - enable : IN std_ulogic; - capture : IN std_ulogic; - timer_reset : IN std_ulogic; - tc : OUT std_ulogic; - cmp : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT udbclockencell - PORT ( - clock_in : IN std_ulogic; - enable : IN std_ulogic; - clock_out : OUT std_ulogic); - END COMPONENT; - COMPONENT usbcell - PORT ( - sof_int : OUT std_ulogic; - arb_int : OUT std_ulogic; - usb_int : OUT std_ulogic; - ord_int : OUT std_ulogic; - ept_int_0 : OUT std_ulogic; - ept_int_1 : OUT std_ulogic; - ept_int_2 : OUT std_ulogic; - ept_int_3 : OUT std_ulogic; - ept_int_4 : OUT std_ulogic; - ept_int_5 : OUT std_ulogic; - ept_int_6 : OUT std_ulogic; - ept_int_7 : OUT std_ulogic; - ept_int_8 : OUT std_ulogic; - dma_req_0 : OUT std_ulogic; - dma_req_1 : OUT std_ulogic; - dma_req_2 : OUT std_ulogic; - dma_req_3 : OUT std_ulogic; - dma_req_4 : OUT std_ulogic; - dma_req_5 : OUT std_ulogic; - dma_req_6 : OUT std_ulogic; - dma_req_7 : OUT std_ulogic; - dma_termin : OUT std_ulogic); - END COMPONENT; - COMPONENT vidaccell - PORT ( - data_0 : IN std_ulogic; - data_1 : IN std_ulogic; - data_2 : IN std_ulogic; - data_3 : IN std_ulogic; - data_4 : IN std_ulogic; - data_5 : IN std_ulogic; - data_6 : IN std_ulogic; - data_7 : IN std_ulogic; - strobe : IN std_ulogic; - strobe_udb : IN std_ulogic; - reset : IN std_ulogic; - idir : IN std_ulogic; - ioff : IN std_ulogic); - END COMPONENT; -BEGIN - - ClockBlock:clockblockcell - PORT MAP( - clk_bus_glb => ClockBlock_BUS_CLK, - clk_bus => ClockBlock_BUS_CLK_local, - clk_sync => ClockBlock_MASTER_CLK, - clk_32k_xtal => ClockBlock_XTAL_32KHZ, - xtal => ClockBlock_XTAL, - ilo => ClockBlock_ILO, - clk_100k => ClockBlock_100k, - clk_1k => ClockBlock_1k, - clk_32k => ClockBlock_32k, - pllout => ClockBlock_PLL_OUT, - imo => ClockBlock_IMO, - dsi_clkin_div => open, - dsi_glb_div => open); - - SCSI_Out:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110110110110", - ibuf_enabled => "1111111111", - id => "11f071e8-9c92-47e0-872a-3f48765a75b8", - init_dr_st => "0000000000", - input_clk_en => 0, - input_sync => "1111111111", - input_sync_mode => "0000000000", - intr_mode => "00000000000000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "5, 5, 5, 5, 5, 5, 5, 5, 5, 5", - layout_mode => "NONCONTIGUOUS", - oe_conn => "0000000000", - oe_reset => 0, - oe_sync => "0000000000", - output_clk_en => 0, - output_clock_mode => "0000000000", - output_conn => "0000000000", - output_mode => "0000000000", - output_reset => 0, - output_sync => "0000000000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "DBP_raw,ATN,BSY,ACK,RST,MSG,SEL,CD,REQ,IO_raw", - pin_mode => "OOOOOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0000000000", - sio_ibuf => "00000000", - sio_info => "00000000000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0000000000", - spanning => 1, - sw_only => 0, - use_annotation => "1111111111", - vtrip => "10101010101010101010", - width => 10, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - SCSI_Out(0):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(0)__PA, - oe => open, - pad_in => SCSI_Out(0)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(1):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(1)__PA, - oe => open, - pad_in => SCSI_Out(1)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(2):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(2)__PA, - oe => open, - pad_in => SCSI_Out(2)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(3):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(3)__PA, - oe => open, - pad_in => SCSI_Out(3)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(4):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(4)__PA, - oe => open, - pad_in => SCSI_Out(4)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(5):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(5)__PA, - oe => open, - pad_in => SCSI_Out(5)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(6):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(6)__PA, - oe => open, - pad_in => SCSI_Out(6)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(7):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 7, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(7)__PA, - oe => open, - pad_in => SCSI_Out(7)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(8):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 8, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(8)__PA, - oe => open, - pad_in => SCSI_Out(8)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(9):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 9, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(9)__PA, - oe => open, - pad_in => SCSI_Out(9)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110110", - ibuf_enabled => "11111111", - id => "52f31aa9-2f0a-497d-9a1f-1424095e13e6", - init_dr_st => "00000000", - input_clk_en => 0, - input_sync => "11111111", - input_sync_mode => "00000000", - intr_mode => "0000000000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => ", , , , , , , 5", - layout_mode => "NONCONTIGUOUS", - oe_conn => "00000000", - oe_reset => 0, - oe_sync => "00000000", - output_clk_en => 0, - output_clock_mode => "00000000", - output_conn => "00000000", - output_mode => "00000000", - output_reset => 0, - output_sync => "00000000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "DB0,DB1,DB2,DB3,DB4,DB5,DB6,DB7", - pin_mode => "OOOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "00000000", - sio_ibuf => "00000000", - sio_info => "0000000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "00000000", - spanning => 1, - sw_only => 0, - use_annotation => "11111111", - vtrip => "1010101010101010", - width => 8, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - SCSI_Out_DBx(0):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(0)__PA, - oe => open, - pad_in => SCSI_Out_DBx(0)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(1):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(1)__PA, - oe => open, - pad_in => SCSI_Out_DBx(1)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(2):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(2)__PA, - oe => open, - pad_in => SCSI_Out_DBx(2)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(3):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(3)__PA, - oe => open, - pad_in => SCSI_Out_DBx(3)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(4):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(4)__PA, - oe => open, - pad_in => SCSI_Out_DBx(4)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(5):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(5)__PA, - oe => open, - pad_in => SCSI_Out_DBx(5)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(6):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(6)__PA, - oe => open, - pad_in => SCSI_Out_DBx(6)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(7):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 7, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(7)__PA, - oe => open, - pad_in => SCSI_Out_DBx(7)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP:logicalport - GENERIC MAP( - drive_mode => "010010010010010", - ibuf_enabled => "11111", - id => "4c15b41e-e284-4978-99e7-5aaee19bd0ce", - init_dr_st => "11111", - input_clk_en => 0, - input_sync => "11111", - input_sync_mode => "00000", - intr_mode => "0000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "3.3, , , , ", - layout_mode => "CONTIGUOUS", - oe_conn => "00000", - oe_reset => 0, - oe_sync => "00000", - output_clk_en => 0, - output_clock_mode => "00000", - output_conn => "00000", - output_mode => "00000", - output_reset => 0, - output_sync => "00000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => ",,,,", - pin_mode => "IIIII", - por_state => 2, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "00000", - sio_ibuf => "00000000", - sio_info => "0000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "00000", - spanning => 0, - sw_only => 0, - use_annotation => "00000", - vtrip => "0000000000", - width => 5, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open, - in_clock => open); - - SD_PULLUP(0):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(0)__PA, - oe => open, - pad_in => SD_PULLUP(0)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(1):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(1)__PA, - oe => open, - pad_in => SD_PULLUP(1)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(2):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(2)__PA, - oe => open, - pad_in => SD_PULLUP(2)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(3):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(3)__PA, - oe => open, - pad_in => SD_PULLUP(3)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(4):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(4)__PA, - oe => open, - pad_in => SD_PULLUP(4)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dm(0)\:iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "\USBFS:Dm\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000010000000000000000") - PORT MAP( - pa_out => \\\USBFS:Dm(0)\\__PA\, - oe => open, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dm\:logicalport - GENERIC MAP( - drive_mode => "000", - ibuf_enabled => "0", - id => "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/8b77a6c4-10a0-4390-971c-672353e2a49c", - init_dr_st => "0", - input_clk_en => 0, - input_sync => "1", - input_sync_mode => "0", - intr_mode => "00", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "", - layout_mode => "NONCONTIGUOUS", - oe_conn => "0", - oe_reset => 0, - oe_sync => "0", - output_clk_en => 0, - output_clock_mode => "0", - output_conn => "0", - output_mode => "0", - output_reset => 0, - output_sync => "0", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "", - pin_mode => "A", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 1, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - \USBFS:Dp(0)\:iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "\USBFS:Dp\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000001000000000000000") - PORT MAP( - pa_out => \\\USBFS:Dp(0)\\__PA\, - oe => open, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dp\:logicalport - GENERIC MAP( - drive_mode => "000", - ibuf_enabled => "0", - id => "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42", - init_dr_st => "0", - input_clk_en => 0, - input_sync => "1", - input_sync_mode => "0", - intr_mode => "10", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - oe_reset => 0, - oe_sync => "0", - output_clk_en => 0, - output_clock_mode => "0", - output_conn => "0", - output_mode => "0", - output_reset => 0, - output_sync => "0", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "", - pin_mode => "I", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "00", - width => 1, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open, - interrupt => \USBFS:Net_1010\, - in_clock => open); - - \USBFS:USB\:usbcell - GENERIC MAP( - cy_registers => "") - PORT MAP( - sof_int => Net_40, - arb_int => \USBFS:Net_79\, - usb_int => \USBFS:Net_81\, - ept_int_8 => \USBFS:ept_int_8\, - ept_int_7 => \USBFS:ept_int_7\, - ept_int_6 => \USBFS:ept_int_6\, - ept_int_5 => \USBFS:ept_int_5\, - ept_int_4 => \USBFS:ept_int_4\, - ept_int_3 => \USBFS:ept_int_3\, - ept_int_2 => \USBFS:ept_int_2\, - ept_int_1 => \USBFS:ept_int_1\, - ept_int_0 => \USBFS:ept_int_0\, - ord_int => \USBFS:Net_95\, - dma_req_7 => \USBFS:dma_req_7\, - dma_req_6 => \USBFS:dma_req_6\, - dma_req_5 => \USBFS:dma_req_5\, - dma_req_4 => \USBFS:dma_req_4\, - dma_req_3 => \USBFS:dma_req_3\, - dma_req_2 => \USBFS:dma_req_2\, - dma_req_1 => \USBFS:dma_req_1\, - dma_req_0 => \USBFS:dma_req_0\, - dma_termin => \USBFS:Net_824\); - - \USBFS:arb_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_79\, - clock => ClockBlock_BUS_CLK); - - \USBFS:bus_reset\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_81\, - clock => ClockBlock_BUS_CLK); - - \USBFS:dp_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_1010\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_0\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_0\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_1\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_1\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_2\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_2\, - clock => ClockBlock_BUS_CLK); - - \USBFS:sof_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => Net_40, - clock => ClockBlock_BUS_CLK); - -END __DEFAULT__; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib deleted file mode 100755 index b4f81be..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.lib +++ /dev/null @@ -1,1699 +0,0 @@ -library (timing) { - timescale : 1ns; - capacitive_load_unit (1,ff); - include_file(device.lib); - cell (iocell1) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.445; - intrinsic_fall : 16.445; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.445; - intrinsic_fall : 16.445; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.093; - intrinsic_fall : 15.093; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.033; - intrinsic_fall : 7.033; - } - } - } - cell (iocell2) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.297; - intrinsic_fall : 17.297; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.297; - intrinsic_fall : 17.297; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.111; - intrinsic_fall : 15.111; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.255; - intrinsic_fall : 7.255; - } - } - } - cell (iocell3) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.269; - intrinsic_fall : 17.269; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.269; - intrinsic_fall : 17.269; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.495; - intrinsic_fall : 15.495; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.644; - intrinsic_fall : 7.644; - } - } - } - cell (iocell4) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.371; - intrinsic_fall : 17.371; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.371; - intrinsic_fall : 17.371; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.561; - intrinsic_fall : 15.561; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.354; - intrinsic_fall : 7.354; - } - } - } - cell (iocell5) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.182; - intrinsic_fall : 17.182; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.023; - intrinsic_fall : 15.023; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 8.264; - intrinsic_fall : 8.264; - } - } - } - cell (iocell6) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.718; - intrinsic_fall : 17.718; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.718; - intrinsic_fall : 17.718; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.880; - intrinsic_fall : 14.880; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.563; - intrinsic_fall : 7.563; - } - } - } - cell (iocell7) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.610; - intrinsic_fall : 17.610; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.610; - intrinsic_fall : 17.610; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.744; - intrinsic_fall : 15.744; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.958; - intrinsic_fall : 7.958; - } - } - } - cell (iocell8) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.428; - intrinsic_fall : 17.428; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.428; - intrinsic_fall : 17.428; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.459; - intrinsic_fall : 15.459; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.950; - intrinsic_fall : 7.950; - } - } - } - cell (iocell9) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.434; - intrinsic_fall : 17.434; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.434; - intrinsic_fall : 17.434; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.802; - intrinsic_fall : 15.802; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.962; - intrinsic_fall : 7.962; - } - } - } - cell (iocell10) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.161; - intrinsic_fall : 17.161; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.161; - intrinsic_fall : 17.161; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.251; - intrinsic_fall : 15.251; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.922; - intrinsic_fall : 7.922; - } - } - } - cell (iocell11) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.840; - intrinsic_fall : 17.840; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.840; - intrinsic_fall : 17.840; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.011; - intrinsic_fall : 15.011; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.576; - intrinsic_fall : 7.576; - } - } - } - cell (iocell12) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.165; - intrinsic_fall : 17.165; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.165; - intrinsic_fall : 17.165; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.746; - intrinsic_fall : 15.746; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.331; - intrinsic_fall : 7.331; - } - } - } - cell (iocell13) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.973; - intrinsic_fall : 16.973; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.973; - intrinsic_fall : 16.973; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.880; - intrinsic_fall : 14.880; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.065; - intrinsic_fall : 7.065; - } - } - } - cell (iocell14) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.979; - intrinsic_fall : 16.979; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.979; - intrinsic_fall : 16.979; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.914; - intrinsic_fall : 14.914; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.816; - intrinsic_fall : 7.816; - } - } - } - cell (iocell15) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.374; - intrinsic_fall : 17.374; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.374; - intrinsic_fall : 17.374; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.222; - intrinsic_fall : 15.222; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.459; - intrinsic_fall : 7.459; - } - } - } - cell (iocell16) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.157; - intrinsic_fall : 17.157; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.157; - intrinsic_fall : 17.157; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.976; - intrinsic_fall : 15.976; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.582; - intrinsic_fall : 7.582; - } - } - } - cell (iocell17) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.578; - intrinsic_fall : 16.578; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.578; - intrinsic_fall : 16.578; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.347; - intrinsic_fall : 15.347; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 7.368; - intrinsic_fall : 7.368; - } - } - } - cell (iocell18) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.786; - intrinsic_fall : 17.786; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.786; - intrinsic_fall : 17.786; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 16.004; - intrinsic_fall : 16.004; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 6.974; - intrinsic_fall : 6.974; - } - } - } - cell (iocell19) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.419; - intrinsic_fall : 16.419; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.419; - intrinsic_fall : 16.419; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.979; - intrinsic_fall : 14.979; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 1.661; - intrinsic_fall : 1.661; - } - } - } - cell (iocell20) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.643; - intrinsic_fall : 17.643; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.643; - intrinsic_fall : 17.643; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.995; - intrinsic_fall : 14.995; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 1.852; - intrinsic_fall : 1.852; - } - } - } - cell (iocell21) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.081; - intrinsic_fall : 17.081; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.081; - intrinsic_fall : 17.081; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.591; - intrinsic_fall : 14.591; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 3.163; - intrinsic_fall : 3.163; - } - } - } - cell (iocell22) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 16.646; - intrinsic_fall : 16.646; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 16.646; - intrinsic_fall : 16.646; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 14.987; - intrinsic_fall : 14.987; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.191; - intrinsic_fall : 2.191; - } - } - } - cell (iocell23) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 17.787; - intrinsic_fall : 17.787; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 17.787; - intrinsic_fall : 17.787; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 15.338; - intrinsic_fall : 15.338; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.064; - intrinsic_fall : 2.064; - } - } - } - cell (iocell24) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.053; - intrinsic_fall : 19.053; - } - } - pin (fb) { - direction : output; - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pad_in"; - intrinsic_rise : 9.497; - intrinsic_fall : 9.497; - } - } - } - cell (iocell25) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : output; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing () { - timing_sense : negative_unate; - timing_type : three_state_disable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : three_state_enable; - related_pin : "oe"; - intrinsic_rise : 52.000; - intrinsic_fall : 52.000; - } - timing () { - timing_sense : positive_unate; - timing_type : combinational; - related_pin : "pin_input"; - intrinsic_rise : 19.129; - intrinsic_fall : 19.129; - } - } - pin (fb) { - direction : output; - timing () { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 2.717; - intrinsic_fall : 2.717; - } - } - } -} diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2 b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2 deleted file mode 100755 index fa0079f..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_t.vh2 +++ /dev/null @@ -1,1972 +0,0 @@ --- Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj --- Generated: 03/22/2014 22:32:56 --- - -ENTITY USB_Bootloader IS - PORT( - SCSI_Out(0)_PAD : OUT std_ulogic; - SCSI_Out(1)_PAD : OUT std_ulogic; - SCSI_Out(2)_PAD : OUT std_ulogic; - SCSI_Out(3)_PAD : OUT std_ulogic; - SCSI_Out(4)_PAD : OUT std_ulogic; - SCSI_Out(5)_PAD : OUT std_ulogic; - SCSI_Out(6)_PAD : OUT std_ulogic; - SCSI_Out(7)_PAD : OUT std_ulogic; - SCSI_Out(8)_PAD : OUT std_ulogic; - SCSI_Out(9)_PAD : OUT std_ulogic; - SCSI_Out_DBx(0)_PAD : OUT std_ulogic; - SCSI_Out_DBx(1)_PAD : OUT std_ulogic; - SCSI_Out_DBx(2)_PAD : OUT std_ulogic; - SCSI_Out_DBx(3)_PAD : OUT std_ulogic; - SCSI_Out_DBx(4)_PAD : OUT std_ulogic; - SCSI_Out_DBx(5)_PAD : OUT std_ulogic; - SCSI_Out_DBx(6)_PAD : OUT std_ulogic; - SCSI_Out_DBx(7)_PAD : OUT std_ulogic; - SD_PULLUP(0)_PAD : IN std_ulogic; - SD_PULLUP(1)_PAD : IN std_ulogic; - SD_PULLUP(2)_PAD : IN std_ulogic; - SD_PULLUP(3)_PAD : IN std_ulogic; - SD_PULLUP(4)_PAD : IN std_ulogic); - ATTRIBUTE voltage_Vio1 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vusb OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vddd OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio3 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vdda OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio0 OF __DEFAULT__ : ENTITY IS 5e0; - ATTRIBUTE voltage_Vio2 OF __DEFAULT__ : ENTITY IS 5e0; -END USB_Bootloader; - -ARCHITECTURE __DEFAULT__ OF USB_Bootloader IS - SIGNAL ClockBlock_100k : bit; - SIGNAL ClockBlock_1k : bit; - SIGNAL ClockBlock_32k : bit; - SIGNAL ClockBlock_BUS_CLK : bit; - ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true; - SIGNAL ClockBlock_BUS_CLK_local : bit; - SIGNAL ClockBlock_ILO : bit; - SIGNAL ClockBlock_IMO : bit; - SIGNAL ClockBlock_MASTER_CLK : bit; - SIGNAL ClockBlock_PLL_OUT : bit; - SIGNAL ClockBlock_XTAL : bit; - SIGNAL ClockBlock_XTAL_32KHZ : bit; - SIGNAL Net_40 : bit; - SIGNAL SCSI_Out(0)__PA : bit; - SIGNAL SCSI_Out(1)__PA : bit; - SIGNAL SCSI_Out(2)__PA : bit; - SIGNAL SCSI_Out(3)__PA : bit; - SIGNAL SCSI_Out(4)__PA : bit; - SIGNAL SCSI_Out(5)__PA : bit; - SIGNAL SCSI_Out(6)__PA : bit; - SIGNAL SCSI_Out(7)__PA : bit; - SIGNAL SCSI_Out(8)__PA : bit; - SIGNAL SCSI_Out(9)__PA : bit; - SIGNAL SCSI_Out_DBx(0)__PA : bit; - SIGNAL SCSI_Out_DBx(1)__PA : bit; - SIGNAL SCSI_Out_DBx(2)__PA : bit; - SIGNAL SCSI_Out_DBx(3)__PA : bit; - SIGNAL SCSI_Out_DBx(4)__PA : bit; - SIGNAL SCSI_Out_DBx(5)__PA : bit; - SIGNAL SCSI_Out_DBx(6)__PA : bit; - SIGNAL SCSI_Out_DBx(7)__PA : bit; - SIGNAL SD_PULLUP(0)__PA : bit; - SIGNAL SD_PULLUP(1)__PA : bit; - SIGNAL SD_PULLUP(2)__PA : bit; - SIGNAL SD_PULLUP(3)__PA : bit; - SIGNAL SD_PULLUP(4)__PA : bit; - SIGNAL \\\USBFS:Dm(0)\\__PA\ : bit; - SIGNAL \\\USBFS:Dp(0)\\__PA\ : bit; - SIGNAL \USBFS:Net_1010\ : bit; - SIGNAL \USBFS:Net_79\ : bit; - SIGNAL \USBFS:Net_81\ : bit; - SIGNAL \USBFS:Net_824\ : bit; - SIGNAL \USBFS:Net_95\ : bit; - SIGNAL \USBFS:dma_req_0\ : bit; - SIGNAL \USBFS:dma_req_1\ : bit; - SIGNAL \USBFS:dma_req_2\ : bit; - SIGNAL \USBFS:dma_req_3\ : bit; - SIGNAL \USBFS:dma_req_4\ : bit; - SIGNAL \USBFS:dma_req_5\ : bit; - SIGNAL \USBFS:dma_req_6\ : bit; - SIGNAL \USBFS:dma_req_7\ : bit; - SIGNAL \USBFS:ept_int_0\ : bit; - SIGNAL \USBFS:ept_int_1\ : bit; - SIGNAL \USBFS:ept_int_2\ : bit; - SIGNAL \USBFS:ept_int_3\ : bit; - SIGNAL \USBFS:ept_int_4\ : bit; - SIGNAL \USBFS:ept_int_5\ : bit; - SIGNAL \USBFS:ept_int_6\ : bit; - SIGNAL \USBFS:ept_int_7\ : bit; - SIGNAL \USBFS:ept_int_8\ : bit; - SIGNAL __ONE__ : bit; - ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true; - SIGNAL __ZERO__ : bit; - ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true; - SIGNAL one : bit; - ATTRIBUTE POWER OF one : SIGNAL IS true; - SIGNAL zero : bit; - ATTRIBUTE GROUND OF zero : SIGNAL IS true; - ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)"; - ATTRIBUTE lib_model OF SCSI_Out(0) : LABEL IS "iocell1"; - ATTRIBUTE Location OF SCSI_Out(0) : LABEL IS "P4[3]"; - ATTRIBUTE lib_model OF SCSI_Out(1) : LABEL IS "iocell2"; - ATTRIBUTE Location OF SCSI_Out(1) : LABEL IS "P4[2]"; - ATTRIBUTE lib_model OF SCSI_Out(2) : LABEL IS "iocell3"; - ATTRIBUTE Location OF SCSI_Out(2) : LABEL IS "P0[7]"; - ATTRIBUTE lib_model OF SCSI_Out(3) : LABEL IS "iocell4"; - ATTRIBUTE Location OF SCSI_Out(3) : LABEL IS "P0[6]"; - ATTRIBUTE lib_model OF SCSI_Out(4) : LABEL IS "iocell5"; - ATTRIBUTE Location OF SCSI_Out(4) : LABEL IS "P0[5]"; - ATTRIBUTE lib_model OF SCSI_Out(5) : LABEL IS "iocell6"; - ATTRIBUTE Location OF SCSI_Out(5) : LABEL IS "P0[4]"; - ATTRIBUTE lib_model OF SCSI_Out(6) : LABEL IS "iocell7"; - ATTRIBUTE Location OF SCSI_Out(6) : LABEL IS "P0[3]"; - ATTRIBUTE lib_model OF SCSI_Out(7) : LABEL IS "iocell8"; - ATTRIBUTE Location OF SCSI_Out(7) : LABEL IS "P0[2]"; - ATTRIBUTE lib_model OF SCSI_Out(8) : LABEL IS "iocell9"; - ATTRIBUTE Location OF SCSI_Out(8) : LABEL IS "P0[1]"; - ATTRIBUTE lib_model OF SCSI_Out(9) : LABEL IS "iocell10"; - ATTRIBUTE Location OF SCSI_Out(9) : LABEL IS "P0[0]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(0) : LABEL IS "iocell11"; - ATTRIBUTE Location OF SCSI_Out_DBx(0) : LABEL IS "P6[3]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(1) : LABEL IS "iocell12"; - ATTRIBUTE Location OF SCSI_Out_DBx(1) : LABEL IS "P6[2]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(2) : LABEL IS "iocell13"; - ATTRIBUTE Location OF SCSI_Out_DBx(2) : LABEL IS "P6[1]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(3) : LABEL IS "iocell14"; - ATTRIBUTE Location OF SCSI_Out_DBx(3) : LABEL IS "P6[0]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(4) : LABEL IS "iocell15"; - ATTRIBUTE Location OF SCSI_Out_DBx(4) : LABEL IS "P4[7]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(5) : LABEL IS "iocell16"; - ATTRIBUTE Location OF SCSI_Out_DBx(5) : LABEL IS "P4[6]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(6) : LABEL IS "iocell17"; - ATTRIBUTE Location OF SCSI_Out_DBx(6) : LABEL IS "P4[5]"; - ATTRIBUTE lib_model OF SCSI_Out_DBx(7) : LABEL IS "iocell18"; - ATTRIBUTE Location OF SCSI_Out_DBx(7) : LABEL IS "P4[4]"; - ATTRIBUTE lib_model OF SD_PULLUP(0) : LABEL IS "iocell19"; - ATTRIBUTE Location OF SD_PULLUP(0) : LABEL IS "P3[1]"; - ATTRIBUTE lib_model OF SD_PULLUP(1) : LABEL IS "iocell20"; - ATTRIBUTE Location OF SD_PULLUP(1) : LABEL IS "P3[2]"; - ATTRIBUTE lib_model OF SD_PULLUP(2) : LABEL IS "iocell21"; - ATTRIBUTE Location OF SD_PULLUP(2) : LABEL IS "P3[3]"; - ATTRIBUTE lib_model OF SD_PULLUP(3) : LABEL IS "iocell22"; - ATTRIBUTE Location OF SD_PULLUP(3) : LABEL IS "P3[4]"; - ATTRIBUTE lib_model OF SD_PULLUP(4) : LABEL IS "iocell23"; - ATTRIBUTE Location OF SD_PULLUP(4) : LABEL IS "P3[5]"; - ATTRIBUTE lib_model OF \USBFS:Dm(0)\ : LABEL IS "iocell24"; - ATTRIBUTE Location OF \USBFS:Dm(0)\ : LABEL IS "P15[7]"; - ATTRIBUTE lib_model OF \USBFS:Dp(0)\ : LABEL IS "iocell25"; - ATTRIBUTE Location OF \USBFS:Dp(0)\ : LABEL IS "P15[6]"; - ATTRIBUTE Location OF \USBFS:Dp\ : LABEL IS "F(PICU,8)"; - ATTRIBUTE Location OF \USBFS:USB\ : LABEL IS "F(USB,0)"; - ATTRIBUTE Location OF \USBFS:arb_int\ : LABEL IS "[IntrHod=(0)][IntrId=(22)]"; - ATTRIBUTE Location OF \USBFS:bus_reset\ : LABEL IS "[IntrHod=(0)][IntrId=(23)]"; - ATTRIBUTE Location OF \USBFS:dp_int\ : LABEL IS "[IntrHod=(0)][IntrId=(12)]"; - ATTRIBUTE Location OF \USBFS:ep_0\ : LABEL IS "[IntrHod=(0)][IntrId=(24)]"; - ATTRIBUTE Location OF \USBFS:ep_1\ : LABEL IS "[IntrHod=(0)][IntrId=(0)]"; - ATTRIBUTE Location OF \USBFS:ep_2\ : LABEL IS "[IntrHod=(0)][IntrId=(1)]"; - ATTRIBUTE Location OF \USBFS:sof_int\ : LABEL IS "[IntrHod=(0)][IntrId=(21)]"; - COMPONENT abufcell - END COMPONENT; - COMPONENT boostcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cachecell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT cancell - PORT ( - clock : IN std_ulogic; - can_rx : IN std_ulogic; - can_tx : OUT std_ulogic; - can_tx_en : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT capsensecell - PORT ( - lft : IN std_ulogic; - rt : IN std_ulogic); - END COMPONENT; - COMPONENT clockblockcell - PORT ( - dclk_0 : OUT std_ulogic; - dclk_1 : OUT std_ulogic; - dclk_2 : OUT std_ulogic; - dclk_3 : OUT std_ulogic; - dclk_4 : OUT std_ulogic; - dclk_5 : OUT std_ulogic; - dclk_6 : OUT std_ulogic; - dclk_7 : OUT std_ulogic; - dclk_glb_0 : OUT std_ulogic; - dclk_glb_1 : OUT std_ulogic; - dclk_glb_2 : OUT std_ulogic; - dclk_glb_3 : OUT std_ulogic; - dclk_glb_4 : OUT std_ulogic; - dclk_glb_5 : OUT std_ulogic; - dclk_glb_6 : OUT std_ulogic; - dclk_glb_7 : OUT std_ulogic; - aclk_0 : OUT std_ulogic; - aclk_1 : OUT std_ulogic; - aclk_2 : OUT std_ulogic; - aclk_3 : OUT std_ulogic; - aclk_glb_0 : OUT std_ulogic; - aclk_glb_1 : OUT std_ulogic; - aclk_glb_2 : OUT std_ulogic; - aclk_glb_3 : OUT std_ulogic; - clk_a_dig_0 : OUT std_ulogic; - clk_a_dig_1 : OUT std_ulogic; - clk_a_dig_2 : OUT std_ulogic; - clk_a_dig_3 : OUT std_ulogic; - clk_a_dig_glb_0 : OUT std_ulogic; - clk_a_dig_glb_1 : OUT std_ulogic; - clk_a_dig_glb_2 : OUT std_ulogic; - clk_a_dig_glb_3 : OUT std_ulogic; - clk_bus : OUT std_ulogic; - clk_bus_glb : OUT std_ulogic; - clk_sync : OUT std_ulogic; - clk_32k_xtal : OUT std_ulogic; - clk_100k : OUT std_ulogic; - clk_32k : OUT std_ulogic; - clk_1k : OUT std_ulogic; - clk_usb : OUT std_ulogic; - xmhz_xerr : OUT std_ulogic; - pll_lock_out : OUT std_ulogic; - dsi_dig_div_0 : IN std_ulogic; - dsi_dig_div_1 : IN std_ulogic; - dsi_dig_div_2 : IN std_ulogic; - dsi_dig_div_3 : IN std_ulogic; - dsi_dig_div_4 : IN std_ulogic; - dsi_dig_div_5 : IN std_ulogic; - dsi_dig_div_6 : IN std_ulogic; - dsi_dig_div_7 : IN std_ulogic; - dsi_ana_div_0 : IN std_ulogic; - dsi_ana_div_1 : IN std_ulogic; - dsi_ana_div_2 : IN std_ulogic; - dsi_ana_div_3 : IN std_ulogic; - dsi_glb_div : IN std_ulogic; - dsi_clkin_div : IN std_ulogic; - imo : OUT std_ulogic; - ilo : OUT std_ulogic; - xtal : OUT std_ulogic; - pllout : OUT std_ulogic; - clk_bus_glb_ff : OUT std_ulogic; - aclk_glb_ff_0 : OUT std_ulogic; - clk_a_dig_glb_ff_0 : OUT std_ulogic; - aclk_glb_ff_1 : OUT std_ulogic; - clk_a_dig_glb_ff_1 : OUT std_ulogic; - aclk_glb_ff_2 : OUT std_ulogic; - clk_a_dig_glb_ff_2 : OUT std_ulogic; - aclk_glb_ff_3 : OUT std_ulogic; - clk_a_dig_glb_ff_3 : OUT std_ulogic; - dclk_glb_ff_0 : OUT std_ulogic; - dclk_glb_ff_1 : OUT std_ulogic; - dclk_glb_ff_2 : OUT std_ulogic; - dclk_glb_ff_3 : OUT std_ulogic; - dclk_glb_ff_4 : OUT std_ulogic; - dclk_glb_ff_5 : OUT std_ulogic; - dclk_glb_ff_6 : OUT std_ulogic; - dclk_glb_ff_7 : OUT std_ulogic); - END COMPONENT; - COMPONENT comparatorcell - PORT ( - out : OUT std_ulogic; - clk_udb : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT controlcell - PORT ( - control_0 : OUT std_ulogic; - control_1 : OUT std_ulogic; - control_2 : OUT std_ulogic; - control_3 : OUT std_ulogic; - control_4 : OUT std_ulogic; - control_5 : OUT std_ulogic; - control_6 : OUT std_ulogic; - control_7 : OUT std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT count7cell - PORT ( - clock : IN std_ulogic; - reset : IN std_ulogic; - load : IN std_ulogic; - enable : IN std_ulogic; - clk_en : IN std_ulogic; - count_0 : OUT std_ulogic; - count_1 : OUT std_ulogic; - count_2 : OUT std_ulogic; - count_3 : OUT std_ulogic; - count_4 : OUT std_ulogic; - count_5 : OUT std_ulogic; - count_6 : OUT std_ulogic; - tc : OUT std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT csabufcell - PORT ( - swon : IN std_ulogic); - END COMPONENT; - COMPONENT datapathcell - PORT ( - clock : IN std_ulogic; - clk_en : IN std_ulogic; - reset : IN std_ulogic; - cs_addr_0 : IN std_ulogic; - cs_addr_1 : IN std_ulogic; - cs_addr_2 : IN std_ulogic; - route_si : IN std_ulogic; - route_ci : IN std_ulogic; - f0_load : IN std_ulogic; - f1_load : IN std_ulogic; - d0_load : IN std_ulogic; - d1_load : IN std_ulogic; - ce0_reg : OUT std_ulogic; - cl0_reg : OUT std_ulogic; - z0_reg : OUT std_ulogic; - f0_reg : OUT std_ulogic; - ce1_reg : OUT std_ulogic; - cl1_reg : OUT std_ulogic; - z1_reg : OUT std_ulogic; - f1_reg : OUT std_ulogic; - ov_msb_reg : OUT std_ulogic; - co_msb_reg : OUT std_ulogic; - cmsb_reg : OUT std_ulogic; - so_reg : OUT std_ulogic; - f0_bus_stat_reg : OUT std_ulogic; - f0_blk_stat_reg : OUT std_ulogic; - f1_bus_stat_reg : OUT std_ulogic; - f1_blk_stat_reg : OUT std_ulogic; - ce0_comb : OUT std_ulogic; - cl0_comb : OUT std_ulogic; - z0_comb : OUT std_ulogic; - f0_comb : OUT std_ulogic; - ce1_comb : OUT std_ulogic; - cl1_comb : OUT std_ulogic; - z1_comb : OUT std_ulogic; - f1_comb : OUT std_ulogic; - ov_msb_comb : OUT std_ulogic; - co_msb_comb : OUT std_ulogic; - cmsb_comb : OUT std_ulogic; - so_comb : OUT std_ulogic; - f0_bus_stat_comb : OUT std_ulogic; - f0_blk_stat_comb : OUT std_ulogic; - f1_bus_stat_comb : OUT std_ulogic; - f1_blk_stat_comb : OUT std_ulogic; - ce0 : OUT std_ulogic; - ce0i : IN std_ulogic; - p_in_0 : IN std_ulogic; - p_in_1 : IN std_ulogic; - p_in_2 : IN std_ulogic; - p_in_3 : IN std_ulogic; - p_in_4 : IN std_ulogic; - p_in_5 : IN std_ulogic; - p_in_6 : IN std_ulogic; - p_in_7 : IN std_ulogic; - p_out_0 : OUT std_ulogic; - p_out_1 : OUT std_ulogic; - p_out_2 : OUT std_ulogic; - p_out_3 : OUT std_ulogic; - p_out_4 : OUT std_ulogic; - p_out_5 : OUT std_ulogic; - p_out_6 : OUT std_ulogic; - p_out_7 : OUT std_ulogic; - cl0i : IN std_ulogic; - cl0 : OUT std_ulogic; - z0i : IN std_ulogic; - z0 : OUT std_ulogic; - ff0i : IN std_ulogic; - ff0 : OUT std_ulogic; - ce1i : IN std_ulogic; - ce1 : OUT std_ulogic; - cl1i : IN std_ulogic; - cl1 : OUT std_ulogic; - z1i : IN std_ulogic; - z1 : OUT std_ulogic; - ff1i : IN std_ulogic; - ff1 : OUT std_ulogic; - cap0i : IN std_ulogic; - cap0 : OUT std_ulogic; - cap1i : IN std_ulogic; - cap1 : OUT std_ulogic; - ci : IN std_ulogic; - co_msb : OUT std_ulogic; - sir : IN std_ulogic; - sol_msb : OUT std_ulogic; - cfbi : IN std_ulogic; - cfbo : OUT std_ulogic; - sil : IN std_ulogic; - sor : OUT std_ulogic; - cmsbi : IN std_ulogic; - cmsbo : OUT std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT decimatorcell - PORT ( - aclock : IN std_ulogic; - mod_dat_0 : IN std_ulogic; - mod_dat_1 : IN std_ulogic; - mod_dat_2 : IN std_ulogic; - mod_dat_3 : IN std_ulogic; - ext_start : IN std_ulogic; - modrst : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT dfbcell - PORT ( - clock : IN std_ulogic; - in_1 : IN std_ulogic; - in_2 : IN std_ulogic; - out_1 : OUT std_ulogic; - out_2 : OUT std_ulogic; - dmareq_1 : OUT std_ulogic; - dmareq_2 : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT drqcell - PORT ( - dmareq : IN std_ulogic; - termin : IN std_ulogic; - termout : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT dsmodcell - PORT ( - aclock : IN std_ulogic; - modbitin_udb : IN std_ulogic; - reset_udb : IN std_ulogic; - reset_dec : IN std_ulogic; - dec_clock : OUT std_ulogic; - mod_dat_0 : OUT std_ulogic; - mod_dat_1 : OUT std_ulogic; - mod_dat_2 : OUT std_ulogic; - mod_dat_3 : OUT std_ulogic; - dout_udb_0 : OUT std_ulogic; - dout_udb_1 : OUT std_ulogic; - dout_udb_2 : OUT std_ulogic; - dout_udb_3 : OUT std_ulogic; - dout_udb_4 : OUT std_ulogic; - dout_udb_5 : OUT std_ulogic; - dout_udb_6 : OUT std_ulogic; - dout_udb_7 : OUT std_ulogic; - extclk_cp_udb : IN std_ulogic; - clk_udb : IN std_ulogic); - END COMPONENT; - COMPONENT emifcell - PORT ( - EM_clock : OUT std_ulogic; - EM_CEn : OUT std_ulogic; - EM_OEn : OUT std_ulogic; - EM_ADSCn : OUT std_ulogic; - EM_sleep : OUT std_ulogic; - EM_WRn : OUT std_ulogic; - dataport_OE : OUT std_ulogic; - dataport_OEn : OUT std_ulogic; - wr : OUT std_ulogic; - rd : OUT std_ulogic; - udb_stall : IN std_ulogic; - udb_ready : IN std_ulogic; - busclk : IN std_ulogic); - END COMPONENT; - COMPONENT i2ccell - PORT ( - clock : IN std_ulogic; - scl_in : IN std_ulogic; - sda_in : IN std_ulogic; - scl_out : OUT std_ulogic; - sda_out : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT interrupt - PORT ( - interrupt : IN std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT iocell - PORT ( - pin_input : IN std_ulogic; - oe : IN std_ulogic; - fb : OUT std_ulogic; - pad_in : IN std_ulogic; - pa_out : OUT std_ulogic; - pad_out : OUT std_ulogic; - oe_reg : OUT std_ulogic; - oe_internal : IN std_ulogic; - in_clock : IN std_ulogic; - in_clock_en : IN std_ulogic; - in_reset : IN std_ulogic; - out_clock : IN std_ulogic; - out_clock_en : IN std_ulogic; - out_reset : IN std_ulogic); - END COMPONENT; - COMPONENT lcdctrlcell - PORT ( - drive_en : IN std_ulogic; - frame : IN std_ulogic; - data_clk : IN std_ulogic; - en_hi : IN std_ulogic; - dac_dis : IN std_ulogic; - chop_clk : IN std_ulogic; - int_clr : IN std_ulogic; - lp_ack_udb : IN std_ulogic; - mode_1 : IN std_ulogic; - mode_2 : IN std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT logicalport - PORT ( - interrupt : OUT std_ulogic; - precharge : IN std_ulogic; - in_clock : IN std_ulogic; - in_clock_en : IN std_ulogic; - in_reset : IN std_ulogic; - out_clock : IN std_ulogic; - out_clock_en : IN std_ulogic; - out_reset : IN std_ulogic); - END COMPONENT; - COMPONENT lpfcell - END COMPONENT; - COMPONENT lvdcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8clockblockcell - PORT ( - imo : OUT std_ulogic; - ext : OUT std_ulogic; - eco : OUT std_ulogic; - ilo : OUT std_ulogic; - wco : OUT std_ulogic; - dbl : OUT std_ulogic; - pll : OUT std_ulogic; - dpll : OUT std_ulogic; - dsi_out_0 : OUT std_ulogic; - dsi_out_1 : OUT std_ulogic; - dsi_out_2 : OUT std_ulogic; - dsi_out_3 : OUT std_ulogic; - lfclk : OUT std_ulogic; - hfclk : OUT std_ulogic; - sysclk : OUT std_ulogic; - halfsysclk : OUT std_ulogic; - udb_div_0 : OUT std_ulogic; - udb_div_1 : OUT std_ulogic; - udb_div_2 : OUT std_ulogic; - udb_div_3 : OUT std_ulogic; - udb_div_4 : OUT std_ulogic; - udb_div_5 : OUT std_ulogic; - udb_div_6 : OUT std_ulogic; - udb_div_7 : OUT std_ulogic; - udb_div_8 : OUT std_ulogic; - udb_div_9 : OUT std_ulogic; - udb_div_10 : OUT std_ulogic; - udb_div_11 : OUT std_ulogic; - udb_div_12 : OUT std_ulogic; - udb_div_13 : OUT std_ulogic; - udb_div_14 : OUT std_ulogic; - udb_div_15 : OUT std_ulogic; - uab_div_0 : OUT std_ulogic; - uab_div_1 : OUT std_ulogic; - uab_div_2 : OUT std_ulogic; - uab_div_3 : OUT std_ulogic; - ff_div_0 : OUT std_ulogic; - ff_div_1 : OUT std_ulogic; - ff_div_2 : OUT std_ulogic; - ff_div_3 : OUT std_ulogic; - ff_div_4 : OUT std_ulogic; - ff_div_5 : OUT std_ulogic; - ff_div_6 : OUT std_ulogic; - ff_div_7 : OUT std_ulogic; - ff_div_8 : OUT std_ulogic; - ff_div_9 : OUT std_ulogic; - ff_div_10 : OUT std_ulogic; - ff_div_11 : OUT std_ulogic; - ff_div_12 : OUT std_ulogic; - ff_div_13 : OUT std_ulogic; - ff_div_14 : OUT std_ulogic; - ff_div_15 : OUT std_ulogic; - dsi_in_0 : IN std_ulogic; - dsi_in_1 : IN std_ulogic; - dsi_in_2 : IN std_ulogic; - dsi_in_3 : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8clockgenblockcell - PORT ( - gen_clk_in_0 : IN std_ulogic; - gen_clk_in_1 : IN std_ulogic; - gen_clk_in_2 : IN std_ulogic; - gen_clk_in_3 : IN std_ulogic; - gen_clk_in_4 : IN std_ulogic; - gen_clk_in_5 : IN std_ulogic; - gen_clk_in_6 : IN std_ulogic; - gen_clk_in_7 : IN std_ulogic; - gen_clk_out_0 : OUT std_ulogic; - gen_clk_out_1 : OUT std_ulogic; - gen_clk_out_2 : OUT std_ulogic; - gen_clk_out_3 : OUT std_ulogic; - gen_clk_out_4 : OUT std_ulogic; - gen_clk_out_5 : OUT std_ulogic; - gen_clk_out_6 : OUT std_ulogic; - gen_clk_out_7 : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8lcdcell - PORT ( - common_0 : OUT std_ulogic; - common_1 : OUT std_ulogic; - common_2 : OUT std_ulogic; - common_3 : OUT std_ulogic; - common_4 : OUT std_ulogic; - common_5 : OUT std_ulogic; - common_6 : OUT std_ulogic; - common_7 : OUT std_ulogic; - common_8 : OUT std_ulogic; - common_9 : OUT std_ulogic; - common_10 : OUT std_ulogic; - common_11 : OUT std_ulogic; - common_12 : OUT std_ulogic; - common_13 : OUT std_ulogic; - common_14 : OUT std_ulogic; - common_15 : OUT std_ulogic; - segment_0 : OUT std_ulogic; - segment_1 : OUT std_ulogic; - segment_2 : OUT std_ulogic; - segment_3 : OUT std_ulogic; - segment_4 : OUT std_ulogic; - segment_5 : OUT std_ulogic; - segment_6 : OUT std_ulogic; - segment_7 : OUT std_ulogic; - segment_8 : OUT std_ulogic; - segment_9 : OUT std_ulogic; - segment_10 : OUT std_ulogic; - segment_11 : OUT std_ulogic; - segment_12 : OUT std_ulogic; - segment_13 : OUT std_ulogic; - segment_14 : OUT std_ulogic; - segment_15 : OUT std_ulogic; - segment_16 : OUT std_ulogic; - segment_17 : OUT std_ulogic; - segment_18 : OUT std_ulogic; - segment_19 : OUT std_ulogic; - segment_20 : OUT std_ulogic; - segment_21 : OUT std_ulogic; - segment_22 : OUT std_ulogic; - segment_23 : OUT std_ulogic; - segment_24 : OUT std_ulogic; - segment_25 : OUT std_ulogic; - segment_26 : OUT std_ulogic; - segment_27 : OUT std_ulogic; - segment_28 : OUT std_ulogic; - segment_29 : OUT std_ulogic; - segment_30 : OUT std_ulogic; - segment_31 : OUT std_ulogic; - segment_32 : OUT std_ulogic; - segment_33 : OUT std_ulogic; - segment_34 : OUT std_ulogic; - segment_35 : OUT std_ulogic; - segment_36 : OUT std_ulogic; - segment_37 : OUT std_ulogic; - segment_38 : OUT std_ulogic; - segment_39 : OUT std_ulogic; - segment_40 : OUT std_ulogic; - segment_41 : OUT std_ulogic; - segment_42 : OUT std_ulogic; - segment_43 : OUT std_ulogic; - segment_44 : OUT std_ulogic; - segment_45 : OUT std_ulogic; - segment_46 : OUT std_ulogic; - segment_47 : OUT std_ulogic; - segment_48 : OUT std_ulogic; - segment_49 : OUT std_ulogic; - segment_50 : OUT std_ulogic; - segment_51 : OUT std_ulogic; - segment_52 : OUT std_ulogic; - segment_53 : OUT std_ulogic; - segment_54 : OUT std_ulogic; - segment_55 : OUT std_ulogic; - segment_56 : OUT std_ulogic; - segment_57 : OUT std_ulogic; - segment_58 : OUT std_ulogic; - segment_59 : OUT std_ulogic; - segment_60 : OUT std_ulogic; - segment_61 : OUT std_ulogic; - segment_62 : OUT std_ulogic; - segment_63 : OUT std_ulogic; - clock : IN std_ulogic); - END COMPONENT; - COMPONENT m0s8pmcell - PORT ( - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8scbcell - PORT ( - clock : IN std_ulogic; - interrupt : OUT std_ulogic; - rx : IN std_ulogic; - tx : OUT std_ulogic; - mosi_m : OUT std_ulogic; - miso_m : IN std_ulogic; - select_m_0 : OUT std_ulogic; - select_m_1 : OUT std_ulogic; - select_m_2 : OUT std_ulogic; - select_m_3 : OUT std_ulogic; - sclk_m : OUT std_ulogic; - mosi_s : IN std_ulogic; - miso_s : OUT std_ulogic; - select_s : IN std_ulogic; - sclk_s : IN std_ulogic; - scl : INOUT std_ulogic; - sda : INOUT std_ulogic); - END COMPONENT; - COMPONENT m0s8spcifcell - PORT ( - spcif_int : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tcpwmcell - PORT ( - clock : IN std_ulogic; - capture : IN std_ulogic; - count : IN std_ulogic; - reload : IN std_ulogic; - stop : IN std_ulogic; - start : IN std_ulogic; - tr_underflow : OUT std_ulogic; - tr_overflow : OUT std_ulogic; - tr_compare_match : OUT std_ulogic; - line_out : OUT std_ulogic; - line_out_compl : OUT std_ulogic; - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8tsscell - PORT ( - clk_seq : IN std_ulogic; - clk_adc : IN std_ulogic; - ext_reject : IN std_ulogic; - ext_sync : IN std_ulogic; - tx_sync : IN std_ulogic; - reject_in : IN std_ulogic; - start_in : IN std_ulogic; - lx_det_hi : OUT std_ulogic; - lx_det_lo : OUT std_ulogic; - rej_window : OUT std_ulogic; - tx_hilo : OUT std_ulogic; - phase_end : OUT std_ulogic; - phase_num_0 : OUT std_ulogic; - phase_num_1 : OUT std_ulogic; - phase_num_2 : OUT std_ulogic; - phase_num_3 : OUT std_ulogic; - ipq_reject : OUT std_ulogic; - ipq_start : OUT std_ulogic; - epq_reject : OUT std_ulogic; - epq_start : OUT std_ulogic; - mcs_reject : OUT std_ulogic; - mcs_start : OUT std_ulogic; - do_switch : OUT std_ulogic; - adc_start : OUT std_ulogic; - adc_done : OUT std_ulogic); - END COMPONENT; - COMPONENT m0s8wdtcell - PORT ( - wdt_int : OUT std_ulogic); - END COMPONENT; - COMPONENT macrocell - PORT ( - main_0 : IN std_ulogic; - main_1 : IN std_ulogic; - main_2 : IN std_ulogic; - main_3 : IN std_ulogic; - main_4 : IN std_ulogic; - main_5 : IN std_ulogic; - main_6 : IN std_ulogic; - main_7 : IN std_ulogic; - main_8 : IN std_ulogic; - main_9 : IN std_ulogic; - main_10 : IN std_ulogic; - main_11 : IN std_ulogic; - ar_0 : IN std_ulogic; - ap_0 : IN std_ulogic; - clock_0 : IN std_ulogic; - clk_en : IN std_ulogic; - cin : IN std_ulogic; - cpt0_0 : IN std_ulogic; - cpt0_1 : IN std_ulogic; - cpt0_2 : IN std_ulogic; - cpt0_3 : IN std_ulogic; - cpt0_4 : IN std_ulogic; - cpt0_5 : IN std_ulogic; - cpt0_6 : IN std_ulogic; - cpt0_7 : IN std_ulogic; - cpt0_8 : IN std_ulogic; - cpt0_9 : IN std_ulogic; - cpt0_10 : IN std_ulogic; - cpt0_11 : IN std_ulogic; - cpt1_0 : IN std_ulogic; - cpt1_1 : IN std_ulogic; - cpt1_2 : IN std_ulogic; - cpt1_3 : IN std_ulogic; - cpt1_4 : IN std_ulogic; - cpt1_5 : IN std_ulogic; - cpt1_6 : IN std_ulogic; - cpt1_7 : IN std_ulogic; - cpt1_8 : IN std_ulogic; - cpt1_9 : IN std_ulogic; - cpt1_10 : IN std_ulogic; - cpt1_11 : IN std_ulogic; - cout : OUT std_ulogic; - q : OUT std_ulogic; - q_fixed : OUT std_ulogic); - END COMPONENT; - COMPONENT p4abufcell - PORT ( - ctb_dsi_comp : OUT std_ulogic; - dsi_out : IN std_ulogic); - END COMPONENT; - COMPONENT p4anapumpcell - PORT ( - pump_clock : IN std_ulogic); - END COMPONENT; - COMPONENT p4csdcell - PORT ( - sense_out : OUT std_ulogic; - sample_out : OUT std_ulogic; - sense_in : IN std_ulogic; - sample_in : IN std_ulogic; - clk1 : IN std_ulogic; - clk2 : IN std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT p4csidac7cell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4csidac8cell - PORT ( - en : IN std_ulogic); - END COMPONENT; - COMPONENT p4ctbmblockcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT p4halfuabcell - PORT ( - clock : IN std_ulogic; - comp : OUT std_ulogic; - ctrl : IN std_ulogic); - END COMPONENT; - COMPONENT p4lpcompblockcell - PORT ( - interrupt : OUT std_ulogic); - END COMPONENT; - COMPONENT p4lpcompcell - PORT ( - cmpout : OUT std_ulogic); - END COMPONENT; - COMPONENT p4rsbcell - END COMPONENT; - COMPONENT p4sarcell - PORT ( - clock : IN std_ulogic; - sample_done : OUT std_ulogic; - chan_id_valid : OUT std_ulogic; - chan_id_0 : OUT std_ulogic; - chan_id_1 : OUT std_ulogic; - chan_id_2 : OUT std_ulogic; - chan_id_3 : OUT std_ulogic; - data_valid : OUT std_ulogic; - data_0 : OUT std_ulogic; - data_1 : OUT std_ulogic; - data_2 : OUT std_ulogic; - data_3 : OUT std_ulogic; - data_4 : OUT std_ulogic; - data_5 : OUT std_ulogic; - data_6 : OUT std_ulogic; - data_7 : OUT std_ulogic; - data_8 : OUT std_ulogic; - data_9 : OUT std_ulogic; - data_10 : OUT std_ulogic; - data_11 : OUT std_ulogic; - eos_intr : OUT std_ulogic; - irq : OUT std_ulogic; - sw_negvref : IN std_ulogic; - cfg_st_sel_0 : IN std_ulogic; - cfg_st_sel_1 : IN std_ulogic; - cfg_average : IN std_ulogic; - cfg_resolution : IN std_ulogic; - cfg_differential : IN std_ulogic; - trigger : IN std_ulogic; - data_hilo_sel : IN std_ulogic; - swctrl0 : IN std_ulogic; - swctrl1 : IN std_ulogic); - END COMPONENT; - COMPONENT p4sarmuxcell - END COMPONENT; - COMPONENT p4tempcell - END COMPONENT; - COMPONENT p4vrefcell - END COMPONENT; - COMPONENT pmcell - PORT ( - ctw_int : OUT std_ulogic; - ftw_int : OUT std_ulogic; - limact_int : OUT std_ulogic; - onepps_int : OUT std_ulogic; - pm_int : OUT std_ulogic); - END COMPONENT; - COMPONENT sarcell - PORT ( - clock : IN std_ulogic; - pump_clock : IN std_ulogic; - clk_udb : IN std_ulogic; - sof_udb : IN std_ulogic; - vp_ctl_udb_0 : IN std_ulogic; - vp_ctl_udb_1 : IN std_ulogic; - vp_ctl_udb_2 : IN std_ulogic; - vp_ctl_udb_3 : IN std_ulogic; - vn_ctl_udb_0 : IN std_ulogic; - vn_ctl_udb_1 : IN std_ulogic; - vn_ctl_udb_2 : IN std_ulogic; - vn_ctl_udb_3 : IN std_ulogic; - data_out_udb_0 : OUT std_ulogic; - data_out_udb_1 : OUT std_ulogic; - data_out_udb_2 : OUT std_ulogic; - data_out_udb_3 : OUT std_ulogic; - data_out_udb_4 : OUT std_ulogic; - data_out_udb_5 : OUT std_ulogic; - data_out_udb_6 : OUT std_ulogic; - data_out_udb_7 : OUT std_ulogic; - data_out_udb_8 : OUT std_ulogic; - data_out_udb_9 : OUT std_ulogic; - data_out_udb_10 : OUT std_ulogic; - data_out_udb_11 : OUT std_ulogic; - eof_udb : OUT std_ulogic; - irq : OUT std_ulogic; - next : OUT std_ulogic); - END COMPONENT; - COMPONENT sccell - PORT ( - aclk : IN std_ulogic; - bst_clk : IN std_ulogic; - clk_udb : IN std_ulogic; - modout : OUT std_ulogic; - dyn_cntl_udb : IN std_ulogic); - END COMPONENT; - COMPONENT spccell - PORT ( - data_ready : OUT std_ulogic; - eeprom_fault_int : OUT std_ulogic; - idle : OUT std_ulogic); - END COMPONENT; - COMPONENT ssccell - PORT ( - rst_n : IN std_ulogic; - scli : IN std_ulogic; - sdai : IN std_ulogic; - csel : IN std_ulogic; - sclo : OUT std_ulogic; - sdao : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT statuscell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - status_7 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT statusicell - PORT ( - status_0 : IN std_ulogic; - status_1 : IN std_ulogic; - status_2 : IN std_ulogic; - status_3 : IN std_ulogic; - status_4 : IN std_ulogic; - status_5 : IN std_ulogic; - status_6 : IN std_ulogic; - clock : IN std_ulogic; - reset : IN std_ulogic; - interrupt : OUT std_ulogic; - clk_en : IN std_ulogic); - END COMPONENT; - COMPONENT synccell - PORT ( - in : IN std_ulogic; - clock : IN std_ulogic; - out : OUT std_ulogic; - clk_en : IN std_ulogic; - clock_n : IN std_ulogic; - extclk : IN std_ulogic; - extclk_n : IN std_ulogic); - END COMPONENT; - COMPONENT tfaultcell - PORT ( - tfault_dsi : OUT std_ulogic); - END COMPONENT; - COMPONENT timercell - PORT ( - clock : IN std_ulogic; - kill : IN std_ulogic; - enable : IN std_ulogic; - capture : IN std_ulogic; - timer_reset : IN std_ulogic; - tc : OUT std_ulogic; - cmp : OUT std_ulogic; - irq : OUT std_ulogic); - END COMPONENT; - COMPONENT udbclockencell - PORT ( - clock_in : IN std_ulogic; - enable : IN std_ulogic; - clock_out : OUT std_ulogic); - END COMPONENT; - COMPONENT usbcell - PORT ( - sof_int : OUT std_ulogic; - arb_int : OUT std_ulogic; - usb_int : OUT std_ulogic; - ord_int : OUT std_ulogic; - ept_int_0 : OUT std_ulogic; - ept_int_1 : OUT std_ulogic; - ept_int_2 : OUT std_ulogic; - ept_int_3 : OUT std_ulogic; - ept_int_4 : OUT std_ulogic; - ept_int_5 : OUT std_ulogic; - ept_int_6 : OUT std_ulogic; - ept_int_7 : OUT std_ulogic; - ept_int_8 : OUT std_ulogic; - dma_req_0 : OUT std_ulogic; - dma_req_1 : OUT std_ulogic; - dma_req_2 : OUT std_ulogic; - dma_req_3 : OUT std_ulogic; - dma_req_4 : OUT std_ulogic; - dma_req_5 : OUT std_ulogic; - dma_req_6 : OUT std_ulogic; - dma_req_7 : OUT std_ulogic; - dma_termin : OUT std_ulogic); - END COMPONENT; - COMPONENT vidaccell - PORT ( - data_0 : IN std_ulogic; - data_1 : IN std_ulogic; - data_2 : IN std_ulogic; - data_3 : IN std_ulogic; - data_4 : IN std_ulogic; - data_5 : IN std_ulogic; - data_6 : IN std_ulogic; - data_7 : IN std_ulogic; - strobe : IN std_ulogic; - strobe_udb : IN std_ulogic; - reset : IN std_ulogic; - idir : IN std_ulogic; - ioff : IN std_ulogic); - END COMPONENT; -BEGIN - - ClockBlock:clockblockcell - PORT MAP( - clk_bus_glb => ClockBlock_BUS_CLK, - clk_bus => ClockBlock_BUS_CLK_local, - clk_sync => ClockBlock_MASTER_CLK, - clk_32k_xtal => ClockBlock_XTAL_32KHZ, - xtal => ClockBlock_XTAL, - ilo => ClockBlock_ILO, - clk_100k => ClockBlock_100k, - clk_1k => ClockBlock_1k, - clk_32k => ClockBlock_32k, - pllout => ClockBlock_PLL_OUT, - imo => ClockBlock_IMO, - dsi_clkin_div => open, - dsi_glb_div => open); - - SCSI_Out:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110110110110", - ibuf_enabled => "1111111111", - id => "11f071e8-9c92-47e0-872a-3f48765a75b8", - init_dr_st => "0000000000", - input_clk_en => 0, - input_sync => "1111111111", - input_sync_mode => "0000000000", - intr_mode => "00000000000000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "5, 5, 5, 5, 5, 5, 5, 5, 5, 5", - layout_mode => "NONCONTIGUOUS", - oe_conn => "0000000000", - oe_reset => 0, - oe_sync => "0000000000", - output_clk_en => 0, - output_clock_mode => "0000000000", - output_conn => "0000000000", - output_mode => "0000000000", - output_reset => 0, - output_sync => "0000000000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "DBP_raw,ATN,BSY,ACK,RST,MSG,SEL,CD,REQ,IO_raw", - pin_mode => "OOOOOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0000000000", - sio_ibuf => "00000000", - sio_info => "00000000000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0000000000", - spanning => 1, - sw_only => 0, - use_annotation => "1111111111", - vtrip => "10101010101010101010", - width => 10, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - SCSI_Out(0):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(0)__PA, - oe => open, - pad_in => SCSI_Out(0)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(1):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(1)__PA, - oe => open, - pad_in => SCSI_Out(1)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(2):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(2)__PA, - oe => open, - pad_in => SCSI_Out(2)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(3):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(3)__PA, - oe => open, - pad_in => SCSI_Out(3)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(4):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(4)__PA, - oe => open, - pad_in => SCSI_Out(4)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(5):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(5)__PA, - oe => open, - pad_in => SCSI_Out(5)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(6):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(6)__PA, - oe => open, - pad_in => SCSI_Out(6)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(7):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 7, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(7)__PA, - oe => open, - pad_in => SCSI_Out(7)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(8):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 8, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(8)__PA, - oe => open, - pad_in => SCSI_Out(8)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out(9):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out", - logicalport_pin_id => 9, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out(9)__PA, - oe => open, - pad_in => SCSI_Out(9)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx:logicalport - GENERIC MAP( - drive_mode => "110110110110110110110110", - ibuf_enabled => "11111111", - id => "52f31aa9-2f0a-497d-9a1f-1424095e13e6", - init_dr_st => "00000000", - input_clk_en => 0, - input_sync => "11111111", - input_sync_mode => "00000000", - intr_mode => "0000000000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => ", , , , , , , 5", - layout_mode => "NONCONTIGUOUS", - oe_conn => "00000000", - oe_reset => 0, - oe_sync => "00000000", - output_clk_en => 0, - output_clock_mode => "00000000", - output_conn => "00000000", - output_mode => "00000000", - output_reset => 0, - output_sync => "00000000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "DB0,DB1,DB2,DB3,DB4,DB5,DB6,DB7", - pin_mode => "OOOOOOOO", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "00000000", - sio_ibuf => "00000000", - sio_info => "0000000000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "00000000", - spanning => 1, - sw_only => 0, - use_annotation => "11111111", - vtrip => "1010101010101010", - width => 8, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - SCSI_Out_DBx(0):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(0)__PA, - oe => open, - pad_in => SCSI_Out_DBx(0)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(1):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(1)__PA, - oe => open, - pad_in => SCSI_Out_DBx(1)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(2):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(2)__PA, - oe => open, - pad_in => SCSI_Out_DBx(2)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(3):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(3)__PA, - oe => open, - pad_in => SCSI_Out_DBx(3)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(4):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(4)__PA, - oe => open, - pad_in => SCSI_Out_DBx(4)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(5):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 5, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(5)__PA, - oe => open, - pad_in => SCSI_Out_DBx(5)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(6):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 6, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(6)__PA, - oe => open, - pad_in => SCSI_Out_DBx(6)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SCSI_Out_DBx(7):iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SCSI_Out_DBx", - logicalport_pin_id => 7, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SCSI_Out_DBx(7)__PA, - oe => open, - pad_in => SCSI_Out_DBx(7)_PAD, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP:logicalport - GENERIC MAP( - drive_mode => "010010010010010", - ibuf_enabled => "11111", - id => "4c15b41e-e284-4978-99e7-5aaee19bd0ce", - init_dr_st => "11111", - input_clk_en => 0, - input_sync => "11111", - input_sync_mode => "00000", - intr_mode => "0000000000", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "3.3, , , , ", - layout_mode => "CONTIGUOUS", - oe_conn => "00000", - oe_reset => 0, - oe_sync => "00000", - output_clk_en => 0, - output_clock_mode => "00000", - output_conn => "00000", - output_mode => "00000", - output_reset => 0, - output_sync => "00000", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => ",,,,", - pin_mode => "IIIII", - por_state => 2, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "00000", - sio_ibuf => "00000000", - sio_info => "0000000000", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "00000", - spanning => 0, - sw_only => 0, - use_annotation => "00000", - vtrip => "0000000000", - width => 5, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open, - in_clock => open); - - SD_PULLUP(0):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(0)__PA, - oe => open, - pad_in => SD_PULLUP(0)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(1):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 1, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(1)__PA, - oe => open, - pad_in => SD_PULLUP(1)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(2):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 2, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(2)__PA, - oe => open, - pad_in => SD_PULLUP(2)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(3):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 3, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(3)__PA, - oe => open, - pad_in => SD_PULLUP(3)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - SD_PULLUP(4):iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "SD_PULLUP", - logicalport_pin_id => 4, - io_capabilities => "0000000000000000000000000000000000000000000000000000000000000001") - PORT MAP( - pa_out => SD_PULLUP(4)__PA, - oe => open, - pad_in => SD_PULLUP(4)_PAD, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dm(0)\:iocell - GENERIC MAP( - in_sync_mode => 0, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "\USBFS:Dm\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000010000000000000000") - PORT MAP( - pa_out => \\\USBFS:Dm(0)\\__PA\, - oe => open, - in_clock => open, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dm\:logicalport - GENERIC MAP( - drive_mode => "000", - ibuf_enabled => "0", - id => "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/8b77a6c4-10a0-4390-971c-672353e2a49c", - init_dr_st => "0", - input_clk_en => 0, - input_sync => "1", - input_sync_mode => "0", - intr_mode => "00", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "", - layout_mode => "NONCONTIGUOUS", - oe_conn => "0", - oe_reset => 0, - oe_sync => "0", - output_clk_en => 0, - output_clock_mode => "0", - output_conn => "0", - output_mode => "0", - output_reset => 0, - output_sync => "0", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "", - pin_mode => "A", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 1, - sw_only => 0, - use_annotation => "0", - vtrip => "10", - width => 1, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open); - - \USBFS:Dp(0)\:iocell - GENERIC MAP( - in_sync_mode => 2, - out_sync_mode => 0, - oe_sync_mode => 0, - logicalport => "\USBFS:Dp\", - logicalport_pin_id => 0, - io_capabilities => "0000000000000000000000000000000000000000000000001000000000000000") - PORT MAP( - pa_out => \\\USBFS:Dp(0)\\__PA\, - oe => open, - in_clock => ClockBlock_BUS_CLK, - in_clock_en => '1', - in_reset => '0', - out_clock => open, - out_clock_en => '1', - out_reset => '0'); - - \USBFS:Dp\:logicalport - GENERIC MAP( - drive_mode => "000", - ibuf_enabled => "0", - id => "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42", - init_dr_st => "0", - input_clk_en => 0, - input_sync => "1", - input_sync_mode => "0", - intr_mode => "10", - invert_in_clock => 0, - invert_in_clock_en => 0, - invert_in_reset => 0, - invert_out_clock => 0, - invert_out_clock_en => 0, - invert_out_reset => 0, - io_voltage => "", - layout_mode => "CONTIGUOUS", - oe_conn => "0", - oe_reset => 0, - oe_sync => "0", - output_clk_en => 0, - output_clock_mode => "0", - output_conn => "0", - output_mode => "0", - output_reset => 0, - output_sync => "0", - pa_in_clock => -1, - pa_in_clock_en => -1, - pa_in_reset => -1, - pa_out_clock => -1, - pa_out_clock_en => -1, - pa_out_reset => -1, - pin_aliases => "", - pin_mode => "I", - por_state => 4, - port_alias_group => "", - port_alias_required => 0, - sio_group_cnt => 0, - sio_hifreq => "", - sio_hyst => "0", - sio_ibuf => "00000000", - sio_info => "00", - sio_obuf => "00000000", - sio_refsel => "00000000", - sio_vtrip => "00000000", - slew_rate => "0", - spanning => 0, - sw_only => 0, - use_annotation => "0", - vtrip => "00", - width => 1, - in_clk_inv => 0, - in_clken_inv => 0, - in_clken_mode => 1, - in_rst_inv => 0, - out_clk_inv => 0, - out_clken_inv => 0, - out_clken_mode => 1, - out_rst_inv => 0) - PORT MAP( - in_clock_en => open, - in_reset => open, - out_clock_en => open, - out_reset => open, - interrupt => \USBFS:Net_1010\, - in_clock => open); - - \USBFS:USB\:usbcell - GENERIC MAP( - cy_registers => "") - PORT MAP( - sof_int => Net_40, - arb_int => \USBFS:Net_79\, - usb_int => \USBFS:Net_81\, - ept_int_8 => \USBFS:ept_int_8\, - ept_int_7 => \USBFS:ept_int_7\, - ept_int_6 => \USBFS:ept_int_6\, - ept_int_5 => \USBFS:ept_int_5\, - ept_int_4 => \USBFS:ept_int_4\, - ept_int_3 => \USBFS:ept_int_3\, - ept_int_2 => \USBFS:ept_int_2\, - ept_int_1 => \USBFS:ept_int_1\, - ept_int_0 => \USBFS:ept_int_0\, - ord_int => \USBFS:Net_95\, - dma_req_7 => \USBFS:dma_req_7\, - dma_req_6 => \USBFS:dma_req_6\, - dma_req_5 => \USBFS:dma_req_5\, - dma_req_4 => \USBFS:dma_req_4\, - dma_req_3 => \USBFS:dma_req_3\, - dma_req_2 => \USBFS:dma_req_2\, - dma_req_1 => \USBFS:dma_req_1\, - dma_req_0 => \USBFS:dma_req_0\, - dma_termin => \USBFS:Net_824\); - - \USBFS:arb_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_79\, - clock => ClockBlock_BUS_CLK); - - \USBFS:bus_reset\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_81\, - clock => ClockBlock_BUS_CLK); - - \USBFS:dp_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:Net_1010\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_0\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_0\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_1\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_1\, - clock => ClockBlock_BUS_CLK); - - \USBFS:ep_2\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => \USBFS:ept_int_2\, - clock => ClockBlock_BUS_CLK); - - \USBFS:sof_int\:interrupt - GENERIC MAP( - int_type => "10") - PORT MAP( - interrupt => Net_40, - clock => ClockBlock_BUS_CLK); - -END __DEFAULT__; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html deleted file mode 100755 index 83b2bc2..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_timing.html +++ /dev/null @@ -1,642 +0,0 @@ - - - - -Static Timing Analysis Report - - - - - -

View this file with a JavaScript-enabled browser to enable all features.

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Static Timing Analysis

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Project : USB_Bootloader
Build Time : 03/22/14 22:32:57
Device : CY8C5267AXI-LP051
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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No Timing Violations
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ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
CyILOCyILO100.000 kHz100.000 kHz N/A
CyIMOCyIMO24.000 MHz24.000 MHz N/A
CyMASTER_CLKCyMASTER_CLK64.000 MHz64.000 MHz N/A
CyBUS_CLKCyMASTER_CLK64.000 MHz64.000 MHz N/A
CyPLL_OUTCyPLL_OUT64.000 MHz64.000 MHz N/A
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- - \ No newline at end of file diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc deleted file mode 100755 index 9a6a731..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/USB_Bootloader_u.sdc +++ /dev/null @@ -1,3 +0,0 @@ -# Component constraints for W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch -# Project: W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -# Date: Sat, 22 Mar 2014 12:32:47 GMT diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt deleted file mode 100755 index 50436bf..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/bitstream.txt +++ /dev/null @@ -1,825 +0,0 @@ -===========Generating Bitstream=========== -# IDMUX (count=6) -00000000: 00 00 00 00 00 00 -# IOPORT_0 (count=7) -00000006: 00 00 00 00 00 00 00 -# IOPINS0_0 (count=8) -0000000d: 00 ff ff 00 00 00 00 00 -# IOPINS1_0 + 0x00000009 (count=5) -00000015: 00 00 00 00 00 -# IOPORT_1 (count=7) -0000001a: 00 00 00 00 00 00 00 -# IOPINS0_1 (count=16) -00000021: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# IOPORT_2 (count=7) -00000031: 00 00 00 00 00 00 00 -# IOPINS0_2 (count=16) -00000038: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# IOPORT_3 (count=7) -00000048: 00 00 00 00 3e 00 00 -# IOPINS0_3 (count=8) -0000004f: 00 3e 00 00 00 00 00 00 -# IOPINS1_3 + 0x00000009 (count=5) -00000057: 00 00 00 00 00 -# IOPORT_4 (count=7) -0000005c: 00 00 00 00 00 00 00 -# IOPINS0_4 (count=8) -00000063: 00 fc fc 00 00 00 00 00 -# IOPINS1_4 + 0x00000009 (count=5) -0000006b: 00 00 00 00 00 -# IOPORT_5 (count=7) -00000070: 00 00 00 00 00 00 00 -# IOPINS0_5 (count=16) -00000077: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# IOPORT_6 (count=7) -00000087: 00 00 00 00 00 00 00 -# IOPINS0_6 (count=8) -0000008e: 00 0f 0f 00 00 00 00 00 -# IOPINS1_6 + 0x00000009 (count=5) -00000096: 00 00 00 00 00 -# IOPORT_7 (count=6) -0000009b: 00 00 00 00 00 00 -# IOPINS0_7 (count=16) -000000a1: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# IOPORT_8 (count=7) -000000b1: 00 00 00 00 40 00 00 -# IOPINS0_8 (count=10) -000000b8: 00 00 00 00 00 00 00 00 c0 00 -# IOPINS1_8 + 0x0000000B (count=5) -000000c2: 00 00 00 00 00 -# IDMUX_IRQ (count=8) -000000c7: 0a 00 00 00 00 00 00 00 -# CYDEV_SLOWCLK_ILO_CR0 (count=1) -000000cf: 06 -# CYDEV_FASTCLK_IMO_CR (count=1) -000000d0: 52 -# CYDEV_FASTCLK_PLL_P (count=2) -000000d1: 18 08 -# CYDEV_FASTCLK_PLL_CFG0 (count=2) -000000d3: 51 12 -# CYDEV_CLKDIST_MSTR0 (count=2) -000000d5: 00 01 -# CYDEV_CLKDIST_MSTR0 (count=1) -000000d7: 07 -# CYDEV_CLKDIST_BCFG0 (count=1) -000000d8: 00 -# CYDEV_CLKDIST_BCFG2 (count=1) -000000d9: 48 -# CYDEV_CLKDIST_MSTR0 (count=1) -000000da: 00 -# CYDEV_CLKDIST_UCFG (count=1) -000000db: 00 -# CYDEV_CLKDIST_LD (count=1) -000000dc: 02 -# PICU_8 (count=8) -000000dd: 00 00 00 00 00 00 02 00 -# UDB_1_5_0_CONFIG (count=128) -000000e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000000f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000105: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000115: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000125: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000135: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000145: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000155: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_5_1_CONFIG (count=128) -00000165: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000175: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000185: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000195: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_4_1_CONFIG (count=128) -000001e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000001f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000205: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000215: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000225: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000235: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000245: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000255: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_4_0_CONFIG (count=128) -00000265: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000275: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000285: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000295: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_3_0_CONFIG (count=128) -000002e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000002f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000305: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000315: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000325: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000335: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000345: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000355: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_3_1_CONFIG (count=128) -00000365: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000375: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000385: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000395: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000003a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000003b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000003c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000003d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_2_1_CONFIG (count=128) -000003e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000003f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000405: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000415: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000425: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000435: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000445: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000455: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_2_0_CONFIG (count=128) -00000465: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000475: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000485: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000495: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000004a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000004b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000004c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000004d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_2_1_CONFIG (count=128) -000004e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000004f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000505: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000515: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000525: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000535: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000545: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000555: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_2_0_CONFIG (count=128) -00000565: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000575: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000585: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000595: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000005a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000005b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000005c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000005d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_3_0_CONFIG (count=128) -000005e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000005f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000605: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000615: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000625: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000635: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000645: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000655: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_3_1_CONFIG (count=128) -00000665: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000675: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000685: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000695: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000006a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000006b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000006c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000006d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_4_1_CONFIG (count=128) -000006e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000006f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000705: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000715: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000725: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000735: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000745: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000755: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_4_0_CONFIG (count=128) -00000765: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000775: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000785: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000795: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000007a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000007b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000007c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000007d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_5_0_CONFIG (count=128) -000007e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000007f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000805: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000815: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000825: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000835: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000845: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000855: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_5_1_CONFIG (count=128) -00000865: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000875: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000885: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000895: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000008a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000008b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000008c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000008d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_0_0_CONFIG (count=128) -000008e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000008f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000905: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000915: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000925: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000935: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000945: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000955: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_0_1_CONFIG (count=128) -00000965: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000975: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000985: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000995: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_1_1_CONFIG (count=128) -000009e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000009f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_1_0_CONFIG (count=128) -00000a65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000a95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000aa5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ab5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ac5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ad5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_1_1_CONFIG (count=128) -00000ae5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000af5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_1_0_CONFIG (count=128) -00000b65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000b95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ba5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000bb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000bc5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000bd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_0_0_CONFIG (count=128) -00000be5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000bf5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_0_0_1_CONFIG (count=128) -00000c65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000c95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ca5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000cb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000cc5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000cd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UWRK_B0_WRK_DP_BITS (count=64) -00000ce5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000cf5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UWRK_B0_WRK_STATCTL_BITS + 0x00000070 (count=32) -00000d25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UWRK_B1_WRK_DP_BITS (count=64) -00000d45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UWRK_B1_WRK_STATCTL_BITS + 0x00000070 (count=32) -00000d85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000d95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UCFG_BCTL1 (count=16) -00000da5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UCFG_BCTL0 (count=16) -00000db5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_0_0 (count=128) -00000dc5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000dd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000de5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000df5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI0_0_HV_ROUTING + 0x00000080 (count=128) -00000e45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000e95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ea5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000eb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_0_1 (count=128) -00000ec5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ed5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ee5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ef5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI0_1_HV_ROUTING + 0x00000080 (count=128) -00000f45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f65: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 40 -00000f75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000f95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000fa5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000fb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_0_2 (count=128) -00000fc5: 00 00 00 00 00 00 00 00 08 00 00 00 00 00 00 40 -00000fd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000fe5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00000ff5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001005: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001015: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001025: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001035: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI0_2_HV_ROUTING + 0x00000080 (count=128) -00001045: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001055: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001065: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001075: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001085: 00 00 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001095: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000010a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000010b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_0_3 (count=128) -000010c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000010d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000010e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000010f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001105: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001115: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001125: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001135: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI0_3_HV_ROUTING + 0x00000080 (count=128) -00001145: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001155: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001165: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001175: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001185: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001195: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000011a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000011b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_0_4 (count=128) -000011c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000011d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000011e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000011f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001205: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001215: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001225: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001235: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI0_4_HV_ROUTING + 0x00000080 (count=128) -00001245: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001255: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001265: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001275: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001285: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001295: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000012a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000012b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_0_5 (count=128) -000012c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000012d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000012e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000012f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001305: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001315: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001325: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001335: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI0_5_HV_ROUTING + 0x00000080 (count=128) -00001345: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001355: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001365: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001375: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001385: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001395: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000013a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000013b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_0_0 (count=128) -000013c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000013d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000013e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000013f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001405: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001415: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001425: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001435: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_0_HV_ROUTING + 0x00000080 (count=128) -00001445: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001455: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001465: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001475: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001485: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001495: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_1_0 (count=128) -000014c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000014f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001505: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001515: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001525: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001535: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_2_0_HV_ROUTING + 0x00000080 (count=128) -00001545: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001555: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001565: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001575: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001585: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001595: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000015a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000015b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_0_1 (count=128) -000015c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000015d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000015e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000015f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001605: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001615: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001625: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001635: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_1_HV_ROUTING + 0x00000080 (count=128) -00001645: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001655: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001665: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001675: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001685: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001695: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000016a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 -000016b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_1_1 (count=128) -000016c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000016d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000016e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000016f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001705: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001715: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001725: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001735: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_2_1_HV_ROUTING + 0x00000080 (count=128) -00001745: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001755: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001765: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001775: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001785: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001795: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000017a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0a 00 -000017b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_0_2 (count=128) -000017c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000017d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000017e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000017f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001805: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001815: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001825: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001835: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_2_HV_ROUTING + 0x00000080 (count=128) -00001845: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001855: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001865: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001875: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001885: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001895: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000018a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000018b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_1_2 (count=128) -000018c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000018d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000018e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000018f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001905: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001915: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001925: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001935: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_2_2_HV_ROUTING + 0x00000080 (count=128) -00001945: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001955: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001965: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001975: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001985: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001995: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000019a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000019b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_0_3 (count=128) -000019c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000019d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000019e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000019f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_3_HV_ROUTING + 0x00000080 (count=128) -00001a45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001a95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001aa5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ab5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_1_3 (count=128) -00001ac5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ad5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ae5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001af5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_2_3_HV_ROUTING + 0x00000080 (count=128) -00001b45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001b95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ba5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001bb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_0_4 (count=128) -00001bc5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001bd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001be5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001bf5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_4_HV_ROUTING + 0x00000080 (count=128) -00001c45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001c95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ca5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001cb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_1_4 (count=128) -00001cc5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001cd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ce5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001cf5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_2_4_HV_ROUTING + 0x00000080 (count=128) -00001d45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001d95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001da5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001db5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_0_5 (count=128) -00001dc5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001dd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001de5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001df5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_1_5_HV_ROUTING + 0x00000080 (count=128) -00001e45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001e95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ea5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001eb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDBSWITCH_1_5 (count=128) -00001ec5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ed5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ee5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ef5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f05: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f35: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# UDB_2_5_HV_ROUTING + 0x00000080 (count=128) -00001f45: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f55: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f65: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f75: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f85: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001f95: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001fa5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001fb5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_1_0 (count=128) -00001fc5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001fd5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001fe5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00001ff5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002005: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002015: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002025: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002035: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI3_0_HV_ROUTING + 0x00000080 (count=128) -00002045: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002055: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002065: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002075: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002085: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002095: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000020a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000020b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_1_1 (count=128) -000020c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000020d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000020e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000020f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002105: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002115: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002125: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002135: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI3_1_HV_ROUTING + 0x00000080 (count=128) -00002145: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002155: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002165: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 80 -00002175: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002185: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002195: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000021a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50 00 -000021b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_1_2 (count=128) -000021c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000021d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000021e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000021f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002205: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002215: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002225: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002235: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI3_2_HV_ROUTING + 0x00000080 (count=128) -00002245: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002255: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002265: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 -00002275: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002285: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002295: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_1_3 (count=128) -000022c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000022f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002305: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002315: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002325: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002335: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI3_3_HV_ROUTING + 0x00000080 (count=128) -00002345: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002355: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002365: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 -00002375: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002385: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002395: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_1_4 (count=128) -000023c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000023f5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002405: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002415: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002425: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002435: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI3_4_HV_ROUTING + 0x00000080 (count=128) -00002445: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002455: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002465: 00 00 00 00 00 00 40 80 00 00 00 00 00 00 00 00 -00002475: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002485: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002495: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSISWITCH_1_5 (count=128) -000024c5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024d5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024e5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000024f5: 00 00 00 80 00 00 40 00 00 00 00 00 00 00 00 00 -00002505: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002515: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002525: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002535: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - -# DSI3_5_HV_ROUTING + 0x00000080 (count=128) -00002545: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002555: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002565: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002575: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00002585: 00 00 00 00 00 00 00 00 00 00 00 00 30 00 00 00 -00002595: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000025a5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -000025b5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cm3gcc.ld b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cm3gcc.ld deleted file mode 100755 index 6427452..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cm3gcc.ld +++ /dev/null @@ -1,295 +0,0 @@ -/* Linker script for ARM M-profile Simulator - * - * Version: Sourcery G++ Lite 2010q1-188 - * Support: https://support.codesourcery.com/GNUToolchain/ - * - * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. - * - * The authors hereby grant permission to use, copy, modify, distribute, - * and license this software and its documentation for any purpose, provided - * that existing copyright notices are retained in all copies and that this - * notice is included verbatim in any distributions. No written agreement, - * license, or royalty fee is required for any of the authorized uses. - * Modifications to this software may be copyrighted by their authors - * and need not follow the licensing terms described here, provided that - * the new terms are clearly indicated on the first page of each file where - * they apply. - */ -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -ENTRY(__cy_reset) -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) - - -MEMORY -{ - rom (rx) : ORIGIN = 0x0, LENGTH = 131072 - ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768 -} - - -CY_APPL_ORIGIN = 0; -CY_FLASH_ROW_SIZE = 256; -CY_ECC_ROW_SIZE = 32; -CY_EE_IN_BTLDR = 0x0; -CY_APPL_LOADABLE = 0; -CY_EE_SIZE = 2048; -CY_APPL_NUM = 1; -CY_APPL_MAX = 1; -CY_METADATA_SIZE = 64; - - -/* These force the linker to search for particular symbols from - * the start of the link process and thus ensure the user's - * overrides are picked up - */ -EXTERN(Reset) - -/* Bring in the interrupt routines & vector */ -EXTERN(main) - -/* Bring in the meta data */ -EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) -EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata) - -/* Provide fall-back values */ -PROVIDE(__cy_heap_start = _end); -PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); -PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); -PROVIDE(__cy_heap_end = __cy_stack - 0x2000); - - -SECTIONS -{ - /* The bootloader location */ - .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom - - /* Calculate where the loadables should start */ - appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); - appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); - appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; - ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; - ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; - ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; - PROVIDE(CY_ECC_OFFSET = ecc_offset); - - .text appl_start : - { - CREATE_OBJECT_SYMBOLS - PROVIDE(__cy_interrupt_vector = RomVectors); - - *(.romvectors) - - /* Make sure we pulled in an interrupt vector. */ - ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); - - ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); - - PROVIDE(__cy_reset = Reset); - *(.text.Reset) - /* Make sure we pulled in some reset code. */ - ASSERT (. != __cy_reset, "No reset code"); - - /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */ - *(.dma_init) - ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); - - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - *(.gnu.warning) - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) - - KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ - - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.gcc_except_table) - } >rom - .eh_frame_hdr : ALIGN (4) - { - KEEP (*(.eh_frame_hdr)) - } >rom - .eh_frame : ALIGN (4) - { - KEEP (*(.eh_frame)) - } >rom - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } >rom - __exidx_end = .; - .rodata : ALIGN (4) - { - *(.rodata .rodata.* .gnu.linkonce.r.*) - - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - __cy_regions = .; - LONG (__cy_region_init_ram) - LONG (__cy_region_start_data) - LONG (__cy_region_init_size_ram) - LONG (__cy_region_zero_size_ram) - __cy_regions_end = .; - - . = ALIGN (8); - _etext = .; - } >rom - - .ramvectors (NOLOAD) : ALIGN(8) - { - __cy_region_start_ram = .; - KEEP(*(.ramvectors)) - } - - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } - - .data : ALIGN(8) - { - __cy_region_start_data = .; - - KEEP(*(.jcr)) - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN (8); - *(.ram) - _edata = .; - } >ram AT>rom - .bss : ALIGN(8) - { - PROVIDE(__bss_start__ = .); - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - *(.ram.b) - _end = .; - __end = .; - } >ram AT>rom - PROVIDE(end = .); - PROVIDE(__bss_end__ = .); - - __cy_region_init_ram = LOADADDR (.data); - __cy_region_init_size_ram = _edata - ADDR (.data); - __cy_region_zero_size_ram = _end - _edata; - - /* The .stack and .heap sections don't contain any symbols. - * They are only used for linker to calculate RAM utilization. - */ - .heap (NOLOAD) : - { - . = _end; - . += 0x0800; - __cy_heap_limit = .; - } >ram - - .stack (__cy_stack - 0x2000) (NOLOAD) : - { - __cy_stack_limit = .; - . += 0x2000; - } >ram - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") - - .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) : - { - KEEP(*(.cyloadermeta)) - } :NONE - - .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) : - { - KEEP(*(.cyloadablemeta)) - } >rom - - .cyconfigecc (0x80000000 + ecc_offset) : - { - KEEP(*(.cyconfigecc)) - } :NONE - - .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE - .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE - - .cyeeprom (0x90200000 + ee_offset) : - { - KEEP(*(.cyeeprom)) - ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM"); - } :NONE - - .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE - - .stab 0 (NOLOAD) : { *(.stab) } - .stabstr 0 (NOLOAD) : { *(.stabstr) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. - */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* DWARF 2.1 */ - .debug_ranges 0 : { *(.debug_ranges) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } - .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) } -} - diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cm3.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cm3.h deleted file mode 100755 index 0e215fc..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cm3.h +++ /dev/null @@ -1,1627 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cm3_psoc5.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cm3_psoc5.h deleted file mode 100755 index a7c7be7..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cm3_psoc5.h +++ /dev/null @@ -1,54 +0,0 @@ -/******************************************************************************* -* File Name: core_cm3_psoc5.h -* Version 4.0 -* -* Description: -* Provides important type information for the PSoC5. This includes types -* necessary for core_cm3.h. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - - -#if !defined(__CORE_CM3_PSOC5_H__) -#define __CORE_CM3_PSOC5_H__ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ - /* Not relevant. All peripheral interrupts are defined by the user */ -} IRQn_Type; - -#include - -#define __CHECK_DEVICE_DEFINES - -#define __CM3_REV 0x0201 - -#define __MPU_PRESENT 0 -#define __NVIC_PRIO_BITS 3 -#define __Vendor_SysTickConfig 0 - -#include - - -#endif /* __CORE_CM3_PSOC5_H__ */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cmFunc.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cmFunc.h deleted file mode 100755 index 139bc3c..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cmFunc.h +++ /dev/null @@ -1,636 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cmInstr.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cmInstr.h deleted file mode 100755 index 0d75f40..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/core_cmInstr.h +++ /dev/null @@ -1,688 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyPm.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyPm.c deleted file mode 100755 index 01f0794..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyPm.c +++ /dev/null @@ -1,1819 +0,0 @@ -/******************************************************************************* -* File Name: cyPm.c -* Version 4.0 -* -* Description: -* Provides an API for the power management. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "cyPm.h" - - -/******************************************************************* -* Place your includes, defines and code here. Do not use merge -* region below unless any component datasheet suggest to do so. -*******************************************************************/ -/* `#START CY_PM_HEADER_INCLUDE` */ - -/* `#END` */ - - -static CY_PM_BACKUP_STRUCT cyPmBackup; -static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; - -/* Convertion table between register's values and frequency in MHz */ -static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; - -/* Function Prototypes */ -static void CyPmHibSaveSet(void); -static void CyPmHibRestore(void) ; - -static void CyPmHibSlpSaveSet(void) ; -static void CyPmHibSlpRestore(void) ; - -static void CyPmHviLviSaveDisable(void) ; -static void CyPmHviLviRestore(void) ; - - -/******************************************************************************* -* Function Name: CyPmSaveClocks -******************************************************************************** -* -* Summary: -* This function is called in preparation for entering sleep or hibernate low -* power modes. Saves all state of the clocking system that does not persist -* during sleep/hibernate or that needs to be altered in preparation for -* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the -* active power mode configuration. -* -* Switches the master clock over to the IMO and shuts down the PLL and MHz -* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the -* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. -* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state -* setting is saved and the Flash wait state setting is set for the current IMO -* speed. -* -* Note If the Master Clock source is routed through the DSI inputs, then it -* must be set manually to another source before using the -* CyPmSaveClocks()/CyPmRestoreClocks() functions. -* -* Parameters: -* None -* -* Return: -* None -* -* Side Effects: -* All peripheral clocks are going to be off after this API method call. -* -*******************************************************************************/ -void CyPmSaveClocks(void) -{ - /* Digital and analog clocks - save enable state and disable them all */ - cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; - cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; - CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); - CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); - - /* Save current flash wait cycles and set the maximum value */ - cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; - CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); - - /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ - cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; - - /* IMO doubler - save enable state */ - if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) - { - /* IMO doubler enabled - save and disable */ - cyPmClockBackup.imo2x = CY_PM_ENABLED; - } - else - { - /* IMO doubler disabled */ - cyPmClockBackup.imo2x = CY_PM_DISABLED; - } - - /* IMO - set appropriate frequency for LPM */ - CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); - - /* IMO - save enable state and enable without wait to settle */ - if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) - { - /* IMO - save enabled state */ - cyPmClockBackup.imoEnable = CY_PM_ENABLED; - } - else - { - /* IMO - save disabled state */ - cyPmClockBackup.imoEnable = CY_PM_DISABLED; - - /* IMO - enable */ - CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); - } - - /* IMO - save the current IMOCLK source and set to IMO if not yet */ - if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) - { - /* DSI or XTAL CLK */ - cyPmClockBackup.imoClkSrc = - (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL; - - /* IMO - set IMOCLK source to MHz OSC */ - CyIMO_SetSource(CY_IMO_SOURCE_IMO); - } - else - { - /* IMO */ - cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; - } - - /* Save clk_imo source */ - cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; - - /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ - if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) - { - /* Set IMOCLK to source for clk_imo */ - CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | - CY_PM_CLKDIST_IMO_OUT_IMO; - } /* Need to change nothing if IMOCLK is source clk_imo */ - - /* IMO doubler - disable it (saved above) */ - if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) - { - CyIMO_DisableDoubler(); - } - - /* Master clock - save divider and set it to divide-by-one (if no yet) */ - cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; - if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) - { - CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); - } /* Need to change nothing if master clock divider is 1 */ - - /* Master clock - save current source */ - cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; - - /* Master clock source - set it to IMO if not yet. */ - if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) - { - CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); - } /* Need to change nothing if master clock source is IMO */ - - /* Bus clock - save divider and set it, if needed, to divide-by-one */ - cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); - cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; - if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) - { - CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); - } /* Do nothing if saved and actual values are equal */ - - /* Set number of wait cycles for the flash according CPU frequency in MHz */ - CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); - - /* PLL - check enable state, disable if needed */ - if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) - { - /* PLL is enabled - save state and disable */ - cyPmClockBackup.pllEnableState = CY_PM_ENABLED; - CyPLL_OUT_Stop(); - } - else - { - /* PLL is disabled - save state */ - cyPmClockBackup.pllEnableState = CY_PM_DISABLED; - } - - /* MHz ECO - check enable state and disable if needed */ - if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) - { - /* MHz ECO is enabled - save state and disable */ - cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; - CyXTAL_Stop(); - } - else - { - /* MHz ECO is disabled - save state */ - cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; - } - - - /*************************************************************************** - * Save enable state of delay between the system bus clock and each of the - * 4 individual analog clocks. This bit non-retention and it's value should - * be restored on wakeup. - ***************************************************************************/ - if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) - { - cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; - } - else - { - cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; - } -} - - -/******************************************************************************* -* Function Name: CyPmRestoreClocks -******************************************************************************** -* -* Summary: -* Restores any state that was preserved by the last call to CyPmSaveClocks(). -* The Flash wait state setting is also restored. -* -* Note If the Master Clock source is routed through the DSI inputs, then it -* must be set manually to another source before using the -* CyPmSaveClocks()/CyPmRestoreClocks() functions. -* -* PSoC 3 and PSoC 5LP: -* The merge region could be used to process state when the megahertz crystal is -* not ready after the hold-off timeout. -* -* PSoC 5: -* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is -* not verified after the hold-off timeout. -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyPmRestoreClocks(void) -{ - cystatus status = CYRET_TIMEOUT; - uint16 i; - uint16 clkBusDivTmp; - - - /* Convertion table between CyIMO_SetFreq() parameters and register's value */ - const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { - CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, - CY_IMO_FREQ_48MHZ, 5u, 6u}; - - /* Restore enable state of delay between the system bus clock and ACLKs. */ - if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) - { - /* Delay for both the bandgap and the delay line to settle out */ - CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) * - CY_PM_GET_CPU_FREQ_MHZ); - - CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; - } - - /* MHz ECO restore state */ - if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) - { - /*********************************************************************** - * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait - * period uses FTW for period measurement. This could cause a problem - * if CTW/FTW is used as a wake up time in the low power modes APIs. - * So, the XTAL wait procedure is implemented with a software delay. - ***********************************************************************/ - - /* Enable XMHZ XTAL with no wait */ - (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); - - /* Read XERR bit to clear it */ - (void) CY_PM_FASTCLK_XMHZ_CSR_REG; - - /* Wait */ - for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) - { - /* Make a 200 microseconds delay */ - CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); - - /* High output indicates oscillator failure */ - if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) - { - status = CYRET_SUCCESS; - break; - } - } - - if(CYRET_TIMEOUT == status) - { - /******************************************************************* - * Process the situation when megahertz crystal is not ready. - * Time to stabialize value is crystal specific. - *******************************************************************/ - /* `#START_MHZ_ECO_TIMEOUT` */ - - /* `#END` */ - } - } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ - - - /* Temprorary set the maximum flash wait cycles */ - CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); - - /* The XTAL and DSI clocks are ready to be source for Master clock. */ - if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || - (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) - { - /* Restore Master clock's divider */ - if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) - { - /* Restore Master clock divider */ - CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); - } - - /* Restore Master clock source */ - CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); - } - - /* IMO - restore IMO frequency */ - if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && - (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) - { - /* Restore IMO frequency (24 MHz) and trim it for USB */ - CyIMO_SetFreq(CY_IMO_FREQ_USB); - } - else - { - /* Restore IMO frequency */ - CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); - - if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) - { - CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; - } - else - { - CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); - } - } - - /* IMO - restore enable state if needed */ - if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && - (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) - { - /* IMO - restore enabled state */ - CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); - } - - /* IMO - restore disable state if needed */ - if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && - (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) - { - CyIMO_Stop(); - } - - /* IMO - restore IMOCLK source */ - CyIMO_SetSource(cyPmClockBackup.imoClkSrc); - - /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ - if(CY_PM_ENABLED == cyPmClockBackup.imo2x) - { - CyIMO_EnableDoubler(); - } - - /* IMO - restore clk_imo source, if needed */ - if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) - { - CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | - cyPmClockBackup.clkImoSrc; - } - - /* PLL restore state */ - if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) - { - /*********************************************************************** - * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW - * for period measurement. This could cause a problem if CTW/FTW is used - * as a wakeup time in the low power modes APIs. To omit this issue PLL - * wait procedure is implemented with a software delay. - ***********************************************************************/ - - /* Enable PLL */ - (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); - - /* Make a 250 us delay */ - CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ); - } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ - - - /* PLL and IMO is ready to be source for Master clock */ - if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || - (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) - { - /* Restore Master clock divider */ - if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) - { - CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); - } - - /* Restore Master clock source */ - CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); - } - - /* Bus clock - restore divider, if needed */ - clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); - clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; - if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) - { - CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); - } - - /* Restore flash wait cycles */ - CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | - cyPmClockBackup.flashWaitCycles); - - /* Digital and analog clocks - restore state */ - CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; - CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; -} - - -/******************************************************************************* -* Function Name: CyPmAltAct -******************************************************************************** -* -* Summary: -* Puts the part into the Alternate Active (Standby) state. The Alternate Active -* state can allow for any of the capabilities of the device to be active, but -* the operation of this function is dependent on the CPU being disabled during -* the Alternate Active state. The configuration code and the component APIs -* will configure the template for the Alternate Active state to be the same as -* the Active state with the exception that the CPU will be disabled during -* Alternate Active. -* -* Note Before calling this function, you must manually configure the power mode -* of the source clocks for the timer that is used as the wakeup timer. -* -* PSoC 3: -* Before switching to Alternate Active, if a wakeupTime other than NONE is -* specified, then the appropriate timer state is configured as specified with -* the interrupt for that timer disabled. The wakeup source will be the -* combination of the values specified in the wakeupSource and any timer -* specified in the wakeupTime argument. Once the wakeup condition is -* satisfied, then all saved state is restored and the function returns in the -* Active state. -* -* Note that if the wakeupTime is made with a different value, the period before -* the wakeup occurs can be significantly shorter than the specified time. If -* the next call is made with the same wakeupTime value, then the wakeup will -* occur the specified period after the previous wakeup occurred. -* -* If a wakeupTime other than NONE is specified, then upon exit the state of the -* specified timer will be left as specified by wakeupTime with the timer -* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already -* configured for wakeup, for example with the SleepTimer or RTC components, -* then specify NONE for the wakeupTime and include the appropriate source for -* wakeupSource. -* -* PSoC 5LP: -* This function is used to both enter the Alternate Active mode and halt the -* processor. For PSoC 3 these two actions must be paired together. With PSoC -* 5LP the processor can be halted independently with the __WFI() function from -* the CMSIS library that is included in Creator. This function should be used -* instead when the action required is just to halt the processor until an -* enabled interrupt occurs. -* -* The wakeupTime parameter is not used for this device. It must be set to zero -* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a -* separate component: the CTW wakeup interval should be configured with the -* Sleep Timer component and one second interval should be configured with the -* RTC component. -* -* The wakeup behavior depends on wakeupSource parameter in the following -* manner: upon function execution the device will be switched from Active to -* Alternate Active mode and then the CPU will be halted. When an enabled wakeup -* event occurs the device will return to Active mode. Similarly when an -* enabled interrupt occurs the CPU will be started. These two actions will -* occur together provided that the event that occurs is an enabled wakeup -* source and also generates an interrupt. If just the wakeup event occurs then -* the device will be in Active mode, but the CPU will remain halted waiting for -* an interrupt. If an interrupt occurs from something other than a wakeup -* source, then the CPU will restart with the device in Alternate Active mode -* until a wakeup event occurs. -* -* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is -* called and PICU interrupt occurs, the CPU will be started and device will be -* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, -* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be -* started while device remains in Alternate Active mode. -* -* Parameters: -* wakeupTime: Specifies a timer wakeup source and the frequency of that -* source. For PSoC 5LP this parameter is ignored. -* -* Define Time -* PM_ALT_ACT_TIME_NONE None -* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second -* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms -* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms -* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms -* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms -* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms -* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms -* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms -* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms -* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms -* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms -* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms -* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms -* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms -* -* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that -* specifies how many increments of 10 us to delay. - For PSoC 3 silicon the valid range of values is 1 to 256. -* -* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if -* a wakeupTime has been specified the associated timer will be -* included as a wakeup source. -* -* Define Source -* PM_ALT_ACT_SRC_NONE None -* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 -* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 -* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 -* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 -* PM_ALT_ACT_SRC_INTERRUPT Interrupt -* PM_ALT_ACT_SRC_PICU PICU -* PM_ALT_ACT_SRC_I2C I2C -* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter -* PM_ALT_ACT_SRC_FTW Fast Timewheel* -* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* -* PM_ALT_ACT_SRC_CTW Central Timewheel** -* PM_ALT_ACT_SRC_ONE_PPS One PPS** -* PM_ALT_ACT_SRC_LCD LCD -* -* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. -* **Note: CTW and One PPS wakeup signals are in the same mask bit. -* -* When specifying a Comparator as the wakeupSource an instance specific define -* should be used that will track with the specific comparator that the instance -* is placed into. As an example, for a Comparator instance named MyComp the -* value to OR into the mask is: MyComp_ctComp__CMP_MASK. -* -* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() -* function must be called upon wakeup with corresponding parameter. Please -* refer to the CyPmReadStatus() API in the System Reference Guide for more -* information. -* -* Return: -* None -* -* Reentrant: -* No -* -* Side Effects: -* If a wakeupTime other than NONE is specified, then upon exit the state of the -* specified timer will be left as specified by wakeupTime with the timer -* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is -* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time) -* will be left started. -* -*******************************************************************************/ -void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) -{ - #if(CY_PSOC5) - - /* Arguments expected to be 0 */ - CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); - - if(0u != wakeupTime) - { - /* To remove unreferenced local variable warning */ - } - - #endif /* (CY_PSOC5) */ - - - #if(CY_PSOC3) - - /* FTW - save current and set new configuration */ - if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) - { - CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); - - /* Include associated timer to the wakeupSource */ - wakeupSource |= PM_ALT_ACT_SRC_FTW; - } - - /* CTW - save current and set new configuration */ - if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) - { - /* Save current CTW configuration and set new one */ - CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); - - /* Include associated timer to the wakeupSource */ - wakeupSource |= PM_ALT_ACT_SRC_CTW; - } - - /* 1PPS - save current and set new configuration */ - if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) - { - /* Save current 1PPS configuration and set new one */ - CyPmOppsSet(); - - /* Include associated timer to the wakeupSource */ - wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; - } - - #endif /* (CY_PSOC3) */ - - - /* Save and set new wake up configuration */ - - /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ - cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - - /* Comparators */ - cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - - /* LCD */ - cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - - - /* Switch to the Alternate Active mode */ - CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT); - - /* Recommended readback. */ - (void) CY_PM_MODE_CSR_REG; - - /* Two recommended NOPs to get into the mode. */ - CY_NOP; - CY_NOP; - - /* Execute WFI instruction (for ARM-based devices only) */ - CY_PM_WFI; - - /* Point of return from Alternate Active Mode */ - - /* Restore wake up configuration */ - CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; - CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; -} - - -/******************************************************************************* -* Function Name: CyPmSleep -******************************************************************************** -* -* Summary: -* Puts the part into the Sleep state. -* -* Note Before calling this function, you must manually configure the power -* mode of the source clocks for the timer that is used as wakeup timer. -* -* Note Before calling this function, you must prepare clock tree configuration -* for the low power mode by calling CyPmSaveClocks(). And restore clock -* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See -* Power Management section, Clock Configuration subsection of the System -* Reference Guide for more information. -* -* PSoC 3: -* Before switching to Sleep, if a wakeupTime other than NONE is specified, -* then the appropriate timer state is configured as specified with the -* interrupt for that timer disabled. The wakeup source will be the combination -* of the values specified in the wakeupSource and any timer specified in the -* wakeupTime argument. Once the wakeup condition is satisfied, then all saved -* state is restored and the function returns in the Active state. -* -* Note that if the wakeupTime is made with a different value, the period before -* the wakeup occurs can be significantly shorter than the specified time. If -* the next call is made with the same wakeupTime value, then the wakeup will -* occur the specified period after the previous wakeup occurred. -* -* If a wakeupTime other than NONE is specified, then upon exit the state of the -* specified timer will be left as specified by wakeupTime with the timer -* enabled and the interrupt disabled. If the CTW or One PPS is already -* configured for wakeup, for example with the SleepTimer or RTC components, -* then specify NONE for the wakeupTime and include the appropriate source for -* wakeupSource. -* -* PSoC 5LP: -* The wakeupTime parameter is not used and the only NONE can be specified. -* The wakeup time must be configured with the component, SleepTimer for CTW -* intervals and RTC for 1PPS interval. The component must be configured to -* generate an interrrupt. -* -* Parameters: -* wakeupTime: Specifies a timer wakeup source and the frequency of that -* source. For PSoC 5LP, this parameter is ignored. -* -* Define Time -* PM_SLEEP_TIME_NONE None -* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second -* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms -* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms -* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms -* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms -* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms -* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms -* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms -* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms -* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms -* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms -* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms -* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms -* -* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if -* a wakeupTime has been specified the associated timer will be -* included as a wakeup source. -* -* Define Source -* PM_SLEEP_SRC_NONE None -* PM_SLEEP_SRC_COMPARATOR0 Comparator 0 -* PM_SLEEP_SRC_COMPARATOR1 Comparator 1 -* PM_SLEEP_SRC_COMPARATOR2 Comparator 2 -* PM_SLEEP_SRC_COMPARATOR3 Comparator 3 -* PM_SLEEP_SRC_PICU PICU -* PM_SLEEP_SRC_I2C I2C -* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter -* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) -* PM_SLEEP_SRC_CTW Central Timewheel* -* PM_SLEEP_SRC_ONE_PPS One PPS* -* PM_SLEEP_SRC_LCD LCD -* -* *Note: CTW and One PPS wakeup signals are in the same mask bit. -* -* When specifying a Comparator as the wakeupSource an instance specific define -* should be used that will track with the specific comparator that the instance -* is placed into. As an example for a Comparator instance named MyComp the -* value to OR into the mask is: MyComp_ctComp__CMP_MASK. -* -* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() -* function must be called upon wakeup with corresponding parameter. Please -* refer to the CyPmReadStatus() API in the System Reference Guide for more -* information. -* -* Return: -* None -* -* Reentrant: -* No -* -* Side Effects and Restrictions: -* If a wakeupTime other than NONE is specified, then upon exit the state of the -* specified timer will be left as specified by wakeupTime with the timer -* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is -* used as wake up time) will be left started. -* -* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to -* measure Hibernate/Sleep regulator settling time after a reset. The holdoff -* delay is measured using rising edges of the 1 kHz ILO. -* -* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep -* power mode. It is disabled by PSoC Creator during startup. -* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out -* detect (power supply supervising capabilities) are required in a design -* during sleep, use the Central Time Wheel (CTW) to periodically wake the -* device, perform software buzz, and refresh the supervisory services. If LVI, -* HVI, or Brown Out is not required, then use of the CTW is not required. -* Refer to the device errata for more information. -* -*******************************************************************************/ -void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) -{ - uint8 interruptState; - - /* Save current global interrupt enable and disable it */ - interruptState = CyEnterCriticalSection(); - - - /*********************************************************************** - * The Hibernate/Sleep regulator has a settling time after a reset. - * During this time, the system ignores requests to enter Sleep and - * Hibernate modes. The holdoff delay is measured using rising edges of - * the 1 kHz ILO. - ***********************************************************************/ - if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) - { - /* Disable hold off - no action on restore */ - CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; - } - else - { - /* Abort, device is not ready for low power mode entry */ - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); - - return; - } - - - /*********************************************************************** - * PSoC3 < TO6: - * - Hardware buzz must be disabled before sleep mode entry. - * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must - * be aslo disabled. - * - * PSoC3 >= TO6: - * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be - * enabled before sleep mode entry and restored on wakeup. - ***********************************************************************/ - #if(CY_PSOC3) - - /* Silicon Revision ID is below TO6 */ - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* Hardware buzz expected to be disabled in Sleep mode */ - CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); - } - - - if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - { - if(CYDEV_CHIP_REV_ACTUAL < 5u) - { - /* LVI/HVI requires hardware buzz to be enabled */ - CYASSERT(0u != 0u); - } - else - { - if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)) - { - cyPmBackup.hardwareBuzz = CY_PM_DISABLED; - CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; - } - else - { - cyPmBackup.hardwareBuzz = CY_PM_ENABLED; - } - } - } - - #endif /* (CY_PSOC3) */ - - - /******************************************************************************* - * For ARM-based devices, an interrupt is required for the CPU to wake up. The - * Power Management implementation assumes that wakeup time is configured with a - * separate component (component-based wakeup time configuration) for an - * interrupt to be issued on terminal count. For more information, refer to the - * Wakeup Time Configuration section of System Reference Guide. - *******************************************************************************/ - #if(CY_PSOC5) - - /* Arguments expected to be 0 */ - CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); - - if(0u != wakeupTime) - { - /* To remove unreferenced local variable warning */ - } - - #endif /* (CY_PSOC5) */ - - - CyPmHibSlpSaveSet(); - - - #if(CY_PSOC3) - - /* CTW - save current and set new configuration */ - if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) - { - /* Save current and set new configuration of the CTW */ - CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); - - /* Include associated timer to the wakeupSource */ - wakeupSource |= PM_SLEEP_SRC_CTW; - } - - /* 1PPS - save current and set new configuration */ - if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) - { - /* Save current and set new configuration of the 1PPS */ - CyPmOppsSet(); - - /* Include associated timer to the wakeupSource */ - wakeupSource |= PM_SLEEP_SRC_ONE_PPS; - } - - #endif /* (CY_PSOC3) */ - - - /* Save and set new wake up configuration */ - - /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ - cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); - - /* Comparators */ - cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); - - /* LCD */ - cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); - - - /******************************************************************* - * Do not use merge region below unless any component datasheet - * suggest to do so. - *******************************************************************/ - /* `#START CY_PM_JUST_BEFORE_SLEEP` */ - - /* `#END` */ - - - /* Last moment IMO frequency change */ - if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) - { - /* IMO frequency is 12 MHz */ - cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; - } - else - { - /* IMO frequency is not 12 MHz */ - cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; - - /* Save IMO frequency */ - cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - - /* Set IMO frequency to 12 MHz */ - CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); - } - - /* Switch to the Sleep mode */ - CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP); - - /* Recommended readback. */ - (void) CY_PM_MODE_CSR_REG; - - /* Two recommended NOPs to get into the mode. */ - CY_NOP; - CY_NOP; - - /* Execute WFI instruction (for ARM-based devices only) */ - CY_PM_WFI; - - /* Point of return from Sleep Mode */ - - /* Restore last moment IMO frequency change */ - if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) - { - CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | - cyPmBackup.imoActFreq; - } - - - /******************************************************************* - * Do not use merge region below unless any component datasheet - * suggest to do so. - *******************************************************************/ - /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ - - /* `#END` */ - - - /* Restore hardware configuration */ - CyPmHibSlpRestore(); - - - /* Disable hardware buzz, if it was previously enabled */ - #if(CY_PSOC3) - - if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | - CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) - { - if(CYDEV_CHIP_REV_ACTUAL >= 5u) - { - if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz) - { - CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ); - } - } - } - - #endif /* (CY_PSOC3) */ - - - /* Restore current wake up configuration */ - CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; - CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: CyPmHibernate -******************************************************************************** -* -* Summary: -* Puts the part into the Hibernate state. -* -* PSoC 3 and PSoC 5LP: -* Before switching to Hibernate, the current status of the PICU wakeup source -* bit is saved and then set. This configures the device to wake up from the -* PICU. Make sure you have at least one pin configured to generate a PICU -* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls -* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." -* In the Pins component datasheet, this register is referred to as the IRQ -* option. Once the wakeup occurs, the PICU wakeup source bit is restored and -* the PSoC returns to the Active state. -* -* Parameters: -* None -* -* Return: -* None -* -* Reentrant: -* No -* -* Side Effects: -* Applications must wait 20 us before re-entering hibernate or sleep after -* waking up from hibernate. The 20 us allows the sleep regulator time to -* stabilize before the next hibernate / sleep event occurs. The 20 us -* requirement begins when the device wakes up. There is no hardware check that -* this requirement is met. The specified delay should be done on ISR entry. -* -* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is -* instance name of the Pins component) function must be called to clear the -* latched pin events to allow proper Hibernate mode entry andd to enable -* detection of future events. -* -* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to -* measure Hibernate/Sleep regulator settling time after a reset. The holdoff -* delay is measured using rising edges of the 1 kHz ILO. -* -*******************************************************************************/ -void CyPmHibernate(void) -{ - uint8 interruptState; - - /* Save current global interrupt enable and disable it */ - interruptState = CyEnterCriticalSection(); - - /*********************************************************************** - * The Hibernate/Sleep regulator has a settling time after a reset. - * During this time, the system ignores requests to enter Sleep and - * Hibernate modes. The holdoff delay is measured using rising edges of - * the 1 kHz ILO. - ***********************************************************************/ - if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) - { - /* Disable hold off - no action on restore */ - CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; - } - else - { - /* Abort, device is not ready for low power mode entry */ - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); - - return; - } - - CyPmHibSaveSet(); - - - /* Save and enable only wakeup on PICU */ - cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; - - cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - CY_PM_WAKEUP_CFG1_REG = 0x00u; - - cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; - CY_PM_WAKEUP_CFG2_REG = 0x00u; - - - /* Last moment IMO frequency change */ - if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) - { - /* IMO frequency is 12 MHz */ - cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; - } - else - { - /* IMO frequency is not 12 MHz */ - cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; - - /* Save IMO frequency */ - cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; - - /* Set IMO frequency to 12 MHz */ - CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); - } - - - /* Switch to Hibernate Mode */ - CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE; - - /* Recommended readback. */ - (void) CY_PM_MODE_CSR_REG; - - /* Two recommended NOPs to get into the mode. */ - CY_NOP; - CY_NOP; - - /* Execute WFI instruction (for ARM-based devices only) */ - CY_PM_WFI; - - - /* Point of return from Hibernate mode */ - - - /* Restore last moment IMO frequency change */ - if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) - { - CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | - cyPmBackup.imoActFreq; - } - - - /* Restore device for proper Hibernate mode exit*/ - CyPmHibRestore(); - - /* Restore current wake up configuration */ - CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; - CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; - CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; - - /* Restore global interrupt enable state */ - CyExitCriticalSection(interruptState); -} - - -/******************************************************************************* -* Function Name: CyPmReadStatus -******************************************************************************** -* -* Summary: -* Manages the Power Manager Interrupt Status Register. This register has the -* interrupt status for the one pulse per second, central timewheel and fast -* timewheel timers. This hardware register clears on read. To allow for only -* clearing the bits of interest and preserving the other bits, this function -* uses a shadow register that retains the state. This function reads the -* status register and ORs that value with the shadow register. That is the -* value that is returned. Then the bits in the mask that are set are cleared -* from this value and written back to the shadow register. -* -* Note You must call this function within 1 ms (1 clock cycle of the ILO) -* after a CTW event has occurred. -* -* Parameters: -* mask: Bits in the shadow register to clear. -* -* Define Source -* CY_PM_FTW_INT Fast Timewheel -* CY_PM_CTW_INT Central Timewheel -* CY_PM_ONEPPS_INT One Pulse Per Second -* -* Return: -* Status. Same bits values as the mask parameter. -* -*******************************************************************************/ -uint8 CyPmReadStatus(uint8 mask) -{ - static uint8 interruptStatus; - uint8 interruptState; - uint8 tmpStatus; - - /* Enter critical section */ - interruptState = CyEnterCriticalSection(); - - /* Save value of the register, copy it and clear desired bit */ - interruptStatus |= CY_PM_INT_SR_REG; - tmpStatus = interruptStatus; - interruptStatus &= ((uint8)(~mask)); - - /* Exit critical section */ - CyExitCriticalSection(interruptState); - - return(tmpStatus); -} - - -/******************************************************************************* -* Function Name: CyPmHibSaveSet -******************************************************************************** -* -* Summary: -* Prepare device for proper Hibernate low power mode entry: -* - Disables I2C backup regulator -* - Saves ILO power down mode state and enable it -* - Saves state of 1 kHz and 100 kHz ILO and disable them -* - Disables sleep regulator and shorts vccd to vpwrsleep -* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() -* - CyPmHibSlpSaveSet() function is called -* -* Parameters: -* None -* -* Return: -* None -* -* Reentrant: -* No -* -*******************************************************************************/ -static void CyPmHibSaveSet(void) -{ - /* I2C backup reg must be off when the sleep regulator is unavailable */ - if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) - { - /*********************************************************************** - * If I2C backup regulator is enabled, all the fixed-function registers - * store their values while device is in low power mode, otherwise their - * configuration is lost. The I2C API makes a decision to restore or not - * to restore I2C registers based on this. If this regulator will be - * disabled and then enabled, I2C API will suppose that I2C block - * registers preserved their values, while this is not true. So, the - * backup regulator is disabled. The I2C sleep APIs is responsible for - * restoration. - ***********************************************************************/ - - /* Disable I2C backup register */ - CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); - } - - - /* Save current ILO power mode and ensure low power mode */ - cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); - - /* Save current 1kHz ILO enable state. Disabled automatically. */ - cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? - CY_PM_DISABLED : CY_PM_ENABLED; - - /* Save current 100kHz ILO enable state. Disabled automatically. */ - cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? - CY_PM_DISABLED : CY_PM_ENABLED; - - - /* Disable the sleep regulator and shorts vccd to vpwrsleep */ - if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) - { - /* Save current bypass state */ - cyPmBackup.slpTrBypass = CY_PM_DISABLED; - CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; - } - else - { - cyPmBackup.slpTrBypass = CY_PM_ENABLED; - } - - /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ - - - /*************************************************************************** - * LVI/HVI must be disabled in Hibernate - ***************************************************************************/ - - /* Save LVI/HVI configuration and disable them */ - CyPmHviLviSaveDisable(); - - - /* Make the same preparations for Hibernate and Sleep modes */ - CyPmHibSlpSaveSet(); - - - /*************************************************************************** - * Save and set power mode wakeup trim registers - ***************************************************************************/ - cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; - cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; - - CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; - CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; -} - - -/******************************************************************************* -* Function Name: CyPmHibRestore -******************************************************************************** -* -* Summary: -* Restore device for proper Hibernate mode exit: -* - Restore LVI/HVI configuration - call CyPmHviLviRestore() -* - CyPmHibSlpSaveRestore() function is called -* - Restores ILO power down mode state and enable it -* - Restores state of 1 kHz and 100 kHz ILO and disable them -* - Restores sleep regulator settings -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -static void CyPmHibRestore(void) -{ - /* Restore LVI/HVI configuration */ - CyPmHviLviRestore(); - - /* Restore the same configuration for Hibernate and Sleep modes */ - CyPmHibSlpRestore(); - - /* Restore 1kHz ILO enable state */ - if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) - { - /* Enable 1kHz ILO */ - CyILO_Start1K(); - } - - /* Restore 100kHz ILO enable state */ - if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) - { - /* Enable 100kHz ILO */ - CyILO_Start100K(); - } - - /* Restore ILO power mode */ - (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); - - - if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) - { - /* Enable the sleep regulator */ - CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); - } - - - /*************************************************************************** - * Restore power mode wakeup trim registers - ***************************************************************************/ - CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; - CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; -} - - -/******************************************************************************* -* Function Name: CyPmCtwSetInterval -******************************************************************************** -* -* Summary: -* Performs CTW configuration: -* - Disables CTW interrupt -* - Enables 1 kHz ILO -* - Sets new CTW interval -* -* Parameters: -* ctwInterval: the CTW interval to be set. -* -* Return: -* None -* -* Side Effects: -* Enables ILO 1 KHz clock and leaves it enabled. -* -*******************************************************************************/ -void CyPmCtwSetInterval(uint8 ctwInterval) -{ - /* Disable CTW interrupt enable */ - CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); - - /* Enable 1kHz ILO (required for CTW operation) */ - CyILO_Start1K(); - - /* Interval could be set only while CTW is disabled */ - if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) - { - /* Set CTW interval if needed */ - if(CY_PM_TW_CFG1_REG != ctwInterval) - { - /* Disable the CTW, set new CTW interval and enable it again */ - CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); - CY_PM_TW_CFG1_REG = ctwInterval; - CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; - } /* Required interval is already set */ - } - else - { - /* Set CTW interval if needed */ - if(CY_PM_TW_CFG1_REG != ctwInterval) - { - /* Set the new CTW interval. Could be changed if CTW is disabled */ - CY_PM_TW_CFG1_REG = ctwInterval; - } /* Required interval is already set */ - - /* Enable the CTW */ - CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; - } -} - - -/******************************************************************************* -* Function Name: CyPmOppsSet -******************************************************************************** -* -* Summary: -* Performs 1PPS configuration: -* - Starts 32 KHz XTAL -* - Disables 1PPS interupts -* - Enables 1PPS -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -void CyPmOppsSet(void) -{ - /* Enable 32kHz XTAL if needed */ - if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) - { - /* Enable 32kHz XTAL */ - CyXTAL_32KHZ_Start(); - } - - /* Disable 1PPS interrupt enable */ - CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); - - /* Enable 1PPS operation */ - CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; -} - - -/******************************************************************************* -* Function Name: CyPmFtwSetInterval -******************************************************************************** -* -* Summary: -* Performs FTW configuration: -* - Disables FTW interrupt -* - Enables 100 kHz ILO -* - Sets new FTW interval. -* -* Parameters: -* ftwInterval - FTW counter interval. -* -* Return: -* None -* -* Side Effects: -* Enables ILO 100 KHz clock and leaves it enabled. -* -*******************************************************************************/ -void CyPmFtwSetInterval(uint8 ftwInterval) -{ - /* Disable FTW interrupt enable */ - CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); - - /* Enable 100kHz ILO */ - CyILO_Start100K(); - - /* Iterval could be set only while FTW is disabled */ - if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) - { - /* Disable FTW, set new FTW interval if needed and enable it again */ - if(CY_PM_TW_CFG0_REG != ftwInterval) - { - /* Disable the CTW, set new CTW interval and enable it again */ - CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); - CY_PM_TW_CFG0_REG = ftwInterval; - CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; - } /* Required interval is already set */ - } - else - { - /* Set new FTW counter interval if needed. FTW is disabled. */ - if(CY_PM_TW_CFG0_REG != ftwInterval) - { - /* Set the new CTW interval. Could be changed if CTW is disabled */ - CY_PM_TW_CFG0_REG = ftwInterval; - } /* Required interval is already set */ - - /* Enable the FTW */ - CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; - } -} - - -/******************************************************************************* -* Function Name: CyPmHibSlpSaveSet -******************************************************************************** -* -* Summary: -* This API is used for preparing device for Sleep and Hibernate low power -* modes entry: -* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5) -* - Saves SC/CT routing connections (PSoC 3/5/5LP) -* - Disables Serial Wire Viewer (SWV) (PSoC 3) -* - Save boost reference selection and set it to internal -* -* Parameters: -* None -* -* Return: -* None -* -* Reentrant: -* No -* -*******************************************************************************/ -static void CyPmHibSlpSaveSet(void) -{ - /* Save SC/CT routing registers */ - cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); - cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); - cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); - cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); - cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); - cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); - cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); - - cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); - cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); - cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); - cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); - cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); - cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); - cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); - - cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); - cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); - cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); - cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); - cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); - cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); - cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); - - cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); - cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); - cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); - cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); - cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); - cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); - cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); - - CY_SET_REG8(CYREG_SC0_SW0 , 0u); - CY_SET_REG8(CYREG_SC0_SW2 , 0u); - CY_SET_REG8(CYREG_SC0_SW3 , 0u); - CY_SET_REG8(CYREG_SC0_SW4 , 0u); - CY_SET_REG8(CYREG_SC0_SW6 , 0u); - CY_SET_REG8(CYREG_SC0_SW8 , 0u); - CY_SET_REG8(CYREG_SC0_SW10, 0u); - - CY_SET_REG8(CYREG_SC1_SW0 , 0u); - CY_SET_REG8(CYREG_SC1_SW2 , 0u); - CY_SET_REG8(CYREG_SC1_SW3 , 0u); - CY_SET_REG8(CYREG_SC1_SW4 , 0u); - CY_SET_REG8(CYREG_SC1_SW6 , 0u); - CY_SET_REG8(CYREG_SC1_SW8 , 0u); - CY_SET_REG8(CYREG_SC1_SW10, 0u); - - CY_SET_REG8(CYREG_SC2_SW0 , 0u); - CY_SET_REG8(CYREG_SC2_SW2 , 0u); - CY_SET_REG8(CYREG_SC2_SW3 , 0u); - CY_SET_REG8(CYREG_SC2_SW4 , 0u); - CY_SET_REG8(CYREG_SC2_SW6 , 0u); - CY_SET_REG8(CYREG_SC2_SW8 , 0u); - CY_SET_REG8(CYREG_SC2_SW10, 0u); - - CY_SET_REG8(CYREG_SC3_SW0 , 0u); - CY_SET_REG8(CYREG_SC3_SW2 , 0u); - CY_SET_REG8(CYREG_SC3_SW3 , 0u); - CY_SET_REG8(CYREG_SC3_SW4 , 0u); - CY_SET_REG8(CYREG_SC3_SW6 , 0u); - CY_SET_REG8(CYREG_SC3_SW8 , 0u); - CY_SET_REG8(CYREG_SC3_SW10, 0u); - - - #if(CY_PSOC3) - - /* Serial Wire Viewer (SWV) workaround */ - - /* Disable SWV before entering low power mode */ - if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) - { - /* Save SWV clock enabled state */ - cyPmBackup.swvClkEnabled = CY_PM_ENABLED; - - /* Save current ports drive mode settings */ - cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); - - /* Set drive mode to strong output */ - CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | - CY_PM_PRT1_PC3_DM_STRONG; - - /* Disable SWV clocks */ - CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); - } - else - { - /* Save SWV clock disabled state */ - cyPmBackup.swvClkEnabled = CY_PM_DISABLED; - } - - #endif /* (CY_PSOC3) */ - - - /*************************************************************************** - * Save boost reference and set it to boost's internal by clearing the bit. - * External (chip bandgap) reference is not available in Sleep and Hibernate. - ***************************************************************************/ - if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) - { - cyPmBackup.boostRefExt = CY_PM_ENABLED; - CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); - } - else - { - cyPmBackup.boostRefExt = CY_PM_DISABLED; - } -} - - -/******************************************************************************* -* Function Name: CyPmHibSlpRestore -******************************************************************************** -* -* Summary: -* This API is used for restoring device configurations after wakeup from Sleep -* and Hibernate low power modes: -* - Restores SC/CT routing connections -* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3) -* - Restore boost reference selection -* -* Parameters: -* None -* -* Return: -* None -* -*******************************************************************************/ -static void CyPmHibSlpRestore(void) -{ - /* Restore SC/CT routing registers */ - CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); - CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); - CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); - CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); - CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); - CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); - CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); - - CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); - CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); - CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); - CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); - CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); - CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); - CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); - - CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); - CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); - CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); - CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); - CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); - CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); - CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); - - CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); - CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); - CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); - CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); - CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); - CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); - CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); - - - #if(CY_PSOC3) - - /* Serial Wire Viewer (SWV) workaround */ - if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) - { - /* Restore ports drive mode */ - CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | - cyPmBackup.prt1Dm; - - /* Enable SWV clocks */ - CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; - } - - #endif /* (CY_PSOC3) */ - - - /* Restore boost reference */ - if(CY_PM_ENABLED == cyPmBackup.boostRefExt) - { - CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; - } -} - - -/******************************************************************************* -* Function Name: CyPmHviLviSaveDisable -******************************************************************************** -* -* Summary: -* Saves analog and digital LVI and HVI configuration and disables them. -* -* Parameters: -* None -* -* Return: -* None -* -* Reentrant: -* No -* -*******************************************************************************/ -static void CyPmHviLviSaveDisable(void) -{ - if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) - { - cyPmBackup.lvidEn = CY_PM_ENABLED; - cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; - - /* Save state of reset device at a specified Vddd threshold */ - cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ - CY_PM_DISABLED : CY_PM_ENABLED; - - CyVdLvDigitDisable(); - } - else - { - cyPmBackup.lvidEn = CY_PM_DISABLED; - } - - if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) - { - cyPmBackup.lviaEn = CY_PM_ENABLED; - cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; - - /* Save state of reset device at a specified Vdda threshold */ - cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ - CY_PM_DISABLED : CY_PM_ENABLED; - - CyVdLvAnalogDisable(); - } - else - { - cyPmBackup.lviaEn = CY_PM_DISABLED; - } - - if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) - { - cyPmBackup.hviaEn = CY_PM_ENABLED; - CyVdHvAnalogDisable(); - } - else - { - cyPmBackup.hviaEn = CY_PM_DISABLED; - } -} - - -/******************************************************************************* -* Function Name: CyPmHviLviRestore -******************************************************************************** -* -* Summary: -* Restores analog and digital LVI and HVI configuration. -* -* Parameters: -* None -* -* Return: -* None -* -* Reentrant: -* No -* -*******************************************************************************/ -static void CyPmHviLviRestore(void) -{ - /* Restore LVI/HVI configuration */ - if(CY_PM_ENABLED == cyPmBackup.lvidEn) - { - CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); - } - - if(CY_PM_ENABLED == cyPmBackup.lviaEn) - { - CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); - } - - if(CY_PM_ENABLED == cyPmBackup.hviaEn) - { - CyVdHvAnalogEnable(); - } -} - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyPm.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyPm.h deleted file mode 100755 index bfa2214..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyPm.h +++ /dev/null @@ -1,635 +0,0 @@ -/******************************************************************************* -* File Name: cyPm.h -* Version 4.0 -* -* Description: -* Provides the function definitions for the power management API. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOT_CYPM_H) -#define CY_BOOT_CYPM_H - -#include "cytypes.h" /* Register access API */ -#include "cydevice_trm.h" /* Registers addresses */ -#include "cyfitter.h" /* Comparators placement */ -#include "CyLib.h" /* Clock API */ -#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */ - - -/*************************************** -* Function Prototypes -***************************************/ -void CyPmSaveClocks(void) ; -void CyPmRestoreClocks(void) ; -void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; -void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; -void CyPmHibernate(void) ; - -uint8 CyPmReadStatus(uint8 mask) ; - -/* Internal APIs and are not meant to be called directly by the user */ -void CyPmCtwSetInterval(uint8 ctwInterval) ; -void CyPmFtwSetInterval(uint8 ftwInterval) ; -void CyPmOppsSet(void) ; - - -/*************************************** -* API Constants -***************************************/ - -#define PM_SLEEP_SRC_NONE (0x0000u) -#define PM_SLEEP_TIME_NONE (0x00u) -#define PM_ALT_ACT_SRC_NONE (0x0000u) -#define PM_ALT_ACT_TIME_NONE (0x0000u) - -#if(CY_PSOC3) - - /* Wake up time for the Sleep mode */ - #define PM_SLEEP_TIME_ONE_PPS (0x01u) - #define PM_SLEEP_TIME_CTW_2MS (0x02u) - #define PM_SLEEP_TIME_CTW_4MS (0x03u) - #define PM_SLEEP_TIME_CTW_8MS (0x04u) - #define PM_SLEEP_TIME_CTW_16MS (0x05u) - #define PM_SLEEP_TIME_CTW_32MS (0x06u) - #define PM_SLEEP_TIME_CTW_64MS (0x07u) - #define PM_SLEEP_TIME_CTW_128MS (0x08u) - #define PM_SLEEP_TIME_CTW_256MS (0x09u) - #define PM_SLEEP_TIME_CTW_512MS (0x0Au) - #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu) - #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu) - #define PM_SLEEP_TIME_CTW_4096MS (0x0Du) - - /* Difference between parameter's value and register's one */ - #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu) - - /* Wake up time for the Alternate Active mode */ - #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u) - #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u) - #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u) - #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u) - #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u) - #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u) - #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u) - #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u) - #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u) - #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au) - #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu) - #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu) - #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du) - #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT) - -#endif /* (CY_PSOC3) */ - - -/* Wake up sources for the Sleep mode */ -#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u) -#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u) -#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u) -#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u) -#define PM_SLEEP_SRC_PICU (0x0040u) -#define PM_SLEEP_SRC_I2C (0x0080u) -#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u) -#define PM_SLEEP_SRC_VD (0x0400u) -#define PM_SLEEP_SRC_CTW (0x0800u) -#define PM_SLEEP_SRC_ONE_PPS (0x0800u) -#define PM_SLEEP_SRC_LCD (0x1000u) - -/* Wake up sources for the Alternate Active mode */ -#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) -#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) -#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u) -#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u) -#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u) -#define PM_ALT_ACT_SRC_PICU (0x0040u) -#define PM_ALT_ACT_SRC_I2C (0x0080u) -#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u) -#define PM_ALT_ACT_SRC_FTW (0x0400u) -#define PM_ALT_ACT_SRC_VD (0x0400u) -#define PM_ALT_ACT_SRC_CTW (0x0800u) -#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u) -#define PM_ALT_ACT_SRC_LCD (0x1000u) - - -#define CY_PM_WAKEUP_PICU (0x04u) -#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u) -#define CY_PM_POWERDOWN_MODE (0x01u) -#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */ -#define CY_PM_ENABLED (0x01u) -#define CY_PM_DISABLED (0x00u) - -/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */ -#define CY_PM_PLL_OUT_NO_WAIT (0u) - -/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */ -#define CY_PM_XTAL_MHZ_NO_WAIT (0u) - -#define CY_PM_WAIT_200_US (200u) -#define CY_PM_WAIT_250_US (250u) -#define CY_PM_WAIT_20_US (20u) - -#define CY_PM_FREQ_3MHZ (3u) -#define CY_PM_FREQ_12MHZ (12u) -#define CY_PM_FREQ_48MHZ (48u) - - -#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u) - - -/* Delay line bandgap current settling time starting from a wakeup event */ -#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u) - -/* Delay line internal bias settling */ -#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u) - - -/* Max flash wait cycles for each device */ -#if(CY_PSOC3) - #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u) -#endif /* (CY_PSOC3) */ - -#if(CY_PSOC5) - #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* This marco is used to obtain the CPU frequency in MHz. It should be only used -* when the clock distribution system is prepared for the low power mode entry. -* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider -* and PSoC 3 devices have different placement of the CPU clock divider register -* bitfield. -*******************************************************************************/ -#if(CY_PSOC3) - #define CY_PM_GET_CPU_FREQ_MHZ \ - ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \ - ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u))) -#endif /* (CY_PSOC3) */ - -#if(CY_PSOC5) - - /* The CPU clock is directly derived from bus clock */ - #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) - -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low -* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI) -* instruction. The ARM compilers has __wfi() instristic that inserts a WFI -* instruction into the instruction stream generated by the compiler. The GCC -* compiler has to execute assembly language instruction. -*******************************************************************************/ -#if(CY_PSOC5) - - #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ - #define CY_PM_WFI __wfi() - #else /* ASM for GCC & IAR */ - #define CY_PM_WFI asm volatile ("WFI \n") - #endif /* (__ARMCC_VERSION) */ - -#else - - #define CY_PM_WFI CY_NOP - -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should -* be programmed manually for non PSoC 3 devices. -*******************************************************************************/ -#if(CY_PSOC3) - - #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT)) - -#endif /* (CY_PSOC3) */ - - -/******************************************************************************* -* This macro defines the IMO frequency that will be set by CyPmSaveClocks() -* function based on Enable Fast IMO during Startup option from the DWR file. -* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering -* low power mode and restore IMO back to the value set by CyPmSaveClocks() -* immediately on wakeup. -*******************************************************************************/ - -/* Enable Fast IMO during Startup - enabled */ -#if(1u == CYDEV_CONFIGURATION_IMOENABLED) - - /* IMO will be configured to 48 MHz */ - #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ) - -#else - - /* IMO will be configured to 12 MHz */ - #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ) - -#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */ - - -typedef struct cyPmClockBackupStruct -{ - /* CyPmSaveClocks()/CyPmRestoreClocks() */ - uint8 enClkA; /* Analog clocks enable */ - uint8 enClkD; /* Digital clocks enable */ - uint8 masterClkSrc; /* The Master clock source */ - uint8 imoFreq; /* IMO frequency (reg's value) */ - uint8 imoUsbClk; /* IMO USB CLK (reg's value) */ - uint8 flashWaitCycles; /* Flash wait cycles */ - uint8 imoEnable; /* IMO enable in Active mode */ - uint8 imoClkSrc; /* The IMO output */ - uint8 clkImoSrc; - uint8 imo2x; /* IMO doubler enable state */ - uint8 clkSyncDiv; /* Master clk divider */ - uint16 clkBusDiv; /* The clk_bus divider */ - uint8 pllEnableState; /* PLL enable state */ - uint8 xmhzEnableState; /* XM HZ enable state */ - uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */ - -} CY_PM_CLOCK_BACKUP_STRUCT; - - -typedef struct cyPmBackupStruct -{ - uint8 iloPowerMode; /* ILO power mode */ - uint8 ilo1kEnable; /* ILO 1K enable state */ - uint8 ilo100kEnable; /* ILO 100K enable state */ - - uint8 slpTrBypass; /* Sleep Trim Bypass */ - - #if(CY_PSOC3) - - uint8 swvClkEnabled; /* SWV clock enable state */ - uint8 prt1Dm; /* Ports drive mode configuration */ - uint8 hardwareBuzz; - - #endif /* (CY_PSOC3) */ - - uint8 wakeupCfg0; /* Wake up configuration 0 */ - uint8 wakeupCfg1; /* Wake up configuration 1 */ - uint8 wakeupCfg2; /* Wake up configuration 2 */ - - uint8 wakeupTrim0; - uint8 wakeupTrim1; - - uint8 scctData[28u]; /* SC/CT routing registers */ - - /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */ - uint8 lvidEn; - uint8 lvidTrip; - uint8 lviaEn; - uint8 lviaTrip; - uint8 hviaEn; - uint8 lvidRst; - uint8 lviaRst; - - uint8 imoActFreq; /* Last moment IMO change */ - uint8 imoActFreq12Mhz; /* 12 MHz or not */ - - uint8 boostRefExt; /* Boost reference selection */ - -} CY_PM_BACKUP_STRUCT; - - -/*************************************** -* Registers -***************************************/ - -/* Power Mode Wakeup Trim Register 1 */ -#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) -#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) - -/* Master clock Divider Value Register */ -#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 ) -#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 ) - -/* Master Clock Configuration Register/CPU Divider Value */ -#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 ) -#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 ) - -/* Clock distribution configuration Register */ -#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR ) -#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR ) - -/* CLK_BUS LSB Divider Value Register */ -#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 ) -#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 ) - -/* CLK_BUS MSB Divider Value Register */ -#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 ) -#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 ) - -/* CLK_BUS Configuration Register */ -#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 ) -#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 ) - -/* Power Mode Control/Status Register */ -#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR ) -#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR ) - -/* Power System Control Register 1 */ -#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 ) -#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 ) - -/* Power System Control Register 0 */ -#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 ) -#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 ) - -/* Internal Low-speed Oscillator Control Register 0 */ -#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) -#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) - -/* External 32kHz Crystal Oscillator Control Register */ -#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR ) -#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR ) - -#if(CY_PSOC3) - - /* MLOGIC Debug Register */ - #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG ) - #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG ) - - /* Port Pin Configuration Register */ - #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 ) - #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 ) - -#endif /* (CY_PSOC3) */ - - -/* Sleep Regulator Trim Register */ -#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR ) -#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR ) - - -/* Reset System Control Register */ -#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 ) -#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 ) - -/* Power Mode Wakeup Trim Register 0 */ -#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) -#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) - -#if(CY_PSOC3) - - /* Power Mode Wakeup Trim Register 2 */ - #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) - #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) - -#endif /* (CY_PSOC3) */ - -/* Power Manager Interrupt Status Register */ -#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR ) -#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR ) - -/* Active Power Mode Configuration Register 0 */ -#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) -#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) - -/* Active Power Mode Configuration Register 1 */ -#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 ) -#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 ) - -/* Active Power Mode Configuration Register 2 */ -#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 ) -#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 ) - -/* Boost Control 1 */ -#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 ) -#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 ) - -/* Timewheel Configuration Register 0 */ -#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 ) -#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 ) - -/* Timewheel Configuration Register 1 */ -#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 ) -#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 ) - -/* Timewheel Configuration Register 2 */ -#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 ) -#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 ) - -/* PLL Status Register */ -#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR ) -#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR ) - -/* Internal Main Oscillator Control Register */ -#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR ) -#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR ) - -/* PLL Configuration Register */ -#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) -#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) - -/* External 4-33 MHz Crystal Oscillator Status and Control Register */ -#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) -#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) - -/* Delay block Configuration Register */ -#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 ) -#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 ) - - -#if(CY_PSOC3) - - /* Cache Control Register */ - #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR ) - #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR ) - -#else /* Device is PSoC 5 */ - - /* Cache Control Register */ - #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) - #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) - -#endif /* (CY_PSOC3) */ - - -/* Power Mode Wakeup Mask Configuration Register 0 */ -#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 ) -#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 ) - -/* Power Mode Wakeup Mask Configuration Register 1 */ -#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 ) -#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 ) - -/* Power Mode Wakeup Mask Configuration Register 2 */ -#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 ) -#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 ) - -/* Boost Control 2 */ -#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 ) -#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 ) - - -/*************************************** -* Register Constants -***************************************/ - -/* Internal Main Oscillator Control Register */ - -#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */ -#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */ -#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */ -#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */ - -#define CY_PM_MASTER_CLK_SRC_IMO (0u) -#define CY_PM_MASTER_CLK_SRC_PLL (1u) -#define CY_PM_MASTER_CLK_SRC_XTAL (2u) -#define CY_PM_MASTER_CLK_SRC_DSI (3u) -#define CY_PM_MASTER_CLK_SRC_MASK (3u) - -#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */ -#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */ -#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */ -#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */ -#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */ -#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */ -#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */ -#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/ -#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */ - -#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */ -#define CY_PM_CTW_EN (0x04u) /* CTW enable */ -#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */ -#define CY_PM_FTW_EN (0x01u) /* FTW enable */ -#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */ -#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */ - - -#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu) -#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu) - -#define CY_PM_DIV_BY_ONE (0x00u) - -/* Internal Main Oscillator Control Register */ -#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u) - -/* Clock distribution configuration Register */ -#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u) -#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u) -#define CY_PM_CLKDIST_IMO2X_SRC (0x40u) - -/* Waiting for the hibernate/sleep regulator to stabilize */ -#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u) - -#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */ -#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */ -#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */ -#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */ -#define CY_PM_MODE_CSR_MASK (0x07u) - -/* I2C regulator backup enable */ -#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u) - -/* When set, prepares the system to disable the LDO-A */ -#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u) - -/* When set, disables the analog LDO regulator */ -#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u) - -#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u) - -#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */ -#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */ -#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */ - -/* Active Power Mode Configuration Register 0 */ -#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */ - -/* Cache Control Register (same mask for all device revisions) */ -#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u) - -/* Bus Clock divider to divide-by-one */ -#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u) - -/* HVI/LVI feature on the external analog and digital supply mask */ -#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u) - -/* The high-voltage-interrupt feature on the external analog supply */ -#define CY_PM_RESET_CR1_HVIA_EN (0x04u) - -/* The low-voltage-interrupt feature on the external analog supply */ -#define CY_PM_RESET_CR1_LVIA_EN (0x02u) - -/* The low-voltage-interrupt feature on the external digital supply */ -#define CY_PM_RESET_CR1_LVID_EN (0x01u) - -/* Allows the system to program delays on clk_sync_d */ -#define CY_PM_CLKDIST_DELAY_EN (0x04u) - - -#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu) - -/* Holdoff mask sleep trim */ -#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu) - -#if(CY_PSOC3) - - /* CPU clock divider mask */ - #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u) - - /* Serial Wire View (SWV) clock enable */ - #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u) - - /* Port drive mode */ - #define CY_PM_PRT1_PC3_DM_MASK (0xf1u) - - /* Mode 6, stong pull-up, strong pull-down */ - #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu) - - /* When set, enables buzz wakeups */ - #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u) - -#endif /* (CY_PSOC3) */ - - -/* Disable the sleep regulator and shorts vccd to vpwrsleep */ -#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u) - -/* Boost Control 2: Select external precision reference */ -#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) - -#if(CY_PSOC3) - - #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) - #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) - -#endif /* (CY_PSOC3) */ - -#if(CY_PSOC5) - - #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) - #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) - -#endif /* (CY_PSOC5) */ - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 -*******************************************************************************/ -#if(CY_PSOC3) - - /* Was removed as redundant */ - #define CY_PM_FTW_INTERVAL_MASK (0xFFu) - -#endif /* (CY_PSOC3) */ - -/* Was removed as redundant */ -#define CY_PM_CTW_INTERVAL_MASK (0x0Fu) - -#endif /* (CY_BOOT_CYPM_H) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h deleted file mode 100755 index 5f1b198..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice.h +++ /dev/null @@ -1,5360 +0,0 @@ -/******************************************************************************* -* FILENAME: cydevice.h -* OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.0 Component Pack 7 -* -* DESCRIPTION: -* This file provides all of the address values for the entire PSoC device. -* This file is automatically generated by PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#if !defined(CYDEVICE_H) -#define CYDEVICE_H -#define CYDEV_FLASH_BASE 0x00000000u -#define CYDEV_FLASH_SIZE 0x00020000u -#define CYDEV_FLASH_DATA_MBASE 0x00000000u -#define CYDEV_FLASH_DATA_MSIZE 0x00020000u -#define CYDEV_SRAM_BASE 0x1fffc000u -#define CYDEV_SRAM_SIZE 0x00008000u -#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u -#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u -#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u -#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u -#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u -#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u -#define CYDEV_SRAM_CODE_MBASE 0x1fffc000u -#define CYDEV_SRAM_CODE_MSIZE 0x00004000u -#define CYDEV_SRAM_DATA_MBASE 0x20000000u -#define CYDEV_SRAM_DATA_MSIZE 0x00004000u -#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u -#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u -#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u -#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u -#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u -#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u -#define CYDEV_DMA_BASE 0x20008000u -#define CYDEV_DMA_SIZE 0x00008000u -#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u -#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u -#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u -#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u -#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u -#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u -#define CYDEV_DMA_SRAM_MBASE 0x2000f000u -#define CYDEV_DMA_SRAM_MSIZE 0x00001000u -#define CYDEV_CLKDIST_BASE 0x40004000u -#define CYDEV_CLKDIST_SIZE 0x00000110u -#define CYDEV_CLKDIST_CR 0x40004000u -#define CYDEV_CLKDIST_LD 0x40004001u -#define CYDEV_CLKDIST_WRK0 0x40004002u -#define CYDEV_CLKDIST_WRK1 0x40004003u -#define CYDEV_CLKDIST_MSTR0 0x40004004u -#define CYDEV_CLKDIST_MSTR1 0x40004005u -#define CYDEV_CLKDIST_BCFG0 0x40004006u -#define CYDEV_CLKDIST_BCFG1 0x40004007u -#define CYDEV_CLKDIST_BCFG2 0x40004008u -#define CYDEV_CLKDIST_UCFG 0x40004009u -#define CYDEV_CLKDIST_DLY0 0x4000400au -#define CYDEV_CLKDIST_DLY1 0x4000400bu -#define CYDEV_CLKDIST_DMASK 0x40004010u -#define CYDEV_CLKDIST_AMASK 0x40004014u -#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u -#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u -#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u -#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u -#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u -#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u -#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u -#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u -#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u -#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u -#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u -#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au -#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu -#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu -#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du -#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu -#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u -#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u -#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u -#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u -#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u -#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u -#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u -#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u -#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u -#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u -#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u -#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au -#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu -#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u -#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu -#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du -#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu -#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u -#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u -#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u -#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u -#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u -#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u -#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u -#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u -#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u -#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u -#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u -#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u -#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u -#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u -#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u -#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u -#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au -#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu -#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu -#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u -#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu -#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du -#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu -#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu -#define CYDEV_FASTCLK_BASE 0x40004200u -#define CYDEV_FASTCLK_SIZE 0x00000026u -#define CYDEV_FASTCLK_IMO_BASE 0x40004200u -#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u -#define CYDEV_FASTCLK_IMO_CR 0x40004200u -#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u -#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u -#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u -#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u -#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u -#define CYDEV_FASTCLK_PLL_BASE 0x40004220u -#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u -#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u -#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u -#define CYDEV_FASTCLK_PLL_P 0x40004222u -#define CYDEV_FASTCLK_PLL_Q 0x40004223u -#define CYDEV_FASTCLK_PLL_SR 0x40004225u -#define CYDEV_SLOWCLK_BASE 0x40004300u -#define CYDEV_SLOWCLK_SIZE 0x0000000bu -#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u -#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u -#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u -#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u -#define CYDEV_SLOWCLK_X32_BASE 0x40004308u -#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u -#define CYDEV_SLOWCLK_X32_CR 0x40004308u -#define CYDEV_SLOWCLK_X32_CFG 0x40004309u -#define CYDEV_SLOWCLK_X32_TST 0x4000430au -#define CYDEV_BOOST_BASE 0x40004320u -#define CYDEV_BOOST_SIZE 0x00000007u -#define CYDEV_BOOST_CR0 0x40004320u -#define CYDEV_BOOST_CR1 0x40004321u -#define CYDEV_BOOST_CR2 0x40004322u -#define CYDEV_BOOST_CR3 0x40004323u -#define CYDEV_BOOST_SR 0x40004324u -#define CYDEV_BOOST_CR4 0x40004325u -#define CYDEV_BOOST_SR2 0x40004326u -#define CYDEV_PWRSYS_BASE 0x40004330u -#define CYDEV_PWRSYS_SIZE 0x00000002u -#define CYDEV_PWRSYS_CR0 0x40004330u -#define CYDEV_PWRSYS_CR1 0x40004331u -#define CYDEV_PM_BASE 0x40004380u -#define CYDEV_PM_SIZE 0x00000057u -#define CYDEV_PM_TW_CFG0 0x40004380u -#define CYDEV_PM_TW_CFG1 0x40004381u -#define CYDEV_PM_TW_CFG2 0x40004382u -#define CYDEV_PM_WDT_CFG 0x40004383u -#define CYDEV_PM_WDT_CR 0x40004384u -#define CYDEV_PM_INT_SR 0x40004390u -#define CYDEV_PM_MODE_CFG0 0x40004391u -#define CYDEV_PM_MODE_CFG1 0x40004392u -#define CYDEV_PM_MODE_CSR 0x40004393u -#define CYDEV_PM_USB_CR0 0x40004394u -#define CYDEV_PM_WAKEUP_CFG0 0x40004398u -#define CYDEV_PM_WAKEUP_CFG1 0x40004399u -#define CYDEV_PM_WAKEUP_CFG2 0x4000439au -#define CYDEV_PM_ACT_BASE 0x400043a0u -#define CYDEV_PM_ACT_SIZE 0x0000000eu -#define CYDEV_PM_ACT_CFG0 0x400043a0u -#define CYDEV_PM_ACT_CFG1 0x400043a1u -#define CYDEV_PM_ACT_CFG2 0x400043a2u -#define CYDEV_PM_ACT_CFG3 0x400043a3u -#define CYDEV_PM_ACT_CFG4 0x400043a4u -#define CYDEV_PM_ACT_CFG5 0x400043a5u -#define CYDEV_PM_ACT_CFG6 0x400043a6u -#define CYDEV_PM_ACT_CFG7 0x400043a7u -#define CYDEV_PM_ACT_CFG8 0x400043a8u -#define CYDEV_PM_ACT_CFG9 0x400043a9u -#define CYDEV_PM_ACT_CFG10 0x400043aau -#define CYDEV_PM_ACT_CFG11 0x400043abu -#define CYDEV_PM_ACT_CFG12 0x400043acu -#define CYDEV_PM_ACT_CFG13 0x400043adu -#define CYDEV_PM_STBY_BASE 0x400043b0u -#define CYDEV_PM_STBY_SIZE 0x0000000eu -#define CYDEV_PM_STBY_CFG0 0x400043b0u -#define CYDEV_PM_STBY_CFG1 0x400043b1u -#define CYDEV_PM_STBY_CFG2 0x400043b2u -#define CYDEV_PM_STBY_CFG3 0x400043b3u -#define CYDEV_PM_STBY_CFG4 0x400043b4u -#define CYDEV_PM_STBY_CFG5 0x400043b5u -#define CYDEV_PM_STBY_CFG6 0x400043b6u -#define CYDEV_PM_STBY_CFG7 0x400043b7u -#define CYDEV_PM_STBY_CFG8 0x400043b8u -#define CYDEV_PM_STBY_CFG9 0x400043b9u -#define CYDEV_PM_STBY_CFG10 0x400043bau -#define CYDEV_PM_STBY_CFG11 0x400043bbu -#define CYDEV_PM_STBY_CFG12 0x400043bcu -#define CYDEV_PM_STBY_CFG13 0x400043bdu -#define CYDEV_PM_AVAIL_BASE 0x400043c0u -#define CYDEV_PM_AVAIL_SIZE 0x00000017u -#define CYDEV_PM_AVAIL_CR0 0x400043c0u -#define CYDEV_PM_AVAIL_CR1 0x400043c1u -#define CYDEV_PM_AVAIL_CR2 0x400043c2u -#define CYDEV_PM_AVAIL_CR3 0x400043c3u -#define CYDEV_PM_AVAIL_CR4 0x400043c4u -#define CYDEV_PM_AVAIL_CR5 0x400043c5u -#define CYDEV_PM_AVAIL_CR6 0x400043c6u -#define CYDEV_PM_AVAIL_SR0 0x400043d0u -#define CYDEV_PM_AVAIL_SR1 0x400043d1u -#define CYDEV_PM_AVAIL_SR2 0x400043d2u -#define CYDEV_PM_AVAIL_SR3 0x400043d3u -#define CYDEV_PM_AVAIL_SR4 0x400043d4u -#define CYDEV_PM_AVAIL_SR5 0x400043d5u -#define CYDEV_PM_AVAIL_SR6 0x400043d6u -#define CYDEV_PICU_BASE 0x40004500u -#define CYDEV_PICU_SIZE 0x000000b0u -#define CYDEV_PICU_INTTYPE_BASE 0x40004500u -#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u -#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u -#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u -#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u -#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu -#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u -#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u -#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u -#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu -#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u -#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u -#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u -#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu -#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u -#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u -#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u -#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u -#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u -#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu -#define CYDEV_PICU_STAT_BASE 0x40004580u -#define CYDEV_PICU_STAT_SIZE 0x00000010u -#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u -#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u -#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u -#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u -#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u -#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u -#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u -#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u -#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u -#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u -#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u -#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u -#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u -#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u -#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu -#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu -#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu -#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u -#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu -#define CYDEV_PICU_SNAP_BASE 0x40004590u -#define CYDEV_PICU_SNAP_SIZE 0x00000010u -#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u -#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u -#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u -#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u -#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u -#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u -#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u -#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u -#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u -#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u -#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u -#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u -#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u -#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u -#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu -#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu -#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu -#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u -#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu -#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u -#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u -#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u -#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u -#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u -#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u -#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u -#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u -#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u -#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u -#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u -#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u -#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u -#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u -#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u -#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u -#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu -#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu -#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu -#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u -#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu -#define CYDEV_MFGCFG_BASE 0x40004600u -#define CYDEV_MFGCFG_SIZE 0x000000edu -#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u -#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u -#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u -#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u -#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u -#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u -#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au -#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au -#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu -#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u -#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u -#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u -#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u -#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u -#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u -#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u -#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u -#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u -#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u -#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u -#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u -#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u -#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u -#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u -#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u -#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u -#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u -#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u -#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u -#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u -#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u -#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u -#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u -#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u -#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u -#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u -#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u -#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u -#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u -#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u -#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u -#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu -#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u -#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u -#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u -#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u -#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u -#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u -#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au -#define CYDEV_MFGCFG_ILO_BASE 0x40004690u -#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u -#define CYDEV_MFGCFG_ILO_TR0 0x40004690u -#define CYDEV_MFGCFG_ILO_TR1 0x40004691u -#define CYDEV_MFGCFG_X32_BASE 0x40004698u -#define CYDEV_MFGCFG_X32_SIZE 0x00000001u -#define CYDEV_MFGCFG_X32_TR 0x40004698u -#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u -#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u -#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u -#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u -#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u -#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u -#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u -#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u -#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u -#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u -#define CYDEV_MFGCFG_DLY 0x400046c0u -#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u -#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du -#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u -#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u -#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u -#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u -#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u -#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau -#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu -#define CYDEV_RESET_BASE 0x400046f0u -#define CYDEV_RESET_SIZE 0x0000000fu -#define CYDEV_RESET_IPOR_CR0 0x400046f0u -#define CYDEV_RESET_IPOR_CR1 0x400046f1u -#define CYDEV_RESET_IPOR_CR2 0x400046f2u -#define CYDEV_RESET_IPOR_CR3 0x400046f3u -#define CYDEV_RESET_CR0 0x400046f4u -#define CYDEV_RESET_CR1 0x400046f5u -#define CYDEV_RESET_CR2 0x400046f6u -#define CYDEV_RESET_CR3 0x400046f7u -#define CYDEV_RESET_CR4 0x400046f8u -#define CYDEV_RESET_CR5 0x400046f9u -#define CYDEV_RESET_SR0 0x400046fau -#define CYDEV_RESET_SR1 0x400046fbu -#define CYDEV_RESET_SR2 0x400046fcu -#define CYDEV_RESET_SR3 0x400046fdu -#define CYDEV_RESET_TR 0x400046feu -#define CYDEV_SPC_BASE 0x40004700u -#define CYDEV_SPC_SIZE 0x00000100u -#define CYDEV_SPC_FM_EE_CR 0x40004700u -#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u -#define CYDEV_SPC_EE_SCR 0x40004702u -#define CYDEV_SPC_EE_ERR 0x40004703u -#define CYDEV_SPC_CPU_DATA 0x40004720u -#define CYDEV_SPC_DMA_DATA 0x40004721u -#define CYDEV_SPC_SR 0x40004722u -#define CYDEV_SPC_CR 0x40004723u -#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u -#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u -#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u -#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u -#define CYDEV_CACHE_BASE 0x40004800u -#define CYDEV_CACHE_SIZE 0x0000009cu -#define CYDEV_CACHE_CC_CTL 0x40004800u -#define CYDEV_CACHE_ECC_CORR 0x40004880u -#define CYDEV_CACHE_ECC_ERR 0x40004888u -#define CYDEV_CACHE_FLASH_ERR 0x40004890u -#define CYDEV_CACHE_HITMISS 0x40004898u -#define CYDEV_I2C_BASE 0x40004900u -#define CYDEV_I2C_SIZE 0x000000e1u -#define CYDEV_I2C_XCFG 0x400049c8u -#define CYDEV_I2C_ADR 0x400049cau -#define CYDEV_I2C_CFG 0x400049d6u -#define CYDEV_I2C_CSR 0x400049d7u -#define CYDEV_I2C_D 0x400049d8u -#define CYDEV_I2C_MCSR 0x400049d9u -#define CYDEV_I2C_CLK_DIV1 0x400049dbu -#define CYDEV_I2C_CLK_DIV2 0x400049dcu -#define CYDEV_I2C_TMOUT_CSR 0x400049ddu -#define CYDEV_I2C_TMOUT_SR 0x400049deu -#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu -#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u -#define CYDEV_DEC_BASE 0x40004e00u -#define CYDEV_DEC_SIZE 0x00000015u -#define CYDEV_DEC_CR 0x40004e00u -#define CYDEV_DEC_SR 0x40004e01u -#define CYDEV_DEC_SHIFT1 0x40004e02u -#define CYDEV_DEC_SHIFT2 0x40004e03u -#define CYDEV_DEC_DR2 0x40004e04u -#define CYDEV_DEC_DR2H 0x40004e05u -#define CYDEV_DEC_DR1 0x40004e06u -#define CYDEV_DEC_OCOR 0x40004e08u -#define CYDEV_DEC_OCORM 0x40004e09u -#define CYDEV_DEC_OCORH 0x40004e0au -#define CYDEV_DEC_GCOR 0x40004e0cu -#define CYDEV_DEC_GCORH 0x40004e0du -#define CYDEV_DEC_GVAL 0x40004e0eu -#define CYDEV_DEC_OUTSAMP 0x40004e10u -#define CYDEV_DEC_OUTSAMPM 0x40004e11u -#define CYDEV_DEC_OUTSAMPH 0x40004e12u -#define CYDEV_DEC_OUTSAMPS 0x40004e13u -#define CYDEV_DEC_COHER 0x40004e14u -#define CYDEV_TMR0_BASE 0x40004f00u -#define CYDEV_TMR0_SIZE 0x0000000cu -#define CYDEV_TMR0_CFG0 0x40004f00u -#define CYDEV_TMR0_CFG1 0x40004f01u -#define CYDEV_TMR0_CFG2 0x40004f02u -#define CYDEV_TMR0_SR0 0x40004f03u -#define CYDEV_TMR0_PER0 0x40004f04u -#define CYDEV_TMR0_PER1 0x40004f05u -#define CYDEV_TMR0_CNT_CMP0 0x40004f06u -#define CYDEV_TMR0_CNT_CMP1 0x40004f07u -#define CYDEV_TMR0_CAP0 0x40004f08u -#define CYDEV_TMR0_CAP1 0x40004f09u -#define CYDEV_TMR0_RT0 0x40004f0au -#define CYDEV_TMR0_RT1 0x40004f0bu -#define CYDEV_TMR1_BASE 0x40004f0cu -#define CYDEV_TMR1_SIZE 0x0000000cu -#define CYDEV_TMR1_CFG0 0x40004f0cu -#define CYDEV_TMR1_CFG1 0x40004f0du -#define CYDEV_TMR1_CFG2 0x40004f0eu -#define CYDEV_TMR1_SR0 0x40004f0fu -#define CYDEV_TMR1_PER0 0x40004f10u -#define CYDEV_TMR1_PER1 0x40004f11u -#define CYDEV_TMR1_CNT_CMP0 0x40004f12u -#define CYDEV_TMR1_CNT_CMP1 0x40004f13u -#define CYDEV_TMR1_CAP0 0x40004f14u -#define CYDEV_TMR1_CAP1 0x40004f15u -#define CYDEV_TMR1_RT0 0x40004f16u -#define CYDEV_TMR1_RT1 0x40004f17u -#define CYDEV_TMR2_BASE 0x40004f18u -#define CYDEV_TMR2_SIZE 0x0000000cu -#define CYDEV_TMR2_CFG0 0x40004f18u -#define CYDEV_TMR2_CFG1 0x40004f19u -#define CYDEV_TMR2_CFG2 0x40004f1au -#define CYDEV_TMR2_SR0 0x40004f1bu -#define CYDEV_TMR2_PER0 0x40004f1cu -#define CYDEV_TMR2_PER1 0x40004f1du -#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu -#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu -#define CYDEV_TMR2_CAP0 0x40004f20u -#define CYDEV_TMR2_CAP1 0x40004f21u -#define CYDEV_TMR2_RT0 0x40004f22u -#define CYDEV_TMR2_RT1 0x40004f23u -#define CYDEV_TMR3_BASE 0x40004f24u -#define CYDEV_TMR3_SIZE 0x0000000cu -#define CYDEV_TMR3_CFG0 0x40004f24u -#define CYDEV_TMR3_CFG1 0x40004f25u -#define CYDEV_TMR3_CFG2 0x40004f26u -#define CYDEV_TMR3_SR0 0x40004f27u -#define CYDEV_TMR3_PER0 0x40004f28u -#define CYDEV_TMR3_PER1 0x40004f29u -#define CYDEV_TMR3_CNT_CMP0 0x40004f2au -#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu -#define CYDEV_TMR3_CAP0 0x40004f2cu -#define CYDEV_TMR3_CAP1 0x40004f2du -#define CYDEV_TMR3_RT0 0x40004f2eu -#define CYDEV_TMR3_RT1 0x40004f2fu -#define CYDEV_IO_BASE 0x40005000u -#define CYDEV_IO_SIZE 0x00000200u -#define CYDEV_IO_PC_BASE 0x40005000u -#define CYDEV_IO_PC_SIZE 0x00000080u -#define CYDEV_IO_PC_PRT0_BASE 0x40005000u -#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT0_PC0 0x40005000u -#define CYDEV_IO_PC_PRT0_PC1 0x40005001u -#define CYDEV_IO_PC_PRT0_PC2 0x40005002u -#define CYDEV_IO_PC_PRT0_PC3 0x40005003u -#define CYDEV_IO_PC_PRT0_PC4 0x40005004u -#define CYDEV_IO_PC_PRT0_PC5 0x40005005u -#define CYDEV_IO_PC_PRT0_PC6 0x40005006u -#define CYDEV_IO_PC_PRT0_PC7 0x40005007u -#define CYDEV_IO_PC_PRT1_BASE 0x40005008u -#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT1_PC0 0x40005008u -#define CYDEV_IO_PC_PRT1_PC1 0x40005009u -#define CYDEV_IO_PC_PRT1_PC2 0x4000500au -#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu -#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu -#define CYDEV_IO_PC_PRT1_PC5 0x4000500du -#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu -#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu -#define CYDEV_IO_PC_PRT2_BASE 0x40005010u -#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT2_PC0 0x40005010u -#define CYDEV_IO_PC_PRT2_PC1 0x40005011u -#define CYDEV_IO_PC_PRT2_PC2 0x40005012u -#define CYDEV_IO_PC_PRT2_PC3 0x40005013u -#define CYDEV_IO_PC_PRT2_PC4 0x40005014u -#define CYDEV_IO_PC_PRT2_PC5 0x40005015u -#define CYDEV_IO_PC_PRT2_PC6 0x40005016u -#define CYDEV_IO_PC_PRT2_PC7 0x40005017u -#define CYDEV_IO_PC_PRT3_BASE 0x40005018u -#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT3_PC0 0x40005018u -#define CYDEV_IO_PC_PRT3_PC1 0x40005019u -#define CYDEV_IO_PC_PRT3_PC2 0x4000501au -#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu -#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu -#define CYDEV_IO_PC_PRT3_PC5 0x4000501du -#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu -#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu -#define CYDEV_IO_PC_PRT4_BASE 0x40005020u -#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT4_PC0 0x40005020u -#define CYDEV_IO_PC_PRT4_PC1 0x40005021u -#define CYDEV_IO_PC_PRT4_PC2 0x40005022u -#define CYDEV_IO_PC_PRT4_PC3 0x40005023u -#define CYDEV_IO_PC_PRT4_PC4 0x40005024u -#define CYDEV_IO_PC_PRT4_PC5 0x40005025u -#define CYDEV_IO_PC_PRT4_PC6 0x40005026u -#define CYDEV_IO_PC_PRT4_PC7 0x40005027u -#define CYDEV_IO_PC_PRT5_BASE 0x40005028u -#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT5_PC0 0x40005028u -#define CYDEV_IO_PC_PRT5_PC1 0x40005029u -#define CYDEV_IO_PC_PRT5_PC2 0x4000502au -#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu -#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu -#define CYDEV_IO_PC_PRT5_PC5 0x4000502du -#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu -#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu -#define CYDEV_IO_PC_PRT6_BASE 0x40005030u -#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT6_PC0 0x40005030u -#define CYDEV_IO_PC_PRT6_PC1 0x40005031u -#define CYDEV_IO_PC_PRT6_PC2 0x40005032u -#define CYDEV_IO_PC_PRT6_PC3 0x40005033u -#define CYDEV_IO_PC_PRT6_PC4 0x40005034u -#define CYDEV_IO_PC_PRT6_PC5 0x40005035u -#define CYDEV_IO_PC_PRT6_PC6 0x40005036u -#define CYDEV_IO_PC_PRT6_PC7 0x40005037u -#define CYDEV_IO_PC_PRT12_BASE 0x40005060u -#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u -#define CYDEV_IO_PC_PRT12_PC0 0x40005060u -#define CYDEV_IO_PC_PRT12_PC1 0x40005061u -#define CYDEV_IO_PC_PRT12_PC2 0x40005062u -#define CYDEV_IO_PC_PRT12_PC3 0x40005063u -#define CYDEV_IO_PC_PRT12_PC4 0x40005064u -#define CYDEV_IO_PC_PRT12_PC5 0x40005065u -#define CYDEV_IO_PC_PRT12_PC6 0x40005066u -#define CYDEV_IO_PC_PRT12_PC7 0x40005067u -#define CYDEV_IO_PC_PRT15_BASE 0x40005078u -#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u -#define CYDEV_IO_PC_PRT15_PC0 0x40005078u -#define CYDEV_IO_PC_PRT15_PC1 0x40005079u -#define CYDEV_IO_PC_PRT15_PC2 0x4000507au -#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu -#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu -#define CYDEV_IO_PC_PRT15_PC5 0x4000507du -#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu -#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u -#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu -#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu -#define CYDEV_IO_DR_BASE 0x40005080u -#define CYDEV_IO_DR_SIZE 0x00000010u -#define CYDEV_IO_DR_PRT0_BASE 0x40005080u -#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u -#define CYDEV_IO_DR_PRT1_BASE 0x40005081u -#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u -#define CYDEV_IO_DR_PRT2_BASE 0x40005082u -#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u -#define CYDEV_IO_DR_PRT3_BASE 0x40005083u -#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u -#define CYDEV_IO_DR_PRT4_BASE 0x40005084u -#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u -#define CYDEV_IO_DR_PRT5_BASE 0x40005085u -#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u -#define CYDEV_IO_DR_PRT6_BASE 0x40005086u -#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u -#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu -#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu -#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu -#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u -#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu -#define CYDEV_IO_PS_BASE 0x40005090u -#define CYDEV_IO_PS_SIZE 0x00000010u -#define CYDEV_IO_PS_PRT0_BASE 0x40005090u -#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u -#define CYDEV_IO_PS_PRT1_BASE 0x40005091u -#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u -#define CYDEV_IO_PS_PRT2_BASE 0x40005092u -#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u -#define CYDEV_IO_PS_PRT3_BASE 0x40005093u -#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u -#define CYDEV_IO_PS_PRT4_BASE 0x40005094u -#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u -#define CYDEV_IO_PS_PRT5_BASE 0x40005095u -#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u -#define CYDEV_IO_PS_PRT6_BASE 0x40005096u -#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u -#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu -#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu -#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu -#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u -#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu -#define CYDEV_IO_PRT_BASE 0x40005100u -#define CYDEV_IO_PRT_SIZE 0x00000100u -#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u -#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT0_DR 0x40005100u -#define CYDEV_IO_PRT_PRT0_PS 0x40005101u -#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u -#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u -#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u -#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u -#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u -#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u -#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u -#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u -#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au -#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu -#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu -#define CYDEV_IO_PRT_PRT0_AG 0x4000510du -#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu -#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu -#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u -#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT1_DR 0x40005110u -#define CYDEV_IO_PRT_PRT1_PS 0x40005111u -#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u -#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u -#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u -#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u -#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u -#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u -#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u -#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u -#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au -#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu -#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu -#define CYDEV_IO_PRT_PRT1_AG 0x4000511du -#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu -#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu -#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u -#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT2_DR 0x40005120u -#define CYDEV_IO_PRT_PRT2_PS 0x40005121u -#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u -#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u -#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u -#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u -#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u -#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u -#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u -#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u -#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au -#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu -#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu -#define CYDEV_IO_PRT_PRT2_AG 0x4000512du -#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu -#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu -#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u -#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT3_DR 0x40005130u -#define CYDEV_IO_PRT_PRT3_PS 0x40005131u -#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u -#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u -#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u -#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u -#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u -#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u -#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u -#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u -#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au -#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu -#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu -#define CYDEV_IO_PRT_PRT3_AG 0x4000513du -#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu -#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu -#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u -#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT4_DR 0x40005140u -#define CYDEV_IO_PRT_PRT4_PS 0x40005141u -#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u -#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u -#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u -#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u -#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u -#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u -#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u -#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u -#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au -#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu -#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu -#define CYDEV_IO_PRT_PRT4_AG 0x4000514du -#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu -#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu -#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u -#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT5_DR 0x40005150u -#define CYDEV_IO_PRT_PRT5_PS 0x40005151u -#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u -#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u -#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u -#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u -#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u -#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u -#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u -#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u -#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au -#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu -#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu -#define CYDEV_IO_PRT_PRT5_AG 0x4000515du -#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu -#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu -#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u -#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT6_DR 0x40005160u -#define CYDEV_IO_PRT_PRT6_PS 0x40005161u -#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u -#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u -#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u -#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u -#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u -#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u -#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u -#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u -#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au -#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu -#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu -#define CYDEV_IO_PRT_PRT6_AG 0x4000516du -#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu -#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu -#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u -#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u -#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u -#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u -#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u -#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u -#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u -#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u -#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u -#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u -#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u -#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau -#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu -#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu -#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu -#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu -#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu -#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u -#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u -#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u -#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u -#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u -#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u -#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u -#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u -#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u -#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u -#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u -#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u -#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau -#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu -#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu -#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu -#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu -#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu -#define CYDEV_PRTDSI_BASE 0x40005200u -#define CYDEV_PRTDSI_SIZE 0x0000007fu -#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u -#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u -#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u -#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u -#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u -#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u -#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u -#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u -#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u -#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u -#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u -#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au -#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu -#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu -#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du -#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu -#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u -#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u -#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u -#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u -#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u -#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u -#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u -#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u -#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u -#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u -#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u -#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au -#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu -#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu -#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du -#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu -#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u -#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u -#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u -#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u -#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u -#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u -#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u -#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u -#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u -#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u -#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u -#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au -#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu -#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu -#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du -#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu -#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u -#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u -#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u -#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u -#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u -#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u -#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u -#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u -#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u -#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u -#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u -#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u -#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u -#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u -#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u -#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u -#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u -#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u -#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u -#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u -#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au -#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu -#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu -#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du -#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu -#define CYDEV_EMIF_BASE 0x40005400u -#define CYDEV_EMIF_SIZE 0x00000007u -#define CYDEV_EMIF_NO_UDB 0x40005400u -#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u -#define CYDEV_EMIF_MEM_DWN 0x40005402u -#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u -#define CYDEV_EMIF_CLOCK_EN 0x40005404u -#define CYDEV_EMIF_EM_TYPE 0x40005405u -#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u -#define CYDEV_ANAIF_BASE 0x40005800u -#define CYDEV_ANAIF_SIZE 0x000003a9u -#define CYDEV_ANAIF_CFG_BASE 0x40005800u -#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu -#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u -#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u -#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u -#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u -#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u -#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u -#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u -#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u -#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u -#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u -#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u -#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au -#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu -#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu -#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du -#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu -#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u -#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u -#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u -#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u -#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u -#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u -#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u -#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u -#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u -#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u -#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u -#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au -#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu -#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u -#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu -#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du -#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu -#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u -#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u -#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u -#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u -#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u -#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u -#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u -#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u -#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u -#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u -#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u -#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u -#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u -#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u -#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u -#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au -#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au -#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu -#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu -#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu -#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du -#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu -#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu -#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu -#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u -#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u -#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u -#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au -#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au -#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu -#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu -#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu -#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du -#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu -#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu -#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu -#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u -#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u -#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u -#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au -#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u -#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au -#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu -#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u -#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu -#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu -#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u -#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu -#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du -#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu -#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu -#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u -#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u -#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u -#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u -#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u -#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u -#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u -#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u -#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u -#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u -#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u -#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u -#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au -#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u -#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au -#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu -#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu -#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u -#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu -#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u -#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u -#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u -#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u -#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u -#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u -#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u -#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u -#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u -#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u -#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u -#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u -#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au -#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu -#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu -#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du -#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu -#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu -#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u -#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u -#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u -#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u -#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u -#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u -#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u -#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u -#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u -#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u -#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au -#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu -#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu -#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du -#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu -#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu -#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u -#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u -#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u -#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u -#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u -#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u -#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u -#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u -#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u -#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u -#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u -#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u -#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u -#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au -#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu -#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu -#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du -#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu -#define CYDEV_ANAIF_RT_BASE 0x40005a00u -#define CYDEV_ANAIF_RT_SIZE 0x00000162u -#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u -#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du -#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u -#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u -#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u -#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u -#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u -#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u -#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u -#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au -#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu -#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu -#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u -#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du -#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u -#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u -#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u -#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u -#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u -#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u -#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u -#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au -#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu -#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu -#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u -#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du -#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u -#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u -#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u -#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u -#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u -#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u -#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u -#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au -#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu -#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu -#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u -#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du -#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u -#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u -#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u -#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u -#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u -#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u -#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u -#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au -#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu -#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu -#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u -#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u -#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u -#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u -#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u -#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u -#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u -#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u -#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au -#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu -#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu -#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu -#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u -#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u -#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u -#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u -#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u -#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u -#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u -#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u -#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au -#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu -#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu -#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu -#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u -#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u -#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u -#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u -#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u -#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u -#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u -#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u -#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u -#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau -#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu -#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu -#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu -#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu -#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u -#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u -#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u -#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u -#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u -#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u -#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u -#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u -#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u -#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau -#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu -#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu -#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu -#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu -#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u -#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u -#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u -#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u -#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u -#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u -#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u -#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u -#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u -#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u -#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u -#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u -#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u -#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u -#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u -#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u -#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u -#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au -#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu -#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu -#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu -#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu -#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u -#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u -#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u -#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u -#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u -#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u -#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u -#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u -#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u -#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u -#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u -#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u -#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u -#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u -#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u -#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u -#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u -#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u -#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u -#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u -#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u -#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u -#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u -#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u -#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u -#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u -#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u -#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u -#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u -#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au -#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu -#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu -#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u -#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu -#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du -#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu -#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu -#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u -#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u -#define CYDEV_ANAIF_WRK_BASE 0x40005b80u -#define CYDEV_ANAIF_WRK_SIZE 0x00000029u -#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u -#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u -#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u -#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u -#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u -#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u -#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u -#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u -#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u -#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u -#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u -#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u -#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u -#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u -#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u -#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u -#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u -#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u -#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u -#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u -#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u -#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u -#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u -#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u -#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u -#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u -#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u -#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u -#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u -#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u -#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u -#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au -#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu -#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu -#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u -#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u -#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u -#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u -#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u -#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u -#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u -#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u -#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u -#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u -#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u -#define CYDEV_USB_BASE 0x40006000u -#define CYDEV_USB_SIZE 0x00000300u -#define CYDEV_USB_EP0_DR0 0x40006000u -#define CYDEV_USB_EP0_DR1 0x40006001u -#define CYDEV_USB_EP0_DR2 0x40006002u -#define CYDEV_USB_EP0_DR3 0x40006003u -#define CYDEV_USB_EP0_DR4 0x40006004u -#define CYDEV_USB_EP0_DR5 0x40006005u -#define CYDEV_USB_EP0_DR6 0x40006006u -#define CYDEV_USB_EP0_DR7 0x40006007u -#define CYDEV_USB_CR0 0x40006008u -#define CYDEV_USB_CR1 0x40006009u -#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au -#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu -#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu -#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu -#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du -#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu -#define CYDEV_USB_USBIO_CR0 0x40006010u -#define CYDEV_USB_USBIO_CR1 0x40006012u -#define CYDEV_USB_DYN_RECONFIG 0x40006014u -#define CYDEV_USB_SOF0 0x40006018u -#define CYDEV_USB_SOF1 0x40006019u -#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu -#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu -#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du -#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu -#define CYDEV_USB_EP0_CR 0x40006028u -#define CYDEV_USB_EP0_CNT 0x40006029u -#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu -#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu -#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du -#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu -#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu -#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu -#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du -#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu -#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu -#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu -#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du -#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu -#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu -#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu -#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du -#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu -#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu -#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu -#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du -#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu -#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu -#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u -#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu -#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du -#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu -#define CYDEV_USB_ARB_EP1_BASE 0x40006080u -#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP1_CFG 0x40006080u -#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u -#define CYDEV_USB_ARB_EP1_SR 0x40006082u -#define CYDEV_USB_ARB_RW1_BASE 0x40006084u -#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW1_WA 0x40006084u -#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u -#define CYDEV_USB_ARB_RW1_RA 0x40006086u -#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u -#define CYDEV_USB_ARB_RW1_DR 0x40006088u -#define CYDEV_USB_BUF_SIZE 0x4000608cu -#define CYDEV_USB_EP_ACTIVE 0x4000608eu -#define CYDEV_USB_EP_TYPE 0x4000608fu -#define CYDEV_USB_ARB_EP2_BASE 0x40006090u -#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP2_CFG 0x40006090u -#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u -#define CYDEV_USB_ARB_EP2_SR 0x40006092u -#define CYDEV_USB_ARB_RW2_BASE 0x40006094u -#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW2_WA 0x40006094u -#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u -#define CYDEV_USB_ARB_RW2_RA 0x40006096u -#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u -#define CYDEV_USB_ARB_RW2_DR 0x40006098u -#define CYDEV_USB_ARB_CFG 0x4000609cu -#define CYDEV_USB_USB_CLK_EN 0x4000609du -#define CYDEV_USB_ARB_INT_EN 0x4000609eu -#define CYDEV_USB_ARB_INT_SR 0x4000609fu -#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u -#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u -#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u -#define CYDEV_USB_ARB_EP3_SR 0x400060a2u -#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u -#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW3_WA 0x400060a4u -#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u -#define CYDEV_USB_ARB_RW3_RA 0x400060a6u -#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u -#define CYDEV_USB_ARB_RW3_DR 0x400060a8u -#define CYDEV_USB_CWA 0x400060acu -#define CYDEV_USB_CWA_MSB 0x400060adu -#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u -#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u -#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u -#define CYDEV_USB_ARB_EP4_SR 0x400060b2u -#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u -#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW4_WA 0x400060b4u -#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u -#define CYDEV_USB_ARB_RW4_RA 0x400060b6u -#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u -#define CYDEV_USB_ARB_RW4_DR 0x400060b8u -#define CYDEV_USB_DMA_THRES 0x400060bcu -#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu -#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u -#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u -#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u -#define CYDEV_USB_ARB_EP5_SR 0x400060c2u -#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u -#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW5_WA 0x400060c4u -#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u -#define CYDEV_USB_ARB_RW5_RA 0x400060c6u -#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u -#define CYDEV_USB_ARB_RW5_DR 0x400060c8u -#define CYDEV_USB_BUS_RST_CNT 0x400060ccu -#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u -#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u -#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u -#define CYDEV_USB_ARB_EP6_SR 0x400060d2u -#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u -#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW6_WA 0x400060d4u -#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u -#define CYDEV_USB_ARB_RW6_RA 0x400060d6u -#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u -#define CYDEV_USB_ARB_RW6_DR 0x400060d8u -#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u -#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u -#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u -#define CYDEV_USB_ARB_EP7_SR 0x400060e2u -#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u -#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW7_WA 0x400060e4u -#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u -#define CYDEV_USB_ARB_RW7_RA 0x400060e6u -#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u -#define CYDEV_USB_ARB_RW7_DR 0x400060e8u -#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u -#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u -#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u -#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u -#define CYDEV_USB_ARB_EP8_SR 0x400060f2u -#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u -#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u -#define CYDEV_USB_ARB_RW8_WA 0x400060f4u -#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u -#define CYDEV_USB_ARB_RW8_RA 0x400060f6u -#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u -#define CYDEV_USB_ARB_RW8_DR 0x400060f8u -#define CYDEV_USB_MEM_BASE 0x40006100u -#define CYDEV_USB_MEM_SIZE 0x00000200u -#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u -#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u -#define CYDEV_UWRK_BASE 0x40006400u -#define CYDEV_UWRK_SIZE 0x00000b60u -#define CYDEV_UWRK_UWRK8_BASE 0x40006400u -#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u -#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u -#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u -#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u -#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u -#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u -#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u -#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u -#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u -#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u -#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u -#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u -#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u -#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au -#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du -#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u -#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u -#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u -#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u -#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u -#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u -#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u -#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u -#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u -#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u -#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au -#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du -#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u -#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u -#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u -#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u -#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u -#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u -#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u -#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u -#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u -#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u -#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au -#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du -#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u -#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u -#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u -#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u -#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u -#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u -#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u -#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u -#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u -#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u -#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au -#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du -#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u -#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u -#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u -#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u -#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u -#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u -#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u -#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u -#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u -#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u -#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au -#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du -#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u -#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u -#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u -#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u -#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u -#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u -#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u -#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u -#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u -#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u -#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au -#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du -#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u -#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u -#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u -#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u -#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u -#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u -#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u -#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u -#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u -#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u -#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au -#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du -#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u -#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u -#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u -#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u -#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u -#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u -#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u -#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u -#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u -#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u -#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au -#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du -#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u -#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u -#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u -#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u -#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u -#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u -#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u -#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u -#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u -#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u -#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au -#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du -#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u -#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u -#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u -#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u -#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u -#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u -#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u -#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u -#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u -#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u -#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au -#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu -#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu -#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du -#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu -#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu -#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u -#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u -#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u -#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u -#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u -#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u -#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u -#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u -#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u -#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u -#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau -#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu -#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu -#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu -#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu -#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu -#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u -#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u -#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u -#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u -#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u -#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u -#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u -#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u -#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au -#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u -#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u -#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u -#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u -#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u -#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u -#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au -#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u -#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u -#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u -#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u -#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u -#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u -#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au -#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u -#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u -#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u -#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u -#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u -#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u -#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au -#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u -#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u -#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u -#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u -#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u -#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u -#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au -#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u -#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u -#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u -#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u -#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u -#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u -#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au -#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u -#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u -#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u -#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u -#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u -#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u -#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au -#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u -#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u -#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u -#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u -#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u -#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u -#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au -#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u -#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u -#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u -#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u -#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u -#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u -#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au -#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u -#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u -#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u -#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u -#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u -#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u -#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au -#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu -#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u -#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u -#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u -#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u -#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u -#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u -#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau -#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu -#define CYDEV_UWRK_UWRK16_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u -#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u -#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu -#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u -#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u -#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu -#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu -#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u -#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u -#define CYDEV_PHUB_BASE 0x40007000u -#define CYDEV_PHUB_SIZE 0x00000c00u -#define CYDEV_PHUB_CFG 0x40007000u -#define CYDEV_PHUB_ERR 0x40007004u -#define CYDEV_PHUB_ERR_ADR 0x40007008u -#define CYDEV_PHUB_CH0_BASE 0x40007010u -#define CYDEV_PHUB_CH0_SIZE 0x0000000cu -#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u -#define CYDEV_PHUB_CH0_ACTION 0x40007014u -#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u -#define CYDEV_PHUB_CH1_BASE 0x40007020u -#define CYDEV_PHUB_CH1_SIZE 0x0000000cu -#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u -#define CYDEV_PHUB_CH1_ACTION 0x40007024u -#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u -#define CYDEV_PHUB_CH2_BASE 0x40007030u -#define CYDEV_PHUB_CH2_SIZE 0x0000000cu -#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u -#define CYDEV_PHUB_CH2_ACTION 0x40007034u -#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u -#define CYDEV_PHUB_CH3_BASE 0x40007040u -#define CYDEV_PHUB_CH3_SIZE 0x0000000cu -#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u -#define CYDEV_PHUB_CH3_ACTION 0x40007044u -#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u -#define CYDEV_PHUB_CH4_BASE 0x40007050u -#define CYDEV_PHUB_CH4_SIZE 0x0000000cu -#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u -#define CYDEV_PHUB_CH4_ACTION 0x40007054u -#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u -#define CYDEV_PHUB_CH5_BASE 0x40007060u -#define CYDEV_PHUB_CH5_SIZE 0x0000000cu -#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u -#define CYDEV_PHUB_CH5_ACTION 0x40007064u -#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u -#define CYDEV_PHUB_CH6_BASE 0x40007070u -#define CYDEV_PHUB_CH6_SIZE 0x0000000cu -#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u -#define CYDEV_PHUB_CH6_ACTION 0x40007074u -#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u -#define CYDEV_PHUB_CH7_BASE 0x40007080u -#define CYDEV_PHUB_CH7_SIZE 0x0000000cu -#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u -#define CYDEV_PHUB_CH7_ACTION 0x40007084u -#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u -#define CYDEV_PHUB_CH8_BASE 0x40007090u -#define CYDEV_PHUB_CH8_SIZE 0x0000000cu -#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u -#define CYDEV_PHUB_CH8_ACTION 0x40007094u -#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u -#define CYDEV_PHUB_CH9_BASE 0x400070a0u -#define CYDEV_PHUB_CH9_SIZE 0x0000000cu -#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u -#define CYDEV_PHUB_CH9_ACTION 0x400070a4u -#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u -#define CYDEV_PHUB_CH10_BASE 0x400070b0u -#define CYDEV_PHUB_CH10_SIZE 0x0000000cu -#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u -#define CYDEV_PHUB_CH10_ACTION 0x400070b4u -#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u -#define CYDEV_PHUB_CH11_BASE 0x400070c0u -#define CYDEV_PHUB_CH11_SIZE 0x0000000cu -#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u -#define CYDEV_PHUB_CH11_ACTION 0x400070c4u -#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u -#define CYDEV_PHUB_CH12_BASE 0x400070d0u -#define CYDEV_PHUB_CH12_SIZE 0x0000000cu -#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u -#define CYDEV_PHUB_CH12_ACTION 0x400070d4u -#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u -#define CYDEV_PHUB_CH13_BASE 0x400070e0u -#define CYDEV_PHUB_CH13_SIZE 0x0000000cu -#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u -#define CYDEV_PHUB_CH13_ACTION 0x400070e4u -#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u -#define CYDEV_PHUB_CH14_BASE 0x400070f0u -#define CYDEV_PHUB_CH14_SIZE 0x0000000cu -#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u -#define CYDEV_PHUB_CH14_ACTION 0x400070f4u -#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u -#define CYDEV_PHUB_CH15_BASE 0x40007100u -#define CYDEV_PHUB_CH15_SIZE 0x0000000cu -#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u -#define CYDEV_PHUB_CH15_ACTION 0x40007104u -#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u -#define CYDEV_PHUB_CH16_BASE 0x40007110u -#define CYDEV_PHUB_CH16_SIZE 0x0000000cu -#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u -#define CYDEV_PHUB_CH16_ACTION 0x40007114u -#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u -#define CYDEV_PHUB_CH17_BASE 0x40007120u -#define CYDEV_PHUB_CH17_SIZE 0x0000000cu -#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u -#define CYDEV_PHUB_CH17_ACTION 0x40007124u -#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u -#define CYDEV_PHUB_CH18_BASE 0x40007130u -#define CYDEV_PHUB_CH18_SIZE 0x0000000cu -#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u -#define CYDEV_PHUB_CH18_ACTION 0x40007134u -#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u -#define CYDEV_PHUB_CH19_BASE 0x40007140u -#define CYDEV_PHUB_CH19_SIZE 0x0000000cu -#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u -#define CYDEV_PHUB_CH19_ACTION 0x40007144u -#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u -#define CYDEV_PHUB_CH20_BASE 0x40007150u -#define CYDEV_PHUB_CH20_SIZE 0x0000000cu -#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u -#define CYDEV_PHUB_CH20_ACTION 0x40007154u -#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u -#define CYDEV_PHUB_CH21_BASE 0x40007160u -#define CYDEV_PHUB_CH21_SIZE 0x0000000cu -#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u -#define CYDEV_PHUB_CH21_ACTION 0x40007164u -#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u -#define CYDEV_PHUB_CH22_BASE 0x40007170u -#define CYDEV_PHUB_CH22_SIZE 0x0000000cu -#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u -#define CYDEV_PHUB_CH22_ACTION 0x40007174u -#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u -#define CYDEV_PHUB_CH23_BASE 0x40007180u -#define CYDEV_PHUB_CH23_SIZE 0x0000000cu -#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u -#define CYDEV_PHUB_CH23_ACTION 0x40007184u -#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u -#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u -#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u -#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u -#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u -#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u -#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu -#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u -#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u -#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u -#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u -#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u -#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu -#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u -#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u -#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u -#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u -#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u -#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu -#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u -#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u -#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u -#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u -#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u -#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu -#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u -#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u -#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u -#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u -#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u -#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu -#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u -#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u -#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u -#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u -#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u -#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu -#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u -#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u -#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u -#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u -#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u -#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu -#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u -#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u -#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u -#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u -#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u -#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu -#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u -#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u -#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u -#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u -#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u -#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu -#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u -#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u -#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u -#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u -#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u -#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu -#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u -#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u -#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u -#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u -#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u -#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu -#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u -#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u -#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u -#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u -#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u -#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u -#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu -#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u -#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u -#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u -#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u -#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u -#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu -#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u -#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u -#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u -#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u -#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u -#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu -#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u -#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u -#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u -#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u -#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u -#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu -#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u -#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u -#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u -#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u -#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u -#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu -#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u -#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u -#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u -#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u -#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u -#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu -#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u -#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u -#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u -#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u -#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u -#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu -#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u -#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u -#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u -#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u -#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u -#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu -#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u -#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u -#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u -#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u -#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u -#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu -#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u -#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u -#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u -#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u -#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u -#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu -#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u -#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u -#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u -#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u -#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u -#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu -#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u -#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u -#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u -#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u -#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u -#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu -#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u -#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u -#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u -#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u -#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u -#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu -#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u -#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u -#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u -#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u -#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u -#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu -#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u -#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u -#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u -#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u -#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u -#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu -#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u -#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u -#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u -#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u -#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u -#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu -#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u -#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u -#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u -#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u -#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u -#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu -#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u -#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u -#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u -#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u -#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u -#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu -#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u -#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u -#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u -#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u -#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u -#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu -#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u -#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u -#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u -#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u -#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u -#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu -#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u -#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u -#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u -#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u -#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u -#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu -#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u -#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u -#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u -#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u -#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u -#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu -#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u -#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u -#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u -#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u -#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u -#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu -#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u -#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u -#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u -#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u -#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u -#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu -#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u -#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u -#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u -#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u -#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u -#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu -#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u -#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u -#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u -#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u -#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u -#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu -#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u -#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u -#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u -#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u -#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u -#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu -#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u -#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u -#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u -#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u -#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u -#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu -#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u -#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u -#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u -#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u -#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u -#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu -#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u -#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u -#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u -#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u -#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u -#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu -#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u -#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u -#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u -#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u -#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u -#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu -#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u -#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u -#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u -#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u -#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u -#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu -#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u -#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u -#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u -#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u -#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u -#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu -#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u -#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u -#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u -#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u -#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u -#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu -#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u -#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u -#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u -#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u -#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u -#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu -#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u -#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u -#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u -#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u -#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u -#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu -#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u -#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u -#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u -#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u -#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u -#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu -#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u -#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u -#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u -#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u -#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u -#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu -#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u -#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u -#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u -#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u -#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u -#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu -#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u -#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u -#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u -#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u -#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u -#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu -#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u -#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u -#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u -#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u -#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u -#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu -#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u -#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u -#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u -#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u -#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u -#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu -#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u -#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u -#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u -#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u -#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u -#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu -#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u -#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u -#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u -#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u -#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u -#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu -#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u -#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u -#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u -#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u -#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u -#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu -#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u -#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u -#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u -#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u -#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u -#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu -#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u -#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u -#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u -#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u -#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u -#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu -#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u -#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u -#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u -#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u -#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u -#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu -#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u -#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u -#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u -#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u -#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u -#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu -#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u -#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u -#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u -#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u -#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u -#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu -#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u -#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u -#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u -#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u -#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u -#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu -#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u -#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u -#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u -#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u -#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u -#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu -#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u -#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u -#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u -#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u -#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u -#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu -#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u -#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u -#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u -#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u -#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u -#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu -#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u -#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u -#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u -#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u -#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u -#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu -#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u -#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u -#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u -#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u -#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u -#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu -#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u -#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u -#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u -#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u -#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u -#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu -#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u -#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u -#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u -#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u -#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u -#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu -#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u -#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u -#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u -#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u -#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u -#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu -#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u -#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u -#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u -#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u -#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u -#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu -#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u -#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u -#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u -#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u -#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u -#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu -#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u -#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u -#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u -#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u -#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u -#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu -#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u -#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u -#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u -#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u -#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u -#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu -#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u -#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u -#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u -#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u -#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u -#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu -#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u -#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u -#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u -#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u -#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u -#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u -#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu -#define CYDEV_EE_BASE 0x40008000u -#define CYDEV_EE_SIZE 0x00000800u -#define CYDEV_EE_DATA_MBASE 0x40008000u -#define CYDEV_EE_DATA_MSIZE 0x00000800u -#define CYDEV_CAN0_BASE 0x4000a000u -#define CYDEV_CAN0_SIZE 0x000002a0u -#define CYDEV_CAN0_CSR_BASE 0x4000a000u -#define CYDEV_CAN0_CSR_SIZE 0x00000018u -#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u -#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u -#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u -#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu -#define CYDEV_CAN0_CSR_CMD 0x4000a010u -#define CYDEV_CAN0_CSR_CFG 0x4000a014u -#define CYDEV_CAN0_TX0_BASE 0x4000a020u -#define CYDEV_CAN0_TX0_SIZE 0x00000010u -#define CYDEV_CAN0_TX0_CMD 0x4000a020u -#define CYDEV_CAN0_TX0_ID 0x4000a024u -#define CYDEV_CAN0_TX0_DH 0x4000a028u -#define CYDEV_CAN0_TX0_DL 0x4000a02cu -#define CYDEV_CAN0_TX1_BASE 0x4000a030u -#define CYDEV_CAN0_TX1_SIZE 0x00000010u -#define CYDEV_CAN0_TX1_CMD 0x4000a030u -#define CYDEV_CAN0_TX1_ID 0x4000a034u -#define CYDEV_CAN0_TX1_DH 0x4000a038u -#define CYDEV_CAN0_TX1_DL 0x4000a03cu -#define CYDEV_CAN0_TX2_BASE 0x4000a040u -#define CYDEV_CAN0_TX2_SIZE 0x00000010u -#define CYDEV_CAN0_TX2_CMD 0x4000a040u -#define CYDEV_CAN0_TX2_ID 0x4000a044u -#define CYDEV_CAN0_TX2_DH 0x4000a048u -#define CYDEV_CAN0_TX2_DL 0x4000a04cu -#define CYDEV_CAN0_TX3_BASE 0x4000a050u -#define CYDEV_CAN0_TX3_SIZE 0x00000010u -#define CYDEV_CAN0_TX3_CMD 0x4000a050u -#define CYDEV_CAN0_TX3_ID 0x4000a054u -#define CYDEV_CAN0_TX3_DH 0x4000a058u -#define CYDEV_CAN0_TX3_DL 0x4000a05cu -#define CYDEV_CAN0_TX4_BASE 0x4000a060u -#define CYDEV_CAN0_TX4_SIZE 0x00000010u -#define CYDEV_CAN0_TX4_CMD 0x4000a060u -#define CYDEV_CAN0_TX4_ID 0x4000a064u -#define CYDEV_CAN0_TX4_DH 0x4000a068u -#define CYDEV_CAN0_TX4_DL 0x4000a06cu -#define CYDEV_CAN0_TX5_BASE 0x4000a070u -#define CYDEV_CAN0_TX5_SIZE 0x00000010u -#define CYDEV_CAN0_TX5_CMD 0x4000a070u -#define CYDEV_CAN0_TX5_ID 0x4000a074u -#define CYDEV_CAN0_TX5_DH 0x4000a078u -#define CYDEV_CAN0_TX5_DL 0x4000a07cu -#define CYDEV_CAN0_TX6_BASE 0x4000a080u -#define CYDEV_CAN0_TX6_SIZE 0x00000010u -#define CYDEV_CAN0_TX6_CMD 0x4000a080u -#define CYDEV_CAN0_TX6_ID 0x4000a084u -#define CYDEV_CAN0_TX6_DH 0x4000a088u -#define CYDEV_CAN0_TX6_DL 0x4000a08cu -#define CYDEV_CAN0_TX7_BASE 0x4000a090u -#define CYDEV_CAN0_TX7_SIZE 0x00000010u -#define CYDEV_CAN0_TX7_CMD 0x4000a090u -#define CYDEV_CAN0_TX7_ID 0x4000a094u -#define CYDEV_CAN0_TX7_DH 0x4000a098u -#define CYDEV_CAN0_TX7_DL 0x4000a09cu -#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u -#define CYDEV_CAN0_RX0_SIZE 0x00000020u -#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u -#define CYDEV_CAN0_RX0_ID 0x4000a0a4u -#define CYDEV_CAN0_RX0_DH 0x4000a0a8u -#define CYDEV_CAN0_RX0_DL 0x4000a0acu -#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u -#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u -#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u -#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu -#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u -#define CYDEV_CAN0_RX1_SIZE 0x00000020u -#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u -#define CYDEV_CAN0_RX1_ID 0x4000a0c4u -#define CYDEV_CAN0_RX1_DH 0x4000a0c8u -#define CYDEV_CAN0_RX1_DL 0x4000a0ccu -#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u -#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u -#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u -#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu -#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u -#define CYDEV_CAN0_RX2_SIZE 0x00000020u -#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u -#define CYDEV_CAN0_RX2_ID 0x4000a0e4u -#define CYDEV_CAN0_RX2_DH 0x4000a0e8u -#define CYDEV_CAN0_RX2_DL 0x4000a0ecu -#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u -#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u -#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u -#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu -#define CYDEV_CAN0_RX3_BASE 0x4000a100u -#define CYDEV_CAN0_RX3_SIZE 0x00000020u -#define CYDEV_CAN0_RX3_CMD 0x4000a100u -#define CYDEV_CAN0_RX3_ID 0x4000a104u -#define CYDEV_CAN0_RX3_DH 0x4000a108u -#define CYDEV_CAN0_RX3_DL 0x4000a10cu -#define CYDEV_CAN0_RX3_AMR 0x4000a110u -#define CYDEV_CAN0_RX3_ACR 0x4000a114u -#define CYDEV_CAN0_RX3_AMRD 0x4000a118u -#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu -#define CYDEV_CAN0_RX4_BASE 0x4000a120u -#define CYDEV_CAN0_RX4_SIZE 0x00000020u -#define CYDEV_CAN0_RX4_CMD 0x4000a120u -#define CYDEV_CAN0_RX4_ID 0x4000a124u -#define CYDEV_CAN0_RX4_DH 0x4000a128u -#define CYDEV_CAN0_RX4_DL 0x4000a12cu -#define CYDEV_CAN0_RX4_AMR 0x4000a130u -#define CYDEV_CAN0_RX4_ACR 0x4000a134u -#define CYDEV_CAN0_RX4_AMRD 0x4000a138u -#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu -#define CYDEV_CAN0_RX5_BASE 0x4000a140u -#define CYDEV_CAN0_RX5_SIZE 0x00000020u -#define CYDEV_CAN0_RX5_CMD 0x4000a140u -#define CYDEV_CAN0_RX5_ID 0x4000a144u -#define CYDEV_CAN0_RX5_DH 0x4000a148u -#define CYDEV_CAN0_RX5_DL 0x4000a14cu -#define CYDEV_CAN0_RX5_AMR 0x4000a150u -#define CYDEV_CAN0_RX5_ACR 0x4000a154u -#define CYDEV_CAN0_RX5_AMRD 0x4000a158u -#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu -#define CYDEV_CAN0_RX6_BASE 0x4000a160u -#define CYDEV_CAN0_RX6_SIZE 0x00000020u -#define CYDEV_CAN0_RX6_CMD 0x4000a160u -#define CYDEV_CAN0_RX6_ID 0x4000a164u -#define CYDEV_CAN0_RX6_DH 0x4000a168u -#define CYDEV_CAN0_RX6_DL 0x4000a16cu -#define CYDEV_CAN0_RX6_AMR 0x4000a170u -#define CYDEV_CAN0_RX6_ACR 0x4000a174u -#define CYDEV_CAN0_RX6_AMRD 0x4000a178u -#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu -#define CYDEV_CAN0_RX7_BASE 0x4000a180u -#define CYDEV_CAN0_RX7_SIZE 0x00000020u -#define CYDEV_CAN0_RX7_CMD 0x4000a180u -#define CYDEV_CAN0_RX7_ID 0x4000a184u -#define CYDEV_CAN0_RX7_DH 0x4000a188u -#define CYDEV_CAN0_RX7_DL 0x4000a18cu -#define CYDEV_CAN0_RX7_AMR 0x4000a190u -#define CYDEV_CAN0_RX7_ACR 0x4000a194u -#define CYDEV_CAN0_RX7_AMRD 0x4000a198u -#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu -#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u -#define CYDEV_CAN0_RX8_SIZE 0x00000020u -#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u -#define CYDEV_CAN0_RX8_ID 0x4000a1a4u -#define CYDEV_CAN0_RX8_DH 0x4000a1a8u -#define CYDEV_CAN0_RX8_DL 0x4000a1acu -#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u -#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u -#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u -#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu -#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u -#define CYDEV_CAN0_RX9_SIZE 0x00000020u -#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u -#define CYDEV_CAN0_RX9_ID 0x4000a1c4u -#define CYDEV_CAN0_RX9_DH 0x4000a1c8u -#define CYDEV_CAN0_RX9_DL 0x4000a1ccu -#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u -#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u -#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u -#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu -#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u -#define CYDEV_CAN0_RX10_SIZE 0x00000020u -#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u -#define CYDEV_CAN0_RX10_ID 0x4000a1e4u -#define CYDEV_CAN0_RX10_DH 0x4000a1e8u -#define CYDEV_CAN0_RX10_DL 0x4000a1ecu -#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u -#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u -#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u -#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu -#define CYDEV_CAN0_RX11_BASE 0x4000a200u -#define CYDEV_CAN0_RX11_SIZE 0x00000020u -#define CYDEV_CAN0_RX11_CMD 0x4000a200u -#define CYDEV_CAN0_RX11_ID 0x4000a204u -#define CYDEV_CAN0_RX11_DH 0x4000a208u -#define CYDEV_CAN0_RX11_DL 0x4000a20cu -#define CYDEV_CAN0_RX11_AMR 0x4000a210u -#define CYDEV_CAN0_RX11_ACR 0x4000a214u -#define CYDEV_CAN0_RX11_AMRD 0x4000a218u -#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu -#define CYDEV_CAN0_RX12_BASE 0x4000a220u -#define CYDEV_CAN0_RX12_SIZE 0x00000020u -#define CYDEV_CAN0_RX12_CMD 0x4000a220u -#define CYDEV_CAN0_RX12_ID 0x4000a224u -#define CYDEV_CAN0_RX12_DH 0x4000a228u -#define CYDEV_CAN0_RX12_DL 0x4000a22cu -#define CYDEV_CAN0_RX12_AMR 0x4000a230u -#define CYDEV_CAN0_RX12_ACR 0x4000a234u -#define CYDEV_CAN0_RX12_AMRD 0x4000a238u -#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu -#define CYDEV_CAN0_RX13_BASE 0x4000a240u -#define CYDEV_CAN0_RX13_SIZE 0x00000020u -#define CYDEV_CAN0_RX13_CMD 0x4000a240u -#define CYDEV_CAN0_RX13_ID 0x4000a244u -#define CYDEV_CAN0_RX13_DH 0x4000a248u -#define CYDEV_CAN0_RX13_DL 0x4000a24cu -#define CYDEV_CAN0_RX13_AMR 0x4000a250u -#define CYDEV_CAN0_RX13_ACR 0x4000a254u -#define CYDEV_CAN0_RX13_AMRD 0x4000a258u -#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu -#define CYDEV_CAN0_RX14_BASE 0x4000a260u -#define CYDEV_CAN0_RX14_SIZE 0x00000020u -#define CYDEV_CAN0_RX14_CMD 0x4000a260u -#define CYDEV_CAN0_RX14_ID 0x4000a264u -#define CYDEV_CAN0_RX14_DH 0x4000a268u -#define CYDEV_CAN0_RX14_DL 0x4000a26cu -#define CYDEV_CAN0_RX14_AMR 0x4000a270u -#define CYDEV_CAN0_RX14_ACR 0x4000a274u -#define CYDEV_CAN0_RX14_AMRD 0x4000a278u -#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu -#define CYDEV_CAN0_RX15_BASE 0x4000a280u -#define CYDEV_CAN0_RX15_SIZE 0x00000020u -#define CYDEV_CAN0_RX15_CMD 0x4000a280u -#define CYDEV_CAN0_RX15_ID 0x4000a284u -#define CYDEV_CAN0_RX15_DH 0x4000a288u -#define CYDEV_CAN0_RX15_DL 0x4000a28cu -#define CYDEV_CAN0_RX15_AMR 0x4000a290u -#define CYDEV_CAN0_RX15_ACR 0x4000a294u -#define CYDEV_CAN0_RX15_AMRD 0x4000a298u -#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu -#define CYDEV_DFB0_BASE 0x4000c000u -#define CYDEV_DFB0_SIZE 0x000007b5u -#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u -#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u -#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u -#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u -#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u -#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u -#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u -#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u -#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u -#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u -#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u -#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u -#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u -#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u -#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u -#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u -#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u -#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u -#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u -#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u -#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u -#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u -#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u -#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u -#define CYDEV_DFB0_CR 0x4000c780u -#define CYDEV_DFB0_SR 0x4000c784u -#define CYDEV_DFB0_RAM_EN 0x4000c788u -#define CYDEV_DFB0_RAM_DIR 0x4000c78cu -#define CYDEV_DFB0_SEMA 0x4000c790u -#define CYDEV_DFB0_DSI_CTRL 0x4000c794u -#define CYDEV_DFB0_INT_CTRL 0x4000c798u -#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu -#define CYDEV_DFB0_STAGEA 0x4000c7a0u -#define CYDEV_DFB0_STAGEAM 0x4000c7a1u -#define CYDEV_DFB0_STAGEAH 0x4000c7a2u -#define CYDEV_DFB0_STAGEB 0x4000c7a4u -#define CYDEV_DFB0_STAGEBM 0x4000c7a5u -#define CYDEV_DFB0_STAGEBH 0x4000c7a6u -#define CYDEV_DFB0_HOLDA 0x4000c7a8u -#define CYDEV_DFB0_HOLDAM 0x4000c7a9u -#define CYDEV_DFB0_HOLDAH 0x4000c7aau -#define CYDEV_DFB0_HOLDAS 0x4000c7abu -#define CYDEV_DFB0_HOLDB 0x4000c7acu -#define CYDEV_DFB0_HOLDBM 0x4000c7adu -#define CYDEV_DFB0_HOLDBH 0x4000c7aeu -#define CYDEV_DFB0_HOLDBS 0x4000c7afu -#define CYDEV_DFB0_COHER 0x4000c7b0u -#define CYDEV_DFB0_DALIGN 0x4000c7b4u -#define CYDEV_UCFG_BASE 0x40010000u -#define CYDEV_UCFG_SIZE 0x00005040u -#define CYDEV_UCFG_B0_BASE 0x40010000u -#define CYDEV_UCFG_B0_SIZE 0x00000fefu -#define CYDEV_UCFG_B0_P0_BASE 0x40010000u -#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u -#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu -#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu -#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u -#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu -#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u -#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u -#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u -#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u -#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u -#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u -#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u -#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u -#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u -#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u -#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au -#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu -#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu -#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du -#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu -#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu -#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u -#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u -#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u -#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u -#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u -#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u -#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u -#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u -#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u -#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u -#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au -#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu -#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu -#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du -#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu -#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu -#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u -#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u -#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u -#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u -#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u -#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au -#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu -#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu -#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u -#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu -#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu -#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u -#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu -#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u -#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u -#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u -#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u -#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u -#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u -#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u -#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u -#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u -#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u -#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau -#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu -#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu -#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu -#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu -#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu -#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u -#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u -#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u -#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u -#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u -#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u -#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u -#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u -#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u -#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u -#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau -#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu -#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu -#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu -#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu -#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu -#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u -#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u -#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u -#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u -#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u -#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau -#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu -#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu -#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u -#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P1_BASE 0x40010200u -#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u -#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu -#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu -#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u -#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu -#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u -#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u -#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u -#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u -#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u -#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u -#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u -#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u -#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u -#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u -#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au -#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu -#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu -#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du -#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu -#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu -#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u -#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u -#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u -#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u -#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u -#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u -#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u -#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u -#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u -#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u -#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au -#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu -#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu -#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du -#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu -#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu -#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u -#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u -#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u -#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u -#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u -#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au -#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu -#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu -#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u -#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu -#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu -#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u -#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu -#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u -#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u -#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u -#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u -#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u -#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u -#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u -#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u -#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u -#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u -#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau -#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu -#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu -#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu -#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu -#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu -#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u -#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u -#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u -#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u -#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u -#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u -#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u -#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u -#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u -#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u -#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau -#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu -#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu -#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu -#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu -#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu -#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u -#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u -#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u -#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u -#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u -#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau -#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu -#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu -#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u -#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P2_BASE 0x40010400u -#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u -#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu -#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu -#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u -#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu -#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u -#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u -#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u -#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u -#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u -#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u -#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u -#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u -#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u -#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u -#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au -#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu -#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu -#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du -#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu -#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu -#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u -#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u -#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u -#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u -#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u -#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u -#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u -#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u -#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u -#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u -#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au -#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu -#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu -#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du -#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu -#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu -#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u -#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u -#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u -#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u -#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u -#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au -#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu -#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu -#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u -#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu -#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu -#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u -#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu -#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u -#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u -#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u -#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u -#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u -#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u -#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u -#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u -#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u -#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u -#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau -#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu -#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu -#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu -#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu -#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu -#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u -#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u -#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u -#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u -#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u -#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u -#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u -#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u -#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u -#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u -#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau -#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu -#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu -#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu -#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu -#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu -#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u -#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u -#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u -#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u -#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u -#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau -#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu -#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu -#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u -#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P3_BASE 0x40010600u -#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u -#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu -#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu -#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u -#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu -#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u -#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u -#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u -#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u -#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u -#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u -#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u -#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u -#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u -#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u -#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au -#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu -#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu -#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du -#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu -#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu -#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u -#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u -#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u -#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u -#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u -#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u -#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u -#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u -#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u -#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u -#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au -#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu -#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu -#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du -#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu -#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu -#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u -#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u -#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u -#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u -#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u -#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au -#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu -#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu -#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u -#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu -#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu -#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u -#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu -#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u -#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u -#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u -#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u -#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u -#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u -#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u -#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u -#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u -#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u -#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau -#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu -#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu -#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu -#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu -#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu -#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u -#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u -#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u -#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u -#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u -#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u -#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u -#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u -#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u -#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u -#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau -#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu -#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu -#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu -#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu -#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu -#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u -#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u -#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u -#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u -#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u -#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau -#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu -#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu -#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u -#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P4_BASE 0x40010800u -#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u -#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu -#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu -#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u -#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu -#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u -#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u -#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u -#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u -#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u -#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u -#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u -#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u -#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u -#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u -#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au -#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu -#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu -#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du -#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu -#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu -#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u -#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u -#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u -#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u -#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u -#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u -#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u -#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u -#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u -#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u -#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au -#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu -#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu -#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du -#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu -#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu -#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u -#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u -#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u -#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u -#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u -#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au -#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu -#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu -#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u -#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu -#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu -#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u -#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu -#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u -#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u -#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u -#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u -#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u -#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u -#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u -#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u -#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u -#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u -#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau -#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu -#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu -#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu -#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu -#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu -#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u -#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u -#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u -#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u -#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u -#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u -#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u -#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u -#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u -#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u -#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau -#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu -#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu -#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu -#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu -#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu -#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u -#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u -#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u -#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u -#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u -#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau -#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu -#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu -#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u -#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u -#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u -#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu -#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu -#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u -#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu -#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u -#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u -#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u -#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u -#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u -#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u -#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u -#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u -#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u -#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u -#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au -#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu -#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu -#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du -#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu -#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu -#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u -#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u -#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u -#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u -#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u -#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u -#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u -#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u -#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u -#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u -#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au -#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu -#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu -#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du -#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu -#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu -#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u -#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u -#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u -#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u -#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u -#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au -#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu -#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu -#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u -#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu -#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu -#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u -#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu -#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u -#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u -#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u -#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u -#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u -#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u -#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u -#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u -#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u -#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u -#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau -#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu -#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu -#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu -#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu -#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu -#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u -#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u -#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u -#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u -#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u -#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u -#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u -#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u -#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u -#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u -#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau -#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu -#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu -#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu -#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu -#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu -#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u -#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u -#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u -#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u -#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u -#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau -#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu -#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu -#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u -#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u -#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u -#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu -#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu -#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u -#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu -#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u -#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u -#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u -#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u -#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u -#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u -#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u -#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u -#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u -#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u -#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au -#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu -#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu -#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du -#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu -#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu -#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u -#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u -#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u -#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u -#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u -#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u -#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u -#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u -#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u -#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u -#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au -#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu -#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu -#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du -#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu -#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu -#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u -#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u -#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u -#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u -#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u -#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au -#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu -#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu -#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u -#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu -#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu -#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u -#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu -#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u -#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u -#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u -#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u -#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u -#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u -#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u -#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u -#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u -#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u -#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau -#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu -#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu -#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu -#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu -#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu -#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u -#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u -#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u -#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u -#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u -#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u -#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u -#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u -#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u -#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u -#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau -#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu -#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu -#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu -#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu -#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu -#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u -#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u -#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u -#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u -#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u -#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau -#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu -#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu -#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u -#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u -#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u -#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu -#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu -#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u -#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu -#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u -#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u -#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u -#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u -#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u -#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u -#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u -#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u -#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u -#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u -#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au -#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu -#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu -#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du -#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu -#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu -#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u -#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u -#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u -#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u -#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u -#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u -#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u -#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u -#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u -#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u -#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au -#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu -#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu -#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du -#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu -#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu -#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u -#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u -#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u -#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u -#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u -#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au -#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu -#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu -#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u -#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu -#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu -#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u -#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu -#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u -#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u -#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u -#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u -#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u -#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u -#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u -#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u -#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u -#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u -#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau -#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu -#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu -#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu -#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu -#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu -#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u -#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u -#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u -#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u -#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u -#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u -#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u -#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u -#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u -#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u -#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau -#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu -#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu -#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu -#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu -#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu -#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u -#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u -#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u -#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u -#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u -#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau -#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu -#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu -#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u -#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_BASE 0x40011000u -#define CYDEV_UCFG_B1_SIZE 0x00000fefu -#define CYDEV_UCFG_B1_P2_BASE 0x40011400u -#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u -#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu -#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu -#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u -#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu -#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u -#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u -#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u -#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u -#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u -#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u -#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u -#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u -#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u -#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u -#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au -#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu -#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu -#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du -#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu -#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu -#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u -#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u -#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u -#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u -#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u -#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u -#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u -#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u -#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u -#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u -#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au -#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu -#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu -#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du -#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu -#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu -#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u -#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u -#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u -#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u -#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u -#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au -#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu -#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu -#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u -#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu -#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu -#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u -#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu -#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u -#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u -#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u -#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u -#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u -#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u -#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u -#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u -#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u -#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u -#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau -#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu -#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu -#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu -#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu -#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu -#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u -#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u -#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u -#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u -#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u -#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u -#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u -#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u -#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u -#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u -#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau -#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu -#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu -#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu -#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu -#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu -#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u -#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u -#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u -#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u -#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u -#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau -#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu -#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu -#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u -#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_P3_BASE 0x40011600u -#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u -#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu -#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu -#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u -#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu -#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u -#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u -#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u -#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u -#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u -#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u -#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u -#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u -#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u -#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u -#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au -#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu -#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu -#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du -#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu -#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu -#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u -#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u -#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u -#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u -#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u -#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u -#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u -#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u -#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u -#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u -#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au -#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu -#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu -#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du -#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu -#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu -#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u -#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u -#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u -#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u -#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u -#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au -#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu -#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu -#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u -#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu -#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu -#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u -#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu -#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u -#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u -#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u -#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u -#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u -#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u -#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u -#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u -#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u -#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u -#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau -#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu -#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu -#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu -#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu -#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu -#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u -#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u -#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u -#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u -#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u -#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u -#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u -#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u -#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u -#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u -#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau -#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu -#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu -#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu -#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu -#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu -#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u -#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u -#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u -#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u -#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u -#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau -#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu -#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu -#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u -#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_P4_BASE 0x40011800u -#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u -#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu -#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu -#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u -#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu -#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u -#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u -#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u -#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u -#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u -#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u -#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u -#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u -#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u -#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u -#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au -#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu -#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu -#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du -#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu -#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu -#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u -#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u -#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u -#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u -#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u -#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u -#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u -#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u -#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u -#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u -#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au -#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu -#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu -#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du -#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu -#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu -#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u -#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u -#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u -#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u -#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u -#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au -#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu -#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu -#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u -#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu -#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu -#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u -#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu -#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u -#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u -#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u -#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u -#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u -#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u -#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u -#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u -#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u -#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u -#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau -#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu -#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu -#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu -#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu -#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu -#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u -#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u -#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u -#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u -#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u -#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u -#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u -#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u -#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u -#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u -#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau -#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu -#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu -#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu -#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu -#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu -#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u -#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u -#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u -#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u -#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u -#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau -#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu -#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu -#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u -#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u -#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u -#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu -#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu -#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u -#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu -#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u -#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u -#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u -#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u -#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u -#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u -#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u -#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u -#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u -#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u -#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au -#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu -#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu -#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du -#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu -#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu -#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u -#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u -#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u -#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u -#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u -#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u -#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u -#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u -#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u -#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u -#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au -#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu -#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu -#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du -#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu -#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu -#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u -#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u -#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u -#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u -#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u -#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au -#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu -#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu -#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u -#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu -#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu -#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u -#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu -#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u -#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u -#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u -#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u -#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u -#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u -#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u -#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u -#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u -#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u -#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau -#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu -#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu -#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu -#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu -#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu -#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u -#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u -#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u -#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u -#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u -#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u -#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u -#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u -#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u -#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u -#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau -#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu -#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu -#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu -#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu -#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu -#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u -#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u -#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u -#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u -#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u -#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau -#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu -#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu -#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u -#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_DSI0_BASE 0x40014000u -#define CYDEV_UCFG_DSI0_SIZE 0x000000efu -#define CYDEV_UCFG_DSI1_BASE 0x40014100u -#define CYDEV_UCFG_DSI1_SIZE 0x000000efu -#define CYDEV_UCFG_DSI2_BASE 0x40014200u -#define CYDEV_UCFG_DSI2_SIZE 0x000000efu -#define CYDEV_UCFG_DSI3_BASE 0x40014300u -#define CYDEV_UCFG_DSI3_SIZE 0x000000efu -#define CYDEV_UCFG_DSI4_BASE 0x40014400u -#define CYDEV_UCFG_DSI4_SIZE 0x000000efu -#define CYDEV_UCFG_DSI5_BASE 0x40014500u -#define CYDEV_UCFG_DSI5_SIZE 0x000000efu -#define CYDEV_UCFG_DSI6_BASE 0x40014600u -#define CYDEV_UCFG_DSI6_SIZE 0x000000efu -#define CYDEV_UCFG_DSI7_BASE 0x40014700u -#define CYDEV_UCFG_DSI7_SIZE 0x000000efu -#define CYDEV_UCFG_DSI8_BASE 0x40014800u -#define CYDEV_UCFG_DSI8_SIZE 0x000000efu -#define CYDEV_UCFG_DSI9_BASE 0x40014900u -#define CYDEV_UCFG_DSI9_SIZE 0x000000efu -#define CYDEV_UCFG_DSI12_BASE 0x40014c00u -#define CYDEV_UCFG_DSI12_SIZE 0x000000efu -#define CYDEV_UCFG_DSI13_BASE 0x40014d00u -#define CYDEV_UCFG_DSI13_SIZE 0x000000efu -#define CYDEV_UCFG_BCTL0_BASE 0x40015000u -#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u -#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u -#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u -#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u -#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u -#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u -#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u -#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u -#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au -#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu -#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu -#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du -#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu -#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu -#define CYDEV_UCFG_BCTL1_BASE 0x40015010u -#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u -#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u -#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u -#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u -#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u -#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u -#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u -#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u -#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au -#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu -#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu -#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du -#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu -#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu -#define CYDEV_IDMUX_BASE 0x40015100u -#define CYDEV_IDMUX_SIZE 0x00000016u -#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u -#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u -#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u -#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u -#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u -#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u -#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u -#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u -#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u -#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u -#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u -#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u -#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u -#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u -#define CYDEV_CACHERAM_BASE 0x40030000u -#define CYDEV_CACHERAM_SIZE 0x00000400u -#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u -#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u -#define CYDEV_SFR_BASE 0x40050100u -#define CYDEV_SFR_SIZE 0x000000fbu -#define CYDEV_SFR_GPIO0 0x40050180u -#define CYDEV_SFR_GPIRD0 0x40050189u -#define CYDEV_SFR_GPIO0_SEL 0x4005018au -#define CYDEV_SFR_GPIO1 0x40050190u -#define CYDEV_SFR_GPIRD1 0x40050191u -#define CYDEV_SFR_GPIO2 0x40050198u -#define CYDEV_SFR_GPIRD2 0x40050199u -#define CYDEV_SFR_GPIO2_SEL 0x4005019au -#define CYDEV_SFR_GPIO1_SEL 0x400501a2u -#define CYDEV_SFR_GPIO3 0x400501b0u -#define CYDEV_SFR_GPIRD3 0x400501b1u -#define CYDEV_SFR_GPIO3_SEL 0x400501b2u -#define CYDEV_SFR_GPIO4 0x400501c0u -#define CYDEV_SFR_GPIRD4 0x400501c1u -#define CYDEV_SFR_GPIO4_SEL 0x400501c2u -#define CYDEV_SFR_GPIO5 0x400501c8u -#define CYDEV_SFR_GPIRD5 0x400501c9u -#define CYDEV_SFR_GPIO5_SEL 0x400501cau -#define CYDEV_SFR_GPIO6 0x400501d8u -#define CYDEV_SFR_GPIRD6 0x400501d9u -#define CYDEV_SFR_GPIO6_SEL 0x400501dau -#define CYDEV_SFR_GPIO12 0x400501e8u -#define CYDEV_SFR_GPIRD12 0x400501e9u -#define CYDEV_SFR_GPIO12_SEL 0x400501f2u -#define CYDEV_SFR_GPIO15 0x400501f8u -#define CYDEV_SFR_GPIRD15 0x400501f9u -#define CYDEV_SFR_GPIO15_SEL 0x400501fau -#define CYDEV_P3BA_BASE 0x40050300u -#define CYDEV_P3BA_SIZE 0x0000002bu -#define CYDEV_P3BA_Y_START 0x40050300u -#define CYDEV_P3BA_YROLL 0x40050301u -#define CYDEV_P3BA_YCFG 0x40050302u -#define CYDEV_P3BA_X_START1 0x40050303u -#define CYDEV_P3BA_X_START2 0x40050304u -#define CYDEV_P3BA_XROLL1 0x40050305u -#define CYDEV_P3BA_XROLL2 0x40050306u -#define CYDEV_P3BA_XINC 0x40050307u -#define CYDEV_P3BA_XCFG 0x40050308u -#define CYDEV_P3BA_OFFSETADDR1 0x40050309u -#define CYDEV_P3BA_OFFSETADDR2 0x4005030au -#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu -#define CYDEV_P3BA_ABSADDR1 0x4005030cu -#define CYDEV_P3BA_ABSADDR2 0x4005030du -#define CYDEV_P3BA_ABSADDR3 0x4005030eu -#define CYDEV_P3BA_ABSADDR4 0x4005030fu -#define CYDEV_P3BA_DATCFG1 0x40050310u -#define CYDEV_P3BA_DATCFG2 0x40050311u -#define CYDEV_P3BA_CMP_RSLT1 0x40050314u -#define CYDEV_P3BA_CMP_RSLT2 0x40050315u -#define CYDEV_P3BA_CMP_RSLT3 0x40050316u -#define CYDEV_P3BA_CMP_RSLT4 0x40050317u -#define CYDEV_P3BA_DATA_REG1 0x40050318u -#define CYDEV_P3BA_DATA_REG2 0x40050319u -#define CYDEV_P3BA_DATA_REG3 0x4005031au -#define CYDEV_P3BA_DATA_REG4 0x4005031bu -#define CYDEV_P3BA_EXP_DATA1 0x4005031cu -#define CYDEV_P3BA_EXP_DATA2 0x4005031du -#define CYDEV_P3BA_EXP_DATA3 0x4005031eu -#define CYDEV_P3BA_EXP_DATA4 0x4005031fu -#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u -#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u -#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u -#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u -#define CYDEV_P3BA_BIST_EN 0x40050324u -#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u -#define CYDEV_P3BA_SEQCFG1 0x40050326u -#define CYDEV_P3BA_SEQCFG2 0x40050327u -#define CYDEV_P3BA_Y_CURR 0x40050328u -#define CYDEV_P3BA_X_CURR1 0x40050329u -#define CYDEV_P3BA_X_CURR2 0x4005032au -#define CYDEV_PANTHER_BASE 0x40080000u -#define CYDEV_PANTHER_SIZE 0x00000020u -#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u -#define CYDEV_PANTHER_WAITPIPE 0x40080004u -#define CYDEV_PANTHER_TRACE_CFG 0x40080008u -#define CYDEV_PANTHER_DBG_CFG 0x4008000cu -#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u -#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu -#define CYDEV_FLSECC_BASE 0x48000000u -#define CYDEV_FLSECC_SIZE 0x00008000u -#define CYDEV_FLSECC_DATA_MBASE 0x48000000u -#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u -#define CYDEV_FLSHID_BASE 0x49000000u -#define CYDEV_FLSHID_SIZE 0x00000200u -#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u -#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u -#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u -#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u -#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u -#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u -#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u -#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u -#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u -#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u -#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u -#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u -#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u -#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u -#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u -#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u -#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au -#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu -#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu -#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du -#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu -#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu -#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u -#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u -#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u -#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u -#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u -#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u -#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u -#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u -#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u -#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u -#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au -#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu -#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu -#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du -#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu -#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu -#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u -#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u -#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u -#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu -#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu -#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u -#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u -#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u -#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u -#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u -#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau -#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu -#define CYDEV_EXTMEM_BASE 0x60000000u -#define CYDEV_EXTMEM_SIZE 0x00800000u -#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u -#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u -#define CYDEV_ITM_BASE 0xe0000000u -#define CYDEV_ITM_SIZE 0x00001000u -#define CYDEV_ITM_TRACE_EN 0xe0000e00u -#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u -#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u -#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u -#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u -#define CYDEV_ITM_PID4 0xe0000fd0u -#define CYDEV_ITM_PID5 0xe0000fd4u -#define CYDEV_ITM_PID6 0xe0000fd8u -#define CYDEV_ITM_PID7 0xe0000fdcu -#define CYDEV_ITM_PID0 0xe0000fe0u -#define CYDEV_ITM_PID1 0xe0000fe4u -#define CYDEV_ITM_PID2 0xe0000fe8u -#define CYDEV_ITM_PID3 0xe0000fecu -#define CYDEV_ITM_CID0 0xe0000ff0u -#define CYDEV_ITM_CID1 0xe0000ff4u -#define CYDEV_ITM_CID2 0xe0000ff8u -#define CYDEV_ITM_CID3 0xe0000ffcu -#define CYDEV_DWT_BASE 0xe0001000u -#define CYDEV_DWT_SIZE 0x0000005cu -#define CYDEV_DWT_CTRL 0xe0001000u -#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u -#define CYDEV_DWT_CPI_COUNT 0xe0001008u -#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu -#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u -#define CYDEV_DWT_LSU_COUNT 0xe0001014u -#define CYDEV_DWT_FOLD_COUNT 0xe0001018u -#define CYDEV_DWT_PC_SAMPLE 0xe000101cu -#define CYDEV_DWT_COMP_0 0xe0001020u -#define CYDEV_DWT_MASK_0 0xe0001024u -#define CYDEV_DWT_FUNCTION_0 0xe0001028u -#define CYDEV_DWT_COMP_1 0xe0001030u -#define CYDEV_DWT_MASK_1 0xe0001034u -#define CYDEV_DWT_FUNCTION_1 0xe0001038u -#define CYDEV_DWT_COMP_2 0xe0001040u -#define CYDEV_DWT_MASK_2 0xe0001044u -#define CYDEV_DWT_FUNCTION_2 0xe0001048u -#define CYDEV_DWT_COMP_3 0xe0001050u -#define CYDEV_DWT_MASK_3 0xe0001054u -#define CYDEV_DWT_FUNCTION_3 0xe0001058u -#define CYDEV_FPB_BASE 0xe0002000u -#define CYDEV_FPB_SIZE 0x00001000u -#define CYDEV_FPB_CTRL 0xe0002000u -#define CYDEV_FPB_REMAP 0xe0002004u -#define CYDEV_FPB_FP_COMP_0 0xe0002008u -#define CYDEV_FPB_FP_COMP_1 0xe000200cu -#define CYDEV_FPB_FP_COMP_2 0xe0002010u -#define CYDEV_FPB_FP_COMP_3 0xe0002014u -#define CYDEV_FPB_FP_COMP_4 0xe0002018u -#define CYDEV_FPB_FP_COMP_5 0xe000201cu -#define CYDEV_FPB_FP_COMP_6 0xe0002020u -#define CYDEV_FPB_FP_COMP_7 0xe0002024u -#define CYDEV_FPB_PID4 0xe0002fd0u -#define CYDEV_FPB_PID5 0xe0002fd4u -#define CYDEV_FPB_PID6 0xe0002fd8u -#define CYDEV_FPB_PID7 0xe0002fdcu -#define CYDEV_FPB_PID0 0xe0002fe0u -#define CYDEV_FPB_PID1 0xe0002fe4u -#define CYDEV_FPB_PID2 0xe0002fe8u -#define CYDEV_FPB_PID3 0xe0002fecu -#define CYDEV_FPB_CID0 0xe0002ff0u -#define CYDEV_FPB_CID1 0xe0002ff4u -#define CYDEV_FPB_CID2 0xe0002ff8u -#define CYDEV_FPB_CID3 0xe0002ffcu -#define CYDEV_NVIC_BASE 0xe000e000u -#define CYDEV_NVIC_SIZE 0x00000d3cu -#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u -#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u -#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u -#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u -#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu -#define CYDEV_NVIC_SETENA0 0xe000e100u -#define CYDEV_NVIC_CLRENA0 0xe000e180u -#define CYDEV_NVIC_SETPEND0 0xe000e200u -#define CYDEV_NVIC_CLRPEND0 0xe000e280u -#define CYDEV_NVIC_ACTIVE0 0xe000e300u -#define CYDEV_NVIC_PRI_0 0xe000e400u -#define CYDEV_NVIC_PRI_1 0xe000e401u -#define CYDEV_NVIC_PRI_2 0xe000e402u -#define CYDEV_NVIC_PRI_3 0xe000e403u -#define CYDEV_NVIC_PRI_4 0xe000e404u -#define CYDEV_NVIC_PRI_5 0xe000e405u -#define CYDEV_NVIC_PRI_6 0xe000e406u -#define CYDEV_NVIC_PRI_7 0xe000e407u -#define CYDEV_NVIC_PRI_8 0xe000e408u -#define CYDEV_NVIC_PRI_9 0xe000e409u -#define CYDEV_NVIC_PRI_10 0xe000e40au -#define CYDEV_NVIC_PRI_11 0xe000e40bu -#define CYDEV_NVIC_PRI_12 0xe000e40cu -#define CYDEV_NVIC_PRI_13 0xe000e40du -#define CYDEV_NVIC_PRI_14 0xe000e40eu -#define CYDEV_NVIC_PRI_15 0xe000e40fu -#define CYDEV_NVIC_PRI_16 0xe000e410u -#define CYDEV_NVIC_PRI_17 0xe000e411u -#define CYDEV_NVIC_PRI_18 0xe000e412u -#define CYDEV_NVIC_PRI_19 0xe000e413u -#define CYDEV_NVIC_PRI_20 0xe000e414u -#define CYDEV_NVIC_PRI_21 0xe000e415u -#define CYDEV_NVIC_PRI_22 0xe000e416u -#define CYDEV_NVIC_PRI_23 0xe000e417u -#define CYDEV_NVIC_PRI_24 0xe000e418u -#define CYDEV_NVIC_PRI_25 0xe000e419u -#define CYDEV_NVIC_PRI_26 0xe000e41au -#define CYDEV_NVIC_PRI_27 0xe000e41bu -#define CYDEV_NVIC_PRI_28 0xe000e41cu -#define CYDEV_NVIC_PRI_29 0xe000e41du -#define CYDEV_NVIC_PRI_30 0xe000e41eu -#define CYDEV_NVIC_PRI_31 0xe000e41fu -#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u -#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u -#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u -#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu -#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u -#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u -#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u -#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu -#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u -#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u -#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u -#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u -#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au -#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu -#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u -#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u -#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u -#define CYDEV_CORE_DBG_BASE 0xe000edf0u -#define CYDEV_CORE_DBG_SIZE 0x00000010u -#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u -#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u -#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u -#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu -#define CYDEV_TPIU_BASE 0xe0040000u -#define CYDEV_TPIU_SIZE 0x00001000u -#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u -#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u -#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u -#define CYDEV_TPIU_PROTOCOL 0xe00400f0u -#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u -#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u -#define CYDEV_TPIU_TRIGGER 0xe0040ee8u -#define CYDEV_TPIU_ITETMDATA 0xe0040eecu -#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u -#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u -#define CYDEV_TPIU_ITITMDATA 0xe0040efcu -#define CYDEV_TPIU_ITCTRL 0xe0040f00u -#define CYDEV_TPIU_DEVID 0xe0040fc8u -#define CYDEV_TPIU_DEVTYPE 0xe0040fccu -#define CYDEV_TPIU_PID4 0xe0040fd0u -#define CYDEV_TPIU_PID5 0xe0040fd4u -#define CYDEV_TPIU_PID6 0xe0040fd8u -#define CYDEV_TPIU_PID7 0xe0040fdcu -#define CYDEV_TPIU_PID0 0xe0040fe0u -#define CYDEV_TPIU_PID1 0xe0040fe4u -#define CYDEV_TPIU_PID2 0xe0040fe8u -#define CYDEV_TPIU_PID3 0xe0040fecu -#define CYDEV_TPIU_CID0 0xe0040ff0u -#define CYDEV_TPIU_CID1 0xe0040ff4u -#define CYDEV_TPIU_CID2 0xe0040ff8u -#define CYDEV_TPIU_CID3 0xe0040ffcu -#define CYDEV_ETM_BASE 0xe0041000u -#define CYDEV_ETM_SIZE 0x00001000u -#define CYDEV_ETM_CTL 0xe0041000u -#define CYDEV_ETM_CFG_CODE 0xe0041004u -#define CYDEV_ETM_TRIG_EVENT 0xe0041008u -#define CYDEV_ETM_STATUS 0xe0041010u -#define CYDEV_ETM_SYS_CFG 0xe0041014u -#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u -#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u -#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu -#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u -#define CYDEV_ETM_ETM_ID 0xe00411e4u -#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u -#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u -#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u -#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u -#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u -#define CYDEV_ETM_PDSR 0xe0041314u -#define CYDEV_ETM_ITMISCIN 0xe0041ee0u -#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u -#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u -#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u -#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u -#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u -#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u -#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u -#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u -#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u -#define CYDEV_ETM_DEV_TYPE 0xe0041fccu -#define CYDEV_ETM_PID4 0xe0041fd0u -#define CYDEV_ETM_PID5 0xe0041fd4u -#define CYDEV_ETM_PID6 0xe0041fd8u -#define CYDEV_ETM_PID7 0xe0041fdcu -#define CYDEV_ETM_PID0 0xe0041fe0u -#define CYDEV_ETM_PID1 0xe0041fe4u -#define CYDEV_ETM_PID2 0xe0041fe8u -#define CYDEV_ETM_PID3 0xe0041fecu -#define CYDEV_ETM_CID0 0xe0041ff0u -#define CYDEV_ETM_CID1 0xe0041ff4u -#define CYDEV_ETM_CID2 0xe0041ff8u -#define CYDEV_ETM_CID3 0xe0041ffcu -#define CYDEV_ROM_TABLE_BASE 0xe00ff000u -#define CYDEV_ROM_TABLE_SIZE 0x00001000u -#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u -#define CYDEV_ROM_TABLE_DWT 0xe00ff004u -#define CYDEV_ROM_TABLE_FPB 0xe00ff008u -#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu -#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u -#define CYDEV_ROM_TABLE_ETM 0xe00ff014u -#define CYDEV_ROM_TABLE_END 0xe00ff018u -#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu -#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u -#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u -#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u -#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu -#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u -#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u -#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u -#define CYDEV_ROM_TABLE_PID3 0xe00fffecu -#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u -#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u -#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u -#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu -#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE -#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE -#define CYDEV_FLS_SECTOR_SIZE 0x00010000u -#define CYDEV_FLS_ROW_SIZE 0x00000100u -#define CYDEV_ECC_SECTOR_SIZE 0x00002000u -#define CYDEV_ECC_ROW_SIZE 0x00000020u -#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u -#define CYDEV_EEPROM_ROW_SIZE 0x00000010u -#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE -#define CYCLK_LD_DISABLE 0x00000004u -#define CYCLK_LD_SYNC_EN 0x00000002u -#define CYCLK_LD_LOAD 0x00000001u -#define CYCLK_PIPE 0x00000080u -#define CYCLK_SSS 0x00000040u -#define CYCLK_EARLY 0x00000020u -#define CYCLK_DUTY 0x00000010u -#define CYCLK_SYNC 0x00000008u -#define CYCLK_SRC_SEL_CLK_SYNC_D 0 -#define CYCLK_SRC_SEL_SYNC_DIG 0 -#define CYCLK_SRC_SEL_IMO 1 -#define CYCLK_SRC_SEL_XTAL_MHZ 2 -#define CYCLK_SRC_SEL_XTALM 2 -#define CYCLK_SRC_SEL_ILO 3 -#define CYCLK_SRC_SEL_PLL 4 -#define CYCLK_SRC_SEL_XTAL_KHZ 5 -#define CYCLK_SRC_SEL_XTALK 5 -#define CYCLK_SRC_SEL_DSI_G 6 -#define CYCLK_SRC_SEL_DSI_D 7 -#define CYCLK_SRC_SEL_CLK_SYNC_A 0 -#define CYCLK_SRC_SEL_DSI_A 7 -#endif /* CYDEVICE_H */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h deleted file mode 100755 index e2c0687..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevice_trm.h +++ /dev/null @@ -1,5360 +0,0 @@ -/******************************************************************************* -* FILENAME: cydevice_trm.h -* -* PSoC Creator 3.0 Component Pack 7 -* -* DESCRIPTION: -* This file provides all of the address values for the entire PSoC device. -* This file is automatically generated by PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#if !defined(CYDEVICE_TRM_H) -#define CYDEVICE_TRM_H -#define CYDEV_FLASH_BASE 0x00000000u -#define CYDEV_FLASH_SIZE 0x00020000u -#define CYREG_FLASH_DATA_MBASE 0x00000000u -#define CYREG_FLASH_DATA_MSIZE 0x00020000u -#define CYDEV_SRAM_BASE 0x1fffc000u -#define CYDEV_SRAM_SIZE 0x00008000u -#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u -#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u -#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u -#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u -#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u -#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u -#define CYREG_SRAM_CODE_MBASE 0x1fffc000u -#define CYREG_SRAM_CODE_MSIZE 0x00004000u -#define CYREG_SRAM_DATA_MBASE 0x20000000u -#define CYREG_SRAM_DATA_MSIZE 0x00004000u -#define CYREG_SRAM_DATA16K_MBASE 0x20001000u -#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u -#define CYREG_SRAM_DATA32K_MBASE 0x20002000u -#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u -#define CYREG_SRAM_DATA64K_MBASE 0x20004000u -#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u -#define CYDEV_DMA_BASE 0x20008000u -#define CYDEV_DMA_SIZE 0x00008000u -#define CYREG_DMA_SRAM64K_MBASE 0x20008000u -#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u -#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u -#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u -#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u -#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u -#define CYREG_DMA_SRAM_MBASE 0x2000f000u -#define CYREG_DMA_SRAM_MSIZE 0x00001000u -#define CYDEV_CLKDIST_BASE 0x40004000u -#define CYDEV_CLKDIST_SIZE 0x00000110u -#define CYREG_CLKDIST_CR 0x40004000u -#define CYREG_CLKDIST_LD 0x40004001u -#define CYREG_CLKDIST_WRK0 0x40004002u -#define CYREG_CLKDIST_WRK1 0x40004003u -#define CYREG_CLKDIST_MSTR0 0x40004004u -#define CYREG_CLKDIST_MSTR1 0x40004005u -#define CYREG_CLKDIST_BCFG0 0x40004006u -#define CYREG_CLKDIST_BCFG1 0x40004007u -#define CYREG_CLKDIST_BCFG2 0x40004008u -#define CYREG_CLKDIST_UCFG 0x40004009u -#define CYREG_CLKDIST_DLY0 0x4000400au -#define CYREG_CLKDIST_DLY1 0x4000400bu -#define CYREG_CLKDIST_DMASK 0x40004010u -#define CYREG_CLKDIST_AMASK 0x40004014u -#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u -#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u -#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u -#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u -#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u -#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u -#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u -#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u -#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u -#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u -#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u -#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au -#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu -#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu -#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du -#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu -#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u -#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u -#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u -#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u -#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u -#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u -#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u -#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u -#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u -#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u -#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u -#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au -#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu -#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u -#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu -#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du -#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu -#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u -#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u -#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u -#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u -#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u -#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u -#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u -#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u -#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u -#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u -#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u -#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u -#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u -#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u -#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u -#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u -#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au -#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu -#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu -#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u -#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu -#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du -#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu -#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu -#define CYDEV_FASTCLK_BASE 0x40004200u -#define CYDEV_FASTCLK_SIZE 0x00000026u -#define CYDEV_FASTCLK_IMO_BASE 0x40004200u -#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u -#define CYREG_FASTCLK_IMO_CR 0x40004200u -#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u -#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u -#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u -#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u -#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u -#define CYDEV_FASTCLK_PLL_BASE 0x40004220u -#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u -#define CYREG_FASTCLK_PLL_CFG0 0x40004220u -#define CYREG_FASTCLK_PLL_CFG1 0x40004221u -#define CYREG_FASTCLK_PLL_P 0x40004222u -#define CYREG_FASTCLK_PLL_Q 0x40004223u -#define CYREG_FASTCLK_PLL_SR 0x40004225u -#define CYDEV_SLOWCLK_BASE 0x40004300u -#define CYDEV_SLOWCLK_SIZE 0x0000000bu -#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u -#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u -#define CYREG_SLOWCLK_ILO_CR0 0x40004300u -#define CYREG_SLOWCLK_ILO_CR1 0x40004301u -#define CYDEV_SLOWCLK_X32_BASE 0x40004308u -#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u -#define CYREG_SLOWCLK_X32_CR 0x40004308u -#define CYREG_SLOWCLK_X32_CFG 0x40004309u -#define CYREG_SLOWCLK_X32_TST 0x4000430au -#define CYDEV_BOOST_BASE 0x40004320u -#define CYDEV_BOOST_SIZE 0x00000007u -#define CYREG_BOOST_CR0 0x40004320u -#define CYREG_BOOST_CR1 0x40004321u -#define CYREG_BOOST_CR2 0x40004322u -#define CYREG_BOOST_CR3 0x40004323u -#define CYREG_BOOST_SR 0x40004324u -#define CYREG_BOOST_CR4 0x40004325u -#define CYREG_BOOST_SR2 0x40004326u -#define CYDEV_PWRSYS_BASE 0x40004330u -#define CYDEV_PWRSYS_SIZE 0x00000002u -#define CYREG_PWRSYS_CR0 0x40004330u -#define CYREG_PWRSYS_CR1 0x40004331u -#define CYDEV_PM_BASE 0x40004380u -#define CYDEV_PM_SIZE 0x00000057u -#define CYREG_PM_TW_CFG0 0x40004380u -#define CYREG_PM_TW_CFG1 0x40004381u -#define CYREG_PM_TW_CFG2 0x40004382u -#define CYREG_PM_WDT_CFG 0x40004383u -#define CYREG_PM_WDT_CR 0x40004384u -#define CYREG_PM_INT_SR 0x40004390u -#define CYREG_PM_MODE_CFG0 0x40004391u -#define CYREG_PM_MODE_CFG1 0x40004392u -#define CYREG_PM_MODE_CSR 0x40004393u -#define CYREG_PM_USB_CR0 0x40004394u -#define CYREG_PM_WAKEUP_CFG0 0x40004398u -#define CYREG_PM_WAKEUP_CFG1 0x40004399u -#define CYREG_PM_WAKEUP_CFG2 0x4000439au -#define CYDEV_PM_ACT_BASE 0x400043a0u -#define CYDEV_PM_ACT_SIZE 0x0000000eu -#define CYREG_PM_ACT_CFG0 0x400043a0u -#define CYREG_PM_ACT_CFG1 0x400043a1u -#define CYREG_PM_ACT_CFG2 0x400043a2u -#define CYREG_PM_ACT_CFG3 0x400043a3u -#define CYREG_PM_ACT_CFG4 0x400043a4u -#define CYREG_PM_ACT_CFG5 0x400043a5u -#define CYREG_PM_ACT_CFG6 0x400043a6u -#define CYREG_PM_ACT_CFG7 0x400043a7u -#define CYREG_PM_ACT_CFG8 0x400043a8u -#define CYREG_PM_ACT_CFG9 0x400043a9u -#define CYREG_PM_ACT_CFG10 0x400043aau -#define CYREG_PM_ACT_CFG11 0x400043abu -#define CYREG_PM_ACT_CFG12 0x400043acu -#define CYREG_PM_ACT_CFG13 0x400043adu -#define CYDEV_PM_STBY_BASE 0x400043b0u -#define CYDEV_PM_STBY_SIZE 0x0000000eu -#define CYREG_PM_STBY_CFG0 0x400043b0u -#define CYREG_PM_STBY_CFG1 0x400043b1u -#define CYREG_PM_STBY_CFG2 0x400043b2u -#define CYREG_PM_STBY_CFG3 0x400043b3u -#define CYREG_PM_STBY_CFG4 0x400043b4u -#define CYREG_PM_STBY_CFG5 0x400043b5u -#define CYREG_PM_STBY_CFG6 0x400043b6u -#define CYREG_PM_STBY_CFG7 0x400043b7u -#define CYREG_PM_STBY_CFG8 0x400043b8u -#define CYREG_PM_STBY_CFG9 0x400043b9u -#define CYREG_PM_STBY_CFG10 0x400043bau -#define CYREG_PM_STBY_CFG11 0x400043bbu -#define CYREG_PM_STBY_CFG12 0x400043bcu -#define CYREG_PM_STBY_CFG13 0x400043bdu -#define CYDEV_PM_AVAIL_BASE 0x400043c0u -#define CYDEV_PM_AVAIL_SIZE 0x00000017u -#define CYREG_PM_AVAIL_CR0 0x400043c0u -#define CYREG_PM_AVAIL_CR1 0x400043c1u -#define CYREG_PM_AVAIL_CR2 0x400043c2u -#define CYREG_PM_AVAIL_CR3 0x400043c3u -#define CYREG_PM_AVAIL_CR4 0x400043c4u -#define CYREG_PM_AVAIL_CR5 0x400043c5u -#define CYREG_PM_AVAIL_CR6 0x400043c6u -#define CYREG_PM_AVAIL_SR0 0x400043d0u -#define CYREG_PM_AVAIL_SR1 0x400043d1u -#define CYREG_PM_AVAIL_SR2 0x400043d2u -#define CYREG_PM_AVAIL_SR3 0x400043d3u -#define CYREG_PM_AVAIL_SR4 0x400043d4u -#define CYREG_PM_AVAIL_SR5 0x400043d5u -#define CYREG_PM_AVAIL_SR6 0x400043d6u -#define CYDEV_PICU_BASE 0x40004500u -#define CYDEV_PICU_SIZE 0x000000b0u -#define CYDEV_PICU_INTTYPE_BASE 0x40004500u -#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u -#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u -#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u -#define CYREG_PICU0_INTTYPE0 0x40004500u -#define CYREG_PICU0_INTTYPE1 0x40004501u -#define CYREG_PICU0_INTTYPE2 0x40004502u -#define CYREG_PICU0_INTTYPE3 0x40004503u -#define CYREG_PICU0_INTTYPE4 0x40004504u -#define CYREG_PICU0_INTTYPE5 0x40004505u -#define CYREG_PICU0_INTTYPE6 0x40004506u -#define CYREG_PICU0_INTTYPE7 0x40004507u -#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u -#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u -#define CYREG_PICU1_INTTYPE0 0x40004508u -#define CYREG_PICU1_INTTYPE1 0x40004509u -#define CYREG_PICU1_INTTYPE2 0x4000450au -#define CYREG_PICU1_INTTYPE3 0x4000450bu -#define CYREG_PICU1_INTTYPE4 0x4000450cu -#define CYREG_PICU1_INTTYPE5 0x4000450du -#define CYREG_PICU1_INTTYPE6 0x4000450eu -#define CYREG_PICU1_INTTYPE7 0x4000450fu -#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u -#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u -#define CYREG_PICU2_INTTYPE0 0x40004510u -#define CYREG_PICU2_INTTYPE1 0x40004511u -#define CYREG_PICU2_INTTYPE2 0x40004512u -#define CYREG_PICU2_INTTYPE3 0x40004513u -#define CYREG_PICU2_INTTYPE4 0x40004514u -#define CYREG_PICU2_INTTYPE5 0x40004515u -#define CYREG_PICU2_INTTYPE6 0x40004516u -#define CYREG_PICU2_INTTYPE7 0x40004517u -#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u -#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u -#define CYREG_PICU3_INTTYPE0 0x40004518u -#define CYREG_PICU3_INTTYPE1 0x40004519u -#define CYREG_PICU3_INTTYPE2 0x4000451au -#define CYREG_PICU3_INTTYPE3 0x4000451bu -#define CYREG_PICU3_INTTYPE4 0x4000451cu -#define CYREG_PICU3_INTTYPE5 0x4000451du -#define CYREG_PICU3_INTTYPE6 0x4000451eu -#define CYREG_PICU3_INTTYPE7 0x4000451fu -#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u -#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u -#define CYREG_PICU4_INTTYPE0 0x40004520u -#define CYREG_PICU4_INTTYPE1 0x40004521u -#define CYREG_PICU4_INTTYPE2 0x40004522u -#define CYREG_PICU4_INTTYPE3 0x40004523u -#define CYREG_PICU4_INTTYPE4 0x40004524u -#define CYREG_PICU4_INTTYPE5 0x40004525u -#define CYREG_PICU4_INTTYPE6 0x40004526u -#define CYREG_PICU4_INTTYPE7 0x40004527u -#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u -#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u -#define CYREG_PICU5_INTTYPE0 0x40004528u -#define CYREG_PICU5_INTTYPE1 0x40004529u -#define CYREG_PICU5_INTTYPE2 0x4000452au -#define CYREG_PICU5_INTTYPE3 0x4000452bu -#define CYREG_PICU5_INTTYPE4 0x4000452cu -#define CYREG_PICU5_INTTYPE5 0x4000452du -#define CYREG_PICU5_INTTYPE6 0x4000452eu -#define CYREG_PICU5_INTTYPE7 0x4000452fu -#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u -#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u -#define CYREG_PICU6_INTTYPE0 0x40004530u -#define CYREG_PICU6_INTTYPE1 0x40004531u -#define CYREG_PICU6_INTTYPE2 0x40004532u -#define CYREG_PICU6_INTTYPE3 0x40004533u -#define CYREG_PICU6_INTTYPE4 0x40004534u -#define CYREG_PICU6_INTTYPE5 0x40004535u -#define CYREG_PICU6_INTTYPE6 0x40004536u -#define CYREG_PICU6_INTTYPE7 0x40004537u -#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u -#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u -#define CYREG_PICU12_INTTYPE0 0x40004560u -#define CYREG_PICU12_INTTYPE1 0x40004561u -#define CYREG_PICU12_INTTYPE2 0x40004562u -#define CYREG_PICU12_INTTYPE3 0x40004563u -#define CYREG_PICU12_INTTYPE4 0x40004564u -#define CYREG_PICU12_INTTYPE5 0x40004565u -#define CYREG_PICU12_INTTYPE6 0x40004566u -#define CYREG_PICU12_INTTYPE7 0x40004567u -#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u -#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u -#define CYREG_PICU15_INTTYPE0 0x40004578u -#define CYREG_PICU15_INTTYPE1 0x40004579u -#define CYREG_PICU15_INTTYPE2 0x4000457au -#define CYREG_PICU15_INTTYPE3 0x4000457bu -#define CYREG_PICU15_INTTYPE4 0x4000457cu -#define CYREG_PICU15_INTTYPE5 0x4000457du -#define CYREG_PICU15_INTTYPE6 0x4000457eu -#define CYREG_PICU15_INTTYPE7 0x4000457fu -#define CYDEV_PICU_STAT_BASE 0x40004580u -#define CYDEV_PICU_STAT_SIZE 0x00000010u -#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u -#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u -#define CYREG_PICU0_INTSTAT 0x40004580u -#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u -#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u -#define CYREG_PICU1_INTSTAT 0x40004581u -#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u -#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u -#define CYREG_PICU2_INTSTAT 0x40004582u -#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u -#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u -#define CYREG_PICU3_INTSTAT 0x40004583u -#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u -#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u -#define CYREG_PICU4_INTSTAT 0x40004584u -#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u -#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u -#define CYREG_PICU5_INTSTAT 0x40004585u -#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u -#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u -#define CYREG_PICU6_INTSTAT 0x40004586u -#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu -#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u -#define CYREG_PICU12_INTSTAT 0x4000458cu -#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu -#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u -#define CYREG_PICU15_INTSTAT 0x4000458fu -#define CYDEV_PICU_SNAP_BASE 0x40004590u -#define CYDEV_PICU_SNAP_SIZE 0x00000010u -#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u -#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u -#define CYREG_PICU0_SNAP 0x40004590u -#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u -#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u -#define CYREG_PICU1_SNAP 0x40004591u -#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u -#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u -#define CYREG_PICU2_SNAP 0x40004592u -#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u -#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u -#define CYREG_PICU3_SNAP 0x40004593u -#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u -#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u -#define CYREG_PICU4_SNAP 0x40004594u -#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u -#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u -#define CYREG_PICU5_SNAP 0x40004595u -#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u -#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u -#define CYREG_PICU6_SNAP 0x40004596u -#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu -#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u -#define CYREG_PICU12_SNAP 0x4000459cu -#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu -#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u -#define CYREG_PICU_15_SNAP_15 0x4000459fu -#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u -#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u -#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u -#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u -#define CYREG_PICU0_DISABLE_COR 0x400045a0u -#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u -#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u -#define CYREG_PICU1_DISABLE_COR 0x400045a1u -#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u -#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u -#define CYREG_PICU2_DISABLE_COR 0x400045a2u -#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u -#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u -#define CYREG_PICU3_DISABLE_COR 0x400045a3u -#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u -#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u -#define CYREG_PICU4_DISABLE_COR 0x400045a4u -#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u -#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u -#define CYREG_PICU5_DISABLE_COR 0x400045a5u -#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u -#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u -#define CYREG_PICU6_DISABLE_COR 0x400045a6u -#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu -#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u -#define CYREG_PICU12_DISABLE_COR 0x400045acu -#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu -#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u -#define CYREG_PICU15_DISABLE_COR 0x400045afu -#define CYDEV_MFGCFG_BASE 0x40004600u -#define CYDEV_MFGCFG_SIZE 0x000000edu -#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u -#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u -#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u -#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u -#define CYREG_DAC0_TR 0x40004608u -#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u -#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u -#define CYREG_DAC1_TR 0x40004609u -#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au -#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u -#define CYREG_DAC2_TR 0x4000460au -#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu -#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u -#define CYREG_DAC3_TR 0x4000460bu -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u -#define CYREG_NPUMP_DSM_TR0 0x40004610u -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u -#define CYREG_NPUMP_SC_TR0 0x40004611u -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u -#define CYREG_NPUMP_OPAMP_TR0 0x40004612u -#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u -#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u -#define CYREG_SAR0_TR0 0x40004614u -#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u -#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u -#define CYREG_SAR1_TR0 0x40004616u -#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u -#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u -#define CYREG_OPAMP0_TR0 0x40004620u -#define CYREG_OPAMP0_TR1 0x40004621u -#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u -#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u -#define CYREG_OPAMP1_TR0 0x40004622u -#define CYREG_OPAMP1_TR1 0x40004623u -#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u -#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u -#define CYREG_OPAMP2_TR0 0x40004624u -#define CYREG_OPAMP2_TR1 0x40004625u -#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u -#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u -#define CYREG_OPAMP3_TR0 0x40004626u -#define CYREG_OPAMP3_TR1 0x40004627u -#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u -#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u -#define CYREG_CMP0_TR0 0x40004630u -#define CYREG_CMP0_TR1 0x40004631u -#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u -#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u -#define CYREG_CMP1_TR0 0x40004632u -#define CYREG_CMP1_TR1 0x40004633u -#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u -#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u -#define CYREG_CMP2_TR0 0x40004634u -#define CYREG_CMP2_TR1 0x40004635u -#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u -#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u -#define CYREG_CMP3_TR0 0x40004636u -#define CYREG_CMP3_TR1 0x40004637u -#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u -#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu -#define CYREG_PWRSYS_HIB_TR0 0x40004680u -#define CYREG_PWRSYS_HIB_TR1 0x40004681u -#define CYREG_PWRSYS_I2C_TR 0x40004682u -#define CYREG_PWRSYS_SLP_TR 0x40004683u -#define CYREG_PWRSYS_BUZZ_TR 0x40004684u -#define CYREG_PWRSYS_WAKE_TR0 0x40004685u -#define CYREG_PWRSYS_WAKE_TR1 0x40004686u -#define CYREG_PWRSYS_BREF_TR 0x40004687u -#define CYREG_PWRSYS_BG_TR 0x40004688u -#define CYREG_PWRSYS_WAKE_TR2 0x40004689u -#define CYREG_PWRSYS_WAKE_TR3 0x4000468au -#define CYDEV_MFGCFG_ILO_BASE 0x40004690u -#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u -#define CYREG_ILO_TR0 0x40004690u -#define CYREG_ILO_TR1 0x40004691u -#define CYDEV_MFGCFG_X32_BASE 0x40004698u -#define CYDEV_MFGCFG_X32_SIZE 0x00000001u -#define CYREG_X32_TR 0x40004698u -#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u -#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u -#define CYREG_IMO_TR0 0x400046a0u -#define CYREG_IMO_TR1 0x400046a1u -#define CYREG_IMO_GAIN 0x400046a2u -#define CYREG_IMO_C36M 0x400046a3u -#define CYREG_IMO_TR2 0x400046a4u -#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u -#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u -#define CYREG_XMHZ_TR 0x400046a8u -#define CYREG_MFGCFG_DLY 0x400046c0u -#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u -#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du -#define CYREG_MLOGIC_DMPSTR 0x400046e2u -#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u -#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u -#define CYREG_MLOGIC_SEG_CR 0x400046e4u -#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u -#define CYREG_MLOGIC_DEBUG 0x400046e8u -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u -#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau -#define CYREG_MLOGIC_REV_ID 0x400046ecu -#define CYDEV_RESET_BASE 0x400046f0u -#define CYDEV_RESET_SIZE 0x0000000fu -#define CYREG_RESET_IPOR_CR0 0x400046f0u -#define CYREG_RESET_IPOR_CR1 0x400046f1u -#define CYREG_RESET_IPOR_CR2 0x400046f2u -#define CYREG_RESET_IPOR_CR3 0x400046f3u -#define CYREG_RESET_CR0 0x400046f4u -#define CYREG_RESET_CR1 0x400046f5u -#define CYREG_RESET_CR2 0x400046f6u -#define CYREG_RESET_CR3 0x400046f7u -#define CYREG_RESET_CR4 0x400046f8u -#define CYREG_RESET_CR5 0x400046f9u -#define CYREG_RESET_SR0 0x400046fau -#define CYREG_RESET_SR1 0x400046fbu -#define CYREG_RESET_SR2 0x400046fcu -#define CYREG_RESET_SR3 0x400046fdu -#define CYREG_RESET_TR 0x400046feu -#define CYDEV_SPC_BASE 0x40004700u -#define CYDEV_SPC_SIZE 0x00000100u -#define CYREG_SPC_FM_EE_CR 0x40004700u -#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u -#define CYREG_SPC_EE_SCR 0x40004702u -#define CYREG_SPC_EE_ERR 0x40004703u -#define CYREG_SPC_CPU_DATA 0x40004720u -#define CYREG_SPC_DMA_DATA 0x40004721u -#define CYREG_SPC_SR 0x40004722u -#define CYREG_SPC_CR 0x40004723u -#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u -#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u -#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u -#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u -#define CYDEV_CACHE_BASE 0x40004800u -#define CYDEV_CACHE_SIZE 0x0000009cu -#define CYREG_CACHE_CC_CTL 0x40004800u -#define CYREG_CACHE_ECC_CORR 0x40004880u -#define CYREG_CACHE_ECC_ERR 0x40004888u -#define CYREG_CACHE_FLASH_ERR 0x40004890u -#define CYREG_CACHE_HITMISS 0x40004898u -#define CYDEV_I2C_BASE 0x40004900u -#define CYDEV_I2C_SIZE 0x000000e1u -#define CYREG_I2C_XCFG 0x400049c8u -#define CYREG_I2C_ADR 0x400049cau -#define CYREG_I2C_CFG 0x400049d6u -#define CYREG_I2C_CSR 0x400049d7u -#define CYREG_I2C_D 0x400049d8u -#define CYREG_I2C_MCSR 0x400049d9u -#define CYREG_I2C_CLK_DIV1 0x400049dbu -#define CYREG_I2C_CLK_DIV2 0x400049dcu -#define CYREG_I2C_TMOUT_CSR 0x400049ddu -#define CYREG_I2C_TMOUT_SR 0x400049deu -#define CYREG_I2C_TMOUT_CFG0 0x400049dfu -#define CYREG_I2C_TMOUT_CFG1 0x400049e0u -#define CYDEV_DEC_BASE 0x40004e00u -#define CYDEV_DEC_SIZE 0x00000015u -#define CYREG_DEC_CR 0x40004e00u -#define CYREG_DEC_SR 0x40004e01u -#define CYREG_DEC_SHIFT1 0x40004e02u -#define CYREG_DEC_SHIFT2 0x40004e03u -#define CYREG_DEC_DR2 0x40004e04u -#define CYREG_DEC_DR2H 0x40004e05u -#define CYREG_DEC_DR1 0x40004e06u -#define CYREG_DEC_OCOR 0x40004e08u -#define CYREG_DEC_OCORM 0x40004e09u -#define CYREG_DEC_OCORH 0x40004e0au -#define CYREG_DEC_GCOR 0x40004e0cu -#define CYREG_DEC_GCORH 0x40004e0du -#define CYREG_DEC_GVAL 0x40004e0eu -#define CYREG_DEC_OUTSAMP 0x40004e10u -#define CYREG_DEC_OUTSAMPM 0x40004e11u -#define CYREG_DEC_OUTSAMPH 0x40004e12u -#define CYREG_DEC_OUTSAMPS 0x40004e13u -#define CYREG_DEC_COHER 0x40004e14u -#define CYDEV_TMR0_BASE 0x40004f00u -#define CYDEV_TMR0_SIZE 0x0000000cu -#define CYREG_TMR0_CFG0 0x40004f00u -#define CYREG_TMR0_CFG1 0x40004f01u -#define CYREG_TMR0_CFG2 0x40004f02u -#define CYREG_TMR0_SR0 0x40004f03u -#define CYREG_TMR0_PER0 0x40004f04u -#define CYREG_TMR0_PER1 0x40004f05u -#define CYREG_TMR0_CNT_CMP0 0x40004f06u -#define CYREG_TMR0_CNT_CMP1 0x40004f07u -#define CYREG_TMR0_CAP0 0x40004f08u -#define CYREG_TMR0_CAP1 0x40004f09u -#define CYREG_TMR0_RT0 0x40004f0au -#define CYREG_TMR0_RT1 0x40004f0bu -#define CYDEV_TMR1_BASE 0x40004f0cu -#define CYDEV_TMR1_SIZE 0x0000000cu -#define CYREG_TMR1_CFG0 0x40004f0cu -#define CYREG_TMR1_CFG1 0x40004f0du -#define CYREG_TMR1_CFG2 0x40004f0eu -#define CYREG_TMR1_SR0 0x40004f0fu -#define CYREG_TMR1_PER0 0x40004f10u -#define CYREG_TMR1_PER1 0x40004f11u -#define CYREG_TMR1_CNT_CMP0 0x40004f12u -#define CYREG_TMR1_CNT_CMP1 0x40004f13u -#define CYREG_TMR1_CAP0 0x40004f14u -#define CYREG_TMR1_CAP1 0x40004f15u -#define CYREG_TMR1_RT0 0x40004f16u -#define CYREG_TMR1_RT1 0x40004f17u -#define CYDEV_TMR2_BASE 0x40004f18u -#define CYDEV_TMR2_SIZE 0x0000000cu -#define CYREG_TMR2_CFG0 0x40004f18u -#define CYREG_TMR2_CFG1 0x40004f19u -#define CYREG_TMR2_CFG2 0x40004f1au -#define CYREG_TMR2_SR0 0x40004f1bu -#define CYREG_TMR2_PER0 0x40004f1cu -#define CYREG_TMR2_PER1 0x40004f1du -#define CYREG_TMR2_CNT_CMP0 0x40004f1eu -#define CYREG_TMR2_CNT_CMP1 0x40004f1fu -#define CYREG_TMR2_CAP0 0x40004f20u -#define CYREG_TMR2_CAP1 0x40004f21u -#define CYREG_TMR2_RT0 0x40004f22u -#define CYREG_TMR2_RT1 0x40004f23u -#define CYDEV_TMR3_BASE 0x40004f24u -#define CYDEV_TMR3_SIZE 0x0000000cu -#define CYREG_TMR3_CFG0 0x40004f24u -#define CYREG_TMR3_CFG1 0x40004f25u -#define CYREG_TMR3_CFG2 0x40004f26u -#define CYREG_TMR3_SR0 0x40004f27u -#define CYREG_TMR3_PER0 0x40004f28u -#define CYREG_TMR3_PER1 0x40004f29u -#define CYREG_TMR3_CNT_CMP0 0x40004f2au -#define CYREG_TMR3_CNT_CMP1 0x40004f2bu -#define CYREG_TMR3_CAP0 0x40004f2cu -#define CYREG_TMR3_CAP1 0x40004f2du -#define CYREG_TMR3_RT0 0x40004f2eu -#define CYREG_TMR3_RT1 0x40004f2fu -#define CYDEV_IO_BASE 0x40005000u -#define CYDEV_IO_SIZE 0x00000200u -#define CYDEV_IO_PC_BASE 0x40005000u -#define CYDEV_IO_PC_SIZE 0x00000080u -#define CYDEV_IO_PC_PRT0_BASE 0x40005000u -#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u -#define CYREG_PRT0_PC0 0x40005000u -#define CYREG_PRT0_PC1 0x40005001u -#define CYREG_PRT0_PC2 0x40005002u -#define CYREG_PRT0_PC3 0x40005003u -#define CYREG_PRT0_PC4 0x40005004u -#define CYREG_PRT0_PC5 0x40005005u -#define CYREG_PRT0_PC6 0x40005006u -#define CYREG_PRT0_PC7 0x40005007u -#define CYDEV_IO_PC_PRT1_BASE 0x40005008u -#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u -#define CYREG_PRT1_PC0 0x40005008u -#define CYREG_PRT1_PC1 0x40005009u -#define CYREG_PRT1_PC2 0x4000500au -#define CYREG_PRT1_PC3 0x4000500bu -#define CYREG_PRT1_PC4 0x4000500cu -#define CYREG_PRT1_PC5 0x4000500du -#define CYREG_PRT1_PC6 0x4000500eu -#define CYREG_PRT1_PC7 0x4000500fu -#define CYDEV_IO_PC_PRT2_BASE 0x40005010u -#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u -#define CYREG_PRT2_PC0 0x40005010u -#define CYREG_PRT2_PC1 0x40005011u -#define CYREG_PRT2_PC2 0x40005012u -#define CYREG_PRT2_PC3 0x40005013u -#define CYREG_PRT2_PC4 0x40005014u -#define CYREG_PRT2_PC5 0x40005015u -#define CYREG_PRT2_PC6 0x40005016u -#define CYREG_PRT2_PC7 0x40005017u -#define CYDEV_IO_PC_PRT3_BASE 0x40005018u -#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u -#define CYREG_PRT3_PC0 0x40005018u -#define CYREG_PRT3_PC1 0x40005019u -#define CYREG_PRT3_PC2 0x4000501au -#define CYREG_PRT3_PC3 0x4000501bu -#define CYREG_PRT3_PC4 0x4000501cu -#define CYREG_PRT3_PC5 0x4000501du -#define CYREG_PRT3_PC6 0x4000501eu -#define CYREG_PRT3_PC7 0x4000501fu -#define CYDEV_IO_PC_PRT4_BASE 0x40005020u -#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u -#define CYREG_PRT4_PC0 0x40005020u -#define CYREG_PRT4_PC1 0x40005021u -#define CYREG_PRT4_PC2 0x40005022u -#define CYREG_PRT4_PC3 0x40005023u -#define CYREG_PRT4_PC4 0x40005024u -#define CYREG_PRT4_PC5 0x40005025u -#define CYREG_PRT4_PC6 0x40005026u -#define CYREG_PRT4_PC7 0x40005027u -#define CYDEV_IO_PC_PRT5_BASE 0x40005028u -#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u -#define CYREG_PRT5_PC0 0x40005028u -#define CYREG_PRT5_PC1 0x40005029u -#define CYREG_PRT5_PC2 0x4000502au -#define CYREG_PRT5_PC3 0x4000502bu -#define CYREG_PRT5_PC4 0x4000502cu -#define CYREG_PRT5_PC5 0x4000502du -#define CYREG_PRT5_PC6 0x4000502eu -#define CYREG_PRT5_PC7 0x4000502fu -#define CYDEV_IO_PC_PRT6_BASE 0x40005030u -#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u -#define CYREG_PRT6_PC0 0x40005030u -#define CYREG_PRT6_PC1 0x40005031u -#define CYREG_PRT6_PC2 0x40005032u -#define CYREG_PRT6_PC3 0x40005033u -#define CYREG_PRT6_PC4 0x40005034u -#define CYREG_PRT6_PC5 0x40005035u -#define CYREG_PRT6_PC6 0x40005036u -#define CYREG_PRT6_PC7 0x40005037u -#define CYDEV_IO_PC_PRT12_BASE 0x40005060u -#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u -#define CYREG_PRT12_PC0 0x40005060u -#define CYREG_PRT12_PC1 0x40005061u -#define CYREG_PRT12_PC2 0x40005062u -#define CYREG_PRT12_PC3 0x40005063u -#define CYREG_PRT12_PC4 0x40005064u -#define CYREG_PRT12_PC5 0x40005065u -#define CYREG_PRT12_PC6 0x40005066u -#define CYREG_PRT12_PC7 0x40005067u -#define CYDEV_IO_PC_PRT15_BASE 0x40005078u -#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u -#define CYREG_IO_PC_PRT15_PC0 0x40005078u -#define CYREG_IO_PC_PRT15_PC1 0x40005079u -#define CYREG_IO_PC_PRT15_PC2 0x4000507au -#define CYREG_IO_PC_PRT15_PC3 0x4000507bu -#define CYREG_IO_PC_PRT15_PC4 0x4000507cu -#define CYREG_IO_PC_PRT15_PC5 0x4000507du -#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu -#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u -#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu -#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu -#define CYDEV_IO_DR_BASE 0x40005080u -#define CYDEV_IO_DR_SIZE 0x00000010u -#define CYDEV_IO_DR_PRT0_BASE 0x40005080u -#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u -#define CYREG_PRT0_DR_ALIAS 0x40005080u -#define CYDEV_IO_DR_PRT1_BASE 0x40005081u -#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u -#define CYREG_PRT1_DR_ALIAS 0x40005081u -#define CYDEV_IO_DR_PRT2_BASE 0x40005082u -#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u -#define CYREG_PRT2_DR_ALIAS 0x40005082u -#define CYDEV_IO_DR_PRT3_BASE 0x40005083u -#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u -#define CYREG_PRT3_DR_ALIAS 0x40005083u -#define CYDEV_IO_DR_PRT4_BASE 0x40005084u -#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u -#define CYREG_PRT4_DR_ALIAS 0x40005084u -#define CYDEV_IO_DR_PRT5_BASE 0x40005085u -#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u -#define CYREG_PRT5_DR_ALIAS 0x40005085u -#define CYDEV_IO_DR_PRT6_BASE 0x40005086u -#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u -#define CYREG_PRT6_DR_ALIAS 0x40005086u -#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu -#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u -#define CYREG_PRT12_DR_ALIAS 0x4000508cu -#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu -#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u -#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu -#define CYDEV_IO_PS_BASE 0x40005090u -#define CYDEV_IO_PS_SIZE 0x00000010u -#define CYDEV_IO_PS_PRT0_BASE 0x40005090u -#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u -#define CYREG_PRT0_PS_ALIAS 0x40005090u -#define CYDEV_IO_PS_PRT1_BASE 0x40005091u -#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u -#define CYREG_PRT1_PS_ALIAS 0x40005091u -#define CYDEV_IO_PS_PRT2_BASE 0x40005092u -#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u -#define CYREG_PRT2_PS_ALIAS 0x40005092u -#define CYDEV_IO_PS_PRT3_BASE 0x40005093u -#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u -#define CYREG_PRT3_PS_ALIAS 0x40005093u -#define CYDEV_IO_PS_PRT4_BASE 0x40005094u -#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u -#define CYREG_PRT4_PS_ALIAS 0x40005094u -#define CYDEV_IO_PS_PRT5_BASE 0x40005095u -#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u -#define CYREG_PRT5_PS_ALIAS 0x40005095u -#define CYDEV_IO_PS_PRT6_BASE 0x40005096u -#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u -#define CYREG_PRT6_PS_ALIAS 0x40005096u -#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu -#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u -#define CYREG_PRT12_PS_ALIAS 0x4000509cu -#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu -#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u -#define CYREG_PRT15_PS15_ALIAS 0x4000509fu -#define CYDEV_IO_PRT_BASE 0x40005100u -#define CYDEV_IO_PRT_SIZE 0x00000100u -#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u -#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u -#define CYREG_PRT0_DR 0x40005100u -#define CYREG_PRT0_PS 0x40005101u -#define CYREG_PRT0_DM0 0x40005102u -#define CYREG_PRT0_DM1 0x40005103u -#define CYREG_PRT0_DM2 0x40005104u -#define CYREG_PRT0_SLW 0x40005105u -#define CYREG_PRT0_BYP 0x40005106u -#define CYREG_PRT0_BIE 0x40005107u -#define CYREG_PRT0_INP_DIS 0x40005108u -#define CYREG_PRT0_CTL 0x40005109u -#define CYREG_PRT0_PRT 0x4000510au -#define CYREG_PRT0_BIT_MASK 0x4000510bu -#define CYREG_PRT0_AMUX 0x4000510cu -#define CYREG_PRT0_AG 0x4000510du -#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu -#define CYREG_PRT0_LCD_EN 0x4000510fu -#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u -#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u -#define CYREG_PRT1_DR 0x40005110u -#define CYREG_PRT1_PS 0x40005111u -#define CYREG_PRT1_DM0 0x40005112u -#define CYREG_PRT1_DM1 0x40005113u -#define CYREG_PRT1_DM2 0x40005114u -#define CYREG_PRT1_SLW 0x40005115u -#define CYREG_PRT1_BYP 0x40005116u -#define CYREG_PRT1_BIE 0x40005117u -#define CYREG_PRT1_INP_DIS 0x40005118u -#define CYREG_PRT1_CTL 0x40005119u -#define CYREG_PRT1_PRT 0x4000511au -#define CYREG_PRT1_BIT_MASK 0x4000511bu -#define CYREG_PRT1_AMUX 0x4000511cu -#define CYREG_PRT1_AG 0x4000511du -#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu -#define CYREG_PRT1_LCD_EN 0x4000511fu -#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u -#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u -#define CYREG_PRT2_DR 0x40005120u -#define CYREG_PRT2_PS 0x40005121u -#define CYREG_PRT2_DM0 0x40005122u -#define CYREG_PRT2_DM1 0x40005123u -#define CYREG_PRT2_DM2 0x40005124u -#define CYREG_PRT2_SLW 0x40005125u -#define CYREG_PRT2_BYP 0x40005126u -#define CYREG_PRT2_BIE 0x40005127u -#define CYREG_PRT2_INP_DIS 0x40005128u -#define CYREG_PRT2_CTL 0x40005129u -#define CYREG_PRT2_PRT 0x4000512au -#define CYREG_PRT2_BIT_MASK 0x4000512bu -#define CYREG_PRT2_AMUX 0x4000512cu -#define CYREG_PRT2_AG 0x4000512du -#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu -#define CYREG_PRT2_LCD_EN 0x4000512fu -#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u -#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u -#define CYREG_PRT3_DR 0x40005130u -#define CYREG_PRT3_PS 0x40005131u -#define CYREG_PRT3_DM0 0x40005132u -#define CYREG_PRT3_DM1 0x40005133u -#define CYREG_PRT3_DM2 0x40005134u -#define CYREG_PRT3_SLW 0x40005135u -#define CYREG_PRT3_BYP 0x40005136u -#define CYREG_PRT3_BIE 0x40005137u -#define CYREG_PRT3_INP_DIS 0x40005138u -#define CYREG_PRT3_CTL 0x40005139u -#define CYREG_PRT3_PRT 0x4000513au -#define CYREG_PRT3_BIT_MASK 0x4000513bu -#define CYREG_PRT3_AMUX 0x4000513cu -#define CYREG_PRT3_AG 0x4000513du -#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu -#define CYREG_PRT3_LCD_EN 0x4000513fu -#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u -#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u -#define CYREG_PRT4_DR 0x40005140u -#define CYREG_PRT4_PS 0x40005141u -#define CYREG_PRT4_DM0 0x40005142u -#define CYREG_PRT4_DM1 0x40005143u -#define CYREG_PRT4_DM2 0x40005144u -#define CYREG_PRT4_SLW 0x40005145u -#define CYREG_PRT4_BYP 0x40005146u -#define CYREG_PRT4_BIE 0x40005147u -#define CYREG_PRT4_INP_DIS 0x40005148u -#define CYREG_PRT4_CTL 0x40005149u -#define CYREG_PRT4_PRT 0x4000514au -#define CYREG_PRT4_BIT_MASK 0x4000514bu -#define CYREG_PRT4_AMUX 0x4000514cu -#define CYREG_PRT4_AG 0x4000514du -#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu -#define CYREG_PRT4_LCD_EN 0x4000514fu -#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u -#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u -#define CYREG_PRT5_DR 0x40005150u -#define CYREG_PRT5_PS 0x40005151u -#define CYREG_PRT5_DM0 0x40005152u -#define CYREG_PRT5_DM1 0x40005153u -#define CYREG_PRT5_DM2 0x40005154u -#define CYREG_PRT5_SLW 0x40005155u -#define CYREG_PRT5_BYP 0x40005156u -#define CYREG_PRT5_BIE 0x40005157u -#define CYREG_PRT5_INP_DIS 0x40005158u -#define CYREG_PRT5_CTL 0x40005159u -#define CYREG_PRT5_PRT 0x4000515au -#define CYREG_PRT5_BIT_MASK 0x4000515bu -#define CYREG_PRT5_AMUX 0x4000515cu -#define CYREG_PRT5_AG 0x4000515du -#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu -#define CYREG_PRT5_LCD_EN 0x4000515fu -#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u -#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u -#define CYREG_PRT6_DR 0x40005160u -#define CYREG_PRT6_PS 0x40005161u -#define CYREG_PRT6_DM0 0x40005162u -#define CYREG_PRT6_DM1 0x40005163u -#define CYREG_PRT6_DM2 0x40005164u -#define CYREG_PRT6_SLW 0x40005165u -#define CYREG_PRT6_BYP 0x40005166u -#define CYREG_PRT6_BIE 0x40005167u -#define CYREG_PRT6_INP_DIS 0x40005168u -#define CYREG_PRT6_CTL 0x40005169u -#define CYREG_PRT6_PRT 0x4000516au -#define CYREG_PRT6_BIT_MASK 0x4000516bu -#define CYREG_PRT6_AMUX 0x4000516cu -#define CYREG_PRT6_AG 0x4000516du -#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu -#define CYREG_PRT6_LCD_EN 0x4000516fu -#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u -#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u -#define CYREG_PRT12_DR 0x400051c0u -#define CYREG_PRT12_PS 0x400051c1u -#define CYREG_PRT12_DM0 0x400051c2u -#define CYREG_PRT12_DM1 0x400051c3u -#define CYREG_PRT12_DM2 0x400051c4u -#define CYREG_PRT12_SLW 0x400051c5u -#define CYREG_PRT12_BYP 0x400051c6u -#define CYREG_PRT12_BIE 0x400051c7u -#define CYREG_PRT12_INP_DIS 0x400051c8u -#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u -#define CYREG_PRT12_PRT 0x400051cau -#define CYREG_PRT12_BIT_MASK 0x400051cbu -#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu -#define CYREG_PRT12_AG 0x400051cdu -#define CYREG_PRT12_SIO_CFG 0x400051ceu -#define CYREG_PRT12_SIO_DIFF 0x400051cfu -#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u -#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u -#define CYREG_PRT15_DR 0x400051f0u -#define CYREG_PRT15_PS 0x400051f1u -#define CYREG_PRT15_DM0 0x400051f2u -#define CYREG_PRT15_DM1 0x400051f3u -#define CYREG_PRT15_DM2 0x400051f4u -#define CYREG_PRT15_SLW 0x400051f5u -#define CYREG_PRT15_BYP 0x400051f6u -#define CYREG_PRT15_BIE 0x400051f7u -#define CYREG_PRT15_INP_DIS 0x400051f8u -#define CYREG_PRT15_CTL 0x400051f9u -#define CYREG_PRT15_PRT 0x400051fau -#define CYREG_PRT15_BIT_MASK 0x400051fbu -#define CYREG_PRT15_AMUX 0x400051fcu -#define CYREG_PRT15_AG 0x400051fdu -#define CYREG_PRT15_LCD_COM_SEG 0x400051feu -#define CYREG_PRT15_LCD_EN 0x400051ffu -#define CYDEV_PRTDSI_BASE 0x40005200u -#define CYDEV_PRTDSI_SIZE 0x0000007fu -#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u -#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u -#define CYREG_PRT0_OUT_SEL0 0x40005200u -#define CYREG_PRT0_OUT_SEL1 0x40005201u -#define CYREG_PRT0_OE_SEL0 0x40005202u -#define CYREG_PRT0_OE_SEL1 0x40005203u -#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u -#define CYREG_PRT0_SYNC_OUT 0x40005205u -#define CYREG_PRT0_CAPS_SEL 0x40005206u -#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u -#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u -#define CYREG_PRT1_OUT_SEL0 0x40005208u -#define CYREG_PRT1_OUT_SEL1 0x40005209u -#define CYREG_PRT1_OE_SEL0 0x4000520au -#define CYREG_PRT1_OE_SEL1 0x4000520bu -#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu -#define CYREG_PRT1_SYNC_OUT 0x4000520du -#define CYREG_PRT1_CAPS_SEL 0x4000520eu -#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u -#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u -#define CYREG_PRT2_OUT_SEL0 0x40005210u -#define CYREG_PRT2_OUT_SEL1 0x40005211u -#define CYREG_PRT2_OE_SEL0 0x40005212u -#define CYREG_PRT2_OE_SEL1 0x40005213u -#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u -#define CYREG_PRT2_SYNC_OUT 0x40005215u -#define CYREG_PRT2_CAPS_SEL 0x40005216u -#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u -#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u -#define CYREG_PRT3_OUT_SEL0 0x40005218u -#define CYREG_PRT3_OUT_SEL1 0x40005219u -#define CYREG_PRT3_OE_SEL0 0x4000521au -#define CYREG_PRT3_OE_SEL1 0x4000521bu -#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu -#define CYREG_PRT3_SYNC_OUT 0x4000521du -#define CYREG_PRT3_CAPS_SEL 0x4000521eu -#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u -#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u -#define CYREG_PRT4_OUT_SEL0 0x40005220u -#define CYREG_PRT4_OUT_SEL1 0x40005221u -#define CYREG_PRT4_OE_SEL0 0x40005222u -#define CYREG_PRT4_OE_SEL1 0x40005223u -#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u -#define CYREG_PRT4_SYNC_OUT 0x40005225u -#define CYREG_PRT4_CAPS_SEL 0x40005226u -#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u -#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u -#define CYREG_PRT5_OUT_SEL0 0x40005228u -#define CYREG_PRT5_OUT_SEL1 0x40005229u -#define CYREG_PRT5_OE_SEL0 0x4000522au -#define CYREG_PRT5_OE_SEL1 0x4000522bu -#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu -#define CYREG_PRT5_SYNC_OUT 0x4000522du -#define CYREG_PRT5_CAPS_SEL 0x4000522eu -#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u -#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u -#define CYREG_PRT6_OUT_SEL0 0x40005230u -#define CYREG_PRT6_OUT_SEL1 0x40005231u -#define CYREG_PRT6_OE_SEL0 0x40005232u -#define CYREG_PRT6_OE_SEL1 0x40005233u -#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u -#define CYREG_PRT6_SYNC_OUT 0x40005235u -#define CYREG_PRT6_CAPS_SEL 0x40005236u -#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u -#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u -#define CYREG_PRT12_OUT_SEL0 0x40005260u -#define CYREG_PRT12_OUT_SEL1 0x40005261u -#define CYREG_PRT12_OE_SEL0 0x40005262u -#define CYREG_PRT12_OE_SEL1 0x40005263u -#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u -#define CYREG_PRT12_SYNC_OUT 0x40005265u -#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u -#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u -#define CYREG_PRT15_OUT_SEL0 0x40005278u -#define CYREG_PRT15_OUT_SEL1 0x40005279u -#define CYREG_PRT15_OE_SEL0 0x4000527au -#define CYREG_PRT15_OE_SEL1 0x4000527bu -#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu -#define CYREG_PRT15_SYNC_OUT 0x4000527du -#define CYREG_PRT15_CAPS_SEL 0x4000527eu -#define CYDEV_EMIF_BASE 0x40005400u -#define CYDEV_EMIF_SIZE 0x00000007u -#define CYREG_EMIF_NO_UDB 0x40005400u -#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u -#define CYREG_EMIF_MEM_DWN 0x40005402u -#define CYREG_EMIF_MEMCLK_DIV 0x40005403u -#define CYREG_EMIF_CLOCK_EN 0x40005404u -#define CYREG_EMIF_EM_TYPE 0x40005405u -#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u -#define CYDEV_ANAIF_BASE 0x40005800u -#define CYDEV_ANAIF_SIZE 0x000003a9u -#define CYDEV_ANAIF_CFG_BASE 0x40005800u -#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu -#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u -#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u -#define CYREG_SC0_CR0 0x40005800u -#define CYREG_SC0_CR1 0x40005801u -#define CYREG_SC0_CR2 0x40005802u -#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u -#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u -#define CYREG_SC1_CR0 0x40005804u -#define CYREG_SC1_CR1 0x40005805u -#define CYREG_SC1_CR2 0x40005806u -#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u -#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u -#define CYREG_SC2_CR0 0x40005808u -#define CYREG_SC2_CR1 0x40005809u -#define CYREG_SC2_CR2 0x4000580au -#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu -#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u -#define CYREG_SC3_CR0 0x4000580cu -#define CYREG_SC3_CR1 0x4000580du -#define CYREG_SC3_CR2 0x4000580eu -#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u -#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u -#define CYREG_DAC0_CR0 0x40005820u -#define CYREG_DAC0_CR1 0x40005821u -#define CYREG_DAC0_TST 0x40005822u -#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u -#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u -#define CYREG_DAC1_CR0 0x40005824u -#define CYREG_DAC1_CR1 0x40005825u -#define CYREG_DAC1_TST 0x40005826u -#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u -#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u -#define CYREG_DAC2_CR0 0x40005828u -#define CYREG_DAC2_CR1 0x40005829u -#define CYREG_DAC2_TST 0x4000582au -#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu -#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u -#define CYREG_DAC3_CR0 0x4000582cu -#define CYREG_DAC3_CR1 0x4000582du -#define CYREG_DAC3_TST 0x4000582eu -#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u -#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u -#define CYREG_CMP0_CR 0x40005840u -#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u -#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u -#define CYREG_CMP1_CR 0x40005841u -#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u -#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u -#define CYREG_CMP2_CR 0x40005842u -#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u -#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u -#define CYREG_CMP3_CR 0x40005843u -#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u -#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u -#define CYREG_LUT0_CR 0x40005848u -#define CYREG_LUT0_MX 0x40005849u -#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au -#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u -#define CYREG_LUT1_CR 0x4000584au -#define CYREG_LUT1_MX 0x4000584bu -#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu -#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u -#define CYREG_LUT2_CR 0x4000584cu -#define CYREG_LUT2_MX 0x4000584du -#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu -#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u -#define CYREG_LUT3_CR 0x4000584eu -#define CYREG_LUT3_MX 0x4000584fu -#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u -#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u -#define CYREG_OPAMP0_CR 0x40005858u -#define CYREG_OPAMP0_RSVD 0x40005859u -#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au -#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u -#define CYREG_OPAMP1_CR 0x4000585au -#define CYREG_OPAMP1_RSVD 0x4000585bu -#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu -#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u -#define CYREG_OPAMP2_CR 0x4000585cu -#define CYREG_OPAMP2_RSVD 0x4000585du -#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu -#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u -#define CYREG_OPAMP3_CR 0x4000585eu -#define CYREG_OPAMP3_RSVD 0x4000585fu -#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u -#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u -#define CYREG_LCDDAC_CR0 0x40005868u -#define CYREG_LCDDAC_CR1 0x40005869u -#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au -#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u -#define CYREG_LCDDRV_CR 0x4000586au -#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu -#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u -#define CYREG_LCDTMR_CFG 0x4000586bu -#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu -#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u -#define CYREG_BG_CR0 0x4000586cu -#define CYREG_BG_RSVD 0x4000586du -#define CYREG_BG_DFT0 0x4000586eu -#define CYREG_BG_DFT1 0x4000586fu -#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u -#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u -#define CYREG_CAPSL_CFG0 0x40005870u -#define CYREG_CAPSL_CFG1 0x40005871u -#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u -#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u -#define CYREG_CAPSR_CFG0 0x40005872u -#define CYREG_CAPSR_CFG1 0x40005873u -#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u -#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u -#define CYREG_PUMP_CR0 0x40005876u -#define CYREG_PUMP_CR1 0x40005877u -#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u -#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u -#define CYREG_LPF0_CR0 0x40005878u -#define CYREG_LPF0_RSVD 0x40005879u -#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au -#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u -#define CYREG_LPF1_CR0 0x4000587au -#define CYREG_LPF1_RSVD 0x4000587bu -#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu -#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u -#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu -#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u -#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u -#define CYREG_DSM0_CR0 0x40005880u -#define CYREG_DSM0_CR1 0x40005881u -#define CYREG_DSM0_CR2 0x40005882u -#define CYREG_DSM0_CR3 0x40005883u -#define CYREG_DSM0_CR4 0x40005884u -#define CYREG_DSM0_CR5 0x40005885u -#define CYREG_DSM0_CR6 0x40005886u -#define CYREG_DSM0_CR7 0x40005887u -#define CYREG_DSM0_CR8 0x40005888u -#define CYREG_DSM0_CR9 0x40005889u -#define CYREG_DSM0_CR10 0x4000588au -#define CYREG_DSM0_CR11 0x4000588bu -#define CYREG_DSM0_CR12 0x4000588cu -#define CYREG_DSM0_CR13 0x4000588du -#define CYREG_DSM0_CR14 0x4000588eu -#define CYREG_DSM0_CR15 0x4000588fu -#define CYREG_DSM0_CR16 0x40005890u -#define CYREG_DSM0_CR17 0x40005891u -#define CYREG_DSM0_REF0 0x40005892u -#define CYREG_DSM0_REF1 0x40005893u -#define CYREG_DSM0_REF2 0x40005894u -#define CYREG_DSM0_REF3 0x40005895u -#define CYREG_DSM0_DEM0 0x40005896u -#define CYREG_DSM0_DEM1 0x40005897u -#define CYREG_DSM0_TST0 0x40005898u -#define CYREG_DSM0_TST1 0x40005899u -#define CYREG_DSM0_BUF0 0x4000589au -#define CYREG_DSM0_BUF1 0x4000589bu -#define CYREG_DSM0_BUF2 0x4000589cu -#define CYREG_DSM0_BUF3 0x4000589du -#define CYREG_DSM0_MISC 0x4000589eu -#define CYREG_DSM0_RSVD1 0x4000589fu -#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u -#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u -#define CYREG_SAR0_CSR0 0x40005900u -#define CYREG_SAR0_CSR1 0x40005901u -#define CYREG_SAR0_CSR2 0x40005902u -#define CYREG_SAR0_CSR3 0x40005903u -#define CYREG_SAR0_CSR4 0x40005904u -#define CYREG_SAR0_CSR5 0x40005905u -#define CYREG_SAR0_CSR6 0x40005906u -#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u -#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u -#define CYREG_SAR1_CSR0 0x40005908u -#define CYREG_SAR1_CSR1 0x40005909u -#define CYREG_SAR1_CSR2 0x4000590au -#define CYREG_SAR1_CSR3 0x4000590bu -#define CYREG_SAR1_CSR4 0x4000590cu -#define CYREG_SAR1_CSR5 0x4000590du -#define CYREG_SAR1_CSR6 0x4000590eu -#define CYDEV_ANAIF_RT_BASE 0x40005a00u -#define CYDEV_ANAIF_RT_SIZE 0x00000162u -#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u -#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du -#define CYREG_SC0_SW0 0x40005a00u -#define CYREG_SC0_SW2 0x40005a02u -#define CYREG_SC0_SW3 0x40005a03u -#define CYREG_SC0_SW4 0x40005a04u -#define CYREG_SC0_SW6 0x40005a06u -#define CYREG_SC0_SW7 0x40005a07u -#define CYREG_SC0_SW8 0x40005a08u -#define CYREG_SC0_SW10 0x40005a0au -#define CYREG_SC0_CLK 0x40005a0bu -#define CYREG_SC0_BST 0x40005a0cu -#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u -#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du -#define CYREG_SC1_SW0 0x40005a10u -#define CYREG_SC1_SW2 0x40005a12u -#define CYREG_SC1_SW3 0x40005a13u -#define CYREG_SC1_SW4 0x40005a14u -#define CYREG_SC1_SW6 0x40005a16u -#define CYREG_SC1_SW7 0x40005a17u -#define CYREG_SC1_SW8 0x40005a18u -#define CYREG_SC1_SW10 0x40005a1au -#define CYREG_SC1_CLK 0x40005a1bu -#define CYREG_SC1_BST 0x40005a1cu -#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u -#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du -#define CYREG_SC2_SW0 0x40005a20u -#define CYREG_SC2_SW2 0x40005a22u -#define CYREG_SC2_SW3 0x40005a23u -#define CYREG_SC2_SW4 0x40005a24u -#define CYREG_SC2_SW6 0x40005a26u -#define CYREG_SC2_SW7 0x40005a27u -#define CYREG_SC2_SW8 0x40005a28u -#define CYREG_SC2_SW10 0x40005a2au -#define CYREG_SC2_CLK 0x40005a2bu -#define CYREG_SC2_BST 0x40005a2cu -#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u -#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du -#define CYREG_SC3_SW0 0x40005a30u -#define CYREG_SC3_SW2 0x40005a32u -#define CYREG_SC3_SW3 0x40005a33u -#define CYREG_SC3_SW4 0x40005a34u -#define CYREG_SC3_SW6 0x40005a36u -#define CYREG_SC3_SW7 0x40005a37u -#define CYREG_SC3_SW8 0x40005a38u -#define CYREG_SC3_SW10 0x40005a3au -#define CYREG_SC3_CLK 0x40005a3bu -#define CYREG_SC3_BST 0x40005a3cu -#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u -#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u -#define CYREG_DAC0_SW0 0x40005a80u -#define CYREG_DAC0_SW2 0x40005a82u -#define CYREG_DAC0_SW3 0x40005a83u -#define CYREG_DAC0_SW4 0x40005a84u -#define CYREG_DAC0_STROBE 0x40005a87u -#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u -#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u -#define CYREG_DAC1_SW0 0x40005a88u -#define CYREG_DAC1_SW2 0x40005a8au -#define CYREG_DAC1_SW3 0x40005a8bu -#define CYREG_DAC1_SW4 0x40005a8cu -#define CYREG_DAC1_STROBE 0x40005a8fu -#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u -#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u -#define CYREG_DAC2_SW0 0x40005a90u -#define CYREG_DAC2_SW2 0x40005a92u -#define CYREG_DAC2_SW3 0x40005a93u -#define CYREG_DAC2_SW4 0x40005a94u -#define CYREG_DAC2_STROBE 0x40005a97u -#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u -#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u -#define CYREG_DAC3_SW0 0x40005a98u -#define CYREG_DAC3_SW2 0x40005a9au -#define CYREG_DAC3_SW3 0x40005a9bu -#define CYREG_DAC3_SW4 0x40005a9cu -#define CYREG_DAC3_STROBE 0x40005a9fu -#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u -#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u -#define CYREG_CMP0_SW0 0x40005ac0u -#define CYREG_CMP0_SW2 0x40005ac2u -#define CYREG_CMP0_SW3 0x40005ac3u -#define CYREG_CMP0_SW4 0x40005ac4u -#define CYREG_CMP0_SW6 0x40005ac6u -#define CYREG_CMP0_CLK 0x40005ac7u -#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u -#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u -#define CYREG_CMP1_SW0 0x40005ac8u -#define CYREG_CMP1_SW2 0x40005acau -#define CYREG_CMP1_SW3 0x40005acbu -#define CYREG_CMP1_SW4 0x40005accu -#define CYREG_CMP1_SW6 0x40005aceu -#define CYREG_CMP1_CLK 0x40005acfu -#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u -#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u -#define CYREG_CMP2_SW0 0x40005ad0u -#define CYREG_CMP2_SW2 0x40005ad2u -#define CYREG_CMP2_SW3 0x40005ad3u -#define CYREG_CMP2_SW4 0x40005ad4u -#define CYREG_CMP2_SW6 0x40005ad6u -#define CYREG_CMP2_CLK 0x40005ad7u -#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u -#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u -#define CYREG_CMP3_SW0 0x40005ad8u -#define CYREG_CMP3_SW2 0x40005adau -#define CYREG_CMP3_SW3 0x40005adbu -#define CYREG_CMP3_SW4 0x40005adcu -#define CYREG_CMP3_SW6 0x40005adeu -#define CYREG_CMP3_CLK 0x40005adfu -#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u -#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u -#define CYREG_DSM0_SW0 0x40005b00u -#define CYREG_DSM0_SW2 0x40005b02u -#define CYREG_DSM0_SW3 0x40005b03u -#define CYREG_DSM0_SW4 0x40005b04u -#define CYREG_DSM0_SW6 0x40005b06u -#define CYREG_DSM0_CLK 0x40005b07u -#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u -#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u -#define CYREG_SAR0_SW0 0x40005b20u -#define CYREG_SAR0_SW2 0x40005b22u -#define CYREG_SAR0_SW3 0x40005b23u -#define CYREG_SAR0_SW4 0x40005b24u -#define CYREG_SAR0_SW6 0x40005b26u -#define CYREG_SAR0_CLK 0x40005b27u -#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u -#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u -#define CYREG_SAR1_SW0 0x40005b28u -#define CYREG_SAR1_SW2 0x40005b2au -#define CYREG_SAR1_SW3 0x40005b2bu -#define CYREG_SAR1_SW4 0x40005b2cu -#define CYREG_SAR1_SW6 0x40005b2eu -#define CYREG_SAR1_CLK 0x40005b2fu -#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u -#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u -#define CYREG_OPAMP0_MX 0x40005b40u -#define CYREG_OPAMP0_SW 0x40005b41u -#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u -#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u -#define CYREG_OPAMP1_MX 0x40005b42u -#define CYREG_OPAMP1_SW 0x40005b43u -#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u -#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u -#define CYREG_OPAMP2_MX 0x40005b44u -#define CYREG_OPAMP2_SW 0x40005b45u -#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u -#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u -#define CYREG_OPAMP3_MX 0x40005b46u -#define CYREG_OPAMP3_SW 0x40005b47u -#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u -#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u -#define CYREG_LCDDAC_SW0 0x40005b50u -#define CYREG_LCDDAC_SW1 0x40005b51u -#define CYREG_LCDDAC_SW2 0x40005b52u -#define CYREG_LCDDAC_SW3 0x40005b53u -#define CYREG_LCDDAC_SW4 0x40005b54u -#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u -#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u -#define CYREG_SC_MISC 0x40005b56u -#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u -#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u -#define CYREG_BUS_SW0 0x40005b58u -#define CYREG_BUS_SW2 0x40005b5au -#define CYREG_BUS_SW3 0x40005b5bu -#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu -#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u -#define CYREG_DFT_CR0 0x40005b5cu -#define CYREG_DFT_CR1 0x40005b5du -#define CYREG_DFT_CR2 0x40005b5eu -#define CYREG_DFT_CR3 0x40005b5fu -#define CYREG_DFT_CR4 0x40005b60u -#define CYREG_DFT_CR5 0x40005b61u -#define CYDEV_ANAIF_WRK_BASE 0x40005b80u -#define CYDEV_ANAIF_WRK_SIZE 0x00000029u -#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u -#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u -#define CYREG_DAC0_D 0x40005b80u -#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u -#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u -#define CYREG_DAC1_D 0x40005b81u -#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u -#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u -#define CYREG_DAC2_D 0x40005b82u -#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u -#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u -#define CYREG_DAC3_D 0x40005b83u -#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u -#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u -#define CYREG_DSM0_OUT0 0x40005b88u -#define CYREG_DSM0_OUT1 0x40005b89u -#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u -#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u -#define CYREG_LUT_SR 0x40005b90u -#define CYREG_LUT_WRK1 0x40005b91u -#define CYREG_LUT_MSK 0x40005b92u -#define CYREG_LUT_CLK 0x40005b93u -#define CYREG_LUT_CPTR 0x40005b94u -#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u -#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u -#define CYREG_CMP_WRK 0x40005b96u -#define CYREG_CMP_TST 0x40005b97u -#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u -#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u -#define CYREG_SC_SR 0x40005b98u -#define CYREG_SC_WRK1 0x40005b99u -#define CYREG_SC_MSK 0x40005b9au -#define CYREG_SC_CMPINV 0x40005b9bu -#define CYREG_SC_CPTR 0x40005b9cu -#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u -#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u -#define CYREG_SAR0_WRK0 0x40005ba0u -#define CYREG_SAR0_WRK1 0x40005ba1u -#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u -#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u -#define CYREG_SAR1_WRK0 0x40005ba2u -#define CYREG_SAR1_WRK1 0x40005ba3u -#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u -#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u -#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u -#define CYDEV_USB_BASE 0x40006000u -#define CYDEV_USB_SIZE 0x00000300u -#define CYREG_USB_EP0_DR0 0x40006000u -#define CYREG_USB_EP0_DR1 0x40006001u -#define CYREG_USB_EP0_DR2 0x40006002u -#define CYREG_USB_EP0_DR3 0x40006003u -#define CYREG_USB_EP0_DR4 0x40006004u -#define CYREG_USB_EP0_DR5 0x40006005u -#define CYREG_USB_EP0_DR6 0x40006006u -#define CYREG_USB_EP0_DR7 0x40006007u -#define CYREG_USB_CR0 0x40006008u -#define CYREG_USB_CR1 0x40006009u -#define CYREG_USB_SIE_EP_INT_EN 0x4000600au -#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu -#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu -#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u -#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu -#define CYREG_USB_SIE_EP1_CNT1 0x4000600du -#define CYREG_USB_SIE_EP1_CR0 0x4000600eu -#define CYREG_USB_USBIO_CR0 0x40006010u -#define CYREG_USB_USBIO_CR1 0x40006012u -#define CYREG_USB_DYN_RECONFIG 0x40006014u -#define CYREG_USB_SOF0 0x40006018u -#define CYREG_USB_SOF1 0x40006019u -#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu -#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u -#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu -#define CYREG_USB_SIE_EP2_CNT1 0x4000601du -#define CYREG_USB_SIE_EP2_CR0 0x4000601eu -#define CYREG_USB_EP0_CR 0x40006028u -#define CYREG_USB_EP0_CNT 0x40006029u -#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu -#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u -#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu -#define CYREG_USB_SIE_EP3_CNT1 0x4000602du -#define CYREG_USB_SIE_EP3_CR0 0x4000602eu -#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu -#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u -#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu -#define CYREG_USB_SIE_EP4_CNT1 0x4000603du -#define CYREG_USB_SIE_EP4_CR0 0x4000603eu -#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu -#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u -#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu -#define CYREG_USB_SIE_EP5_CNT1 0x4000604du -#define CYREG_USB_SIE_EP5_CR0 0x4000604eu -#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu -#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u -#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu -#define CYREG_USB_SIE_EP6_CNT1 0x4000605du -#define CYREG_USB_SIE_EP6_CR0 0x4000605eu -#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu -#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u -#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu -#define CYREG_USB_SIE_EP7_CNT1 0x4000606du -#define CYREG_USB_SIE_EP7_CR0 0x4000606eu -#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu -#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u -#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu -#define CYREG_USB_SIE_EP8_CNT1 0x4000607du -#define CYREG_USB_SIE_EP8_CR0 0x4000607eu -#define CYDEV_USB_ARB_EP1_BASE 0x40006080u -#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u -#define CYREG_USB_ARB_EP1_CFG 0x40006080u -#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u -#define CYREG_USB_ARB_EP1_SR 0x40006082u -#define CYDEV_USB_ARB_RW1_BASE 0x40006084u -#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u -#define CYREG_USB_ARB_RW1_WA 0x40006084u -#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u -#define CYREG_USB_ARB_RW1_RA 0x40006086u -#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u -#define CYREG_USB_ARB_RW1_DR 0x40006088u -#define CYREG_USB_BUF_SIZE 0x4000608cu -#define CYREG_USB_EP_ACTIVE 0x4000608eu -#define CYREG_USB_EP_TYPE 0x4000608fu -#define CYDEV_USB_ARB_EP2_BASE 0x40006090u -#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u -#define CYREG_USB_ARB_EP2_CFG 0x40006090u -#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u -#define CYREG_USB_ARB_EP2_SR 0x40006092u -#define CYDEV_USB_ARB_RW2_BASE 0x40006094u -#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u -#define CYREG_USB_ARB_RW2_WA 0x40006094u -#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u -#define CYREG_USB_ARB_RW2_RA 0x40006096u -#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u -#define CYREG_USB_ARB_RW2_DR 0x40006098u -#define CYREG_USB_ARB_CFG 0x4000609cu -#define CYREG_USB_USB_CLK_EN 0x4000609du -#define CYREG_USB_ARB_INT_EN 0x4000609eu -#define CYREG_USB_ARB_INT_SR 0x4000609fu -#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u -#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u -#define CYREG_USB_ARB_EP3_CFG 0x400060a0u -#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u -#define CYREG_USB_ARB_EP3_SR 0x400060a2u -#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u -#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u -#define CYREG_USB_ARB_RW3_WA 0x400060a4u -#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u -#define CYREG_USB_ARB_RW3_RA 0x400060a6u -#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u -#define CYREG_USB_ARB_RW3_DR 0x400060a8u -#define CYREG_USB_CWA 0x400060acu -#define CYREG_USB_CWA_MSB 0x400060adu -#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u -#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u -#define CYREG_USB_ARB_EP4_CFG 0x400060b0u -#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u -#define CYREG_USB_ARB_EP4_SR 0x400060b2u -#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u -#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u -#define CYREG_USB_ARB_RW4_WA 0x400060b4u -#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u -#define CYREG_USB_ARB_RW4_RA 0x400060b6u -#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u -#define CYREG_USB_ARB_RW4_DR 0x400060b8u -#define CYREG_USB_DMA_THRES 0x400060bcu -#define CYREG_USB_DMA_THRES_MSB 0x400060bdu -#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u -#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u -#define CYREG_USB_ARB_EP5_CFG 0x400060c0u -#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u -#define CYREG_USB_ARB_EP5_SR 0x400060c2u -#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u -#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u -#define CYREG_USB_ARB_RW5_WA 0x400060c4u -#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u -#define CYREG_USB_ARB_RW5_RA 0x400060c6u -#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u -#define CYREG_USB_ARB_RW5_DR 0x400060c8u -#define CYREG_USB_BUS_RST_CNT 0x400060ccu -#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u -#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u -#define CYREG_USB_ARB_EP6_CFG 0x400060d0u -#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u -#define CYREG_USB_ARB_EP6_SR 0x400060d2u -#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u -#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u -#define CYREG_USB_ARB_RW6_WA 0x400060d4u -#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u -#define CYREG_USB_ARB_RW6_RA 0x400060d6u -#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u -#define CYREG_USB_ARB_RW6_DR 0x400060d8u -#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u -#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u -#define CYREG_USB_ARB_EP7_CFG 0x400060e0u -#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u -#define CYREG_USB_ARB_EP7_SR 0x400060e2u -#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u -#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u -#define CYREG_USB_ARB_RW7_WA 0x400060e4u -#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u -#define CYREG_USB_ARB_RW7_RA 0x400060e6u -#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u -#define CYREG_USB_ARB_RW7_DR 0x400060e8u -#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u -#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u -#define CYREG_USB_ARB_EP8_CFG 0x400060f0u -#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u -#define CYREG_USB_ARB_EP8_SR 0x400060f2u -#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u -#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u -#define CYREG_USB_ARB_RW8_WA 0x400060f4u -#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u -#define CYREG_USB_ARB_RW8_RA 0x400060f6u -#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u -#define CYREG_USB_ARB_RW8_DR 0x400060f8u -#define CYDEV_USB_MEM_BASE 0x40006100u -#define CYDEV_USB_MEM_SIZE 0x00000200u -#define CYREG_USB_MEM_DATA_MBASE 0x40006100u -#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u -#define CYDEV_UWRK_BASE 0x40006400u -#define CYDEV_UWRK_SIZE 0x00000b60u -#define CYDEV_UWRK_UWRK8_BASE 0x40006400u -#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u -#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u -#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u -#define CYREG_B0_UDB00_A0 0x40006400u -#define CYREG_B0_UDB01_A0 0x40006401u -#define CYREG_B0_UDB02_A0 0x40006402u -#define CYREG_B0_UDB03_A0 0x40006403u -#define CYREG_B0_UDB04_A0 0x40006404u -#define CYREG_B0_UDB05_A0 0x40006405u -#define CYREG_B0_UDB06_A0 0x40006406u -#define CYREG_B0_UDB07_A0 0x40006407u -#define CYREG_B0_UDB08_A0 0x40006408u -#define CYREG_B0_UDB09_A0 0x40006409u -#define CYREG_B0_UDB10_A0 0x4000640au -#define CYREG_B0_UDB11_A0 0x4000640bu -#define CYREG_B0_UDB12_A0 0x4000640cu -#define CYREG_B0_UDB13_A0 0x4000640du -#define CYREG_B0_UDB14_A0 0x4000640eu -#define CYREG_B0_UDB15_A0 0x4000640fu -#define CYREG_B0_UDB00_A1 0x40006410u -#define CYREG_B0_UDB01_A1 0x40006411u -#define CYREG_B0_UDB02_A1 0x40006412u -#define CYREG_B0_UDB03_A1 0x40006413u -#define CYREG_B0_UDB04_A1 0x40006414u -#define CYREG_B0_UDB05_A1 0x40006415u -#define CYREG_B0_UDB06_A1 0x40006416u -#define CYREG_B0_UDB07_A1 0x40006417u -#define CYREG_B0_UDB08_A1 0x40006418u -#define CYREG_B0_UDB09_A1 0x40006419u -#define CYREG_B0_UDB10_A1 0x4000641au -#define CYREG_B0_UDB11_A1 0x4000641bu -#define CYREG_B0_UDB12_A1 0x4000641cu -#define CYREG_B0_UDB13_A1 0x4000641du -#define CYREG_B0_UDB14_A1 0x4000641eu -#define CYREG_B0_UDB15_A1 0x4000641fu -#define CYREG_B0_UDB00_D0 0x40006420u -#define CYREG_B0_UDB01_D0 0x40006421u -#define CYREG_B0_UDB02_D0 0x40006422u -#define CYREG_B0_UDB03_D0 0x40006423u -#define CYREG_B0_UDB04_D0 0x40006424u -#define CYREG_B0_UDB05_D0 0x40006425u -#define CYREG_B0_UDB06_D0 0x40006426u -#define CYREG_B0_UDB07_D0 0x40006427u -#define CYREG_B0_UDB08_D0 0x40006428u -#define CYREG_B0_UDB09_D0 0x40006429u -#define CYREG_B0_UDB10_D0 0x4000642au -#define CYREG_B0_UDB11_D0 0x4000642bu -#define CYREG_B0_UDB12_D0 0x4000642cu -#define CYREG_B0_UDB13_D0 0x4000642du -#define CYREG_B0_UDB14_D0 0x4000642eu -#define CYREG_B0_UDB15_D0 0x4000642fu -#define CYREG_B0_UDB00_D1 0x40006430u -#define CYREG_B0_UDB01_D1 0x40006431u -#define CYREG_B0_UDB02_D1 0x40006432u -#define CYREG_B0_UDB03_D1 0x40006433u -#define CYREG_B0_UDB04_D1 0x40006434u -#define CYREG_B0_UDB05_D1 0x40006435u -#define CYREG_B0_UDB06_D1 0x40006436u -#define CYREG_B0_UDB07_D1 0x40006437u -#define CYREG_B0_UDB08_D1 0x40006438u -#define CYREG_B0_UDB09_D1 0x40006439u -#define CYREG_B0_UDB10_D1 0x4000643au -#define CYREG_B0_UDB11_D1 0x4000643bu -#define CYREG_B0_UDB12_D1 0x4000643cu -#define CYREG_B0_UDB13_D1 0x4000643du -#define CYREG_B0_UDB14_D1 0x4000643eu -#define CYREG_B0_UDB15_D1 0x4000643fu -#define CYREG_B0_UDB00_F0 0x40006440u -#define CYREG_B0_UDB01_F0 0x40006441u -#define CYREG_B0_UDB02_F0 0x40006442u -#define CYREG_B0_UDB03_F0 0x40006443u -#define CYREG_B0_UDB04_F0 0x40006444u -#define CYREG_B0_UDB05_F0 0x40006445u -#define CYREG_B0_UDB06_F0 0x40006446u -#define CYREG_B0_UDB07_F0 0x40006447u -#define CYREG_B0_UDB08_F0 0x40006448u -#define CYREG_B0_UDB09_F0 0x40006449u -#define CYREG_B0_UDB10_F0 0x4000644au -#define CYREG_B0_UDB11_F0 0x4000644bu -#define CYREG_B0_UDB12_F0 0x4000644cu -#define CYREG_B0_UDB13_F0 0x4000644du -#define CYREG_B0_UDB14_F0 0x4000644eu -#define CYREG_B0_UDB15_F0 0x4000644fu -#define CYREG_B0_UDB00_F1 0x40006450u -#define CYREG_B0_UDB01_F1 0x40006451u -#define CYREG_B0_UDB02_F1 0x40006452u -#define CYREG_B0_UDB03_F1 0x40006453u -#define CYREG_B0_UDB04_F1 0x40006454u -#define CYREG_B0_UDB05_F1 0x40006455u -#define CYREG_B0_UDB06_F1 0x40006456u -#define CYREG_B0_UDB07_F1 0x40006457u -#define CYREG_B0_UDB08_F1 0x40006458u -#define CYREG_B0_UDB09_F1 0x40006459u -#define CYREG_B0_UDB10_F1 0x4000645au -#define CYREG_B0_UDB11_F1 0x4000645bu -#define CYREG_B0_UDB12_F1 0x4000645cu -#define CYREG_B0_UDB13_F1 0x4000645du -#define CYREG_B0_UDB14_F1 0x4000645eu -#define CYREG_B0_UDB15_F1 0x4000645fu -#define CYREG_B0_UDB00_ST 0x40006460u -#define CYREG_B0_UDB01_ST 0x40006461u -#define CYREG_B0_UDB02_ST 0x40006462u -#define CYREG_B0_UDB03_ST 0x40006463u -#define CYREG_B0_UDB04_ST 0x40006464u -#define CYREG_B0_UDB05_ST 0x40006465u -#define CYREG_B0_UDB06_ST 0x40006466u -#define CYREG_B0_UDB07_ST 0x40006467u -#define CYREG_B0_UDB08_ST 0x40006468u -#define CYREG_B0_UDB09_ST 0x40006469u -#define CYREG_B0_UDB10_ST 0x4000646au -#define CYREG_B0_UDB11_ST 0x4000646bu -#define CYREG_B0_UDB12_ST 0x4000646cu -#define CYREG_B0_UDB13_ST 0x4000646du -#define CYREG_B0_UDB14_ST 0x4000646eu -#define CYREG_B0_UDB15_ST 0x4000646fu -#define CYREG_B0_UDB00_CTL 0x40006470u -#define CYREG_B0_UDB01_CTL 0x40006471u -#define CYREG_B0_UDB02_CTL 0x40006472u -#define CYREG_B0_UDB03_CTL 0x40006473u -#define CYREG_B0_UDB04_CTL 0x40006474u -#define CYREG_B0_UDB05_CTL 0x40006475u -#define CYREG_B0_UDB06_CTL 0x40006476u -#define CYREG_B0_UDB07_CTL 0x40006477u -#define CYREG_B0_UDB08_CTL 0x40006478u -#define CYREG_B0_UDB09_CTL 0x40006479u -#define CYREG_B0_UDB10_CTL 0x4000647au -#define CYREG_B0_UDB11_CTL 0x4000647bu -#define CYREG_B0_UDB12_CTL 0x4000647cu -#define CYREG_B0_UDB13_CTL 0x4000647du -#define CYREG_B0_UDB14_CTL 0x4000647eu -#define CYREG_B0_UDB15_CTL 0x4000647fu -#define CYREG_B0_UDB00_MSK 0x40006480u -#define CYREG_B0_UDB01_MSK 0x40006481u -#define CYREG_B0_UDB02_MSK 0x40006482u -#define CYREG_B0_UDB03_MSK 0x40006483u -#define CYREG_B0_UDB04_MSK 0x40006484u -#define CYREG_B0_UDB05_MSK 0x40006485u -#define CYREG_B0_UDB06_MSK 0x40006486u -#define CYREG_B0_UDB07_MSK 0x40006487u -#define CYREG_B0_UDB08_MSK 0x40006488u -#define CYREG_B0_UDB09_MSK 0x40006489u -#define CYREG_B0_UDB10_MSK 0x4000648au -#define CYREG_B0_UDB11_MSK 0x4000648bu -#define CYREG_B0_UDB12_MSK 0x4000648cu -#define CYREG_B0_UDB13_MSK 0x4000648du -#define CYREG_B0_UDB14_MSK 0x4000648eu -#define CYREG_B0_UDB15_MSK 0x4000648fu -#define CYREG_B0_UDB00_ACTL 0x40006490u -#define CYREG_B0_UDB01_ACTL 0x40006491u -#define CYREG_B0_UDB02_ACTL 0x40006492u -#define CYREG_B0_UDB03_ACTL 0x40006493u -#define CYREG_B0_UDB04_ACTL 0x40006494u -#define CYREG_B0_UDB05_ACTL 0x40006495u -#define CYREG_B0_UDB06_ACTL 0x40006496u -#define CYREG_B0_UDB07_ACTL 0x40006497u -#define CYREG_B0_UDB08_ACTL 0x40006498u -#define CYREG_B0_UDB09_ACTL 0x40006499u -#define CYREG_B0_UDB10_ACTL 0x4000649au -#define CYREG_B0_UDB11_ACTL 0x4000649bu -#define CYREG_B0_UDB12_ACTL 0x4000649cu -#define CYREG_B0_UDB13_ACTL 0x4000649du -#define CYREG_B0_UDB14_ACTL 0x4000649eu -#define CYREG_B0_UDB15_ACTL 0x4000649fu -#define CYREG_B0_UDB00_MC 0x400064a0u -#define CYREG_B0_UDB01_MC 0x400064a1u -#define CYREG_B0_UDB02_MC 0x400064a2u -#define CYREG_B0_UDB03_MC 0x400064a3u -#define CYREG_B0_UDB04_MC 0x400064a4u -#define CYREG_B0_UDB05_MC 0x400064a5u -#define CYREG_B0_UDB06_MC 0x400064a6u -#define CYREG_B0_UDB07_MC 0x400064a7u -#define CYREG_B0_UDB08_MC 0x400064a8u -#define CYREG_B0_UDB09_MC 0x400064a9u -#define CYREG_B0_UDB10_MC 0x400064aau -#define CYREG_B0_UDB11_MC 0x400064abu -#define CYREG_B0_UDB12_MC 0x400064acu -#define CYREG_B0_UDB13_MC 0x400064adu -#define CYREG_B0_UDB14_MC 0x400064aeu -#define CYREG_B0_UDB15_MC 0x400064afu -#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u -#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u -#define CYREG_B1_UDB04_A0 0x40006504u -#define CYREG_B1_UDB05_A0 0x40006505u -#define CYREG_B1_UDB06_A0 0x40006506u -#define CYREG_B1_UDB07_A0 0x40006507u -#define CYREG_B1_UDB08_A0 0x40006508u -#define CYREG_B1_UDB09_A0 0x40006509u -#define CYREG_B1_UDB10_A0 0x4000650au -#define CYREG_B1_UDB11_A0 0x4000650bu -#define CYREG_B1_UDB04_A1 0x40006514u -#define CYREG_B1_UDB05_A1 0x40006515u -#define CYREG_B1_UDB06_A1 0x40006516u -#define CYREG_B1_UDB07_A1 0x40006517u -#define CYREG_B1_UDB08_A1 0x40006518u -#define CYREG_B1_UDB09_A1 0x40006519u -#define CYREG_B1_UDB10_A1 0x4000651au -#define CYREG_B1_UDB11_A1 0x4000651bu -#define CYREG_B1_UDB04_D0 0x40006524u -#define CYREG_B1_UDB05_D0 0x40006525u -#define CYREG_B1_UDB06_D0 0x40006526u -#define CYREG_B1_UDB07_D0 0x40006527u -#define CYREG_B1_UDB08_D0 0x40006528u -#define CYREG_B1_UDB09_D0 0x40006529u -#define CYREG_B1_UDB10_D0 0x4000652au -#define CYREG_B1_UDB11_D0 0x4000652bu -#define CYREG_B1_UDB04_D1 0x40006534u -#define CYREG_B1_UDB05_D1 0x40006535u -#define CYREG_B1_UDB06_D1 0x40006536u -#define CYREG_B1_UDB07_D1 0x40006537u -#define CYREG_B1_UDB08_D1 0x40006538u -#define CYREG_B1_UDB09_D1 0x40006539u -#define CYREG_B1_UDB10_D1 0x4000653au -#define CYREG_B1_UDB11_D1 0x4000653bu -#define CYREG_B1_UDB04_F0 0x40006544u -#define CYREG_B1_UDB05_F0 0x40006545u -#define CYREG_B1_UDB06_F0 0x40006546u -#define CYREG_B1_UDB07_F0 0x40006547u -#define CYREG_B1_UDB08_F0 0x40006548u -#define CYREG_B1_UDB09_F0 0x40006549u -#define CYREG_B1_UDB10_F0 0x4000654au -#define CYREG_B1_UDB11_F0 0x4000654bu -#define CYREG_B1_UDB04_F1 0x40006554u -#define CYREG_B1_UDB05_F1 0x40006555u -#define CYREG_B1_UDB06_F1 0x40006556u -#define CYREG_B1_UDB07_F1 0x40006557u -#define CYREG_B1_UDB08_F1 0x40006558u -#define CYREG_B1_UDB09_F1 0x40006559u -#define CYREG_B1_UDB10_F1 0x4000655au -#define CYREG_B1_UDB11_F1 0x4000655bu -#define CYREG_B1_UDB04_ST 0x40006564u -#define CYREG_B1_UDB05_ST 0x40006565u -#define CYREG_B1_UDB06_ST 0x40006566u -#define CYREG_B1_UDB07_ST 0x40006567u -#define CYREG_B1_UDB08_ST 0x40006568u -#define CYREG_B1_UDB09_ST 0x40006569u -#define CYREG_B1_UDB10_ST 0x4000656au -#define CYREG_B1_UDB11_ST 0x4000656bu -#define CYREG_B1_UDB04_CTL 0x40006574u -#define CYREG_B1_UDB05_CTL 0x40006575u -#define CYREG_B1_UDB06_CTL 0x40006576u -#define CYREG_B1_UDB07_CTL 0x40006577u -#define CYREG_B1_UDB08_CTL 0x40006578u -#define CYREG_B1_UDB09_CTL 0x40006579u -#define CYREG_B1_UDB10_CTL 0x4000657au -#define CYREG_B1_UDB11_CTL 0x4000657bu -#define CYREG_B1_UDB04_MSK 0x40006584u -#define CYREG_B1_UDB05_MSK 0x40006585u -#define CYREG_B1_UDB06_MSK 0x40006586u -#define CYREG_B1_UDB07_MSK 0x40006587u -#define CYREG_B1_UDB08_MSK 0x40006588u -#define CYREG_B1_UDB09_MSK 0x40006589u -#define CYREG_B1_UDB10_MSK 0x4000658au -#define CYREG_B1_UDB11_MSK 0x4000658bu -#define CYREG_B1_UDB04_ACTL 0x40006594u -#define CYREG_B1_UDB05_ACTL 0x40006595u -#define CYREG_B1_UDB06_ACTL 0x40006596u -#define CYREG_B1_UDB07_ACTL 0x40006597u -#define CYREG_B1_UDB08_ACTL 0x40006598u -#define CYREG_B1_UDB09_ACTL 0x40006599u -#define CYREG_B1_UDB10_ACTL 0x4000659au -#define CYREG_B1_UDB11_ACTL 0x4000659bu -#define CYREG_B1_UDB04_MC 0x400065a4u -#define CYREG_B1_UDB05_MC 0x400065a5u -#define CYREG_B1_UDB06_MC 0x400065a6u -#define CYREG_B1_UDB07_MC 0x400065a7u -#define CYREG_B1_UDB08_MC 0x400065a8u -#define CYREG_B1_UDB09_MC 0x400065a9u -#define CYREG_B1_UDB10_MC 0x400065aau -#define CYREG_B1_UDB11_MC 0x400065abu -#define CYDEV_UWRK_UWRK16_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u -#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u -#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u -#define CYREG_B0_UDB00_A0_A1 0x40006800u -#define CYREG_B0_UDB01_A0_A1 0x40006802u -#define CYREG_B0_UDB02_A0_A1 0x40006804u -#define CYREG_B0_UDB03_A0_A1 0x40006806u -#define CYREG_B0_UDB04_A0_A1 0x40006808u -#define CYREG_B0_UDB05_A0_A1 0x4000680au -#define CYREG_B0_UDB06_A0_A1 0x4000680cu -#define CYREG_B0_UDB07_A0_A1 0x4000680eu -#define CYREG_B0_UDB08_A0_A1 0x40006810u -#define CYREG_B0_UDB09_A0_A1 0x40006812u -#define CYREG_B0_UDB10_A0_A1 0x40006814u -#define CYREG_B0_UDB11_A0_A1 0x40006816u -#define CYREG_B0_UDB12_A0_A1 0x40006818u -#define CYREG_B0_UDB13_A0_A1 0x4000681au -#define CYREG_B0_UDB14_A0_A1 0x4000681cu -#define CYREG_B0_UDB15_A0_A1 0x4000681eu -#define CYREG_B0_UDB00_D0_D1 0x40006840u -#define CYREG_B0_UDB01_D0_D1 0x40006842u -#define CYREG_B0_UDB02_D0_D1 0x40006844u -#define CYREG_B0_UDB03_D0_D1 0x40006846u -#define CYREG_B0_UDB04_D0_D1 0x40006848u -#define CYREG_B0_UDB05_D0_D1 0x4000684au -#define CYREG_B0_UDB06_D0_D1 0x4000684cu -#define CYREG_B0_UDB07_D0_D1 0x4000684eu -#define CYREG_B0_UDB08_D0_D1 0x40006850u -#define CYREG_B0_UDB09_D0_D1 0x40006852u -#define CYREG_B0_UDB10_D0_D1 0x40006854u -#define CYREG_B0_UDB11_D0_D1 0x40006856u -#define CYREG_B0_UDB12_D0_D1 0x40006858u -#define CYREG_B0_UDB13_D0_D1 0x4000685au -#define CYREG_B0_UDB14_D0_D1 0x4000685cu -#define CYREG_B0_UDB15_D0_D1 0x4000685eu -#define CYREG_B0_UDB00_F0_F1 0x40006880u -#define CYREG_B0_UDB01_F0_F1 0x40006882u -#define CYREG_B0_UDB02_F0_F1 0x40006884u -#define CYREG_B0_UDB03_F0_F1 0x40006886u -#define CYREG_B0_UDB04_F0_F1 0x40006888u -#define CYREG_B0_UDB05_F0_F1 0x4000688au -#define CYREG_B0_UDB06_F0_F1 0x4000688cu -#define CYREG_B0_UDB07_F0_F1 0x4000688eu -#define CYREG_B0_UDB08_F0_F1 0x40006890u -#define CYREG_B0_UDB09_F0_F1 0x40006892u -#define CYREG_B0_UDB10_F0_F1 0x40006894u -#define CYREG_B0_UDB11_F0_F1 0x40006896u -#define CYREG_B0_UDB12_F0_F1 0x40006898u -#define CYREG_B0_UDB13_F0_F1 0x4000689au -#define CYREG_B0_UDB14_F0_F1 0x4000689cu -#define CYREG_B0_UDB15_F0_F1 0x4000689eu -#define CYREG_B0_UDB00_ST_CTL 0x400068c0u -#define CYREG_B0_UDB01_ST_CTL 0x400068c2u -#define CYREG_B0_UDB02_ST_CTL 0x400068c4u -#define CYREG_B0_UDB03_ST_CTL 0x400068c6u -#define CYREG_B0_UDB04_ST_CTL 0x400068c8u -#define CYREG_B0_UDB05_ST_CTL 0x400068cau -#define CYREG_B0_UDB06_ST_CTL 0x400068ccu -#define CYREG_B0_UDB07_ST_CTL 0x400068ceu -#define CYREG_B0_UDB08_ST_CTL 0x400068d0u -#define CYREG_B0_UDB09_ST_CTL 0x400068d2u -#define CYREG_B0_UDB10_ST_CTL 0x400068d4u -#define CYREG_B0_UDB11_ST_CTL 0x400068d6u -#define CYREG_B0_UDB12_ST_CTL 0x400068d8u -#define CYREG_B0_UDB13_ST_CTL 0x400068dau -#define CYREG_B0_UDB14_ST_CTL 0x400068dcu -#define CYREG_B0_UDB15_ST_CTL 0x400068deu -#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u -#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u -#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u -#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u -#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u -#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au -#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu -#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu -#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u -#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u -#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u -#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u -#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u -#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au -#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu -#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu -#define CYREG_B0_UDB00_MC_00 0x40006940u -#define CYREG_B0_UDB01_MC_00 0x40006942u -#define CYREG_B0_UDB02_MC_00 0x40006944u -#define CYREG_B0_UDB03_MC_00 0x40006946u -#define CYREG_B0_UDB04_MC_00 0x40006948u -#define CYREG_B0_UDB05_MC_00 0x4000694au -#define CYREG_B0_UDB06_MC_00 0x4000694cu -#define CYREG_B0_UDB07_MC_00 0x4000694eu -#define CYREG_B0_UDB08_MC_00 0x40006950u -#define CYREG_B0_UDB09_MC_00 0x40006952u -#define CYREG_B0_UDB10_MC_00 0x40006954u -#define CYREG_B0_UDB11_MC_00 0x40006956u -#define CYREG_B0_UDB12_MC_00 0x40006958u -#define CYREG_B0_UDB13_MC_00 0x4000695au -#define CYREG_B0_UDB14_MC_00 0x4000695cu -#define CYREG_B0_UDB15_MC_00 0x4000695eu -#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u -#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u -#define CYREG_B1_UDB04_A0_A1 0x40006a08u -#define CYREG_B1_UDB05_A0_A1 0x40006a0au -#define CYREG_B1_UDB06_A0_A1 0x40006a0cu -#define CYREG_B1_UDB07_A0_A1 0x40006a0eu -#define CYREG_B1_UDB08_A0_A1 0x40006a10u -#define CYREG_B1_UDB09_A0_A1 0x40006a12u -#define CYREG_B1_UDB10_A0_A1 0x40006a14u -#define CYREG_B1_UDB11_A0_A1 0x40006a16u -#define CYREG_B1_UDB04_D0_D1 0x40006a48u -#define CYREG_B1_UDB05_D0_D1 0x40006a4au -#define CYREG_B1_UDB06_D0_D1 0x40006a4cu -#define CYREG_B1_UDB07_D0_D1 0x40006a4eu -#define CYREG_B1_UDB08_D0_D1 0x40006a50u -#define CYREG_B1_UDB09_D0_D1 0x40006a52u -#define CYREG_B1_UDB10_D0_D1 0x40006a54u -#define CYREG_B1_UDB11_D0_D1 0x40006a56u -#define CYREG_B1_UDB04_F0_F1 0x40006a88u -#define CYREG_B1_UDB05_F0_F1 0x40006a8au -#define CYREG_B1_UDB06_F0_F1 0x40006a8cu -#define CYREG_B1_UDB07_F0_F1 0x40006a8eu -#define CYREG_B1_UDB08_F0_F1 0x40006a90u -#define CYREG_B1_UDB09_F0_F1 0x40006a92u -#define CYREG_B1_UDB10_F0_F1 0x40006a94u -#define CYREG_B1_UDB11_F0_F1 0x40006a96u -#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u -#define CYREG_B1_UDB05_ST_CTL 0x40006acau -#define CYREG_B1_UDB06_ST_CTL 0x40006accu -#define CYREG_B1_UDB07_ST_CTL 0x40006aceu -#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u -#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u -#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u -#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u -#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u -#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au -#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu -#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu -#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u -#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u -#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u -#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u -#define CYREG_B1_UDB04_MC_00 0x40006b48u -#define CYREG_B1_UDB05_MC_00 0x40006b4au -#define CYREG_B1_UDB06_MC_00 0x40006b4cu -#define CYREG_B1_UDB07_MC_00 0x40006b4eu -#define CYREG_B1_UDB08_MC_00 0x40006b50u -#define CYREG_B1_UDB09_MC_00 0x40006b52u -#define CYREG_B1_UDB10_MC_00 0x40006b54u -#define CYREG_B1_UDB11_MC_00 0x40006b56u -#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu -#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u -#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu -#define CYREG_B0_UDB00_01_A0 0x40006800u -#define CYREG_B0_UDB01_02_A0 0x40006802u -#define CYREG_B0_UDB02_03_A0 0x40006804u -#define CYREG_B0_UDB03_04_A0 0x40006806u -#define CYREG_B0_UDB04_05_A0 0x40006808u -#define CYREG_B0_UDB05_06_A0 0x4000680au -#define CYREG_B0_UDB06_07_A0 0x4000680cu -#define CYREG_B0_UDB07_08_A0 0x4000680eu -#define CYREG_B0_UDB08_09_A0 0x40006810u -#define CYREG_B0_UDB09_10_A0 0x40006812u -#define CYREG_B0_UDB10_11_A0 0x40006814u -#define CYREG_B0_UDB11_12_A0 0x40006816u -#define CYREG_B0_UDB12_13_A0 0x40006818u -#define CYREG_B0_UDB13_14_A0 0x4000681au -#define CYREG_B0_UDB14_15_A0 0x4000681cu -#define CYREG_B0_UDB00_01_A1 0x40006820u -#define CYREG_B0_UDB01_02_A1 0x40006822u -#define CYREG_B0_UDB02_03_A1 0x40006824u -#define CYREG_B0_UDB03_04_A1 0x40006826u -#define CYREG_B0_UDB04_05_A1 0x40006828u -#define CYREG_B0_UDB05_06_A1 0x4000682au -#define CYREG_B0_UDB06_07_A1 0x4000682cu -#define CYREG_B0_UDB07_08_A1 0x4000682eu -#define CYREG_B0_UDB08_09_A1 0x40006830u -#define CYREG_B0_UDB09_10_A1 0x40006832u -#define CYREG_B0_UDB10_11_A1 0x40006834u -#define CYREG_B0_UDB11_12_A1 0x40006836u -#define CYREG_B0_UDB12_13_A1 0x40006838u -#define CYREG_B0_UDB13_14_A1 0x4000683au -#define CYREG_B0_UDB14_15_A1 0x4000683cu -#define CYREG_B0_UDB00_01_D0 0x40006840u -#define CYREG_B0_UDB01_02_D0 0x40006842u -#define CYREG_B0_UDB02_03_D0 0x40006844u -#define CYREG_B0_UDB03_04_D0 0x40006846u -#define CYREG_B0_UDB04_05_D0 0x40006848u -#define CYREG_B0_UDB05_06_D0 0x4000684au -#define CYREG_B0_UDB06_07_D0 0x4000684cu -#define CYREG_B0_UDB07_08_D0 0x4000684eu -#define CYREG_B0_UDB08_09_D0 0x40006850u -#define CYREG_B0_UDB09_10_D0 0x40006852u -#define CYREG_B0_UDB10_11_D0 0x40006854u -#define CYREG_B0_UDB11_12_D0 0x40006856u -#define CYREG_B0_UDB12_13_D0 0x40006858u -#define CYREG_B0_UDB13_14_D0 0x4000685au -#define CYREG_B0_UDB14_15_D0 0x4000685cu -#define CYREG_B0_UDB00_01_D1 0x40006860u -#define CYREG_B0_UDB01_02_D1 0x40006862u -#define CYREG_B0_UDB02_03_D1 0x40006864u -#define CYREG_B0_UDB03_04_D1 0x40006866u -#define CYREG_B0_UDB04_05_D1 0x40006868u -#define CYREG_B0_UDB05_06_D1 0x4000686au -#define CYREG_B0_UDB06_07_D1 0x4000686cu -#define CYREG_B0_UDB07_08_D1 0x4000686eu -#define CYREG_B0_UDB08_09_D1 0x40006870u -#define CYREG_B0_UDB09_10_D1 0x40006872u -#define CYREG_B0_UDB10_11_D1 0x40006874u -#define CYREG_B0_UDB11_12_D1 0x40006876u -#define CYREG_B0_UDB12_13_D1 0x40006878u -#define CYREG_B0_UDB13_14_D1 0x4000687au -#define CYREG_B0_UDB14_15_D1 0x4000687cu -#define CYREG_B0_UDB00_01_F0 0x40006880u -#define CYREG_B0_UDB01_02_F0 0x40006882u -#define CYREG_B0_UDB02_03_F0 0x40006884u -#define CYREG_B0_UDB03_04_F0 0x40006886u -#define CYREG_B0_UDB04_05_F0 0x40006888u -#define CYREG_B0_UDB05_06_F0 0x4000688au -#define CYREG_B0_UDB06_07_F0 0x4000688cu -#define CYREG_B0_UDB07_08_F0 0x4000688eu -#define CYREG_B0_UDB08_09_F0 0x40006890u -#define CYREG_B0_UDB09_10_F0 0x40006892u -#define CYREG_B0_UDB10_11_F0 0x40006894u -#define CYREG_B0_UDB11_12_F0 0x40006896u -#define CYREG_B0_UDB12_13_F0 0x40006898u -#define CYREG_B0_UDB13_14_F0 0x4000689au -#define CYREG_B0_UDB14_15_F0 0x4000689cu -#define CYREG_B0_UDB00_01_F1 0x400068a0u -#define CYREG_B0_UDB01_02_F1 0x400068a2u -#define CYREG_B0_UDB02_03_F1 0x400068a4u -#define CYREG_B0_UDB03_04_F1 0x400068a6u -#define CYREG_B0_UDB04_05_F1 0x400068a8u -#define CYREG_B0_UDB05_06_F1 0x400068aau -#define CYREG_B0_UDB06_07_F1 0x400068acu -#define CYREG_B0_UDB07_08_F1 0x400068aeu -#define CYREG_B0_UDB08_09_F1 0x400068b0u -#define CYREG_B0_UDB09_10_F1 0x400068b2u -#define CYREG_B0_UDB10_11_F1 0x400068b4u -#define CYREG_B0_UDB11_12_F1 0x400068b6u -#define CYREG_B0_UDB12_13_F1 0x400068b8u -#define CYREG_B0_UDB13_14_F1 0x400068bau -#define CYREG_B0_UDB14_15_F1 0x400068bcu -#define CYREG_B0_UDB00_01_ST 0x400068c0u -#define CYREG_B0_UDB01_02_ST 0x400068c2u -#define CYREG_B0_UDB02_03_ST 0x400068c4u -#define CYREG_B0_UDB03_04_ST 0x400068c6u -#define CYREG_B0_UDB04_05_ST 0x400068c8u -#define CYREG_B0_UDB05_06_ST 0x400068cau -#define CYREG_B0_UDB06_07_ST 0x400068ccu -#define CYREG_B0_UDB07_08_ST 0x400068ceu -#define CYREG_B0_UDB08_09_ST 0x400068d0u -#define CYREG_B0_UDB09_10_ST 0x400068d2u -#define CYREG_B0_UDB10_11_ST 0x400068d4u -#define CYREG_B0_UDB11_12_ST 0x400068d6u -#define CYREG_B0_UDB12_13_ST 0x400068d8u -#define CYREG_B0_UDB13_14_ST 0x400068dau -#define CYREG_B0_UDB14_15_ST 0x400068dcu -#define CYREG_B0_UDB00_01_CTL 0x400068e0u -#define CYREG_B0_UDB01_02_CTL 0x400068e2u -#define CYREG_B0_UDB02_03_CTL 0x400068e4u -#define CYREG_B0_UDB03_04_CTL 0x400068e6u -#define CYREG_B0_UDB04_05_CTL 0x400068e8u -#define CYREG_B0_UDB05_06_CTL 0x400068eau -#define CYREG_B0_UDB06_07_CTL 0x400068ecu -#define CYREG_B0_UDB07_08_CTL 0x400068eeu -#define CYREG_B0_UDB08_09_CTL 0x400068f0u -#define CYREG_B0_UDB09_10_CTL 0x400068f2u -#define CYREG_B0_UDB10_11_CTL 0x400068f4u -#define CYREG_B0_UDB11_12_CTL 0x400068f6u -#define CYREG_B0_UDB12_13_CTL 0x400068f8u -#define CYREG_B0_UDB13_14_CTL 0x400068fau -#define CYREG_B0_UDB14_15_CTL 0x400068fcu -#define CYREG_B0_UDB00_01_MSK 0x40006900u -#define CYREG_B0_UDB01_02_MSK 0x40006902u -#define CYREG_B0_UDB02_03_MSK 0x40006904u -#define CYREG_B0_UDB03_04_MSK 0x40006906u -#define CYREG_B0_UDB04_05_MSK 0x40006908u -#define CYREG_B0_UDB05_06_MSK 0x4000690au -#define CYREG_B0_UDB06_07_MSK 0x4000690cu -#define CYREG_B0_UDB07_08_MSK 0x4000690eu -#define CYREG_B0_UDB08_09_MSK 0x40006910u -#define CYREG_B0_UDB09_10_MSK 0x40006912u -#define CYREG_B0_UDB10_11_MSK 0x40006914u -#define CYREG_B0_UDB11_12_MSK 0x40006916u -#define CYREG_B0_UDB12_13_MSK 0x40006918u -#define CYREG_B0_UDB13_14_MSK 0x4000691au -#define CYREG_B0_UDB14_15_MSK 0x4000691cu -#define CYREG_B0_UDB00_01_ACTL 0x40006920u -#define CYREG_B0_UDB01_02_ACTL 0x40006922u -#define CYREG_B0_UDB02_03_ACTL 0x40006924u -#define CYREG_B0_UDB03_04_ACTL 0x40006926u -#define CYREG_B0_UDB04_05_ACTL 0x40006928u -#define CYREG_B0_UDB05_06_ACTL 0x4000692au -#define CYREG_B0_UDB06_07_ACTL 0x4000692cu -#define CYREG_B0_UDB07_08_ACTL 0x4000692eu -#define CYREG_B0_UDB08_09_ACTL 0x40006930u -#define CYREG_B0_UDB09_10_ACTL 0x40006932u -#define CYREG_B0_UDB10_11_ACTL 0x40006934u -#define CYREG_B0_UDB11_12_ACTL 0x40006936u -#define CYREG_B0_UDB12_13_ACTL 0x40006938u -#define CYREG_B0_UDB13_14_ACTL 0x4000693au -#define CYREG_B0_UDB14_15_ACTL 0x4000693cu -#define CYREG_B0_UDB00_01_MC 0x40006940u -#define CYREG_B0_UDB01_02_MC 0x40006942u -#define CYREG_B0_UDB02_03_MC 0x40006944u -#define CYREG_B0_UDB03_04_MC 0x40006946u -#define CYREG_B0_UDB04_05_MC 0x40006948u -#define CYREG_B0_UDB05_06_MC 0x4000694au -#define CYREG_B0_UDB06_07_MC 0x4000694cu -#define CYREG_B0_UDB07_08_MC 0x4000694eu -#define CYREG_B0_UDB08_09_MC 0x40006950u -#define CYREG_B0_UDB09_10_MC 0x40006952u -#define CYREG_B0_UDB10_11_MC 0x40006954u -#define CYREG_B0_UDB11_12_MC 0x40006956u -#define CYREG_B0_UDB12_13_MC 0x40006958u -#define CYREG_B0_UDB13_14_MC 0x4000695au -#define CYREG_B0_UDB14_15_MC 0x4000695cu -#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u -#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu -#define CYREG_B1_UDB04_05_A0 0x40006a08u -#define CYREG_B1_UDB05_06_A0 0x40006a0au -#define CYREG_B1_UDB06_07_A0 0x40006a0cu -#define CYREG_B1_UDB07_08_A0 0x40006a0eu -#define CYREG_B1_UDB08_09_A0 0x40006a10u -#define CYREG_B1_UDB09_10_A0 0x40006a12u -#define CYREG_B1_UDB10_11_A0 0x40006a14u -#define CYREG_B1_UDB11_12_A0 0x40006a16u -#define CYREG_B1_UDB04_05_A1 0x40006a28u -#define CYREG_B1_UDB05_06_A1 0x40006a2au -#define CYREG_B1_UDB06_07_A1 0x40006a2cu -#define CYREG_B1_UDB07_08_A1 0x40006a2eu -#define CYREG_B1_UDB08_09_A1 0x40006a30u -#define CYREG_B1_UDB09_10_A1 0x40006a32u -#define CYREG_B1_UDB10_11_A1 0x40006a34u -#define CYREG_B1_UDB11_12_A1 0x40006a36u -#define CYREG_B1_UDB04_05_D0 0x40006a48u -#define CYREG_B1_UDB05_06_D0 0x40006a4au -#define CYREG_B1_UDB06_07_D0 0x40006a4cu -#define CYREG_B1_UDB07_08_D0 0x40006a4eu -#define CYREG_B1_UDB08_09_D0 0x40006a50u -#define CYREG_B1_UDB09_10_D0 0x40006a52u -#define CYREG_B1_UDB10_11_D0 0x40006a54u -#define CYREG_B1_UDB11_12_D0 0x40006a56u -#define CYREG_B1_UDB04_05_D1 0x40006a68u -#define CYREG_B1_UDB05_06_D1 0x40006a6au -#define CYREG_B1_UDB06_07_D1 0x40006a6cu -#define CYREG_B1_UDB07_08_D1 0x40006a6eu -#define CYREG_B1_UDB08_09_D1 0x40006a70u -#define CYREG_B1_UDB09_10_D1 0x40006a72u -#define CYREG_B1_UDB10_11_D1 0x40006a74u -#define CYREG_B1_UDB11_12_D1 0x40006a76u -#define CYREG_B1_UDB04_05_F0 0x40006a88u -#define CYREG_B1_UDB05_06_F0 0x40006a8au -#define CYREG_B1_UDB06_07_F0 0x40006a8cu -#define CYREG_B1_UDB07_08_F0 0x40006a8eu -#define CYREG_B1_UDB08_09_F0 0x40006a90u -#define CYREG_B1_UDB09_10_F0 0x40006a92u -#define CYREG_B1_UDB10_11_F0 0x40006a94u -#define CYREG_B1_UDB11_12_F0 0x40006a96u -#define CYREG_B1_UDB04_05_F1 0x40006aa8u -#define CYREG_B1_UDB05_06_F1 0x40006aaau -#define CYREG_B1_UDB06_07_F1 0x40006aacu -#define CYREG_B1_UDB07_08_F1 0x40006aaeu -#define CYREG_B1_UDB08_09_F1 0x40006ab0u -#define CYREG_B1_UDB09_10_F1 0x40006ab2u -#define CYREG_B1_UDB10_11_F1 0x40006ab4u -#define CYREG_B1_UDB11_12_F1 0x40006ab6u -#define CYREG_B1_UDB04_05_ST 0x40006ac8u -#define CYREG_B1_UDB05_06_ST 0x40006acau -#define CYREG_B1_UDB06_07_ST 0x40006accu -#define CYREG_B1_UDB07_08_ST 0x40006aceu -#define CYREG_B1_UDB08_09_ST 0x40006ad0u -#define CYREG_B1_UDB09_10_ST 0x40006ad2u -#define CYREG_B1_UDB10_11_ST 0x40006ad4u -#define CYREG_B1_UDB11_12_ST 0x40006ad6u -#define CYREG_B1_UDB04_05_CTL 0x40006ae8u -#define CYREG_B1_UDB05_06_CTL 0x40006aeau -#define CYREG_B1_UDB06_07_CTL 0x40006aecu -#define CYREG_B1_UDB07_08_CTL 0x40006aeeu -#define CYREG_B1_UDB08_09_CTL 0x40006af0u -#define CYREG_B1_UDB09_10_CTL 0x40006af2u -#define CYREG_B1_UDB10_11_CTL 0x40006af4u -#define CYREG_B1_UDB11_12_CTL 0x40006af6u -#define CYREG_B1_UDB04_05_MSK 0x40006b08u -#define CYREG_B1_UDB05_06_MSK 0x40006b0au -#define CYREG_B1_UDB06_07_MSK 0x40006b0cu -#define CYREG_B1_UDB07_08_MSK 0x40006b0eu -#define CYREG_B1_UDB08_09_MSK 0x40006b10u -#define CYREG_B1_UDB09_10_MSK 0x40006b12u -#define CYREG_B1_UDB10_11_MSK 0x40006b14u -#define CYREG_B1_UDB11_12_MSK 0x40006b16u -#define CYREG_B1_UDB04_05_ACTL 0x40006b28u -#define CYREG_B1_UDB05_06_ACTL 0x40006b2au -#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu -#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu -#define CYREG_B1_UDB08_09_ACTL 0x40006b30u -#define CYREG_B1_UDB09_10_ACTL 0x40006b32u -#define CYREG_B1_UDB10_11_ACTL 0x40006b34u -#define CYREG_B1_UDB11_12_ACTL 0x40006b36u -#define CYREG_B1_UDB04_05_MC 0x40006b48u -#define CYREG_B1_UDB05_06_MC 0x40006b4au -#define CYREG_B1_UDB06_07_MC 0x40006b4cu -#define CYREG_B1_UDB07_08_MC 0x40006b4eu -#define CYREG_B1_UDB08_09_MC 0x40006b50u -#define CYREG_B1_UDB09_10_MC 0x40006b52u -#define CYREG_B1_UDB10_11_MC 0x40006b54u -#define CYREG_B1_UDB11_12_MC 0x40006b56u -#define CYDEV_PHUB_BASE 0x40007000u -#define CYDEV_PHUB_SIZE 0x00000c00u -#define CYREG_PHUB_CFG 0x40007000u -#define CYREG_PHUB_ERR 0x40007004u -#define CYREG_PHUB_ERR_ADR 0x40007008u -#define CYDEV_PHUB_CH0_BASE 0x40007010u -#define CYDEV_PHUB_CH0_SIZE 0x0000000cu -#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u -#define CYREG_PHUB_CH0_ACTION 0x40007014u -#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u -#define CYDEV_PHUB_CH1_BASE 0x40007020u -#define CYDEV_PHUB_CH1_SIZE 0x0000000cu -#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u -#define CYREG_PHUB_CH1_ACTION 0x40007024u -#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u -#define CYDEV_PHUB_CH2_BASE 0x40007030u -#define CYDEV_PHUB_CH2_SIZE 0x0000000cu -#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u -#define CYREG_PHUB_CH2_ACTION 0x40007034u -#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u -#define CYDEV_PHUB_CH3_BASE 0x40007040u -#define CYDEV_PHUB_CH3_SIZE 0x0000000cu -#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u -#define CYREG_PHUB_CH3_ACTION 0x40007044u -#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u -#define CYDEV_PHUB_CH4_BASE 0x40007050u -#define CYDEV_PHUB_CH4_SIZE 0x0000000cu -#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u -#define CYREG_PHUB_CH4_ACTION 0x40007054u -#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u -#define CYDEV_PHUB_CH5_BASE 0x40007060u -#define CYDEV_PHUB_CH5_SIZE 0x0000000cu -#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u -#define CYREG_PHUB_CH5_ACTION 0x40007064u -#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u -#define CYDEV_PHUB_CH6_BASE 0x40007070u -#define CYDEV_PHUB_CH6_SIZE 0x0000000cu -#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u -#define CYREG_PHUB_CH6_ACTION 0x40007074u -#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u -#define CYDEV_PHUB_CH7_BASE 0x40007080u -#define CYDEV_PHUB_CH7_SIZE 0x0000000cu -#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u -#define CYREG_PHUB_CH7_ACTION 0x40007084u -#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u -#define CYDEV_PHUB_CH8_BASE 0x40007090u -#define CYDEV_PHUB_CH8_SIZE 0x0000000cu -#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u -#define CYREG_PHUB_CH8_ACTION 0x40007094u -#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u -#define CYDEV_PHUB_CH9_BASE 0x400070a0u -#define CYDEV_PHUB_CH9_SIZE 0x0000000cu -#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u -#define CYREG_PHUB_CH9_ACTION 0x400070a4u -#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u -#define CYDEV_PHUB_CH10_BASE 0x400070b0u -#define CYDEV_PHUB_CH10_SIZE 0x0000000cu -#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u -#define CYREG_PHUB_CH10_ACTION 0x400070b4u -#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u -#define CYDEV_PHUB_CH11_BASE 0x400070c0u -#define CYDEV_PHUB_CH11_SIZE 0x0000000cu -#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u -#define CYREG_PHUB_CH11_ACTION 0x400070c4u -#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u -#define CYDEV_PHUB_CH12_BASE 0x400070d0u -#define CYDEV_PHUB_CH12_SIZE 0x0000000cu -#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u -#define CYREG_PHUB_CH12_ACTION 0x400070d4u -#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u -#define CYDEV_PHUB_CH13_BASE 0x400070e0u -#define CYDEV_PHUB_CH13_SIZE 0x0000000cu -#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u -#define CYREG_PHUB_CH13_ACTION 0x400070e4u -#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u -#define CYDEV_PHUB_CH14_BASE 0x400070f0u -#define CYDEV_PHUB_CH14_SIZE 0x0000000cu -#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u -#define CYREG_PHUB_CH14_ACTION 0x400070f4u -#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u -#define CYDEV_PHUB_CH15_BASE 0x40007100u -#define CYDEV_PHUB_CH15_SIZE 0x0000000cu -#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u -#define CYREG_PHUB_CH15_ACTION 0x40007104u -#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u -#define CYDEV_PHUB_CH16_BASE 0x40007110u -#define CYDEV_PHUB_CH16_SIZE 0x0000000cu -#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u -#define CYREG_PHUB_CH16_ACTION 0x40007114u -#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u -#define CYDEV_PHUB_CH17_BASE 0x40007120u -#define CYDEV_PHUB_CH17_SIZE 0x0000000cu -#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u -#define CYREG_PHUB_CH17_ACTION 0x40007124u -#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u -#define CYDEV_PHUB_CH18_BASE 0x40007130u -#define CYDEV_PHUB_CH18_SIZE 0x0000000cu -#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u -#define CYREG_PHUB_CH18_ACTION 0x40007134u -#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u -#define CYDEV_PHUB_CH19_BASE 0x40007140u -#define CYDEV_PHUB_CH19_SIZE 0x0000000cu -#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u -#define CYREG_PHUB_CH19_ACTION 0x40007144u -#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u -#define CYDEV_PHUB_CH20_BASE 0x40007150u -#define CYDEV_PHUB_CH20_SIZE 0x0000000cu -#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u -#define CYREG_PHUB_CH20_ACTION 0x40007154u -#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u -#define CYDEV_PHUB_CH21_BASE 0x40007160u -#define CYDEV_PHUB_CH21_SIZE 0x0000000cu -#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u -#define CYREG_PHUB_CH21_ACTION 0x40007164u -#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u -#define CYDEV_PHUB_CH22_BASE 0x40007170u -#define CYDEV_PHUB_CH22_SIZE 0x0000000cu -#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u -#define CYREG_PHUB_CH22_ACTION 0x40007174u -#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u -#define CYDEV_PHUB_CH23_BASE 0x40007180u -#define CYDEV_PHUB_CH23_SIZE 0x0000000cu -#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u -#define CYREG_PHUB_CH23_ACTION 0x40007184u -#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u -#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u -#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u -#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u -#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u -#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u -#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu -#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u -#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u -#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u -#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u -#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u -#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu -#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u -#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u -#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u -#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u -#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u -#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu -#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u -#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u -#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u -#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u -#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u -#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu -#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u -#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u -#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u -#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u -#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u -#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu -#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u -#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u -#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u -#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u -#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u -#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu -#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u -#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u -#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u -#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u -#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u -#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu -#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u -#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u -#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u -#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u -#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u -#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu -#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u -#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u -#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u -#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u -#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u -#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu -#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u -#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u -#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u -#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u -#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u -#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu -#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u -#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u -#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u -#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u -#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u -#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu -#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u -#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u -#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u -#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u -#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u -#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u -#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu -#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u -#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u -#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u -#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u -#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u -#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu -#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u -#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u -#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u -#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u -#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u -#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu -#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u -#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u -#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u -#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u -#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u -#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu -#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u -#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u -#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u -#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u -#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u -#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu -#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u -#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u -#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u -#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u -#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u -#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu -#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u -#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u -#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u -#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u -#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u -#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu -#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u -#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u -#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u -#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u -#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u -#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu -#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u -#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u -#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u -#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u -#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u -#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu -#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u -#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u -#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u -#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u -#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u -#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu -#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u -#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u -#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u -#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u -#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u -#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu -#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u -#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u -#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u -#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u -#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u -#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu -#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u -#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u -#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u -#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u -#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u -#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu -#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u -#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u -#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u -#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u -#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u -#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu -#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u -#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u -#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u -#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u -#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u -#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu -#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u -#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u -#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u -#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u -#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u -#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu -#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u -#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u -#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u -#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u -#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u -#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu -#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u -#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u -#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u -#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u -#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u -#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu -#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u -#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u -#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u -#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u -#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u -#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu -#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u -#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u -#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u -#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u -#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u -#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu -#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u -#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u -#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u -#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u -#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u -#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu -#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u -#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u -#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u -#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u -#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u -#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu -#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u -#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u -#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u -#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u -#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u -#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu -#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u -#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u -#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u -#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u -#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u -#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu -#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u -#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u -#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u -#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u -#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u -#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu -#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u -#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u -#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u -#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u -#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u -#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu -#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u -#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u -#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u -#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u -#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u -#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu -#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u -#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u -#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u -#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u -#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u -#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu -#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u -#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u -#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u -#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u -#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u -#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu -#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u -#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u -#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u -#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u -#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u -#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu -#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u -#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u -#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u -#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u -#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u -#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu -#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u -#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u -#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u -#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u -#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u -#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu -#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u -#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u -#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u -#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u -#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u -#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu -#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u -#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u -#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u -#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u -#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u -#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu -#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u -#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u -#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u -#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u -#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u -#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu -#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u -#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u -#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u -#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u -#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u -#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu -#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u -#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u -#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u -#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u -#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u -#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu -#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u -#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u -#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u -#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u -#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u -#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu -#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u -#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u -#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u -#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u -#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u -#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu -#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u -#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u -#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u -#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u -#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u -#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu -#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u -#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u -#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u -#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u -#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u -#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu -#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u -#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u -#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u -#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u -#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u -#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu -#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u -#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u -#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u -#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u -#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u -#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu -#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u -#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u -#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u -#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u -#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u -#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu -#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u -#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u -#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u -#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u -#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u -#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu -#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u -#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u -#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u -#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u -#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u -#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu -#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u -#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u -#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u -#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u -#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u -#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu -#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u -#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u -#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u -#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u -#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u -#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu -#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u -#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u -#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u -#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u -#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u -#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu -#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u -#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u -#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u -#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u -#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u -#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu -#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u -#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u -#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u -#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u -#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u -#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu -#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u -#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u -#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u -#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u -#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u -#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu -#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u -#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u -#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u -#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u -#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u -#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu -#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u -#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u -#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u -#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u -#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u -#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu -#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u -#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u -#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u -#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u -#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u -#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu -#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u -#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u -#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u -#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u -#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u -#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu -#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u -#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u -#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u -#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u -#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u -#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu -#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u -#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u -#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u -#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u -#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u -#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu -#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u -#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u -#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u -#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u -#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u -#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu -#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u -#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u -#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u -#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u -#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u -#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu -#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u -#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u -#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u -#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u -#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u -#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu -#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u -#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u -#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u -#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u -#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u -#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu -#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u -#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u -#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u -#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u -#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u -#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu -#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u -#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u -#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u -#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u -#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u -#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu -#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u -#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u -#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u -#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u -#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u -#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u -#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu -#define CYDEV_EE_BASE 0x40008000u -#define CYDEV_EE_SIZE 0x00000800u -#define CYREG_EE_DATA_MBASE 0x40008000u -#define CYREG_EE_DATA_MSIZE 0x00000800u -#define CYDEV_CAN0_BASE 0x4000a000u -#define CYDEV_CAN0_SIZE 0x000002a0u -#define CYDEV_CAN0_CSR_BASE 0x4000a000u -#define CYDEV_CAN0_CSR_SIZE 0x00000018u -#define CYREG_CAN0_CSR_INT_SR 0x4000a000u -#define CYREG_CAN0_CSR_INT_EN 0x4000a004u -#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u -#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu -#define CYREG_CAN0_CSR_CMD 0x4000a010u -#define CYREG_CAN0_CSR_CFG 0x4000a014u -#define CYDEV_CAN0_TX0_BASE 0x4000a020u -#define CYDEV_CAN0_TX0_SIZE 0x00000010u -#define CYREG_CAN0_TX0_CMD 0x4000a020u -#define CYREG_CAN0_TX0_ID 0x4000a024u -#define CYREG_CAN0_TX0_DH 0x4000a028u -#define CYREG_CAN0_TX0_DL 0x4000a02cu -#define CYDEV_CAN0_TX1_BASE 0x4000a030u -#define CYDEV_CAN0_TX1_SIZE 0x00000010u -#define CYREG_CAN0_TX1_CMD 0x4000a030u -#define CYREG_CAN0_TX1_ID 0x4000a034u -#define CYREG_CAN0_TX1_DH 0x4000a038u -#define CYREG_CAN0_TX1_DL 0x4000a03cu -#define CYDEV_CAN0_TX2_BASE 0x4000a040u -#define CYDEV_CAN0_TX2_SIZE 0x00000010u -#define CYREG_CAN0_TX2_CMD 0x4000a040u -#define CYREG_CAN0_TX2_ID 0x4000a044u -#define CYREG_CAN0_TX2_DH 0x4000a048u -#define CYREG_CAN0_TX2_DL 0x4000a04cu -#define CYDEV_CAN0_TX3_BASE 0x4000a050u -#define CYDEV_CAN0_TX3_SIZE 0x00000010u -#define CYREG_CAN0_TX3_CMD 0x4000a050u -#define CYREG_CAN0_TX3_ID 0x4000a054u -#define CYREG_CAN0_TX3_DH 0x4000a058u -#define CYREG_CAN0_TX3_DL 0x4000a05cu -#define CYDEV_CAN0_TX4_BASE 0x4000a060u -#define CYDEV_CAN0_TX4_SIZE 0x00000010u -#define CYREG_CAN0_TX4_CMD 0x4000a060u -#define CYREG_CAN0_TX4_ID 0x4000a064u -#define CYREG_CAN0_TX4_DH 0x4000a068u -#define CYREG_CAN0_TX4_DL 0x4000a06cu -#define CYDEV_CAN0_TX5_BASE 0x4000a070u -#define CYDEV_CAN0_TX5_SIZE 0x00000010u -#define CYREG_CAN0_TX5_CMD 0x4000a070u -#define CYREG_CAN0_TX5_ID 0x4000a074u -#define CYREG_CAN0_TX5_DH 0x4000a078u -#define CYREG_CAN0_TX5_DL 0x4000a07cu -#define CYDEV_CAN0_TX6_BASE 0x4000a080u -#define CYDEV_CAN0_TX6_SIZE 0x00000010u -#define CYREG_CAN0_TX6_CMD 0x4000a080u -#define CYREG_CAN0_TX6_ID 0x4000a084u -#define CYREG_CAN0_TX6_DH 0x4000a088u -#define CYREG_CAN0_TX6_DL 0x4000a08cu -#define CYDEV_CAN0_TX7_BASE 0x4000a090u -#define CYDEV_CAN0_TX7_SIZE 0x00000010u -#define CYREG_CAN0_TX7_CMD 0x4000a090u -#define CYREG_CAN0_TX7_ID 0x4000a094u -#define CYREG_CAN0_TX7_DH 0x4000a098u -#define CYREG_CAN0_TX7_DL 0x4000a09cu -#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u -#define CYDEV_CAN0_RX0_SIZE 0x00000020u -#define CYREG_CAN0_RX0_CMD 0x4000a0a0u -#define CYREG_CAN0_RX0_ID 0x4000a0a4u -#define CYREG_CAN0_RX0_DH 0x4000a0a8u -#define CYREG_CAN0_RX0_DL 0x4000a0acu -#define CYREG_CAN0_RX0_AMR 0x4000a0b0u -#define CYREG_CAN0_RX0_ACR 0x4000a0b4u -#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u -#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu -#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u -#define CYDEV_CAN0_RX1_SIZE 0x00000020u -#define CYREG_CAN0_RX1_CMD 0x4000a0c0u -#define CYREG_CAN0_RX1_ID 0x4000a0c4u -#define CYREG_CAN0_RX1_DH 0x4000a0c8u -#define CYREG_CAN0_RX1_DL 0x4000a0ccu -#define CYREG_CAN0_RX1_AMR 0x4000a0d0u -#define CYREG_CAN0_RX1_ACR 0x4000a0d4u -#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u -#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu -#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u -#define CYDEV_CAN0_RX2_SIZE 0x00000020u -#define CYREG_CAN0_RX2_CMD 0x4000a0e0u -#define CYREG_CAN0_RX2_ID 0x4000a0e4u -#define CYREG_CAN0_RX2_DH 0x4000a0e8u -#define CYREG_CAN0_RX2_DL 0x4000a0ecu -#define CYREG_CAN0_RX2_AMR 0x4000a0f0u -#define CYREG_CAN0_RX2_ACR 0x4000a0f4u -#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u -#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu -#define CYDEV_CAN0_RX3_BASE 0x4000a100u -#define CYDEV_CAN0_RX3_SIZE 0x00000020u -#define CYREG_CAN0_RX3_CMD 0x4000a100u -#define CYREG_CAN0_RX3_ID 0x4000a104u -#define CYREG_CAN0_RX3_DH 0x4000a108u -#define CYREG_CAN0_RX3_DL 0x4000a10cu -#define CYREG_CAN0_RX3_AMR 0x4000a110u -#define CYREG_CAN0_RX3_ACR 0x4000a114u -#define CYREG_CAN0_RX3_AMRD 0x4000a118u -#define CYREG_CAN0_RX3_ACRD 0x4000a11cu -#define CYDEV_CAN0_RX4_BASE 0x4000a120u -#define CYDEV_CAN0_RX4_SIZE 0x00000020u -#define CYREG_CAN0_RX4_CMD 0x4000a120u -#define CYREG_CAN0_RX4_ID 0x4000a124u -#define CYREG_CAN0_RX4_DH 0x4000a128u -#define CYREG_CAN0_RX4_DL 0x4000a12cu -#define CYREG_CAN0_RX4_AMR 0x4000a130u -#define CYREG_CAN0_RX4_ACR 0x4000a134u -#define CYREG_CAN0_RX4_AMRD 0x4000a138u -#define CYREG_CAN0_RX4_ACRD 0x4000a13cu -#define CYDEV_CAN0_RX5_BASE 0x4000a140u -#define CYDEV_CAN0_RX5_SIZE 0x00000020u -#define CYREG_CAN0_RX5_CMD 0x4000a140u -#define CYREG_CAN0_RX5_ID 0x4000a144u -#define CYREG_CAN0_RX5_DH 0x4000a148u -#define CYREG_CAN0_RX5_DL 0x4000a14cu -#define CYREG_CAN0_RX5_AMR 0x4000a150u -#define CYREG_CAN0_RX5_ACR 0x4000a154u -#define CYREG_CAN0_RX5_AMRD 0x4000a158u -#define CYREG_CAN0_RX5_ACRD 0x4000a15cu -#define CYDEV_CAN0_RX6_BASE 0x4000a160u -#define CYDEV_CAN0_RX6_SIZE 0x00000020u -#define CYREG_CAN0_RX6_CMD 0x4000a160u -#define CYREG_CAN0_RX6_ID 0x4000a164u -#define CYREG_CAN0_RX6_DH 0x4000a168u -#define CYREG_CAN0_RX6_DL 0x4000a16cu -#define CYREG_CAN0_RX6_AMR 0x4000a170u -#define CYREG_CAN0_RX6_ACR 0x4000a174u -#define CYREG_CAN0_RX6_AMRD 0x4000a178u -#define CYREG_CAN0_RX6_ACRD 0x4000a17cu -#define CYDEV_CAN0_RX7_BASE 0x4000a180u -#define CYDEV_CAN0_RX7_SIZE 0x00000020u -#define CYREG_CAN0_RX7_CMD 0x4000a180u -#define CYREG_CAN0_RX7_ID 0x4000a184u -#define CYREG_CAN0_RX7_DH 0x4000a188u -#define CYREG_CAN0_RX7_DL 0x4000a18cu -#define CYREG_CAN0_RX7_AMR 0x4000a190u -#define CYREG_CAN0_RX7_ACR 0x4000a194u -#define CYREG_CAN0_RX7_AMRD 0x4000a198u -#define CYREG_CAN0_RX7_ACRD 0x4000a19cu -#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u -#define CYDEV_CAN0_RX8_SIZE 0x00000020u -#define CYREG_CAN0_RX8_CMD 0x4000a1a0u -#define CYREG_CAN0_RX8_ID 0x4000a1a4u -#define CYREG_CAN0_RX8_DH 0x4000a1a8u -#define CYREG_CAN0_RX8_DL 0x4000a1acu -#define CYREG_CAN0_RX8_AMR 0x4000a1b0u -#define CYREG_CAN0_RX8_ACR 0x4000a1b4u -#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u -#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu -#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u -#define CYDEV_CAN0_RX9_SIZE 0x00000020u -#define CYREG_CAN0_RX9_CMD 0x4000a1c0u -#define CYREG_CAN0_RX9_ID 0x4000a1c4u -#define CYREG_CAN0_RX9_DH 0x4000a1c8u -#define CYREG_CAN0_RX9_DL 0x4000a1ccu -#define CYREG_CAN0_RX9_AMR 0x4000a1d0u -#define CYREG_CAN0_RX9_ACR 0x4000a1d4u -#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u -#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu -#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u -#define CYDEV_CAN0_RX10_SIZE 0x00000020u -#define CYREG_CAN0_RX10_CMD 0x4000a1e0u -#define CYREG_CAN0_RX10_ID 0x4000a1e4u -#define CYREG_CAN0_RX10_DH 0x4000a1e8u -#define CYREG_CAN0_RX10_DL 0x4000a1ecu -#define CYREG_CAN0_RX10_AMR 0x4000a1f0u -#define CYREG_CAN0_RX10_ACR 0x4000a1f4u -#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u -#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu -#define CYDEV_CAN0_RX11_BASE 0x4000a200u -#define CYDEV_CAN0_RX11_SIZE 0x00000020u -#define CYREG_CAN0_RX11_CMD 0x4000a200u -#define CYREG_CAN0_RX11_ID 0x4000a204u -#define CYREG_CAN0_RX11_DH 0x4000a208u -#define CYREG_CAN0_RX11_DL 0x4000a20cu -#define CYREG_CAN0_RX11_AMR 0x4000a210u -#define CYREG_CAN0_RX11_ACR 0x4000a214u -#define CYREG_CAN0_RX11_AMRD 0x4000a218u -#define CYREG_CAN0_RX11_ACRD 0x4000a21cu -#define CYDEV_CAN0_RX12_BASE 0x4000a220u -#define CYDEV_CAN0_RX12_SIZE 0x00000020u -#define CYREG_CAN0_RX12_CMD 0x4000a220u -#define CYREG_CAN0_RX12_ID 0x4000a224u -#define CYREG_CAN0_RX12_DH 0x4000a228u -#define CYREG_CAN0_RX12_DL 0x4000a22cu -#define CYREG_CAN0_RX12_AMR 0x4000a230u -#define CYREG_CAN0_RX12_ACR 0x4000a234u -#define CYREG_CAN0_RX12_AMRD 0x4000a238u -#define CYREG_CAN0_RX12_ACRD 0x4000a23cu -#define CYDEV_CAN0_RX13_BASE 0x4000a240u -#define CYDEV_CAN0_RX13_SIZE 0x00000020u -#define CYREG_CAN0_RX13_CMD 0x4000a240u -#define CYREG_CAN0_RX13_ID 0x4000a244u -#define CYREG_CAN0_RX13_DH 0x4000a248u -#define CYREG_CAN0_RX13_DL 0x4000a24cu -#define CYREG_CAN0_RX13_AMR 0x4000a250u -#define CYREG_CAN0_RX13_ACR 0x4000a254u -#define CYREG_CAN0_RX13_AMRD 0x4000a258u -#define CYREG_CAN0_RX13_ACRD 0x4000a25cu -#define CYDEV_CAN0_RX14_BASE 0x4000a260u -#define CYDEV_CAN0_RX14_SIZE 0x00000020u -#define CYREG_CAN0_RX14_CMD 0x4000a260u -#define CYREG_CAN0_RX14_ID 0x4000a264u -#define CYREG_CAN0_RX14_DH 0x4000a268u -#define CYREG_CAN0_RX14_DL 0x4000a26cu -#define CYREG_CAN0_RX14_AMR 0x4000a270u -#define CYREG_CAN0_RX14_ACR 0x4000a274u -#define CYREG_CAN0_RX14_AMRD 0x4000a278u -#define CYREG_CAN0_RX14_ACRD 0x4000a27cu -#define CYDEV_CAN0_RX15_BASE 0x4000a280u -#define CYDEV_CAN0_RX15_SIZE 0x00000020u -#define CYREG_CAN0_RX15_CMD 0x4000a280u -#define CYREG_CAN0_RX15_ID 0x4000a284u -#define CYREG_CAN0_RX15_DH 0x4000a288u -#define CYREG_CAN0_RX15_DL 0x4000a28cu -#define CYREG_CAN0_RX15_AMR 0x4000a290u -#define CYREG_CAN0_RX15_ACR 0x4000a294u -#define CYREG_CAN0_RX15_AMRD 0x4000a298u -#define CYREG_CAN0_RX15_ACRD 0x4000a29cu -#define CYDEV_DFB0_BASE 0x4000c000u -#define CYDEV_DFB0_SIZE 0x000007b5u -#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u -#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u -#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u -#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u -#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u -#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u -#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u -#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u -#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u -#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u -#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u -#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u -#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u -#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u -#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u -#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u -#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u -#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u -#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u -#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u -#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u -#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u -#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u -#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u -#define CYREG_DFB0_CR 0x4000c780u -#define CYREG_DFB0_SR 0x4000c784u -#define CYREG_DFB0_RAM_EN 0x4000c788u -#define CYREG_DFB0_RAM_DIR 0x4000c78cu -#define CYREG_DFB0_SEMA 0x4000c790u -#define CYREG_DFB0_DSI_CTRL 0x4000c794u -#define CYREG_DFB0_INT_CTRL 0x4000c798u -#define CYREG_DFB0_DMA_CTRL 0x4000c79cu -#define CYREG_DFB0_STAGEA 0x4000c7a0u -#define CYREG_DFB0_STAGEAM 0x4000c7a1u -#define CYREG_DFB0_STAGEAH 0x4000c7a2u -#define CYREG_DFB0_STAGEB 0x4000c7a4u -#define CYREG_DFB0_STAGEBM 0x4000c7a5u -#define CYREG_DFB0_STAGEBH 0x4000c7a6u -#define CYREG_DFB0_HOLDA 0x4000c7a8u -#define CYREG_DFB0_HOLDAM 0x4000c7a9u -#define CYREG_DFB0_HOLDAH 0x4000c7aau -#define CYREG_DFB0_HOLDAS 0x4000c7abu -#define CYREG_DFB0_HOLDB 0x4000c7acu -#define CYREG_DFB0_HOLDBM 0x4000c7adu -#define CYREG_DFB0_HOLDBH 0x4000c7aeu -#define CYREG_DFB0_HOLDBS 0x4000c7afu -#define CYREG_DFB0_COHER 0x4000c7b0u -#define CYREG_DFB0_DALIGN 0x4000c7b4u -#define CYDEV_UCFG_BASE 0x40010000u -#define CYDEV_UCFG_SIZE 0x00005040u -#define CYDEV_UCFG_B0_BASE 0x40010000u -#define CYDEV_UCFG_B0_SIZE 0x00000fefu -#define CYDEV_UCFG_B0_P0_BASE 0x40010000u -#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u -#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u -#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u -#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u -#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u -#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu -#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u -#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u -#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u -#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu -#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u -#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u -#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u -#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu -#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u -#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u -#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u -#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u -#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u -#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au -#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu -#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu -#define CYREG_B0_P0_U0_CFG0 0x40010040u -#define CYREG_B0_P0_U0_CFG1 0x40010041u -#define CYREG_B0_P0_U0_CFG2 0x40010042u -#define CYREG_B0_P0_U0_CFG3 0x40010043u -#define CYREG_B0_P0_U0_CFG4 0x40010044u -#define CYREG_B0_P0_U0_CFG5 0x40010045u -#define CYREG_B0_P0_U0_CFG6 0x40010046u -#define CYREG_B0_P0_U0_CFG7 0x40010047u -#define CYREG_B0_P0_U0_CFG8 0x40010048u -#define CYREG_B0_P0_U0_CFG9 0x40010049u -#define CYREG_B0_P0_U0_CFG10 0x4001004au -#define CYREG_B0_P0_U0_CFG11 0x4001004bu -#define CYREG_B0_P0_U0_CFG12 0x4001004cu -#define CYREG_B0_P0_U0_CFG13 0x4001004du -#define CYREG_B0_P0_U0_CFG14 0x4001004eu -#define CYREG_B0_P0_U0_CFG15 0x4001004fu -#define CYREG_B0_P0_U0_CFG16 0x40010050u -#define CYREG_B0_P0_U0_CFG17 0x40010051u -#define CYREG_B0_P0_U0_CFG18 0x40010052u -#define CYREG_B0_P0_U0_CFG19 0x40010053u -#define CYREG_B0_P0_U0_CFG20 0x40010054u -#define CYREG_B0_P0_U0_CFG21 0x40010055u -#define CYREG_B0_P0_U0_CFG22 0x40010056u -#define CYREG_B0_P0_U0_CFG23 0x40010057u -#define CYREG_B0_P0_U0_CFG24 0x40010058u -#define CYREG_B0_P0_U0_CFG25 0x40010059u -#define CYREG_B0_P0_U0_CFG26 0x4001005au -#define CYREG_B0_P0_U0_CFG27 0x4001005bu -#define CYREG_B0_P0_U0_CFG28 0x4001005cu -#define CYREG_B0_P0_U0_CFG29 0x4001005du -#define CYREG_B0_P0_U0_CFG30 0x4001005eu -#define CYREG_B0_P0_U0_CFG31 0x4001005fu -#define CYREG_B0_P0_U0_DCFG0 0x40010060u -#define CYREG_B0_P0_U0_DCFG1 0x40010062u -#define CYREG_B0_P0_U0_DCFG2 0x40010064u -#define CYREG_B0_P0_U0_DCFG3 0x40010066u -#define CYREG_B0_P0_U0_DCFG4 0x40010068u -#define CYREG_B0_P0_U0_DCFG5 0x4001006au -#define CYREG_B0_P0_U0_DCFG6 0x4001006cu -#define CYREG_B0_P0_U0_DCFG7 0x4001006eu -#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u -#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u -#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u -#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u -#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u -#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu -#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u -#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u -#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u -#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu -#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u -#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u -#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u -#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu -#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u -#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u -#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u -#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u -#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u -#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau -#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu -#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu -#define CYREG_B0_P0_U1_CFG0 0x400100c0u -#define CYREG_B0_P0_U1_CFG1 0x400100c1u -#define CYREG_B0_P0_U1_CFG2 0x400100c2u -#define CYREG_B0_P0_U1_CFG3 0x400100c3u -#define CYREG_B0_P0_U1_CFG4 0x400100c4u -#define CYREG_B0_P0_U1_CFG5 0x400100c5u -#define CYREG_B0_P0_U1_CFG6 0x400100c6u -#define CYREG_B0_P0_U1_CFG7 0x400100c7u -#define CYREG_B0_P0_U1_CFG8 0x400100c8u -#define CYREG_B0_P0_U1_CFG9 0x400100c9u -#define CYREG_B0_P0_U1_CFG10 0x400100cau -#define CYREG_B0_P0_U1_CFG11 0x400100cbu -#define CYREG_B0_P0_U1_CFG12 0x400100ccu -#define CYREG_B0_P0_U1_CFG13 0x400100cdu -#define CYREG_B0_P0_U1_CFG14 0x400100ceu -#define CYREG_B0_P0_U1_CFG15 0x400100cfu -#define CYREG_B0_P0_U1_CFG16 0x400100d0u -#define CYREG_B0_P0_U1_CFG17 0x400100d1u -#define CYREG_B0_P0_U1_CFG18 0x400100d2u -#define CYREG_B0_P0_U1_CFG19 0x400100d3u -#define CYREG_B0_P0_U1_CFG20 0x400100d4u -#define CYREG_B0_P0_U1_CFG21 0x400100d5u -#define CYREG_B0_P0_U1_CFG22 0x400100d6u -#define CYREG_B0_P0_U1_CFG23 0x400100d7u -#define CYREG_B0_P0_U1_CFG24 0x400100d8u -#define CYREG_B0_P0_U1_CFG25 0x400100d9u -#define CYREG_B0_P0_U1_CFG26 0x400100dau -#define CYREG_B0_P0_U1_CFG27 0x400100dbu -#define CYREG_B0_P0_U1_CFG28 0x400100dcu -#define CYREG_B0_P0_U1_CFG29 0x400100ddu -#define CYREG_B0_P0_U1_CFG30 0x400100deu -#define CYREG_B0_P0_U1_CFG31 0x400100dfu -#define CYREG_B0_P0_U1_DCFG0 0x400100e0u -#define CYREG_B0_P0_U1_DCFG1 0x400100e2u -#define CYREG_B0_P0_U1_DCFG2 0x400100e4u -#define CYREG_B0_P0_U1_DCFG3 0x400100e6u -#define CYREG_B0_P0_U1_DCFG4 0x400100e8u -#define CYREG_B0_P0_U1_DCFG5 0x400100eau -#define CYREG_B0_P0_U1_DCFG6 0x400100ecu -#define CYREG_B0_P0_U1_DCFG7 0x400100eeu -#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u -#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P1_BASE 0x40010200u -#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u -#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u -#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u -#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u -#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u -#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu -#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u -#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u -#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u -#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu -#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u -#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u -#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u -#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu -#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u -#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u -#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u -#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u -#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u -#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au -#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu -#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu -#define CYREG_B0_P1_U0_CFG0 0x40010240u -#define CYREG_B0_P1_U0_CFG1 0x40010241u -#define CYREG_B0_P1_U0_CFG2 0x40010242u -#define CYREG_B0_P1_U0_CFG3 0x40010243u -#define CYREG_B0_P1_U0_CFG4 0x40010244u -#define CYREG_B0_P1_U0_CFG5 0x40010245u -#define CYREG_B0_P1_U0_CFG6 0x40010246u -#define CYREG_B0_P1_U0_CFG7 0x40010247u -#define CYREG_B0_P1_U0_CFG8 0x40010248u -#define CYREG_B0_P1_U0_CFG9 0x40010249u -#define CYREG_B0_P1_U0_CFG10 0x4001024au -#define CYREG_B0_P1_U0_CFG11 0x4001024bu -#define CYREG_B0_P1_U0_CFG12 0x4001024cu -#define CYREG_B0_P1_U0_CFG13 0x4001024du -#define CYREG_B0_P1_U0_CFG14 0x4001024eu -#define CYREG_B0_P1_U0_CFG15 0x4001024fu -#define CYREG_B0_P1_U0_CFG16 0x40010250u -#define CYREG_B0_P1_U0_CFG17 0x40010251u -#define CYREG_B0_P1_U0_CFG18 0x40010252u -#define CYREG_B0_P1_U0_CFG19 0x40010253u -#define CYREG_B0_P1_U0_CFG20 0x40010254u -#define CYREG_B0_P1_U0_CFG21 0x40010255u -#define CYREG_B0_P1_U0_CFG22 0x40010256u -#define CYREG_B0_P1_U0_CFG23 0x40010257u -#define CYREG_B0_P1_U0_CFG24 0x40010258u -#define CYREG_B0_P1_U0_CFG25 0x40010259u -#define CYREG_B0_P1_U0_CFG26 0x4001025au -#define CYREG_B0_P1_U0_CFG27 0x4001025bu -#define CYREG_B0_P1_U0_CFG28 0x4001025cu -#define CYREG_B0_P1_U0_CFG29 0x4001025du -#define CYREG_B0_P1_U0_CFG30 0x4001025eu -#define CYREG_B0_P1_U0_CFG31 0x4001025fu -#define CYREG_B0_P1_U0_DCFG0 0x40010260u -#define CYREG_B0_P1_U0_DCFG1 0x40010262u -#define CYREG_B0_P1_U0_DCFG2 0x40010264u -#define CYREG_B0_P1_U0_DCFG3 0x40010266u -#define CYREG_B0_P1_U0_DCFG4 0x40010268u -#define CYREG_B0_P1_U0_DCFG5 0x4001026au -#define CYREG_B0_P1_U0_DCFG6 0x4001026cu -#define CYREG_B0_P1_U0_DCFG7 0x4001026eu -#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u -#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u -#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u -#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u -#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u -#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu -#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u -#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u -#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u -#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu -#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u -#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u -#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u -#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu -#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u -#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u -#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u -#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u -#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u -#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau -#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu -#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu -#define CYREG_B0_P1_U1_CFG0 0x400102c0u -#define CYREG_B0_P1_U1_CFG1 0x400102c1u -#define CYREG_B0_P1_U1_CFG2 0x400102c2u -#define CYREG_B0_P1_U1_CFG3 0x400102c3u -#define CYREG_B0_P1_U1_CFG4 0x400102c4u -#define CYREG_B0_P1_U1_CFG5 0x400102c5u -#define CYREG_B0_P1_U1_CFG6 0x400102c6u -#define CYREG_B0_P1_U1_CFG7 0x400102c7u -#define CYREG_B0_P1_U1_CFG8 0x400102c8u -#define CYREG_B0_P1_U1_CFG9 0x400102c9u -#define CYREG_B0_P1_U1_CFG10 0x400102cau -#define CYREG_B0_P1_U1_CFG11 0x400102cbu -#define CYREG_B0_P1_U1_CFG12 0x400102ccu -#define CYREG_B0_P1_U1_CFG13 0x400102cdu -#define CYREG_B0_P1_U1_CFG14 0x400102ceu -#define CYREG_B0_P1_U1_CFG15 0x400102cfu -#define CYREG_B0_P1_U1_CFG16 0x400102d0u -#define CYREG_B0_P1_U1_CFG17 0x400102d1u -#define CYREG_B0_P1_U1_CFG18 0x400102d2u -#define CYREG_B0_P1_U1_CFG19 0x400102d3u -#define CYREG_B0_P1_U1_CFG20 0x400102d4u -#define CYREG_B0_P1_U1_CFG21 0x400102d5u -#define CYREG_B0_P1_U1_CFG22 0x400102d6u -#define CYREG_B0_P1_U1_CFG23 0x400102d7u -#define CYREG_B0_P1_U1_CFG24 0x400102d8u -#define CYREG_B0_P1_U1_CFG25 0x400102d9u -#define CYREG_B0_P1_U1_CFG26 0x400102dau -#define CYREG_B0_P1_U1_CFG27 0x400102dbu -#define CYREG_B0_P1_U1_CFG28 0x400102dcu -#define CYREG_B0_P1_U1_CFG29 0x400102ddu -#define CYREG_B0_P1_U1_CFG30 0x400102deu -#define CYREG_B0_P1_U1_CFG31 0x400102dfu -#define CYREG_B0_P1_U1_DCFG0 0x400102e0u -#define CYREG_B0_P1_U1_DCFG1 0x400102e2u -#define CYREG_B0_P1_U1_DCFG2 0x400102e4u -#define CYREG_B0_P1_U1_DCFG3 0x400102e6u -#define CYREG_B0_P1_U1_DCFG4 0x400102e8u -#define CYREG_B0_P1_U1_DCFG5 0x400102eau -#define CYREG_B0_P1_U1_DCFG6 0x400102ecu -#define CYREG_B0_P1_U1_DCFG7 0x400102eeu -#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u -#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P2_BASE 0x40010400u -#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u -#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u -#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u -#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u -#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u -#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu -#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u -#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u -#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u -#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu -#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u -#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u -#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u -#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu -#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u -#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u -#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u -#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u -#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u -#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au -#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu -#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu -#define CYREG_B0_P2_U0_CFG0 0x40010440u -#define CYREG_B0_P2_U0_CFG1 0x40010441u -#define CYREG_B0_P2_U0_CFG2 0x40010442u -#define CYREG_B0_P2_U0_CFG3 0x40010443u -#define CYREG_B0_P2_U0_CFG4 0x40010444u -#define CYREG_B0_P2_U0_CFG5 0x40010445u -#define CYREG_B0_P2_U0_CFG6 0x40010446u -#define CYREG_B0_P2_U0_CFG7 0x40010447u -#define CYREG_B0_P2_U0_CFG8 0x40010448u -#define CYREG_B0_P2_U0_CFG9 0x40010449u -#define CYREG_B0_P2_U0_CFG10 0x4001044au -#define CYREG_B0_P2_U0_CFG11 0x4001044bu -#define CYREG_B0_P2_U0_CFG12 0x4001044cu -#define CYREG_B0_P2_U0_CFG13 0x4001044du -#define CYREG_B0_P2_U0_CFG14 0x4001044eu -#define CYREG_B0_P2_U0_CFG15 0x4001044fu -#define CYREG_B0_P2_U0_CFG16 0x40010450u -#define CYREG_B0_P2_U0_CFG17 0x40010451u -#define CYREG_B0_P2_U0_CFG18 0x40010452u -#define CYREG_B0_P2_U0_CFG19 0x40010453u -#define CYREG_B0_P2_U0_CFG20 0x40010454u -#define CYREG_B0_P2_U0_CFG21 0x40010455u -#define CYREG_B0_P2_U0_CFG22 0x40010456u -#define CYREG_B0_P2_U0_CFG23 0x40010457u -#define CYREG_B0_P2_U0_CFG24 0x40010458u -#define CYREG_B0_P2_U0_CFG25 0x40010459u -#define CYREG_B0_P2_U0_CFG26 0x4001045au -#define CYREG_B0_P2_U0_CFG27 0x4001045bu -#define CYREG_B0_P2_U0_CFG28 0x4001045cu -#define CYREG_B0_P2_U0_CFG29 0x4001045du -#define CYREG_B0_P2_U0_CFG30 0x4001045eu -#define CYREG_B0_P2_U0_CFG31 0x4001045fu -#define CYREG_B0_P2_U0_DCFG0 0x40010460u -#define CYREG_B0_P2_U0_DCFG1 0x40010462u -#define CYREG_B0_P2_U0_DCFG2 0x40010464u -#define CYREG_B0_P2_U0_DCFG3 0x40010466u -#define CYREG_B0_P2_U0_DCFG4 0x40010468u -#define CYREG_B0_P2_U0_DCFG5 0x4001046au -#define CYREG_B0_P2_U0_DCFG6 0x4001046cu -#define CYREG_B0_P2_U0_DCFG7 0x4001046eu -#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u -#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u -#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u -#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u -#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u -#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu -#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u -#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u -#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u -#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu -#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u -#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u -#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u -#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu -#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u -#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u -#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u -#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u -#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u -#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau -#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu -#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu -#define CYREG_B0_P2_U1_CFG0 0x400104c0u -#define CYREG_B0_P2_U1_CFG1 0x400104c1u -#define CYREG_B0_P2_U1_CFG2 0x400104c2u -#define CYREG_B0_P2_U1_CFG3 0x400104c3u -#define CYREG_B0_P2_U1_CFG4 0x400104c4u -#define CYREG_B0_P2_U1_CFG5 0x400104c5u -#define CYREG_B0_P2_U1_CFG6 0x400104c6u -#define CYREG_B0_P2_U1_CFG7 0x400104c7u -#define CYREG_B0_P2_U1_CFG8 0x400104c8u -#define CYREG_B0_P2_U1_CFG9 0x400104c9u -#define CYREG_B0_P2_U1_CFG10 0x400104cau -#define CYREG_B0_P2_U1_CFG11 0x400104cbu -#define CYREG_B0_P2_U1_CFG12 0x400104ccu -#define CYREG_B0_P2_U1_CFG13 0x400104cdu -#define CYREG_B0_P2_U1_CFG14 0x400104ceu -#define CYREG_B0_P2_U1_CFG15 0x400104cfu -#define CYREG_B0_P2_U1_CFG16 0x400104d0u -#define CYREG_B0_P2_U1_CFG17 0x400104d1u -#define CYREG_B0_P2_U1_CFG18 0x400104d2u -#define CYREG_B0_P2_U1_CFG19 0x400104d3u -#define CYREG_B0_P2_U1_CFG20 0x400104d4u -#define CYREG_B0_P2_U1_CFG21 0x400104d5u -#define CYREG_B0_P2_U1_CFG22 0x400104d6u -#define CYREG_B0_P2_U1_CFG23 0x400104d7u -#define CYREG_B0_P2_U1_CFG24 0x400104d8u -#define CYREG_B0_P2_U1_CFG25 0x400104d9u -#define CYREG_B0_P2_U1_CFG26 0x400104dau -#define CYREG_B0_P2_U1_CFG27 0x400104dbu -#define CYREG_B0_P2_U1_CFG28 0x400104dcu -#define CYREG_B0_P2_U1_CFG29 0x400104ddu -#define CYREG_B0_P2_U1_CFG30 0x400104deu -#define CYREG_B0_P2_U1_CFG31 0x400104dfu -#define CYREG_B0_P2_U1_DCFG0 0x400104e0u -#define CYREG_B0_P2_U1_DCFG1 0x400104e2u -#define CYREG_B0_P2_U1_DCFG2 0x400104e4u -#define CYREG_B0_P2_U1_DCFG3 0x400104e6u -#define CYREG_B0_P2_U1_DCFG4 0x400104e8u -#define CYREG_B0_P2_U1_DCFG5 0x400104eau -#define CYREG_B0_P2_U1_DCFG6 0x400104ecu -#define CYREG_B0_P2_U1_DCFG7 0x400104eeu -#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u -#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P3_BASE 0x40010600u -#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u -#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u -#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u -#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u -#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u -#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu -#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u -#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u -#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u -#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu -#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u -#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u -#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u -#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu -#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u -#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u -#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u -#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u -#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u -#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au -#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu -#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu -#define CYREG_B0_P3_U0_CFG0 0x40010640u -#define CYREG_B0_P3_U0_CFG1 0x40010641u -#define CYREG_B0_P3_U0_CFG2 0x40010642u -#define CYREG_B0_P3_U0_CFG3 0x40010643u -#define CYREG_B0_P3_U0_CFG4 0x40010644u -#define CYREG_B0_P3_U0_CFG5 0x40010645u -#define CYREG_B0_P3_U0_CFG6 0x40010646u -#define CYREG_B0_P3_U0_CFG7 0x40010647u -#define CYREG_B0_P3_U0_CFG8 0x40010648u -#define CYREG_B0_P3_U0_CFG9 0x40010649u -#define CYREG_B0_P3_U0_CFG10 0x4001064au -#define CYREG_B0_P3_U0_CFG11 0x4001064bu -#define CYREG_B0_P3_U0_CFG12 0x4001064cu -#define CYREG_B0_P3_U0_CFG13 0x4001064du -#define CYREG_B0_P3_U0_CFG14 0x4001064eu -#define CYREG_B0_P3_U0_CFG15 0x4001064fu -#define CYREG_B0_P3_U0_CFG16 0x40010650u -#define CYREG_B0_P3_U0_CFG17 0x40010651u -#define CYREG_B0_P3_U0_CFG18 0x40010652u -#define CYREG_B0_P3_U0_CFG19 0x40010653u -#define CYREG_B0_P3_U0_CFG20 0x40010654u -#define CYREG_B0_P3_U0_CFG21 0x40010655u -#define CYREG_B0_P3_U0_CFG22 0x40010656u -#define CYREG_B0_P3_U0_CFG23 0x40010657u -#define CYREG_B0_P3_U0_CFG24 0x40010658u -#define CYREG_B0_P3_U0_CFG25 0x40010659u -#define CYREG_B0_P3_U0_CFG26 0x4001065au -#define CYREG_B0_P3_U0_CFG27 0x4001065bu -#define CYREG_B0_P3_U0_CFG28 0x4001065cu -#define CYREG_B0_P3_U0_CFG29 0x4001065du -#define CYREG_B0_P3_U0_CFG30 0x4001065eu -#define CYREG_B0_P3_U0_CFG31 0x4001065fu -#define CYREG_B0_P3_U0_DCFG0 0x40010660u -#define CYREG_B0_P3_U0_DCFG1 0x40010662u -#define CYREG_B0_P3_U0_DCFG2 0x40010664u -#define CYREG_B0_P3_U0_DCFG3 0x40010666u -#define CYREG_B0_P3_U0_DCFG4 0x40010668u -#define CYREG_B0_P3_U0_DCFG5 0x4001066au -#define CYREG_B0_P3_U0_DCFG6 0x4001066cu -#define CYREG_B0_P3_U0_DCFG7 0x4001066eu -#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u -#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u -#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u -#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u -#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u -#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu -#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u -#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u -#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u -#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu -#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u -#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u -#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u -#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu -#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u -#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u -#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u -#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u -#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u -#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau -#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu -#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu -#define CYREG_B0_P3_U1_CFG0 0x400106c0u -#define CYREG_B0_P3_U1_CFG1 0x400106c1u -#define CYREG_B0_P3_U1_CFG2 0x400106c2u -#define CYREG_B0_P3_U1_CFG3 0x400106c3u -#define CYREG_B0_P3_U1_CFG4 0x400106c4u -#define CYREG_B0_P3_U1_CFG5 0x400106c5u -#define CYREG_B0_P3_U1_CFG6 0x400106c6u -#define CYREG_B0_P3_U1_CFG7 0x400106c7u -#define CYREG_B0_P3_U1_CFG8 0x400106c8u -#define CYREG_B0_P3_U1_CFG9 0x400106c9u -#define CYREG_B0_P3_U1_CFG10 0x400106cau -#define CYREG_B0_P3_U1_CFG11 0x400106cbu -#define CYREG_B0_P3_U1_CFG12 0x400106ccu -#define CYREG_B0_P3_U1_CFG13 0x400106cdu -#define CYREG_B0_P3_U1_CFG14 0x400106ceu -#define CYREG_B0_P3_U1_CFG15 0x400106cfu -#define CYREG_B0_P3_U1_CFG16 0x400106d0u -#define CYREG_B0_P3_U1_CFG17 0x400106d1u -#define CYREG_B0_P3_U1_CFG18 0x400106d2u -#define CYREG_B0_P3_U1_CFG19 0x400106d3u -#define CYREG_B0_P3_U1_CFG20 0x400106d4u -#define CYREG_B0_P3_U1_CFG21 0x400106d5u -#define CYREG_B0_P3_U1_CFG22 0x400106d6u -#define CYREG_B0_P3_U1_CFG23 0x400106d7u -#define CYREG_B0_P3_U1_CFG24 0x400106d8u -#define CYREG_B0_P3_U1_CFG25 0x400106d9u -#define CYREG_B0_P3_U1_CFG26 0x400106dau -#define CYREG_B0_P3_U1_CFG27 0x400106dbu -#define CYREG_B0_P3_U1_CFG28 0x400106dcu -#define CYREG_B0_P3_U1_CFG29 0x400106ddu -#define CYREG_B0_P3_U1_CFG30 0x400106deu -#define CYREG_B0_P3_U1_CFG31 0x400106dfu -#define CYREG_B0_P3_U1_DCFG0 0x400106e0u -#define CYREG_B0_P3_U1_DCFG1 0x400106e2u -#define CYREG_B0_P3_U1_DCFG2 0x400106e4u -#define CYREG_B0_P3_U1_DCFG3 0x400106e6u -#define CYREG_B0_P3_U1_DCFG4 0x400106e8u -#define CYREG_B0_P3_U1_DCFG5 0x400106eau -#define CYREG_B0_P3_U1_DCFG6 0x400106ecu -#define CYREG_B0_P3_U1_DCFG7 0x400106eeu -#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u -#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P4_BASE 0x40010800u -#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u -#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u -#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u -#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u -#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u -#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu -#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u -#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u -#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u -#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu -#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u -#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u -#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u -#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu -#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u -#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u -#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u -#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u -#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u -#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au -#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu -#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu -#define CYREG_B0_P4_U0_CFG0 0x40010840u -#define CYREG_B0_P4_U0_CFG1 0x40010841u -#define CYREG_B0_P4_U0_CFG2 0x40010842u -#define CYREG_B0_P4_U0_CFG3 0x40010843u -#define CYREG_B0_P4_U0_CFG4 0x40010844u -#define CYREG_B0_P4_U0_CFG5 0x40010845u -#define CYREG_B0_P4_U0_CFG6 0x40010846u -#define CYREG_B0_P4_U0_CFG7 0x40010847u -#define CYREG_B0_P4_U0_CFG8 0x40010848u -#define CYREG_B0_P4_U0_CFG9 0x40010849u -#define CYREG_B0_P4_U0_CFG10 0x4001084au -#define CYREG_B0_P4_U0_CFG11 0x4001084bu -#define CYREG_B0_P4_U0_CFG12 0x4001084cu -#define CYREG_B0_P4_U0_CFG13 0x4001084du -#define CYREG_B0_P4_U0_CFG14 0x4001084eu -#define CYREG_B0_P4_U0_CFG15 0x4001084fu -#define CYREG_B0_P4_U0_CFG16 0x40010850u -#define CYREG_B0_P4_U0_CFG17 0x40010851u -#define CYREG_B0_P4_U0_CFG18 0x40010852u -#define CYREG_B0_P4_U0_CFG19 0x40010853u -#define CYREG_B0_P4_U0_CFG20 0x40010854u -#define CYREG_B0_P4_U0_CFG21 0x40010855u -#define CYREG_B0_P4_U0_CFG22 0x40010856u -#define CYREG_B0_P4_U0_CFG23 0x40010857u -#define CYREG_B0_P4_U0_CFG24 0x40010858u -#define CYREG_B0_P4_U0_CFG25 0x40010859u -#define CYREG_B0_P4_U0_CFG26 0x4001085au -#define CYREG_B0_P4_U0_CFG27 0x4001085bu -#define CYREG_B0_P4_U0_CFG28 0x4001085cu -#define CYREG_B0_P4_U0_CFG29 0x4001085du -#define CYREG_B0_P4_U0_CFG30 0x4001085eu -#define CYREG_B0_P4_U0_CFG31 0x4001085fu -#define CYREG_B0_P4_U0_DCFG0 0x40010860u -#define CYREG_B0_P4_U0_DCFG1 0x40010862u -#define CYREG_B0_P4_U0_DCFG2 0x40010864u -#define CYREG_B0_P4_U0_DCFG3 0x40010866u -#define CYREG_B0_P4_U0_DCFG4 0x40010868u -#define CYREG_B0_P4_U0_DCFG5 0x4001086au -#define CYREG_B0_P4_U0_DCFG6 0x4001086cu -#define CYREG_B0_P4_U0_DCFG7 0x4001086eu -#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u -#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u -#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u -#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u -#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u -#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu -#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u -#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u -#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u -#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu -#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u -#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u -#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u -#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu -#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u -#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u -#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u -#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u -#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u -#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau -#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu -#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu -#define CYREG_B0_P4_U1_CFG0 0x400108c0u -#define CYREG_B0_P4_U1_CFG1 0x400108c1u -#define CYREG_B0_P4_U1_CFG2 0x400108c2u -#define CYREG_B0_P4_U1_CFG3 0x400108c3u -#define CYREG_B0_P4_U1_CFG4 0x400108c4u -#define CYREG_B0_P4_U1_CFG5 0x400108c5u -#define CYREG_B0_P4_U1_CFG6 0x400108c6u -#define CYREG_B0_P4_U1_CFG7 0x400108c7u -#define CYREG_B0_P4_U1_CFG8 0x400108c8u -#define CYREG_B0_P4_U1_CFG9 0x400108c9u -#define CYREG_B0_P4_U1_CFG10 0x400108cau -#define CYREG_B0_P4_U1_CFG11 0x400108cbu -#define CYREG_B0_P4_U1_CFG12 0x400108ccu -#define CYREG_B0_P4_U1_CFG13 0x400108cdu -#define CYREG_B0_P4_U1_CFG14 0x400108ceu -#define CYREG_B0_P4_U1_CFG15 0x400108cfu -#define CYREG_B0_P4_U1_CFG16 0x400108d0u -#define CYREG_B0_P4_U1_CFG17 0x400108d1u -#define CYREG_B0_P4_U1_CFG18 0x400108d2u -#define CYREG_B0_P4_U1_CFG19 0x400108d3u -#define CYREG_B0_P4_U1_CFG20 0x400108d4u -#define CYREG_B0_P4_U1_CFG21 0x400108d5u -#define CYREG_B0_P4_U1_CFG22 0x400108d6u -#define CYREG_B0_P4_U1_CFG23 0x400108d7u -#define CYREG_B0_P4_U1_CFG24 0x400108d8u -#define CYREG_B0_P4_U1_CFG25 0x400108d9u -#define CYREG_B0_P4_U1_CFG26 0x400108dau -#define CYREG_B0_P4_U1_CFG27 0x400108dbu -#define CYREG_B0_P4_U1_CFG28 0x400108dcu -#define CYREG_B0_P4_U1_CFG29 0x400108ddu -#define CYREG_B0_P4_U1_CFG30 0x400108deu -#define CYREG_B0_P4_U1_CFG31 0x400108dfu -#define CYREG_B0_P4_U1_DCFG0 0x400108e0u -#define CYREG_B0_P4_U1_DCFG1 0x400108e2u -#define CYREG_B0_P4_U1_DCFG2 0x400108e4u -#define CYREG_B0_P4_U1_DCFG3 0x400108e6u -#define CYREG_B0_P4_U1_DCFG4 0x400108e8u -#define CYREG_B0_P4_U1_DCFG5 0x400108eau -#define CYREG_B0_P4_U1_DCFG6 0x400108ecu -#define CYREG_B0_P4_U1_DCFG7 0x400108eeu -#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u -#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u -#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u -#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u -#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u -#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u -#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u -#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu -#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u -#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u -#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u -#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu -#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u -#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u -#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u -#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu -#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u -#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u -#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u -#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u -#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u -#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au -#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu -#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu -#define CYREG_B0_P5_U0_CFG0 0x40010a40u -#define CYREG_B0_P5_U0_CFG1 0x40010a41u -#define CYREG_B0_P5_U0_CFG2 0x40010a42u -#define CYREG_B0_P5_U0_CFG3 0x40010a43u -#define CYREG_B0_P5_U0_CFG4 0x40010a44u -#define CYREG_B0_P5_U0_CFG5 0x40010a45u -#define CYREG_B0_P5_U0_CFG6 0x40010a46u -#define CYREG_B0_P5_U0_CFG7 0x40010a47u -#define CYREG_B0_P5_U0_CFG8 0x40010a48u -#define CYREG_B0_P5_U0_CFG9 0x40010a49u -#define CYREG_B0_P5_U0_CFG10 0x40010a4au -#define CYREG_B0_P5_U0_CFG11 0x40010a4bu -#define CYREG_B0_P5_U0_CFG12 0x40010a4cu -#define CYREG_B0_P5_U0_CFG13 0x40010a4du -#define CYREG_B0_P5_U0_CFG14 0x40010a4eu -#define CYREG_B0_P5_U0_CFG15 0x40010a4fu -#define CYREG_B0_P5_U0_CFG16 0x40010a50u -#define CYREG_B0_P5_U0_CFG17 0x40010a51u -#define CYREG_B0_P5_U0_CFG18 0x40010a52u -#define CYREG_B0_P5_U0_CFG19 0x40010a53u -#define CYREG_B0_P5_U0_CFG20 0x40010a54u -#define CYREG_B0_P5_U0_CFG21 0x40010a55u -#define CYREG_B0_P5_U0_CFG22 0x40010a56u -#define CYREG_B0_P5_U0_CFG23 0x40010a57u -#define CYREG_B0_P5_U0_CFG24 0x40010a58u -#define CYREG_B0_P5_U0_CFG25 0x40010a59u -#define CYREG_B0_P5_U0_CFG26 0x40010a5au -#define CYREG_B0_P5_U0_CFG27 0x40010a5bu -#define CYREG_B0_P5_U0_CFG28 0x40010a5cu -#define CYREG_B0_P5_U0_CFG29 0x40010a5du -#define CYREG_B0_P5_U0_CFG30 0x40010a5eu -#define CYREG_B0_P5_U0_CFG31 0x40010a5fu -#define CYREG_B0_P5_U0_DCFG0 0x40010a60u -#define CYREG_B0_P5_U0_DCFG1 0x40010a62u -#define CYREG_B0_P5_U0_DCFG2 0x40010a64u -#define CYREG_B0_P5_U0_DCFG3 0x40010a66u -#define CYREG_B0_P5_U0_DCFG4 0x40010a68u -#define CYREG_B0_P5_U0_DCFG5 0x40010a6au -#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu -#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu -#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u -#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u -#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u -#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u -#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u -#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu -#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u -#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u -#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u -#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu -#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u -#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u -#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u -#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu -#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u -#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u -#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u -#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u -#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u -#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau -#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu -#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu -#define CYREG_B0_P5_U1_CFG0 0x40010ac0u -#define CYREG_B0_P5_U1_CFG1 0x40010ac1u -#define CYREG_B0_P5_U1_CFG2 0x40010ac2u -#define CYREG_B0_P5_U1_CFG3 0x40010ac3u -#define CYREG_B0_P5_U1_CFG4 0x40010ac4u -#define CYREG_B0_P5_U1_CFG5 0x40010ac5u -#define CYREG_B0_P5_U1_CFG6 0x40010ac6u -#define CYREG_B0_P5_U1_CFG7 0x40010ac7u -#define CYREG_B0_P5_U1_CFG8 0x40010ac8u -#define CYREG_B0_P5_U1_CFG9 0x40010ac9u -#define CYREG_B0_P5_U1_CFG10 0x40010acau -#define CYREG_B0_P5_U1_CFG11 0x40010acbu -#define CYREG_B0_P5_U1_CFG12 0x40010accu -#define CYREG_B0_P5_U1_CFG13 0x40010acdu -#define CYREG_B0_P5_U1_CFG14 0x40010aceu -#define CYREG_B0_P5_U1_CFG15 0x40010acfu -#define CYREG_B0_P5_U1_CFG16 0x40010ad0u -#define CYREG_B0_P5_U1_CFG17 0x40010ad1u -#define CYREG_B0_P5_U1_CFG18 0x40010ad2u -#define CYREG_B0_P5_U1_CFG19 0x40010ad3u -#define CYREG_B0_P5_U1_CFG20 0x40010ad4u -#define CYREG_B0_P5_U1_CFG21 0x40010ad5u -#define CYREG_B0_P5_U1_CFG22 0x40010ad6u -#define CYREG_B0_P5_U1_CFG23 0x40010ad7u -#define CYREG_B0_P5_U1_CFG24 0x40010ad8u -#define CYREG_B0_P5_U1_CFG25 0x40010ad9u -#define CYREG_B0_P5_U1_CFG26 0x40010adau -#define CYREG_B0_P5_U1_CFG27 0x40010adbu -#define CYREG_B0_P5_U1_CFG28 0x40010adcu -#define CYREG_B0_P5_U1_CFG29 0x40010addu -#define CYREG_B0_P5_U1_CFG30 0x40010adeu -#define CYREG_B0_P5_U1_CFG31 0x40010adfu -#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u -#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u -#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u -#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u -#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u -#define CYREG_B0_P5_U1_DCFG5 0x40010aeau -#define CYREG_B0_P5_U1_DCFG6 0x40010aecu -#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu -#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u -#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u -#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u -#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u -#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u -#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u -#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u -#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu -#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u -#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u -#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u -#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu -#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u -#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u -#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u -#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu -#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u -#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u -#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u -#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u -#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u -#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au -#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu -#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu -#define CYREG_B0_P6_U0_CFG0 0x40010c40u -#define CYREG_B0_P6_U0_CFG1 0x40010c41u -#define CYREG_B0_P6_U0_CFG2 0x40010c42u -#define CYREG_B0_P6_U0_CFG3 0x40010c43u -#define CYREG_B0_P6_U0_CFG4 0x40010c44u -#define CYREG_B0_P6_U0_CFG5 0x40010c45u -#define CYREG_B0_P6_U0_CFG6 0x40010c46u -#define CYREG_B0_P6_U0_CFG7 0x40010c47u -#define CYREG_B0_P6_U0_CFG8 0x40010c48u -#define CYREG_B0_P6_U0_CFG9 0x40010c49u -#define CYREG_B0_P6_U0_CFG10 0x40010c4au -#define CYREG_B0_P6_U0_CFG11 0x40010c4bu -#define CYREG_B0_P6_U0_CFG12 0x40010c4cu -#define CYREG_B0_P6_U0_CFG13 0x40010c4du -#define CYREG_B0_P6_U0_CFG14 0x40010c4eu -#define CYREG_B0_P6_U0_CFG15 0x40010c4fu -#define CYREG_B0_P6_U0_CFG16 0x40010c50u -#define CYREG_B0_P6_U0_CFG17 0x40010c51u -#define CYREG_B0_P6_U0_CFG18 0x40010c52u -#define CYREG_B0_P6_U0_CFG19 0x40010c53u -#define CYREG_B0_P6_U0_CFG20 0x40010c54u -#define CYREG_B0_P6_U0_CFG21 0x40010c55u -#define CYREG_B0_P6_U0_CFG22 0x40010c56u -#define CYREG_B0_P6_U0_CFG23 0x40010c57u -#define CYREG_B0_P6_U0_CFG24 0x40010c58u -#define CYREG_B0_P6_U0_CFG25 0x40010c59u -#define CYREG_B0_P6_U0_CFG26 0x40010c5au -#define CYREG_B0_P6_U0_CFG27 0x40010c5bu -#define CYREG_B0_P6_U0_CFG28 0x40010c5cu -#define CYREG_B0_P6_U0_CFG29 0x40010c5du -#define CYREG_B0_P6_U0_CFG30 0x40010c5eu -#define CYREG_B0_P6_U0_CFG31 0x40010c5fu -#define CYREG_B0_P6_U0_DCFG0 0x40010c60u -#define CYREG_B0_P6_U0_DCFG1 0x40010c62u -#define CYREG_B0_P6_U0_DCFG2 0x40010c64u -#define CYREG_B0_P6_U0_DCFG3 0x40010c66u -#define CYREG_B0_P6_U0_DCFG4 0x40010c68u -#define CYREG_B0_P6_U0_DCFG5 0x40010c6au -#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu -#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu -#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u -#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u -#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u -#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u -#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u -#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu -#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u -#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u -#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u -#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu -#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u -#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u -#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u -#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu -#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u -#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u -#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u -#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u -#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u -#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau -#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu -#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu -#define CYREG_B0_P6_U1_CFG0 0x40010cc0u -#define CYREG_B0_P6_U1_CFG1 0x40010cc1u -#define CYREG_B0_P6_U1_CFG2 0x40010cc2u -#define CYREG_B0_P6_U1_CFG3 0x40010cc3u -#define CYREG_B0_P6_U1_CFG4 0x40010cc4u -#define CYREG_B0_P6_U1_CFG5 0x40010cc5u -#define CYREG_B0_P6_U1_CFG6 0x40010cc6u -#define CYREG_B0_P6_U1_CFG7 0x40010cc7u -#define CYREG_B0_P6_U1_CFG8 0x40010cc8u -#define CYREG_B0_P6_U1_CFG9 0x40010cc9u -#define CYREG_B0_P6_U1_CFG10 0x40010ccau -#define CYREG_B0_P6_U1_CFG11 0x40010ccbu -#define CYREG_B0_P6_U1_CFG12 0x40010cccu -#define CYREG_B0_P6_U1_CFG13 0x40010ccdu -#define CYREG_B0_P6_U1_CFG14 0x40010cceu -#define CYREG_B0_P6_U1_CFG15 0x40010ccfu -#define CYREG_B0_P6_U1_CFG16 0x40010cd0u -#define CYREG_B0_P6_U1_CFG17 0x40010cd1u -#define CYREG_B0_P6_U1_CFG18 0x40010cd2u -#define CYREG_B0_P6_U1_CFG19 0x40010cd3u -#define CYREG_B0_P6_U1_CFG20 0x40010cd4u -#define CYREG_B0_P6_U1_CFG21 0x40010cd5u -#define CYREG_B0_P6_U1_CFG22 0x40010cd6u -#define CYREG_B0_P6_U1_CFG23 0x40010cd7u -#define CYREG_B0_P6_U1_CFG24 0x40010cd8u -#define CYREG_B0_P6_U1_CFG25 0x40010cd9u -#define CYREG_B0_P6_U1_CFG26 0x40010cdau -#define CYREG_B0_P6_U1_CFG27 0x40010cdbu -#define CYREG_B0_P6_U1_CFG28 0x40010cdcu -#define CYREG_B0_P6_U1_CFG29 0x40010cddu -#define CYREG_B0_P6_U1_CFG30 0x40010cdeu -#define CYREG_B0_P6_U1_CFG31 0x40010cdfu -#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u -#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u -#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u -#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u -#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u -#define CYREG_B0_P6_U1_DCFG5 0x40010ceau -#define CYREG_B0_P6_U1_DCFG6 0x40010cecu -#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu -#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u -#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u -#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu -#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u -#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u -#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u -#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u -#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u -#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu -#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u -#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u -#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u -#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu -#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u -#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u -#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u -#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu -#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u -#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u -#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u -#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u -#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u -#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au -#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu -#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu -#define CYREG_B0_P7_U0_CFG0 0x40010e40u -#define CYREG_B0_P7_U0_CFG1 0x40010e41u -#define CYREG_B0_P7_U0_CFG2 0x40010e42u -#define CYREG_B0_P7_U0_CFG3 0x40010e43u -#define CYREG_B0_P7_U0_CFG4 0x40010e44u -#define CYREG_B0_P7_U0_CFG5 0x40010e45u -#define CYREG_B0_P7_U0_CFG6 0x40010e46u -#define CYREG_B0_P7_U0_CFG7 0x40010e47u -#define CYREG_B0_P7_U0_CFG8 0x40010e48u -#define CYREG_B0_P7_U0_CFG9 0x40010e49u -#define CYREG_B0_P7_U0_CFG10 0x40010e4au -#define CYREG_B0_P7_U0_CFG11 0x40010e4bu -#define CYREG_B0_P7_U0_CFG12 0x40010e4cu -#define CYREG_B0_P7_U0_CFG13 0x40010e4du -#define CYREG_B0_P7_U0_CFG14 0x40010e4eu -#define CYREG_B0_P7_U0_CFG15 0x40010e4fu -#define CYREG_B0_P7_U0_CFG16 0x40010e50u -#define CYREG_B0_P7_U0_CFG17 0x40010e51u -#define CYREG_B0_P7_U0_CFG18 0x40010e52u -#define CYREG_B0_P7_U0_CFG19 0x40010e53u -#define CYREG_B0_P7_U0_CFG20 0x40010e54u -#define CYREG_B0_P7_U0_CFG21 0x40010e55u -#define CYREG_B0_P7_U0_CFG22 0x40010e56u -#define CYREG_B0_P7_U0_CFG23 0x40010e57u -#define CYREG_B0_P7_U0_CFG24 0x40010e58u -#define CYREG_B0_P7_U0_CFG25 0x40010e59u -#define CYREG_B0_P7_U0_CFG26 0x40010e5au -#define CYREG_B0_P7_U0_CFG27 0x40010e5bu -#define CYREG_B0_P7_U0_CFG28 0x40010e5cu -#define CYREG_B0_P7_U0_CFG29 0x40010e5du -#define CYREG_B0_P7_U0_CFG30 0x40010e5eu -#define CYREG_B0_P7_U0_CFG31 0x40010e5fu -#define CYREG_B0_P7_U0_DCFG0 0x40010e60u -#define CYREG_B0_P7_U0_DCFG1 0x40010e62u -#define CYREG_B0_P7_U0_DCFG2 0x40010e64u -#define CYREG_B0_P7_U0_DCFG3 0x40010e66u -#define CYREG_B0_P7_U0_DCFG4 0x40010e68u -#define CYREG_B0_P7_U0_DCFG5 0x40010e6au -#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu -#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu -#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u -#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u -#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u -#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u -#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u -#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu -#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u -#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u -#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u -#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu -#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u -#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u -#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u -#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu -#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u -#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u -#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u -#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u -#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u -#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau -#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu -#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu -#define CYREG_B0_P7_U1_CFG0 0x40010ec0u -#define CYREG_B0_P7_U1_CFG1 0x40010ec1u -#define CYREG_B0_P7_U1_CFG2 0x40010ec2u -#define CYREG_B0_P7_U1_CFG3 0x40010ec3u -#define CYREG_B0_P7_U1_CFG4 0x40010ec4u -#define CYREG_B0_P7_U1_CFG5 0x40010ec5u -#define CYREG_B0_P7_U1_CFG6 0x40010ec6u -#define CYREG_B0_P7_U1_CFG7 0x40010ec7u -#define CYREG_B0_P7_U1_CFG8 0x40010ec8u -#define CYREG_B0_P7_U1_CFG9 0x40010ec9u -#define CYREG_B0_P7_U1_CFG10 0x40010ecau -#define CYREG_B0_P7_U1_CFG11 0x40010ecbu -#define CYREG_B0_P7_U1_CFG12 0x40010eccu -#define CYREG_B0_P7_U1_CFG13 0x40010ecdu -#define CYREG_B0_P7_U1_CFG14 0x40010eceu -#define CYREG_B0_P7_U1_CFG15 0x40010ecfu -#define CYREG_B0_P7_U1_CFG16 0x40010ed0u -#define CYREG_B0_P7_U1_CFG17 0x40010ed1u -#define CYREG_B0_P7_U1_CFG18 0x40010ed2u -#define CYREG_B0_P7_U1_CFG19 0x40010ed3u -#define CYREG_B0_P7_U1_CFG20 0x40010ed4u -#define CYREG_B0_P7_U1_CFG21 0x40010ed5u -#define CYREG_B0_P7_U1_CFG22 0x40010ed6u -#define CYREG_B0_P7_U1_CFG23 0x40010ed7u -#define CYREG_B0_P7_U1_CFG24 0x40010ed8u -#define CYREG_B0_P7_U1_CFG25 0x40010ed9u -#define CYREG_B0_P7_U1_CFG26 0x40010edau -#define CYREG_B0_P7_U1_CFG27 0x40010edbu -#define CYREG_B0_P7_U1_CFG28 0x40010edcu -#define CYREG_B0_P7_U1_CFG29 0x40010eddu -#define CYREG_B0_P7_U1_CFG30 0x40010edeu -#define CYREG_B0_P7_U1_CFG31 0x40010edfu -#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u -#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u -#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u -#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u -#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u -#define CYREG_B0_P7_U1_DCFG5 0x40010eeau -#define CYREG_B0_P7_U1_DCFG6 0x40010eecu -#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu -#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u -#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_BASE 0x40011000u -#define CYDEV_UCFG_B1_SIZE 0x00000fefu -#define CYDEV_UCFG_B1_P2_BASE 0x40011400u -#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u -#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u -#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u -#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u -#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u -#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu -#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u -#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u -#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u -#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu -#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u -#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u -#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u -#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu -#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u -#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u -#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u -#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u -#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u -#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au -#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu -#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu -#define CYREG_B1_P2_U0_CFG0 0x40011440u -#define CYREG_B1_P2_U0_CFG1 0x40011441u -#define CYREG_B1_P2_U0_CFG2 0x40011442u -#define CYREG_B1_P2_U0_CFG3 0x40011443u -#define CYREG_B1_P2_U0_CFG4 0x40011444u -#define CYREG_B1_P2_U0_CFG5 0x40011445u -#define CYREG_B1_P2_U0_CFG6 0x40011446u -#define CYREG_B1_P2_U0_CFG7 0x40011447u -#define CYREG_B1_P2_U0_CFG8 0x40011448u -#define CYREG_B1_P2_U0_CFG9 0x40011449u -#define CYREG_B1_P2_U0_CFG10 0x4001144au -#define CYREG_B1_P2_U0_CFG11 0x4001144bu -#define CYREG_B1_P2_U0_CFG12 0x4001144cu -#define CYREG_B1_P2_U0_CFG13 0x4001144du -#define CYREG_B1_P2_U0_CFG14 0x4001144eu -#define CYREG_B1_P2_U0_CFG15 0x4001144fu -#define CYREG_B1_P2_U0_CFG16 0x40011450u -#define CYREG_B1_P2_U0_CFG17 0x40011451u -#define CYREG_B1_P2_U0_CFG18 0x40011452u -#define CYREG_B1_P2_U0_CFG19 0x40011453u -#define CYREG_B1_P2_U0_CFG20 0x40011454u -#define CYREG_B1_P2_U0_CFG21 0x40011455u -#define CYREG_B1_P2_U0_CFG22 0x40011456u -#define CYREG_B1_P2_U0_CFG23 0x40011457u -#define CYREG_B1_P2_U0_CFG24 0x40011458u -#define CYREG_B1_P2_U0_CFG25 0x40011459u -#define CYREG_B1_P2_U0_CFG26 0x4001145au -#define CYREG_B1_P2_U0_CFG27 0x4001145bu -#define CYREG_B1_P2_U0_CFG28 0x4001145cu -#define CYREG_B1_P2_U0_CFG29 0x4001145du -#define CYREG_B1_P2_U0_CFG30 0x4001145eu -#define CYREG_B1_P2_U0_CFG31 0x4001145fu -#define CYREG_B1_P2_U0_DCFG0 0x40011460u -#define CYREG_B1_P2_U0_DCFG1 0x40011462u -#define CYREG_B1_P2_U0_DCFG2 0x40011464u -#define CYREG_B1_P2_U0_DCFG3 0x40011466u -#define CYREG_B1_P2_U0_DCFG4 0x40011468u -#define CYREG_B1_P2_U0_DCFG5 0x4001146au -#define CYREG_B1_P2_U0_DCFG6 0x4001146cu -#define CYREG_B1_P2_U0_DCFG7 0x4001146eu -#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u -#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u -#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u -#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u -#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u -#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu -#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u -#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u -#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u -#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu -#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u -#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u -#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u -#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu -#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u -#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u -#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u -#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u -#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u -#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau -#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu -#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu -#define CYREG_B1_P2_U1_CFG0 0x400114c0u -#define CYREG_B1_P2_U1_CFG1 0x400114c1u -#define CYREG_B1_P2_U1_CFG2 0x400114c2u -#define CYREG_B1_P2_U1_CFG3 0x400114c3u -#define CYREG_B1_P2_U1_CFG4 0x400114c4u -#define CYREG_B1_P2_U1_CFG5 0x400114c5u -#define CYREG_B1_P2_U1_CFG6 0x400114c6u -#define CYREG_B1_P2_U1_CFG7 0x400114c7u -#define CYREG_B1_P2_U1_CFG8 0x400114c8u -#define CYREG_B1_P2_U1_CFG9 0x400114c9u -#define CYREG_B1_P2_U1_CFG10 0x400114cau -#define CYREG_B1_P2_U1_CFG11 0x400114cbu -#define CYREG_B1_P2_U1_CFG12 0x400114ccu -#define CYREG_B1_P2_U1_CFG13 0x400114cdu -#define CYREG_B1_P2_U1_CFG14 0x400114ceu -#define CYREG_B1_P2_U1_CFG15 0x400114cfu -#define CYREG_B1_P2_U1_CFG16 0x400114d0u -#define CYREG_B1_P2_U1_CFG17 0x400114d1u -#define CYREG_B1_P2_U1_CFG18 0x400114d2u -#define CYREG_B1_P2_U1_CFG19 0x400114d3u -#define CYREG_B1_P2_U1_CFG20 0x400114d4u -#define CYREG_B1_P2_U1_CFG21 0x400114d5u -#define CYREG_B1_P2_U1_CFG22 0x400114d6u -#define CYREG_B1_P2_U1_CFG23 0x400114d7u -#define CYREG_B1_P2_U1_CFG24 0x400114d8u -#define CYREG_B1_P2_U1_CFG25 0x400114d9u -#define CYREG_B1_P2_U1_CFG26 0x400114dau -#define CYREG_B1_P2_U1_CFG27 0x400114dbu -#define CYREG_B1_P2_U1_CFG28 0x400114dcu -#define CYREG_B1_P2_U1_CFG29 0x400114ddu -#define CYREG_B1_P2_U1_CFG30 0x400114deu -#define CYREG_B1_P2_U1_CFG31 0x400114dfu -#define CYREG_B1_P2_U1_DCFG0 0x400114e0u -#define CYREG_B1_P2_U1_DCFG1 0x400114e2u -#define CYREG_B1_P2_U1_DCFG2 0x400114e4u -#define CYREG_B1_P2_U1_DCFG3 0x400114e6u -#define CYREG_B1_P2_U1_DCFG4 0x400114e8u -#define CYREG_B1_P2_U1_DCFG5 0x400114eau -#define CYREG_B1_P2_U1_DCFG6 0x400114ecu -#define CYREG_B1_P2_U1_DCFG7 0x400114eeu -#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u -#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_P3_BASE 0x40011600u -#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u -#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u -#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u -#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u -#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u -#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu -#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u -#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u -#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u -#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu -#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u -#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u -#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u -#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu -#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u -#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u -#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u -#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u -#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u -#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au -#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu -#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu -#define CYREG_B1_P3_U0_CFG0 0x40011640u -#define CYREG_B1_P3_U0_CFG1 0x40011641u -#define CYREG_B1_P3_U0_CFG2 0x40011642u -#define CYREG_B1_P3_U0_CFG3 0x40011643u -#define CYREG_B1_P3_U0_CFG4 0x40011644u -#define CYREG_B1_P3_U0_CFG5 0x40011645u -#define CYREG_B1_P3_U0_CFG6 0x40011646u -#define CYREG_B1_P3_U0_CFG7 0x40011647u -#define CYREG_B1_P3_U0_CFG8 0x40011648u -#define CYREG_B1_P3_U0_CFG9 0x40011649u -#define CYREG_B1_P3_U0_CFG10 0x4001164au -#define CYREG_B1_P3_U0_CFG11 0x4001164bu -#define CYREG_B1_P3_U0_CFG12 0x4001164cu -#define CYREG_B1_P3_U0_CFG13 0x4001164du -#define CYREG_B1_P3_U0_CFG14 0x4001164eu -#define CYREG_B1_P3_U0_CFG15 0x4001164fu -#define CYREG_B1_P3_U0_CFG16 0x40011650u -#define CYREG_B1_P3_U0_CFG17 0x40011651u -#define CYREG_B1_P3_U0_CFG18 0x40011652u -#define CYREG_B1_P3_U0_CFG19 0x40011653u -#define CYREG_B1_P3_U0_CFG20 0x40011654u -#define CYREG_B1_P3_U0_CFG21 0x40011655u -#define CYREG_B1_P3_U0_CFG22 0x40011656u -#define CYREG_B1_P3_U0_CFG23 0x40011657u -#define CYREG_B1_P3_U0_CFG24 0x40011658u -#define CYREG_B1_P3_U0_CFG25 0x40011659u -#define CYREG_B1_P3_U0_CFG26 0x4001165au -#define CYREG_B1_P3_U0_CFG27 0x4001165bu -#define CYREG_B1_P3_U0_CFG28 0x4001165cu -#define CYREG_B1_P3_U0_CFG29 0x4001165du -#define CYREG_B1_P3_U0_CFG30 0x4001165eu -#define CYREG_B1_P3_U0_CFG31 0x4001165fu -#define CYREG_B1_P3_U0_DCFG0 0x40011660u -#define CYREG_B1_P3_U0_DCFG1 0x40011662u -#define CYREG_B1_P3_U0_DCFG2 0x40011664u -#define CYREG_B1_P3_U0_DCFG3 0x40011666u -#define CYREG_B1_P3_U0_DCFG4 0x40011668u -#define CYREG_B1_P3_U0_DCFG5 0x4001166au -#define CYREG_B1_P3_U0_DCFG6 0x4001166cu -#define CYREG_B1_P3_U0_DCFG7 0x4001166eu -#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u -#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u -#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u -#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u -#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u -#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu -#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u -#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u -#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u -#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu -#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u -#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u -#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u -#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu -#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u -#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u -#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u -#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u -#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u -#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau -#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu -#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu -#define CYREG_B1_P3_U1_CFG0 0x400116c0u -#define CYREG_B1_P3_U1_CFG1 0x400116c1u -#define CYREG_B1_P3_U1_CFG2 0x400116c2u -#define CYREG_B1_P3_U1_CFG3 0x400116c3u -#define CYREG_B1_P3_U1_CFG4 0x400116c4u -#define CYREG_B1_P3_U1_CFG5 0x400116c5u -#define CYREG_B1_P3_U1_CFG6 0x400116c6u -#define CYREG_B1_P3_U1_CFG7 0x400116c7u -#define CYREG_B1_P3_U1_CFG8 0x400116c8u -#define CYREG_B1_P3_U1_CFG9 0x400116c9u -#define CYREG_B1_P3_U1_CFG10 0x400116cau -#define CYREG_B1_P3_U1_CFG11 0x400116cbu -#define CYREG_B1_P3_U1_CFG12 0x400116ccu -#define CYREG_B1_P3_U1_CFG13 0x400116cdu -#define CYREG_B1_P3_U1_CFG14 0x400116ceu -#define CYREG_B1_P3_U1_CFG15 0x400116cfu -#define CYREG_B1_P3_U1_CFG16 0x400116d0u -#define CYREG_B1_P3_U1_CFG17 0x400116d1u -#define CYREG_B1_P3_U1_CFG18 0x400116d2u -#define CYREG_B1_P3_U1_CFG19 0x400116d3u -#define CYREG_B1_P3_U1_CFG20 0x400116d4u -#define CYREG_B1_P3_U1_CFG21 0x400116d5u -#define CYREG_B1_P3_U1_CFG22 0x400116d6u -#define CYREG_B1_P3_U1_CFG23 0x400116d7u -#define CYREG_B1_P3_U1_CFG24 0x400116d8u -#define CYREG_B1_P3_U1_CFG25 0x400116d9u -#define CYREG_B1_P3_U1_CFG26 0x400116dau -#define CYREG_B1_P3_U1_CFG27 0x400116dbu -#define CYREG_B1_P3_U1_CFG28 0x400116dcu -#define CYREG_B1_P3_U1_CFG29 0x400116ddu -#define CYREG_B1_P3_U1_CFG30 0x400116deu -#define CYREG_B1_P3_U1_CFG31 0x400116dfu -#define CYREG_B1_P3_U1_DCFG0 0x400116e0u -#define CYREG_B1_P3_U1_DCFG1 0x400116e2u -#define CYREG_B1_P3_U1_DCFG2 0x400116e4u -#define CYREG_B1_P3_U1_DCFG3 0x400116e6u -#define CYREG_B1_P3_U1_DCFG4 0x400116e8u -#define CYREG_B1_P3_U1_DCFG5 0x400116eau -#define CYREG_B1_P3_U1_DCFG6 0x400116ecu -#define CYREG_B1_P3_U1_DCFG7 0x400116eeu -#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u -#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_P4_BASE 0x40011800u -#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u -#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u -#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u -#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u -#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u -#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu -#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u -#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u -#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u -#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu -#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u -#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u -#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u -#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu -#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u -#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u -#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u -#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u -#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u -#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au -#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu -#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu -#define CYREG_B1_P4_U0_CFG0 0x40011840u -#define CYREG_B1_P4_U0_CFG1 0x40011841u -#define CYREG_B1_P4_U0_CFG2 0x40011842u -#define CYREG_B1_P4_U0_CFG3 0x40011843u -#define CYREG_B1_P4_U0_CFG4 0x40011844u -#define CYREG_B1_P4_U0_CFG5 0x40011845u -#define CYREG_B1_P4_U0_CFG6 0x40011846u -#define CYREG_B1_P4_U0_CFG7 0x40011847u -#define CYREG_B1_P4_U0_CFG8 0x40011848u -#define CYREG_B1_P4_U0_CFG9 0x40011849u -#define CYREG_B1_P4_U0_CFG10 0x4001184au -#define CYREG_B1_P4_U0_CFG11 0x4001184bu -#define CYREG_B1_P4_U0_CFG12 0x4001184cu -#define CYREG_B1_P4_U0_CFG13 0x4001184du -#define CYREG_B1_P4_U0_CFG14 0x4001184eu -#define CYREG_B1_P4_U0_CFG15 0x4001184fu -#define CYREG_B1_P4_U0_CFG16 0x40011850u -#define CYREG_B1_P4_U0_CFG17 0x40011851u -#define CYREG_B1_P4_U0_CFG18 0x40011852u -#define CYREG_B1_P4_U0_CFG19 0x40011853u -#define CYREG_B1_P4_U0_CFG20 0x40011854u -#define CYREG_B1_P4_U0_CFG21 0x40011855u -#define CYREG_B1_P4_U0_CFG22 0x40011856u -#define CYREG_B1_P4_U0_CFG23 0x40011857u -#define CYREG_B1_P4_U0_CFG24 0x40011858u -#define CYREG_B1_P4_U0_CFG25 0x40011859u -#define CYREG_B1_P4_U0_CFG26 0x4001185au -#define CYREG_B1_P4_U0_CFG27 0x4001185bu -#define CYREG_B1_P4_U0_CFG28 0x4001185cu -#define CYREG_B1_P4_U0_CFG29 0x4001185du -#define CYREG_B1_P4_U0_CFG30 0x4001185eu -#define CYREG_B1_P4_U0_CFG31 0x4001185fu -#define CYREG_B1_P4_U0_DCFG0 0x40011860u -#define CYREG_B1_P4_U0_DCFG1 0x40011862u -#define CYREG_B1_P4_U0_DCFG2 0x40011864u -#define CYREG_B1_P4_U0_DCFG3 0x40011866u -#define CYREG_B1_P4_U0_DCFG4 0x40011868u -#define CYREG_B1_P4_U0_DCFG5 0x4001186au -#define CYREG_B1_P4_U0_DCFG6 0x4001186cu -#define CYREG_B1_P4_U0_DCFG7 0x4001186eu -#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u -#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u -#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u -#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u -#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u -#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu -#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u -#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u -#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u -#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu -#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u -#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u -#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u -#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu -#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u -#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u -#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u -#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u -#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u -#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau -#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu -#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu -#define CYREG_B1_P4_U1_CFG0 0x400118c0u -#define CYREG_B1_P4_U1_CFG1 0x400118c1u -#define CYREG_B1_P4_U1_CFG2 0x400118c2u -#define CYREG_B1_P4_U1_CFG3 0x400118c3u -#define CYREG_B1_P4_U1_CFG4 0x400118c4u -#define CYREG_B1_P4_U1_CFG5 0x400118c5u -#define CYREG_B1_P4_U1_CFG6 0x400118c6u -#define CYREG_B1_P4_U1_CFG7 0x400118c7u -#define CYREG_B1_P4_U1_CFG8 0x400118c8u -#define CYREG_B1_P4_U1_CFG9 0x400118c9u -#define CYREG_B1_P4_U1_CFG10 0x400118cau -#define CYREG_B1_P4_U1_CFG11 0x400118cbu -#define CYREG_B1_P4_U1_CFG12 0x400118ccu -#define CYREG_B1_P4_U1_CFG13 0x400118cdu -#define CYREG_B1_P4_U1_CFG14 0x400118ceu -#define CYREG_B1_P4_U1_CFG15 0x400118cfu -#define CYREG_B1_P4_U1_CFG16 0x400118d0u -#define CYREG_B1_P4_U1_CFG17 0x400118d1u -#define CYREG_B1_P4_U1_CFG18 0x400118d2u -#define CYREG_B1_P4_U1_CFG19 0x400118d3u -#define CYREG_B1_P4_U1_CFG20 0x400118d4u -#define CYREG_B1_P4_U1_CFG21 0x400118d5u -#define CYREG_B1_P4_U1_CFG22 0x400118d6u -#define CYREG_B1_P4_U1_CFG23 0x400118d7u -#define CYREG_B1_P4_U1_CFG24 0x400118d8u -#define CYREG_B1_P4_U1_CFG25 0x400118d9u -#define CYREG_B1_P4_U1_CFG26 0x400118dau -#define CYREG_B1_P4_U1_CFG27 0x400118dbu -#define CYREG_B1_P4_U1_CFG28 0x400118dcu -#define CYREG_B1_P4_U1_CFG29 0x400118ddu -#define CYREG_B1_P4_U1_CFG30 0x400118deu -#define CYREG_B1_P4_U1_CFG31 0x400118dfu -#define CYREG_B1_P4_U1_DCFG0 0x400118e0u -#define CYREG_B1_P4_U1_DCFG1 0x400118e2u -#define CYREG_B1_P4_U1_DCFG2 0x400118e4u -#define CYREG_B1_P4_U1_DCFG3 0x400118e6u -#define CYREG_B1_P4_U1_DCFG4 0x400118e8u -#define CYREG_B1_P4_U1_DCFG5 0x400118eau -#define CYREG_B1_P4_U1_DCFG6 0x400118ecu -#define CYREG_B1_P4_U1_DCFG7 0x400118eeu -#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u -#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u -#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu -#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u -#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u -#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u -#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u -#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u -#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu -#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u -#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u -#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u -#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu -#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u -#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u -#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u -#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu -#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u -#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u -#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u -#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u -#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u -#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au -#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu -#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu -#define CYREG_B1_P5_U0_CFG0 0x40011a40u -#define CYREG_B1_P5_U0_CFG1 0x40011a41u -#define CYREG_B1_P5_U0_CFG2 0x40011a42u -#define CYREG_B1_P5_U0_CFG3 0x40011a43u -#define CYREG_B1_P5_U0_CFG4 0x40011a44u -#define CYREG_B1_P5_U0_CFG5 0x40011a45u -#define CYREG_B1_P5_U0_CFG6 0x40011a46u -#define CYREG_B1_P5_U0_CFG7 0x40011a47u -#define CYREG_B1_P5_U0_CFG8 0x40011a48u -#define CYREG_B1_P5_U0_CFG9 0x40011a49u -#define CYREG_B1_P5_U0_CFG10 0x40011a4au -#define CYREG_B1_P5_U0_CFG11 0x40011a4bu -#define CYREG_B1_P5_U0_CFG12 0x40011a4cu -#define CYREG_B1_P5_U0_CFG13 0x40011a4du -#define CYREG_B1_P5_U0_CFG14 0x40011a4eu -#define CYREG_B1_P5_U0_CFG15 0x40011a4fu -#define CYREG_B1_P5_U0_CFG16 0x40011a50u -#define CYREG_B1_P5_U0_CFG17 0x40011a51u -#define CYREG_B1_P5_U0_CFG18 0x40011a52u -#define CYREG_B1_P5_U0_CFG19 0x40011a53u -#define CYREG_B1_P5_U0_CFG20 0x40011a54u -#define CYREG_B1_P5_U0_CFG21 0x40011a55u -#define CYREG_B1_P5_U0_CFG22 0x40011a56u -#define CYREG_B1_P5_U0_CFG23 0x40011a57u -#define CYREG_B1_P5_U0_CFG24 0x40011a58u -#define CYREG_B1_P5_U0_CFG25 0x40011a59u -#define CYREG_B1_P5_U0_CFG26 0x40011a5au -#define CYREG_B1_P5_U0_CFG27 0x40011a5bu -#define CYREG_B1_P5_U0_CFG28 0x40011a5cu -#define CYREG_B1_P5_U0_CFG29 0x40011a5du -#define CYREG_B1_P5_U0_CFG30 0x40011a5eu -#define CYREG_B1_P5_U0_CFG31 0x40011a5fu -#define CYREG_B1_P5_U0_DCFG0 0x40011a60u -#define CYREG_B1_P5_U0_DCFG1 0x40011a62u -#define CYREG_B1_P5_U0_DCFG2 0x40011a64u -#define CYREG_B1_P5_U0_DCFG3 0x40011a66u -#define CYREG_B1_P5_U0_DCFG4 0x40011a68u -#define CYREG_B1_P5_U0_DCFG5 0x40011a6au -#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu -#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu -#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u -#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u -#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u -#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u -#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u -#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu -#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u -#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u -#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u -#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu -#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u -#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u -#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u -#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu -#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u -#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u -#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u -#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u -#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u -#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau -#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu -#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu -#define CYREG_B1_P5_U1_CFG0 0x40011ac0u -#define CYREG_B1_P5_U1_CFG1 0x40011ac1u -#define CYREG_B1_P5_U1_CFG2 0x40011ac2u -#define CYREG_B1_P5_U1_CFG3 0x40011ac3u -#define CYREG_B1_P5_U1_CFG4 0x40011ac4u -#define CYREG_B1_P5_U1_CFG5 0x40011ac5u -#define CYREG_B1_P5_U1_CFG6 0x40011ac6u -#define CYREG_B1_P5_U1_CFG7 0x40011ac7u -#define CYREG_B1_P5_U1_CFG8 0x40011ac8u -#define CYREG_B1_P5_U1_CFG9 0x40011ac9u -#define CYREG_B1_P5_U1_CFG10 0x40011acau -#define CYREG_B1_P5_U1_CFG11 0x40011acbu -#define CYREG_B1_P5_U1_CFG12 0x40011accu -#define CYREG_B1_P5_U1_CFG13 0x40011acdu -#define CYREG_B1_P5_U1_CFG14 0x40011aceu -#define CYREG_B1_P5_U1_CFG15 0x40011acfu -#define CYREG_B1_P5_U1_CFG16 0x40011ad0u -#define CYREG_B1_P5_U1_CFG17 0x40011ad1u -#define CYREG_B1_P5_U1_CFG18 0x40011ad2u -#define CYREG_B1_P5_U1_CFG19 0x40011ad3u -#define CYREG_B1_P5_U1_CFG20 0x40011ad4u -#define CYREG_B1_P5_U1_CFG21 0x40011ad5u -#define CYREG_B1_P5_U1_CFG22 0x40011ad6u -#define CYREG_B1_P5_U1_CFG23 0x40011ad7u -#define CYREG_B1_P5_U1_CFG24 0x40011ad8u -#define CYREG_B1_P5_U1_CFG25 0x40011ad9u -#define CYREG_B1_P5_U1_CFG26 0x40011adau -#define CYREG_B1_P5_U1_CFG27 0x40011adbu -#define CYREG_B1_P5_U1_CFG28 0x40011adcu -#define CYREG_B1_P5_U1_CFG29 0x40011addu -#define CYREG_B1_P5_U1_CFG30 0x40011adeu -#define CYREG_B1_P5_U1_CFG31 0x40011adfu -#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u -#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u -#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u -#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u -#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u -#define CYREG_B1_P5_U1_DCFG5 0x40011aeau -#define CYREG_B1_P5_U1_DCFG6 0x40011aecu -#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu -#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u -#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu -#define CYDEV_UCFG_DSI0_BASE 0x40014000u -#define CYDEV_UCFG_DSI0_SIZE 0x000000efu -#define CYDEV_UCFG_DSI1_BASE 0x40014100u -#define CYDEV_UCFG_DSI1_SIZE 0x000000efu -#define CYDEV_UCFG_DSI2_BASE 0x40014200u -#define CYDEV_UCFG_DSI2_SIZE 0x000000efu -#define CYDEV_UCFG_DSI3_BASE 0x40014300u -#define CYDEV_UCFG_DSI3_SIZE 0x000000efu -#define CYDEV_UCFG_DSI4_BASE 0x40014400u -#define CYDEV_UCFG_DSI4_SIZE 0x000000efu -#define CYDEV_UCFG_DSI5_BASE 0x40014500u -#define CYDEV_UCFG_DSI5_SIZE 0x000000efu -#define CYDEV_UCFG_DSI6_BASE 0x40014600u -#define CYDEV_UCFG_DSI6_SIZE 0x000000efu -#define CYDEV_UCFG_DSI7_BASE 0x40014700u -#define CYDEV_UCFG_DSI7_SIZE 0x000000efu -#define CYDEV_UCFG_DSI8_BASE 0x40014800u -#define CYDEV_UCFG_DSI8_SIZE 0x000000efu -#define CYDEV_UCFG_DSI9_BASE 0x40014900u -#define CYDEV_UCFG_DSI9_SIZE 0x000000efu -#define CYDEV_UCFG_DSI12_BASE 0x40014c00u -#define CYDEV_UCFG_DSI12_SIZE 0x000000efu -#define CYDEV_UCFG_DSI13_BASE 0x40014d00u -#define CYDEV_UCFG_DSI13_SIZE 0x000000efu -#define CYDEV_UCFG_BCTL0_BASE 0x40015000u -#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u -#define CYREG_BCTL0_MDCLK_EN 0x40015000u -#define CYREG_BCTL0_MBCLK_EN 0x40015001u -#define CYREG_BCTL0_WAIT_CFG 0x40015002u -#define CYREG_BCTL0_BANK_CTL 0x40015003u -#define CYREG_BCTL0_UDB_TEST_3 0x40015007u -#define CYREG_BCTL0_DCLK_EN0 0x40015008u -#define CYREG_BCTL0_BCLK_EN0 0x40015009u -#define CYREG_BCTL0_DCLK_EN1 0x4001500au -#define CYREG_BCTL0_BCLK_EN1 0x4001500bu -#define CYREG_BCTL0_DCLK_EN2 0x4001500cu -#define CYREG_BCTL0_BCLK_EN2 0x4001500du -#define CYREG_BCTL0_DCLK_EN3 0x4001500eu -#define CYREG_BCTL0_BCLK_EN3 0x4001500fu -#define CYDEV_UCFG_BCTL1_BASE 0x40015010u -#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u -#define CYREG_BCTL1_MDCLK_EN 0x40015010u -#define CYREG_BCTL1_MBCLK_EN 0x40015011u -#define CYREG_BCTL1_WAIT_CFG 0x40015012u -#define CYREG_BCTL1_BANK_CTL 0x40015013u -#define CYREG_BCTL1_UDB_TEST_3 0x40015017u -#define CYREG_BCTL1_DCLK_EN0 0x40015018u -#define CYREG_BCTL1_BCLK_EN0 0x40015019u -#define CYREG_BCTL1_DCLK_EN1 0x4001501au -#define CYREG_BCTL1_BCLK_EN1 0x4001501bu -#define CYREG_BCTL1_DCLK_EN2 0x4001501cu -#define CYREG_BCTL1_BCLK_EN2 0x4001501du -#define CYREG_BCTL1_DCLK_EN3 0x4001501eu -#define CYREG_BCTL1_BCLK_EN3 0x4001501fu -#define CYDEV_IDMUX_BASE 0x40015100u -#define CYDEV_IDMUX_SIZE 0x00000016u -#define CYREG_IDMUX_IRQ_CTL0 0x40015100u -#define CYREG_IDMUX_IRQ_CTL1 0x40015101u -#define CYREG_IDMUX_IRQ_CTL2 0x40015102u -#define CYREG_IDMUX_IRQ_CTL3 0x40015103u -#define CYREG_IDMUX_IRQ_CTL4 0x40015104u -#define CYREG_IDMUX_IRQ_CTL5 0x40015105u -#define CYREG_IDMUX_IRQ_CTL6 0x40015106u -#define CYREG_IDMUX_IRQ_CTL7 0x40015107u -#define CYREG_IDMUX_DRQ_CTL0 0x40015110u -#define CYREG_IDMUX_DRQ_CTL1 0x40015111u -#define CYREG_IDMUX_DRQ_CTL2 0x40015112u -#define CYREG_IDMUX_DRQ_CTL3 0x40015113u -#define CYREG_IDMUX_DRQ_CTL4 0x40015114u -#define CYREG_IDMUX_DRQ_CTL5 0x40015115u -#define CYDEV_CACHERAM_BASE 0x40030000u -#define CYDEV_CACHERAM_SIZE 0x00000400u -#define CYREG_CACHERAM_DATA_MBASE 0x40030000u -#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u -#define CYDEV_SFR_BASE 0x40050100u -#define CYDEV_SFR_SIZE 0x000000fbu -#define CYREG_SFR_GPIO0 0x40050180u -#define CYREG_SFR_GPIRD0 0x40050189u -#define CYREG_SFR_GPIO0_SEL 0x4005018au -#define CYREG_SFR_GPIO1 0x40050190u -#define CYREG_SFR_GPIRD1 0x40050191u -#define CYREG_SFR_GPIO2 0x40050198u -#define CYREG_SFR_GPIRD2 0x40050199u -#define CYREG_SFR_GPIO2_SEL 0x4005019au -#define CYREG_SFR_GPIO1_SEL 0x400501a2u -#define CYREG_SFR_GPIO3 0x400501b0u -#define CYREG_SFR_GPIRD3 0x400501b1u -#define CYREG_SFR_GPIO3_SEL 0x400501b2u -#define CYREG_SFR_GPIO4 0x400501c0u -#define CYREG_SFR_GPIRD4 0x400501c1u -#define CYREG_SFR_GPIO4_SEL 0x400501c2u -#define CYREG_SFR_GPIO5 0x400501c8u -#define CYREG_SFR_GPIRD5 0x400501c9u -#define CYREG_SFR_GPIO5_SEL 0x400501cau -#define CYREG_SFR_GPIO6 0x400501d8u -#define CYREG_SFR_GPIRD6 0x400501d9u -#define CYREG_SFR_GPIO6_SEL 0x400501dau -#define CYREG_SFR_GPIO12 0x400501e8u -#define CYREG_SFR_GPIRD12 0x400501e9u -#define CYREG_SFR_GPIO12_SEL 0x400501f2u -#define CYREG_SFR_GPIO15 0x400501f8u -#define CYREG_SFR_GPIRD15 0x400501f9u -#define CYREG_SFR_GPIO15_SEL 0x400501fau -#define CYDEV_P3BA_BASE 0x40050300u -#define CYDEV_P3BA_SIZE 0x0000002bu -#define CYREG_P3BA_Y_START 0x40050300u -#define CYREG_P3BA_YROLL 0x40050301u -#define CYREG_P3BA_YCFG 0x40050302u -#define CYREG_P3BA_X_START1 0x40050303u -#define CYREG_P3BA_X_START2 0x40050304u -#define CYREG_P3BA_XROLL1 0x40050305u -#define CYREG_P3BA_XROLL2 0x40050306u -#define CYREG_P3BA_XINC 0x40050307u -#define CYREG_P3BA_XCFG 0x40050308u -#define CYREG_P3BA_OFFSETADDR1 0x40050309u -#define CYREG_P3BA_OFFSETADDR2 0x4005030au -#define CYREG_P3BA_OFFSETADDR3 0x4005030bu -#define CYREG_P3BA_ABSADDR1 0x4005030cu -#define CYREG_P3BA_ABSADDR2 0x4005030du -#define CYREG_P3BA_ABSADDR3 0x4005030eu -#define CYREG_P3BA_ABSADDR4 0x4005030fu -#define CYREG_P3BA_DATCFG1 0x40050310u -#define CYREG_P3BA_DATCFG2 0x40050311u -#define CYREG_P3BA_CMP_RSLT1 0x40050314u -#define CYREG_P3BA_CMP_RSLT2 0x40050315u -#define CYREG_P3BA_CMP_RSLT3 0x40050316u -#define CYREG_P3BA_CMP_RSLT4 0x40050317u -#define CYREG_P3BA_DATA_REG1 0x40050318u -#define CYREG_P3BA_DATA_REG2 0x40050319u -#define CYREG_P3BA_DATA_REG3 0x4005031au -#define CYREG_P3BA_DATA_REG4 0x4005031bu -#define CYREG_P3BA_EXP_DATA1 0x4005031cu -#define CYREG_P3BA_EXP_DATA2 0x4005031du -#define CYREG_P3BA_EXP_DATA3 0x4005031eu -#define CYREG_P3BA_EXP_DATA4 0x4005031fu -#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u -#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u -#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u -#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u -#define CYREG_P3BA_BIST_EN 0x40050324u -#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u -#define CYREG_P3BA_SEQCFG1 0x40050326u -#define CYREG_P3BA_SEQCFG2 0x40050327u -#define CYREG_P3BA_Y_CURR 0x40050328u -#define CYREG_P3BA_X_CURR1 0x40050329u -#define CYREG_P3BA_X_CURR2 0x4005032au -#define CYDEV_PANTHER_BASE 0x40080000u -#define CYDEV_PANTHER_SIZE 0x00000020u -#define CYREG_PANTHER_STCALIB_CFG 0x40080000u -#define CYREG_PANTHER_WAITPIPE 0x40080004u -#define CYREG_PANTHER_TRACE_CFG 0x40080008u -#define CYREG_PANTHER_DBG_CFG 0x4008000cu -#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u -#define CYREG_PANTHER_DEVICE_ID 0x4008001cu -#define CYDEV_FLSECC_BASE 0x48000000u -#define CYDEV_FLSECC_SIZE 0x00008000u -#define CYREG_FLSECC_DATA_MBASE 0x48000000u -#define CYREG_FLSECC_DATA_MSIZE 0x00008000u -#define CYDEV_FLSHID_BASE 0x49000000u -#define CYDEV_FLSHID_SIZE 0x00000200u -#define CYREG_FLSHID_RSVD_MBASE 0x49000000u -#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u -#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u -#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u -#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u -#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u -#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u -#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u -#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u -#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u -#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u -#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u -#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u -#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u -#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u -#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u -#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au -#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu -#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu -#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du -#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu -#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu -#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u -#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u -#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u -#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u -#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u -#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u -#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u -#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u -#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u -#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u -#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au -#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu -#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu -#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du -#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu -#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu -#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u -#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u -#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u -#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u -#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u -#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u -#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u -#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u -#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u -#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u -#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au -#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu -#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu -#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du -#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu -#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu -#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u -#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u -#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u -#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u -#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u -#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u -#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u -#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u -#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u -#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u -#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au -#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu -#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu -#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du -#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu -#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu -#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u -#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u -#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u -#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu -#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu -#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u -#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u -#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u -#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u -#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u -#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau -#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu -#define CYDEV_EXTMEM_BASE 0x60000000u -#define CYDEV_EXTMEM_SIZE 0x00800000u -#define CYREG_EXTMEM_DATA_MBASE 0x60000000u -#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u -#define CYDEV_ITM_BASE 0xe0000000u -#define CYDEV_ITM_SIZE 0x00001000u -#define CYREG_ITM_TRACE_EN 0xe0000e00u -#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u -#define CYREG_ITM_TRACE_CTRL 0xe0000e80u -#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u -#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u -#define CYREG_ITM_PID4 0xe0000fd0u -#define CYREG_ITM_PID5 0xe0000fd4u -#define CYREG_ITM_PID6 0xe0000fd8u -#define CYREG_ITM_PID7 0xe0000fdcu -#define CYREG_ITM_PID0 0xe0000fe0u -#define CYREG_ITM_PID1 0xe0000fe4u -#define CYREG_ITM_PID2 0xe0000fe8u -#define CYREG_ITM_PID3 0xe0000fecu -#define CYREG_ITM_CID0 0xe0000ff0u -#define CYREG_ITM_CID1 0xe0000ff4u -#define CYREG_ITM_CID2 0xe0000ff8u -#define CYREG_ITM_CID3 0xe0000ffcu -#define CYDEV_DWT_BASE 0xe0001000u -#define CYDEV_DWT_SIZE 0x0000005cu -#define CYREG_DWT_CTRL 0xe0001000u -#define CYREG_DWT_CYCLE_COUNT 0xe0001004u -#define CYREG_DWT_CPI_COUNT 0xe0001008u -#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu -#define CYREG_DWT_SLEEP_COUNT 0xe0001010u -#define CYREG_DWT_LSU_COUNT 0xe0001014u -#define CYREG_DWT_FOLD_COUNT 0xe0001018u -#define CYREG_DWT_PC_SAMPLE 0xe000101cu -#define CYREG_DWT_COMP_0 0xe0001020u -#define CYREG_DWT_MASK_0 0xe0001024u -#define CYREG_DWT_FUNCTION_0 0xe0001028u -#define CYREG_DWT_COMP_1 0xe0001030u -#define CYREG_DWT_MASK_1 0xe0001034u -#define CYREG_DWT_FUNCTION_1 0xe0001038u -#define CYREG_DWT_COMP_2 0xe0001040u -#define CYREG_DWT_MASK_2 0xe0001044u -#define CYREG_DWT_FUNCTION_2 0xe0001048u -#define CYREG_DWT_COMP_3 0xe0001050u -#define CYREG_DWT_MASK_3 0xe0001054u -#define CYREG_DWT_FUNCTION_3 0xe0001058u -#define CYDEV_FPB_BASE 0xe0002000u -#define CYDEV_FPB_SIZE 0x00001000u -#define CYREG_FPB_CTRL 0xe0002000u -#define CYREG_FPB_REMAP 0xe0002004u -#define CYREG_FPB_FP_COMP_0 0xe0002008u -#define CYREG_FPB_FP_COMP_1 0xe000200cu -#define CYREG_FPB_FP_COMP_2 0xe0002010u -#define CYREG_FPB_FP_COMP_3 0xe0002014u -#define CYREG_FPB_FP_COMP_4 0xe0002018u -#define CYREG_FPB_FP_COMP_5 0xe000201cu -#define CYREG_FPB_FP_COMP_6 0xe0002020u -#define CYREG_FPB_FP_COMP_7 0xe0002024u -#define CYREG_FPB_PID4 0xe0002fd0u -#define CYREG_FPB_PID5 0xe0002fd4u -#define CYREG_FPB_PID6 0xe0002fd8u -#define CYREG_FPB_PID7 0xe0002fdcu -#define CYREG_FPB_PID0 0xe0002fe0u -#define CYREG_FPB_PID1 0xe0002fe4u -#define CYREG_FPB_PID2 0xe0002fe8u -#define CYREG_FPB_PID3 0xe0002fecu -#define CYREG_FPB_CID0 0xe0002ff0u -#define CYREG_FPB_CID1 0xe0002ff4u -#define CYREG_FPB_CID2 0xe0002ff8u -#define CYREG_FPB_CID3 0xe0002ffcu -#define CYDEV_NVIC_BASE 0xe000e000u -#define CYDEV_NVIC_SIZE 0x00000d3cu -#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u -#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u -#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u -#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u -#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu -#define CYREG_NVIC_SETENA0 0xe000e100u -#define CYREG_NVIC_CLRENA0 0xe000e180u -#define CYREG_NVIC_SETPEND0 0xe000e200u -#define CYREG_NVIC_CLRPEND0 0xe000e280u -#define CYREG_NVIC_ACTIVE0 0xe000e300u -#define CYREG_NVIC_PRI_0 0xe000e400u -#define CYREG_NVIC_PRI_1 0xe000e401u -#define CYREG_NVIC_PRI_2 0xe000e402u -#define CYREG_NVIC_PRI_3 0xe000e403u -#define CYREG_NVIC_PRI_4 0xe000e404u -#define CYREG_NVIC_PRI_5 0xe000e405u -#define CYREG_NVIC_PRI_6 0xe000e406u -#define CYREG_NVIC_PRI_7 0xe000e407u -#define CYREG_NVIC_PRI_8 0xe000e408u -#define CYREG_NVIC_PRI_9 0xe000e409u -#define CYREG_NVIC_PRI_10 0xe000e40au -#define CYREG_NVIC_PRI_11 0xe000e40bu -#define CYREG_NVIC_PRI_12 0xe000e40cu -#define CYREG_NVIC_PRI_13 0xe000e40du -#define CYREG_NVIC_PRI_14 0xe000e40eu -#define CYREG_NVIC_PRI_15 0xe000e40fu -#define CYREG_NVIC_PRI_16 0xe000e410u -#define CYREG_NVIC_PRI_17 0xe000e411u -#define CYREG_NVIC_PRI_18 0xe000e412u -#define CYREG_NVIC_PRI_19 0xe000e413u -#define CYREG_NVIC_PRI_20 0xe000e414u -#define CYREG_NVIC_PRI_21 0xe000e415u -#define CYREG_NVIC_PRI_22 0xe000e416u -#define CYREG_NVIC_PRI_23 0xe000e417u -#define CYREG_NVIC_PRI_24 0xe000e418u -#define CYREG_NVIC_PRI_25 0xe000e419u -#define CYREG_NVIC_PRI_26 0xe000e41au -#define CYREG_NVIC_PRI_27 0xe000e41bu -#define CYREG_NVIC_PRI_28 0xe000e41cu -#define CYREG_NVIC_PRI_29 0xe000e41du -#define CYREG_NVIC_PRI_30 0xe000e41eu -#define CYREG_NVIC_PRI_31 0xe000e41fu -#define CYREG_NVIC_CPUID_BASE 0xe000ed00u -#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u -#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u -#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu -#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u -#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u -#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u -#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu -#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u -#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u -#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u -#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u -#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au -#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu -#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u -#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u -#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u -#define CYDEV_CORE_DBG_BASE 0xe000edf0u -#define CYDEV_CORE_DBG_SIZE 0x00000010u -#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u -#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u -#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u -#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu -#define CYDEV_TPIU_BASE 0xe0040000u -#define CYDEV_TPIU_SIZE 0x00001000u -#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u -#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u -#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u -#define CYREG_TPIU_PROTOCOL 0xe00400f0u -#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u -#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u -#define CYREG_TPIU_TRIGGER 0xe0040ee8u -#define CYREG_TPIU_ITETMDATA 0xe0040eecu -#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u -#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u -#define CYREG_TPIU_ITITMDATA 0xe0040efcu -#define CYREG_TPIU_ITCTRL 0xe0040f00u -#define CYREG_TPIU_DEVID 0xe0040fc8u -#define CYREG_TPIU_DEVTYPE 0xe0040fccu -#define CYREG_TPIU_PID4 0xe0040fd0u -#define CYREG_TPIU_PID5 0xe0040fd4u -#define CYREG_TPIU_PID6 0xe0040fd8u -#define CYREG_TPIU_PID7 0xe0040fdcu -#define CYREG_TPIU_PID0 0xe0040fe0u -#define CYREG_TPIU_PID1 0xe0040fe4u -#define CYREG_TPIU_PID2 0xe0040fe8u -#define CYREG_TPIU_PID3 0xe0040fecu -#define CYREG_TPIU_CID0 0xe0040ff0u -#define CYREG_TPIU_CID1 0xe0040ff4u -#define CYREG_TPIU_CID2 0xe0040ff8u -#define CYREG_TPIU_CID3 0xe0040ffcu -#define CYDEV_ETM_BASE 0xe0041000u -#define CYDEV_ETM_SIZE 0x00001000u -#define CYREG_ETM_CTL 0xe0041000u -#define CYREG_ETM_CFG_CODE 0xe0041004u -#define CYREG_ETM_TRIG_EVENT 0xe0041008u -#define CYREG_ETM_STATUS 0xe0041010u -#define CYREG_ETM_SYS_CFG 0xe0041014u -#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u -#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u -#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu -#define CYREG_ETM_SYNC_FREQ 0xe00411e0u -#define CYREG_ETM_ETM_ID 0xe00411e4u -#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u -#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u -#define CYREG_ETM_CS_TRACE_ID 0xe0041200u -#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u -#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u -#define CYREG_ETM_PDSR 0xe0041314u -#define CYREG_ETM_ITMISCIN 0xe0041ee0u -#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u -#define CYREG_ETM_ITATBCTR2 0xe0041ef0u -#define CYREG_ETM_ITATBCTR0 0xe0041ef8u -#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u -#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u -#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u -#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u -#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u -#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u -#define CYREG_ETM_DEV_TYPE 0xe0041fccu -#define CYREG_ETM_PID4 0xe0041fd0u -#define CYREG_ETM_PID5 0xe0041fd4u -#define CYREG_ETM_PID6 0xe0041fd8u -#define CYREG_ETM_PID7 0xe0041fdcu -#define CYREG_ETM_PID0 0xe0041fe0u -#define CYREG_ETM_PID1 0xe0041fe4u -#define CYREG_ETM_PID2 0xe0041fe8u -#define CYREG_ETM_PID3 0xe0041fecu -#define CYREG_ETM_CID0 0xe0041ff0u -#define CYREG_ETM_CID1 0xe0041ff4u -#define CYREG_ETM_CID2 0xe0041ff8u -#define CYREG_ETM_CID3 0xe0041ffcu -#define CYDEV_ROM_TABLE_BASE 0xe00ff000u -#define CYDEV_ROM_TABLE_SIZE 0x00001000u -#define CYREG_ROM_TABLE_NVIC 0xe00ff000u -#define CYREG_ROM_TABLE_DWT 0xe00ff004u -#define CYREG_ROM_TABLE_FPB 0xe00ff008u -#define CYREG_ROM_TABLE_ITM 0xe00ff00cu -#define CYREG_ROM_TABLE_TPIU 0xe00ff010u -#define CYREG_ROM_TABLE_ETM 0xe00ff014u -#define CYREG_ROM_TABLE_END 0xe00ff018u -#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu -#define CYREG_ROM_TABLE_PID4 0xe00fffd0u -#define CYREG_ROM_TABLE_PID5 0xe00fffd4u -#define CYREG_ROM_TABLE_PID6 0xe00fffd8u -#define CYREG_ROM_TABLE_PID7 0xe00fffdcu -#define CYREG_ROM_TABLE_PID0 0xe00fffe0u -#define CYREG_ROM_TABLE_PID1 0xe00fffe4u -#define CYREG_ROM_TABLE_PID2 0xe00fffe8u -#define CYREG_ROM_TABLE_PID3 0xe00fffecu -#define CYREG_ROM_TABLE_CID0 0xe00ffff0u -#define CYREG_ROM_TABLE_CID1 0xe00ffff4u -#define CYREG_ROM_TABLE_CID2 0xe00ffff8u -#define CYREG_ROM_TABLE_CID3 0xe00ffffcu -#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE -#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE -#define CYDEV_FLS_SECTOR_SIZE 0x00010000u -#define CYDEV_FLS_ROW_SIZE 0x00000100u -#define CYDEV_ECC_SECTOR_SIZE 0x00002000u -#define CYDEV_ECC_ROW_SIZE 0x00000020u -#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u -#define CYDEV_EEPROM_ROW_SIZE 0x00000010u -#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE -#define CYCLK_LD_DISABLE 0x00000004u -#define CYCLK_LD_SYNC_EN 0x00000002u -#define CYCLK_LD_LOAD 0x00000001u -#define CYCLK_PIPE 0x00000080u -#define CYCLK_SSS 0x00000040u -#define CYCLK_EARLY 0x00000020u -#define CYCLK_DUTY 0x00000010u -#define CYCLK_SYNC 0x00000008u -#define CYCLK_SRC_SEL_CLK_SYNC_D 0 -#define CYCLK_SRC_SEL_SYNC_DIG 0 -#define CYCLK_SRC_SEL_IMO 1 -#define CYCLK_SRC_SEL_XTAL_MHZ 2 -#define CYCLK_SRC_SEL_XTALM 2 -#define CYCLK_SRC_SEL_ILO 3 -#define CYCLK_SRC_SEL_PLL 4 -#define CYCLK_SRC_SEL_XTAL_KHZ 5 -#define CYCLK_SRC_SEL_XTALK 5 -#define CYCLK_SRC_SEL_DSI_G 6 -#define CYCLK_SRC_SEL_DSI_D 7 -#define CYCLK_SRC_SEL_CLK_SYNC_A 0 -#define CYCLK_SRC_SEL_DSI_A 7 -#endif /* CYDEVICE_TRM_H */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc deleted file mode 100755 index 1776ef9..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu.inc +++ /dev/null @@ -1,5357 +0,0 @@ -/******************************************************************************* -* FILENAME: cydevicegnu.inc -* OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.0 Component Pack 7 -* -* DESCRIPTION: -* This file provides all of the address values for the entire PSoC device. -* This file is automatically generated by PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -.set CYDEV_FLASH_BASE, 0x00000000 -.set CYDEV_FLASH_SIZE, 0x00020000 -.set CYDEV_FLASH_DATA_MBASE, 0x00000000 -.set CYDEV_FLASH_DATA_MSIZE, 0x00020000 -.set CYDEV_SRAM_BASE, 0x1fffc000 -.set CYDEV_SRAM_SIZE, 0x00008000 -.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000 -.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000 -.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000 -.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000 -.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000 -.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000 -.set CYDEV_SRAM_CODE_MBASE, 0x1fffc000 -.set CYDEV_SRAM_CODE_MSIZE, 0x00004000 -.set CYDEV_SRAM_DATA_MBASE, 0x20000000 -.set CYDEV_SRAM_DATA_MSIZE, 0x00004000 -.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000 -.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000 -.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000 -.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000 -.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000 -.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000 -.set CYDEV_DMA_BASE, 0x20008000 -.set CYDEV_DMA_SIZE, 0x00008000 -.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000 -.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000 -.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000 -.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000 -.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000 -.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000 -.set CYDEV_DMA_SRAM_MBASE, 0x2000f000 -.set CYDEV_DMA_SRAM_MSIZE, 0x00001000 -.set CYDEV_CLKDIST_BASE, 0x40004000 -.set CYDEV_CLKDIST_SIZE, 0x00000110 -.set CYDEV_CLKDIST_CR, 0x40004000 -.set CYDEV_CLKDIST_LD, 0x40004001 -.set CYDEV_CLKDIST_WRK0, 0x40004002 -.set CYDEV_CLKDIST_WRK1, 0x40004003 -.set CYDEV_CLKDIST_MSTR0, 0x40004004 -.set CYDEV_CLKDIST_MSTR1, 0x40004005 -.set CYDEV_CLKDIST_BCFG0, 0x40004006 -.set CYDEV_CLKDIST_BCFG1, 0x40004007 -.set CYDEV_CLKDIST_BCFG2, 0x40004008 -.set CYDEV_CLKDIST_UCFG, 0x40004009 -.set CYDEV_CLKDIST_DLY0, 0x4000400a -.set CYDEV_CLKDIST_DLY1, 0x4000400b -.set CYDEV_CLKDIST_DMASK, 0x40004010 -.set CYDEV_CLKDIST_AMASK, 0x40004014 -.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 -.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080 -.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081 -.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082 -.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 -.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084 -.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085 -.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086 -.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 -.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088 -.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089 -.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a -.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c -.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c -.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d -.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e -.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 -.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090 -.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091 -.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092 -.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 -.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094 -.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095 -.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096 -.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 -.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098 -.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099 -.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a -.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c -.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 -.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c -.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d -.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e -.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 -.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 -.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100 -.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101 -.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102 -.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103 -.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 -.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 -.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104 -.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105 -.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106 -.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107 -.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 -.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 -.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108 -.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109 -.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a -.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b -.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c -.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 -.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c -.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d -.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e -.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f -.set CYDEV_FASTCLK_BASE, 0x40004200 -.set CYDEV_FASTCLK_SIZE, 0x00000026 -.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 -.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 -.set CYDEV_FASTCLK_IMO_CR, 0x40004200 -.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 -.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 -.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210 -.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212 -.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213 -.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 -.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 -.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220 -.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221 -.set CYDEV_FASTCLK_PLL_P, 0x40004222 -.set CYDEV_FASTCLK_PLL_Q, 0x40004223 -.set CYDEV_FASTCLK_PLL_SR, 0x40004225 -.set CYDEV_SLOWCLK_BASE, 0x40004300 -.set CYDEV_SLOWCLK_SIZE, 0x0000000b -.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 -.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 -.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300 -.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301 -.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 -.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 -.set CYDEV_SLOWCLK_X32_CR, 0x40004308 -.set CYDEV_SLOWCLK_X32_CFG, 0x40004309 -.set CYDEV_SLOWCLK_X32_TST, 0x4000430a -.set CYDEV_BOOST_BASE, 0x40004320 -.set CYDEV_BOOST_SIZE, 0x00000007 -.set CYDEV_BOOST_CR0, 0x40004320 -.set CYDEV_BOOST_CR1, 0x40004321 -.set CYDEV_BOOST_CR2, 0x40004322 -.set CYDEV_BOOST_CR3, 0x40004323 -.set CYDEV_BOOST_SR, 0x40004324 -.set CYDEV_BOOST_CR4, 0x40004325 -.set CYDEV_BOOST_SR2, 0x40004326 -.set CYDEV_PWRSYS_BASE, 0x40004330 -.set CYDEV_PWRSYS_SIZE, 0x00000002 -.set CYDEV_PWRSYS_CR0, 0x40004330 -.set CYDEV_PWRSYS_CR1, 0x40004331 -.set CYDEV_PM_BASE, 0x40004380 -.set CYDEV_PM_SIZE, 0x00000057 -.set CYDEV_PM_TW_CFG0, 0x40004380 -.set CYDEV_PM_TW_CFG1, 0x40004381 -.set CYDEV_PM_TW_CFG2, 0x40004382 -.set CYDEV_PM_WDT_CFG, 0x40004383 -.set CYDEV_PM_WDT_CR, 0x40004384 -.set CYDEV_PM_INT_SR, 0x40004390 -.set CYDEV_PM_MODE_CFG0, 0x40004391 -.set CYDEV_PM_MODE_CFG1, 0x40004392 -.set CYDEV_PM_MODE_CSR, 0x40004393 -.set CYDEV_PM_USB_CR0, 0x40004394 -.set CYDEV_PM_WAKEUP_CFG0, 0x40004398 -.set CYDEV_PM_WAKEUP_CFG1, 0x40004399 -.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a -.set CYDEV_PM_ACT_BASE, 0x400043a0 -.set CYDEV_PM_ACT_SIZE, 0x0000000e -.set CYDEV_PM_ACT_CFG0, 0x400043a0 -.set CYDEV_PM_ACT_CFG1, 0x400043a1 -.set CYDEV_PM_ACT_CFG2, 0x400043a2 -.set CYDEV_PM_ACT_CFG3, 0x400043a3 -.set CYDEV_PM_ACT_CFG4, 0x400043a4 -.set CYDEV_PM_ACT_CFG5, 0x400043a5 -.set CYDEV_PM_ACT_CFG6, 0x400043a6 -.set CYDEV_PM_ACT_CFG7, 0x400043a7 -.set CYDEV_PM_ACT_CFG8, 0x400043a8 -.set CYDEV_PM_ACT_CFG9, 0x400043a9 -.set CYDEV_PM_ACT_CFG10, 0x400043aa -.set CYDEV_PM_ACT_CFG11, 0x400043ab -.set CYDEV_PM_ACT_CFG12, 0x400043ac -.set CYDEV_PM_ACT_CFG13, 0x400043ad -.set CYDEV_PM_STBY_BASE, 0x400043b0 -.set CYDEV_PM_STBY_SIZE, 0x0000000e -.set CYDEV_PM_STBY_CFG0, 0x400043b0 -.set CYDEV_PM_STBY_CFG1, 0x400043b1 -.set CYDEV_PM_STBY_CFG2, 0x400043b2 -.set CYDEV_PM_STBY_CFG3, 0x400043b3 -.set CYDEV_PM_STBY_CFG4, 0x400043b4 -.set CYDEV_PM_STBY_CFG5, 0x400043b5 -.set CYDEV_PM_STBY_CFG6, 0x400043b6 -.set CYDEV_PM_STBY_CFG7, 0x400043b7 -.set CYDEV_PM_STBY_CFG8, 0x400043b8 -.set CYDEV_PM_STBY_CFG9, 0x400043b9 -.set CYDEV_PM_STBY_CFG10, 0x400043ba -.set CYDEV_PM_STBY_CFG11, 0x400043bb -.set CYDEV_PM_STBY_CFG12, 0x400043bc -.set CYDEV_PM_STBY_CFG13, 0x400043bd -.set CYDEV_PM_AVAIL_BASE, 0x400043c0 -.set CYDEV_PM_AVAIL_SIZE, 0x00000017 -.set CYDEV_PM_AVAIL_CR0, 0x400043c0 -.set CYDEV_PM_AVAIL_CR1, 0x400043c1 -.set CYDEV_PM_AVAIL_CR2, 0x400043c2 -.set CYDEV_PM_AVAIL_CR3, 0x400043c3 -.set CYDEV_PM_AVAIL_CR4, 0x400043c4 -.set CYDEV_PM_AVAIL_CR5, 0x400043c5 -.set CYDEV_PM_AVAIL_CR6, 0x400043c6 -.set CYDEV_PM_AVAIL_SR0, 0x400043d0 -.set CYDEV_PM_AVAIL_SR1, 0x400043d1 -.set CYDEV_PM_AVAIL_SR2, 0x400043d2 -.set CYDEV_PM_AVAIL_SR3, 0x400043d3 -.set CYDEV_PM_AVAIL_SR4, 0x400043d4 -.set CYDEV_PM_AVAIL_SR5, 0x400043d5 -.set CYDEV_PM_AVAIL_SR6, 0x400043d6 -.set CYDEV_PICU_BASE, 0x40004500 -.set CYDEV_PICU_SIZE, 0x000000b0 -.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 -.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 -.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 -.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506 -.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507 -.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 -.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508 -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509 -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e -.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f -.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 -.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516 -.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517 -.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 -.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518 -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519 -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e -.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f -.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 -.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526 -.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527 -.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 -.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528 -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529 -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e -.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f -.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 -.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536 -.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537 -.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 -.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566 -.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567 -.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 -.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578 -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579 -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e -.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f -.set CYDEV_PICU_STAT_BASE, 0x40004580 -.set CYDEV_PICU_STAT_SIZE, 0x00000010 -.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 -.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580 -.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 -.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581 -.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 -.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582 -.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 -.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583 -.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 -.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584 -.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 -.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585 -.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 -.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586 -.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c -.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c -.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f -.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 -.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f -.set CYDEV_PICU_SNAP_BASE, 0x40004590 -.set CYDEV_PICU_SNAP_SIZE, 0x00000010 -.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 -.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590 -.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 -.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591 -.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 -.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592 -.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 -.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593 -.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 -.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594 -.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 -.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595 -.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 -.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596 -.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c -.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c -.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f -.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 -.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f -.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 -.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 -.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 -.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0 -.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 -.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1 -.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 -.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2 -.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 -.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3 -.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 -.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4 -.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 -.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5 -.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 -.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6 -.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac -.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac -.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af -.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 -.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af -.set CYDEV_MFGCFG_BASE, 0x40004600 -.set CYDEV_MFGCFG_SIZE, 0x000000ed -.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 -.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 -.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 -.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608 -.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 -.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609 -.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a -.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a -.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b -.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b -.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 -.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610 -.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 -.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611 -.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 -.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612 -.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 -.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614 -.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 -.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 -.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616 -.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 -.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620 -.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621 -.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 -.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622 -.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623 -.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 -.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624 -.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625 -.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 -.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626 -.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627 -.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 -.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630 -.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631 -.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 -.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632 -.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633 -.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 -.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634 -.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635 -.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 -.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636 -.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637 -.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 -.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b -.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680 -.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681 -.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682 -.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683 -.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684 -.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685 -.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686 -.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687 -.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688 -.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689 -.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a -.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 -.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 -.set CYDEV_MFGCFG_ILO_TR0, 0x40004690 -.set CYDEV_MFGCFG_ILO_TR1, 0x40004691 -.set CYDEV_MFGCFG_X32_BASE, 0x40004698 -.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 -.set CYDEV_MFGCFG_X32_TR, 0x40004698 -.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 -.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 -.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0 -.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1 -.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2 -.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3 -.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4 -.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 -.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 -.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8 -.set CYDEV_MFGCFG_DLY, 0x400046c0 -.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 -.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d -.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2 -.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 -.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 -.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4 -.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5 -.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8 -.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea -.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 -.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea -.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec -.set CYDEV_RESET_BASE, 0x400046f0 -.set CYDEV_RESET_SIZE, 0x0000000f -.set CYDEV_RESET_IPOR_CR0, 0x400046f0 -.set CYDEV_RESET_IPOR_CR1, 0x400046f1 -.set CYDEV_RESET_IPOR_CR2, 0x400046f2 -.set CYDEV_RESET_IPOR_CR3, 0x400046f3 -.set CYDEV_RESET_CR0, 0x400046f4 -.set CYDEV_RESET_CR1, 0x400046f5 -.set CYDEV_RESET_CR2, 0x400046f6 -.set CYDEV_RESET_CR3, 0x400046f7 -.set CYDEV_RESET_CR4, 0x400046f8 -.set CYDEV_RESET_CR5, 0x400046f9 -.set CYDEV_RESET_SR0, 0x400046fa -.set CYDEV_RESET_SR1, 0x400046fb -.set CYDEV_RESET_SR2, 0x400046fc -.set CYDEV_RESET_SR3, 0x400046fd -.set CYDEV_RESET_TR, 0x400046fe -.set CYDEV_SPC_BASE, 0x40004700 -.set CYDEV_SPC_SIZE, 0x00000100 -.set CYDEV_SPC_FM_EE_CR, 0x40004700 -.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701 -.set CYDEV_SPC_EE_SCR, 0x40004702 -.set CYDEV_SPC_EE_ERR, 0x40004703 -.set CYDEV_SPC_CPU_DATA, 0x40004720 -.set CYDEV_SPC_DMA_DATA, 0x40004721 -.set CYDEV_SPC_SR, 0x40004722 -.set CYDEV_SPC_CR, 0x40004723 -.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 -.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 -.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 -.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 -.set CYDEV_CACHE_BASE, 0x40004800 -.set CYDEV_CACHE_SIZE, 0x0000009c -.set CYDEV_CACHE_CC_CTL, 0x40004800 -.set CYDEV_CACHE_ECC_CORR, 0x40004880 -.set CYDEV_CACHE_ECC_ERR, 0x40004888 -.set CYDEV_CACHE_FLASH_ERR, 0x40004890 -.set CYDEV_CACHE_HITMISS, 0x40004898 -.set CYDEV_I2C_BASE, 0x40004900 -.set CYDEV_I2C_SIZE, 0x000000e1 -.set CYDEV_I2C_XCFG, 0x400049c8 -.set CYDEV_I2C_ADR, 0x400049ca -.set CYDEV_I2C_CFG, 0x400049d6 -.set CYDEV_I2C_CSR, 0x400049d7 -.set CYDEV_I2C_D, 0x400049d8 -.set CYDEV_I2C_MCSR, 0x400049d9 -.set CYDEV_I2C_CLK_DIV1, 0x400049db -.set CYDEV_I2C_CLK_DIV2, 0x400049dc -.set CYDEV_I2C_TMOUT_CSR, 0x400049dd -.set CYDEV_I2C_TMOUT_SR, 0x400049de -.set CYDEV_I2C_TMOUT_CFG0, 0x400049df -.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0 -.set CYDEV_DEC_BASE, 0x40004e00 -.set CYDEV_DEC_SIZE, 0x00000015 -.set CYDEV_DEC_CR, 0x40004e00 -.set CYDEV_DEC_SR, 0x40004e01 -.set CYDEV_DEC_SHIFT1, 0x40004e02 -.set CYDEV_DEC_SHIFT2, 0x40004e03 -.set CYDEV_DEC_DR2, 0x40004e04 -.set CYDEV_DEC_DR2H, 0x40004e05 -.set CYDEV_DEC_DR1, 0x40004e06 -.set CYDEV_DEC_OCOR, 0x40004e08 -.set CYDEV_DEC_OCORM, 0x40004e09 -.set CYDEV_DEC_OCORH, 0x40004e0a -.set CYDEV_DEC_GCOR, 0x40004e0c -.set CYDEV_DEC_GCORH, 0x40004e0d -.set CYDEV_DEC_GVAL, 0x40004e0e -.set CYDEV_DEC_OUTSAMP, 0x40004e10 -.set CYDEV_DEC_OUTSAMPM, 0x40004e11 -.set CYDEV_DEC_OUTSAMPH, 0x40004e12 -.set CYDEV_DEC_OUTSAMPS, 0x40004e13 -.set CYDEV_DEC_COHER, 0x40004e14 -.set CYDEV_TMR0_BASE, 0x40004f00 -.set CYDEV_TMR0_SIZE, 0x0000000c -.set CYDEV_TMR0_CFG0, 0x40004f00 -.set CYDEV_TMR0_CFG1, 0x40004f01 -.set CYDEV_TMR0_CFG2, 0x40004f02 -.set CYDEV_TMR0_SR0, 0x40004f03 -.set CYDEV_TMR0_PER0, 0x40004f04 -.set CYDEV_TMR0_PER1, 0x40004f05 -.set CYDEV_TMR0_CNT_CMP0, 0x40004f06 -.set CYDEV_TMR0_CNT_CMP1, 0x40004f07 -.set CYDEV_TMR0_CAP0, 0x40004f08 -.set CYDEV_TMR0_CAP1, 0x40004f09 -.set CYDEV_TMR0_RT0, 0x40004f0a -.set CYDEV_TMR0_RT1, 0x40004f0b -.set CYDEV_TMR1_BASE, 0x40004f0c -.set CYDEV_TMR1_SIZE, 0x0000000c -.set CYDEV_TMR1_CFG0, 0x40004f0c -.set CYDEV_TMR1_CFG1, 0x40004f0d -.set CYDEV_TMR1_CFG2, 0x40004f0e -.set CYDEV_TMR1_SR0, 0x40004f0f -.set CYDEV_TMR1_PER0, 0x40004f10 -.set CYDEV_TMR1_PER1, 0x40004f11 -.set CYDEV_TMR1_CNT_CMP0, 0x40004f12 -.set CYDEV_TMR1_CNT_CMP1, 0x40004f13 -.set CYDEV_TMR1_CAP0, 0x40004f14 -.set CYDEV_TMR1_CAP1, 0x40004f15 -.set CYDEV_TMR1_RT0, 0x40004f16 -.set CYDEV_TMR1_RT1, 0x40004f17 -.set CYDEV_TMR2_BASE, 0x40004f18 -.set CYDEV_TMR2_SIZE, 0x0000000c -.set CYDEV_TMR2_CFG0, 0x40004f18 -.set CYDEV_TMR2_CFG1, 0x40004f19 -.set CYDEV_TMR2_CFG2, 0x40004f1a -.set CYDEV_TMR2_SR0, 0x40004f1b -.set CYDEV_TMR2_PER0, 0x40004f1c -.set CYDEV_TMR2_PER1, 0x40004f1d -.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e -.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f -.set CYDEV_TMR2_CAP0, 0x40004f20 -.set CYDEV_TMR2_CAP1, 0x40004f21 -.set CYDEV_TMR2_RT0, 0x40004f22 -.set CYDEV_TMR2_RT1, 0x40004f23 -.set CYDEV_TMR3_BASE, 0x40004f24 -.set CYDEV_TMR3_SIZE, 0x0000000c -.set CYDEV_TMR3_CFG0, 0x40004f24 -.set CYDEV_TMR3_CFG1, 0x40004f25 -.set CYDEV_TMR3_CFG2, 0x40004f26 -.set CYDEV_TMR3_SR0, 0x40004f27 -.set CYDEV_TMR3_PER0, 0x40004f28 -.set CYDEV_TMR3_PER1, 0x40004f29 -.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a -.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b -.set CYDEV_TMR3_CAP0, 0x40004f2c -.set CYDEV_TMR3_CAP1, 0x40004f2d -.set CYDEV_TMR3_RT0, 0x40004f2e -.set CYDEV_TMR3_RT1, 0x40004f2f -.set CYDEV_IO_BASE, 0x40005000 -.set CYDEV_IO_SIZE, 0x00000200 -.set CYDEV_IO_PC_BASE, 0x40005000 -.set CYDEV_IO_PC_SIZE, 0x00000080 -.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 -.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT0_PC0, 0x40005000 -.set CYDEV_IO_PC_PRT0_PC1, 0x40005001 -.set CYDEV_IO_PC_PRT0_PC2, 0x40005002 -.set CYDEV_IO_PC_PRT0_PC3, 0x40005003 -.set CYDEV_IO_PC_PRT0_PC4, 0x40005004 -.set CYDEV_IO_PC_PRT0_PC5, 0x40005005 -.set CYDEV_IO_PC_PRT0_PC6, 0x40005006 -.set CYDEV_IO_PC_PRT0_PC7, 0x40005007 -.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 -.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT1_PC0, 0x40005008 -.set CYDEV_IO_PC_PRT1_PC1, 0x40005009 -.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a -.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b -.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c -.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d -.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e -.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f -.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 -.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT2_PC0, 0x40005010 -.set CYDEV_IO_PC_PRT2_PC1, 0x40005011 -.set CYDEV_IO_PC_PRT2_PC2, 0x40005012 -.set CYDEV_IO_PC_PRT2_PC3, 0x40005013 -.set CYDEV_IO_PC_PRT2_PC4, 0x40005014 -.set CYDEV_IO_PC_PRT2_PC5, 0x40005015 -.set CYDEV_IO_PC_PRT2_PC6, 0x40005016 -.set CYDEV_IO_PC_PRT2_PC7, 0x40005017 -.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 -.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT3_PC0, 0x40005018 -.set CYDEV_IO_PC_PRT3_PC1, 0x40005019 -.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a -.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b -.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c -.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d -.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e -.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f -.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 -.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT4_PC0, 0x40005020 -.set CYDEV_IO_PC_PRT4_PC1, 0x40005021 -.set CYDEV_IO_PC_PRT4_PC2, 0x40005022 -.set CYDEV_IO_PC_PRT4_PC3, 0x40005023 -.set CYDEV_IO_PC_PRT4_PC4, 0x40005024 -.set CYDEV_IO_PC_PRT4_PC5, 0x40005025 -.set CYDEV_IO_PC_PRT4_PC6, 0x40005026 -.set CYDEV_IO_PC_PRT4_PC7, 0x40005027 -.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 -.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT5_PC0, 0x40005028 -.set CYDEV_IO_PC_PRT5_PC1, 0x40005029 -.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a -.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b -.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c -.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d -.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e -.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f -.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 -.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT6_PC0, 0x40005030 -.set CYDEV_IO_PC_PRT6_PC1, 0x40005031 -.set CYDEV_IO_PC_PRT6_PC2, 0x40005032 -.set CYDEV_IO_PC_PRT6_PC3, 0x40005033 -.set CYDEV_IO_PC_PRT6_PC4, 0x40005034 -.set CYDEV_IO_PC_PRT6_PC5, 0x40005035 -.set CYDEV_IO_PC_PRT6_PC6, 0x40005036 -.set CYDEV_IO_PC_PRT6_PC7, 0x40005037 -.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 -.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 -.set CYDEV_IO_PC_PRT12_PC0, 0x40005060 -.set CYDEV_IO_PC_PRT12_PC1, 0x40005061 -.set CYDEV_IO_PC_PRT12_PC2, 0x40005062 -.set CYDEV_IO_PC_PRT12_PC3, 0x40005063 -.set CYDEV_IO_PC_PRT12_PC4, 0x40005064 -.set CYDEV_IO_PC_PRT12_PC5, 0x40005065 -.set CYDEV_IO_PC_PRT12_PC6, 0x40005066 -.set CYDEV_IO_PC_PRT12_PC7, 0x40005067 -.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 -.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 -.set CYDEV_IO_PC_PRT15_PC0, 0x40005078 -.set CYDEV_IO_PC_PRT15_PC1, 0x40005079 -.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a -.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b -.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c -.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d -.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e -.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 -.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e -.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f -.set CYDEV_IO_DR_BASE, 0x40005080 -.set CYDEV_IO_DR_SIZE, 0x00000010 -.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 -.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080 -.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 -.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081 -.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 -.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082 -.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 -.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083 -.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 -.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084 -.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 -.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085 -.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 -.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086 -.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c -.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c -.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f -.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 -.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f -.set CYDEV_IO_PS_BASE, 0x40005090 -.set CYDEV_IO_PS_SIZE, 0x00000010 -.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 -.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090 -.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 -.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091 -.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 -.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092 -.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 -.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093 -.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 -.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094 -.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 -.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095 -.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 -.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096 -.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c -.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c -.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f -.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 -.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f -.set CYDEV_IO_PRT_BASE, 0x40005100 -.set CYDEV_IO_PRT_SIZE, 0x00000100 -.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 -.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT0_DR, 0x40005100 -.set CYDEV_IO_PRT_PRT0_PS, 0x40005101 -.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102 -.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103 -.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104 -.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105 -.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106 -.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107 -.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108 -.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109 -.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a -.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b -.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c -.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d -.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e -.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f -.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 -.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT1_DR, 0x40005110 -.set CYDEV_IO_PRT_PRT1_PS, 0x40005111 -.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112 -.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113 -.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114 -.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115 -.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116 -.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117 -.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118 -.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119 -.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a -.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b -.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c -.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d -.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e -.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f -.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 -.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT2_DR, 0x40005120 -.set CYDEV_IO_PRT_PRT2_PS, 0x40005121 -.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122 -.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123 -.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124 -.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125 -.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126 -.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127 -.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128 -.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129 -.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a -.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b -.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c -.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d -.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e -.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f -.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 -.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT3_DR, 0x40005130 -.set CYDEV_IO_PRT_PRT3_PS, 0x40005131 -.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132 -.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133 -.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134 -.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135 -.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136 -.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137 -.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138 -.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139 -.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a -.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b -.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c -.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d -.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e -.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f -.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 -.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT4_DR, 0x40005140 -.set CYDEV_IO_PRT_PRT4_PS, 0x40005141 -.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142 -.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143 -.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144 -.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145 -.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146 -.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147 -.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148 -.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149 -.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a -.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b -.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c -.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d -.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e -.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f -.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 -.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT5_DR, 0x40005150 -.set CYDEV_IO_PRT_PRT5_PS, 0x40005151 -.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152 -.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153 -.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154 -.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155 -.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156 -.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157 -.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158 -.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159 -.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a -.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b -.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c -.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d -.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e -.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f -.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 -.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT6_DR, 0x40005160 -.set CYDEV_IO_PRT_PRT6_PS, 0x40005161 -.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162 -.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163 -.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164 -.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165 -.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166 -.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167 -.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168 -.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169 -.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a -.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b -.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c -.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d -.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e -.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f -.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 -.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0 -.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1 -.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2 -.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3 -.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4 -.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5 -.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6 -.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7 -.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8 -.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9 -.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca -.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb -.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc -.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd -.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce -.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf -.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 -.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 -.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0 -.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1 -.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2 -.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3 -.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4 -.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5 -.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6 -.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7 -.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8 -.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9 -.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa -.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb -.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc -.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd -.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe -.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff -.set CYDEV_PRTDSI_BASE, 0x40005200 -.set CYDEV_PRTDSI_SIZE, 0x0000007f -.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 -.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200 -.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201 -.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202 -.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203 -.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204 -.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205 -.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206 -.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 -.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208 -.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209 -.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a -.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b -.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c -.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d -.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e -.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 -.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210 -.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211 -.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212 -.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213 -.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214 -.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215 -.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216 -.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 -.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218 -.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219 -.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a -.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b -.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c -.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d -.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e -.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 -.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220 -.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221 -.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222 -.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223 -.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224 -.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225 -.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226 -.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 -.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228 -.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229 -.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a -.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b -.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c -.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d -.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e -.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 -.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230 -.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231 -.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232 -.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233 -.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234 -.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235 -.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236 -.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 -.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 -.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260 -.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261 -.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262 -.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263 -.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264 -.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265 -.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 -.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 -.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278 -.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279 -.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a -.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b -.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c -.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d -.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e -.set CYDEV_EMIF_BASE, 0x40005400 -.set CYDEV_EMIF_SIZE, 0x00000007 -.set CYDEV_EMIF_NO_UDB, 0x40005400 -.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401 -.set CYDEV_EMIF_MEM_DWN, 0x40005402 -.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403 -.set CYDEV_EMIF_CLOCK_EN, 0x40005404 -.set CYDEV_EMIF_EM_TYPE, 0x40005405 -.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406 -.set CYDEV_ANAIF_BASE, 0x40005800 -.set CYDEV_ANAIF_SIZE, 0x000003a9 -.set CYDEV_ANAIF_CFG_BASE, 0x40005800 -.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f -.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 -.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800 -.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801 -.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802 -.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 -.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804 -.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805 -.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806 -.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 -.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808 -.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809 -.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a -.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c -.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c -.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d -.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e -.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 -.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820 -.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821 -.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822 -.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 -.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824 -.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825 -.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826 -.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 -.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828 -.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829 -.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a -.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c -.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 -.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c -.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d -.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e -.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 -.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 -.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840 -.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 -.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 -.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841 -.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 -.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 -.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842 -.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 -.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 -.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843 -.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 -.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848 -.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849 -.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a -.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a -.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b -.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c -.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c -.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d -.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e -.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e -.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f -.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 -.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858 -.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859 -.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a -.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a -.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b -.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c -.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c -.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d -.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e -.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e -.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f -.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 -.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868 -.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869 -.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a -.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 -.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a -.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b -.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 -.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b -.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c -.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 -.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c -.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d -.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e -.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f -.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 -.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870 -.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871 -.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 -.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872 -.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873 -.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 -.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876 -.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877 -.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 -.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878 -.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879 -.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a -.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 -.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a -.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b -.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c -.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 -.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c -.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 -.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 -.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880 -.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881 -.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882 -.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883 -.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884 -.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885 -.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886 -.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887 -.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888 -.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889 -.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a -.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b -.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c -.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d -.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e -.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f -.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890 -.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891 -.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892 -.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893 -.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894 -.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895 -.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896 -.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897 -.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898 -.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899 -.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a -.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b -.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c -.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d -.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e -.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f -.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 -.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 -.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900 -.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901 -.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902 -.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903 -.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904 -.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905 -.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906 -.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 -.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 -.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908 -.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909 -.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a -.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b -.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c -.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d -.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e -.set CYDEV_ANAIF_RT_BASE, 0x40005a00 -.set CYDEV_ANAIF_RT_SIZE, 0x00000162 -.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 -.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d -.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00 -.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02 -.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03 -.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04 -.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06 -.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07 -.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08 -.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a -.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b -.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c -.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 -.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d -.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10 -.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12 -.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13 -.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14 -.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16 -.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17 -.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18 -.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a -.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b -.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c -.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 -.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d -.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20 -.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22 -.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23 -.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24 -.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26 -.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27 -.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28 -.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a -.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b -.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c -.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 -.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d -.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30 -.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32 -.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33 -.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34 -.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36 -.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37 -.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38 -.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a -.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b -.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c -.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 -.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80 -.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82 -.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83 -.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84 -.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87 -.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 -.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88 -.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a -.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b -.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c -.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f -.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 -.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90 -.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92 -.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93 -.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94 -.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97 -.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 -.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98 -.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a -.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b -.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c -.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f -.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 -.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0 -.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2 -.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3 -.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4 -.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6 -.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7 -.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 -.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8 -.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca -.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb -.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc -.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace -.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf -.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 -.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0 -.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2 -.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3 -.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4 -.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6 -.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7 -.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 -.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8 -.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada -.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb -.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc -.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade -.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf -.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 -.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00 -.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02 -.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03 -.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04 -.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06 -.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07 -.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 -.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20 -.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22 -.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23 -.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24 -.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26 -.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27 -.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 -.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 -.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28 -.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a -.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b -.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c -.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e -.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f -.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 -.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 -.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40 -.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41 -.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 -.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 -.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42 -.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43 -.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 -.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 -.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44 -.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45 -.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 -.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 -.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46 -.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47 -.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 -.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 -.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50 -.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51 -.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52 -.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53 -.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54 -.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 -.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 -.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56 -.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 -.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 -.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58 -.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a -.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b -.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c -.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 -.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c -.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d -.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e -.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f -.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60 -.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61 -.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 -.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 -.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 -.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 -.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80 -.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 -.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 -.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81 -.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 -.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 -.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82 -.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 -.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 -.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83 -.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 -.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 -.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88 -.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89 -.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 -.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 -.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90 -.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91 -.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92 -.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93 -.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94 -.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 -.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 -.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96 -.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97 -.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 -.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 -.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98 -.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99 -.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a -.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b -.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c -.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 -.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 -.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0 -.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1 -.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 -.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 -.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2 -.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3 -.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 -.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 -.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8 -.set CYDEV_USB_BASE, 0x40006000 -.set CYDEV_USB_SIZE, 0x00000300 -.set CYDEV_USB_EP0_DR0, 0x40006000 -.set CYDEV_USB_EP0_DR1, 0x40006001 -.set CYDEV_USB_EP0_DR2, 0x40006002 -.set CYDEV_USB_EP0_DR3, 0x40006003 -.set CYDEV_USB_EP0_DR4, 0x40006004 -.set CYDEV_USB_EP0_DR5, 0x40006005 -.set CYDEV_USB_EP0_DR6, 0x40006006 -.set CYDEV_USB_EP0_DR7, 0x40006007 -.set CYDEV_USB_CR0, 0x40006008 -.set CYDEV_USB_CR1, 0x40006009 -.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a -.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b -.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c -.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c -.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d -.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e -.set CYDEV_USB_USBIO_CR0, 0x40006010 -.set CYDEV_USB_USBIO_CR1, 0x40006012 -.set CYDEV_USB_DYN_RECONFIG, 0x40006014 -.set CYDEV_USB_SOF0, 0x40006018 -.set CYDEV_USB_SOF1, 0x40006019 -.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c -.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c -.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d -.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e -.set CYDEV_USB_EP0_CR, 0x40006028 -.set CYDEV_USB_EP0_CNT, 0x40006029 -.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c -.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c -.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d -.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e -.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c -.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c -.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d -.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e -.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c -.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c -.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d -.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e -.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c -.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c -.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d -.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e -.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c -.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c -.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d -.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e -.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c -.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 -.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c -.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d -.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e -.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 -.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP1_CFG, 0x40006080 -.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081 -.set CYDEV_USB_ARB_EP1_SR, 0x40006082 -.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 -.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW1_WA, 0x40006084 -.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085 -.set CYDEV_USB_ARB_RW1_RA, 0x40006086 -.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087 -.set CYDEV_USB_ARB_RW1_DR, 0x40006088 -.set CYDEV_USB_BUF_SIZE, 0x4000608c -.set CYDEV_USB_EP_ACTIVE, 0x4000608e -.set CYDEV_USB_EP_TYPE, 0x4000608f -.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 -.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP2_CFG, 0x40006090 -.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091 -.set CYDEV_USB_ARB_EP2_SR, 0x40006092 -.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 -.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW2_WA, 0x40006094 -.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095 -.set CYDEV_USB_ARB_RW2_RA, 0x40006096 -.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097 -.set CYDEV_USB_ARB_RW2_DR, 0x40006098 -.set CYDEV_USB_ARB_CFG, 0x4000609c -.set CYDEV_USB_USB_CLK_EN, 0x4000609d -.set CYDEV_USB_ARB_INT_EN, 0x4000609e -.set CYDEV_USB_ARB_INT_SR, 0x4000609f -.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 -.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0 -.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1 -.set CYDEV_USB_ARB_EP3_SR, 0x400060a2 -.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 -.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW3_WA, 0x400060a4 -.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5 -.set CYDEV_USB_ARB_RW3_RA, 0x400060a6 -.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7 -.set CYDEV_USB_ARB_RW3_DR, 0x400060a8 -.set CYDEV_USB_CWA, 0x400060ac -.set CYDEV_USB_CWA_MSB, 0x400060ad -.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 -.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0 -.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1 -.set CYDEV_USB_ARB_EP4_SR, 0x400060b2 -.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 -.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW4_WA, 0x400060b4 -.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5 -.set CYDEV_USB_ARB_RW4_RA, 0x400060b6 -.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7 -.set CYDEV_USB_ARB_RW4_DR, 0x400060b8 -.set CYDEV_USB_DMA_THRES, 0x400060bc -.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd -.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 -.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0 -.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1 -.set CYDEV_USB_ARB_EP5_SR, 0x400060c2 -.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 -.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW5_WA, 0x400060c4 -.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5 -.set CYDEV_USB_ARB_RW5_RA, 0x400060c6 -.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7 -.set CYDEV_USB_ARB_RW5_DR, 0x400060c8 -.set CYDEV_USB_BUS_RST_CNT, 0x400060cc -.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 -.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0 -.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1 -.set CYDEV_USB_ARB_EP6_SR, 0x400060d2 -.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 -.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW6_WA, 0x400060d4 -.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5 -.set CYDEV_USB_ARB_RW6_RA, 0x400060d6 -.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7 -.set CYDEV_USB_ARB_RW6_DR, 0x400060d8 -.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 -.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0 -.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1 -.set CYDEV_USB_ARB_EP7_SR, 0x400060e2 -.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 -.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW7_WA, 0x400060e4 -.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5 -.set CYDEV_USB_ARB_RW7_RA, 0x400060e6 -.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7 -.set CYDEV_USB_ARB_RW7_DR, 0x400060e8 -.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 -.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 -.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0 -.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1 -.set CYDEV_USB_ARB_EP8_SR, 0x400060f2 -.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 -.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 -.set CYDEV_USB_ARB_RW8_WA, 0x400060f4 -.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5 -.set CYDEV_USB_ARB_RW8_RA, 0x400060f6 -.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7 -.set CYDEV_USB_ARB_RW8_DR, 0x400060f8 -.set CYDEV_USB_MEM_BASE, 0x40006100 -.set CYDEV_USB_MEM_SIZE, 0x00000200 -.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100 -.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200 -.set CYDEV_UWRK_BASE, 0x40006400 -.set CYDEV_UWRK_SIZE, 0x00000b60 -.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 -.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 -.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 -.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 -.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400 -.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401 -.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402 -.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403 -.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404 -.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405 -.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406 -.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407 -.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408 -.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409 -.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a -.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b -.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c -.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d -.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e -.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f -.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410 -.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411 -.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412 -.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413 -.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414 -.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415 -.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416 -.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417 -.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418 -.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419 -.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a -.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b -.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c -.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d -.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e -.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f -.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420 -.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421 -.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422 -.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423 -.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424 -.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425 -.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426 -.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427 -.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428 -.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429 -.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a -.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b -.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c -.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d -.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e -.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f -.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430 -.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431 -.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432 -.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433 -.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434 -.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435 -.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436 -.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437 -.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438 -.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439 -.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a -.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b -.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c -.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d -.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e -.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f -.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440 -.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441 -.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442 -.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443 -.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444 -.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445 -.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446 -.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447 -.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448 -.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449 -.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a -.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b -.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c -.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d -.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e -.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f -.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450 -.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451 -.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452 -.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453 -.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454 -.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455 -.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456 -.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457 -.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458 -.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459 -.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a -.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b -.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c -.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d -.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e -.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f -.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460 -.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461 -.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462 -.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463 -.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464 -.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465 -.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466 -.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467 -.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468 -.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469 -.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a -.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b -.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c -.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d -.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e -.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f -.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470 -.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471 -.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472 -.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473 -.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474 -.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475 -.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476 -.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477 -.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478 -.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479 -.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a -.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b -.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c -.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d -.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e -.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f -.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480 -.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481 -.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482 -.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483 -.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484 -.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485 -.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486 -.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487 -.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488 -.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489 -.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a -.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b -.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c -.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d -.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e -.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f -.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490 -.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491 -.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492 -.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493 -.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494 -.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495 -.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496 -.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497 -.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498 -.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499 -.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a -.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b -.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c -.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d -.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e -.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f -.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0 -.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1 -.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2 -.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3 -.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4 -.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5 -.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6 -.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7 -.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8 -.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9 -.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa -.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab -.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac -.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad -.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae -.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af -.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 -.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 -.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504 -.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505 -.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506 -.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507 -.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508 -.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509 -.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a -.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b -.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514 -.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515 -.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516 -.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517 -.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518 -.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519 -.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a -.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b -.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524 -.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525 -.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526 -.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527 -.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528 -.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529 -.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a -.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b -.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534 -.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535 -.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536 -.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537 -.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538 -.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539 -.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a -.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b -.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544 -.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545 -.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546 -.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547 -.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548 -.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549 -.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a -.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b -.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554 -.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555 -.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556 -.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557 -.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558 -.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559 -.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a -.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b -.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564 -.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565 -.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566 -.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567 -.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568 -.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569 -.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a -.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b -.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574 -.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575 -.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576 -.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577 -.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578 -.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579 -.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a -.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b -.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584 -.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585 -.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586 -.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587 -.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588 -.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589 -.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a -.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b -.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594 -.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595 -.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596 -.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597 -.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598 -.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599 -.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a -.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b -.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4 -.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5 -.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6 -.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7 -.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8 -.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9 -.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa -.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab -.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 -.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 -.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958 -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c -.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e -.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 -.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54 -.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56 -.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e -.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958 -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a -.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c -.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 -.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54 -.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56 -.set CYDEV_PHUB_BASE, 0x40007000 -.set CYDEV_PHUB_SIZE, 0x00000c00 -.set CYDEV_PHUB_CFG, 0x40007000 -.set CYDEV_PHUB_ERR, 0x40007004 -.set CYDEV_PHUB_ERR_ADR, 0x40007008 -.set CYDEV_PHUB_CH0_BASE, 0x40007010 -.set CYDEV_PHUB_CH0_SIZE, 0x0000000c -.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010 -.set CYDEV_PHUB_CH0_ACTION, 0x40007014 -.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018 -.set CYDEV_PHUB_CH1_BASE, 0x40007020 -.set CYDEV_PHUB_CH1_SIZE, 0x0000000c -.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020 -.set CYDEV_PHUB_CH1_ACTION, 0x40007024 -.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028 -.set CYDEV_PHUB_CH2_BASE, 0x40007030 -.set CYDEV_PHUB_CH2_SIZE, 0x0000000c -.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030 -.set CYDEV_PHUB_CH2_ACTION, 0x40007034 -.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038 -.set CYDEV_PHUB_CH3_BASE, 0x40007040 -.set CYDEV_PHUB_CH3_SIZE, 0x0000000c -.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040 -.set CYDEV_PHUB_CH3_ACTION, 0x40007044 -.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048 -.set CYDEV_PHUB_CH4_BASE, 0x40007050 -.set CYDEV_PHUB_CH4_SIZE, 0x0000000c -.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050 -.set CYDEV_PHUB_CH4_ACTION, 0x40007054 -.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058 -.set CYDEV_PHUB_CH5_BASE, 0x40007060 -.set CYDEV_PHUB_CH5_SIZE, 0x0000000c -.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060 -.set CYDEV_PHUB_CH5_ACTION, 0x40007064 -.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068 -.set CYDEV_PHUB_CH6_BASE, 0x40007070 -.set CYDEV_PHUB_CH6_SIZE, 0x0000000c -.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070 -.set CYDEV_PHUB_CH6_ACTION, 0x40007074 -.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078 -.set CYDEV_PHUB_CH7_BASE, 0x40007080 -.set CYDEV_PHUB_CH7_SIZE, 0x0000000c -.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080 -.set CYDEV_PHUB_CH7_ACTION, 0x40007084 -.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088 -.set CYDEV_PHUB_CH8_BASE, 0x40007090 -.set CYDEV_PHUB_CH8_SIZE, 0x0000000c -.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090 -.set CYDEV_PHUB_CH8_ACTION, 0x40007094 -.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098 -.set CYDEV_PHUB_CH9_BASE, 0x400070a0 -.set CYDEV_PHUB_CH9_SIZE, 0x0000000c -.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0 -.set CYDEV_PHUB_CH9_ACTION, 0x400070a4 -.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8 -.set CYDEV_PHUB_CH10_BASE, 0x400070b0 -.set CYDEV_PHUB_CH10_SIZE, 0x0000000c -.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0 -.set CYDEV_PHUB_CH10_ACTION, 0x400070b4 -.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8 -.set CYDEV_PHUB_CH11_BASE, 0x400070c0 -.set CYDEV_PHUB_CH11_SIZE, 0x0000000c -.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0 -.set CYDEV_PHUB_CH11_ACTION, 0x400070c4 -.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8 -.set CYDEV_PHUB_CH12_BASE, 0x400070d0 -.set CYDEV_PHUB_CH12_SIZE, 0x0000000c -.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0 -.set CYDEV_PHUB_CH12_ACTION, 0x400070d4 -.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8 -.set CYDEV_PHUB_CH13_BASE, 0x400070e0 -.set CYDEV_PHUB_CH13_SIZE, 0x0000000c -.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0 -.set CYDEV_PHUB_CH13_ACTION, 0x400070e4 -.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8 -.set CYDEV_PHUB_CH14_BASE, 0x400070f0 -.set CYDEV_PHUB_CH14_SIZE, 0x0000000c -.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0 -.set CYDEV_PHUB_CH14_ACTION, 0x400070f4 -.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8 -.set CYDEV_PHUB_CH15_BASE, 0x40007100 -.set CYDEV_PHUB_CH15_SIZE, 0x0000000c -.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100 -.set CYDEV_PHUB_CH15_ACTION, 0x40007104 -.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108 -.set CYDEV_PHUB_CH16_BASE, 0x40007110 -.set CYDEV_PHUB_CH16_SIZE, 0x0000000c -.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110 -.set CYDEV_PHUB_CH16_ACTION, 0x40007114 -.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118 -.set CYDEV_PHUB_CH17_BASE, 0x40007120 -.set CYDEV_PHUB_CH17_SIZE, 0x0000000c -.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120 -.set CYDEV_PHUB_CH17_ACTION, 0x40007124 -.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128 -.set CYDEV_PHUB_CH18_BASE, 0x40007130 -.set CYDEV_PHUB_CH18_SIZE, 0x0000000c -.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130 -.set CYDEV_PHUB_CH18_ACTION, 0x40007134 -.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138 -.set CYDEV_PHUB_CH19_BASE, 0x40007140 -.set CYDEV_PHUB_CH19_SIZE, 0x0000000c -.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140 -.set CYDEV_PHUB_CH19_ACTION, 0x40007144 -.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148 -.set CYDEV_PHUB_CH20_BASE, 0x40007150 -.set CYDEV_PHUB_CH20_SIZE, 0x0000000c -.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150 -.set CYDEV_PHUB_CH20_ACTION, 0x40007154 -.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158 -.set CYDEV_PHUB_CH21_BASE, 0x40007160 -.set CYDEV_PHUB_CH21_SIZE, 0x0000000c -.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160 -.set CYDEV_PHUB_CH21_ACTION, 0x40007164 -.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168 -.set CYDEV_PHUB_CH22_BASE, 0x40007170 -.set CYDEV_PHUB_CH22_SIZE, 0x0000000c -.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170 -.set CYDEV_PHUB_CH22_ACTION, 0x40007174 -.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178 -.set CYDEV_PHUB_CH23_BASE, 0x40007180 -.set CYDEV_PHUB_CH23_SIZE, 0x0000000c -.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180 -.set CYDEV_PHUB_CH23_ACTION, 0x40007184 -.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188 -.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 -.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600 -.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604 -.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 -.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608 -.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c -.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 -.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610 -.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614 -.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 -.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618 -.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c -.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 -.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620 -.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624 -.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 -.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628 -.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c -.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 -.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630 -.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634 -.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 -.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638 -.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c -.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 -.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640 -.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644 -.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 -.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648 -.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c -.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 -.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650 -.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654 -.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 -.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658 -.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c -.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 -.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660 -.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664 -.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 -.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668 -.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c -.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 -.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670 -.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674 -.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 -.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678 -.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c -.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 -.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680 -.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684 -.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 -.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688 -.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c -.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 -.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690 -.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694 -.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 -.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698 -.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c -.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 -.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0 -.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4 -.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 -.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8 -.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac -.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 -.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0 -.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4 -.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 -.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 -.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8 -.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc -.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 -.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800 -.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804 -.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 -.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808 -.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c -.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 -.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810 -.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814 -.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 -.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818 -.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c -.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 -.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820 -.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824 -.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 -.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828 -.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c -.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 -.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830 -.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834 -.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 -.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838 -.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c -.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 -.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840 -.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844 -.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 -.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848 -.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c -.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 -.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850 -.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854 -.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 -.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858 -.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c -.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 -.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860 -.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864 -.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 -.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868 -.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c -.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 -.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870 -.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874 -.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 -.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878 -.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c -.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 -.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880 -.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884 -.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 -.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888 -.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c -.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 -.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890 -.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894 -.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 -.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898 -.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c -.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 -.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 -.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 -.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 -.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 -.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac -.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 -.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 -.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 -.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 -.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 -.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc -.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 -.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 -.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 -.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 -.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 -.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc -.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 -.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 -.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 -.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 -.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 -.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc -.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 -.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 -.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 -.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 -.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 -.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec -.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 -.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 -.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 -.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 -.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 -.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc -.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 -.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900 -.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904 -.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 -.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908 -.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c -.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 -.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910 -.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914 -.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 -.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918 -.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c -.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 -.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920 -.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924 -.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 -.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928 -.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c -.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 -.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930 -.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934 -.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 -.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938 -.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c -.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 -.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940 -.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944 -.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 -.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948 -.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c -.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 -.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950 -.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954 -.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 -.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958 -.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c -.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 -.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960 -.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964 -.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 -.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968 -.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c -.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 -.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970 -.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974 -.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 -.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978 -.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c -.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 -.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980 -.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984 -.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 -.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988 -.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c -.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 -.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990 -.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994 -.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 -.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998 -.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c -.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 -.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 -.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 -.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 -.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 -.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac -.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 -.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 -.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 -.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 -.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 -.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc -.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 -.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 -.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 -.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 -.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 -.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc -.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 -.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 -.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 -.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 -.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 -.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc -.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 -.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 -.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 -.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 -.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 -.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec -.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 -.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 -.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 -.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 -.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 -.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc -.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 -.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 -.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 -.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 -.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 -.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c -.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 -.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 -.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 -.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 -.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 -.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c -.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 -.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 -.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 -.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 -.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 -.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c -.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 -.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 -.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 -.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 -.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 -.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c -.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 -.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 -.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 -.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 -.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 -.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c -.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 -.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 -.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 -.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 -.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 -.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c -.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 -.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 -.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 -.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 -.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 -.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c -.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 -.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 -.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 -.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 -.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 -.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c -.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 -.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 -.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 -.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 -.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 -.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c -.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 -.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 -.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 -.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 -.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 -.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c -.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 -.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 -.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 -.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 -.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 -.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac -.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 -.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 -.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 -.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 -.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 -.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc -.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 -.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 -.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 -.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 -.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 -.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc -.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 -.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 -.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 -.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 -.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 -.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc -.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 -.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 -.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 -.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 -.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 -.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec -.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 -.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 -.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 -.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 -.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 -.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc -.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 -.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 -.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 -.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 -.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 -.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c -.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 -.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 -.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 -.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 -.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 -.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c -.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 -.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 -.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 -.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 -.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 -.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c -.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 -.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 -.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 -.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 -.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 -.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c -.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 -.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 -.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 -.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 -.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 -.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c -.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 -.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 -.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 -.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 -.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 -.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c -.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 -.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 -.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 -.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 -.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 -.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c -.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 -.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 -.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 -.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 -.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 -.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c -.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 -.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 -.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 -.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 -.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 -.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c -.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 -.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 -.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 -.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 -.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 -.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c -.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 -.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 -.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 -.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 -.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 -.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac -.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 -.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 -.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 -.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 -.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 -.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc -.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 -.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 -.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 -.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 -.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 -.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc -.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 -.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 -.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 -.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 -.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 -.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc -.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 -.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 -.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 -.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 -.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 -.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec -.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 -.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 -.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 -.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 -.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 -.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 -.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc -.set CYDEV_EE_BASE, 0x40008000 -.set CYDEV_EE_SIZE, 0x00000800 -.set CYDEV_EE_DATA_MBASE, 0x40008000 -.set CYDEV_EE_DATA_MSIZE, 0x00000800 -.set CYDEV_CAN0_BASE, 0x4000a000 -.set CYDEV_CAN0_SIZE, 0x000002a0 -.set CYDEV_CAN0_CSR_BASE, 0x4000a000 -.set CYDEV_CAN0_CSR_SIZE, 0x00000018 -.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000 -.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004 -.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008 -.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c -.set CYDEV_CAN0_CSR_CMD, 0x4000a010 -.set CYDEV_CAN0_CSR_CFG, 0x4000a014 -.set CYDEV_CAN0_TX0_BASE, 0x4000a020 -.set CYDEV_CAN0_TX0_SIZE, 0x00000010 -.set CYDEV_CAN0_TX0_CMD, 0x4000a020 -.set CYDEV_CAN0_TX0_ID, 0x4000a024 -.set CYDEV_CAN0_TX0_DH, 0x4000a028 -.set CYDEV_CAN0_TX0_DL, 0x4000a02c -.set CYDEV_CAN0_TX1_BASE, 0x4000a030 -.set CYDEV_CAN0_TX1_SIZE, 0x00000010 -.set CYDEV_CAN0_TX1_CMD, 0x4000a030 -.set CYDEV_CAN0_TX1_ID, 0x4000a034 -.set CYDEV_CAN0_TX1_DH, 0x4000a038 -.set CYDEV_CAN0_TX1_DL, 0x4000a03c -.set CYDEV_CAN0_TX2_BASE, 0x4000a040 -.set CYDEV_CAN0_TX2_SIZE, 0x00000010 -.set CYDEV_CAN0_TX2_CMD, 0x4000a040 -.set CYDEV_CAN0_TX2_ID, 0x4000a044 -.set CYDEV_CAN0_TX2_DH, 0x4000a048 -.set CYDEV_CAN0_TX2_DL, 0x4000a04c -.set CYDEV_CAN0_TX3_BASE, 0x4000a050 -.set CYDEV_CAN0_TX3_SIZE, 0x00000010 -.set CYDEV_CAN0_TX3_CMD, 0x4000a050 -.set CYDEV_CAN0_TX3_ID, 0x4000a054 -.set CYDEV_CAN0_TX3_DH, 0x4000a058 -.set CYDEV_CAN0_TX3_DL, 0x4000a05c -.set CYDEV_CAN0_TX4_BASE, 0x4000a060 -.set CYDEV_CAN0_TX4_SIZE, 0x00000010 -.set CYDEV_CAN0_TX4_CMD, 0x4000a060 -.set CYDEV_CAN0_TX4_ID, 0x4000a064 -.set CYDEV_CAN0_TX4_DH, 0x4000a068 -.set CYDEV_CAN0_TX4_DL, 0x4000a06c -.set CYDEV_CAN0_TX5_BASE, 0x4000a070 -.set CYDEV_CAN0_TX5_SIZE, 0x00000010 -.set CYDEV_CAN0_TX5_CMD, 0x4000a070 -.set CYDEV_CAN0_TX5_ID, 0x4000a074 -.set CYDEV_CAN0_TX5_DH, 0x4000a078 -.set CYDEV_CAN0_TX5_DL, 0x4000a07c -.set CYDEV_CAN0_TX6_BASE, 0x4000a080 -.set CYDEV_CAN0_TX6_SIZE, 0x00000010 -.set CYDEV_CAN0_TX6_CMD, 0x4000a080 -.set CYDEV_CAN0_TX6_ID, 0x4000a084 -.set CYDEV_CAN0_TX6_DH, 0x4000a088 -.set CYDEV_CAN0_TX6_DL, 0x4000a08c -.set CYDEV_CAN0_TX7_BASE, 0x4000a090 -.set CYDEV_CAN0_TX7_SIZE, 0x00000010 -.set CYDEV_CAN0_TX7_CMD, 0x4000a090 -.set CYDEV_CAN0_TX7_ID, 0x4000a094 -.set CYDEV_CAN0_TX7_DH, 0x4000a098 -.set CYDEV_CAN0_TX7_DL, 0x4000a09c -.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 -.set CYDEV_CAN0_RX0_SIZE, 0x00000020 -.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0 -.set CYDEV_CAN0_RX0_ID, 0x4000a0a4 -.set CYDEV_CAN0_RX0_DH, 0x4000a0a8 -.set CYDEV_CAN0_RX0_DL, 0x4000a0ac -.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0 -.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4 -.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8 -.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc -.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 -.set CYDEV_CAN0_RX1_SIZE, 0x00000020 -.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0 -.set CYDEV_CAN0_RX1_ID, 0x4000a0c4 -.set CYDEV_CAN0_RX1_DH, 0x4000a0c8 -.set CYDEV_CAN0_RX1_DL, 0x4000a0cc -.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0 -.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4 -.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8 -.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc -.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 -.set CYDEV_CAN0_RX2_SIZE, 0x00000020 -.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0 -.set CYDEV_CAN0_RX2_ID, 0x4000a0e4 -.set CYDEV_CAN0_RX2_DH, 0x4000a0e8 -.set CYDEV_CAN0_RX2_DL, 0x4000a0ec -.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0 -.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4 -.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8 -.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc -.set CYDEV_CAN0_RX3_BASE, 0x4000a100 -.set CYDEV_CAN0_RX3_SIZE, 0x00000020 -.set CYDEV_CAN0_RX3_CMD, 0x4000a100 -.set CYDEV_CAN0_RX3_ID, 0x4000a104 -.set CYDEV_CAN0_RX3_DH, 0x4000a108 -.set CYDEV_CAN0_RX3_DL, 0x4000a10c -.set CYDEV_CAN0_RX3_AMR, 0x4000a110 -.set CYDEV_CAN0_RX3_ACR, 0x4000a114 -.set CYDEV_CAN0_RX3_AMRD, 0x4000a118 -.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c -.set CYDEV_CAN0_RX4_BASE, 0x4000a120 -.set CYDEV_CAN0_RX4_SIZE, 0x00000020 -.set CYDEV_CAN0_RX4_CMD, 0x4000a120 -.set CYDEV_CAN0_RX4_ID, 0x4000a124 -.set CYDEV_CAN0_RX4_DH, 0x4000a128 -.set CYDEV_CAN0_RX4_DL, 0x4000a12c -.set CYDEV_CAN0_RX4_AMR, 0x4000a130 -.set CYDEV_CAN0_RX4_ACR, 0x4000a134 -.set CYDEV_CAN0_RX4_AMRD, 0x4000a138 -.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c -.set CYDEV_CAN0_RX5_BASE, 0x4000a140 -.set CYDEV_CAN0_RX5_SIZE, 0x00000020 -.set CYDEV_CAN0_RX5_CMD, 0x4000a140 -.set CYDEV_CAN0_RX5_ID, 0x4000a144 -.set CYDEV_CAN0_RX5_DH, 0x4000a148 -.set CYDEV_CAN0_RX5_DL, 0x4000a14c -.set CYDEV_CAN0_RX5_AMR, 0x4000a150 -.set CYDEV_CAN0_RX5_ACR, 0x4000a154 -.set CYDEV_CAN0_RX5_AMRD, 0x4000a158 -.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c -.set CYDEV_CAN0_RX6_BASE, 0x4000a160 -.set CYDEV_CAN0_RX6_SIZE, 0x00000020 -.set CYDEV_CAN0_RX6_CMD, 0x4000a160 -.set CYDEV_CAN0_RX6_ID, 0x4000a164 -.set CYDEV_CAN0_RX6_DH, 0x4000a168 -.set CYDEV_CAN0_RX6_DL, 0x4000a16c -.set CYDEV_CAN0_RX6_AMR, 0x4000a170 -.set CYDEV_CAN0_RX6_ACR, 0x4000a174 -.set CYDEV_CAN0_RX6_AMRD, 0x4000a178 -.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c -.set CYDEV_CAN0_RX7_BASE, 0x4000a180 -.set CYDEV_CAN0_RX7_SIZE, 0x00000020 -.set CYDEV_CAN0_RX7_CMD, 0x4000a180 -.set CYDEV_CAN0_RX7_ID, 0x4000a184 -.set CYDEV_CAN0_RX7_DH, 0x4000a188 -.set CYDEV_CAN0_RX7_DL, 0x4000a18c -.set CYDEV_CAN0_RX7_AMR, 0x4000a190 -.set CYDEV_CAN0_RX7_ACR, 0x4000a194 -.set CYDEV_CAN0_RX7_AMRD, 0x4000a198 -.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c -.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 -.set CYDEV_CAN0_RX8_SIZE, 0x00000020 -.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0 -.set CYDEV_CAN0_RX8_ID, 0x4000a1a4 -.set CYDEV_CAN0_RX8_DH, 0x4000a1a8 -.set CYDEV_CAN0_RX8_DL, 0x4000a1ac -.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0 -.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4 -.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8 -.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc -.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 -.set CYDEV_CAN0_RX9_SIZE, 0x00000020 -.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0 -.set CYDEV_CAN0_RX9_ID, 0x4000a1c4 -.set CYDEV_CAN0_RX9_DH, 0x4000a1c8 -.set CYDEV_CAN0_RX9_DL, 0x4000a1cc -.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0 -.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4 -.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8 -.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc -.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 -.set CYDEV_CAN0_RX10_SIZE, 0x00000020 -.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0 -.set CYDEV_CAN0_RX10_ID, 0x4000a1e4 -.set CYDEV_CAN0_RX10_DH, 0x4000a1e8 -.set CYDEV_CAN0_RX10_DL, 0x4000a1ec -.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0 -.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4 -.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8 -.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc -.set CYDEV_CAN0_RX11_BASE, 0x4000a200 -.set CYDEV_CAN0_RX11_SIZE, 0x00000020 -.set CYDEV_CAN0_RX11_CMD, 0x4000a200 -.set CYDEV_CAN0_RX11_ID, 0x4000a204 -.set CYDEV_CAN0_RX11_DH, 0x4000a208 -.set CYDEV_CAN0_RX11_DL, 0x4000a20c -.set CYDEV_CAN0_RX11_AMR, 0x4000a210 -.set CYDEV_CAN0_RX11_ACR, 0x4000a214 -.set CYDEV_CAN0_RX11_AMRD, 0x4000a218 -.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c -.set CYDEV_CAN0_RX12_BASE, 0x4000a220 -.set CYDEV_CAN0_RX12_SIZE, 0x00000020 -.set CYDEV_CAN0_RX12_CMD, 0x4000a220 -.set CYDEV_CAN0_RX12_ID, 0x4000a224 -.set CYDEV_CAN0_RX12_DH, 0x4000a228 -.set CYDEV_CAN0_RX12_DL, 0x4000a22c -.set CYDEV_CAN0_RX12_AMR, 0x4000a230 -.set CYDEV_CAN0_RX12_ACR, 0x4000a234 -.set CYDEV_CAN0_RX12_AMRD, 0x4000a238 -.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c -.set CYDEV_CAN0_RX13_BASE, 0x4000a240 -.set CYDEV_CAN0_RX13_SIZE, 0x00000020 -.set CYDEV_CAN0_RX13_CMD, 0x4000a240 -.set CYDEV_CAN0_RX13_ID, 0x4000a244 -.set CYDEV_CAN0_RX13_DH, 0x4000a248 -.set CYDEV_CAN0_RX13_DL, 0x4000a24c -.set CYDEV_CAN0_RX13_AMR, 0x4000a250 -.set CYDEV_CAN0_RX13_ACR, 0x4000a254 -.set CYDEV_CAN0_RX13_AMRD, 0x4000a258 -.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c -.set CYDEV_CAN0_RX14_BASE, 0x4000a260 -.set CYDEV_CAN0_RX14_SIZE, 0x00000020 -.set CYDEV_CAN0_RX14_CMD, 0x4000a260 -.set CYDEV_CAN0_RX14_ID, 0x4000a264 -.set CYDEV_CAN0_RX14_DH, 0x4000a268 -.set CYDEV_CAN0_RX14_DL, 0x4000a26c -.set CYDEV_CAN0_RX14_AMR, 0x4000a270 -.set CYDEV_CAN0_RX14_ACR, 0x4000a274 -.set CYDEV_CAN0_RX14_AMRD, 0x4000a278 -.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c -.set CYDEV_CAN0_RX15_BASE, 0x4000a280 -.set CYDEV_CAN0_RX15_SIZE, 0x00000020 -.set CYDEV_CAN0_RX15_CMD, 0x4000a280 -.set CYDEV_CAN0_RX15_ID, 0x4000a284 -.set CYDEV_CAN0_RX15_DH, 0x4000a288 -.set CYDEV_CAN0_RX15_DL, 0x4000a28c -.set CYDEV_CAN0_RX15_AMR, 0x4000a290 -.set CYDEV_CAN0_RX15_ACR, 0x4000a294 -.set CYDEV_CAN0_RX15_AMRD, 0x4000a298 -.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c -.set CYDEV_DFB0_BASE, 0x4000c000 -.set CYDEV_DFB0_SIZE, 0x000007b5 -.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 -.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 -.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 -.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 -.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 -.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 -.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 -.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 -.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 -.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 -.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 -.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 -.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 -.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 -.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 -.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 -.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 -.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 -.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 -.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 -.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 -.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 -.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 -.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 -.set CYDEV_DFB0_CR, 0x4000c780 -.set CYDEV_DFB0_SR, 0x4000c784 -.set CYDEV_DFB0_RAM_EN, 0x4000c788 -.set CYDEV_DFB0_RAM_DIR, 0x4000c78c -.set CYDEV_DFB0_SEMA, 0x4000c790 -.set CYDEV_DFB0_DSI_CTRL, 0x4000c794 -.set CYDEV_DFB0_INT_CTRL, 0x4000c798 -.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c -.set CYDEV_DFB0_STAGEA, 0x4000c7a0 -.set CYDEV_DFB0_STAGEAM, 0x4000c7a1 -.set CYDEV_DFB0_STAGEAH, 0x4000c7a2 -.set CYDEV_DFB0_STAGEB, 0x4000c7a4 -.set CYDEV_DFB0_STAGEBM, 0x4000c7a5 -.set CYDEV_DFB0_STAGEBH, 0x4000c7a6 -.set CYDEV_DFB0_HOLDA, 0x4000c7a8 -.set CYDEV_DFB0_HOLDAM, 0x4000c7a9 -.set CYDEV_DFB0_HOLDAH, 0x4000c7aa -.set CYDEV_DFB0_HOLDAS, 0x4000c7ab -.set CYDEV_DFB0_HOLDB, 0x4000c7ac -.set CYDEV_DFB0_HOLDBM, 0x4000c7ad -.set CYDEV_DFB0_HOLDBH, 0x4000c7ae -.set CYDEV_DFB0_HOLDBS, 0x4000c7af -.set CYDEV_DFB0_COHER, 0x4000c7b0 -.set CYDEV_DFB0_DALIGN, 0x4000c7b4 -.set CYDEV_UCFG_BASE, 0x40010000 -.set CYDEV_UCFG_SIZE, 0x00005040 -.set CYDEV_UCFG_B0_BASE, 0x40010000 -.set CYDEV_UCFG_B0_SIZE, 0x00000fef -.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 -.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 -.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c -.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c -.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028 -.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c -.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030 -.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032 -.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034 -.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036 -.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 -.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a -.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c -.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e -.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040 -.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041 -.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042 -.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043 -.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044 -.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045 -.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046 -.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047 -.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048 -.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049 -.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a -.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b -.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c -.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d -.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e -.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f -.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050 -.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051 -.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052 -.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053 -.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054 -.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055 -.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056 -.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057 -.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058 -.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059 -.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a -.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b -.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c -.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d -.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e -.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f -.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060 -.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062 -.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064 -.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066 -.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068 -.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a -.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c -.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e -.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 -.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c -.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c -.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8 -.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac -.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0 -.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2 -.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4 -.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6 -.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 -.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba -.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc -.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be -.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0 -.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1 -.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2 -.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3 -.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4 -.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5 -.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6 -.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7 -.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8 -.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9 -.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca -.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb -.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc -.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd -.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce -.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf -.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0 -.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1 -.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2 -.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3 -.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4 -.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5 -.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6 -.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7 -.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8 -.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9 -.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da -.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db -.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc -.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd -.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de -.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df -.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0 -.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2 -.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4 -.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6 -.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8 -.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea -.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec -.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee -.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 -.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 -.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 -.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c -.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c -.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228 -.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c -.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230 -.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232 -.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234 -.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236 -.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 -.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a -.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c -.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e -.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240 -.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241 -.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242 -.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243 -.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244 -.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245 -.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246 -.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247 -.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248 -.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249 -.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a -.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b -.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c -.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d -.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e -.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f -.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250 -.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251 -.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252 -.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253 -.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254 -.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255 -.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256 -.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257 -.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258 -.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259 -.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a -.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b -.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c -.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d -.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e -.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f -.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260 -.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262 -.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264 -.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266 -.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268 -.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a -.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c -.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e -.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 -.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c -.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c -.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8 -.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac -.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0 -.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2 -.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4 -.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6 -.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 -.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba -.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc -.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be -.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0 -.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1 -.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2 -.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3 -.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4 -.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5 -.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6 -.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7 -.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8 -.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9 -.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca -.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb -.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc -.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd -.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce -.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf -.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0 -.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1 -.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2 -.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3 -.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4 -.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5 -.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6 -.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7 -.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8 -.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9 -.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da -.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db -.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc -.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd -.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de -.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df -.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0 -.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2 -.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4 -.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6 -.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8 -.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea -.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec -.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee -.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 -.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 -.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 -.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c -.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c -.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428 -.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c -.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430 -.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432 -.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434 -.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436 -.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 -.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a -.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c -.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e -.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440 -.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441 -.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442 -.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443 -.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444 -.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445 -.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446 -.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447 -.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448 -.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449 -.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a -.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b -.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c -.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d -.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e -.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f -.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450 -.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451 -.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452 -.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453 -.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454 -.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455 -.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456 -.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457 -.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458 -.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459 -.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a -.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b -.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c -.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d -.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e -.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f -.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460 -.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462 -.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464 -.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466 -.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468 -.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a -.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c -.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e -.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 -.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c -.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c -.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8 -.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac -.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0 -.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2 -.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4 -.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6 -.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 -.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba -.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc -.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be -.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0 -.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1 -.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2 -.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3 -.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4 -.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5 -.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6 -.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7 -.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8 -.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9 -.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca -.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb -.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc -.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd -.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce -.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf -.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0 -.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1 -.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2 -.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3 -.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4 -.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5 -.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6 -.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7 -.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8 -.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9 -.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da -.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db -.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc -.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd -.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de -.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df -.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0 -.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2 -.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4 -.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6 -.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8 -.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea -.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec -.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee -.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 -.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 -.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 -.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c -.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c -.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628 -.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c -.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630 -.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632 -.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634 -.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636 -.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 -.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a -.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c -.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e -.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640 -.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641 -.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642 -.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643 -.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644 -.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645 -.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646 -.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647 -.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648 -.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649 -.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a -.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b -.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c -.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d -.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e -.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f -.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650 -.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651 -.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652 -.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653 -.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654 -.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655 -.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656 -.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657 -.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658 -.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659 -.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a -.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b -.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c -.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d -.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e -.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f -.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660 -.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662 -.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664 -.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666 -.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668 -.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a -.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c -.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e -.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 -.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c -.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c -.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8 -.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac -.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0 -.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2 -.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4 -.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6 -.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 -.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba -.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc -.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be -.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0 -.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1 -.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2 -.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3 -.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4 -.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5 -.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6 -.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7 -.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8 -.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9 -.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca -.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb -.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc -.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd -.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce -.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf -.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0 -.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1 -.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2 -.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3 -.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4 -.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5 -.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6 -.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7 -.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8 -.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9 -.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da -.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db -.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc -.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd -.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de -.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df -.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0 -.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2 -.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4 -.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6 -.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8 -.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea -.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec -.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee -.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 -.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 -.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 -.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c -.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c -.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828 -.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c -.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830 -.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832 -.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834 -.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836 -.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 -.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a -.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c -.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e -.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840 -.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841 -.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842 -.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843 -.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844 -.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845 -.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846 -.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847 -.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848 -.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849 -.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a -.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b -.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c -.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d -.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e -.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f -.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850 -.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851 -.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852 -.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853 -.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854 -.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855 -.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856 -.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857 -.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858 -.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859 -.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a -.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b -.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c -.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d -.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e -.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f -.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860 -.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862 -.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864 -.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866 -.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868 -.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a -.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c -.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e -.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 -.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c -.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c -.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8 -.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac -.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0 -.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2 -.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4 -.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6 -.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 -.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba -.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc -.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be -.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0 -.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1 -.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2 -.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3 -.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4 -.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5 -.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6 -.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7 -.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8 -.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9 -.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca -.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb -.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc -.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd -.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce -.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf -.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0 -.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1 -.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2 -.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3 -.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4 -.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5 -.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6 -.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7 -.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8 -.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9 -.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da -.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db -.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc -.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd -.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de -.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df -.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0 -.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2 -.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4 -.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6 -.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8 -.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea -.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec -.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee -.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 -.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 -.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 -.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c -.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c -.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28 -.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c -.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30 -.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32 -.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34 -.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36 -.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 -.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a -.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c -.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e -.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40 -.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41 -.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42 -.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43 -.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44 -.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45 -.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46 -.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47 -.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48 -.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49 -.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a -.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b -.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c -.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d -.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e -.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f -.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50 -.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51 -.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52 -.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53 -.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54 -.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55 -.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56 -.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57 -.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58 -.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59 -.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a -.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b -.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c -.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d -.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e -.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f -.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60 -.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62 -.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64 -.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66 -.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68 -.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a -.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c -.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e -.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 -.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c -.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c -.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8 -.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac -.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0 -.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2 -.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4 -.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6 -.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 -.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba -.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc -.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe -.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0 -.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1 -.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2 -.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3 -.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4 -.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5 -.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6 -.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7 -.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8 -.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9 -.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca -.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb -.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc -.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd -.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace -.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf -.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0 -.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1 -.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2 -.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3 -.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4 -.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5 -.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6 -.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7 -.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8 -.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9 -.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada -.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb -.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc -.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add -.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade -.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf -.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0 -.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2 -.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4 -.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6 -.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8 -.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea -.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec -.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee -.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 -.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 -.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 -.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c -.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c -.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28 -.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c -.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30 -.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32 -.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34 -.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36 -.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 -.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a -.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c -.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e -.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40 -.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41 -.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42 -.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43 -.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44 -.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45 -.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46 -.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47 -.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48 -.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49 -.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a -.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b -.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c -.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d -.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e -.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f -.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50 -.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51 -.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52 -.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53 -.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54 -.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55 -.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56 -.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57 -.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58 -.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59 -.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a -.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b -.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c -.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d -.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e -.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f -.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60 -.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62 -.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64 -.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66 -.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68 -.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a -.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c -.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e -.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 -.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c -.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c -.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8 -.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac -.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0 -.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2 -.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4 -.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6 -.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 -.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba -.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc -.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe -.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0 -.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1 -.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2 -.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3 -.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4 -.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5 -.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6 -.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7 -.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8 -.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9 -.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca -.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb -.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc -.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd -.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce -.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf -.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0 -.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1 -.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2 -.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3 -.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4 -.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5 -.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6 -.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7 -.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8 -.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9 -.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda -.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb -.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc -.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd -.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde -.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf -.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0 -.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2 -.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4 -.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6 -.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8 -.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea -.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec -.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee -.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 -.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 -.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 -.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c -.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c -.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28 -.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c -.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30 -.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32 -.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34 -.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36 -.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 -.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a -.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c -.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e -.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40 -.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41 -.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42 -.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43 -.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44 -.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45 -.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46 -.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47 -.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48 -.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49 -.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a -.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b -.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c -.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d -.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e -.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f -.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50 -.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51 -.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52 -.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53 -.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54 -.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55 -.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56 -.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57 -.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58 -.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59 -.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a -.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b -.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c -.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d -.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e -.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f -.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60 -.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62 -.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64 -.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66 -.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68 -.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a -.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c -.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e -.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 -.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c -.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c -.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8 -.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac -.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0 -.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2 -.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4 -.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6 -.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 -.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba -.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc -.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe -.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0 -.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1 -.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2 -.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3 -.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4 -.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5 -.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6 -.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7 -.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8 -.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9 -.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca -.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb -.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc -.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd -.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece -.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf -.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0 -.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1 -.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2 -.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3 -.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4 -.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5 -.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6 -.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7 -.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8 -.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9 -.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda -.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb -.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc -.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd -.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede -.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf -.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0 -.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2 -.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4 -.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6 -.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8 -.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea -.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec -.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee -.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 -.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_BASE, 0x40011000 -.set CYDEV_UCFG_B1_SIZE, 0x00000fef -.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 -.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 -.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c -.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c -.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428 -.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c -.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430 -.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432 -.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434 -.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436 -.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 -.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a -.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c -.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e -.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440 -.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441 -.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442 -.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443 -.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444 -.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445 -.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446 -.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447 -.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448 -.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449 -.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a -.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b -.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c -.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d -.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e -.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f -.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450 -.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451 -.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452 -.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453 -.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454 -.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455 -.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456 -.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457 -.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458 -.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459 -.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a -.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b -.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c -.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d -.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e -.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f -.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460 -.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462 -.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464 -.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466 -.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468 -.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a -.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c -.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e -.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 -.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c -.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c -.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8 -.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac -.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0 -.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2 -.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4 -.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6 -.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 -.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba -.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc -.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be -.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0 -.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1 -.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2 -.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3 -.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4 -.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5 -.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6 -.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7 -.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8 -.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9 -.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca -.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb -.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc -.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd -.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce -.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf -.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0 -.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1 -.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2 -.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3 -.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4 -.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5 -.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6 -.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7 -.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8 -.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9 -.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da -.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db -.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc -.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd -.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de -.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df -.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0 -.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2 -.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4 -.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6 -.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8 -.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea -.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec -.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee -.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 -.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 -.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 -.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c -.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c -.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628 -.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c -.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630 -.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632 -.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634 -.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636 -.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 -.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a -.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c -.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e -.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640 -.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641 -.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642 -.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643 -.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644 -.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645 -.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646 -.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647 -.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648 -.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649 -.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a -.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b -.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c -.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d -.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e -.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f -.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650 -.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651 -.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652 -.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653 -.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654 -.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655 -.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656 -.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657 -.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658 -.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659 -.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a -.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b -.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c -.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d -.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e -.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f -.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660 -.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662 -.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664 -.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666 -.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668 -.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a -.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c -.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e -.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 -.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c -.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c -.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8 -.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac -.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0 -.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2 -.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4 -.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6 -.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 -.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba -.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc -.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be -.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0 -.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1 -.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2 -.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3 -.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4 -.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5 -.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6 -.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7 -.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8 -.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9 -.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca -.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb -.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc -.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd -.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce -.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf -.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0 -.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1 -.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2 -.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3 -.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4 -.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5 -.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6 -.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7 -.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8 -.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9 -.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da -.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db -.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc -.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd -.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de -.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df -.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0 -.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2 -.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4 -.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6 -.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8 -.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea -.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec -.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee -.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 -.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 -.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 -.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c -.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c -.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828 -.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c -.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830 -.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832 -.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834 -.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836 -.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 -.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a -.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c -.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e -.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840 -.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841 -.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842 -.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843 -.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844 -.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845 -.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846 -.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847 -.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848 -.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849 -.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a -.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b -.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c -.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d -.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e -.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f -.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850 -.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851 -.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852 -.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853 -.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854 -.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855 -.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856 -.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857 -.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858 -.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859 -.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a -.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b -.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c -.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d -.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e -.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f -.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860 -.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862 -.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864 -.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866 -.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868 -.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a -.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c -.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e -.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 -.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c -.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c -.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8 -.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac -.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0 -.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2 -.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4 -.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6 -.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 -.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba -.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc -.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be -.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0 -.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1 -.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2 -.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3 -.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4 -.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5 -.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6 -.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7 -.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8 -.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9 -.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca -.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb -.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc -.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd -.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce -.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf -.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0 -.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1 -.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2 -.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3 -.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4 -.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5 -.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6 -.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7 -.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8 -.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9 -.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da -.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db -.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc -.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd -.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de -.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df -.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0 -.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2 -.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4 -.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6 -.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8 -.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea -.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec -.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee -.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 -.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 -.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 -.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c -.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c -.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28 -.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c -.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30 -.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32 -.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34 -.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36 -.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 -.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a -.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c -.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e -.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40 -.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41 -.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42 -.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43 -.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44 -.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45 -.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46 -.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47 -.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48 -.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49 -.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a -.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b -.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c -.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d -.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e -.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f -.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50 -.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51 -.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52 -.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53 -.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54 -.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55 -.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56 -.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57 -.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58 -.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59 -.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a -.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b -.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c -.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d -.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e -.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f -.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60 -.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62 -.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64 -.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66 -.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68 -.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a -.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c -.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e -.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 -.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c -.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c -.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8 -.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac -.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0 -.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2 -.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4 -.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6 -.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 -.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba -.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc -.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe -.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0 -.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1 -.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2 -.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3 -.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4 -.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5 -.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6 -.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7 -.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8 -.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9 -.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca -.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb -.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc -.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd -.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace -.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf -.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0 -.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1 -.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2 -.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3 -.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4 -.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5 -.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6 -.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7 -.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8 -.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9 -.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada -.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb -.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc -.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add -.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade -.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf -.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0 -.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2 -.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4 -.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6 -.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8 -.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea -.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec -.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee -.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 -.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI0_BASE, 0x40014000 -.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI1_BASE, 0x40014100 -.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI2_BASE, 0x40014200 -.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI3_BASE, 0x40014300 -.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI4_BASE, 0x40014400 -.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI5_BASE, 0x40014500 -.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI6_BASE, 0x40014600 -.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI7_BASE, 0x40014700 -.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI8_BASE, 0x40014800 -.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI9_BASE, 0x40014900 -.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 -.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 -.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef -.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 -.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 -.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000 -.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001 -.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002 -.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003 -.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007 -.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008 -.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009 -.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a -.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b -.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c -.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d -.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e -.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f -.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 -.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 -.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010 -.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011 -.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012 -.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013 -.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017 -.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018 -.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019 -.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a -.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b -.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c -.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d -.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e -.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f -.set CYDEV_IDMUX_BASE, 0x40015100 -.set CYDEV_IDMUX_SIZE, 0x00000016 -.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100 -.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101 -.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102 -.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103 -.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104 -.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105 -.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106 -.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107 -.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110 -.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111 -.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112 -.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113 -.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114 -.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115 -.set CYDEV_CACHERAM_BASE, 0x40030000 -.set CYDEV_CACHERAM_SIZE, 0x00000400 -.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000 -.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400 -.set CYDEV_SFR_BASE, 0x40050100 -.set CYDEV_SFR_SIZE, 0x000000fb -.set CYDEV_SFR_GPIO0, 0x40050180 -.set CYDEV_SFR_GPIRD0, 0x40050189 -.set CYDEV_SFR_GPIO0_SEL, 0x4005018a -.set CYDEV_SFR_GPIO1, 0x40050190 -.set CYDEV_SFR_GPIRD1, 0x40050191 -.set CYDEV_SFR_GPIO2, 0x40050198 -.set CYDEV_SFR_GPIRD2, 0x40050199 -.set CYDEV_SFR_GPIO2_SEL, 0x4005019a -.set CYDEV_SFR_GPIO1_SEL, 0x400501a2 -.set CYDEV_SFR_GPIO3, 0x400501b0 -.set CYDEV_SFR_GPIRD3, 0x400501b1 -.set CYDEV_SFR_GPIO3_SEL, 0x400501b2 -.set CYDEV_SFR_GPIO4, 0x400501c0 -.set CYDEV_SFR_GPIRD4, 0x400501c1 -.set CYDEV_SFR_GPIO4_SEL, 0x400501c2 -.set CYDEV_SFR_GPIO5, 0x400501c8 -.set CYDEV_SFR_GPIRD5, 0x400501c9 -.set CYDEV_SFR_GPIO5_SEL, 0x400501ca -.set CYDEV_SFR_GPIO6, 0x400501d8 -.set CYDEV_SFR_GPIRD6, 0x400501d9 -.set CYDEV_SFR_GPIO6_SEL, 0x400501da -.set CYDEV_SFR_GPIO12, 0x400501e8 -.set CYDEV_SFR_GPIRD12, 0x400501e9 -.set CYDEV_SFR_GPIO12_SEL, 0x400501f2 -.set CYDEV_SFR_GPIO15, 0x400501f8 -.set CYDEV_SFR_GPIRD15, 0x400501f9 -.set CYDEV_SFR_GPIO15_SEL, 0x400501fa -.set CYDEV_P3BA_BASE, 0x40050300 -.set CYDEV_P3BA_SIZE, 0x0000002b -.set CYDEV_P3BA_Y_START, 0x40050300 -.set CYDEV_P3BA_YROLL, 0x40050301 -.set CYDEV_P3BA_YCFG, 0x40050302 -.set CYDEV_P3BA_X_START1, 0x40050303 -.set CYDEV_P3BA_X_START2, 0x40050304 -.set CYDEV_P3BA_XROLL1, 0x40050305 -.set CYDEV_P3BA_XROLL2, 0x40050306 -.set CYDEV_P3BA_XINC, 0x40050307 -.set CYDEV_P3BA_XCFG, 0x40050308 -.set CYDEV_P3BA_OFFSETADDR1, 0x40050309 -.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a -.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b -.set CYDEV_P3BA_ABSADDR1, 0x4005030c -.set CYDEV_P3BA_ABSADDR2, 0x4005030d -.set CYDEV_P3BA_ABSADDR3, 0x4005030e -.set CYDEV_P3BA_ABSADDR4, 0x4005030f -.set CYDEV_P3BA_DATCFG1, 0x40050310 -.set CYDEV_P3BA_DATCFG2, 0x40050311 -.set CYDEV_P3BA_CMP_RSLT1, 0x40050314 -.set CYDEV_P3BA_CMP_RSLT2, 0x40050315 -.set CYDEV_P3BA_CMP_RSLT3, 0x40050316 -.set CYDEV_P3BA_CMP_RSLT4, 0x40050317 -.set CYDEV_P3BA_DATA_REG1, 0x40050318 -.set CYDEV_P3BA_DATA_REG2, 0x40050319 -.set CYDEV_P3BA_DATA_REG3, 0x4005031a -.set CYDEV_P3BA_DATA_REG4, 0x4005031b -.set CYDEV_P3BA_EXP_DATA1, 0x4005031c -.set CYDEV_P3BA_EXP_DATA2, 0x4005031d -.set CYDEV_P3BA_EXP_DATA3, 0x4005031e -.set CYDEV_P3BA_EXP_DATA4, 0x4005031f -.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320 -.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321 -.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322 -.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323 -.set CYDEV_P3BA_BIST_EN, 0x40050324 -.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325 -.set CYDEV_P3BA_SEQCFG1, 0x40050326 -.set CYDEV_P3BA_SEQCFG2, 0x40050327 -.set CYDEV_P3BA_Y_CURR, 0x40050328 -.set CYDEV_P3BA_X_CURR1, 0x40050329 -.set CYDEV_P3BA_X_CURR2, 0x4005032a -.set CYDEV_PANTHER_BASE, 0x40080000 -.set CYDEV_PANTHER_SIZE, 0x00000020 -.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000 -.set CYDEV_PANTHER_WAITPIPE, 0x40080004 -.set CYDEV_PANTHER_TRACE_CFG, 0x40080008 -.set CYDEV_PANTHER_DBG_CFG, 0x4008000c -.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018 -.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c -.set CYDEV_FLSECC_BASE, 0x48000000 -.set CYDEV_FLSECC_SIZE, 0x00008000 -.set CYDEV_FLSECC_DATA_MBASE, 0x48000000 -.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000 -.set CYDEV_FLSHID_BASE, 0x49000000 -.set CYDEV_FLSHID_SIZE, 0x00000200 -.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000 -.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080 -.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080 -.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080 -.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 -.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 -.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 -.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101 -.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 -.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 -.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 -.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 -.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 -.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107 -.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 -.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 -.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a -.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b -.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c -.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d -.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e -.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f -.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 -.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 -.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 -.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 -.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 -.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 -.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 -.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 -.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 -.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 -.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a -.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b -.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c -.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d -.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e -.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 -.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e -.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 -.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e -.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f -.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 -.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 -.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 -.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac -.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae -.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 -.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 -.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 -.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 -.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 -.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba -.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce -.set CYDEV_EXTMEM_BASE, 0x60000000 -.set CYDEV_EXTMEM_SIZE, 0x00800000 -.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000 -.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000 -.set CYDEV_ITM_BASE, 0xe0000000 -.set CYDEV_ITM_SIZE, 0x00001000 -.set CYDEV_ITM_TRACE_EN, 0xe0000e00 -.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40 -.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80 -.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0 -.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4 -.set CYDEV_ITM_PID4, 0xe0000fd0 -.set CYDEV_ITM_PID5, 0xe0000fd4 -.set CYDEV_ITM_PID6, 0xe0000fd8 -.set CYDEV_ITM_PID7, 0xe0000fdc -.set CYDEV_ITM_PID0, 0xe0000fe0 -.set CYDEV_ITM_PID1, 0xe0000fe4 -.set CYDEV_ITM_PID2, 0xe0000fe8 -.set CYDEV_ITM_PID3, 0xe0000fec -.set CYDEV_ITM_CID0, 0xe0000ff0 -.set CYDEV_ITM_CID1, 0xe0000ff4 -.set CYDEV_ITM_CID2, 0xe0000ff8 -.set CYDEV_ITM_CID3, 0xe0000ffc -.set CYDEV_DWT_BASE, 0xe0001000 -.set CYDEV_DWT_SIZE, 0x0000005c -.set CYDEV_DWT_CTRL, 0xe0001000 -.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004 -.set CYDEV_DWT_CPI_COUNT, 0xe0001008 -.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c -.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010 -.set CYDEV_DWT_LSU_COUNT, 0xe0001014 -.set CYDEV_DWT_FOLD_COUNT, 0xe0001018 -.set CYDEV_DWT_PC_SAMPLE, 0xe000101c -.set CYDEV_DWT_COMP_0, 0xe0001020 -.set CYDEV_DWT_MASK_0, 0xe0001024 -.set CYDEV_DWT_FUNCTION_0, 0xe0001028 -.set CYDEV_DWT_COMP_1, 0xe0001030 -.set CYDEV_DWT_MASK_1, 0xe0001034 -.set CYDEV_DWT_FUNCTION_1, 0xe0001038 -.set CYDEV_DWT_COMP_2, 0xe0001040 -.set CYDEV_DWT_MASK_2, 0xe0001044 -.set CYDEV_DWT_FUNCTION_2, 0xe0001048 -.set CYDEV_DWT_COMP_3, 0xe0001050 -.set CYDEV_DWT_MASK_3, 0xe0001054 -.set CYDEV_DWT_FUNCTION_3, 0xe0001058 -.set CYDEV_FPB_BASE, 0xe0002000 -.set CYDEV_FPB_SIZE, 0x00001000 -.set CYDEV_FPB_CTRL, 0xe0002000 -.set CYDEV_FPB_REMAP, 0xe0002004 -.set CYDEV_FPB_FP_COMP_0, 0xe0002008 -.set CYDEV_FPB_FP_COMP_1, 0xe000200c -.set CYDEV_FPB_FP_COMP_2, 0xe0002010 -.set CYDEV_FPB_FP_COMP_3, 0xe0002014 -.set CYDEV_FPB_FP_COMP_4, 0xe0002018 -.set CYDEV_FPB_FP_COMP_5, 0xe000201c -.set CYDEV_FPB_FP_COMP_6, 0xe0002020 -.set CYDEV_FPB_FP_COMP_7, 0xe0002024 -.set CYDEV_FPB_PID4, 0xe0002fd0 -.set CYDEV_FPB_PID5, 0xe0002fd4 -.set CYDEV_FPB_PID6, 0xe0002fd8 -.set CYDEV_FPB_PID7, 0xe0002fdc -.set CYDEV_FPB_PID0, 0xe0002fe0 -.set CYDEV_FPB_PID1, 0xe0002fe4 -.set CYDEV_FPB_PID2, 0xe0002fe8 -.set CYDEV_FPB_PID3, 0xe0002fec -.set CYDEV_FPB_CID0, 0xe0002ff0 -.set CYDEV_FPB_CID1, 0xe0002ff4 -.set CYDEV_FPB_CID2, 0xe0002ff8 -.set CYDEV_FPB_CID3, 0xe0002ffc -.set CYDEV_NVIC_BASE, 0xe000e000 -.set CYDEV_NVIC_SIZE, 0x00000d3c -.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004 -.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010 -.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014 -.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018 -.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c -.set CYDEV_NVIC_SETENA0, 0xe000e100 -.set CYDEV_NVIC_CLRENA0, 0xe000e180 -.set CYDEV_NVIC_SETPEND0, 0xe000e200 -.set CYDEV_NVIC_CLRPEND0, 0xe000e280 -.set CYDEV_NVIC_ACTIVE0, 0xe000e300 -.set CYDEV_NVIC_PRI_0, 0xe000e400 -.set CYDEV_NVIC_PRI_1, 0xe000e401 -.set CYDEV_NVIC_PRI_2, 0xe000e402 -.set CYDEV_NVIC_PRI_3, 0xe000e403 -.set CYDEV_NVIC_PRI_4, 0xe000e404 -.set CYDEV_NVIC_PRI_5, 0xe000e405 -.set CYDEV_NVIC_PRI_6, 0xe000e406 -.set CYDEV_NVIC_PRI_7, 0xe000e407 -.set CYDEV_NVIC_PRI_8, 0xe000e408 -.set CYDEV_NVIC_PRI_9, 0xe000e409 -.set CYDEV_NVIC_PRI_10, 0xe000e40a -.set CYDEV_NVIC_PRI_11, 0xe000e40b -.set CYDEV_NVIC_PRI_12, 0xe000e40c -.set CYDEV_NVIC_PRI_13, 0xe000e40d -.set CYDEV_NVIC_PRI_14, 0xe000e40e -.set CYDEV_NVIC_PRI_15, 0xe000e40f -.set CYDEV_NVIC_PRI_16, 0xe000e410 -.set CYDEV_NVIC_PRI_17, 0xe000e411 -.set CYDEV_NVIC_PRI_18, 0xe000e412 -.set CYDEV_NVIC_PRI_19, 0xe000e413 -.set CYDEV_NVIC_PRI_20, 0xe000e414 -.set CYDEV_NVIC_PRI_21, 0xe000e415 -.set CYDEV_NVIC_PRI_22, 0xe000e416 -.set CYDEV_NVIC_PRI_23, 0xe000e417 -.set CYDEV_NVIC_PRI_24, 0xe000e418 -.set CYDEV_NVIC_PRI_25, 0xe000e419 -.set CYDEV_NVIC_PRI_26, 0xe000e41a -.set CYDEV_NVIC_PRI_27, 0xe000e41b -.set CYDEV_NVIC_PRI_28, 0xe000e41c -.set CYDEV_NVIC_PRI_29, 0xe000e41d -.set CYDEV_NVIC_PRI_30, 0xe000e41e -.set CYDEV_NVIC_PRI_31, 0xe000e41f -.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00 -.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04 -.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08 -.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c -.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10 -.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14 -.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 -.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c -.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 -.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24 -.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 -.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29 -.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a -.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c -.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 -.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 -.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38 -.set CYDEV_CORE_DBG_BASE, 0xe000edf0 -.set CYDEV_CORE_DBG_SIZE, 0x00000010 -.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0 -.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4 -.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8 -.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc -.set CYDEV_TPIU_BASE, 0xe0040000 -.set CYDEV_TPIU_SIZE, 0x00001000 -.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 -.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 -.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 -.set CYDEV_TPIU_PROTOCOL, 0xe00400f0 -.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300 -.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304 -.set CYDEV_TPIU_TRIGGER, 0xe0040ee8 -.set CYDEV_TPIU_ITETMDATA, 0xe0040eec -.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0 -.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8 -.set CYDEV_TPIU_ITITMDATA, 0xe0040efc -.set CYDEV_TPIU_ITCTRL, 0xe0040f00 -.set CYDEV_TPIU_DEVID, 0xe0040fc8 -.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc -.set CYDEV_TPIU_PID4, 0xe0040fd0 -.set CYDEV_TPIU_PID5, 0xe0040fd4 -.set CYDEV_TPIU_PID6, 0xe0040fd8 -.set CYDEV_TPIU_PID7, 0xe0040fdc -.set CYDEV_TPIU_PID0, 0xe0040fe0 -.set CYDEV_TPIU_PID1, 0xe0040fe4 -.set CYDEV_TPIU_PID2, 0xe0040fe8 -.set CYDEV_TPIU_PID3, 0xe0040fec -.set CYDEV_TPIU_CID0, 0xe0040ff0 -.set CYDEV_TPIU_CID1, 0xe0040ff4 -.set CYDEV_TPIU_CID2, 0xe0040ff8 -.set CYDEV_TPIU_CID3, 0xe0040ffc -.set CYDEV_ETM_BASE, 0xe0041000 -.set CYDEV_ETM_SIZE, 0x00001000 -.set CYDEV_ETM_CTL, 0xe0041000 -.set CYDEV_ETM_CFG_CODE, 0xe0041004 -.set CYDEV_ETM_TRIG_EVENT, 0xe0041008 -.set CYDEV_ETM_STATUS, 0xe0041010 -.set CYDEV_ETM_SYS_CFG, 0xe0041014 -.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020 -.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024 -.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c -.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0 -.set CYDEV_ETM_ETM_ID, 0xe00411e4 -.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8 -.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 -.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200 -.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300 -.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304 -.set CYDEV_ETM_PDSR, 0xe0041314 -.set CYDEV_ETM_ITMISCIN, 0xe0041ee0 -.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8 -.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0 -.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8 -.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00 -.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0 -.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4 -.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0 -.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4 -.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8 -.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc -.set CYDEV_ETM_PID4, 0xe0041fd0 -.set CYDEV_ETM_PID5, 0xe0041fd4 -.set CYDEV_ETM_PID6, 0xe0041fd8 -.set CYDEV_ETM_PID7, 0xe0041fdc -.set CYDEV_ETM_PID0, 0xe0041fe0 -.set CYDEV_ETM_PID1, 0xe0041fe4 -.set CYDEV_ETM_PID2, 0xe0041fe8 -.set CYDEV_ETM_PID3, 0xe0041fec -.set CYDEV_ETM_CID0, 0xe0041ff0 -.set CYDEV_ETM_CID1, 0xe0041ff4 -.set CYDEV_ETM_CID2, 0xe0041ff8 -.set CYDEV_ETM_CID3, 0xe0041ffc -.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 -.set CYDEV_ROM_TABLE_SIZE, 0x00001000 -.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000 -.set CYDEV_ROM_TABLE_DWT, 0xe00ff004 -.set CYDEV_ROM_TABLE_FPB, 0xe00ff008 -.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c -.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010 -.set CYDEV_ROM_TABLE_ETM, 0xe00ff014 -.set CYDEV_ROM_TABLE_END, 0xe00ff018 -.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc -.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0 -.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4 -.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8 -.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc -.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0 -.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4 -.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8 -.set CYDEV_ROM_TABLE_PID3, 0xe00fffec -.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0 -.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4 -.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8 -.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc -.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE -.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE -.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 -.set CYDEV_FLS_ROW_SIZE, 0x00000100 -.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 -.set CYDEV_ECC_ROW_SIZE, 0x00000020 -.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 -.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 -.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE -.set CYCLK_LD_DISABLE, 0x00000004 -.set CYCLK_LD_SYNC_EN, 0x00000002 -.set CYCLK_LD_LOAD, 0x00000001 -.set CYCLK_PIPE, 0x00000080 -.set CYCLK_SSS, 0x00000040 -.set CYCLK_EARLY, 0x00000020 -.set CYCLK_DUTY, 0x00000010 -.set CYCLK_SYNC, 0x00000008 -.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 -.set CYCLK_SRC_SEL_SYNC_DIG, 0 -.set CYCLK_SRC_SEL_IMO, 1 -.set CYCLK_SRC_SEL_XTAL_MHZ, 2 -.set CYCLK_SRC_SEL_XTALM, 2 -.set CYCLK_SRC_SEL_ILO, 3 -.set CYCLK_SRC_SEL_PLL, 4 -.set CYCLK_SRC_SEL_XTAL_KHZ, 5 -.set CYCLK_SRC_SEL_XTALK, 5 -.set CYCLK_SRC_SEL_DSI_G, 6 -.set CYCLK_SRC_SEL_DSI_D, 7 -.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 -.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc deleted file mode 100755 index 3c24869..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicegnu_trm.inc +++ /dev/null @@ -1,5357 +0,0 @@ -/******************************************************************************* -* FILENAME: cydevicegnu_trm.inc -* -* PSoC Creator 3.0 Component Pack 7 -* -* DESCRIPTION: -* This file provides all of the address values for the entire PSoC device. -* This file is automatically generated by PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -.set CYDEV_FLASH_BASE, 0x00000000 -.set CYDEV_FLASH_SIZE, 0x00020000 -.set CYREG_FLASH_DATA_MBASE, 0x00000000 -.set CYREG_FLASH_DATA_MSIZE, 0x00020000 -.set CYDEV_SRAM_BASE, 0x1fffc000 -.set CYDEV_SRAM_SIZE, 0x00008000 -.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000 -.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000 -.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000 -.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000 -.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000 -.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000 -.set CYREG_SRAM_CODE_MBASE, 0x1fffc000 -.set CYREG_SRAM_CODE_MSIZE, 0x00004000 -.set CYREG_SRAM_DATA_MBASE, 0x20000000 -.set CYREG_SRAM_DATA_MSIZE, 0x00004000 -.set CYREG_SRAM_DATA16K_MBASE, 0x20001000 -.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000 -.set CYREG_SRAM_DATA32K_MBASE, 0x20002000 -.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000 -.set CYREG_SRAM_DATA64K_MBASE, 0x20004000 -.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000 -.set CYDEV_DMA_BASE, 0x20008000 -.set CYDEV_DMA_SIZE, 0x00008000 -.set CYREG_DMA_SRAM64K_MBASE, 0x20008000 -.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000 -.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000 -.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000 -.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000 -.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000 -.set CYREG_DMA_SRAM_MBASE, 0x2000f000 -.set CYREG_DMA_SRAM_MSIZE, 0x00001000 -.set CYDEV_CLKDIST_BASE, 0x40004000 -.set CYDEV_CLKDIST_SIZE, 0x00000110 -.set CYREG_CLKDIST_CR, 0x40004000 -.set CYREG_CLKDIST_LD, 0x40004001 -.set CYREG_CLKDIST_WRK0, 0x40004002 -.set CYREG_CLKDIST_WRK1, 0x40004003 -.set CYREG_CLKDIST_MSTR0, 0x40004004 -.set CYREG_CLKDIST_MSTR1, 0x40004005 -.set CYREG_CLKDIST_BCFG0, 0x40004006 -.set CYREG_CLKDIST_BCFG1, 0x40004007 -.set CYREG_CLKDIST_BCFG2, 0x40004008 -.set CYREG_CLKDIST_UCFG, 0x40004009 -.set CYREG_CLKDIST_DLY0, 0x4000400a -.set CYREG_CLKDIST_DLY1, 0x4000400b -.set CYREG_CLKDIST_DMASK, 0x40004010 -.set CYREG_CLKDIST_AMASK, 0x40004014 -.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 -.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080 -.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081 -.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082 -.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 -.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084 -.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085 -.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086 -.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 -.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088 -.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089 -.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a -.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c -.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c -.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d -.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e -.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 -.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090 -.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091 -.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092 -.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 -.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094 -.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095 -.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096 -.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 -.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098 -.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099 -.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a -.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c -.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 -.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c -.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d -.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e -.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 -.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 -.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100 -.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101 -.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102 -.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103 -.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 -.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 -.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104 -.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105 -.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106 -.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107 -.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 -.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 -.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108 -.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109 -.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a -.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b -.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c -.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 -.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c -.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d -.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e -.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f -.set CYDEV_FASTCLK_BASE, 0x40004200 -.set CYDEV_FASTCLK_SIZE, 0x00000026 -.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 -.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 -.set CYREG_FASTCLK_IMO_CR, 0x40004200 -.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 -.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 -.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210 -.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212 -.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213 -.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 -.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 -.set CYREG_FASTCLK_PLL_CFG0, 0x40004220 -.set CYREG_FASTCLK_PLL_CFG1, 0x40004221 -.set CYREG_FASTCLK_PLL_P, 0x40004222 -.set CYREG_FASTCLK_PLL_Q, 0x40004223 -.set CYREG_FASTCLK_PLL_SR, 0x40004225 -.set CYDEV_SLOWCLK_BASE, 0x40004300 -.set CYDEV_SLOWCLK_SIZE, 0x0000000b -.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 -.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 -.set CYREG_SLOWCLK_ILO_CR0, 0x40004300 -.set CYREG_SLOWCLK_ILO_CR1, 0x40004301 -.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 -.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 -.set CYREG_SLOWCLK_X32_CR, 0x40004308 -.set CYREG_SLOWCLK_X32_CFG, 0x40004309 -.set CYREG_SLOWCLK_X32_TST, 0x4000430a -.set CYDEV_BOOST_BASE, 0x40004320 -.set CYDEV_BOOST_SIZE, 0x00000007 -.set CYREG_BOOST_CR0, 0x40004320 -.set CYREG_BOOST_CR1, 0x40004321 -.set CYREG_BOOST_CR2, 0x40004322 -.set CYREG_BOOST_CR3, 0x40004323 -.set CYREG_BOOST_SR, 0x40004324 -.set CYREG_BOOST_CR4, 0x40004325 -.set CYREG_BOOST_SR2, 0x40004326 -.set CYDEV_PWRSYS_BASE, 0x40004330 -.set CYDEV_PWRSYS_SIZE, 0x00000002 -.set CYREG_PWRSYS_CR0, 0x40004330 -.set CYREG_PWRSYS_CR1, 0x40004331 -.set CYDEV_PM_BASE, 0x40004380 -.set CYDEV_PM_SIZE, 0x00000057 -.set CYREG_PM_TW_CFG0, 0x40004380 -.set CYREG_PM_TW_CFG1, 0x40004381 -.set CYREG_PM_TW_CFG2, 0x40004382 -.set CYREG_PM_WDT_CFG, 0x40004383 -.set CYREG_PM_WDT_CR, 0x40004384 -.set CYREG_PM_INT_SR, 0x40004390 -.set CYREG_PM_MODE_CFG0, 0x40004391 -.set CYREG_PM_MODE_CFG1, 0x40004392 -.set CYREG_PM_MODE_CSR, 0x40004393 -.set CYREG_PM_USB_CR0, 0x40004394 -.set CYREG_PM_WAKEUP_CFG0, 0x40004398 -.set CYREG_PM_WAKEUP_CFG1, 0x40004399 -.set CYREG_PM_WAKEUP_CFG2, 0x4000439a -.set CYDEV_PM_ACT_BASE, 0x400043a0 -.set CYDEV_PM_ACT_SIZE, 0x0000000e -.set CYREG_PM_ACT_CFG0, 0x400043a0 -.set CYREG_PM_ACT_CFG1, 0x400043a1 -.set CYREG_PM_ACT_CFG2, 0x400043a2 -.set CYREG_PM_ACT_CFG3, 0x400043a3 -.set CYREG_PM_ACT_CFG4, 0x400043a4 -.set CYREG_PM_ACT_CFG5, 0x400043a5 -.set CYREG_PM_ACT_CFG6, 0x400043a6 -.set CYREG_PM_ACT_CFG7, 0x400043a7 -.set CYREG_PM_ACT_CFG8, 0x400043a8 -.set CYREG_PM_ACT_CFG9, 0x400043a9 -.set CYREG_PM_ACT_CFG10, 0x400043aa -.set CYREG_PM_ACT_CFG11, 0x400043ab -.set CYREG_PM_ACT_CFG12, 0x400043ac -.set CYREG_PM_ACT_CFG13, 0x400043ad -.set CYDEV_PM_STBY_BASE, 0x400043b0 -.set CYDEV_PM_STBY_SIZE, 0x0000000e -.set CYREG_PM_STBY_CFG0, 0x400043b0 -.set CYREG_PM_STBY_CFG1, 0x400043b1 -.set CYREG_PM_STBY_CFG2, 0x400043b2 -.set CYREG_PM_STBY_CFG3, 0x400043b3 -.set CYREG_PM_STBY_CFG4, 0x400043b4 -.set CYREG_PM_STBY_CFG5, 0x400043b5 -.set CYREG_PM_STBY_CFG6, 0x400043b6 -.set CYREG_PM_STBY_CFG7, 0x400043b7 -.set CYREG_PM_STBY_CFG8, 0x400043b8 -.set CYREG_PM_STBY_CFG9, 0x400043b9 -.set CYREG_PM_STBY_CFG10, 0x400043ba -.set CYREG_PM_STBY_CFG11, 0x400043bb -.set CYREG_PM_STBY_CFG12, 0x400043bc -.set CYREG_PM_STBY_CFG13, 0x400043bd -.set CYDEV_PM_AVAIL_BASE, 0x400043c0 -.set CYDEV_PM_AVAIL_SIZE, 0x00000017 -.set CYREG_PM_AVAIL_CR0, 0x400043c0 -.set CYREG_PM_AVAIL_CR1, 0x400043c1 -.set CYREG_PM_AVAIL_CR2, 0x400043c2 -.set CYREG_PM_AVAIL_CR3, 0x400043c3 -.set CYREG_PM_AVAIL_CR4, 0x400043c4 -.set CYREG_PM_AVAIL_CR5, 0x400043c5 -.set CYREG_PM_AVAIL_CR6, 0x400043c6 -.set CYREG_PM_AVAIL_SR0, 0x400043d0 -.set CYREG_PM_AVAIL_SR1, 0x400043d1 -.set CYREG_PM_AVAIL_SR2, 0x400043d2 -.set CYREG_PM_AVAIL_SR3, 0x400043d3 -.set CYREG_PM_AVAIL_SR4, 0x400043d4 -.set CYREG_PM_AVAIL_SR5, 0x400043d5 -.set CYREG_PM_AVAIL_SR6, 0x400043d6 -.set CYDEV_PICU_BASE, 0x40004500 -.set CYDEV_PICU_SIZE, 0x000000b0 -.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 -.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 -.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 -.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 -.set CYREG_PICU0_INTTYPE0, 0x40004500 -.set CYREG_PICU0_INTTYPE1, 0x40004501 -.set CYREG_PICU0_INTTYPE2, 0x40004502 -.set CYREG_PICU0_INTTYPE3, 0x40004503 -.set CYREG_PICU0_INTTYPE4, 0x40004504 -.set CYREG_PICU0_INTTYPE5, 0x40004505 -.set CYREG_PICU0_INTTYPE6, 0x40004506 -.set CYREG_PICU0_INTTYPE7, 0x40004507 -.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 -.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 -.set CYREG_PICU1_INTTYPE0, 0x40004508 -.set CYREG_PICU1_INTTYPE1, 0x40004509 -.set CYREG_PICU1_INTTYPE2, 0x4000450a -.set CYREG_PICU1_INTTYPE3, 0x4000450b -.set CYREG_PICU1_INTTYPE4, 0x4000450c -.set CYREG_PICU1_INTTYPE5, 0x4000450d -.set CYREG_PICU1_INTTYPE6, 0x4000450e -.set CYREG_PICU1_INTTYPE7, 0x4000450f -.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 -.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 -.set CYREG_PICU2_INTTYPE0, 0x40004510 -.set CYREG_PICU2_INTTYPE1, 0x40004511 -.set CYREG_PICU2_INTTYPE2, 0x40004512 -.set CYREG_PICU2_INTTYPE3, 0x40004513 -.set CYREG_PICU2_INTTYPE4, 0x40004514 -.set CYREG_PICU2_INTTYPE5, 0x40004515 -.set CYREG_PICU2_INTTYPE6, 0x40004516 -.set CYREG_PICU2_INTTYPE7, 0x40004517 -.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 -.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 -.set CYREG_PICU3_INTTYPE0, 0x40004518 -.set CYREG_PICU3_INTTYPE1, 0x40004519 -.set CYREG_PICU3_INTTYPE2, 0x4000451a -.set CYREG_PICU3_INTTYPE3, 0x4000451b -.set CYREG_PICU3_INTTYPE4, 0x4000451c -.set CYREG_PICU3_INTTYPE5, 0x4000451d -.set CYREG_PICU3_INTTYPE6, 0x4000451e -.set CYREG_PICU3_INTTYPE7, 0x4000451f -.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 -.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 -.set CYREG_PICU4_INTTYPE0, 0x40004520 -.set CYREG_PICU4_INTTYPE1, 0x40004521 -.set CYREG_PICU4_INTTYPE2, 0x40004522 -.set CYREG_PICU4_INTTYPE3, 0x40004523 -.set CYREG_PICU4_INTTYPE4, 0x40004524 -.set CYREG_PICU4_INTTYPE5, 0x40004525 -.set CYREG_PICU4_INTTYPE6, 0x40004526 -.set CYREG_PICU4_INTTYPE7, 0x40004527 -.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 -.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 -.set CYREG_PICU5_INTTYPE0, 0x40004528 -.set CYREG_PICU5_INTTYPE1, 0x40004529 -.set CYREG_PICU5_INTTYPE2, 0x4000452a -.set CYREG_PICU5_INTTYPE3, 0x4000452b -.set CYREG_PICU5_INTTYPE4, 0x4000452c -.set CYREG_PICU5_INTTYPE5, 0x4000452d -.set CYREG_PICU5_INTTYPE6, 0x4000452e -.set CYREG_PICU5_INTTYPE7, 0x4000452f -.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 -.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 -.set CYREG_PICU6_INTTYPE0, 0x40004530 -.set CYREG_PICU6_INTTYPE1, 0x40004531 -.set CYREG_PICU6_INTTYPE2, 0x40004532 -.set CYREG_PICU6_INTTYPE3, 0x40004533 -.set CYREG_PICU6_INTTYPE4, 0x40004534 -.set CYREG_PICU6_INTTYPE5, 0x40004535 -.set CYREG_PICU6_INTTYPE6, 0x40004536 -.set CYREG_PICU6_INTTYPE7, 0x40004537 -.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 -.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 -.set CYREG_PICU12_INTTYPE0, 0x40004560 -.set CYREG_PICU12_INTTYPE1, 0x40004561 -.set CYREG_PICU12_INTTYPE2, 0x40004562 -.set CYREG_PICU12_INTTYPE3, 0x40004563 -.set CYREG_PICU12_INTTYPE4, 0x40004564 -.set CYREG_PICU12_INTTYPE5, 0x40004565 -.set CYREG_PICU12_INTTYPE6, 0x40004566 -.set CYREG_PICU12_INTTYPE7, 0x40004567 -.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 -.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 -.set CYREG_PICU15_INTTYPE0, 0x40004578 -.set CYREG_PICU15_INTTYPE1, 0x40004579 -.set CYREG_PICU15_INTTYPE2, 0x4000457a -.set CYREG_PICU15_INTTYPE3, 0x4000457b -.set CYREG_PICU15_INTTYPE4, 0x4000457c -.set CYREG_PICU15_INTTYPE5, 0x4000457d -.set CYREG_PICU15_INTTYPE6, 0x4000457e -.set CYREG_PICU15_INTTYPE7, 0x4000457f -.set CYDEV_PICU_STAT_BASE, 0x40004580 -.set CYDEV_PICU_STAT_SIZE, 0x00000010 -.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 -.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 -.set CYREG_PICU0_INTSTAT, 0x40004580 -.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 -.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 -.set CYREG_PICU1_INTSTAT, 0x40004581 -.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 -.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 -.set CYREG_PICU2_INTSTAT, 0x40004582 -.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 -.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 -.set CYREG_PICU3_INTSTAT, 0x40004583 -.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 -.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 -.set CYREG_PICU4_INTSTAT, 0x40004584 -.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 -.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 -.set CYREG_PICU5_INTSTAT, 0x40004585 -.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 -.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 -.set CYREG_PICU6_INTSTAT, 0x40004586 -.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c -.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 -.set CYREG_PICU12_INTSTAT, 0x4000458c -.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f -.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 -.set CYREG_PICU15_INTSTAT, 0x4000458f -.set CYDEV_PICU_SNAP_BASE, 0x40004590 -.set CYDEV_PICU_SNAP_SIZE, 0x00000010 -.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 -.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 -.set CYREG_PICU0_SNAP, 0x40004590 -.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 -.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 -.set CYREG_PICU1_SNAP, 0x40004591 -.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 -.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 -.set CYREG_PICU2_SNAP, 0x40004592 -.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 -.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 -.set CYREG_PICU3_SNAP, 0x40004593 -.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 -.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 -.set CYREG_PICU4_SNAP, 0x40004594 -.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 -.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 -.set CYREG_PICU5_SNAP, 0x40004595 -.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 -.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 -.set CYREG_PICU6_SNAP, 0x40004596 -.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c -.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 -.set CYREG_PICU12_SNAP, 0x4000459c -.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f -.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 -.set CYREG_PICU_15_SNAP_15, 0x4000459f -.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 -.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 -.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 -.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 -.set CYREG_PICU0_DISABLE_COR, 0x400045a0 -.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 -.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 -.set CYREG_PICU1_DISABLE_COR, 0x400045a1 -.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 -.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 -.set CYREG_PICU2_DISABLE_COR, 0x400045a2 -.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 -.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 -.set CYREG_PICU3_DISABLE_COR, 0x400045a3 -.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 -.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 -.set CYREG_PICU4_DISABLE_COR, 0x400045a4 -.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 -.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 -.set CYREG_PICU5_DISABLE_COR, 0x400045a5 -.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 -.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 -.set CYREG_PICU6_DISABLE_COR, 0x400045a6 -.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac -.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 -.set CYREG_PICU12_DISABLE_COR, 0x400045ac -.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af -.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 -.set CYREG_PICU15_DISABLE_COR, 0x400045af -.set CYDEV_MFGCFG_BASE, 0x40004600 -.set CYDEV_MFGCFG_SIZE, 0x000000ed -.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 -.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 -.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 -.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 -.set CYREG_DAC0_TR, 0x40004608 -.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 -.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 -.set CYREG_DAC1_TR, 0x40004609 -.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a -.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 -.set CYREG_DAC2_TR, 0x4000460a -.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b -.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 -.set CYREG_DAC3_TR, 0x4000460b -.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 -.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 -.set CYREG_NPUMP_DSM_TR0, 0x40004610 -.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 -.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 -.set CYREG_NPUMP_SC_TR0, 0x40004611 -.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 -.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 -.set CYREG_NPUMP_OPAMP_TR0, 0x40004612 -.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 -.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 -.set CYREG_SAR0_TR0, 0x40004614 -.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 -.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 -.set CYREG_SAR1_TR0, 0x40004616 -.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 -.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 -.set CYREG_OPAMP0_TR0, 0x40004620 -.set CYREG_OPAMP0_TR1, 0x40004621 -.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 -.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 -.set CYREG_OPAMP1_TR0, 0x40004622 -.set CYREG_OPAMP1_TR1, 0x40004623 -.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 -.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 -.set CYREG_OPAMP2_TR0, 0x40004624 -.set CYREG_OPAMP2_TR1, 0x40004625 -.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 -.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 -.set CYREG_OPAMP3_TR0, 0x40004626 -.set CYREG_OPAMP3_TR1, 0x40004627 -.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 -.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 -.set CYREG_CMP0_TR0, 0x40004630 -.set CYREG_CMP0_TR1, 0x40004631 -.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 -.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 -.set CYREG_CMP1_TR0, 0x40004632 -.set CYREG_CMP1_TR1, 0x40004633 -.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 -.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 -.set CYREG_CMP2_TR0, 0x40004634 -.set CYREG_CMP2_TR1, 0x40004635 -.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 -.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 -.set CYREG_CMP3_TR0, 0x40004636 -.set CYREG_CMP3_TR1, 0x40004637 -.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 -.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b -.set CYREG_PWRSYS_HIB_TR0, 0x40004680 -.set CYREG_PWRSYS_HIB_TR1, 0x40004681 -.set CYREG_PWRSYS_I2C_TR, 0x40004682 -.set CYREG_PWRSYS_SLP_TR, 0x40004683 -.set CYREG_PWRSYS_BUZZ_TR, 0x40004684 -.set CYREG_PWRSYS_WAKE_TR0, 0x40004685 -.set CYREG_PWRSYS_WAKE_TR1, 0x40004686 -.set CYREG_PWRSYS_BREF_TR, 0x40004687 -.set CYREG_PWRSYS_BG_TR, 0x40004688 -.set CYREG_PWRSYS_WAKE_TR2, 0x40004689 -.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a -.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 -.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 -.set CYREG_ILO_TR0, 0x40004690 -.set CYREG_ILO_TR1, 0x40004691 -.set CYDEV_MFGCFG_X32_BASE, 0x40004698 -.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 -.set CYREG_X32_TR, 0x40004698 -.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 -.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 -.set CYREG_IMO_TR0, 0x400046a0 -.set CYREG_IMO_TR1, 0x400046a1 -.set CYREG_IMO_GAIN, 0x400046a2 -.set CYREG_IMO_C36M, 0x400046a3 -.set CYREG_IMO_TR2, 0x400046a4 -.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 -.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 -.set CYREG_XMHZ_TR, 0x400046a8 -.set CYREG_MFGCFG_DLY, 0x400046c0 -.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 -.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d -.set CYREG_MLOGIC_DMPSTR, 0x400046e2 -.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 -.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 -.set CYREG_MLOGIC_SEG_CR, 0x400046e4 -.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5 -.set CYREG_MLOGIC_DEBUG, 0x400046e8 -.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea -.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 -.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea -.set CYREG_MLOGIC_REV_ID, 0x400046ec -.set CYDEV_RESET_BASE, 0x400046f0 -.set CYDEV_RESET_SIZE, 0x0000000f -.set CYREG_RESET_IPOR_CR0, 0x400046f0 -.set CYREG_RESET_IPOR_CR1, 0x400046f1 -.set CYREG_RESET_IPOR_CR2, 0x400046f2 -.set CYREG_RESET_IPOR_CR3, 0x400046f3 -.set CYREG_RESET_CR0, 0x400046f4 -.set CYREG_RESET_CR1, 0x400046f5 -.set CYREG_RESET_CR2, 0x400046f6 -.set CYREG_RESET_CR3, 0x400046f7 -.set CYREG_RESET_CR4, 0x400046f8 -.set CYREG_RESET_CR5, 0x400046f9 -.set CYREG_RESET_SR0, 0x400046fa -.set CYREG_RESET_SR1, 0x400046fb -.set CYREG_RESET_SR2, 0x400046fc -.set CYREG_RESET_SR3, 0x400046fd -.set CYREG_RESET_TR, 0x400046fe -.set CYDEV_SPC_BASE, 0x40004700 -.set CYDEV_SPC_SIZE, 0x00000100 -.set CYREG_SPC_FM_EE_CR, 0x40004700 -.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701 -.set CYREG_SPC_EE_SCR, 0x40004702 -.set CYREG_SPC_EE_ERR, 0x40004703 -.set CYREG_SPC_CPU_DATA, 0x40004720 -.set CYREG_SPC_DMA_DATA, 0x40004721 -.set CYREG_SPC_SR, 0x40004722 -.set CYREG_SPC_CR, 0x40004723 -.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 -.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 -.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 -.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 -.set CYDEV_CACHE_BASE, 0x40004800 -.set CYDEV_CACHE_SIZE, 0x0000009c -.set CYREG_CACHE_CC_CTL, 0x40004800 -.set CYREG_CACHE_ECC_CORR, 0x40004880 -.set CYREG_CACHE_ECC_ERR, 0x40004888 -.set CYREG_CACHE_FLASH_ERR, 0x40004890 -.set CYREG_CACHE_HITMISS, 0x40004898 -.set CYDEV_I2C_BASE, 0x40004900 -.set CYDEV_I2C_SIZE, 0x000000e1 -.set CYREG_I2C_XCFG, 0x400049c8 -.set CYREG_I2C_ADR, 0x400049ca -.set CYREG_I2C_CFG, 0x400049d6 -.set CYREG_I2C_CSR, 0x400049d7 -.set CYREG_I2C_D, 0x400049d8 -.set CYREG_I2C_MCSR, 0x400049d9 -.set CYREG_I2C_CLK_DIV1, 0x400049db -.set CYREG_I2C_CLK_DIV2, 0x400049dc -.set CYREG_I2C_TMOUT_CSR, 0x400049dd -.set CYREG_I2C_TMOUT_SR, 0x400049de -.set CYREG_I2C_TMOUT_CFG0, 0x400049df -.set CYREG_I2C_TMOUT_CFG1, 0x400049e0 -.set CYDEV_DEC_BASE, 0x40004e00 -.set CYDEV_DEC_SIZE, 0x00000015 -.set CYREG_DEC_CR, 0x40004e00 -.set CYREG_DEC_SR, 0x40004e01 -.set CYREG_DEC_SHIFT1, 0x40004e02 -.set CYREG_DEC_SHIFT2, 0x40004e03 -.set CYREG_DEC_DR2, 0x40004e04 -.set CYREG_DEC_DR2H, 0x40004e05 -.set CYREG_DEC_DR1, 0x40004e06 -.set CYREG_DEC_OCOR, 0x40004e08 -.set CYREG_DEC_OCORM, 0x40004e09 -.set CYREG_DEC_OCORH, 0x40004e0a -.set CYREG_DEC_GCOR, 0x40004e0c -.set CYREG_DEC_GCORH, 0x40004e0d -.set CYREG_DEC_GVAL, 0x40004e0e -.set CYREG_DEC_OUTSAMP, 0x40004e10 -.set CYREG_DEC_OUTSAMPM, 0x40004e11 -.set CYREG_DEC_OUTSAMPH, 0x40004e12 -.set CYREG_DEC_OUTSAMPS, 0x40004e13 -.set CYREG_DEC_COHER, 0x40004e14 -.set CYDEV_TMR0_BASE, 0x40004f00 -.set CYDEV_TMR0_SIZE, 0x0000000c -.set CYREG_TMR0_CFG0, 0x40004f00 -.set CYREG_TMR0_CFG1, 0x40004f01 -.set CYREG_TMR0_CFG2, 0x40004f02 -.set CYREG_TMR0_SR0, 0x40004f03 -.set CYREG_TMR0_PER0, 0x40004f04 -.set CYREG_TMR0_PER1, 0x40004f05 -.set CYREG_TMR0_CNT_CMP0, 0x40004f06 -.set CYREG_TMR0_CNT_CMP1, 0x40004f07 -.set CYREG_TMR0_CAP0, 0x40004f08 -.set CYREG_TMR0_CAP1, 0x40004f09 -.set CYREG_TMR0_RT0, 0x40004f0a -.set CYREG_TMR0_RT1, 0x40004f0b -.set CYDEV_TMR1_BASE, 0x40004f0c -.set CYDEV_TMR1_SIZE, 0x0000000c -.set CYREG_TMR1_CFG0, 0x40004f0c -.set CYREG_TMR1_CFG1, 0x40004f0d -.set CYREG_TMR1_CFG2, 0x40004f0e -.set CYREG_TMR1_SR0, 0x40004f0f -.set CYREG_TMR1_PER0, 0x40004f10 -.set CYREG_TMR1_PER1, 0x40004f11 -.set CYREG_TMR1_CNT_CMP0, 0x40004f12 -.set CYREG_TMR1_CNT_CMP1, 0x40004f13 -.set CYREG_TMR1_CAP0, 0x40004f14 -.set CYREG_TMR1_CAP1, 0x40004f15 -.set CYREG_TMR1_RT0, 0x40004f16 -.set CYREG_TMR1_RT1, 0x40004f17 -.set CYDEV_TMR2_BASE, 0x40004f18 -.set CYDEV_TMR2_SIZE, 0x0000000c -.set CYREG_TMR2_CFG0, 0x40004f18 -.set CYREG_TMR2_CFG1, 0x40004f19 -.set CYREG_TMR2_CFG2, 0x40004f1a -.set CYREG_TMR2_SR0, 0x40004f1b -.set CYREG_TMR2_PER0, 0x40004f1c -.set CYREG_TMR2_PER1, 0x40004f1d -.set CYREG_TMR2_CNT_CMP0, 0x40004f1e -.set CYREG_TMR2_CNT_CMP1, 0x40004f1f -.set CYREG_TMR2_CAP0, 0x40004f20 -.set CYREG_TMR2_CAP1, 0x40004f21 -.set CYREG_TMR2_RT0, 0x40004f22 -.set CYREG_TMR2_RT1, 0x40004f23 -.set CYDEV_TMR3_BASE, 0x40004f24 -.set CYDEV_TMR3_SIZE, 0x0000000c -.set CYREG_TMR3_CFG0, 0x40004f24 -.set CYREG_TMR3_CFG1, 0x40004f25 -.set CYREG_TMR3_CFG2, 0x40004f26 -.set CYREG_TMR3_SR0, 0x40004f27 -.set CYREG_TMR3_PER0, 0x40004f28 -.set CYREG_TMR3_PER1, 0x40004f29 -.set CYREG_TMR3_CNT_CMP0, 0x40004f2a -.set CYREG_TMR3_CNT_CMP1, 0x40004f2b -.set CYREG_TMR3_CAP0, 0x40004f2c -.set CYREG_TMR3_CAP1, 0x40004f2d -.set CYREG_TMR3_RT0, 0x40004f2e -.set CYREG_TMR3_RT1, 0x40004f2f -.set CYDEV_IO_BASE, 0x40005000 -.set CYDEV_IO_SIZE, 0x00000200 -.set CYDEV_IO_PC_BASE, 0x40005000 -.set CYDEV_IO_PC_SIZE, 0x00000080 -.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 -.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 -.set CYREG_PRT0_PC0, 0x40005000 -.set CYREG_PRT0_PC1, 0x40005001 -.set CYREG_PRT0_PC2, 0x40005002 -.set CYREG_PRT0_PC3, 0x40005003 -.set CYREG_PRT0_PC4, 0x40005004 -.set CYREG_PRT0_PC5, 0x40005005 -.set CYREG_PRT0_PC6, 0x40005006 -.set CYREG_PRT0_PC7, 0x40005007 -.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 -.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 -.set CYREG_PRT1_PC0, 0x40005008 -.set CYREG_PRT1_PC1, 0x40005009 -.set CYREG_PRT1_PC2, 0x4000500a -.set CYREG_PRT1_PC3, 0x4000500b -.set CYREG_PRT1_PC4, 0x4000500c -.set CYREG_PRT1_PC5, 0x4000500d -.set CYREG_PRT1_PC6, 0x4000500e -.set CYREG_PRT1_PC7, 0x4000500f -.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 -.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 -.set CYREG_PRT2_PC0, 0x40005010 -.set CYREG_PRT2_PC1, 0x40005011 -.set CYREG_PRT2_PC2, 0x40005012 -.set CYREG_PRT2_PC3, 0x40005013 -.set CYREG_PRT2_PC4, 0x40005014 -.set CYREG_PRT2_PC5, 0x40005015 -.set CYREG_PRT2_PC6, 0x40005016 -.set CYREG_PRT2_PC7, 0x40005017 -.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 -.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 -.set CYREG_PRT3_PC0, 0x40005018 -.set CYREG_PRT3_PC1, 0x40005019 -.set CYREG_PRT3_PC2, 0x4000501a -.set CYREG_PRT3_PC3, 0x4000501b -.set CYREG_PRT3_PC4, 0x4000501c -.set CYREG_PRT3_PC5, 0x4000501d -.set CYREG_PRT3_PC6, 0x4000501e -.set CYREG_PRT3_PC7, 0x4000501f -.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 -.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 -.set CYREG_PRT4_PC0, 0x40005020 -.set CYREG_PRT4_PC1, 0x40005021 -.set CYREG_PRT4_PC2, 0x40005022 -.set CYREG_PRT4_PC3, 0x40005023 -.set CYREG_PRT4_PC4, 0x40005024 -.set CYREG_PRT4_PC5, 0x40005025 -.set CYREG_PRT4_PC6, 0x40005026 -.set CYREG_PRT4_PC7, 0x40005027 -.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 -.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 -.set CYREG_PRT5_PC0, 0x40005028 -.set CYREG_PRT5_PC1, 0x40005029 -.set CYREG_PRT5_PC2, 0x4000502a -.set CYREG_PRT5_PC3, 0x4000502b -.set CYREG_PRT5_PC4, 0x4000502c -.set CYREG_PRT5_PC5, 0x4000502d -.set CYREG_PRT5_PC6, 0x4000502e -.set CYREG_PRT5_PC7, 0x4000502f -.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 -.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 -.set CYREG_PRT6_PC0, 0x40005030 -.set CYREG_PRT6_PC1, 0x40005031 -.set CYREG_PRT6_PC2, 0x40005032 -.set CYREG_PRT6_PC3, 0x40005033 -.set CYREG_PRT6_PC4, 0x40005034 -.set CYREG_PRT6_PC5, 0x40005035 -.set CYREG_PRT6_PC6, 0x40005036 -.set CYREG_PRT6_PC7, 0x40005037 -.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 -.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 -.set CYREG_PRT12_PC0, 0x40005060 -.set CYREG_PRT12_PC1, 0x40005061 -.set CYREG_PRT12_PC2, 0x40005062 -.set CYREG_PRT12_PC3, 0x40005063 -.set CYREG_PRT12_PC4, 0x40005064 -.set CYREG_PRT12_PC5, 0x40005065 -.set CYREG_PRT12_PC6, 0x40005066 -.set CYREG_PRT12_PC7, 0x40005067 -.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 -.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 -.set CYREG_IO_PC_PRT15_PC0, 0x40005078 -.set CYREG_IO_PC_PRT15_PC1, 0x40005079 -.set CYREG_IO_PC_PRT15_PC2, 0x4000507a -.set CYREG_IO_PC_PRT15_PC3, 0x4000507b -.set CYREG_IO_PC_PRT15_PC4, 0x4000507c -.set CYREG_IO_PC_PRT15_PC5, 0x4000507d -.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e -.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 -.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e -.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f -.set CYDEV_IO_DR_BASE, 0x40005080 -.set CYDEV_IO_DR_SIZE, 0x00000010 -.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 -.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 -.set CYREG_PRT0_DR_ALIAS, 0x40005080 -.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 -.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 -.set CYREG_PRT1_DR_ALIAS, 0x40005081 -.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 -.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 -.set CYREG_PRT2_DR_ALIAS, 0x40005082 -.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 -.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 -.set CYREG_PRT3_DR_ALIAS, 0x40005083 -.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 -.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 -.set CYREG_PRT4_DR_ALIAS, 0x40005084 -.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 -.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 -.set CYREG_PRT5_DR_ALIAS, 0x40005085 -.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 -.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 -.set CYREG_PRT6_DR_ALIAS, 0x40005086 -.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c -.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 -.set CYREG_PRT12_DR_ALIAS, 0x4000508c -.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f -.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 -.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f -.set CYDEV_IO_PS_BASE, 0x40005090 -.set CYDEV_IO_PS_SIZE, 0x00000010 -.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 -.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 -.set CYREG_PRT0_PS_ALIAS, 0x40005090 -.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 -.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 -.set CYREG_PRT1_PS_ALIAS, 0x40005091 -.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 -.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 -.set CYREG_PRT2_PS_ALIAS, 0x40005092 -.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 -.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 -.set CYREG_PRT3_PS_ALIAS, 0x40005093 -.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 -.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 -.set CYREG_PRT4_PS_ALIAS, 0x40005094 -.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 -.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 -.set CYREG_PRT5_PS_ALIAS, 0x40005095 -.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 -.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 -.set CYREG_PRT6_PS_ALIAS, 0x40005096 -.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c -.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 -.set CYREG_PRT12_PS_ALIAS, 0x4000509c -.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f -.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 -.set CYREG_PRT15_PS15_ALIAS, 0x4000509f -.set CYDEV_IO_PRT_BASE, 0x40005100 -.set CYDEV_IO_PRT_SIZE, 0x00000100 -.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 -.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 -.set CYREG_PRT0_DR, 0x40005100 -.set CYREG_PRT0_PS, 0x40005101 -.set CYREG_PRT0_DM0, 0x40005102 -.set CYREG_PRT0_DM1, 0x40005103 -.set CYREG_PRT0_DM2, 0x40005104 -.set CYREG_PRT0_SLW, 0x40005105 -.set CYREG_PRT0_BYP, 0x40005106 -.set CYREG_PRT0_BIE, 0x40005107 -.set CYREG_PRT0_INP_DIS, 0x40005108 -.set CYREG_PRT0_CTL, 0x40005109 -.set CYREG_PRT0_PRT, 0x4000510a -.set CYREG_PRT0_BIT_MASK, 0x4000510b -.set CYREG_PRT0_AMUX, 0x4000510c -.set CYREG_PRT0_AG, 0x4000510d -.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e -.set CYREG_PRT0_LCD_EN, 0x4000510f -.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 -.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 -.set CYREG_PRT1_DR, 0x40005110 -.set CYREG_PRT1_PS, 0x40005111 -.set CYREG_PRT1_DM0, 0x40005112 -.set CYREG_PRT1_DM1, 0x40005113 -.set CYREG_PRT1_DM2, 0x40005114 -.set CYREG_PRT1_SLW, 0x40005115 -.set CYREG_PRT1_BYP, 0x40005116 -.set CYREG_PRT1_BIE, 0x40005117 -.set CYREG_PRT1_INP_DIS, 0x40005118 -.set CYREG_PRT1_CTL, 0x40005119 -.set CYREG_PRT1_PRT, 0x4000511a -.set CYREG_PRT1_BIT_MASK, 0x4000511b -.set CYREG_PRT1_AMUX, 0x4000511c -.set CYREG_PRT1_AG, 0x4000511d -.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e -.set CYREG_PRT1_LCD_EN, 0x4000511f -.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 -.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 -.set CYREG_PRT2_DR, 0x40005120 -.set CYREG_PRT2_PS, 0x40005121 -.set CYREG_PRT2_DM0, 0x40005122 -.set CYREG_PRT2_DM1, 0x40005123 -.set CYREG_PRT2_DM2, 0x40005124 -.set CYREG_PRT2_SLW, 0x40005125 -.set CYREG_PRT2_BYP, 0x40005126 -.set CYREG_PRT2_BIE, 0x40005127 -.set CYREG_PRT2_INP_DIS, 0x40005128 -.set CYREG_PRT2_CTL, 0x40005129 -.set CYREG_PRT2_PRT, 0x4000512a -.set CYREG_PRT2_BIT_MASK, 0x4000512b -.set CYREG_PRT2_AMUX, 0x4000512c -.set CYREG_PRT2_AG, 0x4000512d -.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e -.set CYREG_PRT2_LCD_EN, 0x4000512f -.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 -.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 -.set CYREG_PRT3_DR, 0x40005130 -.set CYREG_PRT3_PS, 0x40005131 -.set CYREG_PRT3_DM0, 0x40005132 -.set CYREG_PRT3_DM1, 0x40005133 -.set CYREG_PRT3_DM2, 0x40005134 -.set CYREG_PRT3_SLW, 0x40005135 -.set CYREG_PRT3_BYP, 0x40005136 -.set CYREG_PRT3_BIE, 0x40005137 -.set CYREG_PRT3_INP_DIS, 0x40005138 -.set CYREG_PRT3_CTL, 0x40005139 -.set CYREG_PRT3_PRT, 0x4000513a -.set CYREG_PRT3_BIT_MASK, 0x4000513b -.set CYREG_PRT3_AMUX, 0x4000513c -.set CYREG_PRT3_AG, 0x4000513d -.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e -.set CYREG_PRT3_LCD_EN, 0x4000513f -.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 -.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 -.set CYREG_PRT4_DR, 0x40005140 -.set CYREG_PRT4_PS, 0x40005141 -.set CYREG_PRT4_DM0, 0x40005142 -.set CYREG_PRT4_DM1, 0x40005143 -.set CYREG_PRT4_DM2, 0x40005144 -.set CYREG_PRT4_SLW, 0x40005145 -.set CYREG_PRT4_BYP, 0x40005146 -.set CYREG_PRT4_BIE, 0x40005147 -.set CYREG_PRT4_INP_DIS, 0x40005148 -.set CYREG_PRT4_CTL, 0x40005149 -.set CYREG_PRT4_PRT, 0x4000514a -.set CYREG_PRT4_BIT_MASK, 0x4000514b -.set CYREG_PRT4_AMUX, 0x4000514c -.set CYREG_PRT4_AG, 0x4000514d -.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e -.set CYREG_PRT4_LCD_EN, 0x4000514f -.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 -.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 -.set CYREG_PRT5_DR, 0x40005150 -.set CYREG_PRT5_PS, 0x40005151 -.set CYREG_PRT5_DM0, 0x40005152 -.set CYREG_PRT5_DM1, 0x40005153 -.set CYREG_PRT5_DM2, 0x40005154 -.set CYREG_PRT5_SLW, 0x40005155 -.set CYREG_PRT5_BYP, 0x40005156 -.set CYREG_PRT5_BIE, 0x40005157 -.set CYREG_PRT5_INP_DIS, 0x40005158 -.set CYREG_PRT5_CTL, 0x40005159 -.set CYREG_PRT5_PRT, 0x4000515a -.set CYREG_PRT5_BIT_MASK, 0x4000515b -.set CYREG_PRT5_AMUX, 0x4000515c -.set CYREG_PRT5_AG, 0x4000515d -.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e -.set CYREG_PRT5_LCD_EN, 0x4000515f -.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 -.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 -.set CYREG_PRT6_DR, 0x40005160 -.set CYREG_PRT6_PS, 0x40005161 -.set CYREG_PRT6_DM0, 0x40005162 -.set CYREG_PRT6_DM1, 0x40005163 -.set CYREG_PRT6_DM2, 0x40005164 -.set CYREG_PRT6_SLW, 0x40005165 -.set CYREG_PRT6_BYP, 0x40005166 -.set CYREG_PRT6_BIE, 0x40005167 -.set CYREG_PRT6_INP_DIS, 0x40005168 -.set CYREG_PRT6_CTL, 0x40005169 -.set CYREG_PRT6_PRT, 0x4000516a -.set CYREG_PRT6_BIT_MASK, 0x4000516b -.set CYREG_PRT6_AMUX, 0x4000516c -.set CYREG_PRT6_AG, 0x4000516d -.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e -.set CYREG_PRT6_LCD_EN, 0x4000516f -.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 -.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 -.set CYREG_PRT12_DR, 0x400051c0 -.set CYREG_PRT12_PS, 0x400051c1 -.set CYREG_PRT12_DM0, 0x400051c2 -.set CYREG_PRT12_DM1, 0x400051c3 -.set CYREG_PRT12_DM2, 0x400051c4 -.set CYREG_PRT12_SLW, 0x400051c5 -.set CYREG_PRT12_BYP, 0x400051c6 -.set CYREG_PRT12_BIE, 0x400051c7 -.set CYREG_PRT12_INP_DIS, 0x400051c8 -.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9 -.set CYREG_PRT12_PRT, 0x400051ca -.set CYREG_PRT12_BIT_MASK, 0x400051cb -.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc -.set CYREG_PRT12_AG, 0x400051cd -.set CYREG_PRT12_SIO_CFG, 0x400051ce -.set CYREG_PRT12_SIO_DIFF, 0x400051cf -.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 -.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 -.set CYREG_PRT15_DR, 0x400051f0 -.set CYREG_PRT15_PS, 0x400051f1 -.set CYREG_PRT15_DM0, 0x400051f2 -.set CYREG_PRT15_DM1, 0x400051f3 -.set CYREG_PRT15_DM2, 0x400051f4 -.set CYREG_PRT15_SLW, 0x400051f5 -.set CYREG_PRT15_BYP, 0x400051f6 -.set CYREG_PRT15_BIE, 0x400051f7 -.set CYREG_PRT15_INP_DIS, 0x400051f8 -.set CYREG_PRT15_CTL, 0x400051f9 -.set CYREG_PRT15_PRT, 0x400051fa -.set CYREG_PRT15_BIT_MASK, 0x400051fb -.set CYREG_PRT15_AMUX, 0x400051fc -.set CYREG_PRT15_AG, 0x400051fd -.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe -.set CYREG_PRT15_LCD_EN, 0x400051ff -.set CYDEV_PRTDSI_BASE, 0x40005200 -.set CYDEV_PRTDSI_SIZE, 0x0000007f -.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 -.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 -.set CYREG_PRT0_OUT_SEL0, 0x40005200 -.set CYREG_PRT0_OUT_SEL1, 0x40005201 -.set CYREG_PRT0_OE_SEL0, 0x40005202 -.set CYREG_PRT0_OE_SEL1, 0x40005203 -.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204 -.set CYREG_PRT0_SYNC_OUT, 0x40005205 -.set CYREG_PRT0_CAPS_SEL, 0x40005206 -.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 -.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 -.set CYREG_PRT1_OUT_SEL0, 0x40005208 -.set CYREG_PRT1_OUT_SEL1, 0x40005209 -.set CYREG_PRT1_OE_SEL0, 0x4000520a -.set CYREG_PRT1_OE_SEL1, 0x4000520b -.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c -.set CYREG_PRT1_SYNC_OUT, 0x4000520d -.set CYREG_PRT1_CAPS_SEL, 0x4000520e -.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 -.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 -.set CYREG_PRT2_OUT_SEL0, 0x40005210 -.set CYREG_PRT2_OUT_SEL1, 0x40005211 -.set CYREG_PRT2_OE_SEL0, 0x40005212 -.set CYREG_PRT2_OE_SEL1, 0x40005213 -.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214 -.set CYREG_PRT2_SYNC_OUT, 0x40005215 -.set CYREG_PRT2_CAPS_SEL, 0x40005216 -.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 -.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 -.set CYREG_PRT3_OUT_SEL0, 0x40005218 -.set CYREG_PRT3_OUT_SEL1, 0x40005219 -.set CYREG_PRT3_OE_SEL0, 0x4000521a -.set CYREG_PRT3_OE_SEL1, 0x4000521b -.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c -.set CYREG_PRT3_SYNC_OUT, 0x4000521d -.set CYREG_PRT3_CAPS_SEL, 0x4000521e -.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 -.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 -.set CYREG_PRT4_OUT_SEL0, 0x40005220 -.set CYREG_PRT4_OUT_SEL1, 0x40005221 -.set CYREG_PRT4_OE_SEL0, 0x40005222 -.set CYREG_PRT4_OE_SEL1, 0x40005223 -.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224 -.set CYREG_PRT4_SYNC_OUT, 0x40005225 -.set CYREG_PRT4_CAPS_SEL, 0x40005226 -.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 -.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 -.set CYREG_PRT5_OUT_SEL0, 0x40005228 -.set CYREG_PRT5_OUT_SEL1, 0x40005229 -.set CYREG_PRT5_OE_SEL0, 0x4000522a -.set CYREG_PRT5_OE_SEL1, 0x4000522b -.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c -.set CYREG_PRT5_SYNC_OUT, 0x4000522d -.set CYREG_PRT5_CAPS_SEL, 0x4000522e -.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 -.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 -.set CYREG_PRT6_OUT_SEL0, 0x40005230 -.set CYREG_PRT6_OUT_SEL1, 0x40005231 -.set CYREG_PRT6_OE_SEL0, 0x40005232 -.set CYREG_PRT6_OE_SEL1, 0x40005233 -.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234 -.set CYREG_PRT6_SYNC_OUT, 0x40005235 -.set CYREG_PRT6_CAPS_SEL, 0x40005236 -.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 -.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 -.set CYREG_PRT12_OUT_SEL0, 0x40005260 -.set CYREG_PRT12_OUT_SEL1, 0x40005261 -.set CYREG_PRT12_OE_SEL0, 0x40005262 -.set CYREG_PRT12_OE_SEL1, 0x40005263 -.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264 -.set CYREG_PRT12_SYNC_OUT, 0x40005265 -.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 -.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 -.set CYREG_PRT15_OUT_SEL0, 0x40005278 -.set CYREG_PRT15_OUT_SEL1, 0x40005279 -.set CYREG_PRT15_OE_SEL0, 0x4000527a -.set CYREG_PRT15_OE_SEL1, 0x4000527b -.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c -.set CYREG_PRT15_SYNC_OUT, 0x4000527d -.set CYREG_PRT15_CAPS_SEL, 0x4000527e -.set CYDEV_EMIF_BASE, 0x40005400 -.set CYDEV_EMIF_SIZE, 0x00000007 -.set CYREG_EMIF_NO_UDB, 0x40005400 -.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401 -.set CYREG_EMIF_MEM_DWN, 0x40005402 -.set CYREG_EMIF_MEMCLK_DIV, 0x40005403 -.set CYREG_EMIF_CLOCK_EN, 0x40005404 -.set CYREG_EMIF_EM_TYPE, 0x40005405 -.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406 -.set CYDEV_ANAIF_BASE, 0x40005800 -.set CYDEV_ANAIF_SIZE, 0x000003a9 -.set CYDEV_ANAIF_CFG_BASE, 0x40005800 -.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f -.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 -.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 -.set CYREG_SC0_CR0, 0x40005800 -.set CYREG_SC0_CR1, 0x40005801 -.set CYREG_SC0_CR2, 0x40005802 -.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 -.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 -.set CYREG_SC1_CR0, 0x40005804 -.set CYREG_SC1_CR1, 0x40005805 -.set CYREG_SC1_CR2, 0x40005806 -.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 -.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 -.set CYREG_SC2_CR0, 0x40005808 -.set CYREG_SC2_CR1, 0x40005809 -.set CYREG_SC2_CR2, 0x4000580a -.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c -.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 -.set CYREG_SC3_CR0, 0x4000580c -.set CYREG_SC3_CR1, 0x4000580d -.set CYREG_SC3_CR2, 0x4000580e -.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 -.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 -.set CYREG_DAC0_CR0, 0x40005820 -.set CYREG_DAC0_CR1, 0x40005821 -.set CYREG_DAC0_TST, 0x40005822 -.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 -.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 -.set CYREG_DAC1_CR0, 0x40005824 -.set CYREG_DAC1_CR1, 0x40005825 -.set CYREG_DAC1_TST, 0x40005826 -.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 -.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 -.set CYREG_DAC2_CR0, 0x40005828 -.set CYREG_DAC2_CR1, 0x40005829 -.set CYREG_DAC2_TST, 0x4000582a -.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c -.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 -.set CYREG_DAC3_CR0, 0x4000582c -.set CYREG_DAC3_CR1, 0x4000582d -.set CYREG_DAC3_TST, 0x4000582e -.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 -.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 -.set CYREG_CMP0_CR, 0x40005840 -.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 -.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 -.set CYREG_CMP1_CR, 0x40005841 -.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 -.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 -.set CYREG_CMP2_CR, 0x40005842 -.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 -.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 -.set CYREG_CMP3_CR, 0x40005843 -.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 -.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 -.set CYREG_LUT0_CR, 0x40005848 -.set CYREG_LUT0_MX, 0x40005849 -.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a -.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 -.set CYREG_LUT1_CR, 0x4000584a -.set CYREG_LUT1_MX, 0x4000584b -.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c -.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 -.set CYREG_LUT2_CR, 0x4000584c -.set CYREG_LUT2_MX, 0x4000584d -.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e -.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 -.set CYREG_LUT3_CR, 0x4000584e -.set CYREG_LUT3_MX, 0x4000584f -.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 -.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 -.set CYREG_OPAMP0_CR, 0x40005858 -.set CYREG_OPAMP0_RSVD, 0x40005859 -.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a -.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 -.set CYREG_OPAMP1_CR, 0x4000585a -.set CYREG_OPAMP1_RSVD, 0x4000585b -.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c -.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 -.set CYREG_OPAMP2_CR, 0x4000585c -.set CYREG_OPAMP2_RSVD, 0x4000585d -.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e -.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 -.set CYREG_OPAMP3_CR, 0x4000585e -.set CYREG_OPAMP3_RSVD, 0x4000585f -.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 -.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 -.set CYREG_LCDDAC_CR0, 0x40005868 -.set CYREG_LCDDAC_CR1, 0x40005869 -.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a -.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 -.set CYREG_LCDDRV_CR, 0x4000586a -.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b -.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 -.set CYREG_LCDTMR_CFG, 0x4000586b -.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c -.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 -.set CYREG_BG_CR0, 0x4000586c -.set CYREG_BG_RSVD, 0x4000586d -.set CYREG_BG_DFT0, 0x4000586e -.set CYREG_BG_DFT1, 0x4000586f -.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 -.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 -.set CYREG_CAPSL_CFG0, 0x40005870 -.set CYREG_CAPSL_CFG1, 0x40005871 -.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 -.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 -.set CYREG_CAPSR_CFG0, 0x40005872 -.set CYREG_CAPSR_CFG1, 0x40005873 -.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 -.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 -.set CYREG_PUMP_CR0, 0x40005876 -.set CYREG_PUMP_CR1, 0x40005877 -.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 -.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 -.set CYREG_LPF0_CR0, 0x40005878 -.set CYREG_LPF0_RSVD, 0x40005879 -.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a -.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 -.set CYREG_LPF1_CR0, 0x4000587a -.set CYREG_LPF1_RSVD, 0x4000587b -.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c -.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 -.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c -.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 -.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 -.set CYREG_DSM0_CR0, 0x40005880 -.set CYREG_DSM0_CR1, 0x40005881 -.set CYREG_DSM0_CR2, 0x40005882 -.set CYREG_DSM0_CR3, 0x40005883 -.set CYREG_DSM0_CR4, 0x40005884 -.set CYREG_DSM0_CR5, 0x40005885 -.set CYREG_DSM0_CR6, 0x40005886 -.set CYREG_DSM0_CR7, 0x40005887 -.set CYREG_DSM0_CR8, 0x40005888 -.set CYREG_DSM0_CR9, 0x40005889 -.set CYREG_DSM0_CR10, 0x4000588a -.set CYREG_DSM0_CR11, 0x4000588b -.set CYREG_DSM0_CR12, 0x4000588c -.set CYREG_DSM0_CR13, 0x4000588d -.set CYREG_DSM0_CR14, 0x4000588e -.set CYREG_DSM0_CR15, 0x4000588f -.set CYREG_DSM0_CR16, 0x40005890 -.set CYREG_DSM0_CR17, 0x40005891 -.set CYREG_DSM0_REF0, 0x40005892 -.set CYREG_DSM0_REF1, 0x40005893 -.set CYREG_DSM0_REF2, 0x40005894 -.set CYREG_DSM0_REF3, 0x40005895 -.set CYREG_DSM0_DEM0, 0x40005896 -.set CYREG_DSM0_DEM1, 0x40005897 -.set CYREG_DSM0_TST0, 0x40005898 -.set CYREG_DSM0_TST1, 0x40005899 -.set CYREG_DSM0_BUF0, 0x4000589a -.set CYREG_DSM0_BUF1, 0x4000589b -.set CYREG_DSM0_BUF2, 0x4000589c -.set CYREG_DSM0_BUF3, 0x4000589d -.set CYREG_DSM0_MISC, 0x4000589e -.set CYREG_DSM0_RSVD1, 0x4000589f -.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 -.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 -.set CYREG_SAR0_CSR0, 0x40005900 -.set CYREG_SAR0_CSR1, 0x40005901 -.set CYREG_SAR0_CSR2, 0x40005902 -.set CYREG_SAR0_CSR3, 0x40005903 -.set CYREG_SAR0_CSR4, 0x40005904 -.set CYREG_SAR0_CSR5, 0x40005905 -.set CYREG_SAR0_CSR6, 0x40005906 -.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 -.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 -.set CYREG_SAR1_CSR0, 0x40005908 -.set CYREG_SAR1_CSR1, 0x40005909 -.set CYREG_SAR1_CSR2, 0x4000590a -.set CYREG_SAR1_CSR3, 0x4000590b -.set CYREG_SAR1_CSR4, 0x4000590c -.set CYREG_SAR1_CSR5, 0x4000590d -.set CYREG_SAR1_CSR6, 0x4000590e -.set CYDEV_ANAIF_RT_BASE, 0x40005a00 -.set CYDEV_ANAIF_RT_SIZE, 0x00000162 -.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 -.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d -.set CYREG_SC0_SW0, 0x40005a00 -.set CYREG_SC0_SW2, 0x40005a02 -.set CYREG_SC0_SW3, 0x40005a03 -.set CYREG_SC0_SW4, 0x40005a04 -.set CYREG_SC0_SW6, 0x40005a06 -.set CYREG_SC0_SW7, 0x40005a07 -.set CYREG_SC0_SW8, 0x40005a08 -.set CYREG_SC0_SW10, 0x40005a0a -.set CYREG_SC0_CLK, 0x40005a0b -.set CYREG_SC0_BST, 0x40005a0c -.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 -.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d -.set CYREG_SC1_SW0, 0x40005a10 -.set CYREG_SC1_SW2, 0x40005a12 -.set CYREG_SC1_SW3, 0x40005a13 -.set CYREG_SC1_SW4, 0x40005a14 -.set CYREG_SC1_SW6, 0x40005a16 -.set CYREG_SC1_SW7, 0x40005a17 -.set CYREG_SC1_SW8, 0x40005a18 -.set CYREG_SC1_SW10, 0x40005a1a -.set CYREG_SC1_CLK, 0x40005a1b -.set CYREG_SC1_BST, 0x40005a1c -.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 -.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d -.set CYREG_SC2_SW0, 0x40005a20 -.set CYREG_SC2_SW2, 0x40005a22 -.set CYREG_SC2_SW3, 0x40005a23 -.set CYREG_SC2_SW4, 0x40005a24 -.set CYREG_SC2_SW6, 0x40005a26 -.set CYREG_SC2_SW7, 0x40005a27 -.set CYREG_SC2_SW8, 0x40005a28 -.set CYREG_SC2_SW10, 0x40005a2a -.set CYREG_SC2_CLK, 0x40005a2b -.set CYREG_SC2_BST, 0x40005a2c -.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 -.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d -.set CYREG_SC3_SW0, 0x40005a30 -.set CYREG_SC3_SW2, 0x40005a32 -.set CYREG_SC3_SW3, 0x40005a33 -.set CYREG_SC3_SW4, 0x40005a34 -.set CYREG_SC3_SW6, 0x40005a36 -.set CYREG_SC3_SW7, 0x40005a37 -.set CYREG_SC3_SW8, 0x40005a38 -.set CYREG_SC3_SW10, 0x40005a3a -.set CYREG_SC3_CLK, 0x40005a3b -.set CYREG_SC3_BST, 0x40005a3c -.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 -.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 -.set CYREG_DAC0_SW0, 0x40005a80 -.set CYREG_DAC0_SW2, 0x40005a82 -.set CYREG_DAC0_SW3, 0x40005a83 -.set CYREG_DAC0_SW4, 0x40005a84 -.set CYREG_DAC0_STROBE, 0x40005a87 -.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 -.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 -.set CYREG_DAC1_SW0, 0x40005a88 -.set CYREG_DAC1_SW2, 0x40005a8a -.set CYREG_DAC1_SW3, 0x40005a8b -.set CYREG_DAC1_SW4, 0x40005a8c -.set CYREG_DAC1_STROBE, 0x40005a8f -.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 -.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 -.set CYREG_DAC2_SW0, 0x40005a90 -.set CYREG_DAC2_SW2, 0x40005a92 -.set CYREG_DAC2_SW3, 0x40005a93 -.set CYREG_DAC2_SW4, 0x40005a94 -.set CYREG_DAC2_STROBE, 0x40005a97 -.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 -.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 -.set CYREG_DAC3_SW0, 0x40005a98 -.set CYREG_DAC3_SW2, 0x40005a9a -.set CYREG_DAC3_SW3, 0x40005a9b -.set CYREG_DAC3_SW4, 0x40005a9c -.set CYREG_DAC3_STROBE, 0x40005a9f -.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 -.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 -.set CYREG_CMP0_SW0, 0x40005ac0 -.set CYREG_CMP0_SW2, 0x40005ac2 -.set CYREG_CMP0_SW3, 0x40005ac3 -.set CYREG_CMP0_SW4, 0x40005ac4 -.set CYREG_CMP0_SW6, 0x40005ac6 -.set CYREG_CMP0_CLK, 0x40005ac7 -.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 -.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 -.set CYREG_CMP1_SW0, 0x40005ac8 -.set CYREG_CMP1_SW2, 0x40005aca -.set CYREG_CMP1_SW3, 0x40005acb -.set CYREG_CMP1_SW4, 0x40005acc -.set CYREG_CMP1_SW6, 0x40005ace -.set CYREG_CMP1_CLK, 0x40005acf -.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 -.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 -.set CYREG_CMP2_SW0, 0x40005ad0 -.set CYREG_CMP2_SW2, 0x40005ad2 -.set CYREG_CMP2_SW3, 0x40005ad3 -.set CYREG_CMP2_SW4, 0x40005ad4 -.set CYREG_CMP2_SW6, 0x40005ad6 -.set CYREG_CMP2_CLK, 0x40005ad7 -.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 -.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 -.set CYREG_CMP3_SW0, 0x40005ad8 -.set CYREG_CMP3_SW2, 0x40005ada -.set CYREG_CMP3_SW3, 0x40005adb -.set CYREG_CMP3_SW4, 0x40005adc -.set CYREG_CMP3_SW6, 0x40005ade -.set CYREG_CMP3_CLK, 0x40005adf -.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 -.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 -.set CYREG_DSM0_SW0, 0x40005b00 -.set CYREG_DSM0_SW2, 0x40005b02 -.set CYREG_DSM0_SW3, 0x40005b03 -.set CYREG_DSM0_SW4, 0x40005b04 -.set CYREG_DSM0_SW6, 0x40005b06 -.set CYREG_DSM0_CLK, 0x40005b07 -.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 -.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 -.set CYREG_SAR0_SW0, 0x40005b20 -.set CYREG_SAR0_SW2, 0x40005b22 -.set CYREG_SAR0_SW3, 0x40005b23 -.set CYREG_SAR0_SW4, 0x40005b24 -.set CYREG_SAR0_SW6, 0x40005b26 -.set CYREG_SAR0_CLK, 0x40005b27 -.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 -.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 -.set CYREG_SAR1_SW0, 0x40005b28 -.set CYREG_SAR1_SW2, 0x40005b2a -.set CYREG_SAR1_SW3, 0x40005b2b -.set CYREG_SAR1_SW4, 0x40005b2c -.set CYREG_SAR1_SW6, 0x40005b2e -.set CYREG_SAR1_CLK, 0x40005b2f -.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 -.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 -.set CYREG_OPAMP0_MX, 0x40005b40 -.set CYREG_OPAMP0_SW, 0x40005b41 -.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 -.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 -.set CYREG_OPAMP1_MX, 0x40005b42 -.set CYREG_OPAMP1_SW, 0x40005b43 -.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 -.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 -.set CYREG_OPAMP2_MX, 0x40005b44 -.set CYREG_OPAMP2_SW, 0x40005b45 -.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 -.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 -.set CYREG_OPAMP3_MX, 0x40005b46 -.set CYREG_OPAMP3_SW, 0x40005b47 -.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 -.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 -.set CYREG_LCDDAC_SW0, 0x40005b50 -.set CYREG_LCDDAC_SW1, 0x40005b51 -.set CYREG_LCDDAC_SW2, 0x40005b52 -.set CYREG_LCDDAC_SW3, 0x40005b53 -.set CYREG_LCDDAC_SW4, 0x40005b54 -.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 -.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 -.set CYREG_SC_MISC, 0x40005b56 -.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 -.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 -.set CYREG_BUS_SW0, 0x40005b58 -.set CYREG_BUS_SW2, 0x40005b5a -.set CYREG_BUS_SW3, 0x40005b5b -.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c -.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 -.set CYREG_DFT_CR0, 0x40005b5c -.set CYREG_DFT_CR1, 0x40005b5d -.set CYREG_DFT_CR2, 0x40005b5e -.set CYREG_DFT_CR3, 0x40005b5f -.set CYREG_DFT_CR4, 0x40005b60 -.set CYREG_DFT_CR5, 0x40005b61 -.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 -.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 -.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 -.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 -.set CYREG_DAC0_D, 0x40005b80 -.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 -.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 -.set CYREG_DAC1_D, 0x40005b81 -.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 -.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 -.set CYREG_DAC2_D, 0x40005b82 -.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 -.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 -.set CYREG_DAC3_D, 0x40005b83 -.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 -.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 -.set CYREG_DSM0_OUT0, 0x40005b88 -.set CYREG_DSM0_OUT1, 0x40005b89 -.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 -.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 -.set CYREG_LUT_SR, 0x40005b90 -.set CYREG_LUT_WRK1, 0x40005b91 -.set CYREG_LUT_MSK, 0x40005b92 -.set CYREG_LUT_CLK, 0x40005b93 -.set CYREG_LUT_CPTR, 0x40005b94 -.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 -.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 -.set CYREG_CMP_WRK, 0x40005b96 -.set CYREG_CMP_TST, 0x40005b97 -.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 -.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 -.set CYREG_SC_SR, 0x40005b98 -.set CYREG_SC_WRK1, 0x40005b99 -.set CYREG_SC_MSK, 0x40005b9a -.set CYREG_SC_CMPINV, 0x40005b9b -.set CYREG_SC_CPTR, 0x40005b9c -.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 -.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 -.set CYREG_SAR0_WRK0, 0x40005ba0 -.set CYREG_SAR0_WRK1, 0x40005ba1 -.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 -.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 -.set CYREG_SAR1_WRK0, 0x40005ba2 -.set CYREG_SAR1_WRK1, 0x40005ba3 -.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 -.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 -.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8 -.set CYDEV_USB_BASE, 0x40006000 -.set CYDEV_USB_SIZE, 0x00000300 -.set CYREG_USB_EP0_DR0, 0x40006000 -.set CYREG_USB_EP0_DR1, 0x40006001 -.set CYREG_USB_EP0_DR2, 0x40006002 -.set CYREG_USB_EP0_DR3, 0x40006003 -.set CYREG_USB_EP0_DR4, 0x40006004 -.set CYREG_USB_EP0_DR5, 0x40006005 -.set CYREG_USB_EP0_DR6, 0x40006006 -.set CYREG_USB_EP0_DR7, 0x40006007 -.set CYREG_USB_CR0, 0x40006008 -.set CYREG_USB_CR1, 0x40006009 -.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a -.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b -.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c -.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c -.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d -.set CYREG_USB_SIE_EP1_CR0, 0x4000600e -.set CYREG_USB_USBIO_CR0, 0x40006010 -.set CYREG_USB_USBIO_CR1, 0x40006012 -.set CYREG_USB_DYN_RECONFIG, 0x40006014 -.set CYREG_USB_SOF0, 0x40006018 -.set CYREG_USB_SOF1, 0x40006019 -.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c -.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c -.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d -.set CYREG_USB_SIE_EP2_CR0, 0x4000601e -.set CYREG_USB_EP0_CR, 0x40006028 -.set CYREG_USB_EP0_CNT, 0x40006029 -.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c -.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c -.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d -.set CYREG_USB_SIE_EP3_CR0, 0x4000602e -.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c -.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c -.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d -.set CYREG_USB_SIE_EP4_CR0, 0x4000603e -.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c -.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c -.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d -.set CYREG_USB_SIE_EP5_CR0, 0x4000604e -.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c -.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c -.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d -.set CYREG_USB_SIE_EP6_CR0, 0x4000605e -.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c -.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c -.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d -.set CYREG_USB_SIE_EP7_CR0, 0x4000606e -.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c -.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 -.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c -.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d -.set CYREG_USB_SIE_EP8_CR0, 0x4000607e -.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 -.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP1_CFG, 0x40006080 -.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081 -.set CYREG_USB_ARB_EP1_SR, 0x40006082 -.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 -.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW1_WA, 0x40006084 -.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085 -.set CYREG_USB_ARB_RW1_RA, 0x40006086 -.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087 -.set CYREG_USB_ARB_RW1_DR, 0x40006088 -.set CYREG_USB_BUF_SIZE, 0x4000608c -.set CYREG_USB_EP_ACTIVE, 0x4000608e -.set CYREG_USB_EP_TYPE, 0x4000608f -.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 -.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP2_CFG, 0x40006090 -.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091 -.set CYREG_USB_ARB_EP2_SR, 0x40006092 -.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 -.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW2_WA, 0x40006094 -.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095 -.set CYREG_USB_ARB_RW2_RA, 0x40006096 -.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097 -.set CYREG_USB_ARB_RW2_DR, 0x40006098 -.set CYREG_USB_ARB_CFG, 0x4000609c -.set CYREG_USB_USB_CLK_EN, 0x4000609d -.set CYREG_USB_ARB_INT_EN, 0x4000609e -.set CYREG_USB_ARB_INT_SR, 0x4000609f -.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 -.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP3_CFG, 0x400060a0 -.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1 -.set CYREG_USB_ARB_EP3_SR, 0x400060a2 -.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 -.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW3_WA, 0x400060a4 -.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5 -.set CYREG_USB_ARB_RW3_RA, 0x400060a6 -.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7 -.set CYREG_USB_ARB_RW3_DR, 0x400060a8 -.set CYREG_USB_CWA, 0x400060ac -.set CYREG_USB_CWA_MSB, 0x400060ad -.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 -.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP4_CFG, 0x400060b0 -.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1 -.set CYREG_USB_ARB_EP4_SR, 0x400060b2 -.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 -.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW4_WA, 0x400060b4 -.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5 -.set CYREG_USB_ARB_RW4_RA, 0x400060b6 -.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7 -.set CYREG_USB_ARB_RW4_DR, 0x400060b8 -.set CYREG_USB_DMA_THRES, 0x400060bc -.set CYREG_USB_DMA_THRES_MSB, 0x400060bd -.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 -.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP5_CFG, 0x400060c0 -.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1 -.set CYREG_USB_ARB_EP5_SR, 0x400060c2 -.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 -.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW5_WA, 0x400060c4 -.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5 -.set CYREG_USB_ARB_RW5_RA, 0x400060c6 -.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7 -.set CYREG_USB_ARB_RW5_DR, 0x400060c8 -.set CYREG_USB_BUS_RST_CNT, 0x400060cc -.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 -.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP6_CFG, 0x400060d0 -.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1 -.set CYREG_USB_ARB_EP6_SR, 0x400060d2 -.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 -.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW6_WA, 0x400060d4 -.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5 -.set CYREG_USB_ARB_RW6_RA, 0x400060d6 -.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7 -.set CYREG_USB_ARB_RW6_DR, 0x400060d8 -.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 -.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP7_CFG, 0x400060e0 -.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1 -.set CYREG_USB_ARB_EP7_SR, 0x400060e2 -.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 -.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW7_WA, 0x400060e4 -.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5 -.set CYREG_USB_ARB_RW7_RA, 0x400060e6 -.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7 -.set CYREG_USB_ARB_RW7_DR, 0x400060e8 -.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 -.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 -.set CYREG_USB_ARB_EP8_CFG, 0x400060f0 -.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1 -.set CYREG_USB_ARB_EP8_SR, 0x400060f2 -.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 -.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 -.set CYREG_USB_ARB_RW8_WA, 0x400060f4 -.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5 -.set CYREG_USB_ARB_RW8_RA, 0x400060f6 -.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7 -.set CYREG_USB_ARB_RW8_DR, 0x400060f8 -.set CYDEV_USB_MEM_BASE, 0x40006100 -.set CYDEV_USB_MEM_SIZE, 0x00000200 -.set CYREG_USB_MEM_DATA_MBASE, 0x40006100 -.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200 -.set CYDEV_UWRK_BASE, 0x40006400 -.set CYDEV_UWRK_SIZE, 0x00000b60 -.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 -.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 -.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 -.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 -.set CYREG_B0_UDB00_A0, 0x40006400 -.set CYREG_B0_UDB01_A0, 0x40006401 -.set CYREG_B0_UDB02_A0, 0x40006402 -.set CYREG_B0_UDB03_A0, 0x40006403 -.set CYREG_B0_UDB04_A0, 0x40006404 -.set CYREG_B0_UDB05_A0, 0x40006405 -.set CYREG_B0_UDB06_A0, 0x40006406 -.set CYREG_B0_UDB07_A0, 0x40006407 -.set CYREG_B0_UDB08_A0, 0x40006408 -.set CYREG_B0_UDB09_A0, 0x40006409 -.set CYREG_B0_UDB10_A0, 0x4000640a -.set CYREG_B0_UDB11_A0, 0x4000640b -.set CYREG_B0_UDB12_A0, 0x4000640c -.set CYREG_B0_UDB13_A0, 0x4000640d -.set CYREG_B0_UDB14_A0, 0x4000640e -.set CYREG_B0_UDB15_A0, 0x4000640f -.set CYREG_B0_UDB00_A1, 0x40006410 -.set CYREG_B0_UDB01_A1, 0x40006411 -.set CYREG_B0_UDB02_A1, 0x40006412 -.set CYREG_B0_UDB03_A1, 0x40006413 -.set CYREG_B0_UDB04_A1, 0x40006414 -.set CYREG_B0_UDB05_A1, 0x40006415 -.set CYREG_B0_UDB06_A1, 0x40006416 -.set CYREG_B0_UDB07_A1, 0x40006417 -.set CYREG_B0_UDB08_A1, 0x40006418 -.set CYREG_B0_UDB09_A1, 0x40006419 -.set CYREG_B0_UDB10_A1, 0x4000641a -.set CYREG_B0_UDB11_A1, 0x4000641b -.set CYREG_B0_UDB12_A1, 0x4000641c -.set CYREG_B0_UDB13_A1, 0x4000641d -.set CYREG_B0_UDB14_A1, 0x4000641e -.set CYREG_B0_UDB15_A1, 0x4000641f -.set CYREG_B0_UDB00_D0, 0x40006420 -.set CYREG_B0_UDB01_D0, 0x40006421 -.set CYREG_B0_UDB02_D0, 0x40006422 -.set CYREG_B0_UDB03_D0, 0x40006423 -.set CYREG_B0_UDB04_D0, 0x40006424 -.set CYREG_B0_UDB05_D0, 0x40006425 -.set CYREG_B0_UDB06_D0, 0x40006426 -.set CYREG_B0_UDB07_D0, 0x40006427 -.set CYREG_B0_UDB08_D0, 0x40006428 -.set CYREG_B0_UDB09_D0, 0x40006429 -.set CYREG_B0_UDB10_D0, 0x4000642a -.set CYREG_B0_UDB11_D0, 0x4000642b -.set CYREG_B0_UDB12_D0, 0x4000642c -.set CYREG_B0_UDB13_D0, 0x4000642d -.set CYREG_B0_UDB14_D0, 0x4000642e -.set CYREG_B0_UDB15_D0, 0x4000642f -.set CYREG_B0_UDB00_D1, 0x40006430 -.set CYREG_B0_UDB01_D1, 0x40006431 -.set CYREG_B0_UDB02_D1, 0x40006432 -.set CYREG_B0_UDB03_D1, 0x40006433 -.set CYREG_B0_UDB04_D1, 0x40006434 -.set CYREG_B0_UDB05_D1, 0x40006435 -.set CYREG_B0_UDB06_D1, 0x40006436 -.set CYREG_B0_UDB07_D1, 0x40006437 -.set CYREG_B0_UDB08_D1, 0x40006438 -.set CYREG_B0_UDB09_D1, 0x40006439 -.set CYREG_B0_UDB10_D1, 0x4000643a -.set CYREG_B0_UDB11_D1, 0x4000643b -.set CYREG_B0_UDB12_D1, 0x4000643c -.set CYREG_B0_UDB13_D1, 0x4000643d -.set CYREG_B0_UDB14_D1, 0x4000643e -.set CYREG_B0_UDB15_D1, 0x4000643f -.set CYREG_B0_UDB00_F0, 0x40006440 -.set CYREG_B0_UDB01_F0, 0x40006441 -.set CYREG_B0_UDB02_F0, 0x40006442 -.set CYREG_B0_UDB03_F0, 0x40006443 -.set CYREG_B0_UDB04_F0, 0x40006444 -.set CYREG_B0_UDB05_F0, 0x40006445 -.set CYREG_B0_UDB06_F0, 0x40006446 -.set CYREG_B0_UDB07_F0, 0x40006447 -.set CYREG_B0_UDB08_F0, 0x40006448 -.set CYREG_B0_UDB09_F0, 0x40006449 -.set CYREG_B0_UDB10_F0, 0x4000644a -.set CYREG_B0_UDB11_F0, 0x4000644b -.set CYREG_B0_UDB12_F0, 0x4000644c -.set CYREG_B0_UDB13_F0, 0x4000644d -.set CYREG_B0_UDB14_F0, 0x4000644e -.set CYREG_B0_UDB15_F0, 0x4000644f -.set CYREG_B0_UDB00_F1, 0x40006450 -.set CYREG_B0_UDB01_F1, 0x40006451 -.set CYREG_B0_UDB02_F1, 0x40006452 -.set CYREG_B0_UDB03_F1, 0x40006453 -.set CYREG_B0_UDB04_F1, 0x40006454 -.set CYREG_B0_UDB05_F1, 0x40006455 -.set CYREG_B0_UDB06_F1, 0x40006456 -.set CYREG_B0_UDB07_F1, 0x40006457 -.set CYREG_B0_UDB08_F1, 0x40006458 -.set CYREG_B0_UDB09_F1, 0x40006459 -.set CYREG_B0_UDB10_F1, 0x4000645a -.set CYREG_B0_UDB11_F1, 0x4000645b -.set CYREG_B0_UDB12_F1, 0x4000645c -.set CYREG_B0_UDB13_F1, 0x4000645d -.set CYREG_B0_UDB14_F1, 0x4000645e -.set CYREG_B0_UDB15_F1, 0x4000645f -.set CYREG_B0_UDB00_ST, 0x40006460 -.set CYREG_B0_UDB01_ST, 0x40006461 -.set CYREG_B0_UDB02_ST, 0x40006462 -.set CYREG_B0_UDB03_ST, 0x40006463 -.set CYREG_B0_UDB04_ST, 0x40006464 -.set CYREG_B0_UDB05_ST, 0x40006465 -.set CYREG_B0_UDB06_ST, 0x40006466 -.set CYREG_B0_UDB07_ST, 0x40006467 -.set CYREG_B0_UDB08_ST, 0x40006468 -.set CYREG_B0_UDB09_ST, 0x40006469 -.set CYREG_B0_UDB10_ST, 0x4000646a -.set CYREG_B0_UDB11_ST, 0x4000646b -.set CYREG_B0_UDB12_ST, 0x4000646c -.set CYREG_B0_UDB13_ST, 0x4000646d -.set CYREG_B0_UDB14_ST, 0x4000646e -.set CYREG_B0_UDB15_ST, 0x4000646f -.set CYREG_B0_UDB00_CTL, 0x40006470 -.set CYREG_B0_UDB01_CTL, 0x40006471 -.set CYREG_B0_UDB02_CTL, 0x40006472 -.set CYREG_B0_UDB03_CTL, 0x40006473 -.set CYREG_B0_UDB04_CTL, 0x40006474 -.set CYREG_B0_UDB05_CTL, 0x40006475 -.set CYREG_B0_UDB06_CTL, 0x40006476 -.set CYREG_B0_UDB07_CTL, 0x40006477 -.set CYREG_B0_UDB08_CTL, 0x40006478 -.set CYREG_B0_UDB09_CTL, 0x40006479 -.set CYREG_B0_UDB10_CTL, 0x4000647a -.set CYREG_B0_UDB11_CTL, 0x4000647b -.set CYREG_B0_UDB12_CTL, 0x4000647c -.set CYREG_B0_UDB13_CTL, 0x4000647d -.set CYREG_B0_UDB14_CTL, 0x4000647e -.set CYREG_B0_UDB15_CTL, 0x4000647f -.set CYREG_B0_UDB00_MSK, 0x40006480 -.set CYREG_B0_UDB01_MSK, 0x40006481 -.set CYREG_B0_UDB02_MSK, 0x40006482 -.set CYREG_B0_UDB03_MSK, 0x40006483 -.set CYREG_B0_UDB04_MSK, 0x40006484 -.set CYREG_B0_UDB05_MSK, 0x40006485 -.set CYREG_B0_UDB06_MSK, 0x40006486 -.set CYREG_B0_UDB07_MSK, 0x40006487 -.set CYREG_B0_UDB08_MSK, 0x40006488 -.set CYREG_B0_UDB09_MSK, 0x40006489 -.set CYREG_B0_UDB10_MSK, 0x4000648a -.set CYREG_B0_UDB11_MSK, 0x4000648b -.set CYREG_B0_UDB12_MSK, 0x4000648c -.set CYREG_B0_UDB13_MSK, 0x4000648d -.set CYREG_B0_UDB14_MSK, 0x4000648e -.set CYREG_B0_UDB15_MSK, 0x4000648f -.set CYREG_B0_UDB00_ACTL, 0x40006490 -.set CYREG_B0_UDB01_ACTL, 0x40006491 -.set CYREG_B0_UDB02_ACTL, 0x40006492 -.set CYREG_B0_UDB03_ACTL, 0x40006493 -.set CYREG_B0_UDB04_ACTL, 0x40006494 -.set CYREG_B0_UDB05_ACTL, 0x40006495 -.set CYREG_B0_UDB06_ACTL, 0x40006496 -.set CYREG_B0_UDB07_ACTL, 0x40006497 -.set CYREG_B0_UDB08_ACTL, 0x40006498 -.set CYREG_B0_UDB09_ACTL, 0x40006499 -.set CYREG_B0_UDB10_ACTL, 0x4000649a -.set CYREG_B0_UDB11_ACTL, 0x4000649b -.set CYREG_B0_UDB12_ACTL, 0x4000649c -.set CYREG_B0_UDB13_ACTL, 0x4000649d -.set CYREG_B0_UDB14_ACTL, 0x4000649e -.set CYREG_B0_UDB15_ACTL, 0x4000649f -.set CYREG_B0_UDB00_MC, 0x400064a0 -.set CYREG_B0_UDB01_MC, 0x400064a1 -.set CYREG_B0_UDB02_MC, 0x400064a2 -.set CYREG_B0_UDB03_MC, 0x400064a3 -.set CYREG_B0_UDB04_MC, 0x400064a4 -.set CYREG_B0_UDB05_MC, 0x400064a5 -.set CYREG_B0_UDB06_MC, 0x400064a6 -.set CYREG_B0_UDB07_MC, 0x400064a7 -.set CYREG_B0_UDB08_MC, 0x400064a8 -.set CYREG_B0_UDB09_MC, 0x400064a9 -.set CYREG_B0_UDB10_MC, 0x400064aa -.set CYREG_B0_UDB11_MC, 0x400064ab -.set CYREG_B0_UDB12_MC, 0x400064ac -.set CYREG_B0_UDB13_MC, 0x400064ad -.set CYREG_B0_UDB14_MC, 0x400064ae -.set CYREG_B0_UDB15_MC, 0x400064af -.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 -.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 -.set CYREG_B1_UDB04_A0, 0x40006504 -.set CYREG_B1_UDB05_A0, 0x40006505 -.set CYREG_B1_UDB06_A0, 0x40006506 -.set CYREG_B1_UDB07_A0, 0x40006507 -.set CYREG_B1_UDB08_A0, 0x40006508 -.set CYREG_B1_UDB09_A0, 0x40006509 -.set CYREG_B1_UDB10_A0, 0x4000650a -.set CYREG_B1_UDB11_A0, 0x4000650b -.set CYREG_B1_UDB04_A1, 0x40006514 -.set CYREG_B1_UDB05_A1, 0x40006515 -.set CYREG_B1_UDB06_A1, 0x40006516 -.set CYREG_B1_UDB07_A1, 0x40006517 -.set CYREG_B1_UDB08_A1, 0x40006518 -.set CYREG_B1_UDB09_A1, 0x40006519 -.set CYREG_B1_UDB10_A1, 0x4000651a -.set CYREG_B1_UDB11_A1, 0x4000651b -.set CYREG_B1_UDB04_D0, 0x40006524 -.set CYREG_B1_UDB05_D0, 0x40006525 -.set CYREG_B1_UDB06_D0, 0x40006526 -.set CYREG_B1_UDB07_D0, 0x40006527 -.set CYREG_B1_UDB08_D0, 0x40006528 -.set CYREG_B1_UDB09_D0, 0x40006529 -.set CYREG_B1_UDB10_D0, 0x4000652a -.set CYREG_B1_UDB11_D0, 0x4000652b -.set CYREG_B1_UDB04_D1, 0x40006534 -.set CYREG_B1_UDB05_D1, 0x40006535 -.set CYREG_B1_UDB06_D1, 0x40006536 -.set CYREG_B1_UDB07_D1, 0x40006537 -.set CYREG_B1_UDB08_D1, 0x40006538 -.set CYREG_B1_UDB09_D1, 0x40006539 -.set CYREG_B1_UDB10_D1, 0x4000653a -.set CYREG_B1_UDB11_D1, 0x4000653b -.set CYREG_B1_UDB04_F0, 0x40006544 -.set CYREG_B1_UDB05_F0, 0x40006545 -.set CYREG_B1_UDB06_F0, 0x40006546 -.set CYREG_B1_UDB07_F0, 0x40006547 -.set CYREG_B1_UDB08_F0, 0x40006548 -.set CYREG_B1_UDB09_F0, 0x40006549 -.set CYREG_B1_UDB10_F0, 0x4000654a -.set CYREG_B1_UDB11_F0, 0x4000654b -.set CYREG_B1_UDB04_F1, 0x40006554 -.set CYREG_B1_UDB05_F1, 0x40006555 -.set CYREG_B1_UDB06_F1, 0x40006556 -.set CYREG_B1_UDB07_F1, 0x40006557 -.set CYREG_B1_UDB08_F1, 0x40006558 -.set CYREG_B1_UDB09_F1, 0x40006559 -.set CYREG_B1_UDB10_F1, 0x4000655a -.set CYREG_B1_UDB11_F1, 0x4000655b -.set CYREG_B1_UDB04_ST, 0x40006564 -.set CYREG_B1_UDB05_ST, 0x40006565 -.set CYREG_B1_UDB06_ST, 0x40006566 -.set CYREG_B1_UDB07_ST, 0x40006567 -.set CYREG_B1_UDB08_ST, 0x40006568 -.set CYREG_B1_UDB09_ST, 0x40006569 -.set CYREG_B1_UDB10_ST, 0x4000656a -.set CYREG_B1_UDB11_ST, 0x4000656b -.set CYREG_B1_UDB04_CTL, 0x40006574 -.set CYREG_B1_UDB05_CTL, 0x40006575 -.set CYREG_B1_UDB06_CTL, 0x40006576 -.set CYREG_B1_UDB07_CTL, 0x40006577 -.set CYREG_B1_UDB08_CTL, 0x40006578 -.set CYREG_B1_UDB09_CTL, 0x40006579 -.set CYREG_B1_UDB10_CTL, 0x4000657a -.set CYREG_B1_UDB11_CTL, 0x4000657b -.set CYREG_B1_UDB04_MSK, 0x40006584 -.set CYREG_B1_UDB05_MSK, 0x40006585 -.set CYREG_B1_UDB06_MSK, 0x40006586 -.set CYREG_B1_UDB07_MSK, 0x40006587 -.set CYREG_B1_UDB08_MSK, 0x40006588 -.set CYREG_B1_UDB09_MSK, 0x40006589 -.set CYREG_B1_UDB10_MSK, 0x4000658a -.set CYREG_B1_UDB11_MSK, 0x4000658b -.set CYREG_B1_UDB04_ACTL, 0x40006594 -.set CYREG_B1_UDB05_ACTL, 0x40006595 -.set CYREG_B1_UDB06_ACTL, 0x40006596 -.set CYREG_B1_UDB07_ACTL, 0x40006597 -.set CYREG_B1_UDB08_ACTL, 0x40006598 -.set CYREG_B1_UDB09_ACTL, 0x40006599 -.set CYREG_B1_UDB10_ACTL, 0x4000659a -.set CYREG_B1_UDB11_ACTL, 0x4000659b -.set CYREG_B1_UDB04_MC, 0x400065a4 -.set CYREG_B1_UDB05_MC, 0x400065a5 -.set CYREG_B1_UDB06_MC, 0x400065a6 -.set CYREG_B1_UDB07_MC, 0x400065a7 -.set CYREG_B1_UDB08_MC, 0x400065a8 -.set CYREG_B1_UDB09_MC, 0x400065a9 -.set CYREG_B1_UDB10_MC, 0x400065aa -.set CYREG_B1_UDB11_MC, 0x400065ab -.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 -.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 -.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 -.set CYREG_B0_UDB00_A0_A1, 0x40006800 -.set CYREG_B0_UDB01_A0_A1, 0x40006802 -.set CYREG_B0_UDB02_A0_A1, 0x40006804 -.set CYREG_B0_UDB03_A0_A1, 0x40006806 -.set CYREG_B0_UDB04_A0_A1, 0x40006808 -.set CYREG_B0_UDB05_A0_A1, 0x4000680a -.set CYREG_B0_UDB06_A0_A1, 0x4000680c -.set CYREG_B0_UDB07_A0_A1, 0x4000680e -.set CYREG_B0_UDB08_A0_A1, 0x40006810 -.set CYREG_B0_UDB09_A0_A1, 0x40006812 -.set CYREG_B0_UDB10_A0_A1, 0x40006814 -.set CYREG_B0_UDB11_A0_A1, 0x40006816 -.set CYREG_B0_UDB12_A0_A1, 0x40006818 -.set CYREG_B0_UDB13_A0_A1, 0x4000681a -.set CYREG_B0_UDB14_A0_A1, 0x4000681c -.set CYREG_B0_UDB15_A0_A1, 0x4000681e -.set CYREG_B0_UDB00_D0_D1, 0x40006840 -.set CYREG_B0_UDB01_D0_D1, 0x40006842 -.set CYREG_B0_UDB02_D0_D1, 0x40006844 -.set CYREG_B0_UDB03_D0_D1, 0x40006846 -.set CYREG_B0_UDB04_D0_D1, 0x40006848 -.set CYREG_B0_UDB05_D0_D1, 0x4000684a -.set CYREG_B0_UDB06_D0_D1, 0x4000684c -.set CYREG_B0_UDB07_D0_D1, 0x4000684e -.set CYREG_B0_UDB08_D0_D1, 0x40006850 -.set CYREG_B0_UDB09_D0_D1, 0x40006852 -.set CYREG_B0_UDB10_D0_D1, 0x40006854 -.set CYREG_B0_UDB11_D0_D1, 0x40006856 -.set CYREG_B0_UDB12_D0_D1, 0x40006858 -.set CYREG_B0_UDB13_D0_D1, 0x4000685a -.set CYREG_B0_UDB14_D0_D1, 0x4000685c -.set CYREG_B0_UDB15_D0_D1, 0x4000685e -.set CYREG_B0_UDB00_F0_F1, 0x40006880 -.set CYREG_B0_UDB01_F0_F1, 0x40006882 -.set CYREG_B0_UDB02_F0_F1, 0x40006884 -.set CYREG_B0_UDB03_F0_F1, 0x40006886 -.set CYREG_B0_UDB04_F0_F1, 0x40006888 -.set CYREG_B0_UDB05_F0_F1, 0x4000688a -.set CYREG_B0_UDB06_F0_F1, 0x4000688c -.set CYREG_B0_UDB07_F0_F1, 0x4000688e -.set CYREG_B0_UDB08_F0_F1, 0x40006890 -.set CYREG_B0_UDB09_F0_F1, 0x40006892 -.set CYREG_B0_UDB10_F0_F1, 0x40006894 -.set CYREG_B0_UDB11_F0_F1, 0x40006896 -.set CYREG_B0_UDB12_F0_F1, 0x40006898 -.set CYREG_B0_UDB13_F0_F1, 0x4000689a -.set CYREG_B0_UDB14_F0_F1, 0x4000689c -.set CYREG_B0_UDB15_F0_F1, 0x4000689e -.set CYREG_B0_UDB00_ST_CTL, 0x400068c0 -.set CYREG_B0_UDB01_ST_CTL, 0x400068c2 -.set CYREG_B0_UDB02_ST_CTL, 0x400068c4 -.set CYREG_B0_UDB03_ST_CTL, 0x400068c6 -.set CYREG_B0_UDB04_ST_CTL, 0x400068c8 -.set CYREG_B0_UDB05_ST_CTL, 0x400068ca -.set CYREG_B0_UDB06_ST_CTL, 0x400068cc -.set CYREG_B0_UDB07_ST_CTL, 0x400068ce -.set CYREG_B0_UDB08_ST_CTL, 0x400068d0 -.set CYREG_B0_UDB09_ST_CTL, 0x400068d2 -.set CYREG_B0_UDB10_ST_CTL, 0x400068d4 -.set CYREG_B0_UDB11_ST_CTL, 0x400068d6 -.set CYREG_B0_UDB12_ST_CTL, 0x400068d8 -.set CYREG_B0_UDB13_ST_CTL, 0x400068da -.set CYREG_B0_UDB14_ST_CTL, 0x400068dc -.set CYREG_B0_UDB15_ST_CTL, 0x400068de -.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900 -.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902 -.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904 -.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906 -.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908 -.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a -.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c -.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e -.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910 -.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912 -.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914 -.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916 -.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918 -.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a -.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c -.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e -.set CYREG_B0_UDB00_MC_00, 0x40006940 -.set CYREG_B0_UDB01_MC_00, 0x40006942 -.set CYREG_B0_UDB02_MC_00, 0x40006944 -.set CYREG_B0_UDB03_MC_00, 0x40006946 -.set CYREG_B0_UDB04_MC_00, 0x40006948 -.set CYREG_B0_UDB05_MC_00, 0x4000694a -.set CYREG_B0_UDB06_MC_00, 0x4000694c -.set CYREG_B0_UDB07_MC_00, 0x4000694e -.set CYREG_B0_UDB08_MC_00, 0x40006950 -.set CYREG_B0_UDB09_MC_00, 0x40006952 -.set CYREG_B0_UDB10_MC_00, 0x40006954 -.set CYREG_B0_UDB11_MC_00, 0x40006956 -.set CYREG_B0_UDB12_MC_00, 0x40006958 -.set CYREG_B0_UDB13_MC_00, 0x4000695a -.set CYREG_B0_UDB14_MC_00, 0x4000695c -.set CYREG_B0_UDB15_MC_00, 0x4000695e -.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 -.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 -.set CYREG_B1_UDB04_A0_A1, 0x40006a08 -.set CYREG_B1_UDB05_A0_A1, 0x40006a0a -.set CYREG_B1_UDB06_A0_A1, 0x40006a0c -.set CYREG_B1_UDB07_A0_A1, 0x40006a0e -.set CYREG_B1_UDB08_A0_A1, 0x40006a10 -.set CYREG_B1_UDB09_A0_A1, 0x40006a12 -.set CYREG_B1_UDB10_A0_A1, 0x40006a14 -.set CYREG_B1_UDB11_A0_A1, 0x40006a16 -.set CYREG_B1_UDB04_D0_D1, 0x40006a48 -.set CYREG_B1_UDB05_D0_D1, 0x40006a4a -.set CYREG_B1_UDB06_D0_D1, 0x40006a4c -.set CYREG_B1_UDB07_D0_D1, 0x40006a4e -.set CYREG_B1_UDB08_D0_D1, 0x40006a50 -.set CYREG_B1_UDB09_D0_D1, 0x40006a52 -.set CYREG_B1_UDB10_D0_D1, 0x40006a54 -.set CYREG_B1_UDB11_D0_D1, 0x40006a56 -.set CYREG_B1_UDB04_F0_F1, 0x40006a88 -.set CYREG_B1_UDB05_F0_F1, 0x40006a8a -.set CYREG_B1_UDB06_F0_F1, 0x40006a8c -.set CYREG_B1_UDB07_F0_F1, 0x40006a8e -.set CYREG_B1_UDB08_F0_F1, 0x40006a90 -.set CYREG_B1_UDB09_F0_F1, 0x40006a92 -.set CYREG_B1_UDB10_F0_F1, 0x40006a94 -.set CYREG_B1_UDB11_F0_F1, 0x40006a96 -.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8 -.set CYREG_B1_UDB05_ST_CTL, 0x40006aca -.set CYREG_B1_UDB06_ST_CTL, 0x40006acc -.set CYREG_B1_UDB07_ST_CTL, 0x40006ace -.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0 -.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2 -.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4 -.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6 -.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08 -.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a -.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c -.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e -.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10 -.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12 -.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14 -.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16 -.set CYREG_B1_UDB04_MC_00, 0x40006b48 -.set CYREG_B1_UDB05_MC_00, 0x40006b4a -.set CYREG_B1_UDB06_MC_00, 0x40006b4c -.set CYREG_B1_UDB07_MC_00, 0x40006b4e -.set CYREG_B1_UDB08_MC_00, 0x40006b50 -.set CYREG_B1_UDB09_MC_00, 0x40006b52 -.set CYREG_B1_UDB10_MC_00, 0x40006b54 -.set CYREG_B1_UDB11_MC_00, 0x40006b56 -.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e -.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 -.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e -.set CYREG_B0_UDB00_01_A0, 0x40006800 -.set CYREG_B0_UDB01_02_A0, 0x40006802 -.set CYREG_B0_UDB02_03_A0, 0x40006804 -.set CYREG_B0_UDB03_04_A0, 0x40006806 -.set CYREG_B0_UDB04_05_A0, 0x40006808 -.set CYREG_B0_UDB05_06_A0, 0x4000680a -.set CYREG_B0_UDB06_07_A0, 0x4000680c -.set CYREG_B0_UDB07_08_A0, 0x4000680e -.set CYREG_B0_UDB08_09_A0, 0x40006810 -.set CYREG_B0_UDB09_10_A0, 0x40006812 -.set CYREG_B0_UDB10_11_A0, 0x40006814 -.set CYREG_B0_UDB11_12_A0, 0x40006816 -.set CYREG_B0_UDB12_13_A0, 0x40006818 -.set CYREG_B0_UDB13_14_A0, 0x4000681a -.set CYREG_B0_UDB14_15_A0, 0x4000681c -.set CYREG_B0_UDB00_01_A1, 0x40006820 -.set CYREG_B0_UDB01_02_A1, 0x40006822 -.set CYREG_B0_UDB02_03_A1, 0x40006824 -.set CYREG_B0_UDB03_04_A1, 0x40006826 -.set CYREG_B0_UDB04_05_A1, 0x40006828 -.set CYREG_B0_UDB05_06_A1, 0x4000682a -.set CYREG_B0_UDB06_07_A1, 0x4000682c -.set CYREG_B0_UDB07_08_A1, 0x4000682e -.set CYREG_B0_UDB08_09_A1, 0x40006830 -.set CYREG_B0_UDB09_10_A1, 0x40006832 -.set CYREG_B0_UDB10_11_A1, 0x40006834 -.set CYREG_B0_UDB11_12_A1, 0x40006836 -.set CYREG_B0_UDB12_13_A1, 0x40006838 -.set CYREG_B0_UDB13_14_A1, 0x4000683a -.set CYREG_B0_UDB14_15_A1, 0x4000683c -.set CYREG_B0_UDB00_01_D0, 0x40006840 -.set CYREG_B0_UDB01_02_D0, 0x40006842 -.set CYREG_B0_UDB02_03_D0, 0x40006844 -.set CYREG_B0_UDB03_04_D0, 0x40006846 -.set CYREG_B0_UDB04_05_D0, 0x40006848 -.set CYREG_B0_UDB05_06_D0, 0x4000684a -.set CYREG_B0_UDB06_07_D0, 0x4000684c -.set CYREG_B0_UDB07_08_D0, 0x4000684e -.set CYREG_B0_UDB08_09_D0, 0x40006850 -.set CYREG_B0_UDB09_10_D0, 0x40006852 -.set CYREG_B0_UDB10_11_D0, 0x40006854 -.set CYREG_B0_UDB11_12_D0, 0x40006856 -.set CYREG_B0_UDB12_13_D0, 0x40006858 -.set CYREG_B0_UDB13_14_D0, 0x4000685a -.set CYREG_B0_UDB14_15_D0, 0x4000685c -.set CYREG_B0_UDB00_01_D1, 0x40006860 -.set CYREG_B0_UDB01_02_D1, 0x40006862 -.set CYREG_B0_UDB02_03_D1, 0x40006864 -.set CYREG_B0_UDB03_04_D1, 0x40006866 -.set CYREG_B0_UDB04_05_D1, 0x40006868 -.set CYREG_B0_UDB05_06_D1, 0x4000686a -.set CYREG_B0_UDB06_07_D1, 0x4000686c -.set CYREG_B0_UDB07_08_D1, 0x4000686e -.set CYREG_B0_UDB08_09_D1, 0x40006870 -.set CYREG_B0_UDB09_10_D1, 0x40006872 -.set CYREG_B0_UDB10_11_D1, 0x40006874 -.set CYREG_B0_UDB11_12_D1, 0x40006876 -.set CYREG_B0_UDB12_13_D1, 0x40006878 -.set CYREG_B0_UDB13_14_D1, 0x4000687a -.set CYREG_B0_UDB14_15_D1, 0x4000687c -.set CYREG_B0_UDB00_01_F0, 0x40006880 -.set CYREG_B0_UDB01_02_F0, 0x40006882 -.set CYREG_B0_UDB02_03_F0, 0x40006884 -.set CYREG_B0_UDB03_04_F0, 0x40006886 -.set CYREG_B0_UDB04_05_F0, 0x40006888 -.set CYREG_B0_UDB05_06_F0, 0x4000688a -.set CYREG_B0_UDB06_07_F0, 0x4000688c -.set CYREG_B0_UDB07_08_F0, 0x4000688e -.set CYREG_B0_UDB08_09_F0, 0x40006890 -.set CYREG_B0_UDB09_10_F0, 0x40006892 -.set CYREG_B0_UDB10_11_F0, 0x40006894 -.set CYREG_B0_UDB11_12_F0, 0x40006896 -.set CYREG_B0_UDB12_13_F0, 0x40006898 -.set CYREG_B0_UDB13_14_F0, 0x4000689a -.set CYREG_B0_UDB14_15_F0, 0x4000689c -.set CYREG_B0_UDB00_01_F1, 0x400068a0 -.set CYREG_B0_UDB01_02_F1, 0x400068a2 -.set CYREG_B0_UDB02_03_F1, 0x400068a4 -.set CYREG_B0_UDB03_04_F1, 0x400068a6 -.set CYREG_B0_UDB04_05_F1, 0x400068a8 -.set CYREG_B0_UDB05_06_F1, 0x400068aa -.set CYREG_B0_UDB06_07_F1, 0x400068ac -.set CYREG_B0_UDB07_08_F1, 0x400068ae -.set CYREG_B0_UDB08_09_F1, 0x400068b0 -.set CYREG_B0_UDB09_10_F1, 0x400068b2 -.set CYREG_B0_UDB10_11_F1, 0x400068b4 -.set CYREG_B0_UDB11_12_F1, 0x400068b6 -.set CYREG_B0_UDB12_13_F1, 0x400068b8 -.set CYREG_B0_UDB13_14_F1, 0x400068ba -.set CYREG_B0_UDB14_15_F1, 0x400068bc -.set CYREG_B0_UDB00_01_ST, 0x400068c0 -.set CYREG_B0_UDB01_02_ST, 0x400068c2 -.set CYREG_B0_UDB02_03_ST, 0x400068c4 -.set CYREG_B0_UDB03_04_ST, 0x400068c6 -.set CYREG_B0_UDB04_05_ST, 0x400068c8 -.set CYREG_B0_UDB05_06_ST, 0x400068ca -.set CYREG_B0_UDB06_07_ST, 0x400068cc -.set CYREG_B0_UDB07_08_ST, 0x400068ce -.set CYREG_B0_UDB08_09_ST, 0x400068d0 -.set CYREG_B0_UDB09_10_ST, 0x400068d2 -.set CYREG_B0_UDB10_11_ST, 0x400068d4 -.set CYREG_B0_UDB11_12_ST, 0x400068d6 -.set CYREG_B0_UDB12_13_ST, 0x400068d8 -.set CYREG_B0_UDB13_14_ST, 0x400068da -.set CYREG_B0_UDB14_15_ST, 0x400068dc -.set CYREG_B0_UDB00_01_CTL, 0x400068e0 -.set CYREG_B0_UDB01_02_CTL, 0x400068e2 -.set CYREG_B0_UDB02_03_CTL, 0x400068e4 -.set CYREG_B0_UDB03_04_CTL, 0x400068e6 -.set CYREG_B0_UDB04_05_CTL, 0x400068e8 -.set CYREG_B0_UDB05_06_CTL, 0x400068ea -.set CYREG_B0_UDB06_07_CTL, 0x400068ec -.set CYREG_B0_UDB07_08_CTL, 0x400068ee -.set CYREG_B0_UDB08_09_CTL, 0x400068f0 -.set CYREG_B0_UDB09_10_CTL, 0x400068f2 -.set CYREG_B0_UDB10_11_CTL, 0x400068f4 -.set CYREG_B0_UDB11_12_CTL, 0x400068f6 -.set CYREG_B0_UDB12_13_CTL, 0x400068f8 -.set CYREG_B0_UDB13_14_CTL, 0x400068fa -.set CYREG_B0_UDB14_15_CTL, 0x400068fc -.set CYREG_B0_UDB00_01_MSK, 0x40006900 -.set CYREG_B0_UDB01_02_MSK, 0x40006902 -.set CYREG_B0_UDB02_03_MSK, 0x40006904 -.set CYREG_B0_UDB03_04_MSK, 0x40006906 -.set CYREG_B0_UDB04_05_MSK, 0x40006908 -.set CYREG_B0_UDB05_06_MSK, 0x4000690a -.set CYREG_B0_UDB06_07_MSK, 0x4000690c -.set CYREG_B0_UDB07_08_MSK, 0x4000690e -.set CYREG_B0_UDB08_09_MSK, 0x40006910 -.set CYREG_B0_UDB09_10_MSK, 0x40006912 -.set CYREG_B0_UDB10_11_MSK, 0x40006914 -.set CYREG_B0_UDB11_12_MSK, 0x40006916 -.set CYREG_B0_UDB12_13_MSK, 0x40006918 -.set CYREG_B0_UDB13_14_MSK, 0x4000691a -.set CYREG_B0_UDB14_15_MSK, 0x4000691c -.set CYREG_B0_UDB00_01_ACTL, 0x40006920 -.set CYREG_B0_UDB01_02_ACTL, 0x40006922 -.set CYREG_B0_UDB02_03_ACTL, 0x40006924 -.set CYREG_B0_UDB03_04_ACTL, 0x40006926 -.set CYREG_B0_UDB04_05_ACTL, 0x40006928 -.set CYREG_B0_UDB05_06_ACTL, 0x4000692a -.set CYREG_B0_UDB06_07_ACTL, 0x4000692c -.set CYREG_B0_UDB07_08_ACTL, 0x4000692e -.set CYREG_B0_UDB08_09_ACTL, 0x40006930 -.set CYREG_B0_UDB09_10_ACTL, 0x40006932 -.set CYREG_B0_UDB10_11_ACTL, 0x40006934 -.set CYREG_B0_UDB11_12_ACTL, 0x40006936 -.set CYREG_B0_UDB12_13_ACTL, 0x40006938 -.set CYREG_B0_UDB13_14_ACTL, 0x4000693a -.set CYREG_B0_UDB14_15_ACTL, 0x4000693c -.set CYREG_B0_UDB00_01_MC, 0x40006940 -.set CYREG_B0_UDB01_02_MC, 0x40006942 -.set CYREG_B0_UDB02_03_MC, 0x40006944 -.set CYREG_B0_UDB03_04_MC, 0x40006946 -.set CYREG_B0_UDB04_05_MC, 0x40006948 -.set CYREG_B0_UDB05_06_MC, 0x4000694a -.set CYREG_B0_UDB06_07_MC, 0x4000694c -.set CYREG_B0_UDB07_08_MC, 0x4000694e -.set CYREG_B0_UDB08_09_MC, 0x40006950 -.set CYREG_B0_UDB09_10_MC, 0x40006952 -.set CYREG_B0_UDB10_11_MC, 0x40006954 -.set CYREG_B0_UDB11_12_MC, 0x40006956 -.set CYREG_B0_UDB12_13_MC, 0x40006958 -.set CYREG_B0_UDB13_14_MC, 0x4000695a -.set CYREG_B0_UDB14_15_MC, 0x4000695c -.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 -.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e -.set CYREG_B1_UDB04_05_A0, 0x40006a08 -.set CYREG_B1_UDB05_06_A0, 0x40006a0a -.set CYREG_B1_UDB06_07_A0, 0x40006a0c -.set CYREG_B1_UDB07_08_A0, 0x40006a0e -.set CYREG_B1_UDB08_09_A0, 0x40006a10 -.set CYREG_B1_UDB09_10_A0, 0x40006a12 -.set CYREG_B1_UDB10_11_A0, 0x40006a14 -.set CYREG_B1_UDB11_12_A0, 0x40006a16 -.set CYREG_B1_UDB04_05_A1, 0x40006a28 -.set CYREG_B1_UDB05_06_A1, 0x40006a2a -.set CYREG_B1_UDB06_07_A1, 0x40006a2c -.set CYREG_B1_UDB07_08_A1, 0x40006a2e -.set CYREG_B1_UDB08_09_A1, 0x40006a30 -.set CYREG_B1_UDB09_10_A1, 0x40006a32 -.set CYREG_B1_UDB10_11_A1, 0x40006a34 -.set CYREG_B1_UDB11_12_A1, 0x40006a36 -.set CYREG_B1_UDB04_05_D0, 0x40006a48 -.set CYREG_B1_UDB05_06_D0, 0x40006a4a -.set CYREG_B1_UDB06_07_D0, 0x40006a4c -.set CYREG_B1_UDB07_08_D0, 0x40006a4e -.set CYREG_B1_UDB08_09_D0, 0x40006a50 -.set CYREG_B1_UDB09_10_D0, 0x40006a52 -.set CYREG_B1_UDB10_11_D0, 0x40006a54 -.set CYREG_B1_UDB11_12_D0, 0x40006a56 -.set CYREG_B1_UDB04_05_D1, 0x40006a68 -.set CYREG_B1_UDB05_06_D1, 0x40006a6a -.set CYREG_B1_UDB06_07_D1, 0x40006a6c -.set CYREG_B1_UDB07_08_D1, 0x40006a6e -.set CYREG_B1_UDB08_09_D1, 0x40006a70 -.set CYREG_B1_UDB09_10_D1, 0x40006a72 -.set CYREG_B1_UDB10_11_D1, 0x40006a74 -.set CYREG_B1_UDB11_12_D1, 0x40006a76 -.set CYREG_B1_UDB04_05_F0, 0x40006a88 -.set CYREG_B1_UDB05_06_F0, 0x40006a8a -.set CYREG_B1_UDB06_07_F0, 0x40006a8c -.set CYREG_B1_UDB07_08_F0, 0x40006a8e -.set CYREG_B1_UDB08_09_F0, 0x40006a90 -.set CYREG_B1_UDB09_10_F0, 0x40006a92 -.set CYREG_B1_UDB10_11_F0, 0x40006a94 -.set CYREG_B1_UDB11_12_F0, 0x40006a96 -.set CYREG_B1_UDB04_05_F1, 0x40006aa8 -.set CYREG_B1_UDB05_06_F1, 0x40006aaa -.set CYREG_B1_UDB06_07_F1, 0x40006aac -.set CYREG_B1_UDB07_08_F1, 0x40006aae -.set CYREG_B1_UDB08_09_F1, 0x40006ab0 -.set CYREG_B1_UDB09_10_F1, 0x40006ab2 -.set CYREG_B1_UDB10_11_F1, 0x40006ab4 -.set CYREG_B1_UDB11_12_F1, 0x40006ab6 -.set CYREG_B1_UDB04_05_ST, 0x40006ac8 -.set CYREG_B1_UDB05_06_ST, 0x40006aca -.set CYREG_B1_UDB06_07_ST, 0x40006acc -.set CYREG_B1_UDB07_08_ST, 0x40006ace -.set CYREG_B1_UDB08_09_ST, 0x40006ad0 -.set CYREG_B1_UDB09_10_ST, 0x40006ad2 -.set CYREG_B1_UDB10_11_ST, 0x40006ad4 -.set CYREG_B1_UDB11_12_ST, 0x40006ad6 -.set CYREG_B1_UDB04_05_CTL, 0x40006ae8 -.set CYREG_B1_UDB05_06_CTL, 0x40006aea -.set CYREG_B1_UDB06_07_CTL, 0x40006aec -.set CYREG_B1_UDB07_08_CTL, 0x40006aee -.set CYREG_B1_UDB08_09_CTL, 0x40006af0 -.set CYREG_B1_UDB09_10_CTL, 0x40006af2 -.set CYREG_B1_UDB10_11_CTL, 0x40006af4 -.set CYREG_B1_UDB11_12_CTL, 0x40006af6 -.set CYREG_B1_UDB04_05_MSK, 0x40006b08 -.set CYREG_B1_UDB05_06_MSK, 0x40006b0a -.set CYREG_B1_UDB06_07_MSK, 0x40006b0c -.set CYREG_B1_UDB07_08_MSK, 0x40006b0e -.set CYREG_B1_UDB08_09_MSK, 0x40006b10 -.set CYREG_B1_UDB09_10_MSK, 0x40006b12 -.set CYREG_B1_UDB10_11_MSK, 0x40006b14 -.set CYREG_B1_UDB11_12_MSK, 0x40006b16 -.set CYREG_B1_UDB04_05_ACTL, 0x40006b28 -.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a -.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c -.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e -.set CYREG_B1_UDB08_09_ACTL, 0x40006b30 -.set CYREG_B1_UDB09_10_ACTL, 0x40006b32 -.set CYREG_B1_UDB10_11_ACTL, 0x40006b34 -.set CYREG_B1_UDB11_12_ACTL, 0x40006b36 -.set CYREG_B1_UDB04_05_MC, 0x40006b48 -.set CYREG_B1_UDB05_06_MC, 0x40006b4a -.set CYREG_B1_UDB06_07_MC, 0x40006b4c -.set CYREG_B1_UDB07_08_MC, 0x40006b4e -.set CYREG_B1_UDB08_09_MC, 0x40006b50 -.set CYREG_B1_UDB09_10_MC, 0x40006b52 -.set CYREG_B1_UDB10_11_MC, 0x40006b54 -.set CYREG_B1_UDB11_12_MC, 0x40006b56 -.set CYDEV_PHUB_BASE, 0x40007000 -.set CYDEV_PHUB_SIZE, 0x00000c00 -.set CYREG_PHUB_CFG, 0x40007000 -.set CYREG_PHUB_ERR, 0x40007004 -.set CYREG_PHUB_ERR_ADR, 0x40007008 -.set CYDEV_PHUB_CH0_BASE, 0x40007010 -.set CYDEV_PHUB_CH0_SIZE, 0x0000000c -.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010 -.set CYREG_PHUB_CH0_ACTION, 0x40007014 -.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018 -.set CYDEV_PHUB_CH1_BASE, 0x40007020 -.set CYDEV_PHUB_CH1_SIZE, 0x0000000c -.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020 -.set CYREG_PHUB_CH1_ACTION, 0x40007024 -.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028 -.set CYDEV_PHUB_CH2_BASE, 0x40007030 -.set CYDEV_PHUB_CH2_SIZE, 0x0000000c -.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030 -.set CYREG_PHUB_CH2_ACTION, 0x40007034 -.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038 -.set CYDEV_PHUB_CH3_BASE, 0x40007040 -.set CYDEV_PHUB_CH3_SIZE, 0x0000000c -.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040 -.set CYREG_PHUB_CH3_ACTION, 0x40007044 -.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048 -.set CYDEV_PHUB_CH4_BASE, 0x40007050 -.set CYDEV_PHUB_CH4_SIZE, 0x0000000c -.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050 -.set CYREG_PHUB_CH4_ACTION, 0x40007054 -.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058 -.set CYDEV_PHUB_CH5_BASE, 0x40007060 -.set CYDEV_PHUB_CH5_SIZE, 0x0000000c -.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060 -.set CYREG_PHUB_CH5_ACTION, 0x40007064 -.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068 -.set CYDEV_PHUB_CH6_BASE, 0x40007070 -.set CYDEV_PHUB_CH6_SIZE, 0x0000000c -.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070 -.set CYREG_PHUB_CH6_ACTION, 0x40007074 -.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078 -.set CYDEV_PHUB_CH7_BASE, 0x40007080 -.set CYDEV_PHUB_CH7_SIZE, 0x0000000c -.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080 -.set CYREG_PHUB_CH7_ACTION, 0x40007084 -.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088 -.set CYDEV_PHUB_CH8_BASE, 0x40007090 -.set CYDEV_PHUB_CH8_SIZE, 0x0000000c -.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090 -.set CYREG_PHUB_CH8_ACTION, 0x40007094 -.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098 -.set CYDEV_PHUB_CH9_BASE, 0x400070a0 -.set CYDEV_PHUB_CH9_SIZE, 0x0000000c -.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0 -.set CYREG_PHUB_CH9_ACTION, 0x400070a4 -.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8 -.set CYDEV_PHUB_CH10_BASE, 0x400070b0 -.set CYDEV_PHUB_CH10_SIZE, 0x0000000c -.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0 -.set CYREG_PHUB_CH10_ACTION, 0x400070b4 -.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8 -.set CYDEV_PHUB_CH11_BASE, 0x400070c0 -.set CYDEV_PHUB_CH11_SIZE, 0x0000000c -.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0 -.set CYREG_PHUB_CH11_ACTION, 0x400070c4 -.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8 -.set CYDEV_PHUB_CH12_BASE, 0x400070d0 -.set CYDEV_PHUB_CH12_SIZE, 0x0000000c -.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0 -.set CYREG_PHUB_CH12_ACTION, 0x400070d4 -.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8 -.set CYDEV_PHUB_CH13_BASE, 0x400070e0 -.set CYDEV_PHUB_CH13_SIZE, 0x0000000c -.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0 -.set CYREG_PHUB_CH13_ACTION, 0x400070e4 -.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8 -.set CYDEV_PHUB_CH14_BASE, 0x400070f0 -.set CYDEV_PHUB_CH14_SIZE, 0x0000000c -.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0 -.set CYREG_PHUB_CH14_ACTION, 0x400070f4 -.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8 -.set CYDEV_PHUB_CH15_BASE, 0x40007100 -.set CYDEV_PHUB_CH15_SIZE, 0x0000000c -.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100 -.set CYREG_PHUB_CH15_ACTION, 0x40007104 -.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108 -.set CYDEV_PHUB_CH16_BASE, 0x40007110 -.set CYDEV_PHUB_CH16_SIZE, 0x0000000c -.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110 -.set CYREG_PHUB_CH16_ACTION, 0x40007114 -.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118 -.set CYDEV_PHUB_CH17_BASE, 0x40007120 -.set CYDEV_PHUB_CH17_SIZE, 0x0000000c -.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120 -.set CYREG_PHUB_CH17_ACTION, 0x40007124 -.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128 -.set CYDEV_PHUB_CH18_BASE, 0x40007130 -.set CYDEV_PHUB_CH18_SIZE, 0x0000000c -.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130 -.set CYREG_PHUB_CH18_ACTION, 0x40007134 -.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138 -.set CYDEV_PHUB_CH19_BASE, 0x40007140 -.set CYDEV_PHUB_CH19_SIZE, 0x0000000c -.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140 -.set CYREG_PHUB_CH19_ACTION, 0x40007144 -.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148 -.set CYDEV_PHUB_CH20_BASE, 0x40007150 -.set CYDEV_PHUB_CH20_SIZE, 0x0000000c -.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150 -.set CYREG_PHUB_CH20_ACTION, 0x40007154 -.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158 -.set CYDEV_PHUB_CH21_BASE, 0x40007160 -.set CYDEV_PHUB_CH21_SIZE, 0x0000000c -.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160 -.set CYREG_PHUB_CH21_ACTION, 0x40007164 -.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168 -.set CYDEV_PHUB_CH22_BASE, 0x40007170 -.set CYDEV_PHUB_CH22_SIZE, 0x0000000c -.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170 -.set CYREG_PHUB_CH22_ACTION, 0x40007174 -.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178 -.set CYDEV_PHUB_CH23_BASE, 0x40007180 -.set CYDEV_PHUB_CH23_SIZE, 0x0000000c -.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180 -.set CYREG_PHUB_CH23_ACTION, 0x40007184 -.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188 -.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 -.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600 -.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604 -.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 -.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608 -.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c -.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 -.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610 -.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614 -.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 -.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618 -.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c -.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 -.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620 -.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624 -.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 -.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628 -.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c -.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 -.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630 -.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634 -.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 -.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638 -.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c -.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 -.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640 -.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644 -.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 -.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648 -.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c -.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 -.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650 -.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654 -.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 -.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658 -.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c -.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 -.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660 -.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664 -.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 -.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668 -.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c -.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 -.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670 -.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674 -.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 -.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678 -.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c -.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 -.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680 -.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684 -.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 -.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688 -.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c -.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 -.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690 -.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694 -.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 -.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698 -.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c -.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 -.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0 -.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4 -.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 -.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8 -.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac -.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 -.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0 -.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4 -.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 -.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 -.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8 -.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc -.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 -.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800 -.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804 -.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 -.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808 -.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c -.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 -.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810 -.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814 -.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 -.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818 -.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c -.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 -.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820 -.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824 -.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 -.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828 -.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c -.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 -.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830 -.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834 -.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 -.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838 -.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c -.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 -.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840 -.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844 -.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 -.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848 -.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c -.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 -.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850 -.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854 -.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 -.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858 -.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c -.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 -.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860 -.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864 -.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 -.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868 -.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c -.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 -.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870 -.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874 -.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 -.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878 -.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c -.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 -.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880 -.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884 -.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 -.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888 -.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c -.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 -.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890 -.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894 -.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 -.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898 -.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c -.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 -.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 -.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 -.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 -.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 -.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac -.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 -.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 -.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 -.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 -.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 -.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc -.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 -.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 -.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 -.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 -.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 -.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc -.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 -.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 -.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 -.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 -.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 -.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc -.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 -.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 -.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 -.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 -.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 -.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec -.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 -.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 -.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 -.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 -.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 -.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc -.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 -.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900 -.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904 -.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 -.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908 -.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c -.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 -.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910 -.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914 -.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 -.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918 -.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c -.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 -.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920 -.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924 -.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 -.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928 -.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c -.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 -.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930 -.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934 -.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 -.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938 -.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c -.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 -.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940 -.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944 -.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 -.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948 -.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c -.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 -.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950 -.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954 -.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 -.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958 -.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c -.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 -.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960 -.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964 -.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 -.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968 -.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c -.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 -.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970 -.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974 -.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 -.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978 -.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c -.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 -.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980 -.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984 -.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 -.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988 -.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c -.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 -.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990 -.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994 -.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 -.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998 -.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c -.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 -.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 -.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 -.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 -.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 -.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac -.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 -.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 -.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 -.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 -.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 -.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc -.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 -.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 -.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 -.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 -.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 -.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc -.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 -.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 -.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 -.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 -.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 -.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc -.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 -.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 -.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 -.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 -.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 -.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec -.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 -.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 -.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 -.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 -.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 -.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc -.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 -.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 -.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 -.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 -.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 -.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c -.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 -.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 -.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 -.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 -.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 -.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c -.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 -.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 -.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 -.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 -.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 -.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c -.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 -.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 -.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 -.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 -.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 -.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c -.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 -.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 -.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 -.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 -.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 -.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c -.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 -.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 -.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 -.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 -.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 -.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c -.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 -.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 -.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 -.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 -.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 -.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c -.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 -.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 -.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 -.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 -.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 -.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c -.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 -.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 -.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 -.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 -.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 -.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c -.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 -.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 -.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 -.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 -.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 -.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c -.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 -.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 -.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 -.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 -.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 -.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac -.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 -.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 -.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 -.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 -.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 -.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc -.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 -.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 -.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 -.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 -.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 -.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc -.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 -.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 -.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 -.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 -.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 -.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc -.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 -.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 -.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 -.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 -.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 -.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec -.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 -.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 -.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 -.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 -.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 -.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc -.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 -.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 -.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 -.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 -.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 -.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c -.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 -.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 -.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 -.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 -.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 -.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c -.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 -.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 -.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 -.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 -.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 -.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c -.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 -.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 -.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 -.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 -.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 -.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c -.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 -.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 -.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 -.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 -.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 -.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c -.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 -.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 -.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 -.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 -.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 -.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c -.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 -.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 -.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 -.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 -.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 -.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c -.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 -.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 -.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 -.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 -.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 -.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c -.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 -.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 -.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 -.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 -.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 -.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c -.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 -.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 -.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 -.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 -.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 -.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c -.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 -.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 -.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 -.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 -.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 -.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac -.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 -.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 -.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 -.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 -.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 -.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc -.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 -.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 -.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 -.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 -.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 -.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc -.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 -.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 -.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 -.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 -.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 -.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc -.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 -.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 -.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 -.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 -.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 -.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec -.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 -.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 -.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 -.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 -.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 -.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 -.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc -.set CYDEV_EE_BASE, 0x40008000 -.set CYDEV_EE_SIZE, 0x00000800 -.set CYREG_EE_DATA_MBASE, 0x40008000 -.set CYREG_EE_DATA_MSIZE, 0x00000800 -.set CYDEV_CAN0_BASE, 0x4000a000 -.set CYDEV_CAN0_SIZE, 0x000002a0 -.set CYDEV_CAN0_CSR_BASE, 0x4000a000 -.set CYDEV_CAN0_CSR_SIZE, 0x00000018 -.set CYREG_CAN0_CSR_INT_SR, 0x4000a000 -.set CYREG_CAN0_CSR_INT_EN, 0x4000a004 -.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008 -.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c -.set CYREG_CAN0_CSR_CMD, 0x4000a010 -.set CYREG_CAN0_CSR_CFG, 0x4000a014 -.set CYDEV_CAN0_TX0_BASE, 0x4000a020 -.set CYDEV_CAN0_TX0_SIZE, 0x00000010 -.set CYREG_CAN0_TX0_CMD, 0x4000a020 -.set CYREG_CAN0_TX0_ID, 0x4000a024 -.set CYREG_CAN0_TX0_DH, 0x4000a028 -.set CYREG_CAN0_TX0_DL, 0x4000a02c -.set CYDEV_CAN0_TX1_BASE, 0x4000a030 -.set CYDEV_CAN0_TX1_SIZE, 0x00000010 -.set CYREG_CAN0_TX1_CMD, 0x4000a030 -.set CYREG_CAN0_TX1_ID, 0x4000a034 -.set CYREG_CAN0_TX1_DH, 0x4000a038 -.set CYREG_CAN0_TX1_DL, 0x4000a03c -.set CYDEV_CAN0_TX2_BASE, 0x4000a040 -.set CYDEV_CAN0_TX2_SIZE, 0x00000010 -.set CYREG_CAN0_TX2_CMD, 0x4000a040 -.set CYREG_CAN0_TX2_ID, 0x4000a044 -.set CYREG_CAN0_TX2_DH, 0x4000a048 -.set CYREG_CAN0_TX2_DL, 0x4000a04c -.set CYDEV_CAN0_TX3_BASE, 0x4000a050 -.set CYDEV_CAN0_TX3_SIZE, 0x00000010 -.set CYREG_CAN0_TX3_CMD, 0x4000a050 -.set CYREG_CAN0_TX3_ID, 0x4000a054 -.set CYREG_CAN0_TX3_DH, 0x4000a058 -.set CYREG_CAN0_TX3_DL, 0x4000a05c -.set CYDEV_CAN0_TX4_BASE, 0x4000a060 -.set CYDEV_CAN0_TX4_SIZE, 0x00000010 -.set CYREG_CAN0_TX4_CMD, 0x4000a060 -.set CYREG_CAN0_TX4_ID, 0x4000a064 -.set CYREG_CAN0_TX4_DH, 0x4000a068 -.set CYREG_CAN0_TX4_DL, 0x4000a06c -.set CYDEV_CAN0_TX5_BASE, 0x4000a070 -.set CYDEV_CAN0_TX5_SIZE, 0x00000010 -.set CYREG_CAN0_TX5_CMD, 0x4000a070 -.set CYREG_CAN0_TX5_ID, 0x4000a074 -.set CYREG_CAN0_TX5_DH, 0x4000a078 -.set CYREG_CAN0_TX5_DL, 0x4000a07c -.set CYDEV_CAN0_TX6_BASE, 0x4000a080 -.set CYDEV_CAN0_TX6_SIZE, 0x00000010 -.set CYREG_CAN0_TX6_CMD, 0x4000a080 -.set CYREG_CAN0_TX6_ID, 0x4000a084 -.set CYREG_CAN0_TX6_DH, 0x4000a088 -.set CYREG_CAN0_TX6_DL, 0x4000a08c -.set CYDEV_CAN0_TX7_BASE, 0x4000a090 -.set CYDEV_CAN0_TX7_SIZE, 0x00000010 -.set CYREG_CAN0_TX7_CMD, 0x4000a090 -.set CYREG_CAN0_TX7_ID, 0x4000a094 -.set CYREG_CAN0_TX7_DH, 0x4000a098 -.set CYREG_CAN0_TX7_DL, 0x4000a09c -.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 -.set CYDEV_CAN0_RX0_SIZE, 0x00000020 -.set CYREG_CAN0_RX0_CMD, 0x4000a0a0 -.set CYREG_CAN0_RX0_ID, 0x4000a0a4 -.set CYREG_CAN0_RX0_DH, 0x4000a0a8 -.set CYREG_CAN0_RX0_DL, 0x4000a0ac -.set CYREG_CAN0_RX0_AMR, 0x4000a0b0 -.set CYREG_CAN0_RX0_ACR, 0x4000a0b4 -.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8 -.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc -.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 -.set CYDEV_CAN0_RX1_SIZE, 0x00000020 -.set CYREG_CAN0_RX1_CMD, 0x4000a0c0 -.set CYREG_CAN0_RX1_ID, 0x4000a0c4 -.set CYREG_CAN0_RX1_DH, 0x4000a0c8 -.set CYREG_CAN0_RX1_DL, 0x4000a0cc -.set CYREG_CAN0_RX1_AMR, 0x4000a0d0 -.set CYREG_CAN0_RX1_ACR, 0x4000a0d4 -.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8 -.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc -.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 -.set CYDEV_CAN0_RX2_SIZE, 0x00000020 -.set CYREG_CAN0_RX2_CMD, 0x4000a0e0 -.set CYREG_CAN0_RX2_ID, 0x4000a0e4 -.set CYREG_CAN0_RX2_DH, 0x4000a0e8 -.set CYREG_CAN0_RX2_DL, 0x4000a0ec -.set CYREG_CAN0_RX2_AMR, 0x4000a0f0 -.set CYREG_CAN0_RX2_ACR, 0x4000a0f4 -.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8 -.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc -.set CYDEV_CAN0_RX3_BASE, 0x4000a100 -.set CYDEV_CAN0_RX3_SIZE, 0x00000020 -.set CYREG_CAN0_RX3_CMD, 0x4000a100 -.set CYREG_CAN0_RX3_ID, 0x4000a104 -.set CYREG_CAN0_RX3_DH, 0x4000a108 -.set CYREG_CAN0_RX3_DL, 0x4000a10c -.set CYREG_CAN0_RX3_AMR, 0x4000a110 -.set CYREG_CAN0_RX3_ACR, 0x4000a114 -.set CYREG_CAN0_RX3_AMRD, 0x4000a118 -.set CYREG_CAN0_RX3_ACRD, 0x4000a11c -.set CYDEV_CAN0_RX4_BASE, 0x4000a120 -.set CYDEV_CAN0_RX4_SIZE, 0x00000020 -.set CYREG_CAN0_RX4_CMD, 0x4000a120 -.set CYREG_CAN0_RX4_ID, 0x4000a124 -.set CYREG_CAN0_RX4_DH, 0x4000a128 -.set CYREG_CAN0_RX4_DL, 0x4000a12c -.set CYREG_CAN0_RX4_AMR, 0x4000a130 -.set CYREG_CAN0_RX4_ACR, 0x4000a134 -.set CYREG_CAN0_RX4_AMRD, 0x4000a138 -.set CYREG_CAN0_RX4_ACRD, 0x4000a13c -.set CYDEV_CAN0_RX5_BASE, 0x4000a140 -.set CYDEV_CAN0_RX5_SIZE, 0x00000020 -.set CYREG_CAN0_RX5_CMD, 0x4000a140 -.set CYREG_CAN0_RX5_ID, 0x4000a144 -.set CYREG_CAN0_RX5_DH, 0x4000a148 -.set CYREG_CAN0_RX5_DL, 0x4000a14c -.set CYREG_CAN0_RX5_AMR, 0x4000a150 -.set CYREG_CAN0_RX5_ACR, 0x4000a154 -.set CYREG_CAN0_RX5_AMRD, 0x4000a158 -.set CYREG_CAN0_RX5_ACRD, 0x4000a15c -.set CYDEV_CAN0_RX6_BASE, 0x4000a160 -.set CYDEV_CAN0_RX6_SIZE, 0x00000020 -.set CYREG_CAN0_RX6_CMD, 0x4000a160 -.set CYREG_CAN0_RX6_ID, 0x4000a164 -.set CYREG_CAN0_RX6_DH, 0x4000a168 -.set CYREG_CAN0_RX6_DL, 0x4000a16c -.set CYREG_CAN0_RX6_AMR, 0x4000a170 -.set CYREG_CAN0_RX6_ACR, 0x4000a174 -.set CYREG_CAN0_RX6_AMRD, 0x4000a178 -.set CYREG_CAN0_RX6_ACRD, 0x4000a17c -.set CYDEV_CAN0_RX7_BASE, 0x4000a180 -.set CYDEV_CAN0_RX7_SIZE, 0x00000020 -.set CYREG_CAN0_RX7_CMD, 0x4000a180 -.set CYREG_CAN0_RX7_ID, 0x4000a184 -.set CYREG_CAN0_RX7_DH, 0x4000a188 -.set CYREG_CAN0_RX7_DL, 0x4000a18c -.set CYREG_CAN0_RX7_AMR, 0x4000a190 -.set CYREG_CAN0_RX7_ACR, 0x4000a194 -.set CYREG_CAN0_RX7_AMRD, 0x4000a198 -.set CYREG_CAN0_RX7_ACRD, 0x4000a19c -.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 -.set CYDEV_CAN0_RX8_SIZE, 0x00000020 -.set CYREG_CAN0_RX8_CMD, 0x4000a1a0 -.set CYREG_CAN0_RX8_ID, 0x4000a1a4 -.set CYREG_CAN0_RX8_DH, 0x4000a1a8 -.set CYREG_CAN0_RX8_DL, 0x4000a1ac -.set CYREG_CAN0_RX8_AMR, 0x4000a1b0 -.set CYREG_CAN0_RX8_ACR, 0x4000a1b4 -.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8 -.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc -.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 -.set CYDEV_CAN0_RX9_SIZE, 0x00000020 -.set CYREG_CAN0_RX9_CMD, 0x4000a1c0 -.set CYREG_CAN0_RX9_ID, 0x4000a1c4 -.set CYREG_CAN0_RX9_DH, 0x4000a1c8 -.set CYREG_CAN0_RX9_DL, 0x4000a1cc -.set CYREG_CAN0_RX9_AMR, 0x4000a1d0 -.set CYREG_CAN0_RX9_ACR, 0x4000a1d4 -.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8 -.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc -.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 -.set CYDEV_CAN0_RX10_SIZE, 0x00000020 -.set CYREG_CAN0_RX10_CMD, 0x4000a1e0 -.set CYREG_CAN0_RX10_ID, 0x4000a1e4 -.set CYREG_CAN0_RX10_DH, 0x4000a1e8 -.set CYREG_CAN0_RX10_DL, 0x4000a1ec -.set CYREG_CAN0_RX10_AMR, 0x4000a1f0 -.set CYREG_CAN0_RX10_ACR, 0x4000a1f4 -.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8 -.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc -.set CYDEV_CAN0_RX11_BASE, 0x4000a200 -.set CYDEV_CAN0_RX11_SIZE, 0x00000020 -.set CYREG_CAN0_RX11_CMD, 0x4000a200 -.set CYREG_CAN0_RX11_ID, 0x4000a204 -.set CYREG_CAN0_RX11_DH, 0x4000a208 -.set CYREG_CAN0_RX11_DL, 0x4000a20c -.set CYREG_CAN0_RX11_AMR, 0x4000a210 -.set CYREG_CAN0_RX11_ACR, 0x4000a214 -.set CYREG_CAN0_RX11_AMRD, 0x4000a218 -.set CYREG_CAN0_RX11_ACRD, 0x4000a21c -.set CYDEV_CAN0_RX12_BASE, 0x4000a220 -.set CYDEV_CAN0_RX12_SIZE, 0x00000020 -.set CYREG_CAN0_RX12_CMD, 0x4000a220 -.set CYREG_CAN0_RX12_ID, 0x4000a224 -.set CYREG_CAN0_RX12_DH, 0x4000a228 -.set CYREG_CAN0_RX12_DL, 0x4000a22c -.set CYREG_CAN0_RX12_AMR, 0x4000a230 -.set CYREG_CAN0_RX12_ACR, 0x4000a234 -.set CYREG_CAN0_RX12_AMRD, 0x4000a238 -.set CYREG_CAN0_RX12_ACRD, 0x4000a23c -.set CYDEV_CAN0_RX13_BASE, 0x4000a240 -.set CYDEV_CAN0_RX13_SIZE, 0x00000020 -.set CYREG_CAN0_RX13_CMD, 0x4000a240 -.set CYREG_CAN0_RX13_ID, 0x4000a244 -.set CYREG_CAN0_RX13_DH, 0x4000a248 -.set CYREG_CAN0_RX13_DL, 0x4000a24c -.set CYREG_CAN0_RX13_AMR, 0x4000a250 -.set CYREG_CAN0_RX13_ACR, 0x4000a254 -.set CYREG_CAN0_RX13_AMRD, 0x4000a258 -.set CYREG_CAN0_RX13_ACRD, 0x4000a25c -.set CYDEV_CAN0_RX14_BASE, 0x4000a260 -.set CYDEV_CAN0_RX14_SIZE, 0x00000020 -.set CYREG_CAN0_RX14_CMD, 0x4000a260 -.set CYREG_CAN0_RX14_ID, 0x4000a264 -.set CYREG_CAN0_RX14_DH, 0x4000a268 -.set CYREG_CAN0_RX14_DL, 0x4000a26c -.set CYREG_CAN0_RX14_AMR, 0x4000a270 -.set CYREG_CAN0_RX14_ACR, 0x4000a274 -.set CYREG_CAN0_RX14_AMRD, 0x4000a278 -.set CYREG_CAN0_RX14_ACRD, 0x4000a27c -.set CYDEV_CAN0_RX15_BASE, 0x4000a280 -.set CYDEV_CAN0_RX15_SIZE, 0x00000020 -.set CYREG_CAN0_RX15_CMD, 0x4000a280 -.set CYREG_CAN0_RX15_ID, 0x4000a284 -.set CYREG_CAN0_RX15_DH, 0x4000a288 -.set CYREG_CAN0_RX15_DL, 0x4000a28c -.set CYREG_CAN0_RX15_AMR, 0x4000a290 -.set CYREG_CAN0_RX15_ACR, 0x4000a294 -.set CYREG_CAN0_RX15_AMRD, 0x4000a298 -.set CYREG_CAN0_RX15_ACRD, 0x4000a29c -.set CYDEV_DFB0_BASE, 0x4000c000 -.set CYDEV_DFB0_SIZE, 0x000007b5 -.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 -.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 -.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 -.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 -.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 -.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 -.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 -.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 -.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 -.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 -.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 -.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 -.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 -.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 -.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 -.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 -.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 -.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 -.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 -.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 -.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 -.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 -.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 -.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 -.set CYREG_DFB0_CR, 0x4000c780 -.set CYREG_DFB0_SR, 0x4000c784 -.set CYREG_DFB0_RAM_EN, 0x4000c788 -.set CYREG_DFB0_RAM_DIR, 0x4000c78c -.set CYREG_DFB0_SEMA, 0x4000c790 -.set CYREG_DFB0_DSI_CTRL, 0x4000c794 -.set CYREG_DFB0_INT_CTRL, 0x4000c798 -.set CYREG_DFB0_DMA_CTRL, 0x4000c79c -.set CYREG_DFB0_STAGEA, 0x4000c7a0 -.set CYREG_DFB0_STAGEAM, 0x4000c7a1 -.set CYREG_DFB0_STAGEAH, 0x4000c7a2 -.set CYREG_DFB0_STAGEB, 0x4000c7a4 -.set CYREG_DFB0_STAGEBM, 0x4000c7a5 -.set CYREG_DFB0_STAGEBH, 0x4000c7a6 -.set CYREG_DFB0_HOLDA, 0x4000c7a8 -.set CYREG_DFB0_HOLDAM, 0x4000c7a9 -.set CYREG_DFB0_HOLDAH, 0x4000c7aa -.set CYREG_DFB0_HOLDAS, 0x4000c7ab -.set CYREG_DFB0_HOLDB, 0x4000c7ac -.set CYREG_DFB0_HOLDBM, 0x4000c7ad -.set CYREG_DFB0_HOLDBH, 0x4000c7ae -.set CYREG_DFB0_HOLDBS, 0x4000c7af -.set CYREG_DFB0_COHER, 0x4000c7b0 -.set CYREG_DFB0_DALIGN, 0x4000c7b4 -.set CYDEV_UCFG_BASE, 0x40010000 -.set CYDEV_UCFG_SIZE, 0x00005040 -.set CYDEV_UCFG_B0_BASE, 0x40010000 -.set CYDEV_UCFG_B0_SIZE, 0x00000fef -.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 -.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 -.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 -.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000 -.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004 -.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008 -.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c -.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010 -.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014 -.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018 -.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c -.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020 -.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024 -.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028 -.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c -.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030 -.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032 -.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034 -.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036 -.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 -.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a -.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c -.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e -.set CYREG_B0_P0_U0_CFG0, 0x40010040 -.set CYREG_B0_P0_U0_CFG1, 0x40010041 -.set CYREG_B0_P0_U0_CFG2, 0x40010042 -.set CYREG_B0_P0_U0_CFG3, 0x40010043 -.set CYREG_B0_P0_U0_CFG4, 0x40010044 -.set CYREG_B0_P0_U0_CFG5, 0x40010045 -.set CYREG_B0_P0_U0_CFG6, 0x40010046 -.set CYREG_B0_P0_U0_CFG7, 0x40010047 -.set CYREG_B0_P0_U0_CFG8, 0x40010048 -.set CYREG_B0_P0_U0_CFG9, 0x40010049 -.set CYREG_B0_P0_U0_CFG10, 0x4001004a -.set CYREG_B0_P0_U0_CFG11, 0x4001004b -.set CYREG_B0_P0_U0_CFG12, 0x4001004c -.set CYREG_B0_P0_U0_CFG13, 0x4001004d -.set CYREG_B0_P0_U0_CFG14, 0x4001004e -.set CYREG_B0_P0_U0_CFG15, 0x4001004f -.set CYREG_B0_P0_U0_CFG16, 0x40010050 -.set CYREG_B0_P0_U0_CFG17, 0x40010051 -.set CYREG_B0_P0_U0_CFG18, 0x40010052 -.set CYREG_B0_P0_U0_CFG19, 0x40010053 -.set CYREG_B0_P0_U0_CFG20, 0x40010054 -.set CYREG_B0_P0_U0_CFG21, 0x40010055 -.set CYREG_B0_P0_U0_CFG22, 0x40010056 -.set CYREG_B0_P0_U0_CFG23, 0x40010057 -.set CYREG_B0_P0_U0_CFG24, 0x40010058 -.set CYREG_B0_P0_U0_CFG25, 0x40010059 -.set CYREG_B0_P0_U0_CFG26, 0x4001005a -.set CYREG_B0_P0_U0_CFG27, 0x4001005b -.set CYREG_B0_P0_U0_CFG28, 0x4001005c -.set CYREG_B0_P0_U0_CFG29, 0x4001005d -.set CYREG_B0_P0_U0_CFG30, 0x4001005e -.set CYREG_B0_P0_U0_CFG31, 0x4001005f -.set CYREG_B0_P0_U0_DCFG0, 0x40010060 -.set CYREG_B0_P0_U0_DCFG1, 0x40010062 -.set CYREG_B0_P0_U0_DCFG2, 0x40010064 -.set CYREG_B0_P0_U0_DCFG3, 0x40010066 -.set CYREG_B0_P0_U0_DCFG4, 0x40010068 -.set CYREG_B0_P0_U0_DCFG5, 0x4001006a -.set CYREG_B0_P0_U0_DCFG6, 0x4001006c -.set CYREG_B0_P0_U0_DCFG7, 0x4001006e -.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 -.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 -.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080 -.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084 -.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088 -.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c -.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090 -.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094 -.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098 -.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c -.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0 -.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4 -.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8 -.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac -.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0 -.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2 -.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4 -.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6 -.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 -.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba -.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc -.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be -.set CYREG_B0_P0_U1_CFG0, 0x400100c0 -.set CYREG_B0_P0_U1_CFG1, 0x400100c1 -.set CYREG_B0_P0_U1_CFG2, 0x400100c2 -.set CYREG_B0_P0_U1_CFG3, 0x400100c3 -.set CYREG_B0_P0_U1_CFG4, 0x400100c4 -.set CYREG_B0_P0_U1_CFG5, 0x400100c5 -.set CYREG_B0_P0_U1_CFG6, 0x400100c6 -.set CYREG_B0_P0_U1_CFG7, 0x400100c7 -.set CYREG_B0_P0_U1_CFG8, 0x400100c8 -.set CYREG_B0_P0_U1_CFG9, 0x400100c9 -.set CYREG_B0_P0_U1_CFG10, 0x400100ca -.set CYREG_B0_P0_U1_CFG11, 0x400100cb -.set CYREG_B0_P0_U1_CFG12, 0x400100cc -.set CYREG_B0_P0_U1_CFG13, 0x400100cd -.set CYREG_B0_P0_U1_CFG14, 0x400100ce -.set CYREG_B0_P0_U1_CFG15, 0x400100cf -.set CYREG_B0_P0_U1_CFG16, 0x400100d0 -.set CYREG_B0_P0_U1_CFG17, 0x400100d1 -.set CYREG_B0_P0_U1_CFG18, 0x400100d2 -.set CYREG_B0_P0_U1_CFG19, 0x400100d3 -.set CYREG_B0_P0_U1_CFG20, 0x400100d4 -.set CYREG_B0_P0_U1_CFG21, 0x400100d5 -.set CYREG_B0_P0_U1_CFG22, 0x400100d6 -.set CYREG_B0_P0_U1_CFG23, 0x400100d7 -.set CYREG_B0_P0_U1_CFG24, 0x400100d8 -.set CYREG_B0_P0_U1_CFG25, 0x400100d9 -.set CYREG_B0_P0_U1_CFG26, 0x400100da -.set CYREG_B0_P0_U1_CFG27, 0x400100db -.set CYREG_B0_P0_U1_CFG28, 0x400100dc -.set CYREG_B0_P0_U1_CFG29, 0x400100dd -.set CYREG_B0_P0_U1_CFG30, 0x400100de -.set CYREG_B0_P0_U1_CFG31, 0x400100df -.set CYREG_B0_P0_U1_DCFG0, 0x400100e0 -.set CYREG_B0_P0_U1_DCFG1, 0x400100e2 -.set CYREG_B0_P0_U1_DCFG2, 0x400100e4 -.set CYREG_B0_P0_U1_DCFG3, 0x400100e6 -.set CYREG_B0_P0_U1_DCFG4, 0x400100e8 -.set CYREG_B0_P0_U1_DCFG5, 0x400100ea -.set CYREG_B0_P0_U1_DCFG6, 0x400100ec -.set CYREG_B0_P0_U1_DCFG7, 0x400100ee -.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 -.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 -.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 -.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 -.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200 -.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204 -.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208 -.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c -.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210 -.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214 -.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218 -.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c -.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220 -.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224 -.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228 -.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c -.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230 -.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232 -.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234 -.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236 -.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 -.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a -.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c -.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e -.set CYREG_B0_P1_U0_CFG0, 0x40010240 -.set CYREG_B0_P1_U0_CFG1, 0x40010241 -.set CYREG_B0_P1_U0_CFG2, 0x40010242 -.set CYREG_B0_P1_U0_CFG3, 0x40010243 -.set CYREG_B0_P1_U0_CFG4, 0x40010244 -.set CYREG_B0_P1_U0_CFG5, 0x40010245 -.set CYREG_B0_P1_U0_CFG6, 0x40010246 -.set CYREG_B0_P1_U0_CFG7, 0x40010247 -.set CYREG_B0_P1_U0_CFG8, 0x40010248 -.set CYREG_B0_P1_U0_CFG9, 0x40010249 -.set CYREG_B0_P1_U0_CFG10, 0x4001024a -.set CYREG_B0_P1_U0_CFG11, 0x4001024b -.set CYREG_B0_P1_U0_CFG12, 0x4001024c -.set CYREG_B0_P1_U0_CFG13, 0x4001024d -.set CYREG_B0_P1_U0_CFG14, 0x4001024e -.set CYREG_B0_P1_U0_CFG15, 0x4001024f -.set CYREG_B0_P1_U0_CFG16, 0x40010250 -.set CYREG_B0_P1_U0_CFG17, 0x40010251 -.set CYREG_B0_P1_U0_CFG18, 0x40010252 -.set CYREG_B0_P1_U0_CFG19, 0x40010253 -.set CYREG_B0_P1_U0_CFG20, 0x40010254 -.set CYREG_B0_P1_U0_CFG21, 0x40010255 -.set CYREG_B0_P1_U0_CFG22, 0x40010256 -.set CYREG_B0_P1_U0_CFG23, 0x40010257 -.set CYREG_B0_P1_U0_CFG24, 0x40010258 -.set CYREG_B0_P1_U0_CFG25, 0x40010259 -.set CYREG_B0_P1_U0_CFG26, 0x4001025a -.set CYREG_B0_P1_U0_CFG27, 0x4001025b -.set CYREG_B0_P1_U0_CFG28, 0x4001025c -.set CYREG_B0_P1_U0_CFG29, 0x4001025d -.set CYREG_B0_P1_U0_CFG30, 0x4001025e -.set CYREG_B0_P1_U0_CFG31, 0x4001025f -.set CYREG_B0_P1_U0_DCFG0, 0x40010260 -.set CYREG_B0_P1_U0_DCFG1, 0x40010262 -.set CYREG_B0_P1_U0_DCFG2, 0x40010264 -.set CYREG_B0_P1_U0_DCFG3, 0x40010266 -.set CYREG_B0_P1_U0_DCFG4, 0x40010268 -.set CYREG_B0_P1_U0_DCFG5, 0x4001026a -.set CYREG_B0_P1_U0_DCFG6, 0x4001026c -.set CYREG_B0_P1_U0_DCFG7, 0x4001026e -.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 -.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 -.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280 -.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284 -.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288 -.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c -.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290 -.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294 -.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298 -.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c -.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0 -.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4 -.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8 -.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac -.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0 -.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2 -.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4 -.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6 -.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 -.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba -.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc -.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be -.set CYREG_B0_P1_U1_CFG0, 0x400102c0 -.set CYREG_B0_P1_U1_CFG1, 0x400102c1 -.set CYREG_B0_P1_U1_CFG2, 0x400102c2 -.set CYREG_B0_P1_U1_CFG3, 0x400102c3 -.set CYREG_B0_P1_U1_CFG4, 0x400102c4 -.set CYREG_B0_P1_U1_CFG5, 0x400102c5 -.set CYREG_B0_P1_U1_CFG6, 0x400102c6 -.set CYREG_B0_P1_U1_CFG7, 0x400102c7 -.set CYREG_B0_P1_U1_CFG8, 0x400102c8 -.set CYREG_B0_P1_U1_CFG9, 0x400102c9 -.set CYREG_B0_P1_U1_CFG10, 0x400102ca -.set CYREG_B0_P1_U1_CFG11, 0x400102cb -.set CYREG_B0_P1_U1_CFG12, 0x400102cc -.set CYREG_B0_P1_U1_CFG13, 0x400102cd -.set CYREG_B0_P1_U1_CFG14, 0x400102ce -.set CYREG_B0_P1_U1_CFG15, 0x400102cf -.set CYREG_B0_P1_U1_CFG16, 0x400102d0 -.set CYREG_B0_P1_U1_CFG17, 0x400102d1 -.set CYREG_B0_P1_U1_CFG18, 0x400102d2 -.set CYREG_B0_P1_U1_CFG19, 0x400102d3 -.set CYREG_B0_P1_U1_CFG20, 0x400102d4 -.set CYREG_B0_P1_U1_CFG21, 0x400102d5 -.set CYREG_B0_P1_U1_CFG22, 0x400102d6 -.set CYREG_B0_P1_U1_CFG23, 0x400102d7 -.set CYREG_B0_P1_U1_CFG24, 0x400102d8 -.set CYREG_B0_P1_U1_CFG25, 0x400102d9 -.set CYREG_B0_P1_U1_CFG26, 0x400102da -.set CYREG_B0_P1_U1_CFG27, 0x400102db -.set CYREG_B0_P1_U1_CFG28, 0x400102dc -.set CYREG_B0_P1_U1_CFG29, 0x400102dd -.set CYREG_B0_P1_U1_CFG30, 0x400102de -.set CYREG_B0_P1_U1_CFG31, 0x400102df -.set CYREG_B0_P1_U1_DCFG0, 0x400102e0 -.set CYREG_B0_P1_U1_DCFG1, 0x400102e2 -.set CYREG_B0_P1_U1_DCFG2, 0x400102e4 -.set CYREG_B0_P1_U1_DCFG3, 0x400102e6 -.set CYREG_B0_P1_U1_DCFG4, 0x400102e8 -.set CYREG_B0_P1_U1_DCFG5, 0x400102ea -.set CYREG_B0_P1_U1_DCFG6, 0x400102ec -.set CYREG_B0_P1_U1_DCFG7, 0x400102ee -.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 -.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 -.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 -.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 -.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400 -.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404 -.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408 -.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c -.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410 -.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414 -.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418 -.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c -.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420 -.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424 -.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428 -.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c -.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430 -.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432 -.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434 -.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436 -.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 -.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a -.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c -.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e -.set CYREG_B0_P2_U0_CFG0, 0x40010440 -.set CYREG_B0_P2_U0_CFG1, 0x40010441 -.set CYREG_B0_P2_U0_CFG2, 0x40010442 -.set CYREG_B0_P2_U0_CFG3, 0x40010443 -.set CYREG_B0_P2_U0_CFG4, 0x40010444 -.set CYREG_B0_P2_U0_CFG5, 0x40010445 -.set CYREG_B0_P2_U0_CFG6, 0x40010446 -.set CYREG_B0_P2_U0_CFG7, 0x40010447 -.set CYREG_B0_P2_U0_CFG8, 0x40010448 -.set CYREG_B0_P2_U0_CFG9, 0x40010449 -.set CYREG_B0_P2_U0_CFG10, 0x4001044a -.set CYREG_B0_P2_U0_CFG11, 0x4001044b -.set CYREG_B0_P2_U0_CFG12, 0x4001044c -.set CYREG_B0_P2_U0_CFG13, 0x4001044d -.set CYREG_B0_P2_U0_CFG14, 0x4001044e -.set CYREG_B0_P2_U0_CFG15, 0x4001044f -.set CYREG_B0_P2_U0_CFG16, 0x40010450 -.set CYREG_B0_P2_U0_CFG17, 0x40010451 -.set CYREG_B0_P2_U0_CFG18, 0x40010452 -.set CYREG_B0_P2_U0_CFG19, 0x40010453 -.set CYREG_B0_P2_U0_CFG20, 0x40010454 -.set CYREG_B0_P2_U0_CFG21, 0x40010455 -.set CYREG_B0_P2_U0_CFG22, 0x40010456 -.set CYREG_B0_P2_U0_CFG23, 0x40010457 -.set CYREG_B0_P2_U0_CFG24, 0x40010458 -.set CYREG_B0_P2_U0_CFG25, 0x40010459 -.set CYREG_B0_P2_U0_CFG26, 0x4001045a -.set CYREG_B0_P2_U0_CFG27, 0x4001045b -.set CYREG_B0_P2_U0_CFG28, 0x4001045c -.set CYREG_B0_P2_U0_CFG29, 0x4001045d -.set CYREG_B0_P2_U0_CFG30, 0x4001045e -.set CYREG_B0_P2_U0_CFG31, 0x4001045f -.set CYREG_B0_P2_U0_DCFG0, 0x40010460 -.set CYREG_B0_P2_U0_DCFG1, 0x40010462 -.set CYREG_B0_P2_U0_DCFG2, 0x40010464 -.set CYREG_B0_P2_U0_DCFG3, 0x40010466 -.set CYREG_B0_P2_U0_DCFG4, 0x40010468 -.set CYREG_B0_P2_U0_DCFG5, 0x4001046a -.set CYREG_B0_P2_U0_DCFG6, 0x4001046c -.set CYREG_B0_P2_U0_DCFG7, 0x4001046e -.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 -.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 -.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480 -.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484 -.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488 -.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c -.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490 -.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494 -.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498 -.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c -.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0 -.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4 -.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8 -.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac -.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0 -.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2 -.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4 -.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6 -.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 -.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba -.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc -.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be -.set CYREG_B0_P2_U1_CFG0, 0x400104c0 -.set CYREG_B0_P2_U1_CFG1, 0x400104c1 -.set CYREG_B0_P2_U1_CFG2, 0x400104c2 -.set CYREG_B0_P2_U1_CFG3, 0x400104c3 -.set CYREG_B0_P2_U1_CFG4, 0x400104c4 -.set CYREG_B0_P2_U1_CFG5, 0x400104c5 -.set CYREG_B0_P2_U1_CFG6, 0x400104c6 -.set CYREG_B0_P2_U1_CFG7, 0x400104c7 -.set CYREG_B0_P2_U1_CFG8, 0x400104c8 -.set CYREG_B0_P2_U1_CFG9, 0x400104c9 -.set CYREG_B0_P2_U1_CFG10, 0x400104ca -.set CYREG_B0_P2_U1_CFG11, 0x400104cb -.set CYREG_B0_P2_U1_CFG12, 0x400104cc -.set CYREG_B0_P2_U1_CFG13, 0x400104cd -.set CYREG_B0_P2_U1_CFG14, 0x400104ce -.set CYREG_B0_P2_U1_CFG15, 0x400104cf -.set CYREG_B0_P2_U1_CFG16, 0x400104d0 -.set CYREG_B0_P2_U1_CFG17, 0x400104d1 -.set CYREG_B0_P2_U1_CFG18, 0x400104d2 -.set CYREG_B0_P2_U1_CFG19, 0x400104d3 -.set CYREG_B0_P2_U1_CFG20, 0x400104d4 -.set CYREG_B0_P2_U1_CFG21, 0x400104d5 -.set CYREG_B0_P2_U1_CFG22, 0x400104d6 -.set CYREG_B0_P2_U1_CFG23, 0x400104d7 -.set CYREG_B0_P2_U1_CFG24, 0x400104d8 -.set CYREG_B0_P2_U1_CFG25, 0x400104d9 -.set CYREG_B0_P2_U1_CFG26, 0x400104da -.set CYREG_B0_P2_U1_CFG27, 0x400104db -.set CYREG_B0_P2_U1_CFG28, 0x400104dc -.set CYREG_B0_P2_U1_CFG29, 0x400104dd -.set CYREG_B0_P2_U1_CFG30, 0x400104de -.set CYREG_B0_P2_U1_CFG31, 0x400104df -.set CYREG_B0_P2_U1_DCFG0, 0x400104e0 -.set CYREG_B0_P2_U1_DCFG1, 0x400104e2 -.set CYREG_B0_P2_U1_DCFG2, 0x400104e4 -.set CYREG_B0_P2_U1_DCFG3, 0x400104e6 -.set CYREG_B0_P2_U1_DCFG4, 0x400104e8 -.set CYREG_B0_P2_U1_DCFG5, 0x400104ea -.set CYREG_B0_P2_U1_DCFG6, 0x400104ec -.set CYREG_B0_P2_U1_DCFG7, 0x400104ee -.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 -.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 -.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 -.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 -.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600 -.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604 -.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608 -.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c -.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610 -.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614 -.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618 -.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c -.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620 -.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624 -.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628 -.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c -.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630 -.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632 -.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634 -.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636 -.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 -.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a -.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c -.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e -.set CYREG_B0_P3_U0_CFG0, 0x40010640 -.set CYREG_B0_P3_U0_CFG1, 0x40010641 -.set CYREG_B0_P3_U0_CFG2, 0x40010642 -.set CYREG_B0_P3_U0_CFG3, 0x40010643 -.set CYREG_B0_P3_U0_CFG4, 0x40010644 -.set CYREG_B0_P3_U0_CFG5, 0x40010645 -.set CYREG_B0_P3_U0_CFG6, 0x40010646 -.set CYREG_B0_P3_U0_CFG7, 0x40010647 -.set CYREG_B0_P3_U0_CFG8, 0x40010648 -.set CYREG_B0_P3_U0_CFG9, 0x40010649 -.set CYREG_B0_P3_U0_CFG10, 0x4001064a -.set CYREG_B0_P3_U0_CFG11, 0x4001064b -.set CYREG_B0_P3_U0_CFG12, 0x4001064c -.set CYREG_B0_P3_U0_CFG13, 0x4001064d -.set CYREG_B0_P3_U0_CFG14, 0x4001064e -.set CYREG_B0_P3_U0_CFG15, 0x4001064f -.set CYREG_B0_P3_U0_CFG16, 0x40010650 -.set CYREG_B0_P3_U0_CFG17, 0x40010651 -.set CYREG_B0_P3_U0_CFG18, 0x40010652 -.set CYREG_B0_P3_U0_CFG19, 0x40010653 -.set CYREG_B0_P3_U0_CFG20, 0x40010654 -.set CYREG_B0_P3_U0_CFG21, 0x40010655 -.set CYREG_B0_P3_U0_CFG22, 0x40010656 -.set CYREG_B0_P3_U0_CFG23, 0x40010657 -.set CYREG_B0_P3_U0_CFG24, 0x40010658 -.set CYREG_B0_P3_U0_CFG25, 0x40010659 -.set CYREG_B0_P3_U0_CFG26, 0x4001065a -.set CYREG_B0_P3_U0_CFG27, 0x4001065b -.set CYREG_B0_P3_U0_CFG28, 0x4001065c -.set CYREG_B0_P3_U0_CFG29, 0x4001065d -.set CYREG_B0_P3_U0_CFG30, 0x4001065e -.set CYREG_B0_P3_U0_CFG31, 0x4001065f -.set CYREG_B0_P3_U0_DCFG0, 0x40010660 -.set CYREG_B0_P3_U0_DCFG1, 0x40010662 -.set CYREG_B0_P3_U0_DCFG2, 0x40010664 -.set CYREG_B0_P3_U0_DCFG3, 0x40010666 -.set CYREG_B0_P3_U0_DCFG4, 0x40010668 -.set CYREG_B0_P3_U0_DCFG5, 0x4001066a -.set CYREG_B0_P3_U0_DCFG6, 0x4001066c -.set CYREG_B0_P3_U0_DCFG7, 0x4001066e -.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 -.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 -.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680 -.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684 -.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688 -.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c -.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690 -.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694 -.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698 -.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c -.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0 -.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4 -.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8 -.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac -.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0 -.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2 -.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4 -.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6 -.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 -.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba -.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc -.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be -.set CYREG_B0_P3_U1_CFG0, 0x400106c0 -.set CYREG_B0_P3_U1_CFG1, 0x400106c1 -.set CYREG_B0_P3_U1_CFG2, 0x400106c2 -.set CYREG_B0_P3_U1_CFG3, 0x400106c3 -.set CYREG_B0_P3_U1_CFG4, 0x400106c4 -.set CYREG_B0_P3_U1_CFG5, 0x400106c5 -.set CYREG_B0_P3_U1_CFG6, 0x400106c6 -.set CYREG_B0_P3_U1_CFG7, 0x400106c7 -.set CYREG_B0_P3_U1_CFG8, 0x400106c8 -.set CYREG_B0_P3_U1_CFG9, 0x400106c9 -.set CYREG_B0_P3_U1_CFG10, 0x400106ca -.set CYREG_B0_P3_U1_CFG11, 0x400106cb -.set CYREG_B0_P3_U1_CFG12, 0x400106cc -.set CYREG_B0_P3_U1_CFG13, 0x400106cd -.set CYREG_B0_P3_U1_CFG14, 0x400106ce -.set CYREG_B0_P3_U1_CFG15, 0x400106cf -.set CYREG_B0_P3_U1_CFG16, 0x400106d0 -.set CYREG_B0_P3_U1_CFG17, 0x400106d1 -.set CYREG_B0_P3_U1_CFG18, 0x400106d2 -.set CYREG_B0_P3_U1_CFG19, 0x400106d3 -.set CYREG_B0_P3_U1_CFG20, 0x400106d4 -.set CYREG_B0_P3_U1_CFG21, 0x400106d5 -.set CYREG_B0_P3_U1_CFG22, 0x400106d6 -.set CYREG_B0_P3_U1_CFG23, 0x400106d7 -.set CYREG_B0_P3_U1_CFG24, 0x400106d8 -.set CYREG_B0_P3_U1_CFG25, 0x400106d9 -.set CYREG_B0_P3_U1_CFG26, 0x400106da -.set CYREG_B0_P3_U1_CFG27, 0x400106db -.set CYREG_B0_P3_U1_CFG28, 0x400106dc -.set CYREG_B0_P3_U1_CFG29, 0x400106dd -.set CYREG_B0_P3_U1_CFG30, 0x400106de -.set CYREG_B0_P3_U1_CFG31, 0x400106df -.set CYREG_B0_P3_U1_DCFG0, 0x400106e0 -.set CYREG_B0_P3_U1_DCFG1, 0x400106e2 -.set CYREG_B0_P3_U1_DCFG2, 0x400106e4 -.set CYREG_B0_P3_U1_DCFG3, 0x400106e6 -.set CYREG_B0_P3_U1_DCFG4, 0x400106e8 -.set CYREG_B0_P3_U1_DCFG5, 0x400106ea -.set CYREG_B0_P3_U1_DCFG6, 0x400106ec -.set CYREG_B0_P3_U1_DCFG7, 0x400106ee -.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 -.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 -.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 -.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 -.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800 -.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804 -.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808 -.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c -.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810 -.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814 -.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818 -.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c -.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820 -.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824 -.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828 -.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c -.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830 -.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832 -.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834 -.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836 -.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 -.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a -.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c -.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e -.set CYREG_B0_P4_U0_CFG0, 0x40010840 -.set CYREG_B0_P4_U0_CFG1, 0x40010841 -.set CYREG_B0_P4_U0_CFG2, 0x40010842 -.set CYREG_B0_P4_U0_CFG3, 0x40010843 -.set CYREG_B0_P4_U0_CFG4, 0x40010844 -.set CYREG_B0_P4_U0_CFG5, 0x40010845 -.set CYREG_B0_P4_U0_CFG6, 0x40010846 -.set CYREG_B0_P4_U0_CFG7, 0x40010847 -.set CYREG_B0_P4_U0_CFG8, 0x40010848 -.set CYREG_B0_P4_U0_CFG9, 0x40010849 -.set CYREG_B0_P4_U0_CFG10, 0x4001084a -.set CYREG_B0_P4_U0_CFG11, 0x4001084b -.set CYREG_B0_P4_U0_CFG12, 0x4001084c -.set CYREG_B0_P4_U0_CFG13, 0x4001084d -.set CYREG_B0_P4_U0_CFG14, 0x4001084e -.set CYREG_B0_P4_U0_CFG15, 0x4001084f -.set CYREG_B0_P4_U0_CFG16, 0x40010850 -.set CYREG_B0_P4_U0_CFG17, 0x40010851 -.set CYREG_B0_P4_U0_CFG18, 0x40010852 -.set CYREG_B0_P4_U0_CFG19, 0x40010853 -.set CYREG_B0_P4_U0_CFG20, 0x40010854 -.set CYREG_B0_P4_U0_CFG21, 0x40010855 -.set CYREG_B0_P4_U0_CFG22, 0x40010856 -.set CYREG_B0_P4_U0_CFG23, 0x40010857 -.set CYREG_B0_P4_U0_CFG24, 0x40010858 -.set CYREG_B0_P4_U0_CFG25, 0x40010859 -.set CYREG_B0_P4_U0_CFG26, 0x4001085a -.set CYREG_B0_P4_U0_CFG27, 0x4001085b -.set CYREG_B0_P4_U0_CFG28, 0x4001085c -.set CYREG_B0_P4_U0_CFG29, 0x4001085d -.set CYREG_B0_P4_U0_CFG30, 0x4001085e -.set CYREG_B0_P4_U0_CFG31, 0x4001085f -.set CYREG_B0_P4_U0_DCFG0, 0x40010860 -.set CYREG_B0_P4_U0_DCFG1, 0x40010862 -.set CYREG_B0_P4_U0_DCFG2, 0x40010864 -.set CYREG_B0_P4_U0_DCFG3, 0x40010866 -.set CYREG_B0_P4_U0_DCFG4, 0x40010868 -.set CYREG_B0_P4_U0_DCFG5, 0x4001086a -.set CYREG_B0_P4_U0_DCFG6, 0x4001086c -.set CYREG_B0_P4_U0_DCFG7, 0x4001086e -.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 -.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 -.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880 -.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884 -.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888 -.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c -.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890 -.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894 -.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898 -.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c -.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0 -.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4 -.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8 -.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac -.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0 -.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2 -.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4 -.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6 -.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 -.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba -.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc -.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be -.set CYREG_B0_P4_U1_CFG0, 0x400108c0 -.set CYREG_B0_P4_U1_CFG1, 0x400108c1 -.set CYREG_B0_P4_U1_CFG2, 0x400108c2 -.set CYREG_B0_P4_U1_CFG3, 0x400108c3 -.set CYREG_B0_P4_U1_CFG4, 0x400108c4 -.set CYREG_B0_P4_U1_CFG5, 0x400108c5 -.set CYREG_B0_P4_U1_CFG6, 0x400108c6 -.set CYREG_B0_P4_U1_CFG7, 0x400108c7 -.set CYREG_B0_P4_U1_CFG8, 0x400108c8 -.set CYREG_B0_P4_U1_CFG9, 0x400108c9 -.set CYREG_B0_P4_U1_CFG10, 0x400108ca -.set CYREG_B0_P4_U1_CFG11, 0x400108cb -.set CYREG_B0_P4_U1_CFG12, 0x400108cc -.set CYREG_B0_P4_U1_CFG13, 0x400108cd -.set CYREG_B0_P4_U1_CFG14, 0x400108ce -.set CYREG_B0_P4_U1_CFG15, 0x400108cf -.set CYREG_B0_P4_U1_CFG16, 0x400108d0 -.set CYREG_B0_P4_U1_CFG17, 0x400108d1 -.set CYREG_B0_P4_U1_CFG18, 0x400108d2 -.set CYREG_B0_P4_U1_CFG19, 0x400108d3 -.set CYREG_B0_P4_U1_CFG20, 0x400108d4 -.set CYREG_B0_P4_U1_CFG21, 0x400108d5 -.set CYREG_B0_P4_U1_CFG22, 0x400108d6 -.set CYREG_B0_P4_U1_CFG23, 0x400108d7 -.set CYREG_B0_P4_U1_CFG24, 0x400108d8 -.set CYREG_B0_P4_U1_CFG25, 0x400108d9 -.set CYREG_B0_P4_U1_CFG26, 0x400108da -.set CYREG_B0_P4_U1_CFG27, 0x400108db -.set CYREG_B0_P4_U1_CFG28, 0x400108dc -.set CYREG_B0_P4_U1_CFG29, 0x400108dd -.set CYREG_B0_P4_U1_CFG30, 0x400108de -.set CYREG_B0_P4_U1_CFG31, 0x400108df -.set CYREG_B0_P4_U1_DCFG0, 0x400108e0 -.set CYREG_B0_P4_U1_DCFG1, 0x400108e2 -.set CYREG_B0_P4_U1_DCFG2, 0x400108e4 -.set CYREG_B0_P4_U1_DCFG3, 0x400108e6 -.set CYREG_B0_P4_U1_DCFG4, 0x400108e8 -.set CYREG_B0_P4_U1_DCFG5, 0x400108ea -.set CYREG_B0_P4_U1_DCFG6, 0x400108ec -.set CYREG_B0_P4_U1_DCFG7, 0x400108ee -.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 -.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 -.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 -.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 -.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00 -.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04 -.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08 -.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c -.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10 -.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14 -.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18 -.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c -.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20 -.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24 -.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28 -.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c -.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30 -.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32 -.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34 -.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36 -.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 -.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a -.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c -.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e -.set CYREG_B0_P5_U0_CFG0, 0x40010a40 -.set CYREG_B0_P5_U0_CFG1, 0x40010a41 -.set CYREG_B0_P5_U0_CFG2, 0x40010a42 -.set CYREG_B0_P5_U0_CFG3, 0x40010a43 -.set CYREG_B0_P5_U0_CFG4, 0x40010a44 -.set CYREG_B0_P5_U0_CFG5, 0x40010a45 -.set CYREG_B0_P5_U0_CFG6, 0x40010a46 -.set CYREG_B0_P5_U0_CFG7, 0x40010a47 -.set CYREG_B0_P5_U0_CFG8, 0x40010a48 -.set CYREG_B0_P5_U0_CFG9, 0x40010a49 -.set CYREG_B0_P5_U0_CFG10, 0x40010a4a -.set CYREG_B0_P5_U0_CFG11, 0x40010a4b -.set CYREG_B0_P5_U0_CFG12, 0x40010a4c -.set CYREG_B0_P5_U0_CFG13, 0x40010a4d -.set CYREG_B0_P5_U0_CFG14, 0x40010a4e -.set CYREG_B0_P5_U0_CFG15, 0x40010a4f -.set CYREG_B0_P5_U0_CFG16, 0x40010a50 -.set CYREG_B0_P5_U0_CFG17, 0x40010a51 -.set CYREG_B0_P5_U0_CFG18, 0x40010a52 -.set CYREG_B0_P5_U0_CFG19, 0x40010a53 -.set CYREG_B0_P5_U0_CFG20, 0x40010a54 -.set CYREG_B0_P5_U0_CFG21, 0x40010a55 -.set CYREG_B0_P5_U0_CFG22, 0x40010a56 -.set CYREG_B0_P5_U0_CFG23, 0x40010a57 -.set CYREG_B0_P5_U0_CFG24, 0x40010a58 -.set CYREG_B0_P5_U0_CFG25, 0x40010a59 -.set CYREG_B0_P5_U0_CFG26, 0x40010a5a -.set CYREG_B0_P5_U0_CFG27, 0x40010a5b -.set CYREG_B0_P5_U0_CFG28, 0x40010a5c -.set CYREG_B0_P5_U0_CFG29, 0x40010a5d -.set CYREG_B0_P5_U0_CFG30, 0x40010a5e -.set CYREG_B0_P5_U0_CFG31, 0x40010a5f -.set CYREG_B0_P5_U0_DCFG0, 0x40010a60 -.set CYREG_B0_P5_U0_DCFG1, 0x40010a62 -.set CYREG_B0_P5_U0_DCFG2, 0x40010a64 -.set CYREG_B0_P5_U0_DCFG3, 0x40010a66 -.set CYREG_B0_P5_U0_DCFG4, 0x40010a68 -.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a -.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c -.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e -.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 -.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 -.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80 -.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84 -.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88 -.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c -.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90 -.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94 -.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98 -.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c -.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0 -.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4 -.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8 -.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac -.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0 -.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2 -.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4 -.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6 -.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 -.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba -.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc -.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe -.set CYREG_B0_P5_U1_CFG0, 0x40010ac0 -.set CYREG_B0_P5_U1_CFG1, 0x40010ac1 -.set CYREG_B0_P5_U1_CFG2, 0x40010ac2 -.set CYREG_B0_P5_U1_CFG3, 0x40010ac3 -.set CYREG_B0_P5_U1_CFG4, 0x40010ac4 -.set CYREG_B0_P5_U1_CFG5, 0x40010ac5 -.set CYREG_B0_P5_U1_CFG6, 0x40010ac6 -.set CYREG_B0_P5_U1_CFG7, 0x40010ac7 -.set CYREG_B0_P5_U1_CFG8, 0x40010ac8 -.set CYREG_B0_P5_U1_CFG9, 0x40010ac9 -.set CYREG_B0_P5_U1_CFG10, 0x40010aca -.set CYREG_B0_P5_U1_CFG11, 0x40010acb -.set CYREG_B0_P5_U1_CFG12, 0x40010acc -.set CYREG_B0_P5_U1_CFG13, 0x40010acd -.set CYREG_B0_P5_U1_CFG14, 0x40010ace -.set CYREG_B0_P5_U1_CFG15, 0x40010acf -.set CYREG_B0_P5_U1_CFG16, 0x40010ad0 -.set CYREG_B0_P5_U1_CFG17, 0x40010ad1 -.set CYREG_B0_P5_U1_CFG18, 0x40010ad2 -.set CYREG_B0_P5_U1_CFG19, 0x40010ad3 -.set CYREG_B0_P5_U1_CFG20, 0x40010ad4 -.set CYREG_B0_P5_U1_CFG21, 0x40010ad5 -.set CYREG_B0_P5_U1_CFG22, 0x40010ad6 -.set CYREG_B0_P5_U1_CFG23, 0x40010ad7 -.set CYREG_B0_P5_U1_CFG24, 0x40010ad8 -.set CYREG_B0_P5_U1_CFG25, 0x40010ad9 -.set CYREG_B0_P5_U1_CFG26, 0x40010ada -.set CYREG_B0_P5_U1_CFG27, 0x40010adb -.set CYREG_B0_P5_U1_CFG28, 0x40010adc -.set CYREG_B0_P5_U1_CFG29, 0x40010add -.set CYREG_B0_P5_U1_CFG30, 0x40010ade -.set CYREG_B0_P5_U1_CFG31, 0x40010adf -.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0 -.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2 -.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4 -.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6 -.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8 -.set CYREG_B0_P5_U1_DCFG5, 0x40010aea -.set CYREG_B0_P5_U1_DCFG6, 0x40010aec -.set CYREG_B0_P5_U1_DCFG7, 0x40010aee -.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 -.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 -.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 -.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 -.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00 -.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04 -.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08 -.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c -.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10 -.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14 -.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18 -.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c -.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20 -.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24 -.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28 -.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c -.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30 -.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32 -.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34 -.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36 -.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 -.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a -.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c -.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e -.set CYREG_B0_P6_U0_CFG0, 0x40010c40 -.set CYREG_B0_P6_U0_CFG1, 0x40010c41 -.set CYREG_B0_P6_U0_CFG2, 0x40010c42 -.set CYREG_B0_P6_U0_CFG3, 0x40010c43 -.set CYREG_B0_P6_U0_CFG4, 0x40010c44 -.set CYREG_B0_P6_U0_CFG5, 0x40010c45 -.set CYREG_B0_P6_U0_CFG6, 0x40010c46 -.set CYREG_B0_P6_U0_CFG7, 0x40010c47 -.set CYREG_B0_P6_U0_CFG8, 0x40010c48 -.set CYREG_B0_P6_U0_CFG9, 0x40010c49 -.set CYREG_B0_P6_U0_CFG10, 0x40010c4a -.set CYREG_B0_P6_U0_CFG11, 0x40010c4b -.set CYREG_B0_P6_U0_CFG12, 0x40010c4c -.set CYREG_B0_P6_U0_CFG13, 0x40010c4d -.set CYREG_B0_P6_U0_CFG14, 0x40010c4e -.set CYREG_B0_P6_U0_CFG15, 0x40010c4f -.set CYREG_B0_P6_U0_CFG16, 0x40010c50 -.set CYREG_B0_P6_U0_CFG17, 0x40010c51 -.set CYREG_B0_P6_U0_CFG18, 0x40010c52 -.set CYREG_B0_P6_U0_CFG19, 0x40010c53 -.set CYREG_B0_P6_U0_CFG20, 0x40010c54 -.set CYREG_B0_P6_U0_CFG21, 0x40010c55 -.set CYREG_B0_P6_U0_CFG22, 0x40010c56 -.set CYREG_B0_P6_U0_CFG23, 0x40010c57 -.set CYREG_B0_P6_U0_CFG24, 0x40010c58 -.set CYREG_B0_P6_U0_CFG25, 0x40010c59 -.set CYREG_B0_P6_U0_CFG26, 0x40010c5a -.set CYREG_B0_P6_U0_CFG27, 0x40010c5b -.set CYREG_B0_P6_U0_CFG28, 0x40010c5c -.set CYREG_B0_P6_U0_CFG29, 0x40010c5d -.set CYREG_B0_P6_U0_CFG30, 0x40010c5e -.set CYREG_B0_P6_U0_CFG31, 0x40010c5f -.set CYREG_B0_P6_U0_DCFG0, 0x40010c60 -.set CYREG_B0_P6_U0_DCFG1, 0x40010c62 -.set CYREG_B0_P6_U0_DCFG2, 0x40010c64 -.set CYREG_B0_P6_U0_DCFG3, 0x40010c66 -.set CYREG_B0_P6_U0_DCFG4, 0x40010c68 -.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a -.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c -.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e -.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 -.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 -.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80 -.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84 -.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88 -.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c -.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90 -.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94 -.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98 -.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c -.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0 -.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4 -.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8 -.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac -.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0 -.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2 -.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4 -.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6 -.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 -.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba -.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc -.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe -.set CYREG_B0_P6_U1_CFG0, 0x40010cc0 -.set CYREG_B0_P6_U1_CFG1, 0x40010cc1 -.set CYREG_B0_P6_U1_CFG2, 0x40010cc2 -.set CYREG_B0_P6_U1_CFG3, 0x40010cc3 -.set CYREG_B0_P6_U1_CFG4, 0x40010cc4 -.set CYREG_B0_P6_U1_CFG5, 0x40010cc5 -.set CYREG_B0_P6_U1_CFG6, 0x40010cc6 -.set CYREG_B0_P6_U1_CFG7, 0x40010cc7 -.set CYREG_B0_P6_U1_CFG8, 0x40010cc8 -.set CYREG_B0_P6_U1_CFG9, 0x40010cc9 -.set CYREG_B0_P6_U1_CFG10, 0x40010cca -.set CYREG_B0_P6_U1_CFG11, 0x40010ccb -.set CYREG_B0_P6_U1_CFG12, 0x40010ccc -.set CYREG_B0_P6_U1_CFG13, 0x40010ccd -.set CYREG_B0_P6_U1_CFG14, 0x40010cce -.set CYREG_B0_P6_U1_CFG15, 0x40010ccf -.set CYREG_B0_P6_U1_CFG16, 0x40010cd0 -.set CYREG_B0_P6_U1_CFG17, 0x40010cd1 -.set CYREG_B0_P6_U1_CFG18, 0x40010cd2 -.set CYREG_B0_P6_U1_CFG19, 0x40010cd3 -.set CYREG_B0_P6_U1_CFG20, 0x40010cd4 -.set CYREG_B0_P6_U1_CFG21, 0x40010cd5 -.set CYREG_B0_P6_U1_CFG22, 0x40010cd6 -.set CYREG_B0_P6_U1_CFG23, 0x40010cd7 -.set CYREG_B0_P6_U1_CFG24, 0x40010cd8 -.set CYREG_B0_P6_U1_CFG25, 0x40010cd9 -.set CYREG_B0_P6_U1_CFG26, 0x40010cda -.set CYREG_B0_P6_U1_CFG27, 0x40010cdb -.set CYREG_B0_P6_U1_CFG28, 0x40010cdc -.set CYREG_B0_P6_U1_CFG29, 0x40010cdd -.set CYREG_B0_P6_U1_CFG30, 0x40010cde -.set CYREG_B0_P6_U1_CFG31, 0x40010cdf -.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0 -.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2 -.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4 -.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6 -.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8 -.set CYREG_B0_P6_U1_DCFG5, 0x40010cea -.set CYREG_B0_P6_U1_DCFG6, 0x40010cec -.set CYREG_B0_P6_U1_DCFG7, 0x40010cee -.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 -.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 -.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef -.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 -.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 -.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00 -.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04 -.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08 -.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c -.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10 -.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14 -.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18 -.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c -.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20 -.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24 -.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28 -.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c -.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30 -.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32 -.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34 -.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36 -.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 -.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a -.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c -.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e -.set CYREG_B0_P7_U0_CFG0, 0x40010e40 -.set CYREG_B0_P7_U0_CFG1, 0x40010e41 -.set CYREG_B0_P7_U0_CFG2, 0x40010e42 -.set CYREG_B0_P7_U0_CFG3, 0x40010e43 -.set CYREG_B0_P7_U0_CFG4, 0x40010e44 -.set CYREG_B0_P7_U0_CFG5, 0x40010e45 -.set CYREG_B0_P7_U0_CFG6, 0x40010e46 -.set CYREG_B0_P7_U0_CFG7, 0x40010e47 -.set CYREG_B0_P7_U0_CFG8, 0x40010e48 -.set CYREG_B0_P7_U0_CFG9, 0x40010e49 -.set CYREG_B0_P7_U0_CFG10, 0x40010e4a -.set CYREG_B0_P7_U0_CFG11, 0x40010e4b -.set CYREG_B0_P7_U0_CFG12, 0x40010e4c -.set CYREG_B0_P7_U0_CFG13, 0x40010e4d -.set CYREG_B0_P7_U0_CFG14, 0x40010e4e -.set CYREG_B0_P7_U0_CFG15, 0x40010e4f -.set CYREG_B0_P7_U0_CFG16, 0x40010e50 -.set CYREG_B0_P7_U0_CFG17, 0x40010e51 -.set CYREG_B0_P7_U0_CFG18, 0x40010e52 -.set CYREG_B0_P7_U0_CFG19, 0x40010e53 -.set CYREG_B0_P7_U0_CFG20, 0x40010e54 -.set CYREG_B0_P7_U0_CFG21, 0x40010e55 -.set CYREG_B0_P7_U0_CFG22, 0x40010e56 -.set CYREG_B0_P7_U0_CFG23, 0x40010e57 -.set CYREG_B0_P7_U0_CFG24, 0x40010e58 -.set CYREG_B0_P7_U0_CFG25, 0x40010e59 -.set CYREG_B0_P7_U0_CFG26, 0x40010e5a -.set CYREG_B0_P7_U0_CFG27, 0x40010e5b -.set CYREG_B0_P7_U0_CFG28, 0x40010e5c -.set CYREG_B0_P7_U0_CFG29, 0x40010e5d -.set CYREG_B0_P7_U0_CFG30, 0x40010e5e -.set CYREG_B0_P7_U0_CFG31, 0x40010e5f -.set CYREG_B0_P7_U0_DCFG0, 0x40010e60 -.set CYREG_B0_P7_U0_DCFG1, 0x40010e62 -.set CYREG_B0_P7_U0_DCFG2, 0x40010e64 -.set CYREG_B0_P7_U0_DCFG3, 0x40010e66 -.set CYREG_B0_P7_U0_DCFG4, 0x40010e68 -.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a -.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c -.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e -.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 -.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 -.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80 -.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84 -.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88 -.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c -.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90 -.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94 -.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98 -.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c -.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0 -.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4 -.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8 -.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac -.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0 -.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2 -.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4 -.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6 -.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 -.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba -.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc -.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe -.set CYREG_B0_P7_U1_CFG0, 0x40010ec0 -.set CYREG_B0_P7_U1_CFG1, 0x40010ec1 -.set CYREG_B0_P7_U1_CFG2, 0x40010ec2 -.set CYREG_B0_P7_U1_CFG3, 0x40010ec3 -.set CYREG_B0_P7_U1_CFG4, 0x40010ec4 -.set CYREG_B0_P7_U1_CFG5, 0x40010ec5 -.set CYREG_B0_P7_U1_CFG6, 0x40010ec6 -.set CYREG_B0_P7_U1_CFG7, 0x40010ec7 -.set CYREG_B0_P7_U1_CFG8, 0x40010ec8 -.set CYREG_B0_P7_U1_CFG9, 0x40010ec9 -.set CYREG_B0_P7_U1_CFG10, 0x40010eca -.set CYREG_B0_P7_U1_CFG11, 0x40010ecb -.set CYREG_B0_P7_U1_CFG12, 0x40010ecc -.set CYREG_B0_P7_U1_CFG13, 0x40010ecd -.set CYREG_B0_P7_U1_CFG14, 0x40010ece -.set CYREG_B0_P7_U1_CFG15, 0x40010ecf -.set CYREG_B0_P7_U1_CFG16, 0x40010ed0 -.set CYREG_B0_P7_U1_CFG17, 0x40010ed1 -.set CYREG_B0_P7_U1_CFG18, 0x40010ed2 -.set CYREG_B0_P7_U1_CFG19, 0x40010ed3 -.set CYREG_B0_P7_U1_CFG20, 0x40010ed4 -.set CYREG_B0_P7_U1_CFG21, 0x40010ed5 -.set CYREG_B0_P7_U1_CFG22, 0x40010ed6 -.set CYREG_B0_P7_U1_CFG23, 0x40010ed7 -.set CYREG_B0_P7_U1_CFG24, 0x40010ed8 -.set CYREG_B0_P7_U1_CFG25, 0x40010ed9 -.set CYREG_B0_P7_U1_CFG26, 0x40010eda -.set CYREG_B0_P7_U1_CFG27, 0x40010edb -.set CYREG_B0_P7_U1_CFG28, 0x40010edc -.set CYREG_B0_P7_U1_CFG29, 0x40010edd -.set CYREG_B0_P7_U1_CFG30, 0x40010ede -.set CYREG_B0_P7_U1_CFG31, 0x40010edf -.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0 -.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2 -.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4 -.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6 -.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8 -.set CYREG_B0_P7_U1_DCFG5, 0x40010eea -.set CYREG_B0_P7_U1_DCFG6, 0x40010eec -.set CYREG_B0_P7_U1_DCFG7, 0x40010eee -.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 -.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_BASE, 0x40011000 -.set CYDEV_UCFG_B1_SIZE, 0x00000fef -.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 -.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 -.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 -.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400 -.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404 -.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408 -.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c -.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410 -.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414 -.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418 -.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c -.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420 -.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424 -.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428 -.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c -.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430 -.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432 -.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434 -.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436 -.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 -.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a -.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c -.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e -.set CYREG_B1_P2_U0_CFG0, 0x40011440 -.set CYREG_B1_P2_U0_CFG1, 0x40011441 -.set CYREG_B1_P2_U0_CFG2, 0x40011442 -.set CYREG_B1_P2_U0_CFG3, 0x40011443 -.set CYREG_B1_P2_U0_CFG4, 0x40011444 -.set CYREG_B1_P2_U0_CFG5, 0x40011445 -.set CYREG_B1_P2_U0_CFG6, 0x40011446 -.set CYREG_B1_P2_U0_CFG7, 0x40011447 -.set CYREG_B1_P2_U0_CFG8, 0x40011448 -.set CYREG_B1_P2_U0_CFG9, 0x40011449 -.set CYREG_B1_P2_U0_CFG10, 0x4001144a -.set CYREG_B1_P2_U0_CFG11, 0x4001144b -.set CYREG_B1_P2_U0_CFG12, 0x4001144c -.set CYREG_B1_P2_U0_CFG13, 0x4001144d -.set CYREG_B1_P2_U0_CFG14, 0x4001144e -.set CYREG_B1_P2_U0_CFG15, 0x4001144f -.set CYREG_B1_P2_U0_CFG16, 0x40011450 -.set CYREG_B1_P2_U0_CFG17, 0x40011451 -.set CYREG_B1_P2_U0_CFG18, 0x40011452 -.set CYREG_B1_P2_U0_CFG19, 0x40011453 -.set CYREG_B1_P2_U0_CFG20, 0x40011454 -.set CYREG_B1_P2_U0_CFG21, 0x40011455 -.set CYREG_B1_P2_U0_CFG22, 0x40011456 -.set CYREG_B1_P2_U0_CFG23, 0x40011457 -.set CYREG_B1_P2_U0_CFG24, 0x40011458 -.set CYREG_B1_P2_U0_CFG25, 0x40011459 -.set CYREG_B1_P2_U0_CFG26, 0x4001145a -.set CYREG_B1_P2_U0_CFG27, 0x4001145b -.set CYREG_B1_P2_U0_CFG28, 0x4001145c -.set CYREG_B1_P2_U0_CFG29, 0x4001145d -.set CYREG_B1_P2_U0_CFG30, 0x4001145e -.set CYREG_B1_P2_U0_CFG31, 0x4001145f -.set CYREG_B1_P2_U0_DCFG0, 0x40011460 -.set CYREG_B1_P2_U0_DCFG1, 0x40011462 -.set CYREG_B1_P2_U0_DCFG2, 0x40011464 -.set CYREG_B1_P2_U0_DCFG3, 0x40011466 -.set CYREG_B1_P2_U0_DCFG4, 0x40011468 -.set CYREG_B1_P2_U0_DCFG5, 0x4001146a -.set CYREG_B1_P2_U0_DCFG6, 0x4001146c -.set CYREG_B1_P2_U0_DCFG7, 0x4001146e -.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 -.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 -.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480 -.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484 -.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488 -.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c -.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490 -.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494 -.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498 -.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c -.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0 -.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4 -.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8 -.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac -.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0 -.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2 -.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4 -.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6 -.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 -.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba -.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc -.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be -.set CYREG_B1_P2_U1_CFG0, 0x400114c0 -.set CYREG_B1_P2_U1_CFG1, 0x400114c1 -.set CYREG_B1_P2_U1_CFG2, 0x400114c2 -.set CYREG_B1_P2_U1_CFG3, 0x400114c3 -.set CYREG_B1_P2_U1_CFG4, 0x400114c4 -.set CYREG_B1_P2_U1_CFG5, 0x400114c5 -.set CYREG_B1_P2_U1_CFG6, 0x400114c6 -.set CYREG_B1_P2_U1_CFG7, 0x400114c7 -.set CYREG_B1_P2_U1_CFG8, 0x400114c8 -.set CYREG_B1_P2_U1_CFG9, 0x400114c9 -.set CYREG_B1_P2_U1_CFG10, 0x400114ca -.set CYREG_B1_P2_U1_CFG11, 0x400114cb -.set CYREG_B1_P2_U1_CFG12, 0x400114cc -.set CYREG_B1_P2_U1_CFG13, 0x400114cd -.set CYREG_B1_P2_U1_CFG14, 0x400114ce -.set CYREG_B1_P2_U1_CFG15, 0x400114cf -.set CYREG_B1_P2_U1_CFG16, 0x400114d0 -.set CYREG_B1_P2_U1_CFG17, 0x400114d1 -.set CYREG_B1_P2_U1_CFG18, 0x400114d2 -.set CYREG_B1_P2_U1_CFG19, 0x400114d3 -.set CYREG_B1_P2_U1_CFG20, 0x400114d4 -.set CYREG_B1_P2_U1_CFG21, 0x400114d5 -.set CYREG_B1_P2_U1_CFG22, 0x400114d6 -.set CYREG_B1_P2_U1_CFG23, 0x400114d7 -.set CYREG_B1_P2_U1_CFG24, 0x400114d8 -.set CYREG_B1_P2_U1_CFG25, 0x400114d9 -.set CYREG_B1_P2_U1_CFG26, 0x400114da -.set CYREG_B1_P2_U1_CFG27, 0x400114db -.set CYREG_B1_P2_U1_CFG28, 0x400114dc -.set CYREG_B1_P2_U1_CFG29, 0x400114dd -.set CYREG_B1_P2_U1_CFG30, 0x400114de -.set CYREG_B1_P2_U1_CFG31, 0x400114df -.set CYREG_B1_P2_U1_DCFG0, 0x400114e0 -.set CYREG_B1_P2_U1_DCFG1, 0x400114e2 -.set CYREG_B1_P2_U1_DCFG2, 0x400114e4 -.set CYREG_B1_P2_U1_DCFG3, 0x400114e6 -.set CYREG_B1_P2_U1_DCFG4, 0x400114e8 -.set CYREG_B1_P2_U1_DCFG5, 0x400114ea -.set CYREG_B1_P2_U1_DCFG6, 0x400114ec -.set CYREG_B1_P2_U1_DCFG7, 0x400114ee -.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 -.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 -.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 -.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 -.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600 -.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604 -.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608 -.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c -.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610 -.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614 -.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618 -.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c -.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620 -.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624 -.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628 -.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c -.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630 -.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632 -.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634 -.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636 -.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 -.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a -.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c -.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e -.set CYREG_B1_P3_U0_CFG0, 0x40011640 -.set CYREG_B1_P3_U0_CFG1, 0x40011641 -.set CYREG_B1_P3_U0_CFG2, 0x40011642 -.set CYREG_B1_P3_U0_CFG3, 0x40011643 -.set CYREG_B1_P3_U0_CFG4, 0x40011644 -.set CYREG_B1_P3_U0_CFG5, 0x40011645 -.set CYREG_B1_P3_U0_CFG6, 0x40011646 -.set CYREG_B1_P3_U0_CFG7, 0x40011647 -.set CYREG_B1_P3_U0_CFG8, 0x40011648 -.set CYREG_B1_P3_U0_CFG9, 0x40011649 -.set CYREG_B1_P3_U0_CFG10, 0x4001164a -.set CYREG_B1_P3_U0_CFG11, 0x4001164b -.set CYREG_B1_P3_U0_CFG12, 0x4001164c -.set CYREG_B1_P3_U0_CFG13, 0x4001164d -.set CYREG_B1_P3_U0_CFG14, 0x4001164e -.set CYREG_B1_P3_U0_CFG15, 0x4001164f -.set CYREG_B1_P3_U0_CFG16, 0x40011650 -.set CYREG_B1_P3_U0_CFG17, 0x40011651 -.set CYREG_B1_P3_U0_CFG18, 0x40011652 -.set CYREG_B1_P3_U0_CFG19, 0x40011653 -.set CYREG_B1_P3_U0_CFG20, 0x40011654 -.set CYREG_B1_P3_U0_CFG21, 0x40011655 -.set CYREG_B1_P3_U0_CFG22, 0x40011656 -.set CYREG_B1_P3_U0_CFG23, 0x40011657 -.set CYREG_B1_P3_U0_CFG24, 0x40011658 -.set CYREG_B1_P3_U0_CFG25, 0x40011659 -.set CYREG_B1_P3_U0_CFG26, 0x4001165a -.set CYREG_B1_P3_U0_CFG27, 0x4001165b -.set CYREG_B1_P3_U0_CFG28, 0x4001165c -.set CYREG_B1_P3_U0_CFG29, 0x4001165d -.set CYREG_B1_P3_U0_CFG30, 0x4001165e -.set CYREG_B1_P3_U0_CFG31, 0x4001165f -.set CYREG_B1_P3_U0_DCFG0, 0x40011660 -.set CYREG_B1_P3_U0_DCFG1, 0x40011662 -.set CYREG_B1_P3_U0_DCFG2, 0x40011664 -.set CYREG_B1_P3_U0_DCFG3, 0x40011666 -.set CYREG_B1_P3_U0_DCFG4, 0x40011668 -.set CYREG_B1_P3_U0_DCFG5, 0x4001166a -.set CYREG_B1_P3_U0_DCFG6, 0x4001166c -.set CYREG_B1_P3_U0_DCFG7, 0x4001166e -.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 -.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 -.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680 -.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684 -.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688 -.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c -.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690 -.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694 -.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698 -.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c -.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0 -.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4 -.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8 -.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac -.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0 -.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2 -.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4 -.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6 -.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 -.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba -.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc -.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be -.set CYREG_B1_P3_U1_CFG0, 0x400116c0 -.set CYREG_B1_P3_U1_CFG1, 0x400116c1 -.set CYREG_B1_P3_U1_CFG2, 0x400116c2 -.set CYREG_B1_P3_U1_CFG3, 0x400116c3 -.set CYREG_B1_P3_U1_CFG4, 0x400116c4 -.set CYREG_B1_P3_U1_CFG5, 0x400116c5 -.set CYREG_B1_P3_U1_CFG6, 0x400116c6 -.set CYREG_B1_P3_U1_CFG7, 0x400116c7 -.set CYREG_B1_P3_U1_CFG8, 0x400116c8 -.set CYREG_B1_P3_U1_CFG9, 0x400116c9 -.set CYREG_B1_P3_U1_CFG10, 0x400116ca -.set CYREG_B1_P3_U1_CFG11, 0x400116cb -.set CYREG_B1_P3_U1_CFG12, 0x400116cc -.set CYREG_B1_P3_U1_CFG13, 0x400116cd -.set CYREG_B1_P3_U1_CFG14, 0x400116ce -.set CYREG_B1_P3_U1_CFG15, 0x400116cf -.set CYREG_B1_P3_U1_CFG16, 0x400116d0 -.set CYREG_B1_P3_U1_CFG17, 0x400116d1 -.set CYREG_B1_P3_U1_CFG18, 0x400116d2 -.set CYREG_B1_P3_U1_CFG19, 0x400116d3 -.set CYREG_B1_P3_U1_CFG20, 0x400116d4 -.set CYREG_B1_P3_U1_CFG21, 0x400116d5 -.set CYREG_B1_P3_U1_CFG22, 0x400116d6 -.set CYREG_B1_P3_U1_CFG23, 0x400116d7 -.set CYREG_B1_P3_U1_CFG24, 0x400116d8 -.set CYREG_B1_P3_U1_CFG25, 0x400116d9 -.set CYREG_B1_P3_U1_CFG26, 0x400116da -.set CYREG_B1_P3_U1_CFG27, 0x400116db -.set CYREG_B1_P3_U1_CFG28, 0x400116dc -.set CYREG_B1_P3_U1_CFG29, 0x400116dd -.set CYREG_B1_P3_U1_CFG30, 0x400116de -.set CYREG_B1_P3_U1_CFG31, 0x400116df -.set CYREG_B1_P3_U1_DCFG0, 0x400116e0 -.set CYREG_B1_P3_U1_DCFG1, 0x400116e2 -.set CYREG_B1_P3_U1_DCFG2, 0x400116e4 -.set CYREG_B1_P3_U1_DCFG3, 0x400116e6 -.set CYREG_B1_P3_U1_DCFG4, 0x400116e8 -.set CYREG_B1_P3_U1_DCFG5, 0x400116ea -.set CYREG_B1_P3_U1_DCFG6, 0x400116ec -.set CYREG_B1_P3_U1_DCFG7, 0x400116ee -.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 -.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 -.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 -.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 -.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800 -.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804 -.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808 -.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c -.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810 -.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814 -.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818 -.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c -.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820 -.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824 -.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828 -.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c -.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830 -.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832 -.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834 -.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836 -.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 -.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a -.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c -.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e -.set CYREG_B1_P4_U0_CFG0, 0x40011840 -.set CYREG_B1_P4_U0_CFG1, 0x40011841 -.set CYREG_B1_P4_U0_CFG2, 0x40011842 -.set CYREG_B1_P4_U0_CFG3, 0x40011843 -.set CYREG_B1_P4_U0_CFG4, 0x40011844 -.set CYREG_B1_P4_U0_CFG5, 0x40011845 -.set CYREG_B1_P4_U0_CFG6, 0x40011846 -.set CYREG_B1_P4_U0_CFG7, 0x40011847 -.set CYREG_B1_P4_U0_CFG8, 0x40011848 -.set CYREG_B1_P4_U0_CFG9, 0x40011849 -.set CYREG_B1_P4_U0_CFG10, 0x4001184a -.set CYREG_B1_P4_U0_CFG11, 0x4001184b -.set CYREG_B1_P4_U0_CFG12, 0x4001184c -.set CYREG_B1_P4_U0_CFG13, 0x4001184d -.set CYREG_B1_P4_U0_CFG14, 0x4001184e -.set CYREG_B1_P4_U0_CFG15, 0x4001184f -.set CYREG_B1_P4_U0_CFG16, 0x40011850 -.set CYREG_B1_P4_U0_CFG17, 0x40011851 -.set CYREG_B1_P4_U0_CFG18, 0x40011852 -.set CYREG_B1_P4_U0_CFG19, 0x40011853 -.set CYREG_B1_P4_U0_CFG20, 0x40011854 -.set CYREG_B1_P4_U0_CFG21, 0x40011855 -.set CYREG_B1_P4_U0_CFG22, 0x40011856 -.set CYREG_B1_P4_U0_CFG23, 0x40011857 -.set CYREG_B1_P4_U0_CFG24, 0x40011858 -.set CYREG_B1_P4_U0_CFG25, 0x40011859 -.set CYREG_B1_P4_U0_CFG26, 0x4001185a -.set CYREG_B1_P4_U0_CFG27, 0x4001185b -.set CYREG_B1_P4_U0_CFG28, 0x4001185c -.set CYREG_B1_P4_U0_CFG29, 0x4001185d -.set CYREG_B1_P4_U0_CFG30, 0x4001185e -.set CYREG_B1_P4_U0_CFG31, 0x4001185f -.set CYREG_B1_P4_U0_DCFG0, 0x40011860 -.set CYREG_B1_P4_U0_DCFG1, 0x40011862 -.set CYREG_B1_P4_U0_DCFG2, 0x40011864 -.set CYREG_B1_P4_U0_DCFG3, 0x40011866 -.set CYREG_B1_P4_U0_DCFG4, 0x40011868 -.set CYREG_B1_P4_U0_DCFG5, 0x4001186a -.set CYREG_B1_P4_U0_DCFG6, 0x4001186c -.set CYREG_B1_P4_U0_DCFG7, 0x4001186e -.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 -.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 -.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880 -.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884 -.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888 -.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c -.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890 -.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894 -.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898 -.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c -.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0 -.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4 -.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8 -.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac -.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0 -.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2 -.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4 -.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6 -.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 -.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba -.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc -.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be -.set CYREG_B1_P4_U1_CFG0, 0x400118c0 -.set CYREG_B1_P4_U1_CFG1, 0x400118c1 -.set CYREG_B1_P4_U1_CFG2, 0x400118c2 -.set CYREG_B1_P4_U1_CFG3, 0x400118c3 -.set CYREG_B1_P4_U1_CFG4, 0x400118c4 -.set CYREG_B1_P4_U1_CFG5, 0x400118c5 -.set CYREG_B1_P4_U1_CFG6, 0x400118c6 -.set CYREG_B1_P4_U1_CFG7, 0x400118c7 -.set CYREG_B1_P4_U1_CFG8, 0x400118c8 -.set CYREG_B1_P4_U1_CFG9, 0x400118c9 -.set CYREG_B1_P4_U1_CFG10, 0x400118ca -.set CYREG_B1_P4_U1_CFG11, 0x400118cb -.set CYREG_B1_P4_U1_CFG12, 0x400118cc -.set CYREG_B1_P4_U1_CFG13, 0x400118cd -.set CYREG_B1_P4_U1_CFG14, 0x400118ce -.set CYREG_B1_P4_U1_CFG15, 0x400118cf -.set CYREG_B1_P4_U1_CFG16, 0x400118d0 -.set CYREG_B1_P4_U1_CFG17, 0x400118d1 -.set CYREG_B1_P4_U1_CFG18, 0x400118d2 -.set CYREG_B1_P4_U1_CFG19, 0x400118d3 -.set CYREG_B1_P4_U1_CFG20, 0x400118d4 -.set CYREG_B1_P4_U1_CFG21, 0x400118d5 -.set CYREG_B1_P4_U1_CFG22, 0x400118d6 -.set CYREG_B1_P4_U1_CFG23, 0x400118d7 -.set CYREG_B1_P4_U1_CFG24, 0x400118d8 -.set CYREG_B1_P4_U1_CFG25, 0x400118d9 -.set CYREG_B1_P4_U1_CFG26, 0x400118da -.set CYREG_B1_P4_U1_CFG27, 0x400118db -.set CYREG_B1_P4_U1_CFG28, 0x400118dc -.set CYREG_B1_P4_U1_CFG29, 0x400118dd -.set CYREG_B1_P4_U1_CFG30, 0x400118de -.set CYREG_B1_P4_U1_CFG31, 0x400118df -.set CYREG_B1_P4_U1_DCFG0, 0x400118e0 -.set CYREG_B1_P4_U1_DCFG1, 0x400118e2 -.set CYREG_B1_P4_U1_DCFG2, 0x400118e4 -.set CYREG_B1_P4_U1_DCFG3, 0x400118e6 -.set CYREG_B1_P4_U1_DCFG4, 0x400118e8 -.set CYREG_B1_P4_U1_DCFG5, 0x400118ea -.set CYREG_B1_P4_U1_DCFG6, 0x400118ec -.set CYREG_B1_P4_U1_DCFG7, 0x400118ee -.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 -.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 -.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef -.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 -.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 -.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00 -.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04 -.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08 -.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c -.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10 -.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14 -.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18 -.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c -.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20 -.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24 -.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28 -.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c -.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30 -.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32 -.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34 -.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36 -.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 -.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a -.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c -.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e -.set CYREG_B1_P5_U0_CFG0, 0x40011a40 -.set CYREG_B1_P5_U0_CFG1, 0x40011a41 -.set CYREG_B1_P5_U0_CFG2, 0x40011a42 -.set CYREG_B1_P5_U0_CFG3, 0x40011a43 -.set CYREG_B1_P5_U0_CFG4, 0x40011a44 -.set CYREG_B1_P5_U0_CFG5, 0x40011a45 -.set CYREG_B1_P5_U0_CFG6, 0x40011a46 -.set CYREG_B1_P5_U0_CFG7, 0x40011a47 -.set CYREG_B1_P5_U0_CFG8, 0x40011a48 -.set CYREG_B1_P5_U0_CFG9, 0x40011a49 -.set CYREG_B1_P5_U0_CFG10, 0x40011a4a -.set CYREG_B1_P5_U0_CFG11, 0x40011a4b -.set CYREG_B1_P5_U0_CFG12, 0x40011a4c -.set CYREG_B1_P5_U0_CFG13, 0x40011a4d -.set CYREG_B1_P5_U0_CFG14, 0x40011a4e -.set CYREG_B1_P5_U0_CFG15, 0x40011a4f -.set CYREG_B1_P5_U0_CFG16, 0x40011a50 -.set CYREG_B1_P5_U0_CFG17, 0x40011a51 -.set CYREG_B1_P5_U0_CFG18, 0x40011a52 -.set CYREG_B1_P5_U0_CFG19, 0x40011a53 -.set CYREG_B1_P5_U0_CFG20, 0x40011a54 -.set CYREG_B1_P5_U0_CFG21, 0x40011a55 -.set CYREG_B1_P5_U0_CFG22, 0x40011a56 -.set CYREG_B1_P5_U0_CFG23, 0x40011a57 -.set CYREG_B1_P5_U0_CFG24, 0x40011a58 -.set CYREG_B1_P5_U0_CFG25, 0x40011a59 -.set CYREG_B1_P5_U0_CFG26, 0x40011a5a -.set CYREG_B1_P5_U0_CFG27, 0x40011a5b -.set CYREG_B1_P5_U0_CFG28, 0x40011a5c -.set CYREG_B1_P5_U0_CFG29, 0x40011a5d -.set CYREG_B1_P5_U0_CFG30, 0x40011a5e -.set CYREG_B1_P5_U0_CFG31, 0x40011a5f -.set CYREG_B1_P5_U0_DCFG0, 0x40011a60 -.set CYREG_B1_P5_U0_DCFG1, 0x40011a62 -.set CYREG_B1_P5_U0_DCFG2, 0x40011a64 -.set CYREG_B1_P5_U0_DCFG3, 0x40011a66 -.set CYREG_B1_P5_U0_DCFG4, 0x40011a68 -.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a -.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c -.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e -.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 -.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 -.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80 -.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84 -.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88 -.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c -.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90 -.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94 -.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98 -.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c -.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0 -.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4 -.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8 -.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac -.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0 -.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2 -.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4 -.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6 -.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 -.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba -.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc -.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe -.set CYREG_B1_P5_U1_CFG0, 0x40011ac0 -.set CYREG_B1_P5_U1_CFG1, 0x40011ac1 -.set CYREG_B1_P5_U1_CFG2, 0x40011ac2 -.set CYREG_B1_P5_U1_CFG3, 0x40011ac3 -.set CYREG_B1_P5_U1_CFG4, 0x40011ac4 -.set CYREG_B1_P5_U1_CFG5, 0x40011ac5 -.set CYREG_B1_P5_U1_CFG6, 0x40011ac6 -.set CYREG_B1_P5_U1_CFG7, 0x40011ac7 -.set CYREG_B1_P5_U1_CFG8, 0x40011ac8 -.set CYREG_B1_P5_U1_CFG9, 0x40011ac9 -.set CYREG_B1_P5_U1_CFG10, 0x40011aca -.set CYREG_B1_P5_U1_CFG11, 0x40011acb -.set CYREG_B1_P5_U1_CFG12, 0x40011acc -.set CYREG_B1_P5_U1_CFG13, 0x40011acd -.set CYREG_B1_P5_U1_CFG14, 0x40011ace -.set CYREG_B1_P5_U1_CFG15, 0x40011acf -.set CYREG_B1_P5_U1_CFG16, 0x40011ad0 -.set CYREG_B1_P5_U1_CFG17, 0x40011ad1 -.set CYREG_B1_P5_U1_CFG18, 0x40011ad2 -.set CYREG_B1_P5_U1_CFG19, 0x40011ad3 -.set CYREG_B1_P5_U1_CFG20, 0x40011ad4 -.set CYREG_B1_P5_U1_CFG21, 0x40011ad5 -.set CYREG_B1_P5_U1_CFG22, 0x40011ad6 -.set CYREG_B1_P5_U1_CFG23, 0x40011ad7 -.set CYREG_B1_P5_U1_CFG24, 0x40011ad8 -.set CYREG_B1_P5_U1_CFG25, 0x40011ad9 -.set CYREG_B1_P5_U1_CFG26, 0x40011ada -.set CYREG_B1_P5_U1_CFG27, 0x40011adb -.set CYREG_B1_P5_U1_CFG28, 0x40011adc -.set CYREG_B1_P5_U1_CFG29, 0x40011add -.set CYREG_B1_P5_U1_CFG30, 0x40011ade -.set CYREG_B1_P5_U1_CFG31, 0x40011adf -.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0 -.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2 -.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4 -.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6 -.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8 -.set CYREG_B1_P5_U1_DCFG5, 0x40011aea -.set CYREG_B1_P5_U1_DCFG6, 0x40011aec -.set CYREG_B1_P5_U1_DCFG7, 0x40011aee -.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 -.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI0_BASE, 0x40014000 -.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI1_BASE, 0x40014100 -.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI2_BASE, 0x40014200 -.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI3_BASE, 0x40014300 -.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI4_BASE, 0x40014400 -.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI5_BASE, 0x40014500 -.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI6_BASE, 0x40014600 -.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI7_BASE, 0x40014700 -.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI8_BASE, 0x40014800 -.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI9_BASE, 0x40014900 -.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 -.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef -.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 -.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef -.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 -.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 -.set CYREG_BCTL0_MDCLK_EN, 0x40015000 -.set CYREG_BCTL0_MBCLK_EN, 0x40015001 -.set CYREG_BCTL0_WAIT_CFG, 0x40015002 -.set CYREG_BCTL0_BANK_CTL, 0x40015003 -.set CYREG_BCTL0_UDB_TEST_3, 0x40015007 -.set CYREG_BCTL0_DCLK_EN0, 0x40015008 -.set CYREG_BCTL0_BCLK_EN0, 0x40015009 -.set CYREG_BCTL0_DCLK_EN1, 0x4001500a -.set CYREG_BCTL0_BCLK_EN1, 0x4001500b -.set CYREG_BCTL0_DCLK_EN2, 0x4001500c -.set CYREG_BCTL0_BCLK_EN2, 0x4001500d -.set CYREG_BCTL0_DCLK_EN3, 0x4001500e -.set CYREG_BCTL0_BCLK_EN3, 0x4001500f -.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 -.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 -.set CYREG_BCTL1_MDCLK_EN, 0x40015010 -.set CYREG_BCTL1_MBCLK_EN, 0x40015011 -.set CYREG_BCTL1_WAIT_CFG, 0x40015012 -.set CYREG_BCTL1_BANK_CTL, 0x40015013 -.set CYREG_BCTL1_UDB_TEST_3, 0x40015017 -.set CYREG_BCTL1_DCLK_EN0, 0x40015018 -.set CYREG_BCTL1_BCLK_EN0, 0x40015019 -.set CYREG_BCTL1_DCLK_EN1, 0x4001501a -.set CYREG_BCTL1_BCLK_EN1, 0x4001501b -.set CYREG_BCTL1_DCLK_EN2, 0x4001501c -.set CYREG_BCTL1_BCLK_EN2, 0x4001501d -.set CYREG_BCTL1_DCLK_EN3, 0x4001501e -.set CYREG_BCTL1_BCLK_EN3, 0x4001501f -.set CYDEV_IDMUX_BASE, 0x40015100 -.set CYDEV_IDMUX_SIZE, 0x00000016 -.set CYREG_IDMUX_IRQ_CTL0, 0x40015100 -.set CYREG_IDMUX_IRQ_CTL1, 0x40015101 -.set CYREG_IDMUX_IRQ_CTL2, 0x40015102 -.set CYREG_IDMUX_IRQ_CTL3, 0x40015103 -.set CYREG_IDMUX_IRQ_CTL4, 0x40015104 -.set CYREG_IDMUX_IRQ_CTL5, 0x40015105 -.set CYREG_IDMUX_IRQ_CTL6, 0x40015106 -.set CYREG_IDMUX_IRQ_CTL7, 0x40015107 -.set CYREG_IDMUX_DRQ_CTL0, 0x40015110 -.set CYREG_IDMUX_DRQ_CTL1, 0x40015111 -.set CYREG_IDMUX_DRQ_CTL2, 0x40015112 -.set CYREG_IDMUX_DRQ_CTL3, 0x40015113 -.set CYREG_IDMUX_DRQ_CTL4, 0x40015114 -.set CYREG_IDMUX_DRQ_CTL5, 0x40015115 -.set CYDEV_CACHERAM_BASE, 0x40030000 -.set CYDEV_CACHERAM_SIZE, 0x00000400 -.set CYREG_CACHERAM_DATA_MBASE, 0x40030000 -.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400 -.set CYDEV_SFR_BASE, 0x40050100 -.set CYDEV_SFR_SIZE, 0x000000fb -.set CYREG_SFR_GPIO0, 0x40050180 -.set CYREG_SFR_GPIRD0, 0x40050189 -.set CYREG_SFR_GPIO0_SEL, 0x4005018a -.set CYREG_SFR_GPIO1, 0x40050190 -.set CYREG_SFR_GPIRD1, 0x40050191 -.set CYREG_SFR_GPIO2, 0x40050198 -.set CYREG_SFR_GPIRD2, 0x40050199 -.set CYREG_SFR_GPIO2_SEL, 0x4005019a -.set CYREG_SFR_GPIO1_SEL, 0x400501a2 -.set CYREG_SFR_GPIO3, 0x400501b0 -.set CYREG_SFR_GPIRD3, 0x400501b1 -.set CYREG_SFR_GPIO3_SEL, 0x400501b2 -.set CYREG_SFR_GPIO4, 0x400501c0 -.set CYREG_SFR_GPIRD4, 0x400501c1 -.set CYREG_SFR_GPIO4_SEL, 0x400501c2 -.set CYREG_SFR_GPIO5, 0x400501c8 -.set CYREG_SFR_GPIRD5, 0x400501c9 -.set CYREG_SFR_GPIO5_SEL, 0x400501ca -.set CYREG_SFR_GPIO6, 0x400501d8 -.set CYREG_SFR_GPIRD6, 0x400501d9 -.set CYREG_SFR_GPIO6_SEL, 0x400501da -.set CYREG_SFR_GPIO12, 0x400501e8 -.set CYREG_SFR_GPIRD12, 0x400501e9 -.set CYREG_SFR_GPIO12_SEL, 0x400501f2 -.set CYREG_SFR_GPIO15, 0x400501f8 -.set CYREG_SFR_GPIRD15, 0x400501f9 -.set CYREG_SFR_GPIO15_SEL, 0x400501fa -.set CYDEV_P3BA_BASE, 0x40050300 -.set CYDEV_P3BA_SIZE, 0x0000002b -.set CYREG_P3BA_Y_START, 0x40050300 -.set CYREG_P3BA_YROLL, 0x40050301 -.set CYREG_P3BA_YCFG, 0x40050302 -.set CYREG_P3BA_X_START1, 0x40050303 -.set CYREG_P3BA_X_START2, 0x40050304 -.set CYREG_P3BA_XROLL1, 0x40050305 -.set CYREG_P3BA_XROLL2, 0x40050306 -.set CYREG_P3BA_XINC, 0x40050307 -.set CYREG_P3BA_XCFG, 0x40050308 -.set CYREG_P3BA_OFFSETADDR1, 0x40050309 -.set CYREG_P3BA_OFFSETADDR2, 0x4005030a -.set CYREG_P3BA_OFFSETADDR3, 0x4005030b -.set CYREG_P3BA_ABSADDR1, 0x4005030c -.set CYREG_P3BA_ABSADDR2, 0x4005030d -.set CYREG_P3BA_ABSADDR3, 0x4005030e -.set CYREG_P3BA_ABSADDR4, 0x4005030f -.set CYREG_P3BA_DATCFG1, 0x40050310 -.set CYREG_P3BA_DATCFG2, 0x40050311 -.set CYREG_P3BA_CMP_RSLT1, 0x40050314 -.set CYREG_P3BA_CMP_RSLT2, 0x40050315 -.set CYREG_P3BA_CMP_RSLT3, 0x40050316 -.set CYREG_P3BA_CMP_RSLT4, 0x40050317 -.set CYREG_P3BA_DATA_REG1, 0x40050318 -.set CYREG_P3BA_DATA_REG2, 0x40050319 -.set CYREG_P3BA_DATA_REG3, 0x4005031a -.set CYREG_P3BA_DATA_REG4, 0x4005031b -.set CYREG_P3BA_EXP_DATA1, 0x4005031c -.set CYREG_P3BA_EXP_DATA2, 0x4005031d -.set CYREG_P3BA_EXP_DATA3, 0x4005031e -.set CYREG_P3BA_EXP_DATA4, 0x4005031f -.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320 -.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321 -.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322 -.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323 -.set CYREG_P3BA_BIST_EN, 0x40050324 -.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325 -.set CYREG_P3BA_SEQCFG1, 0x40050326 -.set CYREG_P3BA_SEQCFG2, 0x40050327 -.set CYREG_P3BA_Y_CURR, 0x40050328 -.set CYREG_P3BA_X_CURR1, 0x40050329 -.set CYREG_P3BA_X_CURR2, 0x4005032a -.set CYDEV_PANTHER_BASE, 0x40080000 -.set CYDEV_PANTHER_SIZE, 0x00000020 -.set CYREG_PANTHER_STCALIB_CFG, 0x40080000 -.set CYREG_PANTHER_WAITPIPE, 0x40080004 -.set CYREG_PANTHER_TRACE_CFG, 0x40080008 -.set CYREG_PANTHER_DBG_CFG, 0x4008000c -.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018 -.set CYREG_PANTHER_DEVICE_ID, 0x4008001c -.set CYDEV_FLSECC_BASE, 0x48000000 -.set CYDEV_FLSECC_SIZE, 0x00008000 -.set CYREG_FLSECC_DATA_MBASE, 0x48000000 -.set CYREG_FLSECC_DATA_MSIZE, 0x00008000 -.set CYDEV_FLSHID_BASE, 0x49000000 -.set CYDEV_FLSHID_SIZE, 0x00000200 -.set CYREG_FLSHID_RSVD_MBASE, 0x49000000 -.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080 -.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080 -.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080 -.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 -.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 -.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 -.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101 -.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 -.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 -.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 -.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 -.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 -.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107 -.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 -.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 -.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a -.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b -.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c -.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d -.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e -.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f -.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 -.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 -.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 -.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 -.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 -.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 -.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 -.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 -.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 -.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 -.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a -.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b -.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c -.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d -.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e -.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f -.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 -.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 -.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 -.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 -.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 -.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 -.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 -.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 -.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 -.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 -.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a -.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b -.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c -.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d -.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e -.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f -.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 -.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 -.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 -.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 -.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 -.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 -.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 -.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 -.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 -.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 -.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a -.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b -.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c -.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d -.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e -.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f -.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 -.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 -.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 -.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac -.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae -.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 -.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 -.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 -.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 -.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 -.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba -.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce -.set CYDEV_EXTMEM_BASE, 0x60000000 -.set CYDEV_EXTMEM_SIZE, 0x00800000 -.set CYREG_EXTMEM_DATA_MBASE, 0x60000000 -.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000 -.set CYDEV_ITM_BASE, 0xe0000000 -.set CYDEV_ITM_SIZE, 0x00001000 -.set CYREG_ITM_TRACE_EN, 0xe0000e00 -.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40 -.set CYREG_ITM_TRACE_CTRL, 0xe0000e80 -.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0 -.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4 -.set CYREG_ITM_PID4, 0xe0000fd0 -.set CYREG_ITM_PID5, 0xe0000fd4 -.set CYREG_ITM_PID6, 0xe0000fd8 -.set CYREG_ITM_PID7, 0xe0000fdc -.set CYREG_ITM_PID0, 0xe0000fe0 -.set CYREG_ITM_PID1, 0xe0000fe4 -.set CYREG_ITM_PID2, 0xe0000fe8 -.set CYREG_ITM_PID3, 0xe0000fec -.set CYREG_ITM_CID0, 0xe0000ff0 -.set CYREG_ITM_CID1, 0xe0000ff4 -.set CYREG_ITM_CID2, 0xe0000ff8 -.set CYREG_ITM_CID3, 0xe0000ffc -.set CYDEV_DWT_BASE, 0xe0001000 -.set CYDEV_DWT_SIZE, 0x0000005c -.set CYREG_DWT_CTRL, 0xe0001000 -.set CYREG_DWT_CYCLE_COUNT, 0xe0001004 -.set CYREG_DWT_CPI_COUNT, 0xe0001008 -.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c -.set CYREG_DWT_SLEEP_COUNT, 0xe0001010 -.set CYREG_DWT_LSU_COUNT, 0xe0001014 -.set CYREG_DWT_FOLD_COUNT, 0xe0001018 -.set CYREG_DWT_PC_SAMPLE, 0xe000101c -.set CYREG_DWT_COMP_0, 0xe0001020 -.set CYREG_DWT_MASK_0, 0xe0001024 -.set CYREG_DWT_FUNCTION_0, 0xe0001028 -.set CYREG_DWT_COMP_1, 0xe0001030 -.set CYREG_DWT_MASK_1, 0xe0001034 -.set CYREG_DWT_FUNCTION_1, 0xe0001038 -.set CYREG_DWT_COMP_2, 0xe0001040 -.set CYREG_DWT_MASK_2, 0xe0001044 -.set CYREG_DWT_FUNCTION_2, 0xe0001048 -.set CYREG_DWT_COMP_3, 0xe0001050 -.set CYREG_DWT_MASK_3, 0xe0001054 -.set CYREG_DWT_FUNCTION_3, 0xe0001058 -.set CYDEV_FPB_BASE, 0xe0002000 -.set CYDEV_FPB_SIZE, 0x00001000 -.set CYREG_FPB_CTRL, 0xe0002000 -.set CYREG_FPB_REMAP, 0xe0002004 -.set CYREG_FPB_FP_COMP_0, 0xe0002008 -.set CYREG_FPB_FP_COMP_1, 0xe000200c -.set CYREG_FPB_FP_COMP_2, 0xe0002010 -.set CYREG_FPB_FP_COMP_3, 0xe0002014 -.set CYREG_FPB_FP_COMP_4, 0xe0002018 -.set CYREG_FPB_FP_COMP_5, 0xe000201c -.set CYREG_FPB_FP_COMP_6, 0xe0002020 -.set CYREG_FPB_FP_COMP_7, 0xe0002024 -.set CYREG_FPB_PID4, 0xe0002fd0 -.set CYREG_FPB_PID5, 0xe0002fd4 -.set CYREG_FPB_PID6, 0xe0002fd8 -.set CYREG_FPB_PID7, 0xe0002fdc -.set CYREG_FPB_PID0, 0xe0002fe0 -.set CYREG_FPB_PID1, 0xe0002fe4 -.set CYREG_FPB_PID2, 0xe0002fe8 -.set CYREG_FPB_PID3, 0xe0002fec -.set CYREG_FPB_CID0, 0xe0002ff0 -.set CYREG_FPB_CID1, 0xe0002ff4 -.set CYREG_FPB_CID2, 0xe0002ff8 -.set CYREG_FPB_CID3, 0xe0002ffc -.set CYDEV_NVIC_BASE, 0xe000e000 -.set CYDEV_NVIC_SIZE, 0x00000d3c -.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004 -.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010 -.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014 -.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018 -.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c -.set CYREG_NVIC_SETENA0, 0xe000e100 -.set CYREG_NVIC_CLRENA0, 0xe000e180 -.set CYREG_NVIC_SETPEND0, 0xe000e200 -.set CYREG_NVIC_CLRPEND0, 0xe000e280 -.set CYREG_NVIC_ACTIVE0, 0xe000e300 -.set CYREG_NVIC_PRI_0, 0xe000e400 -.set CYREG_NVIC_PRI_1, 0xe000e401 -.set CYREG_NVIC_PRI_2, 0xe000e402 -.set CYREG_NVIC_PRI_3, 0xe000e403 -.set CYREG_NVIC_PRI_4, 0xe000e404 -.set CYREG_NVIC_PRI_5, 0xe000e405 -.set CYREG_NVIC_PRI_6, 0xe000e406 -.set CYREG_NVIC_PRI_7, 0xe000e407 -.set CYREG_NVIC_PRI_8, 0xe000e408 -.set CYREG_NVIC_PRI_9, 0xe000e409 -.set CYREG_NVIC_PRI_10, 0xe000e40a -.set CYREG_NVIC_PRI_11, 0xe000e40b -.set CYREG_NVIC_PRI_12, 0xe000e40c -.set CYREG_NVIC_PRI_13, 0xe000e40d -.set CYREG_NVIC_PRI_14, 0xe000e40e -.set CYREG_NVIC_PRI_15, 0xe000e40f -.set CYREG_NVIC_PRI_16, 0xe000e410 -.set CYREG_NVIC_PRI_17, 0xe000e411 -.set CYREG_NVIC_PRI_18, 0xe000e412 -.set CYREG_NVIC_PRI_19, 0xe000e413 -.set CYREG_NVIC_PRI_20, 0xe000e414 -.set CYREG_NVIC_PRI_21, 0xe000e415 -.set CYREG_NVIC_PRI_22, 0xe000e416 -.set CYREG_NVIC_PRI_23, 0xe000e417 -.set CYREG_NVIC_PRI_24, 0xe000e418 -.set CYREG_NVIC_PRI_25, 0xe000e419 -.set CYREG_NVIC_PRI_26, 0xe000e41a -.set CYREG_NVIC_PRI_27, 0xe000e41b -.set CYREG_NVIC_PRI_28, 0xe000e41c -.set CYREG_NVIC_PRI_29, 0xe000e41d -.set CYREG_NVIC_PRI_30, 0xe000e41e -.set CYREG_NVIC_PRI_31, 0xe000e41f -.set CYREG_NVIC_CPUID_BASE, 0xe000ed00 -.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04 -.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08 -.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c -.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10 -.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14 -.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 -.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c -.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 -.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24 -.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 -.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29 -.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a -.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c -.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 -.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 -.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38 -.set CYDEV_CORE_DBG_BASE, 0xe000edf0 -.set CYDEV_CORE_DBG_SIZE, 0x00000010 -.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0 -.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4 -.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8 -.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc -.set CYDEV_TPIU_BASE, 0xe0040000 -.set CYDEV_TPIU_SIZE, 0x00001000 -.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 -.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 -.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 -.set CYREG_TPIU_PROTOCOL, 0xe00400f0 -.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300 -.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304 -.set CYREG_TPIU_TRIGGER, 0xe0040ee8 -.set CYREG_TPIU_ITETMDATA, 0xe0040eec -.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0 -.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8 -.set CYREG_TPIU_ITITMDATA, 0xe0040efc -.set CYREG_TPIU_ITCTRL, 0xe0040f00 -.set CYREG_TPIU_DEVID, 0xe0040fc8 -.set CYREG_TPIU_DEVTYPE, 0xe0040fcc -.set CYREG_TPIU_PID4, 0xe0040fd0 -.set CYREG_TPIU_PID5, 0xe0040fd4 -.set CYREG_TPIU_PID6, 0xe0040fd8 -.set CYREG_TPIU_PID7, 0xe0040fdc -.set CYREG_TPIU_PID0, 0xe0040fe0 -.set CYREG_TPIU_PID1, 0xe0040fe4 -.set CYREG_TPIU_PID2, 0xe0040fe8 -.set CYREG_TPIU_PID3, 0xe0040fec -.set CYREG_TPIU_CID0, 0xe0040ff0 -.set CYREG_TPIU_CID1, 0xe0040ff4 -.set CYREG_TPIU_CID2, 0xe0040ff8 -.set CYREG_TPIU_CID3, 0xe0040ffc -.set CYDEV_ETM_BASE, 0xe0041000 -.set CYDEV_ETM_SIZE, 0x00001000 -.set CYREG_ETM_CTL, 0xe0041000 -.set CYREG_ETM_CFG_CODE, 0xe0041004 -.set CYREG_ETM_TRIG_EVENT, 0xe0041008 -.set CYREG_ETM_STATUS, 0xe0041010 -.set CYREG_ETM_SYS_CFG, 0xe0041014 -.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020 -.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024 -.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c -.set CYREG_ETM_SYNC_FREQ, 0xe00411e0 -.set CYREG_ETM_ETM_ID, 0xe00411e4 -.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8 -.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 -.set CYREG_ETM_CS_TRACE_ID, 0xe0041200 -.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300 -.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304 -.set CYREG_ETM_PDSR, 0xe0041314 -.set CYREG_ETM_ITMISCIN, 0xe0041ee0 -.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8 -.set CYREG_ETM_ITATBCTR2, 0xe0041ef0 -.set CYREG_ETM_ITATBCTR0, 0xe0041ef8 -.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00 -.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0 -.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4 -.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0 -.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4 -.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8 -.set CYREG_ETM_DEV_TYPE, 0xe0041fcc -.set CYREG_ETM_PID4, 0xe0041fd0 -.set CYREG_ETM_PID5, 0xe0041fd4 -.set CYREG_ETM_PID6, 0xe0041fd8 -.set CYREG_ETM_PID7, 0xe0041fdc -.set CYREG_ETM_PID0, 0xe0041fe0 -.set CYREG_ETM_PID1, 0xe0041fe4 -.set CYREG_ETM_PID2, 0xe0041fe8 -.set CYREG_ETM_PID3, 0xe0041fec -.set CYREG_ETM_CID0, 0xe0041ff0 -.set CYREG_ETM_CID1, 0xe0041ff4 -.set CYREG_ETM_CID2, 0xe0041ff8 -.set CYREG_ETM_CID3, 0xe0041ffc -.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 -.set CYDEV_ROM_TABLE_SIZE, 0x00001000 -.set CYREG_ROM_TABLE_NVIC, 0xe00ff000 -.set CYREG_ROM_TABLE_DWT, 0xe00ff004 -.set CYREG_ROM_TABLE_FPB, 0xe00ff008 -.set CYREG_ROM_TABLE_ITM, 0xe00ff00c -.set CYREG_ROM_TABLE_TPIU, 0xe00ff010 -.set CYREG_ROM_TABLE_ETM, 0xe00ff014 -.set CYREG_ROM_TABLE_END, 0xe00ff018 -.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc -.set CYREG_ROM_TABLE_PID4, 0xe00fffd0 -.set CYREG_ROM_TABLE_PID5, 0xe00fffd4 -.set CYREG_ROM_TABLE_PID6, 0xe00fffd8 -.set CYREG_ROM_TABLE_PID7, 0xe00fffdc -.set CYREG_ROM_TABLE_PID0, 0xe00fffe0 -.set CYREG_ROM_TABLE_PID1, 0xe00fffe4 -.set CYREG_ROM_TABLE_PID2, 0xe00fffe8 -.set CYREG_ROM_TABLE_PID3, 0xe00fffec -.set CYREG_ROM_TABLE_CID0, 0xe00ffff0 -.set CYREG_ROM_TABLE_CID1, 0xe00ffff4 -.set CYREG_ROM_TABLE_CID2, 0xe00ffff8 -.set CYREG_ROM_TABLE_CID3, 0xe00ffffc -.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE -.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE -.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 -.set CYDEV_FLS_ROW_SIZE, 0x00000100 -.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 -.set CYDEV_ECC_ROW_SIZE, 0x00000020 -.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 -.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 -.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE -.set CYCLK_LD_DISABLE, 0x00000004 -.set CYCLK_LD_SYNC_EN, 0x00000002 -.set CYCLK_LD_LOAD, 0x00000001 -.set CYCLK_PIPE, 0x00000080 -.set CYCLK_SSS, 0x00000040 -.set CYCLK_EARLY, 0x00000020 -.set CYCLK_DUTY, 0x00000010 -.set CYCLK_SYNC, 0x00000008 -.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 -.set CYCLK_SRC_SEL_SYNC_DIG, 0 -.set CYCLK_SRC_SEL_IMO, 1 -.set CYCLK_SRC_SEL_XTAL_MHZ, 2 -.set CYCLK_SRC_SEL_XTALM, 2 -.set CYCLK_SRC_SEL_ILO, 3 -.set CYCLK_SRC_SEL_PLL, 4 -.set CYCLK_SRC_SEL_XTAL_KHZ, 5 -.set CYCLK_SRC_SEL_XTALK, 5 -.set CYCLK_SRC_SEL_DSI_G, 6 -.set CYCLK_SRC_SEL_DSI_D, 7 -.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 -.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc deleted file mode 100755 index e4f1a44..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar.inc +++ /dev/null @@ -1,5356 +0,0 @@ -; -; FILENAME: cydeviceiar.inc -; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.0 Component Pack 7 -; -; DESCRIPTION: -; This file provides all of the address values for the entire PSoC device. -; -;------------------------------------------------------------------------------- -; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying -; the software package with which this file was provided. -;------------------------------------------------------------------------------- - -#define CYDEV_FLASH_BASE 0x00000000 -#define CYDEV_FLASH_SIZE 0x00020000 -#define CYDEV_FLASH_DATA_MBASE 0x00000000 -#define CYDEV_FLASH_DATA_MSIZE 0x00020000 -#define CYDEV_SRAM_BASE 0x1fffc000 -#define CYDEV_SRAM_SIZE 0x00008000 -#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000 -#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000 -#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000 -#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000 -#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000 -#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000 -#define CYDEV_SRAM_CODE_MBASE 0x1fffc000 -#define CYDEV_SRAM_CODE_MSIZE 0x00004000 -#define CYDEV_SRAM_DATA_MBASE 0x20000000 -#define CYDEV_SRAM_DATA_MSIZE 0x00004000 -#define CYDEV_SRAM_DATA16K_MBASE 0x20001000 -#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000 -#define CYDEV_SRAM_DATA32K_MBASE 0x20002000 -#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000 -#define CYDEV_SRAM_DATA64K_MBASE 0x20004000 -#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000 -#define CYDEV_DMA_BASE 0x20008000 -#define CYDEV_DMA_SIZE 0x00008000 -#define CYDEV_DMA_SRAM64K_MBASE 0x20008000 -#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000 -#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000 -#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000 -#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000 -#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000 -#define CYDEV_DMA_SRAM_MBASE 0x2000f000 -#define CYDEV_DMA_SRAM_MSIZE 0x00001000 -#define CYDEV_CLKDIST_BASE 0x40004000 -#define CYDEV_CLKDIST_SIZE 0x00000110 -#define CYDEV_CLKDIST_CR 0x40004000 -#define CYDEV_CLKDIST_LD 0x40004001 -#define CYDEV_CLKDIST_WRK0 0x40004002 -#define CYDEV_CLKDIST_WRK1 0x40004003 -#define CYDEV_CLKDIST_MSTR0 0x40004004 -#define CYDEV_CLKDIST_MSTR1 0x40004005 -#define CYDEV_CLKDIST_BCFG0 0x40004006 -#define CYDEV_CLKDIST_BCFG1 0x40004007 -#define CYDEV_CLKDIST_BCFG2 0x40004008 -#define CYDEV_CLKDIST_UCFG 0x40004009 -#define CYDEV_CLKDIST_DLY0 0x4000400a -#define CYDEV_CLKDIST_DLY1 0x4000400b -#define CYDEV_CLKDIST_DMASK 0x40004010 -#define CYDEV_CLKDIST_AMASK 0x40004014 -#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 -#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080 -#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081 -#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082 -#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 -#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084 -#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085 -#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086 -#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 -#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088 -#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089 -#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a -#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c -#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c -#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d -#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e -#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 -#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090 -#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091 -#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092 -#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 -#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094 -#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095 -#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096 -#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 -#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098 -#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099 -#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a -#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c -#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 -#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c -#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d -#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e -#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 -#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 -#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100 -#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101 -#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102 -#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103 -#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 -#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 -#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104 -#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105 -#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106 -#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107 -#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 -#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 -#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108 -#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109 -#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a -#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b -#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c -#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 -#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c -#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d -#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e -#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f -#define CYDEV_FASTCLK_BASE 0x40004200 -#define CYDEV_FASTCLK_SIZE 0x00000026 -#define CYDEV_FASTCLK_IMO_BASE 0x40004200 -#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 -#define CYDEV_FASTCLK_IMO_CR 0x40004200 -#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 -#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 -#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210 -#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212 -#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213 -#define CYDEV_FASTCLK_PLL_BASE 0x40004220 -#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 -#define CYDEV_FASTCLK_PLL_CFG0 0x40004220 -#define CYDEV_FASTCLK_PLL_CFG1 0x40004221 -#define CYDEV_FASTCLK_PLL_P 0x40004222 -#define CYDEV_FASTCLK_PLL_Q 0x40004223 -#define CYDEV_FASTCLK_PLL_SR 0x40004225 -#define CYDEV_SLOWCLK_BASE 0x40004300 -#define CYDEV_SLOWCLK_SIZE 0x0000000b -#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 -#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 -#define CYDEV_SLOWCLK_ILO_CR0 0x40004300 -#define CYDEV_SLOWCLK_ILO_CR1 0x40004301 -#define CYDEV_SLOWCLK_X32_BASE 0x40004308 -#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 -#define CYDEV_SLOWCLK_X32_CR 0x40004308 -#define CYDEV_SLOWCLK_X32_CFG 0x40004309 -#define CYDEV_SLOWCLK_X32_TST 0x4000430a -#define CYDEV_BOOST_BASE 0x40004320 -#define CYDEV_BOOST_SIZE 0x00000007 -#define CYDEV_BOOST_CR0 0x40004320 -#define CYDEV_BOOST_CR1 0x40004321 -#define CYDEV_BOOST_CR2 0x40004322 -#define CYDEV_BOOST_CR3 0x40004323 -#define CYDEV_BOOST_SR 0x40004324 -#define CYDEV_BOOST_CR4 0x40004325 -#define CYDEV_BOOST_SR2 0x40004326 -#define CYDEV_PWRSYS_BASE 0x40004330 -#define CYDEV_PWRSYS_SIZE 0x00000002 -#define CYDEV_PWRSYS_CR0 0x40004330 -#define CYDEV_PWRSYS_CR1 0x40004331 -#define CYDEV_PM_BASE 0x40004380 -#define CYDEV_PM_SIZE 0x00000057 -#define CYDEV_PM_TW_CFG0 0x40004380 -#define CYDEV_PM_TW_CFG1 0x40004381 -#define CYDEV_PM_TW_CFG2 0x40004382 -#define CYDEV_PM_WDT_CFG 0x40004383 -#define CYDEV_PM_WDT_CR 0x40004384 -#define CYDEV_PM_INT_SR 0x40004390 -#define CYDEV_PM_MODE_CFG0 0x40004391 -#define CYDEV_PM_MODE_CFG1 0x40004392 -#define CYDEV_PM_MODE_CSR 0x40004393 -#define CYDEV_PM_USB_CR0 0x40004394 -#define CYDEV_PM_WAKEUP_CFG0 0x40004398 -#define CYDEV_PM_WAKEUP_CFG1 0x40004399 -#define CYDEV_PM_WAKEUP_CFG2 0x4000439a -#define CYDEV_PM_ACT_BASE 0x400043a0 -#define CYDEV_PM_ACT_SIZE 0x0000000e -#define CYDEV_PM_ACT_CFG0 0x400043a0 -#define CYDEV_PM_ACT_CFG1 0x400043a1 -#define CYDEV_PM_ACT_CFG2 0x400043a2 -#define CYDEV_PM_ACT_CFG3 0x400043a3 -#define CYDEV_PM_ACT_CFG4 0x400043a4 -#define CYDEV_PM_ACT_CFG5 0x400043a5 -#define CYDEV_PM_ACT_CFG6 0x400043a6 -#define CYDEV_PM_ACT_CFG7 0x400043a7 -#define CYDEV_PM_ACT_CFG8 0x400043a8 -#define CYDEV_PM_ACT_CFG9 0x400043a9 -#define CYDEV_PM_ACT_CFG10 0x400043aa -#define CYDEV_PM_ACT_CFG11 0x400043ab -#define CYDEV_PM_ACT_CFG12 0x400043ac -#define CYDEV_PM_ACT_CFG13 0x400043ad -#define CYDEV_PM_STBY_BASE 0x400043b0 -#define CYDEV_PM_STBY_SIZE 0x0000000e -#define CYDEV_PM_STBY_CFG0 0x400043b0 -#define CYDEV_PM_STBY_CFG1 0x400043b1 -#define CYDEV_PM_STBY_CFG2 0x400043b2 -#define CYDEV_PM_STBY_CFG3 0x400043b3 -#define CYDEV_PM_STBY_CFG4 0x400043b4 -#define CYDEV_PM_STBY_CFG5 0x400043b5 -#define CYDEV_PM_STBY_CFG6 0x400043b6 -#define CYDEV_PM_STBY_CFG7 0x400043b7 -#define CYDEV_PM_STBY_CFG8 0x400043b8 -#define CYDEV_PM_STBY_CFG9 0x400043b9 -#define CYDEV_PM_STBY_CFG10 0x400043ba -#define CYDEV_PM_STBY_CFG11 0x400043bb -#define CYDEV_PM_STBY_CFG12 0x400043bc -#define CYDEV_PM_STBY_CFG13 0x400043bd -#define CYDEV_PM_AVAIL_BASE 0x400043c0 -#define CYDEV_PM_AVAIL_SIZE 0x00000017 -#define CYDEV_PM_AVAIL_CR0 0x400043c0 -#define CYDEV_PM_AVAIL_CR1 0x400043c1 -#define CYDEV_PM_AVAIL_CR2 0x400043c2 -#define CYDEV_PM_AVAIL_CR3 0x400043c3 -#define CYDEV_PM_AVAIL_CR4 0x400043c4 -#define CYDEV_PM_AVAIL_CR5 0x400043c5 -#define CYDEV_PM_AVAIL_CR6 0x400043c6 -#define CYDEV_PM_AVAIL_SR0 0x400043d0 -#define CYDEV_PM_AVAIL_SR1 0x400043d1 -#define CYDEV_PM_AVAIL_SR2 0x400043d2 -#define CYDEV_PM_AVAIL_SR3 0x400043d3 -#define CYDEV_PM_AVAIL_SR4 0x400043d4 -#define CYDEV_PM_AVAIL_SR5 0x400043d5 -#define CYDEV_PM_AVAIL_SR6 0x400043d6 -#define CYDEV_PICU_BASE 0x40004500 -#define CYDEV_PICU_SIZE 0x000000b0 -#define CYDEV_PICU_INTTYPE_BASE 0x40004500 -#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 -#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 -#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506 -#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507 -#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 -#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508 -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509 -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e -#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f -#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 -#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516 -#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517 -#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 -#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518 -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519 -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e -#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f -#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 -#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526 -#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527 -#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 -#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528 -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529 -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e -#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f -#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 -#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536 -#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537 -#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 -#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566 -#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567 -#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 -#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578 -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579 -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e -#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f -#define CYDEV_PICU_STAT_BASE 0x40004580 -#define CYDEV_PICU_STAT_SIZE 0x00000010 -#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 -#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580 -#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 -#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581 -#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 -#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582 -#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 -#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583 -#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 -#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584 -#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 -#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585 -#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 -#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586 -#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c -#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c -#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f -#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 -#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f -#define CYDEV_PICU_SNAP_BASE 0x40004590 -#define CYDEV_PICU_SNAP_SIZE 0x00000010 -#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 -#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590 -#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 -#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591 -#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 -#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592 -#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 -#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593 -#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 -#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594 -#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 -#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595 -#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 -#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596 -#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c -#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c -#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f -#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 -#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f -#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 -#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 -#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 -#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0 -#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 -#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1 -#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 -#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2 -#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 -#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3 -#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 -#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4 -#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 -#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5 -#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 -#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6 -#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac -#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac -#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af -#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 -#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af -#define CYDEV_MFGCFG_BASE 0x40004600 -#define CYDEV_MFGCFG_SIZE 0x000000ed -#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 -#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 -#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 -#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608 -#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 -#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609 -#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a -#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a -#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b -#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610 -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611 -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612 -#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 -#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614 -#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 -#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 -#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616 -#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 -#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620 -#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621 -#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 -#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622 -#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623 -#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 -#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624 -#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625 -#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 -#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626 -#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627 -#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 -#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630 -#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631 -#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 -#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632 -#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633 -#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 -#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634 -#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635 -#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 -#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 -#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636 -#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637 -#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 -#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b -#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680 -#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681 -#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682 -#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683 -#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684 -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685 -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686 -#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687 -#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688 -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689 -#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a -#define CYDEV_MFGCFG_ILO_BASE 0x40004690 -#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 -#define CYDEV_MFGCFG_ILO_TR0 0x40004690 -#define CYDEV_MFGCFG_ILO_TR1 0x40004691 -#define CYDEV_MFGCFG_X32_BASE 0x40004698 -#define CYDEV_MFGCFG_X32_SIZE 0x00000001 -#define CYDEV_MFGCFG_X32_TR 0x40004698 -#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 -#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 -#define CYDEV_MFGCFG_IMO_TR0 0x400046a0 -#define CYDEV_MFGCFG_IMO_TR1 0x400046a1 -#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2 -#define CYDEV_MFGCFG_IMO_C36M 0x400046a3 -#define CYDEV_MFGCFG_IMO_TR2 0x400046a4 -#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 -#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 -#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8 -#define CYDEV_MFGCFG_DLY 0x400046c0 -#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 -#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d -#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2 -#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 -#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 -#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4 -#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5 -#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8 -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea -#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec -#define CYDEV_RESET_BASE 0x400046f0 -#define CYDEV_RESET_SIZE 0x0000000f -#define CYDEV_RESET_IPOR_CR0 0x400046f0 -#define CYDEV_RESET_IPOR_CR1 0x400046f1 -#define CYDEV_RESET_IPOR_CR2 0x400046f2 -#define CYDEV_RESET_IPOR_CR3 0x400046f3 -#define CYDEV_RESET_CR0 0x400046f4 -#define CYDEV_RESET_CR1 0x400046f5 -#define CYDEV_RESET_CR2 0x400046f6 -#define CYDEV_RESET_CR3 0x400046f7 -#define CYDEV_RESET_CR4 0x400046f8 -#define CYDEV_RESET_CR5 0x400046f9 -#define CYDEV_RESET_SR0 0x400046fa -#define CYDEV_RESET_SR1 0x400046fb -#define CYDEV_RESET_SR2 0x400046fc -#define CYDEV_RESET_SR3 0x400046fd -#define CYDEV_RESET_TR 0x400046fe -#define CYDEV_SPC_BASE 0x40004700 -#define CYDEV_SPC_SIZE 0x00000100 -#define CYDEV_SPC_FM_EE_CR 0x40004700 -#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701 -#define CYDEV_SPC_EE_SCR 0x40004702 -#define CYDEV_SPC_EE_ERR 0x40004703 -#define CYDEV_SPC_CPU_DATA 0x40004720 -#define CYDEV_SPC_DMA_DATA 0x40004721 -#define CYDEV_SPC_SR 0x40004722 -#define CYDEV_SPC_CR 0x40004723 -#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 -#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 -#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780 -#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 -#define CYDEV_CACHE_BASE 0x40004800 -#define CYDEV_CACHE_SIZE 0x0000009c -#define CYDEV_CACHE_CC_CTL 0x40004800 -#define CYDEV_CACHE_ECC_CORR 0x40004880 -#define CYDEV_CACHE_ECC_ERR 0x40004888 -#define CYDEV_CACHE_FLASH_ERR 0x40004890 -#define CYDEV_CACHE_HITMISS 0x40004898 -#define CYDEV_I2C_BASE 0x40004900 -#define CYDEV_I2C_SIZE 0x000000e1 -#define CYDEV_I2C_XCFG 0x400049c8 -#define CYDEV_I2C_ADR 0x400049ca -#define CYDEV_I2C_CFG 0x400049d6 -#define CYDEV_I2C_CSR 0x400049d7 -#define CYDEV_I2C_D 0x400049d8 -#define CYDEV_I2C_MCSR 0x400049d9 -#define CYDEV_I2C_CLK_DIV1 0x400049db -#define CYDEV_I2C_CLK_DIV2 0x400049dc -#define CYDEV_I2C_TMOUT_CSR 0x400049dd -#define CYDEV_I2C_TMOUT_SR 0x400049de -#define CYDEV_I2C_TMOUT_CFG0 0x400049df -#define CYDEV_I2C_TMOUT_CFG1 0x400049e0 -#define CYDEV_DEC_BASE 0x40004e00 -#define CYDEV_DEC_SIZE 0x00000015 -#define CYDEV_DEC_CR 0x40004e00 -#define CYDEV_DEC_SR 0x40004e01 -#define CYDEV_DEC_SHIFT1 0x40004e02 -#define CYDEV_DEC_SHIFT2 0x40004e03 -#define CYDEV_DEC_DR2 0x40004e04 -#define CYDEV_DEC_DR2H 0x40004e05 -#define CYDEV_DEC_DR1 0x40004e06 -#define CYDEV_DEC_OCOR 0x40004e08 -#define CYDEV_DEC_OCORM 0x40004e09 -#define CYDEV_DEC_OCORH 0x40004e0a -#define CYDEV_DEC_GCOR 0x40004e0c -#define CYDEV_DEC_GCORH 0x40004e0d -#define CYDEV_DEC_GVAL 0x40004e0e -#define CYDEV_DEC_OUTSAMP 0x40004e10 -#define CYDEV_DEC_OUTSAMPM 0x40004e11 -#define CYDEV_DEC_OUTSAMPH 0x40004e12 -#define CYDEV_DEC_OUTSAMPS 0x40004e13 -#define CYDEV_DEC_COHER 0x40004e14 -#define CYDEV_TMR0_BASE 0x40004f00 -#define CYDEV_TMR0_SIZE 0x0000000c -#define CYDEV_TMR0_CFG0 0x40004f00 -#define CYDEV_TMR0_CFG1 0x40004f01 -#define CYDEV_TMR0_CFG2 0x40004f02 -#define CYDEV_TMR0_SR0 0x40004f03 -#define CYDEV_TMR0_PER0 0x40004f04 -#define CYDEV_TMR0_PER1 0x40004f05 -#define CYDEV_TMR0_CNT_CMP0 0x40004f06 -#define CYDEV_TMR0_CNT_CMP1 0x40004f07 -#define CYDEV_TMR0_CAP0 0x40004f08 -#define CYDEV_TMR0_CAP1 0x40004f09 -#define CYDEV_TMR0_RT0 0x40004f0a -#define CYDEV_TMR0_RT1 0x40004f0b -#define CYDEV_TMR1_BASE 0x40004f0c -#define CYDEV_TMR1_SIZE 0x0000000c -#define CYDEV_TMR1_CFG0 0x40004f0c -#define CYDEV_TMR1_CFG1 0x40004f0d -#define CYDEV_TMR1_CFG2 0x40004f0e -#define CYDEV_TMR1_SR0 0x40004f0f -#define CYDEV_TMR1_PER0 0x40004f10 -#define CYDEV_TMR1_PER1 0x40004f11 -#define CYDEV_TMR1_CNT_CMP0 0x40004f12 -#define CYDEV_TMR1_CNT_CMP1 0x40004f13 -#define CYDEV_TMR1_CAP0 0x40004f14 -#define CYDEV_TMR1_CAP1 0x40004f15 -#define CYDEV_TMR1_RT0 0x40004f16 -#define CYDEV_TMR1_RT1 0x40004f17 -#define CYDEV_TMR2_BASE 0x40004f18 -#define CYDEV_TMR2_SIZE 0x0000000c -#define CYDEV_TMR2_CFG0 0x40004f18 -#define CYDEV_TMR2_CFG1 0x40004f19 -#define CYDEV_TMR2_CFG2 0x40004f1a -#define CYDEV_TMR2_SR0 0x40004f1b -#define CYDEV_TMR2_PER0 0x40004f1c -#define CYDEV_TMR2_PER1 0x40004f1d -#define CYDEV_TMR2_CNT_CMP0 0x40004f1e -#define CYDEV_TMR2_CNT_CMP1 0x40004f1f -#define CYDEV_TMR2_CAP0 0x40004f20 -#define CYDEV_TMR2_CAP1 0x40004f21 -#define CYDEV_TMR2_RT0 0x40004f22 -#define CYDEV_TMR2_RT1 0x40004f23 -#define CYDEV_TMR3_BASE 0x40004f24 -#define CYDEV_TMR3_SIZE 0x0000000c -#define CYDEV_TMR3_CFG0 0x40004f24 -#define CYDEV_TMR3_CFG1 0x40004f25 -#define CYDEV_TMR3_CFG2 0x40004f26 -#define CYDEV_TMR3_SR0 0x40004f27 -#define CYDEV_TMR3_PER0 0x40004f28 -#define CYDEV_TMR3_PER1 0x40004f29 -#define CYDEV_TMR3_CNT_CMP0 0x40004f2a -#define CYDEV_TMR3_CNT_CMP1 0x40004f2b -#define CYDEV_TMR3_CAP0 0x40004f2c -#define CYDEV_TMR3_CAP1 0x40004f2d -#define CYDEV_TMR3_RT0 0x40004f2e -#define CYDEV_TMR3_RT1 0x40004f2f -#define CYDEV_IO_BASE 0x40005000 -#define CYDEV_IO_SIZE 0x00000200 -#define CYDEV_IO_PC_BASE 0x40005000 -#define CYDEV_IO_PC_SIZE 0x00000080 -#define CYDEV_IO_PC_PRT0_BASE 0x40005000 -#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT0_PC0 0x40005000 -#define CYDEV_IO_PC_PRT0_PC1 0x40005001 -#define CYDEV_IO_PC_PRT0_PC2 0x40005002 -#define CYDEV_IO_PC_PRT0_PC3 0x40005003 -#define CYDEV_IO_PC_PRT0_PC4 0x40005004 -#define CYDEV_IO_PC_PRT0_PC5 0x40005005 -#define CYDEV_IO_PC_PRT0_PC6 0x40005006 -#define CYDEV_IO_PC_PRT0_PC7 0x40005007 -#define CYDEV_IO_PC_PRT1_BASE 0x40005008 -#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT1_PC0 0x40005008 -#define CYDEV_IO_PC_PRT1_PC1 0x40005009 -#define CYDEV_IO_PC_PRT1_PC2 0x4000500a -#define CYDEV_IO_PC_PRT1_PC3 0x4000500b -#define CYDEV_IO_PC_PRT1_PC4 0x4000500c -#define CYDEV_IO_PC_PRT1_PC5 0x4000500d -#define CYDEV_IO_PC_PRT1_PC6 0x4000500e -#define CYDEV_IO_PC_PRT1_PC7 0x4000500f -#define CYDEV_IO_PC_PRT2_BASE 0x40005010 -#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT2_PC0 0x40005010 -#define CYDEV_IO_PC_PRT2_PC1 0x40005011 -#define CYDEV_IO_PC_PRT2_PC2 0x40005012 -#define CYDEV_IO_PC_PRT2_PC3 0x40005013 -#define CYDEV_IO_PC_PRT2_PC4 0x40005014 -#define CYDEV_IO_PC_PRT2_PC5 0x40005015 -#define CYDEV_IO_PC_PRT2_PC6 0x40005016 -#define CYDEV_IO_PC_PRT2_PC7 0x40005017 -#define CYDEV_IO_PC_PRT3_BASE 0x40005018 -#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT3_PC0 0x40005018 -#define CYDEV_IO_PC_PRT3_PC1 0x40005019 -#define CYDEV_IO_PC_PRT3_PC2 0x4000501a -#define CYDEV_IO_PC_PRT3_PC3 0x4000501b -#define CYDEV_IO_PC_PRT3_PC4 0x4000501c -#define CYDEV_IO_PC_PRT3_PC5 0x4000501d -#define CYDEV_IO_PC_PRT3_PC6 0x4000501e -#define CYDEV_IO_PC_PRT3_PC7 0x4000501f -#define CYDEV_IO_PC_PRT4_BASE 0x40005020 -#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT4_PC0 0x40005020 -#define CYDEV_IO_PC_PRT4_PC1 0x40005021 -#define CYDEV_IO_PC_PRT4_PC2 0x40005022 -#define CYDEV_IO_PC_PRT4_PC3 0x40005023 -#define CYDEV_IO_PC_PRT4_PC4 0x40005024 -#define CYDEV_IO_PC_PRT4_PC5 0x40005025 -#define CYDEV_IO_PC_PRT4_PC6 0x40005026 -#define CYDEV_IO_PC_PRT4_PC7 0x40005027 -#define CYDEV_IO_PC_PRT5_BASE 0x40005028 -#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT5_PC0 0x40005028 -#define CYDEV_IO_PC_PRT5_PC1 0x40005029 -#define CYDEV_IO_PC_PRT5_PC2 0x4000502a -#define CYDEV_IO_PC_PRT5_PC3 0x4000502b -#define CYDEV_IO_PC_PRT5_PC4 0x4000502c -#define CYDEV_IO_PC_PRT5_PC5 0x4000502d -#define CYDEV_IO_PC_PRT5_PC6 0x4000502e -#define CYDEV_IO_PC_PRT5_PC7 0x4000502f -#define CYDEV_IO_PC_PRT6_BASE 0x40005030 -#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT6_PC0 0x40005030 -#define CYDEV_IO_PC_PRT6_PC1 0x40005031 -#define CYDEV_IO_PC_PRT6_PC2 0x40005032 -#define CYDEV_IO_PC_PRT6_PC3 0x40005033 -#define CYDEV_IO_PC_PRT6_PC4 0x40005034 -#define CYDEV_IO_PC_PRT6_PC5 0x40005035 -#define CYDEV_IO_PC_PRT6_PC6 0x40005036 -#define CYDEV_IO_PC_PRT6_PC7 0x40005037 -#define CYDEV_IO_PC_PRT12_BASE 0x40005060 -#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 -#define CYDEV_IO_PC_PRT12_PC0 0x40005060 -#define CYDEV_IO_PC_PRT12_PC1 0x40005061 -#define CYDEV_IO_PC_PRT12_PC2 0x40005062 -#define CYDEV_IO_PC_PRT12_PC3 0x40005063 -#define CYDEV_IO_PC_PRT12_PC4 0x40005064 -#define CYDEV_IO_PC_PRT12_PC5 0x40005065 -#define CYDEV_IO_PC_PRT12_PC6 0x40005066 -#define CYDEV_IO_PC_PRT12_PC7 0x40005067 -#define CYDEV_IO_PC_PRT15_BASE 0x40005078 -#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 -#define CYDEV_IO_PC_PRT15_PC0 0x40005078 -#define CYDEV_IO_PC_PRT15_PC1 0x40005079 -#define CYDEV_IO_PC_PRT15_PC2 0x4000507a -#define CYDEV_IO_PC_PRT15_PC3 0x4000507b -#define CYDEV_IO_PC_PRT15_PC4 0x4000507c -#define CYDEV_IO_PC_PRT15_PC5 0x4000507d -#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e -#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 -#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e -#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f -#define CYDEV_IO_DR_BASE 0x40005080 -#define CYDEV_IO_DR_SIZE 0x00000010 -#define CYDEV_IO_DR_PRT0_BASE 0x40005080 -#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080 -#define CYDEV_IO_DR_PRT1_BASE 0x40005081 -#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081 -#define CYDEV_IO_DR_PRT2_BASE 0x40005082 -#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082 -#define CYDEV_IO_DR_PRT3_BASE 0x40005083 -#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083 -#define CYDEV_IO_DR_PRT4_BASE 0x40005084 -#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084 -#define CYDEV_IO_DR_PRT5_BASE 0x40005085 -#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085 -#define CYDEV_IO_DR_PRT6_BASE 0x40005086 -#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086 -#define CYDEV_IO_DR_PRT12_BASE 0x4000508c -#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c -#define CYDEV_IO_DR_PRT15_BASE 0x4000508f -#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 -#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f -#define CYDEV_IO_PS_BASE 0x40005090 -#define CYDEV_IO_PS_SIZE 0x00000010 -#define CYDEV_IO_PS_PRT0_BASE 0x40005090 -#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090 -#define CYDEV_IO_PS_PRT1_BASE 0x40005091 -#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091 -#define CYDEV_IO_PS_PRT2_BASE 0x40005092 -#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092 -#define CYDEV_IO_PS_PRT3_BASE 0x40005093 -#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093 -#define CYDEV_IO_PS_PRT4_BASE 0x40005094 -#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094 -#define CYDEV_IO_PS_PRT5_BASE 0x40005095 -#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095 -#define CYDEV_IO_PS_PRT6_BASE 0x40005096 -#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096 -#define CYDEV_IO_PS_PRT12_BASE 0x4000509c -#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c -#define CYDEV_IO_PS_PRT15_BASE 0x4000509f -#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 -#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f -#define CYDEV_IO_PRT_BASE 0x40005100 -#define CYDEV_IO_PRT_SIZE 0x00000100 -#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 -#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT0_DR 0x40005100 -#define CYDEV_IO_PRT_PRT0_PS 0x40005101 -#define CYDEV_IO_PRT_PRT0_DM0 0x40005102 -#define CYDEV_IO_PRT_PRT0_DM1 0x40005103 -#define CYDEV_IO_PRT_PRT0_DM2 0x40005104 -#define CYDEV_IO_PRT_PRT0_SLW 0x40005105 -#define CYDEV_IO_PRT_PRT0_BYP 0x40005106 -#define CYDEV_IO_PRT_PRT0_BIE 0x40005107 -#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108 -#define CYDEV_IO_PRT_PRT0_CTL 0x40005109 -#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a -#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b -#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c -#define CYDEV_IO_PRT_PRT0_AG 0x4000510d -#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e -#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f -#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 -#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT1_DR 0x40005110 -#define CYDEV_IO_PRT_PRT1_PS 0x40005111 -#define CYDEV_IO_PRT_PRT1_DM0 0x40005112 -#define CYDEV_IO_PRT_PRT1_DM1 0x40005113 -#define CYDEV_IO_PRT_PRT1_DM2 0x40005114 -#define CYDEV_IO_PRT_PRT1_SLW 0x40005115 -#define CYDEV_IO_PRT_PRT1_BYP 0x40005116 -#define CYDEV_IO_PRT_PRT1_BIE 0x40005117 -#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118 -#define CYDEV_IO_PRT_PRT1_CTL 0x40005119 -#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a -#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b -#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c -#define CYDEV_IO_PRT_PRT1_AG 0x4000511d -#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e -#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f -#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 -#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT2_DR 0x40005120 -#define CYDEV_IO_PRT_PRT2_PS 0x40005121 -#define CYDEV_IO_PRT_PRT2_DM0 0x40005122 -#define CYDEV_IO_PRT_PRT2_DM1 0x40005123 -#define CYDEV_IO_PRT_PRT2_DM2 0x40005124 -#define CYDEV_IO_PRT_PRT2_SLW 0x40005125 -#define CYDEV_IO_PRT_PRT2_BYP 0x40005126 -#define CYDEV_IO_PRT_PRT2_BIE 0x40005127 -#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128 -#define CYDEV_IO_PRT_PRT2_CTL 0x40005129 -#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a -#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b -#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c -#define CYDEV_IO_PRT_PRT2_AG 0x4000512d -#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e -#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f -#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 -#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT3_DR 0x40005130 -#define CYDEV_IO_PRT_PRT3_PS 0x40005131 -#define CYDEV_IO_PRT_PRT3_DM0 0x40005132 -#define CYDEV_IO_PRT_PRT3_DM1 0x40005133 -#define CYDEV_IO_PRT_PRT3_DM2 0x40005134 -#define CYDEV_IO_PRT_PRT3_SLW 0x40005135 -#define CYDEV_IO_PRT_PRT3_BYP 0x40005136 -#define CYDEV_IO_PRT_PRT3_BIE 0x40005137 -#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138 -#define CYDEV_IO_PRT_PRT3_CTL 0x40005139 -#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a -#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b -#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c -#define CYDEV_IO_PRT_PRT3_AG 0x4000513d -#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e -#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f -#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 -#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT4_DR 0x40005140 -#define CYDEV_IO_PRT_PRT4_PS 0x40005141 -#define CYDEV_IO_PRT_PRT4_DM0 0x40005142 -#define CYDEV_IO_PRT_PRT4_DM1 0x40005143 -#define CYDEV_IO_PRT_PRT4_DM2 0x40005144 -#define CYDEV_IO_PRT_PRT4_SLW 0x40005145 -#define CYDEV_IO_PRT_PRT4_BYP 0x40005146 -#define CYDEV_IO_PRT_PRT4_BIE 0x40005147 -#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148 -#define CYDEV_IO_PRT_PRT4_CTL 0x40005149 -#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a -#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b -#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c -#define CYDEV_IO_PRT_PRT4_AG 0x4000514d -#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e -#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f -#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 -#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT5_DR 0x40005150 -#define CYDEV_IO_PRT_PRT5_PS 0x40005151 -#define CYDEV_IO_PRT_PRT5_DM0 0x40005152 -#define CYDEV_IO_PRT_PRT5_DM1 0x40005153 -#define CYDEV_IO_PRT_PRT5_DM2 0x40005154 -#define CYDEV_IO_PRT_PRT5_SLW 0x40005155 -#define CYDEV_IO_PRT_PRT5_BYP 0x40005156 -#define CYDEV_IO_PRT_PRT5_BIE 0x40005157 -#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158 -#define CYDEV_IO_PRT_PRT5_CTL 0x40005159 -#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a -#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b -#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c -#define CYDEV_IO_PRT_PRT5_AG 0x4000515d -#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e -#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f -#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 -#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT6_DR 0x40005160 -#define CYDEV_IO_PRT_PRT6_PS 0x40005161 -#define CYDEV_IO_PRT_PRT6_DM0 0x40005162 -#define CYDEV_IO_PRT_PRT6_DM1 0x40005163 -#define CYDEV_IO_PRT_PRT6_DM2 0x40005164 -#define CYDEV_IO_PRT_PRT6_SLW 0x40005165 -#define CYDEV_IO_PRT_PRT6_BYP 0x40005166 -#define CYDEV_IO_PRT_PRT6_BIE 0x40005167 -#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168 -#define CYDEV_IO_PRT_PRT6_CTL 0x40005169 -#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a -#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b -#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c -#define CYDEV_IO_PRT_PRT6_AG 0x4000516d -#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e -#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f -#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 -#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT12_DR 0x400051c0 -#define CYDEV_IO_PRT_PRT12_PS 0x400051c1 -#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2 -#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3 -#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4 -#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5 -#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6 -#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7 -#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8 -#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9 -#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca -#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb -#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc -#define CYDEV_IO_PRT_PRT12_AG 0x400051cd -#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce -#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf -#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 -#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 -#define CYDEV_IO_PRT_PRT15_DR 0x400051f0 -#define CYDEV_IO_PRT_PRT15_PS 0x400051f1 -#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2 -#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3 -#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4 -#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5 -#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6 -#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7 -#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8 -#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9 -#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa -#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb -#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc -#define CYDEV_IO_PRT_PRT15_AG 0x400051fd -#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe -#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff -#define CYDEV_PRTDSI_BASE 0x40005200 -#define CYDEV_PRTDSI_SIZE 0x0000007f -#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 -#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200 -#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201 -#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202 -#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203 -#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204 -#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205 -#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206 -#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 -#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208 -#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209 -#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a -#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b -#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c -#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d -#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e -#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 -#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210 -#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211 -#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212 -#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213 -#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214 -#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215 -#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216 -#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 -#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218 -#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219 -#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a -#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b -#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c -#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d -#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e -#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 -#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220 -#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221 -#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222 -#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223 -#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224 -#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225 -#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226 -#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 -#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228 -#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229 -#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a -#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b -#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c -#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d -#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e -#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 -#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230 -#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231 -#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232 -#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233 -#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234 -#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235 -#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236 -#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 -#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 -#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260 -#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261 -#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262 -#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263 -#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264 -#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265 -#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 -#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 -#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278 -#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279 -#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a -#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b -#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c -#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d -#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e -#define CYDEV_EMIF_BASE 0x40005400 -#define CYDEV_EMIF_SIZE 0x00000007 -#define CYDEV_EMIF_NO_UDB 0x40005400 -#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401 -#define CYDEV_EMIF_MEM_DWN 0x40005402 -#define CYDEV_EMIF_MEMCLK_DIV 0x40005403 -#define CYDEV_EMIF_CLOCK_EN 0x40005404 -#define CYDEV_EMIF_EM_TYPE 0x40005405 -#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406 -#define CYDEV_ANAIF_BASE 0x40005800 -#define CYDEV_ANAIF_SIZE 0x000003a9 -#define CYDEV_ANAIF_CFG_BASE 0x40005800 -#define CYDEV_ANAIF_CFG_SIZE 0x0000010f -#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 -#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800 -#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801 -#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802 -#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 -#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804 -#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805 -#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806 -#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 -#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808 -#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809 -#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a -#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c -#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c -#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d -#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e -#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 -#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820 -#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821 -#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822 -#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 -#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824 -#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825 -#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826 -#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 -#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828 -#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829 -#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a -#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c -#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 -#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c -#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d -#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e -#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 -#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 -#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840 -#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 -#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 -#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841 -#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 -#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 -#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842 -#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 -#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 -#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843 -#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 -#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848 -#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849 -#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a -#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a -#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b -#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c -#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c -#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d -#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e -#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e -#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f -#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 -#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858 -#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859 -#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a -#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a -#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b -#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c -#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c -#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d -#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e -#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e -#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f -#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 -#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868 -#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869 -#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a -#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 -#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a -#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b -#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 -#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b -#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c -#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 -#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c -#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d -#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e -#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f -#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 -#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870 -#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871 -#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 -#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872 -#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873 -#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 -#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876 -#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877 -#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 -#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878 -#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879 -#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a -#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 -#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a -#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b -#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c -#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 -#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c -#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 -#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 -#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880 -#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881 -#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882 -#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883 -#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884 -#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885 -#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886 -#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887 -#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888 -#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889 -#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a -#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b -#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c -#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d -#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e -#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f -#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890 -#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891 -#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892 -#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893 -#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894 -#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895 -#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896 -#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897 -#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898 -#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899 -#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a -#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b -#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c -#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d -#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e -#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f -#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 -#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 -#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900 -#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901 -#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902 -#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903 -#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904 -#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905 -#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906 -#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 -#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 -#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908 -#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909 -#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a -#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b -#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c -#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d -#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e -#define CYDEV_ANAIF_RT_BASE 0x40005a00 -#define CYDEV_ANAIF_RT_SIZE 0x00000162 -#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 -#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d -#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00 -#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02 -#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03 -#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04 -#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06 -#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07 -#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08 -#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a -#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b -#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c -#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 -#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d -#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10 -#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12 -#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13 -#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14 -#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16 -#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17 -#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18 -#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a -#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b -#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c -#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 -#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d -#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20 -#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22 -#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23 -#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24 -#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26 -#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27 -#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28 -#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a -#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b -#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c -#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 -#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d -#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30 -#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32 -#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33 -#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34 -#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36 -#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37 -#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38 -#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a -#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b -#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c -#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 -#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80 -#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82 -#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83 -#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84 -#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87 -#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 -#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88 -#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a -#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b -#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c -#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f -#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 -#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90 -#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92 -#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93 -#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94 -#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97 -#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 -#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98 -#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a -#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b -#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c -#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f -#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 -#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0 -#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2 -#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3 -#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4 -#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6 -#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7 -#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 -#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8 -#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca -#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb -#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc -#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace -#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf -#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 -#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0 -#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2 -#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3 -#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4 -#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6 -#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7 -#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 -#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8 -#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada -#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb -#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc -#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade -#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf -#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 -#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00 -#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02 -#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03 -#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04 -#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06 -#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07 -#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 -#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20 -#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22 -#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23 -#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24 -#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26 -#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27 -#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 -#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 -#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28 -#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a -#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b -#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c -#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e -#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f -#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 -#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 -#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40 -#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41 -#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 -#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 -#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42 -#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43 -#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 -#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 -#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44 -#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45 -#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 -#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 -#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46 -#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47 -#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 -#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 -#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50 -#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51 -#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52 -#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53 -#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54 -#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 -#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 -#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56 -#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 -#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 -#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58 -#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a -#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b -#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c -#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 -#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c -#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d -#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e -#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f -#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60 -#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61 -#define CYDEV_ANAIF_WRK_BASE 0x40005b80 -#define CYDEV_ANAIF_WRK_SIZE 0x00000029 -#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 -#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 -#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80 -#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 -#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 -#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81 -#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 -#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 -#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82 -#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 -#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 -#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83 -#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 -#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 -#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88 -#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89 -#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 -#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 -#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90 -#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91 -#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92 -#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93 -#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94 -#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 -#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 -#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96 -#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97 -#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 -#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 -#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98 -#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99 -#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a -#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b -#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c -#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 -#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 -#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0 -#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1 -#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 -#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 -#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2 -#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3 -#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 -#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 -#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8 -#define CYDEV_USB_BASE 0x40006000 -#define CYDEV_USB_SIZE 0x00000300 -#define CYDEV_USB_EP0_DR0 0x40006000 -#define CYDEV_USB_EP0_DR1 0x40006001 -#define CYDEV_USB_EP0_DR2 0x40006002 -#define CYDEV_USB_EP0_DR3 0x40006003 -#define CYDEV_USB_EP0_DR4 0x40006004 -#define CYDEV_USB_EP0_DR5 0x40006005 -#define CYDEV_USB_EP0_DR6 0x40006006 -#define CYDEV_USB_EP0_DR7 0x40006007 -#define CYDEV_USB_CR0 0x40006008 -#define CYDEV_USB_CR1 0x40006009 -#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a -#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b -#define CYDEV_USB_SIE_EP1_BASE 0x4000600c -#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c -#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d -#define CYDEV_USB_SIE_EP1_CR0 0x4000600e -#define CYDEV_USB_USBIO_CR0 0x40006010 -#define CYDEV_USB_USBIO_CR1 0x40006012 -#define CYDEV_USB_DYN_RECONFIG 0x40006014 -#define CYDEV_USB_SOF0 0x40006018 -#define CYDEV_USB_SOF1 0x40006019 -#define CYDEV_USB_SIE_EP2_BASE 0x4000601c -#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c -#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d -#define CYDEV_USB_SIE_EP2_CR0 0x4000601e -#define CYDEV_USB_EP0_CR 0x40006028 -#define CYDEV_USB_EP0_CNT 0x40006029 -#define CYDEV_USB_SIE_EP3_BASE 0x4000602c -#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c -#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d -#define CYDEV_USB_SIE_EP3_CR0 0x4000602e -#define CYDEV_USB_SIE_EP4_BASE 0x4000603c -#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c -#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d -#define CYDEV_USB_SIE_EP4_CR0 0x4000603e -#define CYDEV_USB_SIE_EP5_BASE 0x4000604c -#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c -#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d -#define CYDEV_USB_SIE_EP5_CR0 0x4000604e -#define CYDEV_USB_SIE_EP6_BASE 0x4000605c -#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c -#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d -#define CYDEV_USB_SIE_EP6_CR0 0x4000605e -#define CYDEV_USB_SIE_EP7_BASE 0x4000606c -#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c -#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d -#define CYDEV_USB_SIE_EP7_CR0 0x4000606e -#define CYDEV_USB_SIE_EP8_BASE 0x4000607c -#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 -#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c -#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d -#define CYDEV_USB_SIE_EP8_CR0 0x4000607e -#define CYDEV_USB_ARB_EP1_BASE 0x40006080 -#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP1_CFG 0x40006080 -#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081 -#define CYDEV_USB_ARB_EP1_SR 0x40006082 -#define CYDEV_USB_ARB_RW1_BASE 0x40006084 -#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW1_WA 0x40006084 -#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085 -#define CYDEV_USB_ARB_RW1_RA 0x40006086 -#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087 -#define CYDEV_USB_ARB_RW1_DR 0x40006088 -#define CYDEV_USB_BUF_SIZE 0x4000608c -#define CYDEV_USB_EP_ACTIVE 0x4000608e -#define CYDEV_USB_EP_TYPE 0x4000608f -#define CYDEV_USB_ARB_EP2_BASE 0x40006090 -#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP2_CFG 0x40006090 -#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091 -#define CYDEV_USB_ARB_EP2_SR 0x40006092 -#define CYDEV_USB_ARB_RW2_BASE 0x40006094 -#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW2_WA 0x40006094 -#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095 -#define CYDEV_USB_ARB_RW2_RA 0x40006096 -#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097 -#define CYDEV_USB_ARB_RW2_DR 0x40006098 -#define CYDEV_USB_ARB_CFG 0x4000609c -#define CYDEV_USB_USB_CLK_EN 0x4000609d -#define CYDEV_USB_ARB_INT_EN 0x4000609e -#define CYDEV_USB_ARB_INT_SR 0x4000609f -#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 -#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP3_CFG 0x400060a0 -#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1 -#define CYDEV_USB_ARB_EP3_SR 0x400060a2 -#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 -#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW3_WA 0x400060a4 -#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5 -#define CYDEV_USB_ARB_RW3_RA 0x400060a6 -#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7 -#define CYDEV_USB_ARB_RW3_DR 0x400060a8 -#define CYDEV_USB_CWA 0x400060ac -#define CYDEV_USB_CWA_MSB 0x400060ad -#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 -#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP4_CFG 0x400060b0 -#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1 -#define CYDEV_USB_ARB_EP4_SR 0x400060b2 -#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 -#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW4_WA 0x400060b4 -#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5 -#define CYDEV_USB_ARB_RW4_RA 0x400060b6 -#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7 -#define CYDEV_USB_ARB_RW4_DR 0x400060b8 -#define CYDEV_USB_DMA_THRES 0x400060bc -#define CYDEV_USB_DMA_THRES_MSB 0x400060bd -#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 -#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP5_CFG 0x400060c0 -#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1 -#define CYDEV_USB_ARB_EP5_SR 0x400060c2 -#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 -#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW5_WA 0x400060c4 -#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5 -#define CYDEV_USB_ARB_RW5_RA 0x400060c6 -#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7 -#define CYDEV_USB_ARB_RW5_DR 0x400060c8 -#define CYDEV_USB_BUS_RST_CNT 0x400060cc -#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 -#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP6_CFG 0x400060d0 -#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1 -#define CYDEV_USB_ARB_EP6_SR 0x400060d2 -#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 -#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW6_WA 0x400060d4 -#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5 -#define CYDEV_USB_ARB_RW6_RA 0x400060d6 -#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7 -#define CYDEV_USB_ARB_RW6_DR 0x400060d8 -#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 -#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP7_CFG 0x400060e0 -#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1 -#define CYDEV_USB_ARB_EP7_SR 0x400060e2 -#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 -#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW7_WA 0x400060e4 -#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5 -#define CYDEV_USB_ARB_RW7_RA 0x400060e6 -#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7 -#define CYDEV_USB_ARB_RW7_DR 0x400060e8 -#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 -#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 -#define CYDEV_USB_ARB_EP8_CFG 0x400060f0 -#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1 -#define CYDEV_USB_ARB_EP8_SR 0x400060f2 -#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 -#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 -#define CYDEV_USB_ARB_RW8_WA 0x400060f4 -#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5 -#define CYDEV_USB_ARB_RW8_RA 0x400060f6 -#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7 -#define CYDEV_USB_ARB_RW8_DR 0x400060f8 -#define CYDEV_USB_MEM_BASE 0x40006100 -#define CYDEV_USB_MEM_SIZE 0x00000200 -#define CYDEV_USB_MEM_DATA_MBASE 0x40006100 -#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200 -#define CYDEV_UWRK_BASE 0x40006400 -#define CYDEV_UWRK_SIZE 0x00000b60 -#define CYDEV_UWRK_UWRK8_BASE 0x40006400 -#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 -#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 -#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 -#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400 -#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401 -#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402 -#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403 -#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404 -#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405 -#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406 -#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407 -#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408 -#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409 -#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a -#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b -#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c -#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d -#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e -#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f -#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410 -#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411 -#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412 -#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413 -#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414 -#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415 -#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416 -#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417 -#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418 -#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419 -#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a -#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b -#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c -#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d -#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e -#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f -#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420 -#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421 -#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422 -#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423 -#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424 -#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425 -#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426 -#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427 -#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428 -#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429 -#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a -#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b -#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c -#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d -#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e -#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f -#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430 -#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431 -#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432 -#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433 -#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434 -#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435 -#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436 -#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437 -#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438 -#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439 -#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a -#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b -#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c -#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d -#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e -#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f -#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440 -#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441 -#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442 -#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443 -#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444 -#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445 -#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446 -#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447 -#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448 -#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449 -#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a -#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b -#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c -#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d -#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e -#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f -#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450 -#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451 -#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452 -#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453 -#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454 -#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455 -#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456 -#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457 -#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458 -#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459 -#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a -#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b -#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c -#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d -#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e -#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f -#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460 -#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461 -#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462 -#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463 -#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464 -#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465 -#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466 -#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467 -#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468 -#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469 -#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a -#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b -#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c -#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d -#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e -#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f -#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470 -#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471 -#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472 -#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473 -#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474 -#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475 -#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476 -#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477 -#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478 -#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479 -#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a -#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b -#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c -#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d -#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e -#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f -#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480 -#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481 -#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482 -#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483 -#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484 -#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485 -#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486 -#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487 -#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488 -#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489 -#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a -#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b -#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c -#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d -#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e -#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f -#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490 -#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491 -#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492 -#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493 -#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494 -#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495 -#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496 -#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497 -#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498 -#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499 -#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a -#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b -#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c -#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d -#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e -#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f -#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0 -#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1 -#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2 -#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3 -#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4 -#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5 -#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6 -#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7 -#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8 -#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9 -#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa -#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab -#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac -#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad -#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae -#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af -#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 -#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 -#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504 -#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505 -#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506 -#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507 -#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508 -#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509 -#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a -#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b -#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514 -#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515 -#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516 -#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517 -#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518 -#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519 -#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a -#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b -#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524 -#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525 -#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526 -#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527 -#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528 -#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529 -#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a -#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b -#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534 -#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535 -#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536 -#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537 -#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538 -#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539 -#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a -#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b -#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544 -#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545 -#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546 -#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547 -#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548 -#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549 -#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a -#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b -#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554 -#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555 -#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556 -#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557 -#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558 -#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559 -#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a -#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b -#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564 -#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565 -#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566 -#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567 -#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568 -#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569 -#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a -#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b -#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574 -#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575 -#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576 -#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577 -#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578 -#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579 -#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a -#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b -#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584 -#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585 -#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586 -#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587 -#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588 -#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589 -#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a -#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b -#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594 -#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595 -#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596 -#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597 -#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598 -#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599 -#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a -#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b -#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4 -#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5 -#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6 -#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7 -#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8 -#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9 -#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa -#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab -#define CYDEV_UWRK_UWRK16_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 -#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 -#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958 -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c -#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e -#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 -#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54 -#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56 -#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e -#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958 -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a -#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c -#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 -#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54 -#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56 -#define CYDEV_PHUB_BASE 0x40007000 -#define CYDEV_PHUB_SIZE 0x00000c00 -#define CYDEV_PHUB_CFG 0x40007000 -#define CYDEV_PHUB_ERR 0x40007004 -#define CYDEV_PHUB_ERR_ADR 0x40007008 -#define CYDEV_PHUB_CH0_BASE 0x40007010 -#define CYDEV_PHUB_CH0_SIZE 0x0000000c -#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010 -#define CYDEV_PHUB_CH0_ACTION 0x40007014 -#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018 -#define CYDEV_PHUB_CH1_BASE 0x40007020 -#define CYDEV_PHUB_CH1_SIZE 0x0000000c -#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020 -#define CYDEV_PHUB_CH1_ACTION 0x40007024 -#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028 -#define CYDEV_PHUB_CH2_BASE 0x40007030 -#define CYDEV_PHUB_CH2_SIZE 0x0000000c -#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030 -#define CYDEV_PHUB_CH2_ACTION 0x40007034 -#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038 -#define CYDEV_PHUB_CH3_BASE 0x40007040 -#define CYDEV_PHUB_CH3_SIZE 0x0000000c -#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040 -#define CYDEV_PHUB_CH3_ACTION 0x40007044 -#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048 -#define CYDEV_PHUB_CH4_BASE 0x40007050 -#define CYDEV_PHUB_CH4_SIZE 0x0000000c -#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050 -#define CYDEV_PHUB_CH4_ACTION 0x40007054 -#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058 -#define CYDEV_PHUB_CH5_BASE 0x40007060 -#define CYDEV_PHUB_CH5_SIZE 0x0000000c -#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060 -#define CYDEV_PHUB_CH5_ACTION 0x40007064 -#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068 -#define CYDEV_PHUB_CH6_BASE 0x40007070 -#define CYDEV_PHUB_CH6_SIZE 0x0000000c -#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070 -#define CYDEV_PHUB_CH6_ACTION 0x40007074 -#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078 -#define CYDEV_PHUB_CH7_BASE 0x40007080 -#define CYDEV_PHUB_CH7_SIZE 0x0000000c -#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080 -#define CYDEV_PHUB_CH7_ACTION 0x40007084 -#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088 -#define CYDEV_PHUB_CH8_BASE 0x40007090 -#define CYDEV_PHUB_CH8_SIZE 0x0000000c -#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090 -#define CYDEV_PHUB_CH8_ACTION 0x40007094 -#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098 -#define CYDEV_PHUB_CH9_BASE 0x400070a0 -#define CYDEV_PHUB_CH9_SIZE 0x0000000c -#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0 -#define CYDEV_PHUB_CH9_ACTION 0x400070a4 -#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8 -#define CYDEV_PHUB_CH10_BASE 0x400070b0 -#define CYDEV_PHUB_CH10_SIZE 0x0000000c -#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0 -#define CYDEV_PHUB_CH10_ACTION 0x400070b4 -#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8 -#define CYDEV_PHUB_CH11_BASE 0x400070c0 -#define CYDEV_PHUB_CH11_SIZE 0x0000000c -#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0 -#define CYDEV_PHUB_CH11_ACTION 0x400070c4 -#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8 -#define CYDEV_PHUB_CH12_BASE 0x400070d0 -#define CYDEV_PHUB_CH12_SIZE 0x0000000c -#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0 -#define CYDEV_PHUB_CH12_ACTION 0x400070d4 -#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8 -#define CYDEV_PHUB_CH13_BASE 0x400070e0 -#define CYDEV_PHUB_CH13_SIZE 0x0000000c -#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0 -#define CYDEV_PHUB_CH13_ACTION 0x400070e4 -#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8 -#define CYDEV_PHUB_CH14_BASE 0x400070f0 -#define CYDEV_PHUB_CH14_SIZE 0x0000000c -#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0 -#define CYDEV_PHUB_CH14_ACTION 0x400070f4 -#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8 -#define CYDEV_PHUB_CH15_BASE 0x40007100 -#define CYDEV_PHUB_CH15_SIZE 0x0000000c -#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100 -#define CYDEV_PHUB_CH15_ACTION 0x40007104 -#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108 -#define CYDEV_PHUB_CH16_BASE 0x40007110 -#define CYDEV_PHUB_CH16_SIZE 0x0000000c -#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110 -#define CYDEV_PHUB_CH16_ACTION 0x40007114 -#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118 -#define CYDEV_PHUB_CH17_BASE 0x40007120 -#define CYDEV_PHUB_CH17_SIZE 0x0000000c -#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120 -#define CYDEV_PHUB_CH17_ACTION 0x40007124 -#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128 -#define CYDEV_PHUB_CH18_BASE 0x40007130 -#define CYDEV_PHUB_CH18_SIZE 0x0000000c -#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130 -#define CYDEV_PHUB_CH18_ACTION 0x40007134 -#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138 -#define CYDEV_PHUB_CH19_BASE 0x40007140 -#define CYDEV_PHUB_CH19_SIZE 0x0000000c -#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140 -#define CYDEV_PHUB_CH19_ACTION 0x40007144 -#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148 -#define CYDEV_PHUB_CH20_BASE 0x40007150 -#define CYDEV_PHUB_CH20_SIZE 0x0000000c -#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150 -#define CYDEV_PHUB_CH20_ACTION 0x40007154 -#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158 -#define CYDEV_PHUB_CH21_BASE 0x40007160 -#define CYDEV_PHUB_CH21_SIZE 0x0000000c -#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160 -#define CYDEV_PHUB_CH21_ACTION 0x40007164 -#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168 -#define CYDEV_PHUB_CH22_BASE 0x40007170 -#define CYDEV_PHUB_CH22_SIZE 0x0000000c -#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170 -#define CYDEV_PHUB_CH22_ACTION 0x40007174 -#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178 -#define CYDEV_PHUB_CH23_BASE 0x40007180 -#define CYDEV_PHUB_CH23_SIZE 0x0000000c -#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180 -#define CYDEV_PHUB_CH23_ACTION 0x40007184 -#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188 -#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 -#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600 -#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604 -#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 -#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608 -#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c -#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 -#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610 -#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614 -#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 -#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618 -#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c -#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 -#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620 -#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624 -#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 -#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628 -#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c -#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 -#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630 -#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634 -#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 -#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638 -#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c -#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 -#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640 -#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644 -#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 -#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648 -#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c -#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 -#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650 -#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654 -#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 -#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658 -#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c -#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 -#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660 -#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664 -#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 -#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668 -#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c -#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 -#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670 -#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674 -#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 -#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678 -#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c -#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 -#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680 -#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684 -#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 -#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688 -#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c -#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 -#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690 -#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694 -#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 -#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698 -#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c -#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 -#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0 -#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4 -#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 -#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8 -#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac -#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 -#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0 -#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4 -#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 -#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 -#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8 -#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc -#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 -#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800 -#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804 -#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 -#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808 -#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c -#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 -#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810 -#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814 -#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 -#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818 -#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c -#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 -#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820 -#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824 -#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 -#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828 -#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c -#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 -#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830 -#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834 -#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 -#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838 -#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c -#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 -#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840 -#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844 -#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 -#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848 -#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c -#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 -#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850 -#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854 -#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 -#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858 -#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c -#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 -#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860 -#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864 -#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 -#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868 -#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c -#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 -#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870 -#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874 -#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 -#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878 -#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c -#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 -#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880 -#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884 -#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 -#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888 -#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c -#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 -#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890 -#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894 -#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 -#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898 -#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c -#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 -#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0 -#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4 -#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 -#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8 -#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac -#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 -#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0 -#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4 -#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 -#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8 -#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc -#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 -#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0 -#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4 -#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 -#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8 -#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc -#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 -#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0 -#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4 -#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 -#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8 -#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc -#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 -#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0 -#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4 -#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 -#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8 -#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec -#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 -#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0 -#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4 -#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 -#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8 -#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc -#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 -#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900 -#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904 -#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 -#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908 -#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c -#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 -#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910 -#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914 -#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 -#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918 -#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c -#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 -#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920 -#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924 -#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 -#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928 -#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c -#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 -#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930 -#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934 -#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 -#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938 -#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c -#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 -#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940 -#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944 -#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 -#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948 -#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c -#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 -#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950 -#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954 -#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 -#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958 -#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c -#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 -#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960 -#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964 -#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 -#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968 -#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c -#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 -#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970 -#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974 -#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 -#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978 -#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c -#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 -#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980 -#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984 -#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 -#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988 -#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c -#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 -#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990 -#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994 -#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 -#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998 -#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c -#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 -#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0 -#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4 -#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 -#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8 -#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac -#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 -#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0 -#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4 -#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 -#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8 -#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc -#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 -#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0 -#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4 -#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 -#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8 -#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc -#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 -#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0 -#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4 -#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 -#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8 -#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc -#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 -#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0 -#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4 -#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 -#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8 -#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec -#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 -#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0 -#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4 -#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 -#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8 -#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc -#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 -#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00 -#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04 -#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 -#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08 -#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c -#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 -#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10 -#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14 -#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 -#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18 -#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c -#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 -#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20 -#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24 -#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 -#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28 -#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c -#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 -#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30 -#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34 -#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 -#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38 -#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c -#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 -#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40 -#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44 -#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 -#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48 -#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c -#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 -#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50 -#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54 -#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 -#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58 -#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c -#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 -#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60 -#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64 -#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 -#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68 -#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c -#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 -#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70 -#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74 -#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 -#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78 -#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c -#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 -#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80 -#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84 -#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 -#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88 -#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c -#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 -#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90 -#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94 -#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 -#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98 -#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c -#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 -#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 -#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 -#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 -#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 -#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac -#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 -#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 -#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 -#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 -#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 -#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc -#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 -#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 -#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 -#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 -#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 -#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc -#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 -#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 -#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 -#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 -#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 -#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc -#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 -#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 -#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 -#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 -#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 -#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec -#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 -#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0 -#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4 -#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 -#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8 -#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc -#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 -#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00 -#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04 -#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 -#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08 -#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c -#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 -#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10 -#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14 -#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 -#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18 -#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c -#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 -#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20 -#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24 -#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 -#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28 -#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c -#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 -#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30 -#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34 -#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 -#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38 -#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c -#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 -#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40 -#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44 -#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 -#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48 -#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c -#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 -#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50 -#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54 -#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 -#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58 -#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c -#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 -#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60 -#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64 -#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 -#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68 -#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c -#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 -#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70 -#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74 -#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 -#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78 -#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c -#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 -#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80 -#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84 -#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 -#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88 -#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c -#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 -#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90 -#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94 -#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 -#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98 -#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c -#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 -#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 -#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 -#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 -#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 -#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac -#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 -#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 -#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 -#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 -#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 -#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc -#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 -#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 -#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 -#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 -#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 -#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc -#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 -#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 -#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 -#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 -#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 -#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc -#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 -#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0 -#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4 -#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 -#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8 -#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec -#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 -#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 -#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 -#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 -#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 -#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 -#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc -#define CYDEV_EE_BASE 0x40008000 -#define CYDEV_EE_SIZE 0x00000800 -#define CYDEV_EE_DATA_MBASE 0x40008000 -#define CYDEV_EE_DATA_MSIZE 0x00000800 -#define CYDEV_CAN0_BASE 0x4000a000 -#define CYDEV_CAN0_SIZE 0x000002a0 -#define CYDEV_CAN0_CSR_BASE 0x4000a000 -#define CYDEV_CAN0_CSR_SIZE 0x00000018 -#define CYDEV_CAN0_CSR_INT_SR 0x4000a000 -#define CYDEV_CAN0_CSR_INT_EN 0x4000a004 -#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008 -#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c -#define CYDEV_CAN0_CSR_CMD 0x4000a010 -#define CYDEV_CAN0_CSR_CFG 0x4000a014 -#define CYDEV_CAN0_TX0_BASE 0x4000a020 -#define CYDEV_CAN0_TX0_SIZE 0x00000010 -#define CYDEV_CAN0_TX0_CMD 0x4000a020 -#define CYDEV_CAN0_TX0_ID 0x4000a024 -#define CYDEV_CAN0_TX0_DH 0x4000a028 -#define CYDEV_CAN0_TX0_DL 0x4000a02c -#define CYDEV_CAN0_TX1_BASE 0x4000a030 -#define CYDEV_CAN0_TX1_SIZE 0x00000010 -#define CYDEV_CAN0_TX1_CMD 0x4000a030 -#define CYDEV_CAN0_TX1_ID 0x4000a034 -#define CYDEV_CAN0_TX1_DH 0x4000a038 -#define CYDEV_CAN0_TX1_DL 0x4000a03c -#define CYDEV_CAN0_TX2_BASE 0x4000a040 -#define CYDEV_CAN0_TX2_SIZE 0x00000010 -#define CYDEV_CAN0_TX2_CMD 0x4000a040 -#define CYDEV_CAN0_TX2_ID 0x4000a044 -#define CYDEV_CAN0_TX2_DH 0x4000a048 -#define CYDEV_CAN0_TX2_DL 0x4000a04c -#define CYDEV_CAN0_TX3_BASE 0x4000a050 -#define CYDEV_CAN0_TX3_SIZE 0x00000010 -#define CYDEV_CAN0_TX3_CMD 0x4000a050 -#define CYDEV_CAN0_TX3_ID 0x4000a054 -#define CYDEV_CAN0_TX3_DH 0x4000a058 -#define CYDEV_CAN0_TX3_DL 0x4000a05c -#define CYDEV_CAN0_TX4_BASE 0x4000a060 -#define CYDEV_CAN0_TX4_SIZE 0x00000010 -#define CYDEV_CAN0_TX4_CMD 0x4000a060 -#define CYDEV_CAN0_TX4_ID 0x4000a064 -#define CYDEV_CAN0_TX4_DH 0x4000a068 -#define CYDEV_CAN0_TX4_DL 0x4000a06c -#define CYDEV_CAN0_TX5_BASE 0x4000a070 -#define CYDEV_CAN0_TX5_SIZE 0x00000010 -#define CYDEV_CAN0_TX5_CMD 0x4000a070 -#define CYDEV_CAN0_TX5_ID 0x4000a074 -#define CYDEV_CAN0_TX5_DH 0x4000a078 -#define CYDEV_CAN0_TX5_DL 0x4000a07c -#define CYDEV_CAN0_TX6_BASE 0x4000a080 -#define CYDEV_CAN0_TX6_SIZE 0x00000010 -#define CYDEV_CAN0_TX6_CMD 0x4000a080 -#define CYDEV_CAN0_TX6_ID 0x4000a084 -#define CYDEV_CAN0_TX6_DH 0x4000a088 -#define CYDEV_CAN0_TX6_DL 0x4000a08c -#define CYDEV_CAN0_TX7_BASE 0x4000a090 -#define CYDEV_CAN0_TX7_SIZE 0x00000010 -#define CYDEV_CAN0_TX7_CMD 0x4000a090 -#define CYDEV_CAN0_TX7_ID 0x4000a094 -#define CYDEV_CAN0_TX7_DH 0x4000a098 -#define CYDEV_CAN0_TX7_DL 0x4000a09c -#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 -#define CYDEV_CAN0_RX0_SIZE 0x00000020 -#define CYDEV_CAN0_RX0_CMD 0x4000a0a0 -#define CYDEV_CAN0_RX0_ID 0x4000a0a4 -#define CYDEV_CAN0_RX0_DH 0x4000a0a8 -#define CYDEV_CAN0_RX0_DL 0x4000a0ac -#define CYDEV_CAN0_RX0_AMR 0x4000a0b0 -#define CYDEV_CAN0_RX0_ACR 0x4000a0b4 -#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8 -#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc -#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 -#define CYDEV_CAN0_RX1_SIZE 0x00000020 -#define CYDEV_CAN0_RX1_CMD 0x4000a0c0 -#define CYDEV_CAN0_RX1_ID 0x4000a0c4 -#define CYDEV_CAN0_RX1_DH 0x4000a0c8 -#define CYDEV_CAN0_RX1_DL 0x4000a0cc -#define CYDEV_CAN0_RX1_AMR 0x4000a0d0 -#define CYDEV_CAN0_RX1_ACR 0x4000a0d4 -#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8 -#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc -#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 -#define CYDEV_CAN0_RX2_SIZE 0x00000020 -#define CYDEV_CAN0_RX2_CMD 0x4000a0e0 -#define CYDEV_CAN0_RX2_ID 0x4000a0e4 -#define CYDEV_CAN0_RX2_DH 0x4000a0e8 -#define CYDEV_CAN0_RX2_DL 0x4000a0ec -#define CYDEV_CAN0_RX2_AMR 0x4000a0f0 -#define CYDEV_CAN0_RX2_ACR 0x4000a0f4 -#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8 -#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc -#define CYDEV_CAN0_RX3_BASE 0x4000a100 -#define CYDEV_CAN0_RX3_SIZE 0x00000020 -#define CYDEV_CAN0_RX3_CMD 0x4000a100 -#define CYDEV_CAN0_RX3_ID 0x4000a104 -#define CYDEV_CAN0_RX3_DH 0x4000a108 -#define CYDEV_CAN0_RX3_DL 0x4000a10c -#define CYDEV_CAN0_RX3_AMR 0x4000a110 -#define CYDEV_CAN0_RX3_ACR 0x4000a114 -#define CYDEV_CAN0_RX3_AMRD 0x4000a118 -#define CYDEV_CAN0_RX3_ACRD 0x4000a11c -#define CYDEV_CAN0_RX4_BASE 0x4000a120 -#define CYDEV_CAN0_RX4_SIZE 0x00000020 -#define CYDEV_CAN0_RX4_CMD 0x4000a120 -#define CYDEV_CAN0_RX4_ID 0x4000a124 -#define CYDEV_CAN0_RX4_DH 0x4000a128 -#define CYDEV_CAN0_RX4_DL 0x4000a12c -#define CYDEV_CAN0_RX4_AMR 0x4000a130 -#define CYDEV_CAN0_RX4_ACR 0x4000a134 -#define CYDEV_CAN0_RX4_AMRD 0x4000a138 -#define CYDEV_CAN0_RX4_ACRD 0x4000a13c -#define CYDEV_CAN0_RX5_BASE 0x4000a140 -#define CYDEV_CAN0_RX5_SIZE 0x00000020 -#define CYDEV_CAN0_RX5_CMD 0x4000a140 -#define CYDEV_CAN0_RX5_ID 0x4000a144 -#define CYDEV_CAN0_RX5_DH 0x4000a148 -#define CYDEV_CAN0_RX5_DL 0x4000a14c -#define CYDEV_CAN0_RX5_AMR 0x4000a150 -#define CYDEV_CAN0_RX5_ACR 0x4000a154 -#define CYDEV_CAN0_RX5_AMRD 0x4000a158 -#define CYDEV_CAN0_RX5_ACRD 0x4000a15c -#define CYDEV_CAN0_RX6_BASE 0x4000a160 -#define CYDEV_CAN0_RX6_SIZE 0x00000020 -#define CYDEV_CAN0_RX6_CMD 0x4000a160 -#define CYDEV_CAN0_RX6_ID 0x4000a164 -#define CYDEV_CAN0_RX6_DH 0x4000a168 -#define CYDEV_CAN0_RX6_DL 0x4000a16c -#define CYDEV_CAN0_RX6_AMR 0x4000a170 -#define CYDEV_CAN0_RX6_ACR 0x4000a174 -#define CYDEV_CAN0_RX6_AMRD 0x4000a178 -#define CYDEV_CAN0_RX6_ACRD 0x4000a17c -#define CYDEV_CAN0_RX7_BASE 0x4000a180 -#define CYDEV_CAN0_RX7_SIZE 0x00000020 -#define CYDEV_CAN0_RX7_CMD 0x4000a180 -#define CYDEV_CAN0_RX7_ID 0x4000a184 -#define CYDEV_CAN0_RX7_DH 0x4000a188 -#define CYDEV_CAN0_RX7_DL 0x4000a18c -#define CYDEV_CAN0_RX7_AMR 0x4000a190 -#define CYDEV_CAN0_RX7_ACR 0x4000a194 -#define CYDEV_CAN0_RX7_AMRD 0x4000a198 -#define CYDEV_CAN0_RX7_ACRD 0x4000a19c -#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 -#define CYDEV_CAN0_RX8_SIZE 0x00000020 -#define CYDEV_CAN0_RX8_CMD 0x4000a1a0 -#define CYDEV_CAN0_RX8_ID 0x4000a1a4 -#define CYDEV_CAN0_RX8_DH 0x4000a1a8 -#define CYDEV_CAN0_RX8_DL 0x4000a1ac -#define CYDEV_CAN0_RX8_AMR 0x4000a1b0 -#define CYDEV_CAN0_RX8_ACR 0x4000a1b4 -#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8 -#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc -#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 -#define CYDEV_CAN0_RX9_SIZE 0x00000020 -#define CYDEV_CAN0_RX9_CMD 0x4000a1c0 -#define CYDEV_CAN0_RX9_ID 0x4000a1c4 -#define CYDEV_CAN0_RX9_DH 0x4000a1c8 -#define CYDEV_CAN0_RX9_DL 0x4000a1cc -#define CYDEV_CAN0_RX9_AMR 0x4000a1d0 -#define CYDEV_CAN0_RX9_ACR 0x4000a1d4 -#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8 -#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc -#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 -#define CYDEV_CAN0_RX10_SIZE 0x00000020 -#define CYDEV_CAN0_RX10_CMD 0x4000a1e0 -#define CYDEV_CAN0_RX10_ID 0x4000a1e4 -#define CYDEV_CAN0_RX10_DH 0x4000a1e8 -#define CYDEV_CAN0_RX10_DL 0x4000a1ec -#define CYDEV_CAN0_RX10_AMR 0x4000a1f0 -#define CYDEV_CAN0_RX10_ACR 0x4000a1f4 -#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8 -#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc -#define CYDEV_CAN0_RX11_BASE 0x4000a200 -#define CYDEV_CAN0_RX11_SIZE 0x00000020 -#define CYDEV_CAN0_RX11_CMD 0x4000a200 -#define CYDEV_CAN0_RX11_ID 0x4000a204 -#define CYDEV_CAN0_RX11_DH 0x4000a208 -#define CYDEV_CAN0_RX11_DL 0x4000a20c -#define CYDEV_CAN0_RX11_AMR 0x4000a210 -#define CYDEV_CAN0_RX11_ACR 0x4000a214 -#define CYDEV_CAN0_RX11_AMRD 0x4000a218 -#define CYDEV_CAN0_RX11_ACRD 0x4000a21c -#define CYDEV_CAN0_RX12_BASE 0x4000a220 -#define CYDEV_CAN0_RX12_SIZE 0x00000020 -#define CYDEV_CAN0_RX12_CMD 0x4000a220 -#define CYDEV_CAN0_RX12_ID 0x4000a224 -#define CYDEV_CAN0_RX12_DH 0x4000a228 -#define CYDEV_CAN0_RX12_DL 0x4000a22c -#define CYDEV_CAN0_RX12_AMR 0x4000a230 -#define CYDEV_CAN0_RX12_ACR 0x4000a234 -#define CYDEV_CAN0_RX12_AMRD 0x4000a238 -#define CYDEV_CAN0_RX12_ACRD 0x4000a23c -#define CYDEV_CAN0_RX13_BASE 0x4000a240 -#define CYDEV_CAN0_RX13_SIZE 0x00000020 -#define CYDEV_CAN0_RX13_CMD 0x4000a240 -#define CYDEV_CAN0_RX13_ID 0x4000a244 -#define CYDEV_CAN0_RX13_DH 0x4000a248 -#define CYDEV_CAN0_RX13_DL 0x4000a24c -#define CYDEV_CAN0_RX13_AMR 0x4000a250 -#define CYDEV_CAN0_RX13_ACR 0x4000a254 -#define CYDEV_CAN0_RX13_AMRD 0x4000a258 -#define CYDEV_CAN0_RX13_ACRD 0x4000a25c -#define CYDEV_CAN0_RX14_BASE 0x4000a260 -#define CYDEV_CAN0_RX14_SIZE 0x00000020 -#define CYDEV_CAN0_RX14_CMD 0x4000a260 -#define CYDEV_CAN0_RX14_ID 0x4000a264 -#define CYDEV_CAN0_RX14_DH 0x4000a268 -#define CYDEV_CAN0_RX14_DL 0x4000a26c -#define CYDEV_CAN0_RX14_AMR 0x4000a270 -#define CYDEV_CAN0_RX14_ACR 0x4000a274 -#define CYDEV_CAN0_RX14_AMRD 0x4000a278 -#define CYDEV_CAN0_RX14_ACRD 0x4000a27c -#define CYDEV_CAN0_RX15_BASE 0x4000a280 -#define CYDEV_CAN0_RX15_SIZE 0x00000020 -#define CYDEV_CAN0_RX15_CMD 0x4000a280 -#define CYDEV_CAN0_RX15_ID 0x4000a284 -#define CYDEV_CAN0_RX15_DH 0x4000a288 -#define CYDEV_CAN0_RX15_DL 0x4000a28c -#define CYDEV_CAN0_RX15_AMR 0x4000a290 -#define CYDEV_CAN0_RX15_ACR 0x4000a294 -#define CYDEV_CAN0_RX15_AMRD 0x4000a298 -#define CYDEV_CAN0_RX15_ACRD 0x4000a29c -#define CYDEV_DFB0_BASE 0x4000c000 -#define CYDEV_DFB0_SIZE 0x000007b5 -#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 -#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 -#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 -#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 -#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 -#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 -#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 -#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 -#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 -#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 -#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 -#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 -#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 -#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 -#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 -#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 -#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 -#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 -#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 -#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 -#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 -#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 -#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 -#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 -#define CYDEV_DFB0_CR 0x4000c780 -#define CYDEV_DFB0_SR 0x4000c784 -#define CYDEV_DFB0_RAM_EN 0x4000c788 -#define CYDEV_DFB0_RAM_DIR 0x4000c78c -#define CYDEV_DFB0_SEMA 0x4000c790 -#define CYDEV_DFB0_DSI_CTRL 0x4000c794 -#define CYDEV_DFB0_INT_CTRL 0x4000c798 -#define CYDEV_DFB0_DMA_CTRL 0x4000c79c -#define CYDEV_DFB0_STAGEA 0x4000c7a0 -#define CYDEV_DFB0_STAGEAM 0x4000c7a1 -#define CYDEV_DFB0_STAGEAH 0x4000c7a2 -#define CYDEV_DFB0_STAGEB 0x4000c7a4 -#define CYDEV_DFB0_STAGEBM 0x4000c7a5 -#define CYDEV_DFB0_STAGEBH 0x4000c7a6 -#define CYDEV_DFB0_HOLDA 0x4000c7a8 -#define CYDEV_DFB0_HOLDAM 0x4000c7a9 -#define CYDEV_DFB0_HOLDAH 0x4000c7aa -#define CYDEV_DFB0_HOLDAS 0x4000c7ab -#define CYDEV_DFB0_HOLDB 0x4000c7ac -#define CYDEV_DFB0_HOLDBM 0x4000c7ad -#define CYDEV_DFB0_HOLDBH 0x4000c7ae -#define CYDEV_DFB0_HOLDBS 0x4000c7af -#define CYDEV_DFB0_COHER 0x4000c7b0 -#define CYDEV_DFB0_DALIGN 0x4000c7b4 -#define CYDEV_UCFG_BASE 0x40010000 -#define CYDEV_UCFG_SIZE 0x00005040 -#define CYDEV_UCFG_B0_BASE 0x40010000 -#define CYDEV_UCFG_B0_SIZE 0x00000fef -#define CYDEV_UCFG_B0_P0_BASE 0x40010000 -#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 -#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c -#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c -#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028 -#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030 -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032 -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034 -#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036 -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c -#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e -#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040 -#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041 -#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042 -#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043 -#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044 -#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045 -#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046 -#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047 -#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048 -#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049 -#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a -#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b -#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c -#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d -#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e -#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f -#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050 -#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051 -#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052 -#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053 -#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054 -#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055 -#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056 -#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057 -#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058 -#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059 -#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a -#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b -#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c -#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d -#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e -#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f -#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060 -#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062 -#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064 -#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066 -#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068 -#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a -#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c -#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e -#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 -#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c -#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c -#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8 -#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0 -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2 -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4 -#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6 -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc -#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be -#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0 -#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1 -#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2 -#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3 -#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4 -#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5 -#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6 -#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7 -#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8 -#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9 -#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca -#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb -#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc -#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd -#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce -#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf -#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0 -#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1 -#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2 -#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3 -#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4 -#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5 -#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6 -#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7 -#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8 -#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9 -#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da -#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db -#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc -#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd -#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de -#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df -#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0 -#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2 -#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4 -#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6 -#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8 -#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea -#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec -#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee -#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 -#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P1_BASE 0x40010200 -#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 -#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c -#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c -#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228 -#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230 -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232 -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234 -#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236 -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c -#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e -#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240 -#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241 -#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242 -#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243 -#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244 -#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245 -#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246 -#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247 -#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248 -#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249 -#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a -#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b -#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c -#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d -#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e -#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f -#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250 -#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251 -#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252 -#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253 -#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254 -#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255 -#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256 -#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257 -#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258 -#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259 -#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a -#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b -#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c -#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d -#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e -#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f -#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260 -#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262 -#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264 -#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266 -#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268 -#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a -#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c -#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e -#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 -#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c -#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c -#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8 -#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0 -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2 -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4 -#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6 -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc -#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be -#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0 -#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1 -#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2 -#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3 -#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4 -#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5 -#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6 -#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7 -#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8 -#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9 -#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca -#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb -#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc -#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd -#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce -#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf -#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0 -#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1 -#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2 -#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3 -#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4 -#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5 -#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6 -#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7 -#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8 -#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9 -#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da -#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db -#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc -#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd -#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de -#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df -#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0 -#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2 -#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4 -#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6 -#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8 -#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea -#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec -#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee -#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 -#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P2_BASE 0x40010400 -#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 -#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c -#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c -#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428 -#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430 -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432 -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434 -#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436 -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c -#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e -#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440 -#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441 -#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442 -#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443 -#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444 -#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445 -#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446 -#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447 -#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448 -#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449 -#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a -#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b -#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c -#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d -#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e -#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f -#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450 -#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451 -#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452 -#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453 -#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454 -#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455 -#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456 -#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457 -#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458 -#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459 -#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a -#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b -#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c -#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d -#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e -#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f -#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460 -#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462 -#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464 -#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466 -#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468 -#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a -#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c -#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e -#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 -#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c -#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c -#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8 -#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0 -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2 -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4 -#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6 -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc -#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be -#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0 -#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1 -#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2 -#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3 -#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4 -#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5 -#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6 -#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7 -#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8 -#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9 -#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca -#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb -#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc -#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd -#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce -#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf -#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0 -#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1 -#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2 -#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3 -#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4 -#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5 -#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6 -#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7 -#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8 -#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9 -#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da -#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db -#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc -#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd -#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de -#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df -#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0 -#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2 -#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4 -#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6 -#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8 -#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea -#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec -#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee -#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 -#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P3_BASE 0x40010600 -#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 -#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c -#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c -#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628 -#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630 -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632 -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634 -#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636 -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c -#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e -#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640 -#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641 -#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642 -#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643 -#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644 -#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645 -#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646 -#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647 -#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648 -#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649 -#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a -#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b -#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c -#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d -#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e -#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f -#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650 -#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651 -#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652 -#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653 -#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654 -#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655 -#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656 -#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657 -#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658 -#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659 -#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a -#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b -#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c -#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d -#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e -#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f -#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660 -#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662 -#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664 -#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666 -#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668 -#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a -#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c -#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e -#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 -#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c -#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c -#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8 -#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0 -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2 -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4 -#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6 -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc -#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be -#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0 -#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1 -#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2 -#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3 -#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4 -#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5 -#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6 -#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7 -#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8 -#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9 -#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca -#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb -#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc -#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd -#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce -#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf -#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0 -#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1 -#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2 -#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3 -#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4 -#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5 -#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6 -#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7 -#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8 -#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9 -#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da -#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db -#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc -#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd -#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de -#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df -#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0 -#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2 -#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4 -#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6 -#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8 -#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea -#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec -#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee -#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 -#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P4_BASE 0x40010800 -#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 -#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c -#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c -#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828 -#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830 -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832 -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834 -#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836 -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c -#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e -#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840 -#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841 -#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842 -#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843 -#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844 -#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845 -#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846 -#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847 -#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848 -#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849 -#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a -#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b -#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c -#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d -#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e -#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f -#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850 -#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851 -#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852 -#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853 -#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854 -#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855 -#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856 -#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857 -#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858 -#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859 -#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a -#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b -#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c -#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d -#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e -#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f -#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860 -#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862 -#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864 -#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866 -#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868 -#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a -#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c -#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e -#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 -#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c -#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c -#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8 -#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0 -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2 -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4 -#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6 -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc -#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be -#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0 -#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1 -#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2 -#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3 -#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4 -#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5 -#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6 -#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7 -#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8 -#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9 -#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca -#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb -#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc -#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd -#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce -#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf -#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0 -#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1 -#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2 -#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3 -#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4 -#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5 -#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6 -#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7 -#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8 -#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9 -#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da -#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db -#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc -#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd -#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de -#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df -#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0 -#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2 -#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4 -#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6 -#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8 -#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea -#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec -#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee -#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 -#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 -#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 -#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c -#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c -#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28 -#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30 -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32 -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34 -#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36 -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c -#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e -#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40 -#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41 -#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42 -#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43 -#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44 -#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45 -#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46 -#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47 -#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48 -#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49 -#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a -#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b -#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c -#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d -#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e -#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f -#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50 -#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51 -#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52 -#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53 -#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54 -#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55 -#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56 -#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57 -#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58 -#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59 -#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a -#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b -#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c -#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d -#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e -#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f -#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60 -#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62 -#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64 -#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66 -#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68 -#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a -#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c -#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e -#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 -#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c -#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c -#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8 -#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0 -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2 -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4 -#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6 -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc -#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe -#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0 -#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1 -#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2 -#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3 -#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4 -#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5 -#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6 -#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7 -#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8 -#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9 -#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca -#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb -#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc -#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd -#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace -#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf -#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0 -#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1 -#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2 -#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3 -#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4 -#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5 -#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6 -#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7 -#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8 -#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9 -#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada -#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb -#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc -#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add -#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade -#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf -#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0 -#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2 -#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4 -#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6 -#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8 -#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea -#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec -#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee -#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 -#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 -#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 -#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c -#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c -#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28 -#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30 -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32 -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34 -#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36 -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c -#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e -#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40 -#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41 -#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42 -#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43 -#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44 -#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45 -#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46 -#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47 -#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48 -#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49 -#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a -#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b -#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c -#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d -#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e -#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f -#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50 -#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51 -#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52 -#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53 -#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54 -#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55 -#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56 -#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57 -#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58 -#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59 -#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a -#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b -#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c -#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d -#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e -#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f -#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60 -#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62 -#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64 -#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66 -#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68 -#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a -#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c -#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e -#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 -#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c -#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c -#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8 -#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0 -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2 -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4 -#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6 -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc -#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe -#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0 -#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1 -#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2 -#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3 -#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4 -#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5 -#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6 -#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7 -#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8 -#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9 -#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca -#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb -#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc -#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd -#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce -#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf -#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0 -#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1 -#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2 -#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3 -#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4 -#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5 -#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6 -#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7 -#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8 -#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9 -#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda -#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb -#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc -#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd -#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde -#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf -#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0 -#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2 -#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4 -#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6 -#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8 -#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea -#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec -#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee -#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 -#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 -#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 -#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c -#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c -#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28 -#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30 -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32 -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34 -#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36 -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c -#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e -#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40 -#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41 -#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42 -#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43 -#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44 -#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45 -#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46 -#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47 -#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48 -#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49 -#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a -#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b -#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c -#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d -#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e -#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f -#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50 -#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51 -#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52 -#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53 -#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54 -#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55 -#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56 -#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57 -#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58 -#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59 -#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a -#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b -#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c -#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d -#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e -#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f -#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60 -#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62 -#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64 -#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66 -#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68 -#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a -#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c -#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e -#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 -#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c -#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c -#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8 -#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0 -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2 -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4 -#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6 -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc -#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe -#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0 -#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1 -#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2 -#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3 -#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4 -#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5 -#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6 -#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7 -#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8 -#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9 -#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca -#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb -#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc -#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd -#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece -#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf -#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0 -#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1 -#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2 -#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3 -#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4 -#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5 -#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6 -#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7 -#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8 -#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9 -#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda -#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb -#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc -#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd -#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede -#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf -#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0 -#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2 -#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4 -#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6 -#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8 -#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea -#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec -#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee -#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 -#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_BASE 0x40011000 -#define CYDEV_UCFG_B1_SIZE 0x00000fef -#define CYDEV_UCFG_B1_P2_BASE 0x40011400 -#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 -#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c -#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c -#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428 -#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430 -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432 -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434 -#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436 -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c -#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e -#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440 -#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441 -#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442 -#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443 -#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444 -#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445 -#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446 -#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447 -#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448 -#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449 -#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a -#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b -#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c -#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d -#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e -#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f -#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450 -#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451 -#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452 -#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453 -#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454 -#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455 -#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456 -#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457 -#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458 -#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459 -#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a -#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b -#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c -#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d -#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e -#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f -#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460 -#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462 -#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464 -#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466 -#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468 -#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a -#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c -#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e -#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 -#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c -#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c -#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8 -#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0 -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2 -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4 -#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6 -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc -#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be -#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0 -#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1 -#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2 -#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3 -#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4 -#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5 -#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6 -#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7 -#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8 -#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9 -#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca -#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb -#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc -#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd -#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce -#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf -#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0 -#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1 -#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2 -#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3 -#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4 -#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5 -#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6 -#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7 -#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8 -#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9 -#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da -#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db -#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc -#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd -#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de -#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df -#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0 -#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2 -#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4 -#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6 -#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8 -#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea -#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec -#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee -#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 -#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_P3_BASE 0x40011600 -#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 -#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c -#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c -#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628 -#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630 -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632 -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634 -#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636 -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c -#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e -#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640 -#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641 -#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642 -#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643 -#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644 -#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645 -#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646 -#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647 -#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648 -#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649 -#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a -#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b -#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c -#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d -#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e -#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f -#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650 -#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651 -#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652 -#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653 -#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654 -#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655 -#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656 -#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657 -#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658 -#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659 -#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a -#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b -#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c -#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d -#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e -#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f -#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660 -#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662 -#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664 -#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666 -#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668 -#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a -#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c -#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e -#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 -#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c -#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c -#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8 -#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0 -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2 -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4 -#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6 -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc -#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be -#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0 -#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1 -#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2 -#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3 -#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4 -#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5 -#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6 -#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7 -#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8 -#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9 -#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca -#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb -#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc -#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd -#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce -#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf -#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0 -#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1 -#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2 -#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3 -#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4 -#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5 -#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6 -#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7 -#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8 -#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9 -#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da -#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db -#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc -#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd -#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de -#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df -#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0 -#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2 -#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4 -#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6 -#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8 -#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea -#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec -#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee -#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 -#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_P4_BASE 0x40011800 -#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 -#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c -#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c -#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828 -#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830 -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832 -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834 -#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836 -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c -#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e -#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840 -#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841 -#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842 -#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843 -#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844 -#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845 -#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846 -#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847 -#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848 -#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849 -#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a -#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b -#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c -#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d -#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e -#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f -#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850 -#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851 -#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852 -#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853 -#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854 -#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855 -#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856 -#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857 -#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858 -#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859 -#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a -#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b -#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c -#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d -#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e -#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f -#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860 -#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862 -#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864 -#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866 -#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868 -#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a -#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c -#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e -#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 -#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c -#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c -#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8 -#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0 -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2 -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4 -#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6 -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc -#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be -#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0 -#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1 -#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2 -#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3 -#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4 -#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5 -#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6 -#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7 -#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8 -#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9 -#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca -#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb -#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc -#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd -#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce -#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf -#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0 -#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1 -#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2 -#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3 -#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4 -#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5 -#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6 -#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7 -#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8 -#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9 -#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da -#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db -#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc -#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd -#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de -#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df -#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0 -#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2 -#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4 -#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6 -#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8 -#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea -#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec -#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee -#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 -#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 -#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 -#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c -#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c -#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28 -#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30 -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32 -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34 -#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36 -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c -#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e -#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40 -#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41 -#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42 -#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43 -#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44 -#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45 -#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46 -#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47 -#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48 -#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49 -#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a -#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b -#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c -#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d -#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e -#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f -#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50 -#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51 -#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52 -#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53 -#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54 -#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55 -#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56 -#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57 -#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58 -#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59 -#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a -#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b -#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c -#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d -#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e -#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f -#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60 -#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62 -#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64 -#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66 -#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68 -#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a -#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c -#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e -#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 -#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c -#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c -#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8 -#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0 -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2 -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4 -#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6 -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc -#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe -#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0 -#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1 -#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2 -#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3 -#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4 -#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5 -#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6 -#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7 -#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8 -#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9 -#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca -#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb -#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc -#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd -#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace -#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf -#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0 -#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1 -#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2 -#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3 -#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4 -#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5 -#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6 -#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7 -#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8 -#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9 -#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada -#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb -#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc -#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add -#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade -#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf -#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0 -#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2 -#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4 -#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6 -#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8 -#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea -#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec -#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee -#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 -#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_DSI0_BASE 0x40014000 -#define CYDEV_UCFG_DSI0_SIZE 0x000000ef -#define CYDEV_UCFG_DSI1_BASE 0x40014100 -#define CYDEV_UCFG_DSI1_SIZE 0x000000ef -#define CYDEV_UCFG_DSI2_BASE 0x40014200 -#define CYDEV_UCFG_DSI2_SIZE 0x000000ef -#define CYDEV_UCFG_DSI3_BASE 0x40014300 -#define CYDEV_UCFG_DSI3_SIZE 0x000000ef -#define CYDEV_UCFG_DSI4_BASE 0x40014400 -#define CYDEV_UCFG_DSI4_SIZE 0x000000ef -#define CYDEV_UCFG_DSI5_BASE 0x40014500 -#define CYDEV_UCFG_DSI5_SIZE 0x000000ef -#define CYDEV_UCFG_DSI6_BASE 0x40014600 -#define CYDEV_UCFG_DSI6_SIZE 0x000000ef -#define CYDEV_UCFG_DSI7_BASE 0x40014700 -#define CYDEV_UCFG_DSI7_SIZE 0x000000ef -#define CYDEV_UCFG_DSI8_BASE 0x40014800 -#define CYDEV_UCFG_DSI8_SIZE 0x000000ef -#define CYDEV_UCFG_DSI9_BASE 0x40014900 -#define CYDEV_UCFG_DSI9_SIZE 0x000000ef -#define CYDEV_UCFG_DSI12_BASE 0x40014c00 -#define CYDEV_UCFG_DSI12_SIZE 0x000000ef -#define CYDEV_UCFG_DSI13_BASE 0x40014d00 -#define CYDEV_UCFG_DSI13_SIZE 0x000000ef -#define CYDEV_UCFG_BCTL0_BASE 0x40015000 -#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 -#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000 -#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001 -#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002 -#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003 -#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007 -#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008 -#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009 -#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a -#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b -#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c -#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d -#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e -#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f -#define CYDEV_UCFG_BCTL1_BASE 0x40015010 -#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 -#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010 -#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011 -#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012 -#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013 -#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017 -#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018 -#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019 -#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a -#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b -#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c -#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d -#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e -#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f -#define CYDEV_IDMUX_BASE 0x40015100 -#define CYDEV_IDMUX_SIZE 0x00000016 -#define CYDEV_IDMUX_IRQ_CTL0 0x40015100 -#define CYDEV_IDMUX_IRQ_CTL1 0x40015101 -#define CYDEV_IDMUX_IRQ_CTL2 0x40015102 -#define CYDEV_IDMUX_IRQ_CTL3 0x40015103 -#define CYDEV_IDMUX_IRQ_CTL4 0x40015104 -#define CYDEV_IDMUX_IRQ_CTL5 0x40015105 -#define CYDEV_IDMUX_IRQ_CTL6 0x40015106 -#define CYDEV_IDMUX_IRQ_CTL7 0x40015107 -#define CYDEV_IDMUX_DRQ_CTL0 0x40015110 -#define CYDEV_IDMUX_DRQ_CTL1 0x40015111 -#define CYDEV_IDMUX_DRQ_CTL2 0x40015112 -#define CYDEV_IDMUX_DRQ_CTL3 0x40015113 -#define CYDEV_IDMUX_DRQ_CTL4 0x40015114 -#define CYDEV_IDMUX_DRQ_CTL5 0x40015115 -#define CYDEV_CACHERAM_BASE 0x40030000 -#define CYDEV_CACHERAM_SIZE 0x00000400 -#define CYDEV_CACHERAM_DATA_MBASE 0x40030000 -#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400 -#define CYDEV_SFR_BASE 0x40050100 -#define CYDEV_SFR_SIZE 0x000000fb -#define CYDEV_SFR_GPIO0 0x40050180 -#define CYDEV_SFR_GPIRD0 0x40050189 -#define CYDEV_SFR_GPIO0_SEL 0x4005018a -#define CYDEV_SFR_GPIO1 0x40050190 -#define CYDEV_SFR_GPIRD1 0x40050191 -#define CYDEV_SFR_GPIO2 0x40050198 -#define CYDEV_SFR_GPIRD2 0x40050199 -#define CYDEV_SFR_GPIO2_SEL 0x4005019a -#define CYDEV_SFR_GPIO1_SEL 0x400501a2 -#define CYDEV_SFR_GPIO3 0x400501b0 -#define CYDEV_SFR_GPIRD3 0x400501b1 -#define CYDEV_SFR_GPIO3_SEL 0x400501b2 -#define CYDEV_SFR_GPIO4 0x400501c0 -#define CYDEV_SFR_GPIRD4 0x400501c1 -#define CYDEV_SFR_GPIO4_SEL 0x400501c2 -#define CYDEV_SFR_GPIO5 0x400501c8 -#define CYDEV_SFR_GPIRD5 0x400501c9 -#define CYDEV_SFR_GPIO5_SEL 0x400501ca -#define CYDEV_SFR_GPIO6 0x400501d8 -#define CYDEV_SFR_GPIRD6 0x400501d9 -#define CYDEV_SFR_GPIO6_SEL 0x400501da -#define CYDEV_SFR_GPIO12 0x400501e8 -#define CYDEV_SFR_GPIRD12 0x400501e9 -#define CYDEV_SFR_GPIO12_SEL 0x400501f2 -#define CYDEV_SFR_GPIO15 0x400501f8 -#define CYDEV_SFR_GPIRD15 0x400501f9 -#define CYDEV_SFR_GPIO15_SEL 0x400501fa -#define CYDEV_P3BA_BASE 0x40050300 -#define CYDEV_P3BA_SIZE 0x0000002b -#define CYDEV_P3BA_Y_START 0x40050300 -#define CYDEV_P3BA_YROLL 0x40050301 -#define CYDEV_P3BA_YCFG 0x40050302 -#define CYDEV_P3BA_X_START1 0x40050303 -#define CYDEV_P3BA_X_START2 0x40050304 -#define CYDEV_P3BA_XROLL1 0x40050305 -#define CYDEV_P3BA_XROLL2 0x40050306 -#define CYDEV_P3BA_XINC 0x40050307 -#define CYDEV_P3BA_XCFG 0x40050308 -#define CYDEV_P3BA_OFFSETADDR1 0x40050309 -#define CYDEV_P3BA_OFFSETADDR2 0x4005030a -#define CYDEV_P3BA_OFFSETADDR3 0x4005030b -#define CYDEV_P3BA_ABSADDR1 0x4005030c -#define CYDEV_P3BA_ABSADDR2 0x4005030d -#define CYDEV_P3BA_ABSADDR3 0x4005030e -#define CYDEV_P3BA_ABSADDR4 0x4005030f -#define CYDEV_P3BA_DATCFG1 0x40050310 -#define CYDEV_P3BA_DATCFG2 0x40050311 -#define CYDEV_P3BA_CMP_RSLT1 0x40050314 -#define CYDEV_P3BA_CMP_RSLT2 0x40050315 -#define CYDEV_P3BA_CMP_RSLT3 0x40050316 -#define CYDEV_P3BA_CMP_RSLT4 0x40050317 -#define CYDEV_P3BA_DATA_REG1 0x40050318 -#define CYDEV_P3BA_DATA_REG2 0x40050319 -#define CYDEV_P3BA_DATA_REG3 0x4005031a -#define CYDEV_P3BA_DATA_REG4 0x4005031b -#define CYDEV_P3BA_EXP_DATA1 0x4005031c -#define CYDEV_P3BA_EXP_DATA2 0x4005031d -#define CYDEV_P3BA_EXP_DATA3 0x4005031e -#define CYDEV_P3BA_EXP_DATA4 0x4005031f -#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320 -#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321 -#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322 -#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323 -#define CYDEV_P3BA_BIST_EN 0x40050324 -#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325 -#define CYDEV_P3BA_SEQCFG1 0x40050326 -#define CYDEV_P3BA_SEQCFG2 0x40050327 -#define CYDEV_P3BA_Y_CURR 0x40050328 -#define CYDEV_P3BA_X_CURR1 0x40050329 -#define CYDEV_P3BA_X_CURR2 0x4005032a -#define CYDEV_PANTHER_BASE 0x40080000 -#define CYDEV_PANTHER_SIZE 0x00000020 -#define CYDEV_PANTHER_STCALIB_CFG 0x40080000 -#define CYDEV_PANTHER_WAITPIPE 0x40080004 -#define CYDEV_PANTHER_TRACE_CFG 0x40080008 -#define CYDEV_PANTHER_DBG_CFG 0x4008000c -#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018 -#define CYDEV_PANTHER_DEVICE_ID 0x4008001c -#define CYDEV_FLSECC_BASE 0x48000000 -#define CYDEV_FLSECC_SIZE 0x00008000 -#define CYDEV_FLSECC_DATA_MBASE 0x48000000 -#define CYDEV_FLSECC_DATA_MSIZE 0x00008000 -#define CYDEV_FLSHID_BASE 0x49000000 -#define CYDEV_FLSHID_SIZE 0x00000200 -#define CYDEV_FLSHID_RSVD_MBASE 0x49000000 -#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080 -#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080 -#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080 -#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 -#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 -#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100 -#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101 -#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 -#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 -#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 -#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105 -#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106 -#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107 -#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 -#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 -#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a -#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b -#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c -#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d -#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e -#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f -#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 -#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 -#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 -#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 -#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 -#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 -#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 -#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 -#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118 -#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119 -#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a -#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b -#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c -#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d -#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e -#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 -#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e -#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 -#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e -#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f -#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 -#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 -#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188 -#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac -#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae -#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 -#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 -#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 -#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 -#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 -#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba -#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce -#define CYDEV_EXTMEM_BASE 0x60000000 -#define CYDEV_EXTMEM_SIZE 0x00800000 -#define CYDEV_EXTMEM_DATA_MBASE 0x60000000 -#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000 -#define CYDEV_ITM_BASE 0xe0000000 -#define CYDEV_ITM_SIZE 0x00001000 -#define CYDEV_ITM_TRACE_EN 0xe0000e00 -#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40 -#define CYDEV_ITM_TRACE_CTRL 0xe0000e80 -#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0 -#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4 -#define CYDEV_ITM_PID4 0xe0000fd0 -#define CYDEV_ITM_PID5 0xe0000fd4 -#define CYDEV_ITM_PID6 0xe0000fd8 -#define CYDEV_ITM_PID7 0xe0000fdc -#define CYDEV_ITM_PID0 0xe0000fe0 -#define CYDEV_ITM_PID1 0xe0000fe4 -#define CYDEV_ITM_PID2 0xe0000fe8 -#define CYDEV_ITM_PID3 0xe0000fec -#define CYDEV_ITM_CID0 0xe0000ff0 -#define CYDEV_ITM_CID1 0xe0000ff4 -#define CYDEV_ITM_CID2 0xe0000ff8 -#define CYDEV_ITM_CID3 0xe0000ffc -#define CYDEV_DWT_BASE 0xe0001000 -#define CYDEV_DWT_SIZE 0x0000005c -#define CYDEV_DWT_CTRL 0xe0001000 -#define CYDEV_DWT_CYCLE_COUNT 0xe0001004 -#define CYDEV_DWT_CPI_COUNT 0xe0001008 -#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c -#define CYDEV_DWT_SLEEP_COUNT 0xe0001010 -#define CYDEV_DWT_LSU_COUNT 0xe0001014 -#define CYDEV_DWT_FOLD_COUNT 0xe0001018 -#define CYDEV_DWT_PC_SAMPLE 0xe000101c -#define CYDEV_DWT_COMP_0 0xe0001020 -#define CYDEV_DWT_MASK_0 0xe0001024 -#define CYDEV_DWT_FUNCTION_0 0xe0001028 -#define CYDEV_DWT_COMP_1 0xe0001030 -#define CYDEV_DWT_MASK_1 0xe0001034 -#define CYDEV_DWT_FUNCTION_1 0xe0001038 -#define CYDEV_DWT_COMP_2 0xe0001040 -#define CYDEV_DWT_MASK_2 0xe0001044 -#define CYDEV_DWT_FUNCTION_2 0xe0001048 -#define CYDEV_DWT_COMP_3 0xe0001050 -#define CYDEV_DWT_MASK_3 0xe0001054 -#define CYDEV_DWT_FUNCTION_3 0xe0001058 -#define CYDEV_FPB_BASE 0xe0002000 -#define CYDEV_FPB_SIZE 0x00001000 -#define CYDEV_FPB_CTRL 0xe0002000 -#define CYDEV_FPB_REMAP 0xe0002004 -#define CYDEV_FPB_FP_COMP_0 0xe0002008 -#define CYDEV_FPB_FP_COMP_1 0xe000200c -#define CYDEV_FPB_FP_COMP_2 0xe0002010 -#define CYDEV_FPB_FP_COMP_3 0xe0002014 -#define CYDEV_FPB_FP_COMP_4 0xe0002018 -#define CYDEV_FPB_FP_COMP_5 0xe000201c -#define CYDEV_FPB_FP_COMP_6 0xe0002020 -#define CYDEV_FPB_FP_COMP_7 0xe0002024 -#define CYDEV_FPB_PID4 0xe0002fd0 -#define CYDEV_FPB_PID5 0xe0002fd4 -#define CYDEV_FPB_PID6 0xe0002fd8 -#define CYDEV_FPB_PID7 0xe0002fdc -#define CYDEV_FPB_PID0 0xe0002fe0 -#define CYDEV_FPB_PID1 0xe0002fe4 -#define CYDEV_FPB_PID2 0xe0002fe8 -#define CYDEV_FPB_PID3 0xe0002fec -#define CYDEV_FPB_CID0 0xe0002ff0 -#define CYDEV_FPB_CID1 0xe0002ff4 -#define CYDEV_FPB_CID2 0xe0002ff8 -#define CYDEV_FPB_CID3 0xe0002ffc -#define CYDEV_NVIC_BASE 0xe000e000 -#define CYDEV_NVIC_SIZE 0x00000d3c -#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004 -#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010 -#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014 -#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018 -#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c -#define CYDEV_NVIC_SETENA0 0xe000e100 -#define CYDEV_NVIC_CLRENA0 0xe000e180 -#define CYDEV_NVIC_SETPEND0 0xe000e200 -#define CYDEV_NVIC_CLRPEND0 0xe000e280 -#define CYDEV_NVIC_ACTIVE0 0xe000e300 -#define CYDEV_NVIC_PRI_0 0xe000e400 -#define CYDEV_NVIC_PRI_1 0xe000e401 -#define CYDEV_NVIC_PRI_2 0xe000e402 -#define CYDEV_NVIC_PRI_3 0xe000e403 -#define CYDEV_NVIC_PRI_4 0xe000e404 -#define CYDEV_NVIC_PRI_5 0xe000e405 -#define CYDEV_NVIC_PRI_6 0xe000e406 -#define CYDEV_NVIC_PRI_7 0xe000e407 -#define CYDEV_NVIC_PRI_8 0xe000e408 -#define CYDEV_NVIC_PRI_9 0xe000e409 -#define CYDEV_NVIC_PRI_10 0xe000e40a -#define CYDEV_NVIC_PRI_11 0xe000e40b -#define CYDEV_NVIC_PRI_12 0xe000e40c -#define CYDEV_NVIC_PRI_13 0xe000e40d -#define CYDEV_NVIC_PRI_14 0xe000e40e -#define CYDEV_NVIC_PRI_15 0xe000e40f -#define CYDEV_NVIC_PRI_16 0xe000e410 -#define CYDEV_NVIC_PRI_17 0xe000e411 -#define CYDEV_NVIC_PRI_18 0xe000e412 -#define CYDEV_NVIC_PRI_19 0xe000e413 -#define CYDEV_NVIC_PRI_20 0xe000e414 -#define CYDEV_NVIC_PRI_21 0xe000e415 -#define CYDEV_NVIC_PRI_22 0xe000e416 -#define CYDEV_NVIC_PRI_23 0xe000e417 -#define CYDEV_NVIC_PRI_24 0xe000e418 -#define CYDEV_NVIC_PRI_25 0xe000e419 -#define CYDEV_NVIC_PRI_26 0xe000e41a -#define CYDEV_NVIC_PRI_27 0xe000e41b -#define CYDEV_NVIC_PRI_28 0xe000e41c -#define CYDEV_NVIC_PRI_29 0xe000e41d -#define CYDEV_NVIC_PRI_30 0xe000e41e -#define CYDEV_NVIC_PRI_31 0xe000e41f -#define CYDEV_NVIC_CPUID_BASE 0xe000ed00 -#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04 -#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08 -#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c -#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10 -#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14 -#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 -#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c -#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 -#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24 -#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 -#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29 -#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a -#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c -#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 -#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 -#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38 -#define CYDEV_CORE_DBG_BASE 0xe000edf0 -#define CYDEV_CORE_DBG_SIZE 0x00000010 -#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0 -#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4 -#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8 -#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc -#define CYDEV_TPIU_BASE 0xe0040000 -#define CYDEV_TPIU_SIZE 0x00001000 -#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 -#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 -#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 -#define CYDEV_TPIU_PROTOCOL 0xe00400f0 -#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300 -#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304 -#define CYDEV_TPIU_TRIGGER 0xe0040ee8 -#define CYDEV_TPIU_ITETMDATA 0xe0040eec -#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0 -#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8 -#define CYDEV_TPIU_ITITMDATA 0xe0040efc -#define CYDEV_TPIU_ITCTRL 0xe0040f00 -#define CYDEV_TPIU_DEVID 0xe0040fc8 -#define CYDEV_TPIU_DEVTYPE 0xe0040fcc -#define CYDEV_TPIU_PID4 0xe0040fd0 -#define CYDEV_TPIU_PID5 0xe0040fd4 -#define CYDEV_TPIU_PID6 0xe0040fd8 -#define CYDEV_TPIU_PID7 0xe0040fdc -#define CYDEV_TPIU_PID0 0xe0040fe0 -#define CYDEV_TPIU_PID1 0xe0040fe4 -#define CYDEV_TPIU_PID2 0xe0040fe8 -#define CYDEV_TPIU_PID3 0xe0040fec -#define CYDEV_TPIU_CID0 0xe0040ff0 -#define CYDEV_TPIU_CID1 0xe0040ff4 -#define CYDEV_TPIU_CID2 0xe0040ff8 -#define CYDEV_TPIU_CID3 0xe0040ffc -#define CYDEV_ETM_BASE 0xe0041000 -#define CYDEV_ETM_SIZE 0x00001000 -#define CYDEV_ETM_CTL 0xe0041000 -#define CYDEV_ETM_CFG_CODE 0xe0041004 -#define CYDEV_ETM_TRIG_EVENT 0xe0041008 -#define CYDEV_ETM_STATUS 0xe0041010 -#define CYDEV_ETM_SYS_CFG 0xe0041014 -#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020 -#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024 -#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c -#define CYDEV_ETM_SYNC_FREQ 0xe00411e0 -#define CYDEV_ETM_ETM_ID 0xe00411e4 -#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8 -#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 -#define CYDEV_ETM_CS_TRACE_ID 0xe0041200 -#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300 -#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304 -#define CYDEV_ETM_PDSR 0xe0041314 -#define CYDEV_ETM_ITMISCIN 0xe0041ee0 -#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8 -#define CYDEV_ETM_ITATBCTR2 0xe0041ef0 -#define CYDEV_ETM_ITATBCTR0 0xe0041ef8 -#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00 -#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0 -#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4 -#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0 -#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4 -#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8 -#define CYDEV_ETM_DEV_TYPE 0xe0041fcc -#define CYDEV_ETM_PID4 0xe0041fd0 -#define CYDEV_ETM_PID5 0xe0041fd4 -#define CYDEV_ETM_PID6 0xe0041fd8 -#define CYDEV_ETM_PID7 0xe0041fdc -#define CYDEV_ETM_PID0 0xe0041fe0 -#define CYDEV_ETM_PID1 0xe0041fe4 -#define CYDEV_ETM_PID2 0xe0041fe8 -#define CYDEV_ETM_PID3 0xe0041fec -#define CYDEV_ETM_CID0 0xe0041ff0 -#define CYDEV_ETM_CID1 0xe0041ff4 -#define CYDEV_ETM_CID2 0xe0041ff8 -#define CYDEV_ETM_CID3 0xe0041ffc -#define CYDEV_ROM_TABLE_BASE 0xe00ff000 -#define CYDEV_ROM_TABLE_SIZE 0x00001000 -#define CYDEV_ROM_TABLE_NVIC 0xe00ff000 -#define CYDEV_ROM_TABLE_DWT 0xe00ff004 -#define CYDEV_ROM_TABLE_FPB 0xe00ff008 -#define CYDEV_ROM_TABLE_ITM 0xe00ff00c -#define CYDEV_ROM_TABLE_TPIU 0xe00ff010 -#define CYDEV_ROM_TABLE_ETM 0xe00ff014 -#define CYDEV_ROM_TABLE_END 0xe00ff018 -#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc -#define CYDEV_ROM_TABLE_PID4 0xe00fffd0 -#define CYDEV_ROM_TABLE_PID5 0xe00fffd4 -#define CYDEV_ROM_TABLE_PID6 0xe00fffd8 -#define CYDEV_ROM_TABLE_PID7 0xe00fffdc -#define CYDEV_ROM_TABLE_PID0 0xe00fffe0 -#define CYDEV_ROM_TABLE_PID1 0xe00fffe4 -#define CYDEV_ROM_TABLE_PID2 0xe00fffe8 -#define CYDEV_ROM_TABLE_PID3 0xe00fffec -#define CYDEV_ROM_TABLE_CID0 0xe00ffff0 -#define CYDEV_ROM_TABLE_CID1 0xe00ffff4 -#define CYDEV_ROM_TABLE_CID2 0xe00ffff8 -#define CYDEV_ROM_TABLE_CID3 0xe00ffffc -#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE -#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE -#define CYDEV_FLS_SECTOR_SIZE 0x00010000 -#define CYDEV_FLS_ROW_SIZE 0x00000100 -#define CYDEV_ECC_SECTOR_SIZE 0x00002000 -#define CYDEV_ECC_ROW_SIZE 0x00000020 -#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 -#define CYDEV_EEPROM_ROW_SIZE 0x00000010 -#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE -#define CYCLK_LD_DISABLE 0x00000004 -#define CYCLK_LD_SYNC_EN 0x00000002 -#define CYCLK_LD_LOAD 0x00000001 -#define CYCLK_PIPE 0x00000080 -#define CYCLK_SSS 0x00000040 -#define CYCLK_EARLY 0x00000020 -#define CYCLK_DUTY 0x00000010 -#define CYCLK_SYNC 0x00000008 -#define CYCLK_SRC_SEL_CLK_SYNC_D 0 -#define CYCLK_SRC_SEL_SYNC_DIG 0 -#define CYCLK_SRC_SEL_IMO 1 -#define CYCLK_SRC_SEL_XTAL_MHZ 2 -#define CYCLK_SRC_SEL_XTALM 2 -#define CYCLK_SRC_SEL_ILO 3 -#define CYCLK_SRC_SEL_PLL 4 -#define CYCLK_SRC_SEL_XTAL_KHZ 5 -#define CYCLK_SRC_SEL_XTALK 5 -#define CYCLK_SRC_SEL_DSI_G 6 -#define CYCLK_SRC_SEL_DSI_D 7 -#define CYCLK_SRC_SEL_CLK_SYNC_A 0 -#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc deleted file mode 100755 index ebd1b1d..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydeviceiar_trm.inc +++ /dev/null @@ -1,5356 +0,0 @@ -; -; FILENAME: cydeviceiar_trm.inc -; -; PSoC Creator 3.0 Component Pack 7 -; -; DESCRIPTION: -; This file provides all of the address values for the entire PSoC device. -; -;------------------------------------------------------------------------------- -; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying -; the software package with which this file was provided. -;------------------------------------------------------------------------------- - -#define CYDEV_FLASH_BASE 0x00000000 -#define CYDEV_FLASH_SIZE 0x00020000 -#define CYREG_FLASH_DATA_MBASE 0x00000000 -#define CYREG_FLASH_DATA_MSIZE 0x00020000 -#define CYDEV_SRAM_BASE 0x1fffc000 -#define CYDEV_SRAM_SIZE 0x00008000 -#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000 -#define CYREG_SRAM_CODE64K_MSIZE 0x00004000 -#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000 -#define CYREG_SRAM_CODE32K_MSIZE 0x00002000 -#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000 -#define CYREG_SRAM_CODE16K_MSIZE 0x00001000 -#define CYREG_SRAM_CODE_MBASE 0x1fffc000 -#define CYREG_SRAM_CODE_MSIZE 0x00004000 -#define CYREG_SRAM_DATA_MBASE 0x20000000 -#define CYREG_SRAM_DATA_MSIZE 0x00004000 -#define CYREG_SRAM_DATA16K_MBASE 0x20001000 -#define CYREG_SRAM_DATA16K_MSIZE 0x00001000 -#define CYREG_SRAM_DATA32K_MBASE 0x20002000 -#define CYREG_SRAM_DATA32K_MSIZE 0x00002000 -#define CYREG_SRAM_DATA64K_MBASE 0x20004000 -#define CYREG_SRAM_DATA64K_MSIZE 0x00004000 -#define CYDEV_DMA_BASE 0x20008000 -#define CYDEV_DMA_SIZE 0x00008000 -#define CYREG_DMA_SRAM64K_MBASE 0x20008000 -#define CYREG_DMA_SRAM64K_MSIZE 0x00004000 -#define CYREG_DMA_SRAM32K_MBASE 0x2000c000 -#define CYREG_DMA_SRAM32K_MSIZE 0x00002000 -#define CYREG_DMA_SRAM16K_MBASE 0x2000e000 -#define CYREG_DMA_SRAM16K_MSIZE 0x00001000 -#define CYREG_DMA_SRAM_MBASE 0x2000f000 -#define CYREG_DMA_SRAM_MSIZE 0x00001000 -#define CYDEV_CLKDIST_BASE 0x40004000 -#define CYDEV_CLKDIST_SIZE 0x00000110 -#define CYREG_CLKDIST_CR 0x40004000 -#define CYREG_CLKDIST_LD 0x40004001 -#define CYREG_CLKDIST_WRK0 0x40004002 -#define CYREG_CLKDIST_WRK1 0x40004003 -#define CYREG_CLKDIST_MSTR0 0x40004004 -#define CYREG_CLKDIST_MSTR1 0x40004005 -#define CYREG_CLKDIST_BCFG0 0x40004006 -#define CYREG_CLKDIST_BCFG1 0x40004007 -#define CYREG_CLKDIST_BCFG2 0x40004008 -#define CYREG_CLKDIST_UCFG 0x40004009 -#define CYREG_CLKDIST_DLY0 0x4000400a -#define CYREG_CLKDIST_DLY1 0x4000400b -#define CYREG_CLKDIST_DMASK 0x40004010 -#define CYREG_CLKDIST_AMASK 0x40004014 -#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 -#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080 -#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081 -#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082 -#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 -#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084 -#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085 -#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086 -#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 -#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088 -#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089 -#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408a -#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c -#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408c -#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408d -#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408e -#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 -#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090 -#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091 -#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092 -#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 -#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094 -#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095 -#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096 -#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 -#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098 -#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099 -#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409a -#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c -#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 -#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409c -#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409d -#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409e -#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 -#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 -#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100 -#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101 -#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102 -#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103 -#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 -#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 -#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104 -#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105 -#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106 -#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107 -#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 -#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 -#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108 -#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109 -#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410a -#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410b -#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c -#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 -#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410c -#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410d -#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410e -#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410f -#define CYDEV_FASTCLK_BASE 0x40004200 -#define CYDEV_FASTCLK_SIZE 0x00000026 -#define CYDEV_FASTCLK_IMO_BASE 0x40004200 -#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 -#define CYREG_FASTCLK_IMO_CR 0x40004200 -#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 -#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 -#define CYREG_FASTCLK_XMHZ_CSR 0x40004210 -#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212 -#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213 -#define CYDEV_FASTCLK_PLL_BASE 0x40004220 -#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 -#define CYREG_FASTCLK_PLL_CFG0 0x40004220 -#define CYREG_FASTCLK_PLL_CFG1 0x40004221 -#define CYREG_FASTCLK_PLL_P 0x40004222 -#define CYREG_FASTCLK_PLL_Q 0x40004223 -#define CYREG_FASTCLK_PLL_SR 0x40004225 -#define CYDEV_SLOWCLK_BASE 0x40004300 -#define CYDEV_SLOWCLK_SIZE 0x0000000b -#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 -#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 -#define CYREG_SLOWCLK_ILO_CR0 0x40004300 -#define CYREG_SLOWCLK_ILO_CR1 0x40004301 -#define CYDEV_SLOWCLK_X32_BASE 0x40004308 -#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 -#define CYREG_SLOWCLK_X32_CR 0x40004308 -#define CYREG_SLOWCLK_X32_CFG 0x40004309 -#define CYREG_SLOWCLK_X32_TST 0x4000430a -#define CYDEV_BOOST_BASE 0x40004320 -#define CYDEV_BOOST_SIZE 0x00000007 -#define CYREG_BOOST_CR0 0x40004320 -#define CYREG_BOOST_CR1 0x40004321 -#define CYREG_BOOST_CR2 0x40004322 -#define CYREG_BOOST_CR3 0x40004323 -#define CYREG_BOOST_SR 0x40004324 -#define CYREG_BOOST_CR4 0x40004325 -#define CYREG_BOOST_SR2 0x40004326 -#define CYDEV_PWRSYS_BASE 0x40004330 -#define CYDEV_PWRSYS_SIZE 0x00000002 -#define CYREG_PWRSYS_CR0 0x40004330 -#define CYREG_PWRSYS_CR1 0x40004331 -#define CYDEV_PM_BASE 0x40004380 -#define CYDEV_PM_SIZE 0x00000057 -#define CYREG_PM_TW_CFG0 0x40004380 -#define CYREG_PM_TW_CFG1 0x40004381 -#define CYREG_PM_TW_CFG2 0x40004382 -#define CYREG_PM_WDT_CFG 0x40004383 -#define CYREG_PM_WDT_CR 0x40004384 -#define CYREG_PM_INT_SR 0x40004390 -#define CYREG_PM_MODE_CFG0 0x40004391 -#define CYREG_PM_MODE_CFG1 0x40004392 -#define CYREG_PM_MODE_CSR 0x40004393 -#define CYREG_PM_USB_CR0 0x40004394 -#define CYREG_PM_WAKEUP_CFG0 0x40004398 -#define CYREG_PM_WAKEUP_CFG1 0x40004399 -#define CYREG_PM_WAKEUP_CFG2 0x4000439a -#define CYDEV_PM_ACT_BASE 0x400043a0 -#define CYDEV_PM_ACT_SIZE 0x0000000e -#define CYREG_PM_ACT_CFG0 0x400043a0 -#define CYREG_PM_ACT_CFG1 0x400043a1 -#define CYREG_PM_ACT_CFG2 0x400043a2 -#define CYREG_PM_ACT_CFG3 0x400043a3 -#define CYREG_PM_ACT_CFG4 0x400043a4 -#define CYREG_PM_ACT_CFG5 0x400043a5 -#define CYREG_PM_ACT_CFG6 0x400043a6 -#define CYREG_PM_ACT_CFG7 0x400043a7 -#define CYREG_PM_ACT_CFG8 0x400043a8 -#define CYREG_PM_ACT_CFG9 0x400043a9 -#define CYREG_PM_ACT_CFG10 0x400043aa -#define CYREG_PM_ACT_CFG11 0x400043ab -#define CYREG_PM_ACT_CFG12 0x400043ac -#define CYREG_PM_ACT_CFG13 0x400043ad -#define CYDEV_PM_STBY_BASE 0x400043b0 -#define CYDEV_PM_STBY_SIZE 0x0000000e -#define CYREG_PM_STBY_CFG0 0x400043b0 -#define CYREG_PM_STBY_CFG1 0x400043b1 -#define CYREG_PM_STBY_CFG2 0x400043b2 -#define CYREG_PM_STBY_CFG3 0x400043b3 -#define CYREG_PM_STBY_CFG4 0x400043b4 -#define CYREG_PM_STBY_CFG5 0x400043b5 -#define CYREG_PM_STBY_CFG6 0x400043b6 -#define CYREG_PM_STBY_CFG7 0x400043b7 -#define CYREG_PM_STBY_CFG8 0x400043b8 -#define CYREG_PM_STBY_CFG9 0x400043b9 -#define CYREG_PM_STBY_CFG10 0x400043ba -#define CYREG_PM_STBY_CFG11 0x400043bb -#define CYREG_PM_STBY_CFG12 0x400043bc -#define CYREG_PM_STBY_CFG13 0x400043bd -#define CYDEV_PM_AVAIL_BASE 0x400043c0 -#define CYDEV_PM_AVAIL_SIZE 0x00000017 -#define CYREG_PM_AVAIL_CR0 0x400043c0 -#define CYREG_PM_AVAIL_CR1 0x400043c1 -#define CYREG_PM_AVAIL_CR2 0x400043c2 -#define CYREG_PM_AVAIL_CR3 0x400043c3 -#define CYREG_PM_AVAIL_CR4 0x400043c4 -#define CYREG_PM_AVAIL_CR5 0x400043c5 -#define CYREG_PM_AVAIL_CR6 0x400043c6 -#define CYREG_PM_AVAIL_SR0 0x400043d0 -#define CYREG_PM_AVAIL_SR1 0x400043d1 -#define CYREG_PM_AVAIL_SR2 0x400043d2 -#define CYREG_PM_AVAIL_SR3 0x400043d3 -#define CYREG_PM_AVAIL_SR4 0x400043d4 -#define CYREG_PM_AVAIL_SR5 0x400043d5 -#define CYREG_PM_AVAIL_SR6 0x400043d6 -#define CYDEV_PICU_BASE 0x40004500 -#define CYDEV_PICU_SIZE 0x000000b0 -#define CYDEV_PICU_INTTYPE_BASE 0x40004500 -#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 -#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 -#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 -#define CYREG_PICU0_INTTYPE0 0x40004500 -#define CYREG_PICU0_INTTYPE1 0x40004501 -#define CYREG_PICU0_INTTYPE2 0x40004502 -#define CYREG_PICU0_INTTYPE3 0x40004503 -#define CYREG_PICU0_INTTYPE4 0x40004504 -#define CYREG_PICU0_INTTYPE5 0x40004505 -#define CYREG_PICU0_INTTYPE6 0x40004506 -#define CYREG_PICU0_INTTYPE7 0x40004507 -#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 -#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 -#define CYREG_PICU1_INTTYPE0 0x40004508 -#define CYREG_PICU1_INTTYPE1 0x40004509 -#define CYREG_PICU1_INTTYPE2 0x4000450a -#define CYREG_PICU1_INTTYPE3 0x4000450b -#define CYREG_PICU1_INTTYPE4 0x4000450c -#define CYREG_PICU1_INTTYPE5 0x4000450d -#define CYREG_PICU1_INTTYPE6 0x4000450e -#define CYREG_PICU1_INTTYPE7 0x4000450f -#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 -#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 -#define CYREG_PICU2_INTTYPE0 0x40004510 -#define CYREG_PICU2_INTTYPE1 0x40004511 -#define CYREG_PICU2_INTTYPE2 0x40004512 -#define CYREG_PICU2_INTTYPE3 0x40004513 -#define CYREG_PICU2_INTTYPE4 0x40004514 -#define CYREG_PICU2_INTTYPE5 0x40004515 -#define CYREG_PICU2_INTTYPE6 0x40004516 -#define CYREG_PICU2_INTTYPE7 0x40004517 -#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 -#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 -#define CYREG_PICU3_INTTYPE0 0x40004518 -#define CYREG_PICU3_INTTYPE1 0x40004519 -#define CYREG_PICU3_INTTYPE2 0x4000451a -#define CYREG_PICU3_INTTYPE3 0x4000451b -#define CYREG_PICU3_INTTYPE4 0x4000451c -#define CYREG_PICU3_INTTYPE5 0x4000451d -#define CYREG_PICU3_INTTYPE6 0x4000451e -#define CYREG_PICU3_INTTYPE7 0x4000451f -#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 -#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 -#define CYREG_PICU4_INTTYPE0 0x40004520 -#define CYREG_PICU4_INTTYPE1 0x40004521 -#define CYREG_PICU4_INTTYPE2 0x40004522 -#define CYREG_PICU4_INTTYPE3 0x40004523 -#define CYREG_PICU4_INTTYPE4 0x40004524 -#define CYREG_PICU4_INTTYPE5 0x40004525 -#define CYREG_PICU4_INTTYPE6 0x40004526 -#define CYREG_PICU4_INTTYPE7 0x40004527 -#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 -#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 -#define CYREG_PICU5_INTTYPE0 0x40004528 -#define CYREG_PICU5_INTTYPE1 0x40004529 -#define CYREG_PICU5_INTTYPE2 0x4000452a -#define CYREG_PICU5_INTTYPE3 0x4000452b -#define CYREG_PICU5_INTTYPE4 0x4000452c -#define CYREG_PICU5_INTTYPE5 0x4000452d -#define CYREG_PICU5_INTTYPE6 0x4000452e -#define CYREG_PICU5_INTTYPE7 0x4000452f -#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 -#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 -#define CYREG_PICU6_INTTYPE0 0x40004530 -#define CYREG_PICU6_INTTYPE1 0x40004531 -#define CYREG_PICU6_INTTYPE2 0x40004532 -#define CYREG_PICU6_INTTYPE3 0x40004533 -#define CYREG_PICU6_INTTYPE4 0x40004534 -#define CYREG_PICU6_INTTYPE5 0x40004535 -#define CYREG_PICU6_INTTYPE6 0x40004536 -#define CYREG_PICU6_INTTYPE7 0x40004537 -#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 -#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 -#define CYREG_PICU12_INTTYPE0 0x40004560 -#define CYREG_PICU12_INTTYPE1 0x40004561 -#define CYREG_PICU12_INTTYPE2 0x40004562 -#define CYREG_PICU12_INTTYPE3 0x40004563 -#define CYREG_PICU12_INTTYPE4 0x40004564 -#define CYREG_PICU12_INTTYPE5 0x40004565 -#define CYREG_PICU12_INTTYPE6 0x40004566 -#define CYREG_PICU12_INTTYPE7 0x40004567 -#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 -#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 -#define CYREG_PICU15_INTTYPE0 0x40004578 -#define CYREG_PICU15_INTTYPE1 0x40004579 -#define CYREG_PICU15_INTTYPE2 0x4000457a -#define CYREG_PICU15_INTTYPE3 0x4000457b -#define CYREG_PICU15_INTTYPE4 0x4000457c -#define CYREG_PICU15_INTTYPE5 0x4000457d -#define CYREG_PICU15_INTTYPE6 0x4000457e -#define CYREG_PICU15_INTTYPE7 0x4000457f -#define CYDEV_PICU_STAT_BASE 0x40004580 -#define CYDEV_PICU_STAT_SIZE 0x00000010 -#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 -#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 -#define CYREG_PICU0_INTSTAT 0x40004580 -#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 -#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 -#define CYREG_PICU1_INTSTAT 0x40004581 -#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 -#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 -#define CYREG_PICU2_INTSTAT 0x40004582 -#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 -#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 -#define CYREG_PICU3_INTSTAT 0x40004583 -#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 -#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 -#define CYREG_PICU4_INTSTAT 0x40004584 -#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 -#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 -#define CYREG_PICU5_INTSTAT 0x40004585 -#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 -#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 -#define CYREG_PICU6_INTSTAT 0x40004586 -#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c -#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 -#define CYREG_PICU12_INTSTAT 0x4000458c -#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f -#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 -#define CYREG_PICU15_INTSTAT 0x4000458f -#define CYDEV_PICU_SNAP_BASE 0x40004590 -#define CYDEV_PICU_SNAP_SIZE 0x00000010 -#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 -#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 -#define CYREG_PICU0_SNAP 0x40004590 -#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 -#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 -#define CYREG_PICU1_SNAP 0x40004591 -#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 -#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 -#define CYREG_PICU2_SNAP 0x40004592 -#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 -#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 -#define CYREG_PICU3_SNAP 0x40004593 -#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 -#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 -#define CYREG_PICU4_SNAP 0x40004594 -#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 -#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 -#define CYREG_PICU5_SNAP 0x40004595 -#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 -#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 -#define CYREG_PICU6_SNAP 0x40004596 -#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c -#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 -#define CYREG_PICU12_SNAP 0x4000459c -#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f -#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 -#define CYREG_PICU_15_SNAP_15 0x4000459f -#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 -#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 -#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 -#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 -#define CYREG_PICU0_DISABLE_COR 0x400045a0 -#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 -#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 -#define CYREG_PICU1_DISABLE_COR 0x400045a1 -#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 -#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 -#define CYREG_PICU2_DISABLE_COR 0x400045a2 -#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 -#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 -#define CYREG_PICU3_DISABLE_COR 0x400045a3 -#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 -#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 -#define CYREG_PICU4_DISABLE_COR 0x400045a4 -#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 -#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 -#define CYREG_PICU5_DISABLE_COR 0x400045a5 -#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 -#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 -#define CYREG_PICU6_DISABLE_COR 0x400045a6 -#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac -#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 -#define CYREG_PICU12_DISABLE_COR 0x400045ac -#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af -#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 -#define CYREG_PICU15_DISABLE_COR 0x400045af -#define CYDEV_MFGCFG_BASE 0x40004600 -#define CYDEV_MFGCFG_SIZE 0x000000ed -#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 -#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 -#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 -#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 -#define CYREG_DAC0_TR 0x40004608 -#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 -#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 -#define CYREG_DAC1_TR 0x40004609 -#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a -#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 -#define CYREG_DAC2_TR 0x4000460a -#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b -#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 -#define CYREG_DAC3_TR 0x4000460b -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 -#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 -#define CYREG_NPUMP_DSM_TR0 0x40004610 -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 -#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 -#define CYREG_NPUMP_SC_TR0 0x40004611 -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 -#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 -#define CYREG_NPUMP_OPAMP_TR0 0x40004612 -#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 -#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 -#define CYREG_SAR0_TR0 0x40004614 -#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 -#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 -#define CYREG_SAR1_TR0 0x40004616 -#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 -#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 -#define CYREG_OPAMP0_TR0 0x40004620 -#define CYREG_OPAMP0_TR1 0x40004621 -#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 -#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 -#define CYREG_OPAMP1_TR0 0x40004622 -#define CYREG_OPAMP1_TR1 0x40004623 -#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 -#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 -#define CYREG_OPAMP2_TR0 0x40004624 -#define CYREG_OPAMP2_TR1 0x40004625 -#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 -#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 -#define CYREG_OPAMP3_TR0 0x40004626 -#define CYREG_OPAMP3_TR1 0x40004627 -#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 -#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 -#define CYREG_CMP0_TR0 0x40004630 -#define CYREG_CMP0_TR1 0x40004631 -#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 -#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 -#define CYREG_CMP1_TR0 0x40004632 -#define CYREG_CMP1_TR1 0x40004633 -#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 -#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 -#define CYREG_CMP2_TR0 0x40004634 -#define CYREG_CMP2_TR1 0x40004635 -#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 -#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 -#define CYREG_CMP3_TR0 0x40004636 -#define CYREG_CMP3_TR1 0x40004637 -#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 -#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b -#define CYREG_PWRSYS_HIB_TR0 0x40004680 -#define CYREG_PWRSYS_HIB_TR1 0x40004681 -#define CYREG_PWRSYS_I2C_TR 0x40004682 -#define CYREG_PWRSYS_SLP_TR 0x40004683 -#define CYREG_PWRSYS_BUZZ_TR 0x40004684 -#define CYREG_PWRSYS_WAKE_TR0 0x40004685 -#define CYREG_PWRSYS_WAKE_TR1 0x40004686 -#define CYREG_PWRSYS_BREF_TR 0x40004687 -#define CYREG_PWRSYS_BG_TR 0x40004688 -#define CYREG_PWRSYS_WAKE_TR2 0x40004689 -#define CYREG_PWRSYS_WAKE_TR3 0x4000468a -#define CYDEV_MFGCFG_ILO_BASE 0x40004690 -#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 -#define CYREG_ILO_TR0 0x40004690 -#define CYREG_ILO_TR1 0x40004691 -#define CYDEV_MFGCFG_X32_BASE 0x40004698 -#define CYDEV_MFGCFG_X32_SIZE 0x00000001 -#define CYREG_X32_TR 0x40004698 -#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 -#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 -#define CYREG_IMO_TR0 0x400046a0 -#define CYREG_IMO_TR1 0x400046a1 -#define CYREG_IMO_GAIN 0x400046a2 -#define CYREG_IMO_C36M 0x400046a3 -#define CYREG_IMO_TR2 0x400046a4 -#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 -#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 -#define CYREG_XMHZ_TR 0x400046a8 -#define CYREG_MFGCFG_DLY 0x400046c0 -#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 -#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d -#define CYREG_MLOGIC_DMPSTR 0x400046e2 -#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 -#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 -#define CYREG_MLOGIC_SEG_CR 0x400046e4 -#define CYREG_MLOGIC_SEG_CFG0 0x400046e5 -#define CYREG_MLOGIC_DEBUG 0x400046e8 -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea -#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 -#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea -#define CYREG_MLOGIC_REV_ID 0x400046ec -#define CYDEV_RESET_BASE 0x400046f0 -#define CYDEV_RESET_SIZE 0x0000000f -#define CYREG_RESET_IPOR_CR0 0x400046f0 -#define CYREG_RESET_IPOR_CR1 0x400046f1 -#define CYREG_RESET_IPOR_CR2 0x400046f2 -#define CYREG_RESET_IPOR_CR3 0x400046f3 -#define CYREG_RESET_CR0 0x400046f4 -#define CYREG_RESET_CR1 0x400046f5 -#define CYREG_RESET_CR2 0x400046f6 -#define CYREG_RESET_CR3 0x400046f7 -#define CYREG_RESET_CR4 0x400046f8 -#define CYREG_RESET_CR5 0x400046f9 -#define CYREG_RESET_SR0 0x400046fa -#define CYREG_RESET_SR1 0x400046fb -#define CYREG_RESET_SR2 0x400046fc -#define CYREG_RESET_SR3 0x400046fd -#define CYREG_RESET_TR 0x400046fe -#define CYDEV_SPC_BASE 0x40004700 -#define CYDEV_SPC_SIZE 0x00000100 -#define CYREG_SPC_FM_EE_CR 0x40004700 -#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701 -#define CYREG_SPC_EE_SCR 0x40004702 -#define CYREG_SPC_EE_ERR 0x40004703 -#define CYREG_SPC_CPU_DATA 0x40004720 -#define CYREG_SPC_DMA_DATA 0x40004721 -#define CYREG_SPC_SR 0x40004722 -#define CYREG_SPC_CR 0x40004723 -#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 -#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 -#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780 -#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 -#define CYDEV_CACHE_BASE 0x40004800 -#define CYDEV_CACHE_SIZE 0x0000009c -#define CYREG_CACHE_CC_CTL 0x40004800 -#define CYREG_CACHE_ECC_CORR 0x40004880 -#define CYREG_CACHE_ECC_ERR 0x40004888 -#define CYREG_CACHE_FLASH_ERR 0x40004890 -#define CYREG_CACHE_HITMISS 0x40004898 -#define CYDEV_I2C_BASE 0x40004900 -#define CYDEV_I2C_SIZE 0x000000e1 -#define CYREG_I2C_XCFG 0x400049c8 -#define CYREG_I2C_ADR 0x400049ca -#define CYREG_I2C_CFG 0x400049d6 -#define CYREG_I2C_CSR 0x400049d7 -#define CYREG_I2C_D 0x400049d8 -#define CYREG_I2C_MCSR 0x400049d9 -#define CYREG_I2C_CLK_DIV1 0x400049db -#define CYREG_I2C_CLK_DIV2 0x400049dc -#define CYREG_I2C_TMOUT_CSR 0x400049dd -#define CYREG_I2C_TMOUT_SR 0x400049de -#define CYREG_I2C_TMOUT_CFG0 0x400049df -#define CYREG_I2C_TMOUT_CFG1 0x400049e0 -#define CYDEV_DEC_BASE 0x40004e00 -#define CYDEV_DEC_SIZE 0x00000015 -#define CYREG_DEC_CR 0x40004e00 -#define CYREG_DEC_SR 0x40004e01 -#define CYREG_DEC_SHIFT1 0x40004e02 -#define CYREG_DEC_SHIFT2 0x40004e03 -#define CYREG_DEC_DR2 0x40004e04 -#define CYREG_DEC_DR2H 0x40004e05 -#define CYREG_DEC_DR1 0x40004e06 -#define CYREG_DEC_OCOR 0x40004e08 -#define CYREG_DEC_OCORM 0x40004e09 -#define CYREG_DEC_OCORH 0x40004e0a -#define CYREG_DEC_GCOR 0x40004e0c -#define CYREG_DEC_GCORH 0x40004e0d -#define CYREG_DEC_GVAL 0x40004e0e -#define CYREG_DEC_OUTSAMP 0x40004e10 -#define CYREG_DEC_OUTSAMPM 0x40004e11 -#define CYREG_DEC_OUTSAMPH 0x40004e12 -#define CYREG_DEC_OUTSAMPS 0x40004e13 -#define CYREG_DEC_COHER 0x40004e14 -#define CYDEV_TMR0_BASE 0x40004f00 -#define CYDEV_TMR0_SIZE 0x0000000c -#define CYREG_TMR0_CFG0 0x40004f00 -#define CYREG_TMR0_CFG1 0x40004f01 -#define CYREG_TMR0_CFG2 0x40004f02 -#define CYREG_TMR0_SR0 0x40004f03 -#define CYREG_TMR0_PER0 0x40004f04 -#define CYREG_TMR0_PER1 0x40004f05 -#define CYREG_TMR0_CNT_CMP0 0x40004f06 -#define CYREG_TMR0_CNT_CMP1 0x40004f07 -#define CYREG_TMR0_CAP0 0x40004f08 -#define CYREG_TMR0_CAP1 0x40004f09 -#define CYREG_TMR0_RT0 0x40004f0a -#define CYREG_TMR0_RT1 0x40004f0b -#define CYDEV_TMR1_BASE 0x40004f0c -#define CYDEV_TMR1_SIZE 0x0000000c -#define CYREG_TMR1_CFG0 0x40004f0c -#define CYREG_TMR1_CFG1 0x40004f0d -#define CYREG_TMR1_CFG2 0x40004f0e -#define CYREG_TMR1_SR0 0x40004f0f -#define CYREG_TMR1_PER0 0x40004f10 -#define CYREG_TMR1_PER1 0x40004f11 -#define CYREG_TMR1_CNT_CMP0 0x40004f12 -#define CYREG_TMR1_CNT_CMP1 0x40004f13 -#define CYREG_TMR1_CAP0 0x40004f14 -#define CYREG_TMR1_CAP1 0x40004f15 -#define CYREG_TMR1_RT0 0x40004f16 -#define CYREG_TMR1_RT1 0x40004f17 -#define CYDEV_TMR2_BASE 0x40004f18 -#define CYDEV_TMR2_SIZE 0x0000000c -#define CYREG_TMR2_CFG0 0x40004f18 -#define CYREG_TMR2_CFG1 0x40004f19 -#define CYREG_TMR2_CFG2 0x40004f1a -#define CYREG_TMR2_SR0 0x40004f1b -#define CYREG_TMR2_PER0 0x40004f1c -#define CYREG_TMR2_PER1 0x40004f1d -#define CYREG_TMR2_CNT_CMP0 0x40004f1e -#define CYREG_TMR2_CNT_CMP1 0x40004f1f -#define CYREG_TMR2_CAP0 0x40004f20 -#define CYREG_TMR2_CAP1 0x40004f21 -#define CYREG_TMR2_RT0 0x40004f22 -#define CYREG_TMR2_RT1 0x40004f23 -#define CYDEV_TMR3_BASE 0x40004f24 -#define CYDEV_TMR3_SIZE 0x0000000c -#define CYREG_TMR3_CFG0 0x40004f24 -#define CYREG_TMR3_CFG1 0x40004f25 -#define CYREG_TMR3_CFG2 0x40004f26 -#define CYREG_TMR3_SR0 0x40004f27 -#define CYREG_TMR3_PER0 0x40004f28 -#define CYREG_TMR3_PER1 0x40004f29 -#define CYREG_TMR3_CNT_CMP0 0x40004f2a -#define CYREG_TMR3_CNT_CMP1 0x40004f2b -#define CYREG_TMR3_CAP0 0x40004f2c -#define CYREG_TMR3_CAP1 0x40004f2d -#define CYREG_TMR3_RT0 0x40004f2e -#define CYREG_TMR3_RT1 0x40004f2f -#define CYDEV_IO_BASE 0x40005000 -#define CYDEV_IO_SIZE 0x00000200 -#define CYDEV_IO_PC_BASE 0x40005000 -#define CYDEV_IO_PC_SIZE 0x00000080 -#define CYDEV_IO_PC_PRT0_BASE 0x40005000 -#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 -#define CYREG_PRT0_PC0 0x40005000 -#define CYREG_PRT0_PC1 0x40005001 -#define CYREG_PRT0_PC2 0x40005002 -#define CYREG_PRT0_PC3 0x40005003 -#define CYREG_PRT0_PC4 0x40005004 -#define CYREG_PRT0_PC5 0x40005005 -#define CYREG_PRT0_PC6 0x40005006 -#define CYREG_PRT0_PC7 0x40005007 -#define CYDEV_IO_PC_PRT1_BASE 0x40005008 -#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 -#define CYREG_PRT1_PC0 0x40005008 -#define CYREG_PRT1_PC1 0x40005009 -#define CYREG_PRT1_PC2 0x4000500a -#define CYREG_PRT1_PC3 0x4000500b -#define CYREG_PRT1_PC4 0x4000500c -#define CYREG_PRT1_PC5 0x4000500d -#define CYREG_PRT1_PC6 0x4000500e -#define CYREG_PRT1_PC7 0x4000500f -#define CYDEV_IO_PC_PRT2_BASE 0x40005010 -#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 -#define CYREG_PRT2_PC0 0x40005010 -#define CYREG_PRT2_PC1 0x40005011 -#define CYREG_PRT2_PC2 0x40005012 -#define CYREG_PRT2_PC3 0x40005013 -#define CYREG_PRT2_PC4 0x40005014 -#define CYREG_PRT2_PC5 0x40005015 -#define CYREG_PRT2_PC6 0x40005016 -#define CYREG_PRT2_PC7 0x40005017 -#define CYDEV_IO_PC_PRT3_BASE 0x40005018 -#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 -#define CYREG_PRT3_PC0 0x40005018 -#define CYREG_PRT3_PC1 0x40005019 -#define CYREG_PRT3_PC2 0x4000501a -#define CYREG_PRT3_PC3 0x4000501b -#define CYREG_PRT3_PC4 0x4000501c -#define CYREG_PRT3_PC5 0x4000501d -#define CYREG_PRT3_PC6 0x4000501e -#define CYREG_PRT3_PC7 0x4000501f -#define CYDEV_IO_PC_PRT4_BASE 0x40005020 -#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 -#define CYREG_PRT4_PC0 0x40005020 -#define CYREG_PRT4_PC1 0x40005021 -#define CYREG_PRT4_PC2 0x40005022 -#define CYREG_PRT4_PC3 0x40005023 -#define CYREG_PRT4_PC4 0x40005024 -#define CYREG_PRT4_PC5 0x40005025 -#define CYREG_PRT4_PC6 0x40005026 -#define CYREG_PRT4_PC7 0x40005027 -#define CYDEV_IO_PC_PRT5_BASE 0x40005028 -#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 -#define CYREG_PRT5_PC0 0x40005028 -#define CYREG_PRT5_PC1 0x40005029 -#define CYREG_PRT5_PC2 0x4000502a -#define CYREG_PRT5_PC3 0x4000502b -#define CYREG_PRT5_PC4 0x4000502c -#define CYREG_PRT5_PC5 0x4000502d -#define CYREG_PRT5_PC6 0x4000502e -#define CYREG_PRT5_PC7 0x4000502f -#define CYDEV_IO_PC_PRT6_BASE 0x40005030 -#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 -#define CYREG_PRT6_PC0 0x40005030 -#define CYREG_PRT6_PC1 0x40005031 -#define CYREG_PRT6_PC2 0x40005032 -#define CYREG_PRT6_PC3 0x40005033 -#define CYREG_PRT6_PC4 0x40005034 -#define CYREG_PRT6_PC5 0x40005035 -#define CYREG_PRT6_PC6 0x40005036 -#define CYREG_PRT6_PC7 0x40005037 -#define CYDEV_IO_PC_PRT12_BASE 0x40005060 -#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 -#define CYREG_PRT12_PC0 0x40005060 -#define CYREG_PRT12_PC1 0x40005061 -#define CYREG_PRT12_PC2 0x40005062 -#define CYREG_PRT12_PC3 0x40005063 -#define CYREG_PRT12_PC4 0x40005064 -#define CYREG_PRT12_PC5 0x40005065 -#define CYREG_PRT12_PC6 0x40005066 -#define CYREG_PRT12_PC7 0x40005067 -#define CYDEV_IO_PC_PRT15_BASE 0x40005078 -#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 -#define CYREG_IO_PC_PRT15_PC0 0x40005078 -#define CYREG_IO_PC_PRT15_PC1 0x40005079 -#define CYREG_IO_PC_PRT15_PC2 0x4000507a -#define CYREG_IO_PC_PRT15_PC3 0x4000507b -#define CYREG_IO_PC_PRT15_PC4 0x4000507c -#define CYREG_IO_PC_PRT15_PC5 0x4000507d -#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e -#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 -#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507e -#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507f -#define CYDEV_IO_DR_BASE 0x40005080 -#define CYDEV_IO_DR_SIZE 0x00000010 -#define CYDEV_IO_DR_PRT0_BASE 0x40005080 -#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 -#define CYREG_PRT0_DR_ALIAS 0x40005080 -#define CYDEV_IO_DR_PRT1_BASE 0x40005081 -#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 -#define CYREG_PRT1_DR_ALIAS 0x40005081 -#define CYDEV_IO_DR_PRT2_BASE 0x40005082 -#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 -#define CYREG_PRT2_DR_ALIAS 0x40005082 -#define CYDEV_IO_DR_PRT3_BASE 0x40005083 -#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 -#define CYREG_PRT3_DR_ALIAS 0x40005083 -#define CYDEV_IO_DR_PRT4_BASE 0x40005084 -#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 -#define CYREG_PRT4_DR_ALIAS 0x40005084 -#define CYDEV_IO_DR_PRT5_BASE 0x40005085 -#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 -#define CYREG_PRT5_DR_ALIAS 0x40005085 -#define CYDEV_IO_DR_PRT6_BASE 0x40005086 -#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 -#define CYREG_PRT6_DR_ALIAS 0x40005086 -#define CYDEV_IO_DR_PRT12_BASE 0x4000508c -#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 -#define CYREG_PRT12_DR_ALIAS 0x4000508c -#define CYDEV_IO_DR_PRT15_BASE 0x4000508f -#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 -#define CYREG_PRT15_DR_15_ALIAS 0x4000508f -#define CYDEV_IO_PS_BASE 0x40005090 -#define CYDEV_IO_PS_SIZE 0x00000010 -#define CYDEV_IO_PS_PRT0_BASE 0x40005090 -#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 -#define CYREG_PRT0_PS_ALIAS 0x40005090 -#define CYDEV_IO_PS_PRT1_BASE 0x40005091 -#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 -#define CYREG_PRT1_PS_ALIAS 0x40005091 -#define CYDEV_IO_PS_PRT2_BASE 0x40005092 -#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 -#define CYREG_PRT2_PS_ALIAS 0x40005092 -#define CYDEV_IO_PS_PRT3_BASE 0x40005093 -#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 -#define CYREG_PRT3_PS_ALIAS 0x40005093 -#define CYDEV_IO_PS_PRT4_BASE 0x40005094 -#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 -#define CYREG_PRT4_PS_ALIAS 0x40005094 -#define CYDEV_IO_PS_PRT5_BASE 0x40005095 -#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 -#define CYREG_PRT5_PS_ALIAS 0x40005095 -#define CYDEV_IO_PS_PRT6_BASE 0x40005096 -#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 -#define CYREG_PRT6_PS_ALIAS 0x40005096 -#define CYDEV_IO_PS_PRT12_BASE 0x4000509c -#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 -#define CYREG_PRT12_PS_ALIAS 0x4000509c -#define CYDEV_IO_PS_PRT15_BASE 0x4000509f -#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 -#define CYREG_PRT15_PS15_ALIAS 0x4000509f -#define CYDEV_IO_PRT_BASE 0x40005100 -#define CYDEV_IO_PRT_SIZE 0x00000100 -#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 -#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 -#define CYREG_PRT0_DR 0x40005100 -#define CYREG_PRT0_PS 0x40005101 -#define CYREG_PRT0_DM0 0x40005102 -#define CYREG_PRT0_DM1 0x40005103 -#define CYREG_PRT0_DM2 0x40005104 -#define CYREG_PRT0_SLW 0x40005105 -#define CYREG_PRT0_BYP 0x40005106 -#define CYREG_PRT0_BIE 0x40005107 -#define CYREG_PRT0_INP_DIS 0x40005108 -#define CYREG_PRT0_CTL 0x40005109 -#define CYREG_PRT0_PRT 0x4000510a -#define CYREG_PRT0_BIT_MASK 0x4000510b -#define CYREG_PRT0_AMUX 0x4000510c -#define CYREG_PRT0_AG 0x4000510d -#define CYREG_PRT0_LCD_COM_SEG 0x4000510e -#define CYREG_PRT0_LCD_EN 0x4000510f -#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 -#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 -#define CYREG_PRT1_DR 0x40005110 -#define CYREG_PRT1_PS 0x40005111 -#define CYREG_PRT1_DM0 0x40005112 -#define CYREG_PRT1_DM1 0x40005113 -#define CYREG_PRT1_DM2 0x40005114 -#define CYREG_PRT1_SLW 0x40005115 -#define CYREG_PRT1_BYP 0x40005116 -#define CYREG_PRT1_BIE 0x40005117 -#define CYREG_PRT1_INP_DIS 0x40005118 -#define CYREG_PRT1_CTL 0x40005119 -#define CYREG_PRT1_PRT 0x4000511a -#define CYREG_PRT1_BIT_MASK 0x4000511b -#define CYREG_PRT1_AMUX 0x4000511c -#define CYREG_PRT1_AG 0x4000511d -#define CYREG_PRT1_LCD_COM_SEG 0x4000511e -#define CYREG_PRT1_LCD_EN 0x4000511f -#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 -#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 -#define CYREG_PRT2_DR 0x40005120 -#define CYREG_PRT2_PS 0x40005121 -#define CYREG_PRT2_DM0 0x40005122 -#define CYREG_PRT2_DM1 0x40005123 -#define CYREG_PRT2_DM2 0x40005124 -#define CYREG_PRT2_SLW 0x40005125 -#define CYREG_PRT2_BYP 0x40005126 -#define CYREG_PRT2_BIE 0x40005127 -#define CYREG_PRT2_INP_DIS 0x40005128 -#define CYREG_PRT2_CTL 0x40005129 -#define CYREG_PRT2_PRT 0x4000512a -#define CYREG_PRT2_BIT_MASK 0x4000512b -#define CYREG_PRT2_AMUX 0x4000512c -#define CYREG_PRT2_AG 0x4000512d -#define CYREG_PRT2_LCD_COM_SEG 0x4000512e -#define CYREG_PRT2_LCD_EN 0x4000512f -#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 -#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 -#define CYREG_PRT3_DR 0x40005130 -#define CYREG_PRT3_PS 0x40005131 -#define CYREG_PRT3_DM0 0x40005132 -#define CYREG_PRT3_DM1 0x40005133 -#define CYREG_PRT3_DM2 0x40005134 -#define CYREG_PRT3_SLW 0x40005135 -#define CYREG_PRT3_BYP 0x40005136 -#define CYREG_PRT3_BIE 0x40005137 -#define CYREG_PRT3_INP_DIS 0x40005138 -#define CYREG_PRT3_CTL 0x40005139 -#define CYREG_PRT3_PRT 0x4000513a -#define CYREG_PRT3_BIT_MASK 0x4000513b -#define CYREG_PRT3_AMUX 0x4000513c -#define CYREG_PRT3_AG 0x4000513d -#define CYREG_PRT3_LCD_COM_SEG 0x4000513e -#define CYREG_PRT3_LCD_EN 0x4000513f -#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 -#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 -#define CYREG_PRT4_DR 0x40005140 -#define CYREG_PRT4_PS 0x40005141 -#define CYREG_PRT4_DM0 0x40005142 -#define CYREG_PRT4_DM1 0x40005143 -#define CYREG_PRT4_DM2 0x40005144 -#define CYREG_PRT4_SLW 0x40005145 -#define CYREG_PRT4_BYP 0x40005146 -#define CYREG_PRT4_BIE 0x40005147 -#define CYREG_PRT4_INP_DIS 0x40005148 -#define CYREG_PRT4_CTL 0x40005149 -#define CYREG_PRT4_PRT 0x4000514a -#define CYREG_PRT4_BIT_MASK 0x4000514b -#define CYREG_PRT4_AMUX 0x4000514c -#define CYREG_PRT4_AG 0x4000514d -#define CYREG_PRT4_LCD_COM_SEG 0x4000514e -#define CYREG_PRT4_LCD_EN 0x4000514f -#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 -#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 -#define CYREG_PRT5_DR 0x40005150 -#define CYREG_PRT5_PS 0x40005151 -#define CYREG_PRT5_DM0 0x40005152 -#define CYREG_PRT5_DM1 0x40005153 -#define CYREG_PRT5_DM2 0x40005154 -#define CYREG_PRT5_SLW 0x40005155 -#define CYREG_PRT5_BYP 0x40005156 -#define CYREG_PRT5_BIE 0x40005157 -#define CYREG_PRT5_INP_DIS 0x40005158 -#define CYREG_PRT5_CTL 0x40005159 -#define CYREG_PRT5_PRT 0x4000515a -#define CYREG_PRT5_BIT_MASK 0x4000515b -#define CYREG_PRT5_AMUX 0x4000515c -#define CYREG_PRT5_AG 0x4000515d -#define CYREG_PRT5_LCD_COM_SEG 0x4000515e -#define CYREG_PRT5_LCD_EN 0x4000515f -#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 -#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 -#define CYREG_PRT6_DR 0x40005160 -#define CYREG_PRT6_PS 0x40005161 -#define CYREG_PRT6_DM0 0x40005162 -#define CYREG_PRT6_DM1 0x40005163 -#define CYREG_PRT6_DM2 0x40005164 -#define CYREG_PRT6_SLW 0x40005165 -#define CYREG_PRT6_BYP 0x40005166 -#define CYREG_PRT6_BIE 0x40005167 -#define CYREG_PRT6_INP_DIS 0x40005168 -#define CYREG_PRT6_CTL 0x40005169 -#define CYREG_PRT6_PRT 0x4000516a -#define CYREG_PRT6_BIT_MASK 0x4000516b -#define CYREG_PRT6_AMUX 0x4000516c -#define CYREG_PRT6_AG 0x4000516d -#define CYREG_PRT6_LCD_COM_SEG 0x4000516e -#define CYREG_PRT6_LCD_EN 0x4000516f -#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 -#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 -#define CYREG_PRT12_DR 0x400051c0 -#define CYREG_PRT12_PS 0x400051c1 -#define CYREG_PRT12_DM0 0x400051c2 -#define CYREG_PRT12_DM1 0x400051c3 -#define CYREG_PRT12_DM2 0x400051c4 -#define CYREG_PRT12_SLW 0x400051c5 -#define CYREG_PRT12_BYP 0x400051c6 -#define CYREG_PRT12_BIE 0x400051c7 -#define CYREG_PRT12_INP_DIS 0x400051c8 -#define CYREG_PRT12_SIO_HYST_EN 0x400051c9 -#define CYREG_PRT12_PRT 0x400051ca -#define CYREG_PRT12_BIT_MASK 0x400051cb -#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051cc -#define CYREG_PRT12_AG 0x400051cd -#define CYREG_PRT12_SIO_CFG 0x400051ce -#define CYREG_PRT12_SIO_DIFF 0x400051cf -#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 -#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 -#define CYREG_PRT15_DR 0x400051f0 -#define CYREG_PRT15_PS 0x400051f1 -#define CYREG_PRT15_DM0 0x400051f2 -#define CYREG_PRT15_DM1 0x400051f3 -#define CYREG_PRT15_DM2 0x400051f4 -#define CYREG_PRT15_SLW 0x400051f5 -#define CYREG_PRT15_BYP 0x400051f6 -#define CYREG_PRT15_BIE 0x400051f7 -#define CYREG_PRT15_INP_DIS 0x400051f8 -#define CYREG_PRT15_CTL 0x400051f9 -#define CYREG_PRT15_PRT 0x400051fa -#define CYREG_PRT15_BIT_MASK 0x400051fb -#define CYREG_PRT15_AMUX 0x400051fc -#define CYREG_PRT15_AG 0x400051fd -#define CYREG_PRT15_LCD_COM_SEG 0x400051fe -#define CYREG_PRT15_LCD_EN 0x400051ff -#define CYDEV_PRTDSI_BASE 0x40005200 -#define CYDEV_PRTDSI_SIZE 0x0000007f -#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 -#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 -#define CYREG_PRT0_OUT_SEL0 0x40005200 -#define CYREG_PRT0_OUT_SEL1 0x40005201 -#define CYREG_PRT0_OE_SEL0 0x40005202 -#define CYREG_PRT0_OE_SEL1 0x40005203 -#define CYREG_PRT0_DBL_SYNC_IN 0x40005204 -#define CYREG_PRT0_SYNC_OUT 0x40005205 -#define CYREG_PRT0_CAPS_SEL 0x40005206 -#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 -#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 -#define CYREG_PRT1_OUT_SEL0 0x40005208 -#define CYREG_PRT1_OUT_SEL1 0x40005209 -#define CYREG_PRT1_OE_SEL0 0x4000520a -#define CYREG_PRT1_OE_SEL1 0x4000520b -#define CYREG_PRT1_DBL_SYNC_IN 0x4000520c -#define CYREG_PRT1_SYNC_OUT 0x4000520d -#define CYREG_PRT1_CAPS_SEL 0x4000520e -#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 -#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 -#define CYREG_PRT2_OUT_SEL0 0x40005210 -#define CYREG_PRT2_OUT_SEL1 0x40005211 -#define CYREG_PRT2_OE_SEL0 0x40005212 -#define CYREG_PRT2_OE_SEL1 0x40005213 -#define CYREG_PRT2_DBL_SYNC_IN 0x40005214 -#define CYREG_PRT2_SYNC_OUT 0x40005215 -#define CYREG_PRT2_CAPS_SEL 0x40005216 -#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 -#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 -#define CYREG_PRT3_OUT_SEL0 0x40005218 -#define CYREG_PRT3_OUT_SEL1 0x40005219 -#define CYREG_PRT3_OE_SEL0 0x4000521a -#define CYREG_PRT3_OE_SEL1 0x4000521b -#define CYREG_PRT3_DBL_SYNC_IN 0x4000521c -#define CYREG_PRT3_SYNC_OUT 0x4000521d -#define CYREG_PRT3_CAPS_SEL 0x4000521e -#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 -#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 -#define CYREG_PRT4_OUT_SEL0 0x40005220 -#define CYREG_PRT4_OUT_SEL1 0x40005221 -#define CYREG_PRT4_OE_SEL0 0x40005222 -#define CYREG_PRT4_OE_SEL1 0x40005223 -#define CYREG_PRT4_DBL_SYNC_IN 0x40005224 -#define CYREG_PRT4_SYNC_OUT 0x40005225 -#define CYREG_PRT4_CAPS_SEL 0x40005226 -#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 -#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 -#define CYREG_PRT5_OUT_SEL0 0x40005228 -#define CYREG_PRT5_OUT_SEL1 0x40005229 -#define CYREG_PRT5_OE_SEL0 0x4000522a -#define CYREG_PRT5_OE_SEL1 0x4000522b -#define CYREG_PRT5_DBL_SYNC_IN 0x4000522c -#define CYREG_PRT5_SYNC_OUT 0x4000522d -#define CYREG_PRT5_CAPS_SEL 0x4000522e -#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 -#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 -#define CYREG_PRT6_OUT_SEL0 0x40005230 -#define CYREG_PRT6_OUT_SEL1 0x40005231 -#define CYREG_PRT6_OE_SEL0 0x40005232 -#define CYREG_PRT6_OE_SEL1 0x40005233 -#define CYREG_PRT6_DBL_SYNC_IN 0x40005234 -#define CYREG_PRT6_SYNC_OUT 0x40005235 -#define CYREG_PRT6_CAPS_SEL 0x40005236 -#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 -#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 -#define CYREG_PRT12_OUT_SEL0 0x40005260 -#define CYREG_PRT12_OUT_SEL1 0x40005261 -#define CYREG_PRT12_OE_SEL0 0x40005262 -#define CYREG_PRT12_OE_SEL1 0x40005263 -#define CYREG_PRT12_DBL_SYNC_IN 0x40005264 -#define CYREG_PRT12_SYNC_OUT 0x40005265 -#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 -#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 -#define CYREG_PRT15_OUT_SEL0 0x40005278 -#define CYREG_PRT15_OUT_SEL1 0x40005279 -#define CYREG_PRT15_OE_SEL0 0x4000527a -#define CYREG_PRT15_OE_SEL1 0x4000527b -#define CYREG_PRT15_DBL_SYNC_IN 0x4000527c -#define CYREG_PRT15_SYNC_OUT 0x4000527d -#define CYREG_PRT15_CAPS_SEL 0x4000527e -#define CYDEV_EMIF_BASE 0x40005400 -#define CYDEV_EMIF_SIZE 0x00000007 -#define CYREG_EMIF_NO_UDB 0x40005400 -#define CYREG_EMIF_RP_WAIT_STATES 0x40005401 -#define CYREG_EMIF_MEM_DWN 0x40005402 -#define CYREG_EMIF_MEMCLK_DIV 0x40005403 -#define CYREG_EMIF_CLOCK_EN 0x40005404 -#define CYREG_EMIF_EM_TYPE 0x40005405 -#define CYREG_EMIF_WP_WAIT_STATES 0x40005406 -#define CYDEV_ANAIF_BASE 0x40005800 -#define CYDEV_ANAIF_SIZE 0x000003a9 -#define CYDEV_ANAIF_CFG_BASE 0x40005800 -#define CYDEV_ANAIF_CFG_SIZE 0x0000010f -#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 -#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 -#define CYREG_SC0_CR0 0x40005800 -#define CYREG_SC0_CR1 0x40005801 -#define CYREG_SC0_CR2 0x40005802 -#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 -#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 -#define CYREG_SC1_CR0 0x40005804 -#define CYREG_SC1_CR1 0x40005805 -#define CYREG_SC1_CR2 0x40005806 -#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 -#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 -#define CYREG_SC2_CR0 0x40005808 -#define CYREG_SC2_CR1 0x40005809 -#define CYREG_SC2_CR2 0x4000580a -#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c -#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 -#define CYREG_SC3_CR0 0x4000580c -#define CYREG_SC3_CR1 0x4000580d -#define CYREG_SC3_CR2 0x4000580e -#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 -#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 -#define CYREG_DAC0_CR0 0x40005820 -#define CYREG_DAC0_CR1 0x40005821 -#define CYREG_DAC0_TST 0x40005822 -#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 -#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 -#define CYREG_DAC1_CR0 0x40005824 -#define CYREG_DAC1_CR1 0x40005825 -#define CYREG_DAC1_TST 0x40005826 -#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 -#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 -#define CYREG_DAC2_CR0 0x40005828 -#define CYREG_DAC2_CR1 0x40005829 -#define CYREG_DAC2_TST 0x4000582a -#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c -#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 -#define CYREG_DAC3_CR0 0x4000582c -#define CYREG_DAC3_CR1 0x4000582d -#define CYREG_DAC3_TST 0x4000582e -#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 -#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 -#define CYREG_CMP0_CR 0x40005840 -#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 -#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 -#define CYREG_CMP1_CR 0x40005841 -#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 -#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 -#define CYREG_CMP2_CR 0x40005842 -#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 -#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 -#define CYREG_CMP3_CR 0x40005843 -#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 -#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 -#define CYREG_LUT0_CR 0x40005848 -#define CYREG_LUT0_MX 0x40005849 -#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a -#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 -#define CYREG_LUT1_CR 0x4000584a -#define CYREG_LUT1_MX 0x4000584b -#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c -#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 -#define CYREG_LUT2_CR 0x4000584c -#define CYREG_LUT2_MX 0x4000584d -#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e -#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 -#define CYREG_LUT3_CR 0x4000584e -#define CYREG_LUT3_MX 0x4000584f -#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 -#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 -#define CYREG_OPAMP0_CR 0x40005858 -#define CYREG_OPAMP0_RSVD 0x40005859 -#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a -#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 -#define CYREG_OPAMP1_CR 0x4000585a -#define CYREG_OPAMP1_RSVD 0x4000585b -#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c -#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 -#define CYREG_OPAMP2_CR 0x4000585c -#define CYREG_OPAMP2_RSVD 0x4000585d -#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e -#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 -#define CYREG_OPAMP3_CR 0x4000585e -#define CYREG_OPAMP3_RSVD 0x4000585f -#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 -#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 -#define CYREG_LCDDAC_CR0 0x40005868 -#define CYREG_LCDDAC_CR1 0x40005869 -#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a -#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 -#define CYREG_LCDDRV_CR 0x4000586a -#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b -#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 -#define CYREG_LCDTMR_CFG 0x4000586b -#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c -#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 -#define CYREG_BG_CR0 0x4000586c -#define CYREG_BG_RSVD 0x4000586d -#define CYREG_BG_DFT0 0x4000586e -#define CYREG_BG_DFT1 0x4000586f -#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 -#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 -#define CYREG_CAPSL_CFG0 0x40005870 -#define CYREG_CAPSL_CFG1 0x40005871 -#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 -#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 -#define CYREG_CAPSR_CFG0 0x40005872 -#define CYREG_CAPSR_CFG1 0x40005873 -#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 -#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 -#define CYREG_PUMP_CR0 0x40005876 -#define CYREG_PUMP_CR1 0x40005877 -#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 -#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 -#define CYREG_LPF0_CR0 0x40005878 -#define CYREG_LPF0_RSVD 0x40005879 -#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a -#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 -#define CYREG_LPF1_CR0 0x4000587a -#define CYREG_LPF1_RSVD 0x4000587b -#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c -#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 -#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587c -#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 -#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 -#define CYREG_DSM0_CR0 0x40005880 -#define CYREG_DSM0_CR1 0x40005881 -#define CYREG_DSM0_CR2 0x40005882 -#define CYREG_DSM0_CR3 0x40005883 -#define CYREG_DSM0_CR4 0x40005884 -#define CYREG_DSM0_CR5 0x40005885 -#define CYREG_DSM0_CR6 0x40005886 -#define CYREG_DSM0_CR7 0x40005887 -#define CYREG_DSM0_CR8 0x40005888 -#define CYREG_DSM0_CR9 0x40005889 -#define CYREG_DSM0_CR10 0x4000588a -#define CYREG_DSM0_CR11 0x4000588b -#define CYREG_DSM0_CR12 0x4000588c -#define CYREG_DSM0_CR13 0x4000588d -#define CYREG_DSM0_CR14 0x4000588e -#define CYREG_DSM0_CR15 0x4000588f -#define CYREG_DSM0_CR16 0x40005890 -#define CYREG_DSM0_CR17 0x40005891 -#define CYREG_DSM0_REF0 0x40005892 -#define CYREG_DSM0_REF1 0x40005893 -#define CYREG_DSM0_REF2 0x40005894 -#define CYREG_DSM0_REF3 0x40005895 -#define CYREG_DSM0_DEM0 0x40005896 -#define CYREG_DSM0_DEM1 0x40005897 -#define CYREG_DSM0_TST0 0x40005898 -#define CYREG_DSM0_TST1 0x40005899 -#define CYREG_DSM0_BUF0 0x4000589a -#define CYREG_DSM0_BUF1 0x4000589b -#define CYREG_DSM0_BUF2 0x4000589c -#define CYREG_DSM0_BUF3 0x4000589d -#define CYREG_DSM0_MISC 0x4000589e -#define CYREG_DSM0_RSVD1 0x4000589f -#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 -#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 -#define CYREG_SAR0_CSR0 0x40005900 -#define CYREG_SAR0_CSR1 0x40005901 -#define CYREG_SAR0_CSR2 0x40005902 -#define CYREG_SAR0_CSR3 0x40005903 -#define CYREG_SAR0_CSR4 0x40005904 -#define CYREG_SAR0_CSR5 0x40005905 -#define CYREG_SAR0_CSR6 0x40005906 -#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 -#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 -#define CYREG_SAR1_CSR0 0x40005908 -#define CYREG_SAR1_CSR1 0x40005909 -#define CYREG_SAR1_CSR2 0x4000590a -#define CYREG_SAR1_CSR3 0x4000590b -#define CYREG_SAR1_CSR4 0x4000590c -#define CYREG_SAR1_CSR5 0x4000590d -#define CYREG_SAR1_CSR6 0x4000590e -#define CYDEV_ANAIF_RT_BASE 0x40005a00 -#define CYDEV_ANAIF_RT_SIZE 0x00000162 -#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 -#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d -#define CYREG_SC0_SW0 0x40005a00 -#define CYREG_SC0_SW2 0x40005a02 -#define CYREG_SC0_SW3 0x40005a03 -#define CYREG_SC0_SW4 0x40005a04 -#define CYREG_SC0_SW6 0x40005a06 -#define CYREG_SC0_SW7 0x40005a07 -#define CYREG_SC0_SW8 0x40005a08 -#define CYREG_SC0_SW10 0x40005a0a -#define CYREG_SC0_CLK 0x40005a0b -#define CYREG_SC0_BST 0x40005a0c -#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 -#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d -#define CYREG_SC1_SW0 0x40005a10 -#define CYREG_SC1_SW2 0x40005a12 -#define CYREG_SC1_SW3 0x40005a13 -#define CYREG_SC1_SW4 0x40005a14 -#define CYREG_SC1_SW6 0x40005a16 -#define CYREG_SC1_SW7 0x40005a17 -#define CYREG_SC1_SW8 0x40005a18 -#define CYREG_SC1_SW10 0x40005a1a -#define CYREG_SC1_CLK 0x40005a1b -#define CYREG_SC1_BST 0x40005a1c -#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 -#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d -#define CYREG_SC2_SW0 0x40005a20 -#define CYREG_SC2_SW2 0x40005a22 -#define CYREG_SC2_SW3 0x40005a23 -#define CYREG_SC2_SW4 0x40005a24 -#define CYREG_SC2_SW6 0x40005a26 -#define CYREG_SC2_SW7 0x40005a27 -#define CYREG_SC2_SW8 0x40005a28 -#define CYREG_SC2_SW10 0x40005a2a -#define CYREG_SC2_CLK 0x40005a2b -#define CYREG_SC2_BST 0x40005a2c -#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 -#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d -#define CYREG_SC3_SW0 0x40005a30 -#define CYREG_SC3_SW2 0x40005a32 -#define CYREG_SC3_SW3 0x40005a33 -#define CYREG_SC3_SW4 0x40005a34 -#define CYREG_SC3_SW6 0x40005a36 -#define CYREG_SC3_SW7 0x40005a37 -#define CYREG_SC3_SW8 0x40005a38 -#define CYREG_SC3_SW10 0x40005a3a -#define CYREG_SC3_CLK 0x40005a3b -#define CYREG_SC3_BST 0x40005a3c -#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 -#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 -#define CYREG_DAC0_SW0 0x40005a80 -#define CYREG_DAC0_SW2 0x40005a82 -#define CYREG_DAC0_SW3 0x40005a83 -#define CYREG_DAC0_SW4 0x40005a84 -#define CYREG_DAC0_STROBE 0x40005a87 -#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 -#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 -#define CYREG_DAC1_SW0 0x40005a88 -#define CYREG_DAC1_SW2 0x40005a8a -#define CYREG_DAC1_SW3 0x40005a8b -#define CYREG_DAC1_SW4 0x40005a8c -#define CYREG_DAC1_STROBE 0x40005a8f -#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 -#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 -#define CYREG_DAC2_SW0 0x40005a90 -#define CYREG_DAC2_SW2 0x40005a92 -#define CYREG_DAC2_SW3 0x40005a93 -#define CYREG_DAC2_SW4 0x40005a94 -#define CYREG_DAC2_STROBE 0x40005a97 -#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 -#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 -#define CYREG_DAC3_SW0 0x40005a98 -#define CYREG_DAC3_SW2 0x40005a9a -#define CYREG_DAC3_SW3 0x40005a9b -#define CYREG_DAC3_SW4 0x40005a9c -#define CYREG_DAC3_STROBE 0x40005a9f -#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 -#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 -#define CYREG_CMP0_SW0 0x40005ac0 -#define CYREG_CMP0_SW2 0x40005ac2 -#define CYREG_CMP0_SW3 0x40005ac3 -#define CYREG_CMP0_SW4 0x40005ac4 -#define CYREG_CMP0_SW6 0x40005ac6 -#define CYREG_CMP0_CLK 0x40005ac7 -#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 -#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 -#define CYREG_CMP1_SW0 0x40005ac8 -#define CYREG_CMP1_SW2 0x40005aca -#define CYREG_CMP1_SW3 0x40005acb -#define CYREG_CMP1_SW4 0x40005acc -#define CYREG_CMP1_SW6 0x40005ace -#define CYREG_CMP1_CLK 0x40005acf -#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 -#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 -#define CYREG_CMP2_SW0 0x40005ad0 -#define CYREG_CMP2_SW2 0x40005ad2 -#define CYREG_CMP2_SW3 0x40005ad3 -#define CYREG_CMP2_SW4 0x40005ad4 -#define CYREG_CMP2_SW6 0x40005ad6 -#define CYREG_CMP2_CLK 0x40005ad7 -#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 -#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 -#define CYREG_CMP3_SW0 0x40005ad8 -#define CYREG_CMP3_SW2 0x40005ada -#define CYREG_CMP3_SW3 0x40005adb -#define CYREG_CMP3_SW4 0x40005adc -#define CYREG_CMP3_SW6 0x40005ade -#define CYREG_CMP3_CLK 0x40005adf -#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 -#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 -#define CYREG_DSM0_SW0 0x40005b00 -#define CYREG_DSM0_SW2 0x40005b02 -#define CYREG_DSM0_SW3 0x40005b03 -#define CYREG_DSM0_SW4 0x40005b04 -#define CYREG_DSM0_SW6 0x40005b06 -#define CYREG_DSM0_CLK 0x40005b07 -#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 -#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 -#define CYREG_SAR0_SW0 0x40005b20 -#define CYREG_SAR0_SW2 0x40005b22 -#define CYREG_SAR0_SW3 0x40005b23 -#define CYREG_SAR0_SW4 0x40005b24 -#define CYREG_SAR0_SW6 0x40005b26 -#define CYREG_SAR0_CLK 0x40005b27 -#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 -#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 -#define CYREG_SAR1_SW0 0x40005b28 -#define CYREG_SAR1_SW2 0x40005b2a -#define CYREG_SAR1_SW3 0x40005b2b -#define CYREG_SAR1_SW4 0x40005b2c -#define CYREG_SAR1_SW6 0x40005b2e -#define CYREG_SAR1_CLK 0x40005b2f -#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 -#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 -#define CYREG_OPAMP0_MX 0x40005b40 -#define CYREG_OPAMP0_SW 0x40005b41 -#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 -#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 -#define CYREG_OPAMP1_MX 0x40005b42 -#define CYREG_OPAMP1_SW 0x40005b43 -#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 -#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 -#define CYREG_OPAMP2_MX 0x40005b44 -#define CYREG_OPAMP2_SW 0x40005b45 -#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 -#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 -#define CYREG_OPAMP3_MX 0x40005b46 -#define CYREG_OPAMP3_SW 0x40005b47 -#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 -#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 -#define CYREG_LCDDAC_SW0 0x40005b50 -#define CYREG_LCDDAC_SW1 0x40005b51 -#define CYREG_LCDDAC_SW2 0x40005b52 -#define CYREG_LCDDAC_SW3 0x40005b53 -#define CYREG_LCDDAC_SW4 0x40005b54 -#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 -#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 -#define CYREG_SC_MISC 0x40005b56 -#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 -#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 -#define CYREG_BUS_SW0 0x40005b58 -#define CYREG_BUS_SW2 0x40005b5a -#define CYREG_BUS_SW3 0x40005b5b -#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c -#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 -#define CYREG_DFT_CR0 0x40005b5c -#define CYREG_DFT_CR1 0x40005b5d -#define CYREG_DFT_CR2 0x40005b5e -#define CYREG_DFT_CR3 0x40005b5f -#define CYREG_DFT_CR4 0x40005b60 -#define CYREG_DFT_CR5 0x40005b61 -#define CYDEV_ANAIF_WRK_BASE 0x40005b80 -#define CYDEV_ANAIF_WRK_SIZE 0x00000029 -#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 -#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 -#define CYREG_DAC0_D 0x40005b80 -#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 -#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 -#define CYREG_DAC1_D 0x40005b81 -#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 -#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 -#define CYREG_DAC2_D 0x40005b82 -#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 -#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 -#define CYREG_DAC3_D 0x40005b83 -#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 -#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 -#define CYREG_DSM0_OUT0 0x40005b88 -#define CYREG_DSM0_OUT1 0x40005b89 -#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 -#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 -#define CYREG_LUT_SR 0x40005b90 -#define CYREG_LUT_WRK1 0x40005b91 -#define CYREG_LUT_MSK 0x40005b92 -#define CYREG_LUT_CLK 0x40005b93 -#define CYREG_LUT_CPTR 0x40005b94 -#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 -#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 -#define CYREG_CMP_WRK 0x40005b96 -#define CYREG_CMP_TST 0x40005b97 -#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 -#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 -#define CYREG_SC_SR 0x40005b98 -#define CYREG_SC_WRK1 0x40005b99 -#define CYREG_SC_MSK 0x40005b9a -#define CYREG_SC_CMPINV 0x40005b9b -#define CYREG_SC_CPTR 0x40005b9c -#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 -#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 -#define CYREG_SAR0_WRK0 0x40005ba0 -#define CYREG_SAR0_WRK1 0x40005ba1 -#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 -#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 -#define CYREG_SAR1_WRK0 0x40005ba2 -#define CYREG_SAR1_WRK1 0x40005ba3 -#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 -#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 -#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8 -#define CYDEV_USB_BASE 0x40006000 -#define CYDEV_USB_SIZE 0x00000300 -#define CYREG_USB_EP0_DR0 0x40006000 -#define CYREG_USB_EP0_DR1 0x40006001 -#define CYREG_USB_EP0_DR2 0x40006002 -#define CYREG_USB_EP0_DR3 0x40006003 -#define CYREG_USB_EP0_DR4 0x40006004 -#define CYREG_USB_EP0_DR5 0x40006005 -#define CYREG_USB_EP0_DR6 0x40006006 -#define CYREG_USB_EP0_DR7 0x40006007 -#define CYREG_USB_CR0 0x40006008 -#define CYREG_USB_CR1 0x40006009 -#define CYREG_USB_SIE_EP_INT_EN 0x4000600a -#define CYREG_USB_SIE_EP_INT_SR 0x4000600b -#define CYDEV_USB_SIE_EP1_BASE 0x4000600c -#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 -#define CYREG_USB_SIE_EP1_CNT0 0x4000600c -#define CYREG_USB_SIE_EP1_CNT1 0x4000600d -#define CYREG_USB_SIE_EP1_CR0 0x4000600e -#define CYREG_USB_USBIO_CR0 0x40006010 -#define CYREG_USB_USBIO_CR1 0x40006012 -#define CYREG_USB_DYN_RECONFIG 0x40006014 -#define CYREG_USB_SOF0 0x40006018 -#define CYREG_USB_SOF1 0x40006019 -#define CYDEV_USB_SIE_EP2_BASE 0x4000601c -#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 -#define CYREG_USB_SIE_EP2_CNT0 0x4000601c -#define CYREG_USB_SIE_EP2_CNT1 0x4000601d -#define CYREG_USB_SIE_EP2_CR0 0x4000601e -#define CYREG_USB_EP0_CR 0x40006028 -#define CYREG_USB_EP0_CNT 0x40006029 -#define CYDEV_USB_SIE_EP3_BASE 0x4000602c -#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 -#define CYREG_USB_SIE_EP3_CNT0 0x4000602c -#define CYREG_USB_SIE_EP3_CNT1 0x4000602d -#define CYREG_USB_SIE_EP3_CR0 0x4000602e -#define CYDEV_USB_SIE_EP4_BASE 0x4000603c -#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 -#define CYREG_USB_SIE_EP4_CNT0 0x4000603c -#define CYREG_USB_SIE_EP4_CNT1 0x4000603d -#define CYREG_USB_SIE_EP4_CR0 0x4000603e -#define CYDEV_USB_SIE_EP5_BASE 0x4000604c -#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 -#define CYREG_USB_SIE_EP5_CNT0 0x4000604c -#define CYREG_USB_SIE_EP5_CNT1 0x4000604d -#define CYREG_USB_SIE_EP5_CR0 0x4000604e -#define CYDEV_USB_SIE_EP6_BASE 0x4000605c -#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 -#define CYREG_USB_SIE_EP6_CNT0 0x4000605c -#define CYREG_USB_SIE_EP6_CNT1 0x4000605d -#define CYREG_USB_SIE_EP6_CR0 0x4000605e -#define CYDEV_USB_SIE_EP7_BASE 0x4000606c -#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 -#define CYREG_USB_SIE_EP7_CNT0 0x4000606c -#define CYREG_USB_SIE_EP7_CNT1 0x4000606d -#define CYREG_USB_SIE_EP7_CR0 0x4000606e -#define CYDEV_USB_SIE_EP8_BASE 0x4000607c -#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 -#define CYREG_USB_SIE_EP8_CNT0 0x4000607c -#define CYREG_USB_SIE_EP8_CNT1 0x4000607d -#define CYREG_USB_SIE_EP8_CR0 0x4000607e -#define CYDEV_USB_ARB_EP1_BASE 0x40006080 -#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 -#define CYREG_USB_ARB_EP1_CFG 0x40006080 -#define CYREG_USB_ARB_EP1_INT_EN 0x40006081 -#define CYREG_USB_ARB_EP1_SR 0x40006082 -#define CYDEV_USB_ARB_RW1_BASE 0x40006084 -#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 -#define CYREG_USB_ARB_RW1_WA 0x40006084 -#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085 -#define CYREG_USB_ARB_RW1_RA 0x40006086 -#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087 -#define CYREG_USB_ARB_RW1_DR 0x40006088 -#define CYREG_USB_BUF_SIZE 0x4000608c -#define CYREG_USB_EP_ACTIVE 0x4000608e -#define CYREG_USB_EP_TYPE 0x4000608f -#define CYDEV_USB_ARB_EP2_BASE 0x40006090 -#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 -#define CYREG_USB_ARB_EP2_CFG 0x40006090 -#define CYREG_USB_ARB_EP2_INT_EN 0x40006091 -#define CYREG_USB_ARB_EP2_SR 0x40006092 -#define CYDEV_USB_ARB_RW2_BASE 0x40006094 -#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 -#define CYREG_USB_ARB_RW2_WA 0x40006094 -#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095 -#define CYREG_USB_ARB_RW2_RA 0x40006096 -#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097 -#define CYREG_USB_ARB_RW2_DR 0x40006098 -#define CYREG_USB_ARB_CFG 0x4000609c -#define CYREG_USB_USB_CLK_EN 0x4000609d -#define CYREG_USB_ARB_INT_EN 0x4000609e -#define CYREG_USB_ARB_INT_SR 0x4000609f -#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 -#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 -#define CYREG_USB_ARB_EP3_CFG 0x400060a0 -#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1 -#define CYREG_USB_ARB_EP3_SR 0x400060a2 -#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 -#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 -#define CYREG_USB_ARB_RW3_WA 0x400060a4 -#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5 -#define CYREG_USB_ARB_RW3_RA 0x400060a6 -#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7 -#define CYREG_USB_ARB_RW3_DR 0x400060a8 -#define CYREG_USB_CWA 0x400060ac -#define CYREG_USB_CWA_MSB 0x400060ad -#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 -#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 -#define CYREG_USB_ARB_EP4_CFG 0x400060b0 -#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1 -#define CYREG_USB_ARB_EP4_SR 0x400060b2 -#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 -#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 -#define CYREG_USB_ARB_RW4_WA 0x400060b4 -#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5 -#define CYREG_USB_ARB_RW4_RA 0x400060b6 -#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7 -#define CYREG_USB_ARB_RW4_DR 0x400060b8 -#define CYREG_USB_DMA_THRES 0x400060bc -#define CYREG_USB_DMA_THRES_MSB 0x400060bd -#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 -#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 -#define CYREG_USB_ARB_EP5_CFG 0x400060c0 -#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1 -#define CYREG_USB_ARB_EP5_SR 0x400060c2 -#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 -#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 -#define CYREG_USB_ARB_RW5_WA 0x400060c4 -#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5 -#define CYREG_USB_ARB_RW5_RA 0x400060c6 -#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7 -#define CYREG_USB_ARB_RW5_DR 0x400060c8 -#define CYREG_USB_BUS_RST_CNT 0x400060cc -#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 -#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 -#define CYREG_USB_ARB_EP6_CFG 0x400060d0 -#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1 -#define CYREG_USB_ARB_EP6_SR 0x400060d2 -#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 -#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 -#define CYREG_USB_ARB_RW6_WA 0x400060d4 -#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5 -#define CYREG_USB_ARB_RW6_RA 0x400060d6 -#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7 -#define CYREG_USB_ARB_RW6_DR 0x400060d8 -#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 -#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 -#define CYREG_USB_ARB_EP7_CFG 0x400060e0 -#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1 -#define CYREG_USB_ARB_EP7_SR 0x400060e2 -#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 -#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 -#define CYREG_USB_ARB_RW7_WA 0x400060e4 -#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5 -#define CYREG_USB_ARB_RW7_RA 0x400060e6 -#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7 -#define CYREG_USB_ARB_RW7_DR 0x400060e8 -#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 -#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 -#define CYREG_USB_ARB_EP8_CFG 0x400060f0 -#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1 -#define CYREG_USB_ARB_EP8_SR 0x400060f2 -#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 -#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 -#define CYREG_USB_ARB_RW8_WA 0x400060f4 -#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5 -#define CYREG_USB_ARB_RW8_RA 0x400060f6 -#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7 -#define CYREG_USB_ARB_RW8_DR 0x400060f8 -#define CYDEV_USB_MEM_BASE 0x40006100 -#define CYDEV_USB_MEM_SIZE 0x00000200 -#define CYREG_USB_MEM_DATA_MBASE 0x40006100 -#define CYREG_USB_MEM_DATA_MSIZE 0x00000200 -#define CYDEV_UWRK_BASE 0x40006400 -#define CYDEV_UWRK_SIZE 0x00000b60 -#define CYDEV_UWRK_UWRK8_BASE 0x40006400 -#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 -#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 -#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 -#define CYREG_B0_UDB00_A0 0x40006400 -#define CYREG_B0_UDB01_A0 0x40006401 -#define CYREG_B0_UDB02_A0 0x40006402 -#define CYREG_B0_UDB03_A0 0x40006403 -#define CYREG_B0_UDB04_A0 0x40006404 -#define CYREG_B0_UDB05_A0 0x40006405 -#define CYREG_B0_UDB06_A0 0x40006406 -#define CYREG_B0_UDB07_A0 0x40006407 -#define CYREG_B0_UDB08_A0 0x40006408 -#define CYREG_B0_UDB09_A0 0x40006409 -#define CYREG_B0_UDB10_A0 0x4000640a -#define CYREG_B0_UDB11_A0 0x4000640b -#define CYREG_B0_UDB12_A0 0x4000640c -#define CYREG_B0_UDB13_A0 0x4000640d -#define CYREG_B0_UDB14_A0 0x4000640e -#define CYREG_B0_UDB15_A0 0x4000640f -#define CYREG_B0_UDB00_A1 0x40006410 -#define CYREG_B0_UDB01_A1 0x40006411 -#define CYREG_B0_UDB02_A1 0x40006412 -#define CYREG_B0_UDB03_A1 0x40006413 -#define CYREG_B0_UDB04_A1 0x40006414 -#define CYREG_B0_UDB05_A1 0x40006415 -#define CYREG_B0_UDB06_A1 0x40006416 -#define CYREG_B0_UDB07_A1 0x40006417 -#define CYREG_B0_UDB08_A1 0x40006418 -#define CYREG_B0_UDB09_A1 0x40006419 -#define CYREG_B0_UDB10_A1 0x4000641a -#define CYREG_B0_UDB11_A1 0x4000641b -#define CYREG_B0_UDB12_A1 0x4000641c -#define CYREG_B0_UDB13_A1 0x4000641d -#define CYREG_B0_UDB14_A1 0x4000641e -#define CYREG_B0_UDB15_A1 0x4000641f -#define CYREG_B0_UDB00_D0 0x40006420 -#define CYREG_B0_UDB01_D0 0x40006421 -#define CYREG_B0_UDB02_D0 0x40006422 -#define CYREG_B0_UDB03_D0 0x40006423 -#define CYREG_B0_UDB04_D0 0x40006424 -#define CYREG_B0_UDB05_D0 0x40006425 -#define CYREG_B0_UDB06_D0 0x40006426 -#define CYREG_B0_UDB07_D0 0x40006427 -#define CYREG_B0_UDB08_D0 0x40006428 -#define CYREG_B0_UDB09_D0 0x40006429 -#define CYREG_B0_UDB10_D0 0x4000642a -#define CYREG_B0_UDB11_D0 0x4000642b -#define CYREG_B0_UDB12_D0 0x4000642c -#define CYREG_B0_UDB13_D0 0x4000642d -#define CYREG_B0_UDB14_D0 0x4000642e -#define CYREG_B0_UDB15_D0 0x4000642f -#define CYREG_B0_UDB00_D1 0x40006430 -#define CYREG_B0_UDB01_D1 0x40006431 -#define CYREG_B0_UDB02_D1 0x40006432 -#define CYREG_B0_UDB03_D1 0x40006433 -#define CYREG_B0_UDB04_D1 0x40006434 -#define CYREG_B0_UDB05_D1 0x40006435 -#define CYREG_B0_UDB06_D1 0x40006436 -#define CYREG_B0_UDB07_D1 0x40006437 -#define CYREG_B0_UDB08_D1 0x40006438 -#define CYREG_B0_UDB09_D1 0x40006439 -#define CYREG_B0_UDB10_D1 0x4000643a -#define CYREG_B0_UDB11_D1 0x4000643b -#define CYREG_B0_UDB12_D1 0x4000643c -#define CYREG_B0_UDB13_D1 0x4000643d -#define CYREG_B0_UDB14_D1 0x4000643e -#define CYREG_B0_UDB15_D1 0x4000643f -#define CYREG_B0_UDB00_F0 0x40006440 -#define CYREG_B0_UDB01_F0 0x40006441 -#define CYREG_B0_UDB02_F0 0x40006442 -#define CYREG_B0_UDB03_F0 0x40006443 -#define CYREG_B0_UDB04_F0 0x40006444 -#define CYREG_B0_UDB05_F0 0x40006445 -#define CYREG_B0_UDB06_F0 0x40006446 -#define CYREG_B0_UDB07_F0 0x40006447 -#define CYREG_B0_UDB08_F0 0x40006448 -#define CYREG_B0_UDB09_F0 0x40006449 -#define CYREG_B0_UDB10_F0 0x4000644a -#define CYREG_B0_UDB11_F0 0x4000644b -#define CYREG_B0_UDB12_F0 0x4000644c -#define CYREG_B0_UDB13_F0 0x4000644d -#define CYREG_B0_UDB14_F0 0x4000644e -#define CYREG_B0_UDB15_F0 0x4000644f -#define CYREG_B0_UDB00_F1 0x40006450 -#define CYREG_B0_UDB01_F1 0x40006451 -#define CYREG_B0_UDB02_F1 0x40006452 -#define CYREG_B0_UDB03_F1 0x40006453 -#define CYREG_B0_UDB04_F1 0x40006454 -#define CYREG_B0_UDB05_F1 0x40006455 -#define CYREG_B0_UDB06_F1 0x40006456 -#define CYREG_B0_UDB07_F1 0x40006457 -#define CYREG_B0_UDB08_F1 0x40006458 -#define CYREG_B0_UDB09_F1 0x40006459 -#define CYREG_B0_UDB10_F1 0x4000645a -#define CYREG_B0_UDB11_F1 0x4000645b -#define CYREG_B0_UDB12_F1 0x4000645c -#define CYREG_B0_UDB13_F1 0x4000645d -#define CYREG_B0_UDB14_F1 0x4000645e -#define CYREG_B0_UDB15_F1 0x4000645f -#define CYREG_B0_UDB00_ST 0x40006460 -#define CYREG_B0_UDB01_ST 0x40006461 -#define CYREG_B0_UDB02_ST 0x40006462 -#define CYREG_B0_UDB03_ST 0x40006463 -#define CYREG_B0_UDB04_ST 0x40006464 -#define CYREG_B0_UDB05_ST 0x40006465 -#define CYREG_B0_UDB06_ST 0x40006466 -#define CYREG_B0_UDB07_ST 0x40006467 -#define CYREG_B0_UDB08_ST 0x40006468 -#define CYREG_B0_UDB09_ST 0x40006469 -#define CYREG_B0_UDB10_ST 0x4000646a -#define CYREG_B0_UDB11_ST 0x4000646b -#define CYREG_B0_UDB12_ST 0x4000646c -#define CYREG_B0_UDB13_ST 0x4000646d -#define CYREG_B0_UDB14_ST 0x4000646e -#define CYREG_B0_UDB15_ST 0x4000646f -#define CYREG_B0_UDB00_CTL 0x40006470 -#define CYREG_B0_UDB01_CTL 0x40006471 -#define CYREG_B0_UDB02_CTL 0x40006472 -#define CYREG_B0_UDB03_CTL 0x40006473 -#define CYREG_B0_UDB04_CTL 0x40006474 -#define CYREG_B0_UDB05_CTL 0x40006475 -#define CYREG_B0_UDB06_CTL 0x40006476 -#define CYREG_B0_UDB07_CTL 0x40006477 -#define CYREG_B0_UDB08_CTL 0x40006478 -#define CYREG_B0_UDB09_CTL 0x40006479 -#define CYREG_B0_UDB10_CTL 0x4000647a -#define CYREG_B0_UDB11_CTL 0x4000647b -#define CYREG_B0_UDB12_CTL 0x4000647c -#define CYREG_B0_UDB13_CTL 0x4000647d -#define CYREG_B0_UDB14_CTL 0x4000647e -#define CYREG_B0_UDB15_CTL 0x4000647f -#define CYREG_B0_UDB00_MSK 0x40006480 -#define CYREG_B0_UDB01_MSK 0x40006481 -#define CYREG_B0_UDB02_MSK 0x40006482 -#define CYREG_B0_UDB03_MSK 0x40006483 -#define CYREG_B0_UDB04_MSK 0x40006484 -#define CYREG_B0_UDB05_MSK 0x40006485 -#define CYREG_B0_UDB06_MSK 0x40006486 -#define CYREG_B0_UDB07_MSK 0x40006487 -#define CYREG_B0_UDB08_MSK 0x40006488 -#define CYREG_B0_UDB09_MSK 0x40006489 -#define CYREG_B0_UDB10_MSK 0x4000648a -#define CYREG_B0_UDB11_MSK 0x4000648b -#define CYREG_B0_UDB12_MSK 0x4000648c -#define CYREG_B0_UDB13_MSK 0x4000648d -#define CYREG_B0_UDB14_MSK 0x4000648e -#define CYREG_B0_UDB15_MSK 0x4000648f -#define CYREG_B0_UDB00_ACTL 0x40006490 -#define CYREG_B0_UDB01_ACTL 0x40006491 -#define CYREG_B0_UDB02_ACTL 0x40006492 -#define CYREG_B0_UDB03_ACTL 0x40006493 -#define CYREG_B0_UDB04_ACTL 0x40006494 -#define CYREG_B0_UDB05_ACTL 0x40006495 -#define CYREG_B0_UDB06_ACTL 0x40006496 -#define CYREG_B0_UDB07_ACTL 0x40006497 -#define CYREG_B0_UDB08_ACTL 0x40006498 -#define CYREG_B0_UDB09_ACTL 0x40006499 -#define CYREG_B0_UDB10_ACTL 0x4000649a -#define CYREG_B0_UDB11_ACTL 0x4000649b -#define CYREG_B0_UDB12_ACTL 0x4000649c -#define CYREG_B0_UDB13_ACTL 0x4000649d -#define CYREG_B0_UDB14_ACTL 0x4000649e -#define CYREG_B0_UDB15_ACTL 0x4000649f -#define CYREG_B0_UDB00_MC 0x400064a0 -#define CYREG_B0_UDB01_MC 0x400064a1 -#define CYREG_B0_UDB02_MC 0x400064a2 -#define CYREG_B0_UDB03_MC 0x400064a3 -#define CYREG_B0_UDB04_MC 0x400064a4 -#define CYREG_B0_UDB05_MC 0x400064a5 -#define CYREG_B0_UDB06_MC 0x400064a6 -#define CYREG_B0_UDB07_MC 0x400064a7 -#define CYREG_B0_UDB08_MC 0x400064a8 -#define CYREG_B0_UDB09_MC 0x400064a9 -#define CYREG_B0_UDB10_MC 0x400064aa -#define CYREG_B0_UDB11_MC 0x400064ab -#define CYREG_B0_UDB12_MC 0x400064ac -#define CYREG_B0_UDB13_MC 0x400064ad -#define CYREG_B0_UDB14_MC 0x400064ae -#define CYREG_B0_UDB15_MC 0x400064af -#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 -#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 -#define CYREG_B1_UDB04_A0 0x40006504 -#define CYREG_B1_UDB05_A0 0x40006505 -#define CYREG_B1_UDB06_A0 0x40006506 -#define CYREG_B1_UDB07_A0 0x40006507 -#define CYREG_B1_UDB08_A0 0x40006508 -#define CYREG_B1_UDB09_A0 0x40006509 -#define CYREG_B1_UDB10_A0 0x4000650a -#define CYREG_B1_UDB11_A0 0x4000650b -#define CYREG_B1_UDB04_A1 0x40006514 -#define CYREG_B1_UDB05_A1 0x40006515 -#define CYREG_B1_UDB06_A1 0x40006516 -#define CYREG_B1_UDB07_A1 0x40006517 -#define CYREG_B1_UDB08_A1 0x40006518 -#define CYREG_B1_UDB09_A1 0x40006519 -#define CYREG_B1_UDB10_A1 0x4000651a -#define CYREG_B1_UDB11_A1 0x4000651b -#define CYREG_B1_UDB04_D0 0x40006524 -#define CYREG_B1_UDB05_D0 0x40006525 -#define CYREG_B1_UDB06_D0 0x40006526 -#define CYREG_B1_UDB07_D0 0x40006527 -#define CYREG_B1_UDB08_D0 0x40006528 -#define CYREG_B1_UDB09_D0 0x40006529 -#define CYREG_B1_UDB10_D0 0x4000652a -#define CYREG_B1_UDB11_D0 0x4000652b -#define CYREG_B1_UDB04_D1 0x40006534 -#define CYREG_B1_UDB05_D1 0x40006535 -#define CYREG_B1_UDB06_D1 0x40006536 -#define CYREG_B1_UDB07_D1 0x40006537 -#define CYREG_B1_UDB08_D1 0x40006538 -#define CYREG_B1_UDB09_D1 0x40006539 -#define CYREG_B1_UDB10_D1 0x4000653a -#define CYREG_B1_UDB11_D1 0x4000653b -#define CYREG_B1_UDB04_F0 0x40006544 -#define CYREG_B1_UDB05_F0 0x40006545 -#define CYREG_B1_UDB06_F0 0x40006546 -#define CYREG_B1_UDB07_F0 0x40006547 -#define CYREG_B1_UDB08_F0 0x40006548 -#define CYREG_B1_UDB09_F0 0x40006549 -#define CYREG_B1_UDB10_F0 0x4000654a -#define CYREG_B1_UDB11_F0 0x4000654b -#define CYREG_B1_UDB04_F1 0x40006554 -#define CYREG_B1_UDB05_F1 0x40006555 -#define CYREG_B1_UDB06_F1 0x40006556 -#define CYREG_B1_UDB07_F1 0x40006557 -#define CYREG_B1_UDB08_F1 0x40006558 -#define CYREG_B1_UDB09_F1 0x40006559 -#define CYREG_B1_UDB10_F1 0x4000655a -#define CYREG_B1_UDB11_F1 0x4000655b -#define CYREG_B1_UDB04_ST 0x40006564 -#define CYREG_B1_UDB05_ST 0x40006565 -#define CYREG_B1_UDB06_ST 0x40006566 -#define CYREG_B1_UDB07_ST 0x40006567 -#define CYREG_B1_UDB08_ST 0x40006568 -#define CYREG_B1_UDB09_ST 0x40006569 -#define CYREG_B1_UDB10_ST 0x4000656a -#define CYREG_B1_UDB11_ST 0x4000656b -#define CYREG_B1_UDB04_CTL 0x40006574 -#define CYREG_B1_UDB05_CTL 0x40006575 -#define CYREG_B1_UDB06_CTL 0x40006576 -#define CYREG_B1_UDB07_CTL 0x40006577 -#define CYREG_B1_UDB08_CTL 0x40006578 -#define CYREG_B1_UDB09_CTL 0x40006579 -#define CYREG_B1_UDB10_CTL 0x4000657a -#define CYREG_B1_UDB11_CTL 0x4000657b -#define CYREG_B1_UDB04_MSK 0x40006584 -#define CYREG_B1_UDB05_MSK 0x40006585 -#define CYREG_B1_UDB06_MSK 0x40006586 -#define CYREG_B1_UDB07_MSK 0x40006587 -#define CYREG_B1_UDB08_MSK 0x40006588 -#define CYREG_B1_UDB09_MSK 0x40006589 -#define CYREG_B1_UDB10_MSK 0x4000658a -#define CYREG_B1_UDB11_MSK 0x4000658b -#define CYREG_B1_UDB04_ACTL 0x40006594 -#define CYREG_B1_UDB05_ACTL 0x40006595 -#define CYREG_B1_UDB06_ACTL 0x40006596 -#define CYREG_B1_UDB07_ACTL 0x40006597 -#define CYREG_B1_UDB08_ACTL 0x40006598 -#define CYREG_B1_UDB09_ACTL 0x40006599 -#define CYREG_B1_UDB10_ACTL 0x4000659a -#define CYREG_B1_UDB11_ACTL 0x4000659b -#define CYREG_B1_UDB04_MC 0x400065a4 -#define CYREG_B1_UDB05_MC 0x400065a5 -#define CYREG_B1_UDB06_MC 0x400065a6 -#define CYREG_B1_UDB07_MC 0x400065a7 -#define CYREG_B1_UDB08_MC 0x400065a8 -#define CYREG_B1_UDB09_MC 0x400065a9 -#define CYREG_B1_UDB10_MC 0x400065aa -#define CYREG_B1_UDB11_MC 0x400065ab -#define CYDEV_UWRK_UWRK16_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 -#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 -#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 -#define CYREG_B0_UDB00_A0_A1 0x40006800 -#define CYREG_B0_UDB01_A0_A1 0x40006802 -#define CYREG_B0_UDB02_A0_A1 0x40006804 -#define CYREG_B0_UDB03_A0_A1 0x40006806 -#define CYREG_B0_UDB04_A0_A1 0x40006808 -#define CYREG_B0_UDB05_A0_A1 0x4000680a -#define CYREG_B0_UDB06_A0_A1 0x4000680c -#define CYREG_B0_UDB07_A0_A1 0x4000680e -#define CYREG_B0_UDB08_A0_A1 0x40006810 -#define CYREG_B0_UDB09_A0_A1 0x40006812 -#define CYREG_B0_UDB10_A0_A1 0x40006814 -#define CYREG_B0_UDB11_A0_A1 0x40006816 -#define CYREG_B0_UDB12_A0_A1 0x40006818 -#define CYREG_B0_UDB13_A0_A1 0x4000681a -#define CYREG_B0_UDB14_A0_A1 0x4000681c -#define CYREG_B0_UDB15_A0_A1 0x4000681e -#define CYREG_B0_UDB00_D0_D1 0x40006840 -#define CYREG_B0_UDB01_D0_D1 0x40006842 -#define CYREG_B0_UDB02_D0_D1 0x40006844 -#define CYREG_B0_UDB03_D0_D1 0x40006846 -#define CYREG_B0_UDB04_D0_D1 0x40006848 -#define CYREG_B0_UDB05_D0_D1 0x4000684a -#define CYREG_B0_UDB06_D0_D1 0x4000684c -#define CYREG_B0_UDB07_D0_D1 0x4000684e -#define CYREG_B0_UDB08_D0_D1 0x40006850 -#define CYREG_B0_UDB09_D0_D1 0x40006852 -#define CYREG_B0_UDB10_D0_D1 0x40006854 -#define CYREG_B0_UDB11_D0_D1 0x40006856 -#define CYREG_B0_UDB12_D0_D1 0x40006858 -#define CYREG_B0_UDB13_D0_D1 0x4000685a -#define CYREG_B0_UDB14_D0_D1 0x4000685c -#define CYREG_B0_UDB15_D0_D1 0x4000685e -#define CYREG_B0_UDB00_F0_F1 0x40006880 -#define CYREG_B0_UDB01_F0_F1 0x40006882 -#define CYREG_B0_UDB02_F0_F1 0x40006884 -#define CYREG_B0_UDB03_F0_F1 0x40006886 -#define CYREG_B0_UDB04_F0_F1 0x40006888 -#define CYREG_B0_UDB05_F0_F1 0x4000688a -#define CYREG_B0_UDB06_F0_F1 0x4000688c -#define CYREG_B0_UDB07_F0_F1 0x4000688e -#define CYREG_B0_UDB08_F0_F1 0x40006890 -#define CYREG_B0_UDB09_F0_F1 0x40006892 -#define CYREG_B0_UDB10_F0_F1 0x40006894 -#define CYREG_B0_UDB11_F0_F1 0x40006896 -#define CYREG_B0_UDB12_F0_F1 0x40006898 -#define CYREG_B0_UDB13_F0_F1 0x4000689a -#define CYREG_B0_UDB14_F0_F1 0x4000689c -#define CYREG_B0_UDB15_F0_F1 0x4000689e -#define CYREG_B0_UDB00_ST_CTL 0x400068c0 -#define CYREG_B0_UDB01_ST_CTL 0x400068c2 -#define CYREG_B0_UDB02_ST_CTL 0x400068c4 -#define CYREG_B0_UDB03_ST_CTL 0x400068c6 -#define CYREG_B0_UDB04_ST_CTL 0x400068c8 -#define CYREG_B0_UDB05_ST_CTL 0x400068ca -#define CYREG_B0_UDB06_ST_CTL 0x400068cc -#define CYREG_B0_UDB07_ST_CTL 0x400068ce -#define CYREG_B0_UDB08_ST_CTL 0x400068d0 -#define CYREG_B0_UDB09_ST_CTL 0x400068d2 -#define CYREG_B0_UDB10_ST_CTL 0x400068d4 -#define CYREG_B0_UDB11_ST_CTL 0x400068d6 -#define CYREG_B0_UDB12_ST_CTL 0x400068d8 -#define CYREG_B0_UDB13_ST_CTL 0x400068da -#define CYREG_B0_UDB14_ST_CTL 0x400068dc -#define CYREG_B0_UDB15_ST_CTL 0x400068de -#define CYREG_B0_UDB00_MSK_ACTL 0x40006900 -#define CYREG_B0_UDB01_MSK_ACTL 0x40006902 -#define CYREG_B0_UDB02_MSK_ACTL 0x40006904 -#define CYREG_B0_UDB03_MSK_ACTL 0x40006906 -#define CYREG_B0_UDB04_MSK_ACTL 0x40006908 -#define CYREG_B0_UDB05_MSK_ACTL 0x4000690a -#define CYREG_B0_UDB06_MSK_ACTL 0x4000690c -#define CYREG_B0_UDB07_MSK_ACTL 0x4000690e -#define CYREG_B0_UDB08_MSK_ACTL 0x40006910 -#define CYREG_B0_UDB09_MSK_ACTL 0x40006912 -#define CYREG_B0_UDB10_MSK_ACTL 0x40006914 -#define CYREG_B0_UDB11_MSK_ACTL 0x40006916 -#define CYREG_B0_UDB12_MSK_ACTL 0x40006918 -#define CYREG_B0_UDB13_MSK_ACTL 0x4000691a -#define CYREG_B0_UDB14_MSK_ACTL 0x4000691c -#define CYREG_B0_UDB15_MSK_ACTL 0x4000691e -#define CYREG_B0_UDB00_MC_00 0x40006940 -#define CYREG_B0_UDB01_MC_00 0x40006942 -#define CYREG_B0_UDB02_MC_00 0x40006944 -#define CYREG_B0_UDB03_MC_00 0x40006946 -#define CYREG_B0_UDB04_MC_00 0x40006948 -#define CYREG_B0_UDB05_MC_00 0x4000694a -#define CYREG_B0_UDB06_MC_00 0x4000694c -#define CYREG_B0_UDB07_MC_00 0x4000694e -#define CYREG_B0_UDB08_MC_00 0x40006950 -#define CYREG_B0_UDB09_MC_00 0x40006952 -#define CYREG_B0_UDB10_MC_00 0x40006954 -#define CYREG_B0_UDB11_MC_00 0x40006956 -#define CYREG_B0_UDB12_MC_00 0x40006958 -#define CYREG_B0_UDB13_MC_00 0x4000695a -#define CYREG_B0_UDB14_MC_00 0x4000695c -#define CYREG_B0_UDB15_MC_00 0x4000695e -#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 -#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 -#define CYREG_B1_UDB04_A0_A1 0x40006a08 -#define CYREG_B1_UDB05_A0_A1 0x40006a0a -#define CYREG_B1_UDB06_A0_A1 0x40006a0c -#define CYREG_B1_UDB07_A0_A1 0x40006a0e -#define CYREG_B1_UDB08_A0_A1 0x40006a10 -#define CYREG_B1_UDB09_A0_A1 0x40006a12 -#define CYREG_B1_UDB10_A0_A1 0x40006a14 -#define CYREG_B1_UDB11_A0_A1 0x40006a16 -#define CYREG_B1_UDB04_D0_D1 0x40006a48 -#define CYREG_B1_UDB05_D0_D1 0x40006a4a -#define CYREG_B1_UDB06_D0_D1 0x40006a4c -#define CYREG_B1_UDB07_D0_D1 0x40006a4e -#define CYREG_B1_UDB08_D0_D1 0x40006a50 -#define CYREG_B1_UDB09_D0_D1 0x40006a52 -#define CYREG_B1_UDB10_D0_D1 0x40006a54 -#define CYREG_B1_UDB11_D0_D1 0x40006a56 -#define CYREG_B1_UDB04_F0_F1 0x40006a88 -#define CYREG_B1_UDB05_F0_F1 0x40006a8a -#define CYREG_B1_UDB06_F0_F1 0x40006a8c -#define CYREG_B1_UDB07_F0_F1 0x40006a8e -#define CYREG_B1_UDB08_F0_F1 0x40006a90 -#define CYREG_B1_UDB09_F0_F1 0x40006a92 -#define CYREG_B1_UDB10_F0_F1 0x40006a94 -#define CYREG_B1_UDB11_F0_F1 0x40006a96 -#define CYREG_B1_UDB04_ST_CTL 0x40006ac8 -#define CYREG_B1_UDB05_ST_CTL 0x40006aca -#define CYREG_B1_UDB06_ST_CTL 0x40006acc -#define CYREG_B1_UDB07_ST_CTL 0x40006ace -#define CYREG_B1_UDB08_ST_CTL 0x40006ad0 -#define CYREG_B1_UDB09_ST_CTL 0x40006ad2 -#define CYREG_B1_UDB10_ST_CTL 0x40006ad4 -#define CYREG_B1_UDB11_ST_CTL 0x40006ad6 -#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08 -#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0a -#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0c -#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0e -#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10 -#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12 -#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14 -#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16 -#define CYREG_B1_UDB04_MC_00 0x40006b48 -#define CYREG_B1_UDB05_MC_00 0x40006b4a -#define CYREG_B1_UDB06_MC_00 0x40006b4c -#define CYREG_B1_UDB07_MC_00 0x40006b4e -#define CYREG_B1_UDB08_MC_00 0x40006b50 -#define CYREG_B1_UDB09_MC_00 0x40006b52 -#define CYREG_B1_UDB10_MC_00 0x40006b54 -#define CYREG_B1_UDB11_MC_00 0x40006b56 -#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e -#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 -#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e -#define CYREG_B0_UDB00_01_A0 0x40006800 -#define CYREG_B0_UDB01_02_A0 0x40006802 -#define CYREG_B0_UDB02_03_A0 0x40006804 -#define CYREG_B0_UDB03_04_A0 0x40006806 -#define CYREG_B0_UDB04_05_A0 0x40006808 -#define CYREG_B0_UDB05_06_A0 0x4000680a -#define CYREG_B0_UDB06_07_A0 0x4000680c -#define CYREG_B0_UDB07_08_A0 0x4000680e -#define CYREG_B0_UDB08_09_A0 0x40006810 -#define CYREG_B0_UDB09_10_A0 0x40006812 -#define CYREG_B0_UDB10_11_A0 0x40006814 -#define CYREG_B0_UDB11_12_A0 0x40006816 -#define CYREG_B0_UDB12_13_A0 0x40006818 -#define CYREG_B0_UDB13_14_A0 0x4000681a -#define CYREG_B0_UDB14_15_A0 0x4000681c -#define CYREG_B0_UDB00_01_A1 0x40006820 -#define CYREG_B0_UDB01_02_A1 0x40006822 -#define CYREG_B0_UDB02_03_A1 0x40006824 -#define CYREG_B0_UDB03_04_A1 0x40006826 -#define CYREG_B0_UDB04_05_A1 0x40006828 -#define CYREG_B0_UDB05_06_A1 0x4000682a -#define CYREG_B0_UDB06_07_A1 0x4000682c -#define CYREG_B0_UDB07_08_A1 0x4000682e -#define CYREG_B0_UDB08_09_A1 0x40006830 -#define CYREG_B0_UDB09_10_A1 0x40006832 -#define CYREG_B0_UDB10_11_A1 0x40006834 -#define CYREG_B0_UDB11_12_A1 0x40006836 -#define CYREG_B0_UDB12_13_A1 0x40006838 -#define CYREG_B0_UDB13_14_A1 0x4000683a -#define CYREG_B0_UDB14_15_A1 0x4000683c -#define CYREG_B0_UDB00_01_D0 0x40006840 -#define CYREG_B0_UDB01_02_D0 0x40006842 -#define CYREG_B0_UDB02_03_D0 0x40006844 -#define CYREG_B0_UDB03_04_D0 0x40006846 -#define CYREG_B0_UDB04_05_D0 0x40006848 -#define CYREG_B0_UDB05_06_D0 0x4000684a -#define CYREG_B0_UDB06_07_D0 0x4000684c -#define CYREG_B0_UDB07_08_D0 0x4000684e -#define CYREG_B0_UDB08_09_D0 0x40006850 -#define CYREG_B0_UDB09_10_D0 0x40006852 -#define CYREG_B0_UDB10_11_D0 0x40006854 -#define CYREG_B0_UDB11_12_D0 0x40006856 -#define CYREG_B0_UDB12_13_D0 0x40006858 -#define CYREG_B0_UDB13_14_D0 0x4000685a -#define CYREG_B0_UDB14_15_D0 0x4000685c -#define CYREG_B0_UDB00_01_D1 0x40006860 -#define CYREG_B0_UDB01_02_D1 0x40006862 -#define CYREG_B0_UDB02_03_D1 0x40006864 -#define CYREG_B0_UDB03_04_D1 0x40006866 -#define CYREG_B0_UDB04_05_D1 0x40006868 -#define CYREG_B0_UDB05_06_D1 0x4000686a -#define CYREG_B0_UDB06_07_D1 0x4000686c -#define CYREG_B0_UDB07_08_D1 0x4000686e -#define CYREG_B0_UDB08_09_D1 0x40006870 -#define CYREG_B0_UDB09_10_D1 0x40006872 -#define CYREG_B0_UDB10_11_D1 0x40006874 -#define CYREG_B0_UDB11_12_D1 0x40006876 -#define CYREG_B0_UDB12_13_D1 0x40006878 -#define CYREG_B0_UDB13_14_D1 0x4000687a -#define CYREG_B0_UDB14_15_D1 0x4000687c -#define CYREG_B0_UDB00_01_F0 0x40006880 -#define CYREG_B0_UDB01_02_F0 0x40006882 -#define CYREG_B0_UDB02_03_F0 0x40006884 -#define CYREG_B0_UDB03_04_F0 0x40006886 -#define CYREG_B0_UDB04_05_F0 0x40006888 -#define CYREG_B0_UDB05_06_F0 0x4000688a -#define CYREG_B0_UDB06_07_F0 0x4000688c -#define CYREG_B0_UDB07_08_F0 0x4000688e -#define CYREG_B0_UDB08_09_F0 0x40006890 -#define CYREG_B0_UDB09_10_F0 0x40006892 -#define CYREG_B0_UDB10_11_F0 0x40006894 -#define CYREG_B0_UDB11_12_F0 0x40006896 -#define CYREG_B0_UDB12_13_F0 0x40006898 -#define CYREG_B0_UDB13_14_F0 0x4000689a -#define CYREG_B0_UDB14_15_F0 0x4000689c -#define CYREG_B0_UDB00_01_F1 0x400068a0 -#define CYREG_B0_UDB01_02_F1 0x400068a2 -#define CYREG_B0_UDB02_03_F1 0x400068a4 -#define CYREG_B0_UDB03_04_F1 0x400068a6 -#define CYREG_B0_UDB04_05_F1 0x400068a8 -#define CYREG_B0_UDB05_06_F1 0x400068aa -#define CYREG_B0_UDB06_07_F1 0x400068ac -#define CYREG_B0_UDB07_08_F1 0x400068ae -#define CYREG_B0_UDB08_09_F1 0x400068b0 -#define CYREG_B0_UDB09_10_F1 0x400068b2 -#define CYREG_B0_UDB10_11_F1 0x400068b4 -#define CYREG_B0_UDB11_12_F1 0x400068b6 -#define CYREG_B0_UDB12_13_F1 0x400068b8 -#define CYREG_B0_UDB13_14_F1 0x400068ba -#define CYREG_B0_UDB14_15_F1 0x400068bc -#define CYREG_B0_UDB00_01_ST 0x400068c0 -#define CYREG_B0_UDB01_02_ST 0x400068c2 -#define CYREG_B0_UDB02_03_ST 0x400068c4 -#define CYREG_B0_UDB03_04_ST 0x400068c6 -#define CYREG_B0_UDB04_05_ST 0x400068c8 -#define CYREG_B0_UDB05_06_ST 0x400068ca -#define CYREG_B0_UDB06_07_ST 0x400068cc -#define CYREG_B0_UDB07_08_ST 0x400068ce -#define CYREG_B0_UDB08_09_ST 0x400068d0 -#define CYREG_B0_UDB09_10_ST 0x400068d2 -#define CYREG_B0_UDB10_11_ST 0x400068d4 -#define CYREG_B0_UDB11_12_ST 0x400068d6 -#define CYREG_B0_UDB12_13_ST 0x400068d8 -#define CYREG_B0_UDB13_14_ST 0x400068da -#define CYREG_B0_UDB14_15_ST 0x400068dc -#define CYREG_B0_UDB00_01_CTL 0x400068e0 -#define CYREG_B0_UDB01_02_CTL 0x400068e2 -#define CYREG_B0_UDB02_03_CTL 0x400068e4 -#define CYREG_B0_UDB03_04_CTL 0x400068e6 -#define CYREG_B0_UDB04_05_CTL 0x400068e8 -#define CYREG_B0_UDB05_06_CTL 0x400068ea -#define CYREG_B0_UDB06_07_CTL 0x400068ec -#define CYREG_B0_UDB07_08_CTL 0x400068ee -#define CYREG_B0_UDB08_09_CTL 0x400068f0 -#define CYREG_B0_UDB09_10_CTL 0x400068f2 -#define CYREG_B0_UDB10_11_CTL 0x400068f4 -#define CYREG_B0_UDB11_12_CTL 0x400068f6 -#define CYREG_B0_UDB12_13_CTL 0x400068f8 -#define CYREG_B0_UDB13_14_CTL 0x400068fa -#define CYREG_B0_UDB14_15_CTL 0x400068fc -#define CYREG_B0_UDB00_01_MSK 0x40006900 -#define CYREG_B0_UDB01_02_MSK 0x40006902 -#define CYREG_B0_UDB02_03_MSK 0x40006904 -#define CYREG_B0_UDB03_04_MSK 0x40006906 -#define CYREG_B0_UDB04_05_MSK 0x40006908 -#define CYREG_B0_UDB05_06_MSK 0x4000690a -#define CYREG_B0_UDB06_07_MSK 0x4000690c -#define CYREG_B0_UDB07_08_MSK 0x4000690e -#define CYREG_B0_UDB08_09_MSK 0x40006910 -#define CYREG_B0_UDB09_10_MSK 0x40006912 -#define CYREG_B0_UDB10_11_MSK 0x40006914 -#define CYREG_B0_UDB11_12_MSK 0x40006916 -#define CYREG_B0_UDB12_13_MSK 0x40006918 -#define CYREG_B0_UDB13_14_MSK 0x4000691a -#define CYREG_B0_UDB14_15_MSK 0x4000691c -#define CYREG_B0_UDB00_01_ACTL 0x40006920 -#define CYREG_B0_UDB01_02_ACTL 0x40006922 -#define CYREG_B0_UDB02_03_ACTL 0x40006924 -#define CYREG_B0_UDB03_04_ACTL 0x40006926 -#define CYREG_B0_UDB04_05_ACTL 0x40006928 -#define CYREG_B0_UDB05_06_ACTL 0x4000692a -#define CYREG_B0_UDB06_07_ACTL 0x4000692c -#define CYREG_B0_UDB07_08_ACTL 0x4000692e -#define CYREG_B0_UDB08_09_ACTL 0x40006930 -#define CYREG_B0_UDB09_10_ACTL 0x40006932 -#define CYREG_B0_UDB10_11_ACTL 0x40006934 -#define CYREG_B0_UDB11_12_ACTL 0x40006936 -#define CYREG_B0_UDB12_13_ACTL 0x40006938 -#define CYREG_B0_UDB13_14_ACTL 0x4000693a -#define CYREG_B0_UDB14_15_ACTL 0x4000693c -#define CYREG_B0_UDB00_01_MC 0x40006940 -#define CYREG_B0_UDB01_02_MC 0x40006942 -#define CYREG_B0_UDB02_03_MC 0x40006944 -#define CYREG_B0_UDB03_04_MC 0x40006946 -#define CYREG_B0_UDB04_05_MC 0x40006948 -#define CYREG_B0_UDB05_06_MC 0x4000694a -#define CYREG_B0_UDB06_07_MC 0x4000694c -#define CYREG_B0_UDB07_08_MC 0x4000694e -#define CYREG_B0_UDB08_09_MC 0x40006950 -#define CYREG_B0_UDB09_10_MC 0x40006952 -#define CYREG_B0_UDB10_11_MC 0x40006954 -#define CYREG_B0_UDB11_12_MC 0x40006956 -#define CYREG_B0_UDB12_13_MC 0x40006958 -#define CYREG_B0_UDB13_14_MC 0x4000695a -#define CYREG_B0_UDB14_15_MC 0x4000695c -#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 -#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e -#define CYREG_B1_UDB04_05_A0 0x40006a08 -#define CYREG_B1_UDB05_06_A0 0x40006a0a -#define CYREG_B1_UDB06_07_A0 0x40006a0c -#define CYREG_B1_UDB07_08_A0 0x40006a0e -#define CYREG_B1_UDB08_09_A0 0x40006a10 -#define CYREG_B1_UDB09_10_A0 0x40006a12 -#define CYREG_B1_UDB10_11_A0 0x40006a14 -#define CYREG_B1_UDB11_12_A0 0x40006a16 -#define CYREG_B1_UDB04_05_A1 0x40006a28 -#define CYREG_B1_UDB05_06_A1 0x40006a2a -#define CYREG_B1_UDB06_07_A1 0x40006a2c -#define CYREG_B1_UDB07_08_A1 0x40006a2e -#define CYREG_B1_UDB08_09_A1 0x40006a30 -#define CYREG_B1_UDB09_10_A1 0x40006a32 -#define CYREG_B1_UDB10_11_A1 0x40006a34 -#define CYREG_B1_UDB11_12_A1 0x40006a36 -#define CYREG_B1_UDB04_05_D0 0x40006a48 -#define CYREG_B1_UDB05_06_D0 0x40006a4a -#define CYREG_B1_UDB06_07_D0 0x40006a4c -#define CYREG_B1_UDB07_08_D0 0x40006a4e -#define CYREG_B1_UDB08_09_D0 0x40006a50 -#define CYREG_B1_UDB09_10_D0 0x40006a52 -#define CYREG_B1_UDB10_11_D0 0x40006a54 -#define CYREG_B1_UDB11_12_D0 0x40006a56 -#define CYREG_B1_UDB04_05_D1 0x40006a68 -#define CYREG_B1_UDB05_06_D1 0x40006a6a -#define CYREG_B1_UDB06_07_D1 0x40006a6c -#define CYREG_B1_UDB07_08_D1 0x40006a6e -#define CYREG_B1_UDB08_09_D1 0x40006a70 -#define CYREG_B1_UDB09_10_D1 0x40006a72 -#define CYREG_B1_UDB10_11_D1 0x40006a74 -#define CYREG_B1_UDB11_12_D1 0x40006a76 -#define CYREG_B1_UDB04_05_F0 0x40006a88 -#define CYREG_B1_UDB05_06_F0 0x40006a8a -#define CYREG_B1_UDB06_07_F0 0x40006a8c -#define CYREG_B1_UDB07_08_F0 0x40006a8e -#define CYREG_B1_UDB08_09_F0 0x40006a90 -#define CYREG_B1_UDB09_10_F0 0x40006a92 -#define CYREG_B1_UDB10_11_F0 0x40006a94 -#define CYREG_B1_UDB11_12_F0 0x40006a96 -#define CYREG_B1_UDB04_05_F1 0x40006aa8 -#define CYREG_B1_UDB05_06_F1 0x40006aaa -#define CYREG_B1_UDB06_07_F1 0x40006aac -#define CYREG_B1_UDB07_08_F1 0x40006aae -#define CYREG_B1_UDB08_09_F1 0x40006ab0 -#define CYREG_B1_UDB09_10_F1 0x40006ab2 -#define CYREG_B1_UDB10_11_F1 0x40006ab4 -#define CYREG_B1_UDB11_12_F1 0x40006ab6 -#define CYREG_B1_UDB04_05_ST 0x40006ac8 -#define CYREG_B1_UDB05_06_ST 0x40006aca -#define CYREG_B1_UDB06_07_ST 0x40006acc -#define CYREG_B1_UDB07_08_ST 0x40006ace -#define CYREG_B1_UDB08_09_ST 0x40006ad0 -#define CYREG_B1_UDB09_10_ST 0x40006ad2 -#define CYREG_B1_UDB10_11_ST 0x40006ad4 -#define CYREG_B1_UDB11_12_ST 0x40006ad6 -#define CYREG_B1_UDB04_05_CTL 0x40006ae8 -#define CYREG_B1_UDB05_06_CTL 0x40006aea -#define CYREG_B1_UDB06_07_CTL 0x40006aec -#define CYREG_B1_UDB07_08_CTL 0x40006aee -#define CYREG_B1_UDB08_09_CTL 0x40006af0 -#define CYREG_B1_UDB09_10_CTL 0x40006af2 -#define CYREG_B1_UDB10_11_CTL 0x40006af4 -#define CYREG_B1_UDB11_12_CTL 0x40006af6 -#define CYREG_B1_UDB04_05_MSK 0x40006b08 -#define CYREG_B1_UDB05_06_MSK 0x40006b0a -#define CYREG_B1_UDB06_07_MSK 0x40006b0c -#define CYREG_B1_UDB07_08_MSK 0x40006b0e -#define CYREG_B1_UDB08_09_MSK 0x40006b10 -#define CYREG_B1_UDB09_10_MSK 0x40006b12 -#define CYREG_B1_UDB10_11_MSK 0x40006b14 -#define CYREG_B1_UDB11_12_MSK 0x40006b16 -#define CYREG_B1_UDB04_05_ACTL 0x40006b28 -#define CYREG_B1_UDB05_06_ACTL 0x40006b2a -#define CYREG_B1_UDB06_07_ACTL 0x40006b2c -#define CYREG_B1_UDB07_08_ACTL 0x40006b2e -#define CYREG_B1_UDB08_09_ACTL 0x40006b30 -#define CYREG_B1_UDB09_10_ACTL 0x40006b32 -#define CYREG_B1_UDB10_11_ACTL 0x40006b34 -#define CYREG_B1_UDB11_12_ACTL 0x40006b36 -#define CYREG_B1_UDB04_05_MC 0x40006b48 -#define CYREG_B1_UDB05_06_MC 0x40006b4a -#define CYREG_B1_UDB06_07_MC 0x40006b4c -#define CYREG_B1_UDB07_08_MC 0x40006b4e -#define CYREG_B1_UDB08_09_MC 0x40006b50 -#define CYREG_B1_UDB09_10_MC 0x40006b52 -#define CYREG_B1_UDB10_11_MC 0x40006b54 -#define CYREG_B1_UDB11_12_MC 0x40006b56 -#define CYDEV_PHUB_BASE 0x40007000 -#define CYDEV_PHUB_SIZE 0x00000c00 -#define CYREG_PHUB_CFG 0x40007000 -#define CYREG_PHUB_ERR 0x40007004 -#define CYREG_PHUB_ERR_ADR 0x40007008 -#define CYDEV_PHUB_CH0_BASE 0x40007010 -#define CYDEV_PHUB_CH0_SIZE 0x0000000c -#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010 -#define CYREG_PHUB_CH0_ACTION 0x40007014 -#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018 -#define CYDEV_PHUB_CH1_BASE 0x40007020 -#define CYDEV_PHUB_CH1_SIZE 0x0000000c -#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020 -#define CYREG_PHUB_CH1_ACTION 0x40007024 -#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028 -#define CYDEV_PHUB_CH2_BASE 0x40007030 -#define CYDEV_PHUB_CH2_SIZE 0x0000000c -#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030 -#define CYREG_PHUB_CH2_ACTION 0x40007034 -#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038 -#define CYDEV_PHUB_CH3_BASE 0x40007040 -#define CYDEV_PHUB_CH3_SIZE 0x0000000c -#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040 -#define CYREG_PHUB_CH3_ACTION 0x40007044 -#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048 -#define CYDEV_PHUB_CH4_BASE 0x40007050 -#define CYDEV_PHUB_CH4_SIZE 0x0000000c -#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050 -#define CYREG_PHUB_CH4_ACTION 0x40007054 -#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058 -#define CYDEV_PHUB_CH5_BASE 0x40007060 -#define CYDEV_PHUB_CH5_SIZE 0x0000000c -#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060 -#define CYREG_PHUB_CH5_ACTION 0x40007064 -#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068 -#define CYDEV_PHUB_CH6_BASE 0x40007070 -#define CYDEV_PHUB_CH6_SIZE 0x0000000c -#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070 -#define CYREG_PHUB_CH6_ACTION 0x40007074 -#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078 -#define CYDEV_PHUB_CH7_BASE 0x40007080 -#define CYDEV_PHUB_CH7_SIZE 0x0000000c -#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080 -#define CYREG_PHUB_CH7_ACTION 0x40007084 -#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088 -#define CYDEV_PHUB_CH8_BASE 0x40007090 -#define CYDEV_PHUB_CH8_SIZE 0x0000000c -#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090 -#define CYREG_PHUB_CH8_ACTION 0x40007094 -#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098 -#define CYDEV_PHUB_CH9_BASE 0x400070a0 -#define CYDEV_PHUB_CH9_SIZE 0x0000000c -#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0 -#define CYREG_PHUB_CH9_ACTION 0x400070a4 -#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8 -#define CYDEV_PHUB_CH10_BASE 0x400070b0 -#define CYDEV_PHUB_CH10_SIZE 0x0000000c -#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0 -#define CYREG_PHUB_CH10_ACTION 0x400070b4 -#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8 -#define CYDEV_PHUB_CH11_BASE 0x400070c0 -#define CYDEV_PHUB_CH11_SIZE 0x0000000c -#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0 -#define CYREG_PHUB_CH11_ACTION 0x400070c4 -#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8 -#define CYDEV_PHUB_CH12_BASE 0x400070d0 -#define CYDEV_PHUB_CH12_SIZE 0x0000000c -#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0 -#define CYREG_PHUB_CH12_ACTION 0x400070d4 -#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8 -#define CYDEV_PHUB_CH13_BASE 0x400070e0 -#define CYDEV_PHUB_CH13_SIZE 0x0000000c -#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0 -#define CYREG_PHUB_CH13_ACTION 0x400070e4 -#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8 -#define CYDEV_PHUB_CH14_BASE 0x400070f0 -#define CYDEV_PHUB_CH14_SIZE 0x0000000c -#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0 -#define CYREG_PHUB_CH14_ACTION 0x400070f4 -#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8 -#define CYDEV_PHUB_CH15_BASE 0x40007100 -#define CYDEV_PHUB_CH15_SIZE 0x0000000c -#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100 -#define CYREG_PHUB_CH15_ACTION 0x40007104 -#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108 -#define CYDEV_PHUB_CH16_BASE 0x40007110 -#define CYDEV_PHUB_CH16_SIZE 0x0000000c -#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110 -#define CYREG_PHUB_CH16_ACTION 0x40007114 -#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118 -#define CYDEV_PHUB_CH17_BASE 0x40007120 -#define CYDEV_PHUB_CH17_SIZE 0x0000000c -#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120 -#define CYREG_PHUB_CH17_ACTION 0x40007124 -#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128 -#define CYDEV_PHUB_CH18_BASE 0x40007130 -#define CYDEV_PHUB_CH18_SIZE 0x0000000c -#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130 -#define CYREG_PHUB_CH18_ACTION 0x40007134 -#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138 -#define CYDEV_PHUB_CH19_BASE 0x40007140 -#define CYDEV_PHUB_CH19_SIZE 0x0000000c -#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140 -#define CYREG_PHUB_CH19_ACTION 0x40007144 -#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148 -#define CYDEV_PHUB_CH20_BASE 0x40007150 -#define CYDEV_PHUB_CH20_SIZE 0x0000000c -#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150 -#define CYREG_PHUB_CH20_ACTION 0x40007154 -#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158 -#define CYDEV_PHUB_CH21_BASE 0x40007160 -#define CYDEV_PHUB_CH21_SIZE 0x0000000c -#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160 -#define CYREG_PHUB_CH21_ACTION 0x40007164 -#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168 -#define CYDEV_PHUB_CH22_BASE 0x40007170 -#define CYDEV_PHUB_CH22_SIZE 0x0000000c -#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170 -#define CYREG_PHUB_CH22_ACTION 0x40007174 -#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178 -#define CYDEV_PHUB_CH23_BASE 0x40007180 -#define CYDEV_PHUB_CH23_SIZE 0x0000000c -#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180 -#define CYREG_PHUB_CH23_ACTION 0x40007184 -#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188 -#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 -#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600 -#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604 -#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 -#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608 -#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760c -#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 -#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610 -#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614 -#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 -#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618 -#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761c -#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 -#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620 -#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624 -#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 -#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628 -#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762c -#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 -#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630 -#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634 -#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 -#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638 -#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763c -#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 -#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640 -#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644 -#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 -#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648 -#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764c -#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 -#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650 -#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654 -#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 -#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658 -#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765c -#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 -#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660 -#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664 -#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 -#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668 -#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766c -#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 -#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670 -#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674 -#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 -#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678 -#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767c -#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 -#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680 -#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684 -#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 -#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688 -#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768c -#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 -#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690 -#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694 -#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 -#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698 -#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769c -#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 -#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0 -#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4 -#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 -#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8 -#define CYREG_PHUB_CFGMEM21_CFG1 0x400076ac -#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 -#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0 -#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4 -#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 -#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 -#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8 -#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bc -#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 -#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800 -#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804 -#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 -#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808 -#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780c -#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 -#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810 -#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814 -#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 -#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818 -#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781c -#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 -#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820 -#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824 -#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 -#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828 -#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782c -#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 -#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830 -#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834 -#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 -#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838 -#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783c -#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 -#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840 -#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844 -#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 -#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848 -#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784c -#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 -#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850 -#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854 -#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 -#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858 -#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785c -#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 -#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860 -#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864 -#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 -#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868 -#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786c -#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 -#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870 -#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874 -#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 -#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878 -#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787c -#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 -#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880 -#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884 -#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 -#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888 -#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788c -#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 -#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890 -#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894 -#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 -#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898 -#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789c -#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 -#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0 -#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4 -#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 -#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8 -#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078ac -#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 -#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0 -#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4 -#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 -#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8 -#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bc -#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 -#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0 -#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4 -#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 -#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8 -#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078cc -#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 -#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0 -#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4 -#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 -#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8 -#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dc -#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 -#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0 -#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4 -#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 -#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8 -#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ec -#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 -#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0 -#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4 -#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 -#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8 -#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fc -#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 -#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900 -#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904 -#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 -#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908 -#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790c -#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 -#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910 -#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914 -#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 -#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918 -#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791c -#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 -#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920 -#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924 -#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 -#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928 -#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792c -#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 -#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930 -#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934 -#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 -#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938 -#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793c -#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 -#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940 -#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944 -#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 -#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948 -#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794c -#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 -#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950 -#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954 -#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 -#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958 -#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795c -#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 -#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960 -#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964 -#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 -#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968 -#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796c -#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 -#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970 -#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974 -#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 -#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978 -#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797c -#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 -#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980 -#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984 -#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 -#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988 -#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798c -#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 -#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990 -#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994 -#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 -#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998 -#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799c -#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 -#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0 -#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4 -#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 -#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8 -#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079ac -#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 -#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0 -#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4 -#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 -#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8 -#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bc -#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 -#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0 -#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4 -#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 -#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8 -#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079cc -#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 -#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0 -#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4 -#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 -#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8 -#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dc -#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 -#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0 -#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4 -#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 -#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8 -#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ec -#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 -#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0 -#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4 -#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 -#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8 -#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fc -#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 -#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00 -#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04 -#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 -#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08 -#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0c -#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 -#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10 -#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14 -#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 -#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18 -#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1c -#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 -#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20 -#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24 -#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 -#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28 -#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2c -#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 -#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30 -#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34 -#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 -#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38 -#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3c -#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 -#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40 -#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44 -#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 -#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48 -#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4c -#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 -#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50 -#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54 -#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 -#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58 -#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5c -#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 -#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60 -#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64 -#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 -#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68 -#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6c -#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 -#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70 -#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74 -#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 -#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78 -#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7c -#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 -#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80 -#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84 -#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 -#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88 -#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8c -#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 -#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90 -#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94 -#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 -#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98 -#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9c -#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 -#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 -#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 -#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 -#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 -#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aac -#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 -#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 -#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 -#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 -#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 -#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abc -#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 -#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 -#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 -#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 -#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 -#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007acc -#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 -#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 -#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 -#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 -#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 -#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adc -#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 -#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 -#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 -#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 -#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 -#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aec -#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 -#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0 -#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4 -#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 -#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8 -#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afc -#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 -#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00 -#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04 -#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 -#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08 -#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0c -#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 -#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10 -#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14 -#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 -#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18 -#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1c -#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 -#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20 -#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24 -#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 -#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28 -#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2c -#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 -#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30 -#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34 -#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 -#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38 -#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3c -#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 -#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40 -#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44 -#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 -#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48 -#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4c -#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 -#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50 -#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54 -#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 -#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58 -#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5c -#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 -#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60 -#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64 -#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 -#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68 -#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6c -#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 -#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70 -#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74 -#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 -#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78 -#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7c -#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 -#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80 -#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84 -#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 -#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88 -#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8c -#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 -#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90 -#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94 -#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 -#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98 -#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9c -#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 -#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 -#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 -#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 -#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 -#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bac -#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 -#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 -#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 -#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 -#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 -#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbc -#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 -#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 -#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 -#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 -#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 -#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bcc -#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 -#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 -#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 -#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 -#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 -#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdc -#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 -#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0 -#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4 -#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 -#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8 -#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007bec -#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 -#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 -#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 -#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 -#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 -#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 -#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfc -#define CYDEV_EE_BASE 0x40008000 -#define CYDEV_EE_SIZE 0x00000800 -#define CYREG_EE_DATA_MBASE 0x40008000 -#define CYREG_EE_DATA_MSIZE 0x00000800 -#define CYDEV_CAN0_BASE 0x4000a000 -#define CYDEV_CAN0_SIZE 0x000002a0 -#define CYDEV_CAN0_CSR_BASE 0x4000a000 -#define CYDEV_CAN0_CSR_SIZE 0x00000018 -#define CYREG_CAN0_CSR_INT_SR 0x4000a000 -#define CYREG_CAN0_CSR_INT_EN 0x4000a004 -#define CYREG_CAN0_CSR_BUF_SR 0x4000a008 -#define CYREG_CAN0_CSR_ERR_SR 0x4000a00c -#define CYREG_CAN0_CSR_CMD 0x4000a010 -#define CYREG_CAN0_CSR_CFG 0x4000a014 -#define CYDEV_CAN0_TX0_BASE 0x4000a020 -#define CYDEV_CAN0_TX0_SIZE 0x00000010 -#define CYREG_CAN0_TX0_CMD 0x4000a020 -#define CYREG_CAN0_TX0_ID 0x4000a024 -#define CYREG_CAN0_TX0_DH 0x4000a028 -#define CYREG_CAN0_TX0_DL 0x4000a02c -#define CYDEV_CAN0_TX1_BASE 0x4000a030 -#define CYDEV_CAN0_TX1_SIZE 0x00000010 -#define CYREG_CAN0_TX1_CMD 0x4000a030 -#define CYREG_CAN0_TX1_ID 0x4000a034 -#define CYREG_CAN0_TX1_DH 0x4000a038 -#define CYREG_CAN0_TX1_DL 0x4000a03c -#define CYDEV_CAN0_TX2_BASE 0x4000a040 -#define CYDEV_CAN0_TX2_SIZE 0x00000010 -#define CYREG_CAN0_TX2_CMD 0x4000a040 -#define CYREG_CAN0_TX2_ID 0x4000a044 -#define CYREG_CAN0_TX2_DH 0x4000a048 -#define CYREG_CAN0_TX2_DL 0x4000a04c -#define CYDEV_CAN0_TX3_BASE 0x4000a050 -#define CYDEV_CAN0_TX3_SIZE 0x00000010 -#define CYREG_CAN0_TX3_CMD 0x4000a050 -#define CYREG_CAN0_TX3_ID 0x4000a054 -#define CYREG_CAN0_TX3_DH 0x4000a058 -#define CYREG_CAN0_TX3_DL 0x4000a05c -#define CYDEV_CAN0_TX4_BASE 0x4000a060 -#define CYDEV_CAN0_TX4_SIZE 0x00000010 -#define CYREG_CAN0_TX4_CMD 0x4000a060 -#define CYREG_CAN0_TX4_ID 0x4000a064 -#define CYREG_CAN0_TX4_DH 0x4000a068 -#define CYREG_CAN0_TX4_DL 0x4000a06c -#define CYDEV_CAN0_TX5_BASE 0x4000a070 -#define CYDEV_CAN0_TX5_SIZE 0x00000010 -#define CYREG_CAN0_TX5_CMD 0x4000a070 -#define CYREG_CAN0_TX5_ID 0x4000a074 -#define CYREG_CAN0_TX5_DH 0x4000a078 -#define CYREG_CAN0_TX5_DL 0x4000a07c -#define CYDEV_CAN0_TX6_BASE 0x4000a080 -#define CYDEV_CAN0_TX6_SIZE 0x00000010 -#define CYREG_CAN0_TX6_CMD 0x4000a080 -#define CYREG_CAN0_TX6_ID 0x4000a084 -#define CYREG_CAN0_TX6_DH 0x4000a088 -#define CYREG_CAN0_TX6_DL 0x4000a08c -#define CYDEV_CAN0_TX7_BASE 0x4000a090 -#define CYDEV_CAN0_TX7_SIZE 0x00000010 -#define CYREG_CAN0_TX7_CMD 0x4000a090 -#define CYREG_CAN0_TX7_ID 0x4000a094 -#define CYREG_CAN0_TX7_DH 0x4000a098 -#define CYREG_CAN0_TX7_DL 0x4000a09c -#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 -#define CYDEV_CAN0_RX0_SIZE 0x00000020 -#define CYREG_CAN0_RX0_CMD 0x4000a0a0 -#define CYREG_CAN0_RX0_ID 0x4000a0a4 -#define CYREG_CAN0_RX0_DH 0x4000a0a8 -#define CYREG_CAN0_RX0_DL 0x4000a0ac -#define CYREG_CAN0_RX0_AMR 0x4000a0b0 -#define CYREG_CAN0_RX0_ACR 0x4000a0b4 -#define CYREG_CAN0_RX0_AMRD 0x4000a0b8 -#define CYREG_CAN0_RX0_ACRD 0x4000a0bc -#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 -#define CYDEV_CAN0_RX1_SIZE 0x00000020 -#define CYREG_CAN0_RX1_CMD 0x4000a0c0 -#define CYREG_CAN0_RX1_ID 0x4000a0c4 -#define CYREG_CAN0_RX1_DH 0x4000a0c8 -#define CYREG_CAN0_RX1_DL 0x4000a0cc -#define CYREG_CAN0_RX1_AMR 0x4000a0d0 -#define CYREG_CAN0_RX1_ACR 0x4000a0d4 -#define CYREG_CAN0_RX1_AMRD 0x4000a0d8 -#define CYREG_CAN0_RX1_ACRD 0x4000a0dc -#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 -#define CYDEV_CAN0_RX2_SIZE 0x00000020 -#define CYREG_CAN0_RX2_CMD 0x4000a0e0 -#define CYREG_CAN0_RX2_ID 0x4000a0e4 -#define CYREG_CAN0_RX2_DH 0x4000a0e8 -#define CYREG_CAN0_RX2_DL 0x4000a0ec -#define CYREG_CAN0_RX2_AMR 0x4000a0f0 -#define CYREG_CAN0_RX2_ACR 0x4000a0f4 -#define CYREG_CAN0_RX2_AMRD 0x4000a0f8 -#define CYREG_CAN0_RX2_ACRD 0x4000a0fc -#define CYDEV_CAN0_RX3_BASE 0x4000a100 -#define CYDEV_CAN0_RX3_SIZE 0x00000020 -#define CYREG_CAN0_RX3_CMD 0x4000a100 -#define CYREG_CAN0_RX3_ID 0x4000a104 -#define CYREG_CAN0_RX3_DH 0x4000a108 -#define CYREG_CAN0_RX3_DL 0x4000a10c -#define CYREG_CAN0_RX3_AMR 0x4000a110 -#define CYREG_CAN0_RX3_ACR 0x4000a114 -#define CYREG_CAN0_RX3_AMRD 0x4000a118 -#define CYREG_CAN0_RX3_ACRD 0x4000a11c -#define CYDEV_CAN0_RX4_BASE 0x4000a120 -#define CYDEV_CAN0_RX4_SIZE 0x00000020 -#define CYREG_CAN0_RX4_CMD 0x4000a120 -#define CYREG_CAN0_RX4_ID 0x4000a124 -#define CYREG_CAN0_RX4_DH 0x4000a128 -#define CYREG_CAN0_RX4_DL 0x4000a12c -#define CYREG_CAN0_RX4_AMR 0x4000a130 -#define CYREG_CAN0_RX4_ACR 0x4000a134 -#define CYREG_CAN0_RX4_AMRD 0x4000a138 -#define CYREG_CAN0_RX4_ACRD 0x4000a13c -#define CYDEV_CAN0_RX5_BASE 0x4000a140 -#define CYDEV_CAN0_RX5_SIZE 0x00000020 -#define CYREG_CAN0_RX5_CMD 0x4000a140 -#define CYREG_CAN0_RX5_ID 0x4000a144 -#define CYREG_CAN0_RX5_DH 0x4000a148 -#define CYREG_CAN0_RX5_DL 0x4000a14c -#define CYREG_CAN0_RX5_AMR 0x4000a150 -#define CYREG_CAN0_RX5_ACR 0x4000a154 -#define CYREG_CAN0_RX5_AMRD 0x4000a158 -#define CYREG_CAN0_RX5_ACRD 0x4000a15c -#define CYDEV_CAN0_RX6_BASE 0x4000a160 -#define CYDEV_CAN0_RX6_SIZE 0x00000020 -#define CYREG_CAN0_RX6_CMD 0x4000a160 -#define CYREG_CAN0_RX6_ID 0x4000a164 -#define CYREG_CAN0_RX6_DH 0x4000a168 -#define CYREG_CAN0_RX6_DL 0x4000a16c -#define CYREG_CAN0_RX6_AMR 0x4000a170 -#define CYREG_CAN0_RX6_ACR 0x4000a174 -#define CYREG_CAN0_RX6_AMRD 0x4000a178 -#define CYREG_CAN0_RX6_ACRD 0x4000a17c -#define CYDEV_CAN0_RX7_BASE 0x4000a180 -#define CYDEV_CAN0_RX7_SIZE 0x00000020 -#define CYREG_CAN0_RX7_CMD 0x4000a180 -#define CYREG_CAN0_RX7_ID 0x4000a184 -#define CYREG_CAN0_RX7_DH 0x4000a188 -#define CYREG_CAN0_RX7_DL 0x4000a18c -#define CYREG_CAN0_RX7_AMR 0x4000a190 -#define CYREG_CAN0_RX7_ACR 0x4000a194 -#define CYREG_CAN0_RX7_AMRD 0x4000a198 -#define CYREG_CAN0_RX7_ACRD 0x4000a19c -#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 -#define CYDEV_CAN0_RX8_SIZE 0x00000020 -#define CYREG_CAN0_RX8_CMD 0x4000a1a0 -#define CYREG_CAN0_RX8_ID 0x4000a1a4 -#define CYREG_CAN0_RX8_DH 0x4000a1a8 -#define CYREG_CAN0_RX8_DL 0x4000a1ac -#define CYREG_CAN0_RX8_AMR 0x4000a1b0 -#define CYREG_CAN0_RX8_ACR 0x4000a1b4 -#define CYREG_CAN0_RX8_AMRD 0x4000a1b8 -#define CYREG_CAN0_RX8_ACRD 0x4000a1bc -#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 -#define CYDEV_CAN0_RX9_SIZE 0x00000020 -#define CYREG_CAN0_RX9_CMD 0x4000a1c0 -#define CYREG_CAN0_RX9_ID 0x4000a1c4 -#define CYREG_CAN0_RX9_DH 0x4000a1c8 -#define CYREG_CAN0_RX9_DL 0x4000a1cc -#define CYREG_CAN0_RX9_AMR 0x4000a1d0 -#define CYREG_CAN0_RX9_ACR 0x4000a1d4 -#define CYREG_CAN0_RX9_AMRD 0x4000a1d8 -#define CYREG_CAN0_RX9_ACRD 0x4000a1dc -#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 -#define CYDEV_CAN0_RX10_SIZE 0x00000020 -#define CYREG_CAN0_RX10_CMD 0x4000a1e0 -#define CYREG_CAN0_RX10_ID 0x4000a1e4 -#define CYREG_CAN0_RX10_DH 0x4000a1e8 -#define CYREG_CAN0_RX10_DL 0x4000a1ec -#define CYREG_CAN0_RX10_AMR 0x4000a1f0 -#define CYREG_CAN0_RX10_ACR 0x4000a1f4 -#define CYREG_CAN0_RX10_AMRD 0x4000a1f8 -#define CYREG_CAN0_RX10_ACRD 0x4000a1fc -#define CYDEV_CAN0_RX11_BASE 0x4000a200 -#define CYDEV_CAN0_RX11_SIZE 0x00000020 -#define CYREG_CAN0_RX11_CMD 0x4000a200 -#define CYREG_CAN0_RX11_ID 0x4000a204 -#define CYREG_CAN0_RX11_DH 0x4000a208 -#define CYREG_CAN0_RX11_DL 0x4000a20c -#define CYREG_CAN0_RX11_AMR 0x4000a210 -#define CYREG_CAN0_RX11_ACR 0x4000a214 -#define CYREG_CAN0_RX11_AMRD 0x4000a218 -#define CYREG_CAN0_RX11_ACRD 0x4000a21c -#define CYDEV_CAN0_RX12_BASE 0x4000a220 -#define CYDEV_CAN0_RX12_SIZE 0x00000020 -#define CYREG_CAN0_RX12_CMD 0x4000a220 -#define CYREG_CAN0_RX12_ID 0x4000a224 -#define CYREG_CAN0_RX12_DH 0x4000a228 -#define CYREG_CAN0_RX12_DL 0x4000a22c -#define CYREG_CAN0_RX12_AMR 0x4000a230 -#define CYREG_CAN0_RX12_ACR 0x4000a234 -#define CYREG_CAN0_RX12_AMRD 0x4000a238 -#define CYREG_CAN0_RX12_ACRD 0x4000a23c -#define CYDEV_CAN0_RX13_BASE 0x4000a240 -#define CYDEV_CAN0_RX13_SIZE 0x00000020 -#define CYREG_CAN0_RX13_CMD 0x4000a240 -#define CYREG_CAN0_RX13_ID 0x4000a244 -#define CYREG_CAN0_RX13_DH 0x4000a248 -#define CYREG_CAN0_RX13_DL 0x4000a24c -#define CYREG_CAN0_RX13_AMR 0x4000a250 -#define CYREG_CAN0_RX13_ACR 0x4000a254 -#define CYREG_CAN0_RX13_AMRD 0x4000a258 -#define CYREG_CAN0_RX13_ACRD 0x4000a25c -#define CYDEV_CAN0_RX14_BASE 0x4000a260 -#define CYDEV_CAN0_RX14_SIZE 0x00000020 -#define CYREG_CAN0_RX14_CMD 0x4000a260 -#define CYREG_CAN0_RX14_ID 0x4000a264 -#define CYREG_CAN0_RX14_DH 0x4000a268 -#define CYREG_CAN0_RX14_DL 0x4000a26c -#define CYREG_CAN0_RX14_AMR 0x4000a270 -#define CYREG_CAN0_RX14_ACR 0x4000a274 -#define CYREG_CAN0_RX14_AMRD 0x4000a278 -#define CYREG_CAN0_RX14_ACRD 0x4000a27c -#define CYDEV_CAN0_RX15_BASE 0x4000a280 -#define CYDEV_CAN0_RX15_SIZE 0x00000020 -#define CYREG_CAN0_RX15_CMD 0x4000a280 -#define CYREG_CAN0_RX15_ID 0x4000a284 -#define CYREG_CAN0_RX15_DH 0x4000a288 -#define CYREG_CAN0_RX15_DL 0x4000a28c -#define CYREG_CAN0_RX15_AMR 0x4000a290 -#define CYREG_CAN0_RX15_ACR 0x4000a294 -#define CYREG_CAN0_RX15_AMRD 0x4000a298 -#define CYREG_CAN0_RX15_ACRD 0x4000a29c -#define CYDEV_DFB0_BASE 0x4000c000 -#define CYDEV_DFB0_SIZE 0x000007b5 -#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 -#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 -#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 -#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 -#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 -#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 -#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 -#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 -#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 -#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 -#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 -#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 -#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 -#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 -#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 -#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 -#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 -#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 -#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 -#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 -#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 -#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 -#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 -#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 -#define CYREG_DFB0_CR 0x4000c780 -#define CYREG_DFB0_SR 0x4000c784 -#define CYREG_DFB0_RAM_EN 0x4000c788 -#define CYREG_DFB0_RAM_DIR 0x4000c78c -#define CYREG_DFB0_SEMA 0x4000c790 -#define CYREG_DFB0_DSI_CTRL 0x4000c794 -#define CYREG_DFB0_INT_CTRL 0x4000c798 -#define CYREG_DFB0_DMA_CTRL 0x4000c79c -#define CYREG_DFB0_STAGEA 0x4000c7a0 -#define CYREG_DFB0_STAGEAM 0x4000c7a1 -#define CYREG_DFB0_STAGEAH 0x4000c7a2 -#define CYREG_DFB0_STAGEB 0x4000c7a4 -#define CYREG_DFB0_STAGEBM 0x4000c7a5 -#define CYREG_DFB0_STAGEBH 0x4000c7a6 -#define CYREG_DFB0_HOLDA 0x4000c7a8 -#define CYREG_DFB0_HOLDAM 0x4000c7a9 -#define CYREG_DFB0_HOLDAH 0x4000c7aa -#define CYREG_DFB0_HOLDAS 0x4000c7ab -#define CYREG_DFB0_HOLDB 0x4000c7ac -#define CYREG_DFB0_HOLDBM 0x4000c7ad -#define CYREG_DFB0_HOLDBH 0x4000c7ae -#define CYREG_DFB0_HOLDBS 0x4000c7af -#define CYREG_DFB0_COHER 0x4000c7b0 -#define CYREG_DFB0_DALIGN 0x4000c7b4 -#define CYDEV_UCFG_BASE 0x40010000 -#define CYDEV_UCFG_SIZE 0x00005040 -#define CYDEV_UCFG_B0_BASE 0x40010000 -#define CYDEV_UCFG_B0_SIZE 0x00000fef -#define CYDEV_UCFG_B0_P0_BASE 0x40010000 -#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 -#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 -#define CYREG_B0_P0_U0_PLD_IT0 0x40010000 -#define CYREG_B0_P0_U0_PLD_IT1 0x40010004 -#define CYREG_B0_P0_U0_PLD_IT2 0x40010008 -#define CYREG_B0_P0_U0_PLD_IT3 0x4001000c -#define CYREG_B0_P0_U0_PLD_IT4 0x40010010 -#define CYREG_B0_P0_U0_PLD_IT5 0x40010014 -#define CYREG_B0_P0_U0_PLD_IT6 0x40010018 -#define CYREG_B0_P0_U0_PLD_IT7 0x4001001c -#define CYREG_B0_P0_U0_PLD_IT8 0x40010020 -#define CYREG_B0_P0_U0_PLD_IT9 0x40010024 -#define CYREG_B0_P0_U0_PLD_IT10 0x40010028 -#define CYREG_B0_P0_U0_PLD_IT11 0x4001002c -#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030 -#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032 -#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034 -#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036 -#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 -#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003a -#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c -#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e -#define CYREG_B0_P0_U0_CFG0 0x40010040 -#define CYREG_B0_P0_U0_CFG1 0x40010041 -#define CYREG_B0_P0_U0_CFG2 0x40010042 -#define CYREG_B0_P0_U0_CFG3 0x40010043 -#define CYREG_B0_P0_U0_CFG4 0x40010044 -#define CYREG_B0_P0_U0_CFG5 0x40010045 -#define CYREG_B0_P0_U0_CFG6 0x40010046 -#define CYREG_B0_P0_U0_CFG7 0x40010047 -#define CYREG_B0_P0_U0_CFG8 0x40010048 -#define CYREG_B0_P0_U0_CFG9 0x40010049 -#define CYREG_B0_P0_U0_CFG10 0x4001004a -#define CYREG_B0_P0_U0_CFG11 0x4001004b -#define CYREG_B0_P0_U0_CFG12 0x4001004c -#define CYREG_B0_P0_U0_CFG13 0x4001004d -#define CYREG_B0_P0_U0_CFG14 0x4001004e -#define CYREG_B0_P0_U0_CFG15 0x4001004f -#define CYREG_B0_P0_U0_CFG16 0x40010050 -#define CYREG_B0_P0_U0_CFG17 0x40010051 -#define CYREG_B0_P0_U0_CFG18 0x40010052 -#define CYREG_B0_P0_U0_CFG19 0x40010053 -#define CYREG_B0_P0_U0_CFG20 0x40010054 -#define CYREG_B0_P0_U0_CFG21 0x40010055 -#define CYREG_B0_P0_U0_CFG22 0x40010056 -#define CYREG_B0_P0_U0_CFG23 0x40010057 -#define CYREG_B0_P0_U0_CFG24 0x40010058 -#define CYREG_B0_P0_U0_CFG25 0x40010059 -#define CYREG_B0_P0_U0_CFG26 0x4001005a -#define CYREG_B0_P0_U0_CFG27 0x4001005b -#define CYREG_B0_P0_U0_CFG28 0x4001005c -#define CYREG_B0_P0_U0_CFG29 0x4001005d -#define CYREG_B0_P0_U0_CFG30 0x4001005e -#define CYREG_B0_P0_U0_CFG31 0x4001005f -#define CYREG_B0_P0_U0_DCFG0 0x40010060 -#define CYREG_B0_P0_U0_DCFG1 0x40010062 -#define CYREG_B0_P0_U0_DCFG2 0x40010064 -#define CYREG_B0_P0_U0_DCFG3 0x40010066 -#define CYREG_B0_P0_U0_DCFG4 0x40010068 -#define CYREG_B0_P0_U0_DCFG5 0x4001006a -#define CYREG_B0_P0_U0_DCFG6 0x4001006c -#define CYREG_B0_P0_U0_DCFG7 0x4001006e -#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 -#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 -#define CYREG_B0_P0_U1_PLD_IT0 0x40010080 -#define CYREG_B0_P0_U1_PLD_IT1 0x40010084 -#define CYREG_B0_P0_U1_PLD_IT2 0x40010088 -#define CYREG_B0_P0_U1_PLD_IT3 0x4001008c -#define CYREG_B0_P0_U1_PLD_IT4 0x40010090 -#define CYREG_B0_P0_U1_PLD_IT5 0x40010094 -#define CYREG_B0_P0_U1_PLD_IT6 0x40010098 -#define CYREG_B0_P0_U1_PLD_IT7 0x4001009c -#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0 -#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4 -#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8 -#define CYREG_B0_P0_U1_PLD_IT11 0x400100ac -#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0 -#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2 -#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4 -#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6 -#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 -#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100ba -#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc -#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100be -#define CYREG_B0_P0_U1_CFG0 0x400100c0 -#define CYREG_B0_P0_U1_CFG1 0x400100c1 -#define CYREG_B0_P0_U1_CFG2 0x400100c2 -#define CYREG_B0_P0_U1_CFG3 0x400100c3 -#define CYREG_B0_P0_U1_CFG4 0x400100c4 -#define CYREG_B0_P0_U1_CFG5 0x400100c5 -#define CYREG_B0_P0_U1_CFG6 0x400100c6 -#define CYREG_B0_P0_U1_CFG7 0x400100c7 -#define CYREG_B0_P0_U1_CFG8 0x400100c8 -#define CYREG_B0_P0_U1_CFG9 0x400100c9 -#define CYREG_B0_P0_U1_CFG10 0x400100ca -#define CYREG_B0_P0_U1_CFG11 0x400100cb -#define CYREG_B0_P0_U1_CFG12 0x400100cc -#define CYREG_B0_P0_U1_CFG13 0x400100cd -#define CYREG_B0_P0_U1_CFG14 0x400100ce -#define CYREG_B0_P0_U1_CFG15 0x400100cf -#define CYREG_B0_P0_U1_CFG16 0x400100d0 -#define CYREG_B0_P0_U1_CFG17 0x400100d1 -#define CYREG_B0_P0_U1_CFG18 0x400100d2 -#define CYREG_B0_P0_U1_CFG19 0x400100d3 -#define CYREG_B0_P0_U1_CFG20 0x400100d4 -#define CYREG_B0_P0_U1_CFG21 0x400100d5 -#define CYREG_B0_P0_U1_CFG22 0x400100d6 -#define CYREG_B0_P0_U1_CFG23 0x400100d7 -#define CYREG_B0_P0_U1_CFG24 0x400100d8 -#define CYREG_B0_P0_U1_CFG25 0x400100d9 -#define CYREG_B0_P0_U1_CFG26 0x400100da -#define CYREG_B0_P0_U1_CFG27 0x400100db -#define CYREG_B0_P0_U1_CFG28 0x400100dc -#define CYREG_B0_P0_U1_CFG29 0x400100dd -#define CYREG_B0_P0_U1_CFG30 0x400100de -#define CYREG_B0_P0_U1_CFG31 0x400100df -#define CYREG_B0_P0_U1_DCFG0 0x400100e0 -#define CYREG_B0_P0_U1_DCFG1 0x400100e2 -#define CYREG_B0_P0_U1_DCFG2 0x400100e4 -#define CYREG_B0_P0_U1_DCFG3 0x400100e6 -#define CYREG_B0_P0_U1_DCFG4 0x400100e8 -#define CYREG_B0_P0_U1_DCFG5 0x400100ea -#define CYREG_B0_P0_U1_DCFG6 0x400100ec -#define CYREG_B0_P0_U1_DCFG7 0x400100ee -#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 -#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P1_BASE 0x40010200 -#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 -#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 -#define CYREG_B0_P1_U0_PLD_IT0 0x40010200 -#define CYREG_B0_P1_U0_PLD_IT1 0x40010204 -#define CYREG_B0_P1_U0_PLD_IT2 0x40010208 -#define CYREG_B0_P1_U0_PLD_IT3 0x4001020c -#define CYREG_B0_P1_U0_PLD_IT4 0x40010210 -#define CYREG_B0_P1_U0_PLD_IT5 0x40010214 -#define CYREG_B0_P1_U0_PLD_IT6 0x40010218 -#define CYREG_B0_P1_U0_PLD_IT7 0x4001021c -#define CYREG_B0_P1_U0_PLD_IT8 0x40010220 -#define CYREG_B0_P1_U0_PLD_IT9 0x40010224 -#define CYREG_B0_P1_U0_PLD_IT10 0x40010228 -#define CYREG_B0_P1_U0_PLD_IT11 0x4001022c -#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230 -#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232 -#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234 -#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236 -#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 -#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023a -#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c -#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e -#define CYREG_B0_P1_U0_CFG0 0x40010240 -#define CYREG_B0_P1_U0_CFG1 0x40010241 -#define CYREG_B0_P1_U0_CFG2 0x40010242 -#define CYREG_B0_P1_U0_CFG3 0x40010243 -#define CYREG_B0_P1_U0_CFG4 0x40010244 -#define CYREG_B0_P1_U0_CFG5 0x40010245 -#define CYREG_B0_P1_U0_CFG6 0x40010246 -#define CYREG_B0_P1_U0_CFG7 0x40010247 -#define CYREG_B0_P1_U0_CFG8 0x40010248 -#define CYREG_B0_P1_U0_CFG9 0x40010249 -#define CYREG_B0_P1_U0_CFG10 0x4001024a -#define CYREG_B0_P1_U0_CFG11 0x4001024b -#define CYREG_B0_P1_U0_CFG12 0x4001024c -#define CYREG_B0_P1_U0_CFG13 0x4001024d -#define CYREG_B0_P1_U0_CFG14 0x4001024e -#define CYREG_B0_P1_U0_CFG15 0x4001024f -#define CYREG_B0_P1_U0_CFG16 0x40010250 -#define CYREG_B0_P1_U0_CFG17 0x40010251 -#define CYREG_B0_P1_U0_CFG18 0x40010252 -#define CYREG_B0_P1_U0_CFG19 0x40010253 -#define CYREG_B0_P1_U0_CFG20 0x40010254 -#define CYREG_B0_P1_U0_CFG21 0x40010255 -#define CYREG_B0_P1_U0_CFG22 0x40010256 -#define CYREG_B0_P1_U0_CFG23 0x40010257 -#define CYREG_B0_P1_U0_CFG24 0x40010258 -#define CYREG_B0_P1_U0_CFG25 0x40010259 -#define CYREG_B0_P1_U0_CFG26 0x4001025a -#define CYREG_B0_P1_U0_CFG27 0x4001025b -#define CYREG_B0_P1_U0_CFG28 0x4001025c -#define CYREG_B0_P1_U0_CFG29 0x4001025d -#define CYREG_B0_P1_U0_CFG30 0x4001025e -#define CYREG_B0_P1_U0_CFG31 0x4001025f -#define CYREG_B0_P1_U0_DCFG0 0x40010260 -#define CYREG_B0_P1_U0_DCFG1 0x40010262 -#define CYREG_B0_P1_U0_DCFG2 0x40010264 -#define CYREG_B0_P1_U0_DCFG3 0x40010266 -#define CYREG_B0_P1_U0_DCFG4 0x40010268 -#define CYREG_B0_P1_U0_DCFG5 0x4001026a -#define CYREG_B0_P1_U0_DCFG6 0x4001026c -#define CYREG_B0_P1_U0_DCFG7 0x4001026e -#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 -#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 -#define CYREG_B0_P1_U1_PLD_IT0 0x40010280 -#define CYREG_B0_P1_U1_PLD_IT1 0x40010284 -#define CYREG_B0_P1_U1_PLD_IT2 0x40010288 -#define CYREG_B0_P1_U1_PLD_IT3 0x4001028c -#define CYREG_B0_P1_U1_PLD_IT4 0x40010290 -#define CYREG_B0_P1_U1_PLD_IT5 0x40010294 -#define CYREG_B0_P1_U1_PLD_IT6 0x40010298 -#define CYREG_B0_P1_U1_PLD_IT7 0x4001029c -#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0 -#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4 -#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8 -#define CYREG_B0_P1_U1_PLD_IT11 0x400102ac -#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0 -#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2 -#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4 -#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6 -#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 -#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102ba -#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc -#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102be -#define CYREG_B0_P1_U1_CFG0 0x400102c0 -#define CYREG_B0_P1_U1_CFG1 0x400102c1 -#define CYREG_B0_P1_U1_CFG2 0x400102c2 -#define CYREG_B0_P1_U1_CFG3 0x400102c3 -#define CYREG_B0_P1_U1_CFG4 0x400102c4 -#define CYREG_B0_P1_U1_CFG5 0x400102c5 -#define CYREG_B0_P1_U1_CFG6 0x400102c6 -#define CYREG_B0_P1_U1_CFG7 0x400102c7 -#define CYREG_B0_P1_U1_CFG8 0x400102c8 -#define CYREG_B0_P1_U1_CFG9 0x400102c9 -#define CYREG_B0_P1_U1_CFG10 0x400102ca -#define CYREG_B0_P1_U1_CFG11 0x400102cb -#define CYREG_B0_P1_U1_CFG12 0x400102cc -#define CYREG_B0_P1_U1_CFG13 0x400102cd -#define CYREG_B0_P1_U1_CFG14 0x400102ce -#define CYREG_B0_P1_U1_CFG15 0x400102cf -#define CYREG_B0_P1_U1_CFG16 0x400102d0 -#define CYREG_B0_P1_U1_CFG17 0x400102d1 -#define CYREG_B0_P1_U1_CFG18 0x400102d2 -#define CYREG_B0_P1_U1_CFG19 0x400102d3 -#define CYREG_B0_P1_U1_CFG20 0x400102d4 -#define CYREG_B0_P1_U1_CFG21 0x400102d5 -#define CYREG_B0_P1_U1_CFG22 0x400102d6 -#define CYREG_B0_P1_U1_CFG23 0x400102d7 -#define CYREG_B0_P1_U1_CFG24 0x400102d8 -#define CYREG_B0_P1_U1_CFG25 0x400102d9 -#define CYREG_B0_P1_U1_CFG26 0x400102da -#define CYREG_B0_P1_U1_CFG27 0x400102db -#define CYREG_B0_P1_U1_CFG28 0x400102dc -#define CYREG_B0_P1_U1_CFG29 0x400102dd -#define CYREG_B0_P1_U1_CFG30 0x400102de -#define CYREG_B0_P1_U1_CFG31 0x400102df -#define CYREG_B0_P1_U1_DCFG0 0x400102e0 -#define CYREG_B0_P1_U1_DCFG1 0x400102e2 -#define CYREG_B0_P1_U1_DCFG2 0x400102e4 -#define CYREG_B0_P1_U1_DCFG3 0x400102e6 -#define CYREG_B0_P1_U1_DCFG4 0x400102e8 -#define CYREG_B0_P1_U1_DCFG5 0x400102ea -#define CYREG_B0_P1_U1_DCFG6 0x400102ec -#define CYREG_B0_P1_U1_DCFG7 0x400102ee -#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 -#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P2_BASE 0x40010400 -#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 -#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 -#define CYREG_B0_P2_U0_PLD_IT0 0x40010400 -#define CYREG_B0_P2_U0_PLD_IT1 0x40010404 -#define CYREG_B0_P2_U0_PLD_IT2 0x40010408 -#define CYREG_B0_P2_U0_PLD_IT3 0x4001040c -#define CYREG_B0_P2_U0_PLD_IT4 0x40010410 -#define CYREG_B0_P2_U0_PLD_IT5 0x40010414 -#define CYREG_B0_P2_U0_PLD_IT6 0x40010418 -#define CYREG_B0_P2_U0_PLD_IT7 0x4001041c -#define CYREG_B0_P2_U0_PLD_IT8 0x40010420 -#define CYREG_B0_P2_U0_PLD_IT9 0x40010424 -#define CYREG_B0_P2_U0_PLD_IT10 0x40010428 -#define CYREG_B0_P2_U0_PLD_IT11 0x4001042c -#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430 -#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432 -#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434 -#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436 -#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 -#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043a -#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c -#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e -#define CYREG_B0_P2_U0_CFG0 0x40010440 -#define CYREG_B0_P2_U0_CFG1 0x40010441 -#define CYREG_B0_P2_U0_CFG2 0x40010442 -#define CYREG_B0_P2_U0_CFG3 0x40010443 -#define CYREG_B0_P2_U0_CFG4 0x40010444 -#define CYREG_B0_P2_U0_CFG5 0x40010445 -#define CYREG_B0_P2_U0_CFG6 0x40010446 -#define CYREG_B0_P2_U0_CFG7 0x40010447 -#define CYREG_B0_P2_U0_CFG8 0x40010448 -#define CYREG_B0_P2_U0_CFG9 0x40010449 -#define CYREG_B0_P2_U0_CFG10 0x4001044a -#define CYREG_B0_P2_U0_CFG11 0x4001044b -#define CYREG_B0_P2_U0_CFG12 0x4001044c -#define CYREG_B0_P2_U0_CFG13 0x4001044d -#define CYREG_B0_P2_U0_CFG14 0x4001044e -#define CYREG_B0_P2_U0_CFG15 0x4001044f -#define CYREG_B0_P2_U0_CFG16 0x40010450 -#define CYREG_B0_P2_U0_CFG17 0x40010451 -#define CYREG_B0_P2_U0_CFG18 0x40010452 -#define CYREG_B0_P2_U0_CFG19 0x40010453 -#define CYREG_B0_P2_U0_CFG20 0x40010454 -#define CYREG_B0_P2_U0_CFG21 0x40010455 -#define CYREG_B0_P2_U0_CFG22 0x40010456 -#define CYREG_B0_P2_U0_CFG23 0x40010457 -#define CYREG_B0_P2_U0_CFG24 0x40010458 -#define CYREG_B0_P2_U0_CFG25 0x40010459 -#define CYREG_B0_P2_U0_CFG26 0x4001045a -#define CYREG_B0_P2_U0_CFG27 0x4001045b -#define CYREG_B0_P2_U0_CFG28 0x4001045c -#define CYREG_B0_P2_U0_CFG29 0x4001045d -#define CYREG_B0_P2_U0_CFG30 0x4001045e -#define CYREG_B0_P2_U0_CFG31 0x4001045f -#define CYREG_B0_P2_U0_DCFG0 0x40010460 -#define CYREG_B0_P2_U0_DCFG1 0x40010462 -#define CYREG_B0_P2_U0_DCFG2 0x40010464 -#define CYREG_B0_P2_U0_DCFG3 0x40010466 -#define CYREG_B0_P2_U0_DCFG4 0x40010468 -#define CYREG_B0_P2_U0_DCFG5 0x4001046a -#define CYREG_B0_P2_U0_DCFG6 0x4001046c -#define CYREG_B0_P2_U0_DCFG7 0x4001046e -#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 -#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 -#define CYREG_B0_P2_U1_PLD_IT0 0x40010480 -#define CYREG_B0_P2_U1_PLD_IT1 0x40010484 -#define CYREG_B0_P2_U1_PLD_IT2 0x40010488 -#define CYREG_B0_P2_U1_PLD_IT3 0x4001048c -#define CYREG_B0_P2_U1_PLD_IT4 0x40010490 -#define CYREG_B0_P2_U1_PLD_IT5 0x40010494 -#define CYREG_B0_P2_U1_PLD_IT6 0x40010498 -#define CYREG_B0_P2_U1_PLD_IT7 0x4001049c -#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0 -#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4 -#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8 -#define CYREG_B0_P2_U1_PLD_IT11 0x400104ac -#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0 -#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2 -#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4 -#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6 -#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 -#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104ba -#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc -#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104be -#define CYREG_B0_P2_U1_CFG0 0x400104c0 -#define CYREG_B0_P2_U1_CFG1 0x400104c1 -#define CYREG_B0_P2_U1_CFG2 0x400104c2 -#define CYREG_B0_P2_U1_CFG3 0x400104c3 -#define CYREG_B0_P2_U1_CFG4 0x400104c4 -#define CYREG_B0_P2_U1_CFG5 0x400104c5 -#define CYREG_B0_P2_U1_CFG6 0x400104c6 -#define CYREG_B0_P2_U1_CFG7 0x400104c7 -#define CYREG_B0_P2_U1_CFG8 0x400104c8 -#define CYREG_B0_P2_U1_CFG9 0x400104c9 -#define CYREG_B0_P2_U1_CFG10 0x400104ca -#define CYREG_B0_P2_U1_CFG11 0x400104cb -#define CYREG_B0_P2_U1_CFG12 0x400104cc -#define CYREG_B0_P2_U1_CFG13 0x400104cd -#define CYREG_B0_P2_U1_CFG14 0x400104ce -#define CYREG_B0_P2_U1_CFG15 0x400104cf -#define CYREG_B0_P2_U1_CFG16 0x400104d0 -#define CYREG_B0_P2_U1_CFG17 0x400104d1 -#define CYREG_B0_P2_U1_CFG18 0x400104d2 -#define CYREG_B0_P2_U1_CFG19 0x400104d3 -#define CYREG_B0_P2_U1_CFG20 0x400104d4 -#define CYREG_B0_P2_U1_CFG21 0x400104d5 -#define CYREG_B0_P2_U1_CFG22 0x400104d6 -#define CYREG_B0_P2_U1_CFG23 0x400104d7 -#define CYREG_B0_P2_U1_CFG24 0x400104d8 -#define CYREG_B0_P2_U1_CFG25 0x400104d9 -#define CYREG_B0_P2_U1_CFG26 0x400104da -#define CYREG_B0_P2_U1_CFG27 0x400104db -#define CYREG_B0_P2_U1_CFG28 0x400104dc -#define CYREG_B0_P2_U1_CFG29 0x400104dd -#define CYREG_B0_P2_U1_CFG30 0x400104de -#define CYREG_B0_P2_U1_CFG31 0x400104df -#define CYREG_B0_P2_U1_DCFG0 0x400104e0 -#define CYREG_B0_P2_U1_DCFG1 0x400104e2 -#define CYREG_B0_P2_U1_DCFG2 0x400104e4 -#define CYREG_B0_P2_U1_DCFG3 0x400104e6 -#define CYREG_B0_P2_U1_DCFG4 0x400104e8 -#define CYREG_B0_P2_U1_DCFG5 0x400104ea -#define CYREG_B0_P2_U1_DCFG6 0x400104ec -#define CYREG_B0_P2_U1_DCFG7 0x400104ee -#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 -#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P3_BASE 0x40010600 -#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 -#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 -#define CYREG_B0_P3_U0_PLD_IT0 0x40010600 -#define CYREG_B0_P3_U0_PLD_IT1 0x40010604 -#define CYREG_B0_P3_U0_PLD_IT2 0x40010608 -#define CYREG_B0_P3_U0_PLD_IT3 0x4001060c -#define CYREG_B0_P3_U0_PLD_IT4 0x40010610 -#define CYREG_B0_P3_U0_PLD_IT5 0x40010614 -#define CYREG_B0_P3_U0_PLD_IT6 0x40010618 -#define CYREG_B0_P3_U0_PLD_IT7 0x4001061c -#define CYREG_B0_P3_U0_PLD_IT8 0x40010620 -#define CYREG_B0_P3_U0_PLD_IT9 0x40010624 -#define CYREG_B0_P3_U0_PLD_IT10 0x40010628 -#define CYREG_B0_P3_U0_PLD_IT11 0x4001062c -#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630 -#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632 -#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634 -#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636 -#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 -#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063a -#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c -#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e -#define CYREG_B0_P3_U0_CFG0 0x40010640 -#define CYREG_B0_P3_U0_CFG1 0x40010641 -#define CYREG_B0_P3_U0_CFG2 0x40010642 -#define CYREG_B0_P3_U0_CFG3 0x40010643 -#define CYREG_B0_P3_U0_CFG4 0x40010644 -#define CYREG_B0_P3_U0_CFG5 0x40010645 -#define CYREG_B0_P3_U0_CFG6 0x40010646 -#define CYREG_B0_P3_U0_CFG7 0x40010647 -#define CYREG_B0_P3_U0_CFG8 0x40010648 -#define CYREG_B0_P3_U0_CFG9 0x40010649 -#define CYREG_B0_P3_U0_CFG10 0x4001064a -#define CYREG_B0_P3_U0_CFG11 0x4001064b -#define CYREG_B0_P3_U0_CFG12 0x4001064c -#define CYREG_B0_P3_U0_CFG13 0x4001064d -#define CYREG_B0_P3_U0_CFG14 0x4001064e -#define CYREG_B0_P3_U0_CFG15 0x4001064f -#define CYREG_B0_P3_U0_CFG16 0x40010650 -#define CYREG_B0_P3_U0_CFG17 0x40010651 -#define CYREG_B0_P3_U0_CFG18 0x40010652 -#define CYREG_B0_P3_U0_CFG19 0x40010653 -#define CYREG_B0_P3_U0_CFG20 0x40010654 -#define CYREG_B0_P3_U0_CFG21 0x40010655 -#define CYREG_B0_P3_U0_CFG22 0x40010656 -#define CYREG_B0_P3_U0_CFG23 0x40010657 -#define CYREG_B0_P3_U0_CFG24 0x40010658 -#define CYREG_B0_P3_U0_CFG25 0x40010659 -#define CYREG_B0_P3_U0_CFG26 0x4001065a -#define CYREG_B0_P3_U0_CFG27 0x4001065b -#define CYREG_B0_P3_U0_CFG28 0x4001065c -#define CYREG_B0_P3_U0_CFG29 0x4001065d -#define CYREG_B0_P3_U0_CFG30 0x4001065e -#define CYREG_B0_P3_U0_CFG31 0x4001065f -#define CYREG_B0_P3_U0_DCFG0 0x40010660 -#define CYREG_B0_P3_U0_DCFG1 0x40010662 -#define CYREG_B0_P3_U0_DCFG2 0x40010664 -#define CYREG_B0_P3_U0_DCFG3 0x40010666 -#define CYREG_B0_P3_U0_DCFG4 0x40010668 -#define CYREG_B0_P3_U0_DCFG5 0x4001066a -#define CYREG_B0_P3_U0_DCFG6 0x4001066c -#define CYREG_B0_P3_U0_DCFG7 0x4001066e -#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 -#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 -#define CYREG_B0_P3_U1_PLD_IT0 0x40010680 -#define CYREG_B0_P3_U1_PLD_IT1 0x40010684 -#define CYREG_B0_P3_U1_PLD_IT2 0x40010688 -#define CYREG_B0_P3_U1_PLD_IT3 0x4001068c -#define CYREG_B0_P3_U1_PLD_IT4 0x40010690 -#define CYREG_B0_P3_U1_PLD_IT5 0x40010694 -#define CYREG_B0_P3_U1_PLD_IT6 0x40010698 -#define CYREG_B0_P3_U1_PLD_IT7 0x4001069c -#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0 -#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4 -#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8 -#define CYREG_B0_P3_U1_PLD_IT11 0x400106ac -#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0 -#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2 -#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4 -#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6 -#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 -#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106ba -#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc -#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106be -#define CYREG_B0_P3_U1_CFG0 0x400106c0 -#define CYREG_B0_P3_U1_CFG1 0x400106c1 -#define CYREG_B0_P3_U1_CFG2 0x400106c2 -#define CYREG_B0_P3_U1_CFG3 0x400106c3 -#define CYREG_B0_P3_U1_CFG4 0x400106c4 -#define CYREG_B0_P3_U1_CFG5 0x400106c5 -#define CYREG_B0_P3_U1_CFG6 0x400106c6 -#define CYREG_B0_P3_U1_CFG7 0x400106c7 -#define CYREG_B0_P3_U1_CFG8 0x400106c8 -#define CYREG_B0_P3_U1_CFG9 0x400106c9 -#define CYREG_B0_P3_U1_CFG10 0x400106ca -#define CYREG_B0_P3_U1_CFG11 0x400106cb -#define CYREG_B0_P3_U1_CFG12 0x400106cc -#define CYREG_B0_P3_U1_CFG13 0x400106cd -#define CYREG_B0_P3_U1_CFG14 0x400106ce -#define CYREG_B0_P3_U1_CFG15 0x400106cf -#define CYREG_B0_P3_U1_CFG16 0x400106d0 -#define CYREG_B0_P3_U1_CFG17 0x400106d1 -#define CYREG_B0_P3_U1_CFG18 0x400106d2 -#define CYREG_B0_P3_U1_CFG19 0x400106d3 -#define CYREG_B0_P3_U1_CFG20 0x400106d4 -#define CYREG_B0_P3_U1_CFG21 0x400106d5 -#define CYREG_B0_P3_U1_CFG22 0x400106d6 -#define CYREG_B0_P3_U1_CFG23 0x400106d7 -#define CYREG_B0_P3_U1_CFG24 0x400106d8 -#define CYREG_B0_P3_U1_CFG25 0x400106d9 -#define CYREG_B0_P3_U1_CFG26 0x400106da -#define CYREG_B0_P3_U1_CFG27 0x400106db -#define CYREG_B0_P3_U1_CFG28 0x400106dc -#define CYREG_B0_P3_U1_CFG29 0x400106dd -#define CYREG_B0_P3_U1_CFG30 0x400106de -#define CYREG_B0_P3_U1_CFG31 0x400106df -#define CYREG_B0_P3_U1_DCFG0 0x400106e0 -#define CYREG_B0_P3_U1_DCFG1 0x400106e2 -#define CYREG_B0_P3_U1_DCFG2 0x400106e4 -#define CYREG_B0_P3_U1_DCFG3 0x400106e6 -#define CYREG_B0_P3_U1_DCFG4 0x400106e8 -#define CYREG_B0_P3_U1_DCFG5 0x400106ea -#define CYREG_B0_P3_U1_DCFG6 0x400106ec -#define CYREG_B0_P3_U1_DCFG7 0x400106ee -#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 -#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P4_BASE 0x40010800 -#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 -#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 -#define CYREG_B0_P4_U0_PLD_IT0 0x40010800 -#define CYREG_B0_P4_U0_PLD_IT1 0x40010804 -#define CYREG_B0_P4_U0_PLD_IT2 0x40010808 -#define CYREG_B0_P4_U0_PLD_IT3 0x4001080c -#define CYREG_B0_P4_U0_PLD_IT4 0x40010810 -#define CYREG_B0_P4_U0_PLD_IT5 0x40010814 -#define CYREG_B0_P4_U0_PLD_IT6 0x40010818 -#define CYREG_B0_P4_U0_PLD_IT7 0x4001081c -#define CYREG_B0_P4_U0_PLD_IT8 0x40010820 -#define CYREG_B0_P4_U0_PLD_IT9 0x40010824 -#define CYREG_B0_P4_U0_PLD_IT10 0x40010828 -#define CYREG_B0_P4_U0_PLD_IT11 0x4001082c -#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830 -#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832 -#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834 -#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836 -#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 -#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083a -#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c -#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e -#define CYREG_B0_P4_U0_CFG0 0x40010840 -#define CYREG_B0_P4_U0_CFG1 0x40010841 -#define CYREG_B0_P4_U0_CFG2 0x40010842 -#define CYREG_B0_P4_U0_CFG3 0x40010843 -#define CYREG_B0_P4_U0_CFG4 0x40010844 -#define CYREG_B0_P4_U0_CFG5 0x40010845 -#define CYREG_B0_P4_U0_CFG6 0x40010846 -#define CYREG_B0_P4_U0_CFG7 0x40010847 -#define CYREG_B0_P4_U0_CFG8 0x40010848 -#define CYREG_B0_P4_U0_CFG9 0x40010849 -#define CYREG_B0_P4_U0_CFG10 0x4001084a -#define CYREG_B0_P4_U0_CFG11 0x4001084b -#define CYREG_B0_P4_U0_CFG12 0x4001084c -#define CYREG_B0_P4_U0_CFG13 0x4001084d -#define CYREG_B0_P4_U0_CFG14 0x4001084e -#define CYREG_B0_P4_U0_CFG15 0x4001084f -#define CYREG_B0_P4_U0_CFG16 0x40010850 -#define CYREG_B0_P4_U0_CFG17 0x40010851 -#define CYREG_B0_P4_U0_CFG18 0x40010852 -#define CYREG_B0_P4_U0_CFG19 0x40010853 -#define CYREG_B0_P4_U0_CFG20 0x40010854 -#define CYREG_B0_P4_U0_CFG21 0x40010855 -#define CYREG_B0_P4_U0_CFG22 0x40010856 -#define CYREG_B0_P4_U0_CFG23 0x40010857 -#define CYREG_B0_P4_U0_CFG24 0x40010858 -#define CYREG_B0_P4_U0_CFG25 0x40010859 -#define CYREG_B0_P4_U0_CFG26 0x4001085a -#define CYREG_B0_P4_U0_CFG27 0x4001085b -#define CYREG_B0_P4_U0_CFG28 0x4001085c -#define CYREG_B0_P4_U0_CFG29 0x4001085d -#define CYREG_B0_P4_U0_CFG30 0x4001085e -#define CYREG_B0_P4_U0_CFG31 0x4001085f -#define CYREG_B0_P4_U0_DCFG0 0x40010860 -#define CYREG_B0_P4_U0_DCFG1 0x40010862 -#define CYREG_B0_P4_U0_DCFG2 0x40010864 -#define CYREG_B0_P4_U0_DCFG3 0x40010866 -#define CYREG_B0_P4_U0_DCFG4 0x40010868 -#define CYREG_B0_P4_U0_DCFG5 0x4001086a -#define CYREG_B0_P4_U0_DCFG6 0x4001086c -#define CYREG_B0_P4_U0_DCFG7 0x4001086e -#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 -#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 -#define CYREG_B0_P4_U1_PLD_IT0 0x40010880 -#define CYREG_B0_P4_U1_PLD_IT1 0x40010884 -#define CYREG_B0_P4_U1_PLD_IT2 0x40010888 -#define CYREG_B0_P4_U1_PLD_IT3 0x4001088c -#define CYREG_B0_P4_U1_PLD_IT4 0x40010890 -#define CYREG_B0_P4_U1_PLD_IT5 0x40010894 -#define CYREG_B0_P4_U1_PLD_IT6 0x40010898 -#define CYREG_B0_P4_U1_PLD_IT7 0x4001089c -#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0 -#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4 -#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8 -#define CYREG_B0_P4_U1_PLD_IT11 0x400108ac -#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0 -#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2 -#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4 -#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6 -#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 -#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108ba -#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc -#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108be -#define CYREG_B0_P4_U1_CFG0 0x400108c0 -#define CYREG_B0_P4_U1_CFG1 0x400108c1 -#define CYREG_B0_P4_U1_CFG2 0x400108c2 -#define CYREG_B0_P4_U1_CFG3 0x400108c3 -#define CYREG_B0_P4_U1_CFG4 0x400108c4 -#define CYREG_B0_P4_U1_CFG5 0x400108c5 -#define CYREG_B0_P4_U1_CFG6 0x400108c6 -#define CYREG_B0_P4_U1_CFG7 0x400108c7 -#define CYREG_B0_P4_U1_CFG8 0x400108c8 -#define CYREG_B0_P4_U1_CFG9 0x400108c9 -#define CYREG_B0_P4_U1_CFG10 0x400108ca -#define CYREG_B0_P4_U1_CFG11 0x400108cb -#define CYREG_B0_P4_U1_CFG12 0x400108cc -#define CYREG_B0_P4_U1_CFG13 0x400108cd -#define CYREG_B0_P4_U1_CFG14 0x400108ce -#define CYREG_B0_P4_U1_CFG15 0x400108cf -#define CYREG_B0_P4_U1_CFG16 0x400108d0 -#define CYREG_B0_P4_U1_CFG17 0x400108d1 -#define CYREG_B0_P4_U1_CFG18 0x400108d2 -#define CYREG_B0_P4_U1_CFG19 0x400108d3 -#define CYREG_B0_P4_U1_CFG20 0x400108d4 -#define CYREG_B0_P4_U1_CFG21 0x400108d5 -#define CYREG_B0_P4_U1_CFG22 0x400108d6 -#define CYREG_B0_P4_U1_CFG23 0x400108d7 -#define CYREG_B0_P4_U1_CFG24 0x400108d8 -#define CYREG_B0_P4_U1_CFG25 0x400108d9 -#define CYREG_B0_P4_U1_CFG26 0x400108da -#define CYREG_B0_P4_U1_CFG27 0x400108db -#define CYREG_B0_P4_U1_CFG28 0x400108dc -#define CYREG_B0_P4_U1_CFG29 0x400108dd -#define CYREG_B0_P4_U1_CFG30 0x400108de -#define CYREG_B0_P4_U1_CFG31 0x400108df -#define CYREG_B0_P4_U1_DCFG0 0x400108e0 -#define CYREG_B0_P4_U1_DCFG1 0x400108e2 -#define CYREG_B0_P4_U1_DCFG2 0x400108e4 -#define CYREG_B0_P4_U1_DCFG3 0x400108e6 -#define CYREG_B0_P4_U1_DCFG4 0x400108e8 -#define CYREG_B0_P4_U1_DCFG5 0x400108ea -#define CYREG_B0_P4_U1_DCFG6 0x400108ec -#define CYREG_B0_P4_U1_DCFG7 0x400108ee -#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 -#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 -#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 -#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 -#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00 -#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04 -#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08 -#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0c -#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10 -#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14 -#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18 -#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1c -#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20 -#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24 -#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28 -#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2c -#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30 -#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32 -#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34 -#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36 -#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 -#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a -#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c -#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e -#define CYREG_B0_P5_U0_CFG0 0x40010a40 -#define CYREG_B0_P5_U0_CFG1 0x40010a41 -#define CYREG_B0_P5_U0_CFG2 0x40010a42 -#define CYREG_B0_P5_U0_CFG3 0x40010a43 -#define CYREG_B0_P5_U0_CFG4 0x40010a44 -#define CYREG_B0_P5_U0_CFG5 0x40010a45 -#define CYREG_B0_P5_U0_CFG6 0x40010a46 -#define CYREG_B0_P5_U0_CFG7 0x40010a47 -#define CYREG_B0_P5_U0_CFG8 0x40010a48 -#define CYREG_B0_P5_U0_CFG9 0x40010a49 -#define CYREG_B0_P5_U0_CFG10 0x40010a4a -#define CYREG_B0_P5_U0_CFG11 0x40010a4b -#define CYREG_B0_P5_U0_CFG12 0x40010a4c -#define CYREG_B0_P5_U0_CFG13 0x40010a4d -#define CYREG_B0_P5_U0_CFG14 0x40010a4e -#define CYREG_B0_P5_U0_CFG15 0x40010a4f -#define CYREG_B0_P5_U0_CFG16 0x40010a50 -#define CYREG_B0_P5_U0_CFG17 0x40010a51 -#define CYREG_B0_P5_U0_CFG18 0x40010a52 -#define CYREG_B0_P5_U0_CFG19 0x40010a53 -#define CYREG_B0_P5_U0_CFG20 0x40010a54 -#define CYREG_B0_P5_U0_CFG21 0x40010a55 -#define CYREG_B0_P5_U0_CFG22 0x40010a56 -#define CYREG_B0_P5_U0_CFG23 0x40010a57 -#define CYREG_B0_P5_U0_CFG24 0x40010a58 -#define CYREG_B0_P5_U0_CFG25 0x40010a59 -#define CYREG_B0_P5_U0_CFG26 0x40010a5a -#define CYREG_B0_P5_U0_CFG27 0x40010a5b -#define CYREG_B0_P5_U0_CFG28 0x40010a5c -#define CYREG_B0_P5_U0_CFG29 0x40010a5d -#define CYREG_B0_P5_U0_CFG30 0x40010a5e -#define CYREG_B0_P5_U0_CFG31 0x40010a5f -#define CYREG_B0_P5_U0_DCFG0 0x40010a60 -#define CYREG_B0_P5_U0_DCFG1 0x40010a62 -#define CYREG_B0_P5_U0_DCFG2 0x40010a64 -#define CYREG_B0_P5_U0_DCFG3 0x40010a66 -#define CYREG_B0_P5_U0_DCFG4 0x40010a68 -#define CYREG_B0_P5_U0_DCFG5 0x40010a6a -#define CYREG_B0_P5_U0_DCFG6 0x40010a6c -#define CYREG_B0_P5_U0_DCFG7 0x40010a6e -#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 -#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 -#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80 -#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84 -#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88 -#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8c -#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90 -#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94 -#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98 -#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9c -#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0 -#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4 -#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8 -#define CYREG_B0_P5_U1_PLD_IT11 0x40010aac -#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0 -#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2 -#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4 -#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6 -#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 -#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010aba -#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc -#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe -#define CYREG_B0_P5_U1_CFG0 0x40010ac0 -#define CYREG_B0_P5_U1_CFG1 0x40010ac1 -#define CYREG_B0_P5_U1_CFG2 0x40010ac2 -#define CYREG_B0_P5_U1_CFG3 0x40010ac3 -#define CYREG_B0_P5_U1_CFG4 0x40010ac4 -#define CYREG_B0_P5_U1_CFG5 0x40010ac5 -#define CYREG_B0_P5_U1_CFG6 0x40010ac6 -#define CYREG_B0_P5_U1_CFG7 0x40010ac7 -#define CYREG_B0_P5_U1_CFG8 0x40010ac8 -#define CYREG_B0_P5_U1_CFG9 0x40010ac9 -#define CYREG_B0_P5_U1_CFG10 0x40010aca -#define CYREG_B0_P5_U1_CFG11 0x40010acb -#define CYREG_B0_P5_U1_CFG12 0x40010acc -#define CYREG_B0_P5_U1_CFG13 0x40010acd -#define CYREG_B0_P5_U1_CFG14 0x40010ace -#define CYREG_B0_P5_U1_CFG15 0x40010acf -#define CYREG_B0_P5_U1_CFG16 0x40010ad0 -#define CYREG_B0_P5_U1_CFG17 0x40010ad1 -#define CYREG_B0_P5_U1_CFG18 0x40010ad2 -#define CYREG_B0_P5_U1_CFG19 0x40010ad3 -#define CYREG_B0_P5_U1_CFG20 0x40010ad4 -#define CYREG_B0_P5_U1_CFG21 0x40010ad5 -#define CYREG_B0_P5_U1_CFG22 0x40010ad6 -#define CYREG_B0_P5_U1_CFG23 0x40010ad7 -#define CYREG_B0_P5_U1_CFG24 0x40010ad8 -#define CYREG_B0_P5_U1_CFG25 0x40010ad9 -#define CYREG_B0_P5_U1_CFG26 0x40010ada -#define CYREG_B0_P5_U1_CFG27 0x40010adb -#define CYREG_B0_P5_U1_CFG28 0x40010adc -#define CYREG_B0_P5_U1_CFG29 0x40010add -#define CYREG_B0_P5_U1_CFG30 0x40010ade -#define CYREG_B0_P5_U1_CFG31 0x40010adf -#define CYREG_B0_P5_U1_DCFG0 0x40010ae0 -#define CYREG_B0_P5_U1_DCFG1 0x40010ae2 -#define CYREG_B0_P5_U1_DCFG2 0x40010ae4 -#define CYREG_B0_P5_U1_DCFG3 0x40010ae6 -#define CYREG_B0_P5_U1_DCFG4 0x40010ae8 -#define CYREG_B0_P5_U1_DCFG5 0x40010aea -#define CYREG_B0_P5_U1_DCFG6 0x40010aec -#define CYREG_B0_P5_U1_DCFG7 0x40010aee -#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 -#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 -#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 -#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 -#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00 -#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04 -#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08 -#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0c -#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10 -#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14 -#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18 -#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1c -#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20 -#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24 -#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28 -#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2c -#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30 -#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32 -#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34 -#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36 -#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 -#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a -#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c -#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e -#define CYREG_B0_P6_U0_CFG0 0x40010c40 -#define CYREG_B0_P6_U0_CFG1 0x40010c41 -#define CYREG_B0_P6_U0_CFG2 0x40010c42 -#define CYREG_B0_P6_U0_CFG3 0x40010c43 -#define CYREG_B0_P6_U0_CFG4 0x40010c44 -#define CYREG_B0_P6_U0_CFG5 0x40010c45 -#define CYREG_B0_P6_U0_CFG6 0x40010c46 -#define CYREG_B0_P6_U0_CFG7 0x40010c47 -#define CYREG_B0_P6_U0_CFG8 0x40010c48 -#define CYREG_B0_P6_U0_CFG9 0x40010c49 -#define CYREG_B0_P6_U0_CFG10 0x40010c4a -#define CYREG_B0_P6_U0_CFG11 0x40010c4b -#define CYREG_B0_P6_U0_CFG12 0x40010c4c -#define CYREG_B0_P6_U0_CFG13 0x40010c4d -#define CYREG_B0_P6_U0_CFG14 0x40010c4e -#define CYREG_B0_P6_U0_CFG15 0x40010c4f -#define CYREG_B0_P6_U0_CFG16 0x40010c50 -#define CYREG_B0_P6_U0_CFG17 0x40010c51 -#define CYREG_B0_P6_U0_CFG18 0x40010c52 -#define CYREG_B0_P6_U0_CFG19 0x40010c53 -#define CYREG_B0_P6_U0_CFG20 0x40010c54 -#define CYREG_B0_P6_U0_CFG21 0x40010c55 -#define CYREG_B0_P6_U0_CFG22 0x40010c56 -#define CYREG_B0_P6_U0_CFG23 0x40010c57 -#define CYREG_B0_P6_U0_CFG24 0x40010c58 -#define CYREG_B0_P6_U0_CFG25 0x40010c59 -#define CYREG_B0_P6_U0_CFG26 0x40010c5a -#define CYREG_B0_P6_U0_CFG27 0x40010c5b -#define CYREG_B0_P6_U0_CFG28 0x40010c5c -#define CYREG_B0_P6_U0_CFG29 0x40010c5d -#define CYREG_B0_P6_U0_CFG30 0x40010c5e -#define CYREG_B0_P6_U0_CFG31 0x40010c5f -#define CYREG_B0_P6_U0_DCFG0 0x40010c60 -#define CYREG_B0_P6_U0_DCFG1 0x40010c62 -#define CYREG_B0_P6_U0_DCFG2 0x40010c64 -#define CYREG_B0_P6_U0_DCFG3 0x40010c66 -#define CYREG_B0_P6_U0_DCFG4 0x40010c68 -#define CYREG_B0_P6_U0_DCFG5 0x40010c6a -#define CYREG_B0_P6_U0_DCFG6 0x40010c6c -#define CYREG_B0_P6_U0_DCFG7 0x40010c6e -#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 -#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 -#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80 -#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84 -#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88 -#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8c -#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90 -#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94 -#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98 -#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9c -#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0 -#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4 -#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8 -#define CYREG_B0_P6_U1_PLD_IT11 0x40010cac -#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0 -#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2 -#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4 -#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6 -#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 -#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cba -#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc -#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe -#define CYREG_B0_P6_U1_CFG0 0x40010cc0 -#define CYREG_B0_P6_U1_CFG1 0x40010cc1 -#define CYREG_B0_P6_U1_CFG2 0x40010cc2 -#define CYREG_B0_P6_U1_CFG3 0x40010cc3 -#define CYREG_B0_P6_U1_CFG4 0x40010cc4 -#define CYREG_B0_P6_U1_CFG5 0x40010cc5 -#define CYREG_B0_P6_U1_CFG6 0x40010cc6 -#define CYREG_B0_P6_U1_CFG7 0x40010cc7 -#define CYREG_B0_P6_U1_CFG8 0x40010cc8 -#define CYREG_B0_P6_U1_CFG9 0x40010cc9 -#define CYREG_B0_P6_U1_CFG10 0x40010cca -#define CYREG_B0_P6_U1_CFG11 0x40010ccb -#define CYREG_B0_P6_U1_CFG12 0x40010ccc -#define CYREG_B0_P6_U1_CFG13 0x40010ccd -#define CYREG_B0_P6_U1_CFG14 0x40010cce -#define CYREG_B0_P6_U1_CFG15 0x40010ccf -#define CYREG_B0_P6_U1_CFG16 0x40010cd0 -#define CYREG_B0_P6_U1_CFG17 0x40010cd1 -#define CYREG_B0_P6_U1_CFG18 0x40010cd2 -#define CYREG_B0_P6_U1_CFG19 0x40010cd3 -#define CYREG_B0_P6_U1_CFG20 0x40010cd4 -#define CYREG_B0_P6_U1_CFG21 0x40010cd5 -#define CYREG_B0_P6_U1_CFG22 0x40010cd6 -#define CYREG_B0_P6_U1_CFG23 0x40010cd7 -#define CYREG_B0_P6_U1_CFG24 0x40010cd8 -#define CYREG_B0_P6_U1_CFG25 0x40010cd9 -#define CYREG_B0_P6_U1_CFG26 0x40010cda -#define CYREG_B0_P6_U1_CFG27 0x40010cdb -#define CYREG_B0_P6_U1_CFG28 0x40010cdc -#define CYREG_B0_P6_U1_CFG29 0x40010cdd -#define CYREG_B0_P6_U1_CFG30 0x40010cde -#define CYREG_B0_P6_U1_CFG31 0x40010cdf -#define CYREG_B0_P6_U1_DCFG0 0x40010ce0 -#define CYREG_B0_P6_U1_DCFG1 0x40010ce2 -#define CYREG_B0_P6_U1_DCFG2 0x40010ce4 -#define CYREG_B0_P6_U1_DCFG3 0x40010ce6 -#define CYREG_B0_P6_U1_DCFG4 0x40010ce8 -#define CYREG_B0_P6_U1_DCFG5 0x40010cea -#define CYREG_B0_P6_U1_DCFG6 0x40010cec -#define CYREG_B0_P6_U1_DCFG7 0x40010cee -#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 -#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 -#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef -#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 -#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 -#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00 -#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04 -#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08 -#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0c -#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10 -#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14 -#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18 -#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1c -#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20 -#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24 -#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28 -#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2c -#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30 -#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32 -#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34 -#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36 -#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 -#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a -#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c -#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e -#define CYREG_B0_P7_U0_CFG0 0x40010e40 -#define CYREG_B0_P7_U0_CFG1 0x40010e41 -#define CYREG_B0_P7_U0_CFG2 0x40010e42 -#define CYREG_B0_P7_U0_CFG3 0x40010e43 -#define CYREG_B0_P7_U0_CFG4 0x40010e44 -#define CYREG_B0_P7_U0_CFG5 0x40010e45 -#define CYREG_B0_P7_U0_CFG6 0x40010e46 -#define CYREG_B0_P7_U0_CFG7 0x40010e47 -#define CYREG_B0_P7_U0_CFG8 0x40010e48 -#define CYREG_B0_P7_U0_CFG9 0x40010e49 -#define CYREG_B0_P7_U0_CFG10 0x40010e4a -#define CYREG_B0_P7_U0_CFG11 0x40010e4b -#define CYREG_B0_P7_U0_CFG12 0x40010e4c -#define CYREG_B0_P7_U0_CFG13 0x40010e4d -#define CYREG_B0_P7_U0_CFG14 0x40010e4e -#define CYREG_B0_P7_U0_CFG15 0x40010e4f -#define CYREG_B0_P7_U0_CFG16 0x40010e50 -#define CYREG_B0_P7_U0_CFG17 0x40010e51 -#define CYREG_B0_P7_U0_CFG18 0x40010e52 -#define CYREG_B0_P7_U0_CFG19 0x40010e53 -#define CYREG_B0_P7_U0_CFG20 0x40010e54 -#define CYREG_B0_P7_U0_CFG21 0x40010e55 -#define CYREG_B0_P7_U0_CFG22 0x40010e56 -#define CYREG_B0_P7_U0_CFG23 0x40010e57 -#define CYREG_B0_P7_U0_CFG24 0x40010e58 -#define CYREG_B0_P7_U0_CFG25 0x40010e59 -#define CYREG_B0_P7_U0_CFG26 0x40010e5a -#define CYREG_B0_P7_U0_CFG27 0x40010e5b -#define CYREG_B0_P7_U0_CFG28 0x40010e5c -#define CYREG_B0_P7_U0_CFG29 0x40010e5d -#define CYREG_B0_P7_U0_CFG30 0x40010e5e -#define CYREG_B0_P7_U0_CFG31 0x40010e5f -#define CYREG_B0_P7_U0_DCFG0 0x40010e60 -#define CYREG_B0_P7_U0_DCFG1 0x40010e62 -#define CYREG_B0_P7_U0_DCFG2 0x40010e64 -#define CYREG_B0_P7_U0_DCFG3 0x40010e66 -#define CYREG_B0_P7_U0_DCFG4 0x40010e68 -#define CYREG_B0_P7_U0_DCFG5 0x40010e6a -#define CYREG_B0_P7_U0_DCFG6 0x40010e6c -#define CYREG_B0_P7_U0_DCFG7 0x40010e6e -#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 -#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 -#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80 -#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84 -#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88 -#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8c -#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90 -#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94 -#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98 -#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9c -#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0 -#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4 -#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8 -#define CYREG_B0_P7_U1_PLD_IT11 0x40010eac -#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0 -#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2 -#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4 -#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6 -#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 -#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010eba -#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc -#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe -#define CYREG_B0_P7_U1_CFG0 0x40010ec0 -#define CYREG_B0_P7_U1_CFG1 0x40010ec1 -#define CYREG_B0_P7_U1_CFG2 0x40010ec2 -#define CYREG_B0_P7_U1_CFG3 0x40010ec3 -#define CYREG_B0_P7_U1_CFG4 0x40010ec4 -#define CYREG_B0_P7_U1_CFG5 0x40010ec5 -#define CYREG_B0_P7_U1_CFG6 0x40010ec6 -#define CYREG_B0_P7_U1_CFG7 0x40010ec7 -#define CYREG_B0_P7_U1_CFG8 0x40010ec8 -#define CYREG_B0_P7_U1_CFG9 0x40010ec9 -#define CYREG_B0_P7_U1_CFG10 0x40010eca -#define CYREG_B0_P7_U1_CFG11 0x40010ecb -#define CYREG_B0_P7_U1_CFG12 0x40010ecc -#define CYREG_B0_P7_U1_CFG13 0x40010ecd -#define CYREG_B0_P7_U1_CFG14 0x40010ece -#define CYREG_B0_P7_U1_CFG15 0x40010ecf -#define CYREG_B0_P7_U1_CFG16 0x40010ed0 -#define CYREG_B0_P7_U1_CFG17 0x40010ed1 -#define CYREG_B0_P7_U1_CFG18 0x40010ed2 -#define CYREG_B0_P7_U1_CFG19 0x40010ed3 -#define CYREG_B0_P7_U1_CFG20 0x40010ed4 -#define CYREG_B0_P7_U1_CFG21 0x40010ed5 -#define CYREG_B0_P7_U1_CFG22 0x40010ed6 -#define CYREG_B0_P7_U1_CFG23 0x40010ed7 -#define CYREG_B0_P7_U1_CFG24 0x40010ed8 -#define CYREG_B0_P7_U1_CFG25 0x40010ed9 -#define CYREG_B0_P7_U1_CFG26 0x40010eda -#define CYREG_B0_P7_U1_CFG27 0x40010edb -#define CYREG_B0_P7_U1_CFG28 0x40010edc -#define CYREG_B0_P7_U1_CFG29 0x40010edd -#define CYREG_B0_P7_U1_CFG30 0x40010ede -#define CYREG_B0_P7_U1_CFG31 0x40010edf -#define CYREG_B0_P7_U1_DCFG0 0x40010ee0 -#define CYREG_B0_P7_U1_DCFG1 0x40010ee2 -#define CYREG_B0_P7_U1_DCFG2 0x40010ee4 -#define CYREG_B0_P7_U1_DCFG3 0x40010ee6 -#define CYREG_B0_P7_U1_DCFG4 0x40010ee8 -#define CYREG_B0_P7_U1_DCFG5 0x40010eea -#define CYREG_B0_P7_U1_DCFG6 0x40010eec -#define CYREG_B0_P7_U1_DCFG7 0x40010eee -#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 -#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_BASE 0x40011000 -#define CYDEV_UCFG_B1_SIZE 0x00000fef -#define CYDEV_UCFG_B1_P2_BASE 0x40011400 -#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 -#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 -#define CYREG_B1_P2_U0_PLD_IT0 0x40011400 -#define CYREG_B1_P2_U0_PLD_IT1 0x40011404 -#define CYREG_B1_P2_U0_PLD_IT2 0x40011408 -#define CYREG_B1_P2_U0_PLD_IT3 0x4001140c -#define CYREG_B1_P2_U0_PLD_IT4 0x40011410 -#define CYREG_B1_P2_U0_PLD_IT5 0x40011414 -#define CYREG_B1_P2_U0_PLD_IT6 0x40011418 -#define CYREG_B1_P2_U0_PLD_IT7 0x4001141c -#define CYREG_B1_P2_U0_PLD_IT8 0x40011420 -#define CYREG_B1_P2_U0_PLD_IT9 0x40011424 -#define CYREG_B1_P2_U0_PLD_IT10 0x40011428 -#define CYREG_B1_P2_U0_PLD_IT11 0x4001142c -#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430 -#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432 -#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434 -#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436 -#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 -#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143a -#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c -#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e -#define CYREG_B1_P2_U0_CFG0 0x40011440 -#define CYREG_B1_P2_U0_CFG1 0x40011441 -#define CYREG_B1_P2_U0_CFG2 0x40011442 -#define CYREG_B1_P2_U0_CFG3 0x40011443 -#define CYREG_B1_P2_U0_CFG4 0x40011444 -#define CYREG_B1_P2_U0_CFG5 0x40011445 -#define CYREG_B1_P2_U0_CFG6 0x40011446 -#define CYREG_B1_P2_U0_CFG7 0x40011447 -#define CYREG_B1_P2_U0_CFG8 0x40011448 -#define CYREG_B1_P2_U0_CFG9 0x40011449 -#define CYREG_B1_P2_U0_CFG10 0x4001144a -#define CYREG_B1_P2_U0_CFG11 0x4001144b -#define CYREG_B1_P2_U0_CFG12 0x4001144c -#define CYREG_B1_P2_U0_CFG13 0x4001144d -#define CYREG_B1_P2_U0_CFG14 0x4001144e -#define CYREG_B1_P2_U0_CFG15 0x4001144f -#define CYREG_B1_P2_U0_CFG16 0x40011450 -#define CYREG_B1_P2_U0_CFG17 0x40011451 -#define CYREG_B1_P2_U0_CFG18 0x40011452 -#define CYREG_B1_P2_U0_CFG19 0x40011453 -#define CYREG_B1_P2_U0_CFG20 0x40011454 -#define CYREG_B1_P2_U0_CFG21 0x40011455 -#define CYREG_B1_P2_U0_CFG22 0x40011456 -#define CYREG_B1_P2_U0_CFG23 0x40011457 -#define CYREG_B1_P2_U0_CFG24 0x40011458 -#define CYREG_B1_P2_U0_CFG25 0x40011459 -#define CYREG_B1_P2_U0_CFG26 0x4001145a -#define CYREG_B1_P2_U0_CFG27 0x4001145b -#define CYREG_B1_P2_U0_CFG28 0x4001145c -#define CYREG_B1_P2_U0_CFG29 0x4001145d -#define CYREG_B1_P2_U0_CFG30 0x4001145e -#define CYREG_B1_P2_U0_CFG31 0x4001145f -#define CYREG_B1_P2_U0_DCFG0 0x40011460 -#define CYREG_B1_P2_U0_DCFG1 0x40011462 -#define CYREG_B1_P2_U0_DCFG2 0x40011464 -#define CYREG_B1_P2_U0_DCFG3 0x40011466 -#define CYREG_B1_P2_U0_DCFG4 0x40011468 -#define CYREG_B1_P2_U0_DCFG5 0x4001146a -#define CYREG_B1_P2_U0_DCFG6 0x4001146c -#define CYREG_B1_P2_U0_DCFG7 0x4001146e -#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 -#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 -#define CYREG_B1_P2_U1_PLD_IT0 0x40011480 -#define CYREG_B1_P2_U1_PLD_IT1 0x40011484 -#define CYREG_B1_P2_U1_PLD_IT2 0x40011488 -#define CYREG_B1_P2_U1_PLD_IT3 0x4001148c -#define CYREG_B1_P2_U1_PLD_IT4 0x40011490 -#define CYREG_B1_P2_U1_PLD_IT5 0x40011494 -#define CYREG_B1_P2_U1_PLD_IT6 0x40011498 -#define CYREG_B1_P2_U1_PLD_IT7 0x4001149c -#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0 -#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4 -#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8 -#define CYREG_B1_P2_U1_PLD_IT11 0x400114ac -#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0 -#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2 -#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4 -#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6 -#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 -#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114ba -#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc -#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114be -#define CYREG_B1_P2_U1_CFG0 0x400114c0 -#define CYREG_B1_P2_U1_CFG1 0x400114c1 -#define CYREG_B1_P2_U1_CFG2 0x400114c2 -#define CYREG_B1_P2_U1_CFG3 0x400114c3 -#define CYREG_B1_P2_U1_CFG4 0x400114c4 -#define CYREG_B1_P2_U1_CFG5 0x400114c5 -#define CYREG_B1_P2_U1_CFG6 0x400114c6 -#define CYREG_B1_P2_U1_CFG7 0x400114c7 -#define CYREG_B1_P2_U1_CFG8 0x400114c8 -#define CYREG_B1_P2_U1_CFG9 0x400114c9 -#define CYREG_B1_P2_U1_CFG10 0x400114ca -#define CYREG_B1_P2_U1_CFG11 0x400114cb -#define CYREG_B1_P2_U1_CFG12 0x400114cc -#define CYREG_B1_P2_U1_CFG13 0x400114cd -#define CYREG_B1_P2_U1_CFG14 0x400114ce -#define CYREG_B1_P2_U1_CFG15 0x400114cf -#define CYREG_B1_P2_U1_CFG16 0x400114d0 -#define CYREG_B1_P2_U1_CFG17 0x400114d1 -#define CYREG_B1_P2_U1_CFG18 0x400114d2 -#define CYREG_B1_P2_U1_CFG19 0x400114d3 -#define CYREG_B1_P2_U1_CFG20 0x400114d4 -#define CYREG_B1_P2_U1_CFG21 0x400114d5 -#define CYREG_B1_P2_U1_CFG22 0x400114d6 -#define CYREG_B1_P2_U1_CFG23 0x400114d7 -#define CYREG_B1_P2_U1_CFG24 0x400114d8 -#define CYREG_B1_P2_U1_CFG25 0x400114d9 -#define CYREG_B1_P2_U1_CFG26 0x400114da -#define CYREG_B1_P2_U1_CFG27 0x400114db -#define CYREG_B1_P2_U1_CFG28 0x400114dc -#define CYREG_B1_P2_U1_CFG29 0x400114dd -#define CYREG_B1_P2_U1_CFG30 0x400114de -#define CYREG_B1_P2_U1_CFG31 0x400114df -#define CYREG_B1_P2_U1_DCFG0 0x400114e0 -#define CYREG_B1_P2_U1_DCFG1 0x400114e2 -#define CYREG_B1_P2_U1_DCFG2 0x400114e4 -#define CYREG_B1_P2_U1_DCFG3 0x400114e6 -#define CYREG_B1_P2_U1_DCFG4 0x400114e8 -#define CYREG_B1_P2_U1_DCFG5 0x400114ea -#define CYREG_B1_P2_U1_DCFG6 0x400114ec -#define CYREG_B1_P2_U1_DCFG7 0x400114ee -#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 -#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_P3_BASE 0x40011600 -#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 -#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 -#define CYREG_B1_P3_U0_PLD_IT0 0x40011600 -#define CYREG_B1_P3_U0_PLD_IT1 0x40011604 -#define CYREG_B1_P3_U0_PLD_IT2 0x40011608 -#define CYREG_B1_P3_U0_PLD_IT3 0x4001160c -#define CYREG_B1_P3_U0_PLD_IT4 0x40011610 -#define CYREG_B1_P3_U0_PLD_IT5 0x40011614 -#define CYREG_B1_P3_U0_PLD_IT6 0x40011618 -#define CYREG_B1_P3_U0_PLD_IT7 0x4001161c -#define CYREG_B1_P3_U0_PLD_IT8 0x40011620 -#define CYREG_B1_P3_U0_PLD_IT9 0x40011624 -#define CYREG_B1_P3_U0_PLD_IT10 0x40011628 -#define CYREG_B1_P3_U0_PLD_IT11 0x4001162c -#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630 -#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632 -#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634 -#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636 -#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 -#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163a -#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c -#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e -#define CYREG_B1_P3_U0_CFG0 0x40011640 -#define CYREG_B1_P3_U0_CFG1 0x40011641 -#define CYREG_B1_P3_U0_CFG2 0x40011642 -#define CYREG_B1_P3_U0_CFG3 0x40011643 -#define CYREG_B1_P3_U0_CFG4 0x40011644 -#define CYREG_B1_P3_U0_CFG5 0x40011645 -#define CYREG_B1_P3_U0_CFG6 0x40011646 -#define CYREG_B1_P3_U0_CFG7 0x40011647 -#define CYREG_B1_P3_U0_CFG8 0x40011648 -#define CYREG_B1_P3_U0_CFG9 0x40011649 -#define CYREG_B1_P3_U0_CFG10 0x4001164a -#define CYREG_B1_P3_U0_CFG11 0x4001164b -#define CYREG_B1_P3_U0_CFG12 0x4001164c -#define CYREG_B1_P3_U0_CFG13 0x4001164d -#define CYREG_B1_P3_U0_CFG14 0x4001164e -#define CYREG_B1_P3_U0_CFG15 0x4001164f -#define CYREG_B1_P3_U0_CFG16 0x40011650 -#define CYREG_B1_P3_U0_CFG17 0x40011651 -#define CYREG_B1_P3_U0_CFG18 0x40011652 -#define CYREG_B1_P3_U0_CFG19 0x40011653 -#define CYREG_B1_P3_U0_CFG20 0x40011654 -#define CYREG_B1_P3_U0_CFG21 0x40011655 -#define CYREG_B1_P3_U0_CFG22 0x40011656 -#define CYREG_B1_P3_U0_CFG23 0x40011657 -#define CYREG_B1_P3_U0_CFG24 0x40011658 -#define CYREG_B1_P3_U0_CFG25 0x40011659 -#define CYREG_B1_P3_U0_CFG26 0x4001165a -#define CYREG_B1_P3_U0_CFG27 0x4001165b -#define CYREG_B1_P3_U0_CFG28 0x4001165c -#define CYREG_B1_P3_U0_CFG29 0x4001165d -#define CYREG_B1_P3_U0_CFG30 0x4001165e -#define CYREG_B1_P3_U0_CFG31 0x4001165f -#define CYREG_B1_P3_U0_DCFG0 0x40011660 -#define CYREG_B1_P3_U0_DCFG1 0x40011662 -#define CYREG_B1_P3_U0_DCFG2 0x40011664 -#define CYREG_B1_P3_U0_DCFG3 0x40011666 -#define CYREG_B1_P3_U0_DCFG4 0x40011668 -#define CYREG_B1_P3_U0_DCFG5 0x4001166a -#define CYREG_B1_P3_U0_DCFG6 0x4001166c -#define CYREG_B1_P3_U0_DCFG7 0x4001166e -#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 -#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 -#define CYREG_B1_P3_U1_PLD_IT0 0x40011680 -#define CYREG_B1_P3_U1_PLD_IT1 0x40011684 -#define CYREG_B1_P3_U1_PLD_IT2 0x40011688 -#define CYREG_B1_P3_U1_PLD_IT3 0x4001168c -#define CYREG_B1_P3_U1_PLD_IT4 0x40011690 -#define CYREG_B1_P3_U1_PLD_IT5 0x40011694 -#define CYREG_B1_P3_U1_PLD_IT6 0x40011698 -#define CYREG_B1_P3_U1_PLD_IT7 0x4001169c -#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0 -#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4 -#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8 -#define CYREG_B1_P3_U1_PLD_IT11 0x400116ac -#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0 -#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2 -#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4 -#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6 -#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 -#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116ba -#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc -#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116be -#define CYREG_B1_P3_U1_CFG0 0x400116c0 -#define CYREG_B1_P3_U1_CFG1 0x400116c1 -#define CYREG_B1_P3_U1_CFG2 0x400116c2 -#define CYREG_B1_P3_U1_CFG3 0x400116c3 -#define CYREG_B1_P3_U1_CFG4 0x400116c4 -#define CYREG_B1_P3_U1_CFG5 0x400116c5 -#define CYREG_B1_P3_U1_CFG6 0x400116c6 -#define CYREG_B1_P3_U1_CFG7 0x400116c7 -#define CYREG_B1_P3_U1_CFG8 0x400116c8 -#define CYREG_B1_P3_U1_CFG9 0x400116c9 -#define CYREG_B1_P3_U1_CFG10 0x400116ca -#define CYREG_B1_P3_U1_CFG11 0x400116cb -#define CYREG_B1_P3_U1_CFG12 0x400116cc -#define CYREG_B1_P3_U1_CFG13 0x400116cd -#define CYREG_B1_P3_U1_CFG14 0x400116ce -#define CYREG_B1_P3_U1_CFG15 0x400116cf -#define CYREG_B1_P3_U1_CFG16 0x400116d0 -#define CYREG_B1_P3_U1_CFG17 0x400116d1 -#define CYREG_B1_P3_U1_CFG18 0x400116d2 -#define CYREG_B1_P3_U1_CFG19 0x400116d3 -#define CYREG_B1_P3_U1_CFG20 0x400116d4 -#define CYREG_B1_P3_U1_CFG21 0x400116d5 -#define CYREG_B1_P3_U1_CFG22 0x400116d6 -#define CYREG_B1_P3_U1_CFG23 0x400116d7 -#define CYREG_B1_P3_U1_CFG24 0x400116d8 -#define CYREG_B1_P3_U1_CFG25 0x400116d9 -#define CYREG_B1_P3_U1_CFG26 0x400116da -#define CYREG_B1_P3_U1_CFG27 0x400116db -#define CYREG_B1_P3_U1_CFG28 0x400116dc -#define CYREG_B1_P3_U1_CFG29 0x400116dd -#define CYREG_B1_P3_U1_CFG30 0x400116de -#define CYREG_B1_P3_U1_CFG31 0x400116df -#define CYREG_B1_P3_U1_DCFG0 0x400116e0 -#define CYREG_B1_P3_U1_DCFG1 0x400116e2 -#define CYREG_B1_P3_U1_DCFG2 0x400116e4 -#define CYREG_B1_P3_U1_DCFG3 0x400116e6 -#define CYREG_B1_P3_U1_DCFG4 0x400116e8 -#define CYREG_B1_P3_U1_DCFG5 0x400116ea -#define CYREG_B1_P3_U1_DCFG6 0x400116ec -#define CYREG_B1_P3_U1_DCFG7 0x400116ee -#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 -#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_P4_BASE 0x40011800 -#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 -#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 -#define CYREG_B1_P4_U0_PLD_IT0 0x40011800 -#define CYREG_B1_P4_U0_PLD_IT1 0x40011804 -#define CYREG_B1_P4_U0_PLD_IT2 0x40011808 -#define CYREG_B1_P4_U0_PLD_IT3 0x4001180c -#define CYREG_B1_P4_U0_PLD_IT4 0x40011810 -#define CYREG_B1_P4_U0_PLD_IT5 0x40011814 -#define CYREG_B1_P4_U0_PLD_IT6 0x40011818 -#define CYREG_B1_P4_U0_PLD_IT7 0x4001181c -#define CYREG_B1_P4_U0_PLD_IT8 0x40011820 -#define CYREG_B1_P4_U0_PLD_IT9 0x40011824 -#define CYREG_B1_P4_U0_PLD_IT10 0x40011828 -#define CYREG_B1_P4_U0_PLD_IT11 0x4001182c -#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830 -#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832 -#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834 -#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836 -#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 -#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183a -#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c -#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e -#define CYREG_B1_P4_U0_CFG0 0x40011840 -#define CYREG_B1_P4_U0_CFG1 0x40011841 -#define CYREG_B1_P4_U0_CFG2 0x40011842 -#define CYREG_B1_P4_U0_CFG3 0x40011843 -#define CYREG_B1_P4_U0_CFG4 0x40011844 -#define CYREG_B1_P4_U0_CFG5 0x40011845 -#define CYREG_B1_P4_U0_CFG6 0x40011846 -#define CYREG_B1_P4_U0_CFG7 0x40011847 -#define CYREG_B1_P4_U0_CFG8 0x40011848 -#define CYREG_B1_P4_U0_CFG9 0x40011849 -#define CYREG_B1_P4_U0_CFG10 0x4001184a -#define CYREG_B1_P4_U0_CFG11 0x4001184b -#define CYREG_B1_P4_U0_CFG12 0x4001184c -#define CYREG_B1_P4_U0_CFG13 0x4001184d -#define CYREG_B1_P4_U0_CFG14 0x4001184e -#define CYREG_B1_P4_U0_CFG15 0x4001184f -#define CYREG_B1_P4_U0_CFG16 0x40011850 -#define CYREG_B1_P4_U0_CFG17 0x40011851 -#define CYREG_B1_P4_U0_CFG18 0x40011852 -#define CYREG_B1_P4_U0_CFG19 0x40011853 -#define CYREG_B1_P4_U0_CFG20 0x40011854 -#define CYREG_B1_P4_U0_CFG21 0x40011855 -#define CYREG_B1_P4_U0_CFG22 0x40011856 -#define CYREG_B1_P4_U0_CFG23 0x40011857 -#define CYREG_B1_P4_U0_CFG24 0x40011858 -#define CYREG_B1_P4_U0_CFG25 0x40011859 -#define CYREG_B1_P4_U0_CFG26 0x4001185a -#define CYREG_B1_P4_U0_CFG27 0x4001185b -#define CYREG_B1_P4_U0_CFG28 0x4001185c -#define CYREG_B1_P4_U0_CFG29 0x4001185d -#define CYREG_B1_P4_U0_CFG30 0x4001185e -#define CYREG_B1_P4_U0_CFG31 0x4001185f -#define CYREG_B1_P4_U0_DCFG0 0x40011860 -#define CYREG_B1_P4_U0_DCFG1 0x40011862 -#define CYREG_B1_P4_U0_DCFG2 0x40011864 -#define CYREG_B1_P4_U0_DCFG3 0x40011866 -#define CYREG_B1_P4_U0_DCFG4 0x40011868 -#define CYREG_B1_P4_U0_DCFG5 0x4001186a -#define CYREG_B1_P4_U0_DCFG6 0x4001186c -#define CYREG_B1_P4_U0_DCFG7 0x4001186e -#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 -#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 -#define CYREG_B1_P4_U1_PLD_IT0 0x40011880 -#define CYREG_B1_P4_U1_PLD_IT1 0x40011884 -#define CYREG_B1_P4_U1_PLD_IT2 0x40011888 -#define CYREG_B1_P4_U1_PLD_IT3 0x4001188c -#define CYREG_B1_P4_U1_PLD_IT4 0x40011890 -#define CYREG_B1_P4_U1_PLD_IT5 0x40011894 -#define CYREG_B1_P4_U1_PLD_IT6 0x40011898 -#define CYREG_B1_P4_U1_PLD_IT7 0x4001189c -#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0 -#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4 -#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8 -#define CYREG_B1_P4_U1_PLD_IT11 0x400118ac -#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0 -#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2 -#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4 -#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6 -#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 -#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118ba -#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc -#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118be -#define CYREG_B1_P4_U1_CFG0 0x400118c0 -#define CYREG_B1_P4_U1_CFG1 0x400118c1 -#define CYREG_B1_P4_U1_CFG2 0x400118c2 -#define CYREG_B1_P4_U1_CFG3 0x400118c3 -#define CYREG_B1_P4_U1_CFG4 0x400118c4 -#define CYREG_B1_P4_U1_CFG5 0x400118c5 -#define CYREG_B1_P4_U1_CFG6 0x400118c6 -#define CYREG_B1_P4_U1_CFG7 0x400118c7 -#define CYREG_B1_P4_U1_CFG8 0x400118c8 -#define CYREG_B1_P4_U1_CFG9 0x400118c9 -#define CYREG_B1_P4_U1_CFG10 0x400118ca -#define CYREG_B1_P4_U1_CFG11 0x400118cb -#define CYREG_B1_P4_U1_CFG12 0x400118cc -#define CYREG_B1_P4_U1_CFG13 0x400118cd -#define CYREG_B1_P4_U1_CFG14 0x400118ce -#define CYREG_B1_P4_U1_CFG15 0x400118cf -#define CYREG_B1_P4_U1_CFG16 0x400118d0 -#define CYREG_B1_P4_U1_CFG17 0x400118d1 -#define CYREG_B1_P4_U1_CFG18 0x400118d2 -#define CYREG_B1_P4_U1_CFG19 0x400118d3 -#define CYREG_B1_P4_U1_CFG20 0x400118d4 -#define CYREG_B1_P4_U1_CFG21 0x400118d5 -#define CYREG_B1_P4_U1_CFG22 0x400118d6 -#define CYREG_B1_P4_U1_CFG23 0x400118d7 -#define CYREG_B1_P4_U1_CFG24 0x400118d8 -#define CYREG_B1_P4_U1_CFG25 0x400118d9 -#define CYREG_B1_P4_U1_CFG26 0x400118da -#define CYREG_B1_P4_U1_CFG27 0x400118db -#define CYREG_B1_P4_U1_CFG28 0x400118dc -#define CYREG_B1_P4_U1_CFG29 0x400118dd -#define CYREG_B1_P4_U1_CFG30 0x400118de -#define CYREG_B1_P4_U1_CFG31 0x400118df -#define CYREG_B1_P4_U1_DCFG0 0x400118e0 -#define CYREG_B1_P4_U1_DCFG1 0x400118e2 -#define CYREG_B1_P4_U1_DCFG2 0x400118e4 -#define CYREG_B1_P4_U1_DCFG3 0x400118e6 -#define CYREG_B1_P4_U1_DCFG4 0x400118e8 -#define CYREG_B1_P4_U1_DCFG5 0x400118ea -#define CYREG_B1_P4_U1_DCFG6 0x400118ec -#define CYREG_B1_P4_U1_DCFG7 0x400118ee -#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 -#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 -#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef -#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 -#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 -#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00 -#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04 -#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08 -#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0c -#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10 -#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14 -#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18 -#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1c -#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20 -#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24 -#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28 -#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2c -#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30 -#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32 -#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34 -#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36 -#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 -#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a -#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c -#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e -#define CYREG_B1_P5_U0_CFG0 0x40011a40 -#define CYREG_B1_P5_U0_CFG1 0x40011a41 -#define CYREG_B1_P5_U0_CFG2 0x40011a42 -#define CYREG_B1_P5_U0_CFG3 0x40011a43 -#define CYREG_B1_P5_U0_CFG4 0x40011a44 -#define CYREG_B1_P5_U0_CFG5 0x40011a45 -#define CYREG_B1_P5_U0_CFG6 0x40011a46 -#define CYREG_B1_P5_U0_CFG7 0x40011a47 -#define CYREG_B1_P5_U0_CFG8 0x40011a48 -#define CYREG_B1_P5_U0_CFG9 0x40011a49 -#define CYREG_B1_P5_U0_CFG10 0x40011a4a -#define CYREG_B1_P5_U0_CFG11 0x40011a4b -#define CYREG_B1_P5_U0_CFG12 0x40011a4c -#define CYREG_B1_P5_U0_CFG13 0x40011a4d -#define CYREG_B1_P5_U0_CFG14 0x40011a4e -#define CYREG_B1_P5_U0_CFG15 0x40011a4f -#define CYREG_B1_P5_U0_CFG16 0x40011a50 -#define CYREG_B1_P5_U0_CFG17 0x40011a51 -#define CYREG_B1_P5_U0_CFG18 0x40011a52 -#define CYREG_B1_P5_U0_CFG19 0x40011a53 -#define CYREG_B1_P5_U0_CFG20 0x40011a54 -#define CYREG_B1_P5_U0_CFG21 0x40011a55 -#define CYREG_B1_P5_U0_CFG22 0x40011a56 -#define CYREG_B1_P5_U0_CFG23 0x40011a57 -#define CYREG_B1_P5_U0_CFG24 0x40011a58 -#define CYREG_B1_P5_U0_CFG25 0x40011a59 -#define CYREG_B1_P5_U0_CFG26 0x40011a5a -#define CYREG_B1_P5_U0_CFG27 0x40011a5b -#define CYREG_B1_P5_U0_CFG28 0x40011a5c -#define CYREG_B1_P5_U0_CFG29 0x40011a5d -#define CYREG_B1_P5_U0_CFG30 0x40011a5e -#define CYREG_B1_P5_U0_CFG31 0x40011a5f -#define CYREG_B1_P5_U0_DCFG0 0x40011a60 -#define CYREG_B1_P5_U0_DCFG1 0x40011a62 -#define CYREG_B1_P5_U0_DCFG2 0x40011a64 -#define CYREG_B1_P5_U0_DCFG3 0x40011a66 -#define CYREG_B1_P5_U0_DCFG4 0x40011a68 -#define CYREG_B1_P5_U0_DCFG5 0x40011a6a -#define CYREG_B1_P5_U0_DCFG6 0x40011a6c -#define CYREG_B1_P5_U0_DCFG7 0x40011a6e -#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 -#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 -#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80 -#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84 -#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88 -#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8c -#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90 -#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94 -#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98 -#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9c -#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0 -#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4 -#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8 -#define CYREG_B1_P5_U1_PLD_IT11 0x40011aac -#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0 -#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2 -#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4 -#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6 -#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 -#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011aba -#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc -#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe -#define CYREG_B1_P5_U1_CFG0 0x40011ac0 -#define CYREG_B1_P5_U1_CFG1 0x40011ac1 -#define CYREG_B1_P5_U1_CFG2 0x40011ac2 -#define CYREG_B1_P5_U1_CFG3 0x40011ac3 -#define CYREG_B1_P5_U1_CFG4 0x40011ac4 -#define CYREG_B1_P5_U1_CFG5 0x40011ac5 -#define CYREG_B1_P5_U1_CFG6 0x40011ac6 -#define CYREG_B1_P5_U1_CFG7 0x40011ac7 -#define CYREG_B1_P5_U1_CFG8 0x40011ac8 -#define CYREG_B1_P5_U1_CFG9 0x40011ac9 -#define CYREG_B1_P5_U1_CFG10 0x40011aca -#define CYREG_B1_P5_U1_CFG11 0x40011acb -#define CYREG_B1_P5_U1_CFG12 0x40011acc -#define CYREG_B1_P5_U1_CFG13 0x40011acd -#define CYREG_B1_P5_U1_CFG14 0x40011ace -#define CYREG_B1_P5_U1_CFG15 0x40011acf -#define CYREG_B1_P5_U1_CFG16 0x40011ad0 -#define CYREG_B1_P5_U1_CFG17 0x40011ad1 -#define CYREG_B1_P5_U1_CFG18 0x40011ad2 -#define CYREG_B1_P5_U1_CFG19 0x40011ad3 -#define CYREG_B1_P5_U1_CFG20 0x40011ad4 -#define CYREG_B1_P5_U1_CFG21 0x40011ad5 -#define CYREG_B1_P5_U1_CFG22 0x40011ad6 -#define CYREG_B1_P5_U1_CFG23 0x40011ad7 -#define CYREG_B1_P5_U1_CFG24 0x40011ad8 -#define CYREG_B1_P5_U1_CFG25 0x40011ad9 -#define CYREG_B1_P5_U1_CFG26 0x40011ada -#define CYREG_B1_P5_U1_CFG27 0x40011adb -#define CYREG_B1_P5_U1_CFG28 0x40011adc -#define CYREG_B1_P5_U1_CFG29 0x40011add -#define CYREG_B1_P5_U1_CFG30 0x40011ade -#define CYREG_B1_P5_U1_CFG31 0x40011adf -#define CYREG_B1_P5_U1_DCFG0 0x40011ae0 -#define CYREG_B1_P5_U1_DCFG1 0x40011ae2 -#define CYREG_B1_P5_U1_DCFG2 0x40011ae4 -#define CYREG_B1_P5_U1_DCFG3 0x40011ae6 -#define CYREG_B1_P5_U1_DCFG4 0x40011ae8 -#define CYREG_B1_P5_U1_DCFG5 0x40011aea -#define CYREG_B1_P5_U1_DCFG6 0x40011aec -#define CYREG_B1_P5_U1_DCFG7 0x40011aee -#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 -#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef -#define CYDEV_UCFG_DSI0_BASE 0x40014000 -#define CYDEV_UCFG_DSI0_SIZE 0x000000ef -#define CYDEV_UCFG_DSI1_BASE 0x40014100 -#define CYDEV_UCFG_DSI1_SIZE 0x000000ef -#define CYDEV_UCFG_DSI2_BASE 0x40014200 -#define CYDEV_UCFG_DSI2_SIZE 0x000000ef -#define CYDEV_UCFG_DSI3_BASE 0x40014300 -#define CYDEV_UCFG_DSI3_SIZE 0x000000ef -#define CYDEV_UCFG_DSI4_BASE 0x40014400 -#define CYDEV_UCFG_DSI4_SIZE 0x000000ef -#define CYDEV_UCFG_DSI5_BASE 0x40014500 -#define CYDEV_UCFG_DSI5_SIZE 0x000000ef -#define CYDEV_UCFG_DSI6_BASE 0x40014600 -#define CYDEV_UCFG_DSI6_SIZE 0x000000ef -#define CYDEV_UCFG_DSI7_BASE 0x40014700 -#define CYDEV_UCFG_DSI7_SIZE 0x000000ef -#define CYDEV_UCFG_DSI8_BASE 0x40014800 -#define CYDEV_UCFG_DSI8_SIZE 0x000000ef -#define CYDEV_UCFG_DSI9_BASE 0x40014900 -#define CYDEV_UCFG_DSI9_SIZE 0x000000ef -#define CYDEV_UCFG_DSI12_BASE 0x40014c00 -#define CYDEV_UCFG_DSI12_SIZE 0x000000ef -#define CYDEV_UCFG_DSI13_BASE 0x40014d00 -#define CYDEV_UCFG_DSI13_SIZE 0x000000ef -#define CYDEV_UCFG_BCTL0_BASE 0x40015000 -#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 -#define CYREG_BCTL0_MDCLK_EN 0x40015000 -#define CYREG_BCTL0_MBCLK_EN 0x40015001 -#define CYREG_BCTL0_WAIT_CFG 0x40015002 -#define CYREG_BCTL0_BANK_CTL 0x40015003 -#define CYREG_BCTL0_UDB_TEST_3 0x40015007 -#define CYREG_BCTL0_DCLK_EN0 0x40015008 -#define CYREG_BCTL0_BCLK_EN0 0x40015009 -#define CYREG_BCTL0_DCLK_EN1 0x4001500a -#define CYREG_BCTL0_BCLK_EN1 0x4001500b -#define CYREG_BCTL0_DCLK_EN2 0x4001500c -#define CYREG_BCTL0_BCLK_EN2 0x4001500d -#define CYREG_BCTL0_DCLK_EN3 0x4001500e -#define CYREG_BCTL0_BCLK_EN3 0x4001500f -#define CYDEV_UCFG_BCTL1_BASE 0x40015010 -#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 -#define CYREG_BCTL1_MDCLK_EN 0x40015010 -#define CYREG_BCTL1_MBCLK_EN 0x40015011 -#define CYREG_BCTL1_WAIT_CFG 0x40015012 -#define CYREG_BCTL1_BANK_CTL 0x40015013 -#define CYREG_BCTL1_UDB_TEST_3 0x40015017 -#define CYREG_BCTL1_DCLK_EN0 0x40015018 -#define CYREG_BCTL1_BCLK_EN0 0x40015019 -#define CYREG_BCTL1_DCLK_EN1 0x4001501a -#define CYREG_BCTL1_BCLK_EN1 0x4001501b -#define CYREG_BCTL1_DCLK_EN2 0x4001501c -#define CYREG_BCTL1_BCLK_EN2 0x4001501d -#define CYREG_BCTL1_DCLK_EN3 0x4001501e -#define CYREG_BCTL1_BCLK_EN3 0x4001501f -#define CYDEV_IDMUX_BASE 0x40015100 -#define CYDEV_IDMUX_SIZE 0x00000016 -#define CYREG_IDMUX_IRQ_CTL0 0x40015100 -#define CYREG_IDMUX_IRQ_CTL1 0x40015101 -#define CYREG_IDMUX_IRQ_CTL2 0x40015102 -#define CYREG_IDMUX_IRQ_CTL3 0x40015103 -#define CYREG_IDMUX_IRQ_CTL4 0x40015104 -#define CYREG_IDMUX_IRQ_CTL5 0x40015105 -#define CYREG_IDMUX_IRQ_CTL6 0x40015106 -#define CYREG_IDMUX_IRQ_CTL7 0x40015107 -#define CYREG_IDMUX_DRQ_CTL0 0x40015110 -#define CYREG_IDMUX_DRQ_CTL1 0x40015111 -#define CYREG_IDMUX_DRQ_CTL2 0x40015112 -#define CYREG_IDMUX_DRQ_CTL3 0x40015113 -#define CYREG_IDMUX_DRQ_CTL4 0x40015114 -#define CYREG_IDMUX_DRQ_CTL5 0x40015115 -#define CYDEV_CACHERAM_BASE 0x40030000 -#define CYDEV_CACHERAM_SIZE 0x00000400 -#define CYREG_CACHERAM_DATA_MBASE 0x40030000 -#define CYREG_CACHERAM_DATA_MSIZE 0x00000400 -#define CYDEV_SFR_BASE 0x40050100 -#define CYDEV_SFR_SIZE 0x000000fb -#define CYREG_SFR_GPIO0 0x40050180 -#define CYREG_SFR_GPIRD0 0x40050189 -#define CYREG_SFR_GPIO0_SEL 0x4005018a -#define CYREG_SFR_GPIO1 0x40050190 -#define CYREG_SFR_GPIRD1 0x40050191 -#define CYREG_SFR_GPIO2 0x40050198 -#define CYREG_SFR_GPIRD2 0x40050199 -#define CYREG_SFR_GPIO2_SEL 0x4005019a -#define CYREG_SFR_GPIO1_SEL 0x400501a2 -#define CYREG_SFR_GPIO3 0x400501b0 -#define CYREG_SFR_GPIRD3 0x400501b1 -#define CYREG_SFR_GPIO3_SEL 0x400501b2 -#define CYREG_SFR_GPIO4 0x400501c0 -#define CYREG_SFR_GPIRD4 0x400501c1 -#define CYREG_SFR_GPIO4_SEL 0x400501c2 -#define CYREG_SFR_GPIO5 0x400501c8 -#define CYREG_SFR_GPIRD5 0x400501c9 -#define CYREG_SFR_GPIO5_SEL 0x400501ca -#define CYREG_SFR_GPIO6 0x400501d8 -#define CYREG_SFR_GPIRD6 0x400501d9 -#define CYREG_SFR_GPIO6_SEL 0x400501da -#define CYREG_SFR_GPIO12 0x400501e8 -#define CYREG_SFR_GPIRD12 0x400501e9 -#define CYREG_SFR_GPIO12_SEL 0x400501f2 -#define CYREG_SFR_GPIO15 0x400501f8 -#define CYREG_SFR_GPIRD15 0x400501f9 -#define CYREG_SFR_GPIO15_SEL 0x400501fa -#define CYDEV_P3BA_BASE 0x40050300 -#define CYDEV_P3BA_SIZE 0x0000002b -#define CYREG_P3BA_Y_START 0x40050300 -#define CYREG_P3BA_YROLL 0x40050301 -#define CYREG_P3BA_YCFG 0x40050302 -#define CYREG_P3BA_X_START1 0x40050303 -#define CYREG_P3BA_X_START2 0x40050304 -#define CYREG_P3BA_XROLL1 0x40050305 -#define CYREG_P3BA_XROLL2 0x40050306 -#define CYREG_P3BA_XINC 0x40050307 -#define CYREG_P3BA_XCFG 0x40050308 -#define CYREG_P3BA_OFFSETADDR1 0x40050309 -#define CYREG_P3BA_OFFSETADDR2 0x4005030a -#define CYREG_P3BA_OFFSETADDR3 0x4005030b -#define CYREG_P3BA_ABSADDR1 0x4005030c -#define CYREG_P3BA_ABSADDR2 0x4005030d -#define CYREG_P3BA_ABSADDR3 0x4005030e -#define CYREG_P3BA_ABSADDR4 0x4005030f -#define CYREG_P3BA_DATCFG1 0x40050310 -#define CYREG_P3BA_DATCFG2 0x40050311 -#define CYREG_P3BA_CMP_RSLT1 0x40050314 -#define CYREG_P3BA_CMP_RSLT2 0x40050315 -#define CYREG_P3BA_CMP_RSLT3 0x40050316 -#define CYREG_P3BA_CMP_RSLT4 0x40050317 -#define CYREG_P3BA_DATA_REG1 0x40050318 -#define CYREG_P3BA_DATA_REG2 0x40050319 -#define CYREG_P3BA_DATA_REG3 0x4005031a -#define CYREG_P3BA_DATA_REG4 0x4005031b -#define CYREG_P3BA_EXP_DATA1 0x4005031c -#define CYREG_P3BA_EXP_DATA2 0x4005031d -#define CYREG_P3BA_EXP_DATA3 0x4005031e -#define CYREG_P3BA_EXP_DATA4 0x4005031f -#define CYREG_P3BA_MSTR_HRDATA1 0x40050320 -#define CYREG_P3BA_MSTR_HRDATA2 0x40050321 -#define CYREG_P3BA_MSTR_HRDATA3 0x40050322 -#define CYREG_P3BA_MSTR_HRDATA4 0x40050323 -#define CYREG_P3BA_BIST_EN 0x40050324 -#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325 -#define CYREG_P3BA_SEQCFG1 0x40050326 -#define CYREG_P3BA_SEQCFG2 0x40050327 -#define CYREG_P3BA_Y_CURR 0x40050328 -#define CYREG_P3BA_X_CURR1 0x40050329 -#define CYREG_P3BA_X_CURR2 0x4005032a -#define CYDEV_PANTHER_BASE 0x40080000 -#define CYDEV_PANTHER_SIZE 0x00000020 -#define CYREG_PANTHER_STCALIB_CFG 0x40080000 -#define CYREG_PANTHER_WAITPIPE 0x40080004 -#define CYREG_PANTHER_TRACE_CFG 0x40080008 -#define CYREG_PANTHER_DBG_CFG 0x4008000c -#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018 -#define CYREG_PANTHER_DEVICE_ID 0x4008001c -#define CYDEV_FLSECC_BASE 0x48000000 -#define CYDEV_FLSECC_SIZE 0x00008000 -#define CYREG_FLSECC_DATA_MBASE 0x48000000 -#define CYREG_FLSECC_DATA_MSIZE 0x00008000 -#define CYDEV_FLSHID_BASE 0x49000000 -#define CYDEV_FLSHID_SIZE 0x00000200 -#define CYREG_FLSHID_RSVD_MBASE 0x49000000 -#define CYREG_FLSHID_RSVD_MSIZE 0x00000080 -#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080 -#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080 -#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 -#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 -#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100 -#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101 -#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 -#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 -#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 -#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105 -#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106 -#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107 -#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 -#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 -#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a -#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b -#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c -#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d -#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e -#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010f -#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 -#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 -#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 -#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 -#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 -#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 -#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 -#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 -#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118 -#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119 -#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011a -#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011b -#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011c -#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011d -#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011e -#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011f -#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 -#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 -#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 -#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 -#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 -#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 -#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 -#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 -#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 -#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 -#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a -#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b -#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c -#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d -#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e -#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f -#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 -#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 -#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 -#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 -#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 -#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 -#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 -#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 -#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 -#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 -#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a -#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b -#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c -#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d -#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e -#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f -#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 -#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 -#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188 -#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac -#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae -#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 -#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 -#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 -#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 -#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 -#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba -#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce -#define CYDEV_EXTMEM_BASE 0x60000000 -#define CYDEV_EXTMEM_SIZE 0x00800000 -#define CYREG_EXTMEM_DATA_MBASE 0x60000000 -#define CYREG_EXTMEM_DATA_MSIZE 0x00800000 -#define CYDEV_ITM_BASE 0xe0000000 -#define CYDEV_ITM_SIZE 0x00001000 -#define CYREG_ITM_TRACE_EN 0xe0000e00 -#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40 -#define CYREG_ITM_TRACE_CTRL 0xe0000e80 -#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0 -#define CYREG_ITM_LOCK_STATUS 0xe0000fb4 -#define CYREG_ITM_PID4 0xe0000fd0 -#define CYREG_ITM_PID5 0xe0000fd4 -#define CYREG_ITM_PID6 0xe0000fd8 -#define CYREG_ITM_PID7 0xe0000fdc -#define CYREG_ITM_PID0 0xe0000fe0 -#define CYREG_ITM_PID1 0xe0000fe4 -#define CYREG_ITM_PID2 0xe0000fe8 -#define CYREG_ITM_PID3 0xe0000fec -#define CYREG_ITM_CID0 0xe0000ff0 -#define CYREG_ITM_CID1 0xe0000ff4 -#define CYREG_ITM_CID2 0xe0000ff8 -#define CYREG_ITM_CID3 0xe0000ffc -#define CYDEV_DWT_BASE 0xe0001000 -#define CYDEV_DWT_SIZE 0x0000005c -#define CYREG_DWT_CTRL 0xe0001000 -#define CYREG_DWT_CYCLE_COUNT 0xe0001004 -#define CYREG_DWT_CPI_COUNT 0xe0001008 -#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100c -#define CYREG_DWT_SLEEP_COUNT 0xe0001010 -#define CYREG_DWT_LSU_COUNT 0xe0001014 -#define CYREG_DWT_FOLD_COUNT 0xe0001018 -#define CYREG_DWT_PC_SAMPLE 0xe000101c -#define CYREG_DWT_COMP_0 0xe0001020 -#define CYREG_DWT_MASK_0 0xe0001024 -#define CYREG_DWT_FUNCTION_0 0xe0001028 -#define CYREG_DWT_COMP_1 0xe0001030 -#define CYREG_DWT_MASK_1 0xe0001034 -#define CYREG_DWT_FUNCTION_1 0xe0001038 -#define CYREG_DWT_COMP_2 0xe0001040 -#define CYREG_DWT_MASK_2 0xe0001044 -#define CYREG_DWT_FUNCTION_2 0xe0001048 -#define CYREG_DWT_COMP_3 0xe0001050 -#define CYREG_DWT_MASK_3 0xe0001054 -#define CYREG_DWT_FUNCTION_3 0xe0001058 -#define CYDEV_FPB_BASE 0xe0002000 -#define CYDEV_FPB_SIZE 0x00001000 -#define CYREG_FPB_CTRL 0xe0002000 -#define CYREG_FPB_REMAP 0xe0002004 -#define CYREG_FPB_FP_COMP_0 0xe0002008 -#define CYREG_FPB_FP_COMP_1 0xe000200c -#define CYREG_FPB_FP_COMP_2 0xe0002010 -#define CYREG_FPB_FP_COMP_3 0xe0002014 -#define CYREG_FPB_FP_COMP_4 0xe0002018 -#define CYREG_FPB_FP_COMP_5 0xe000201c -#define CYREG_FPB_FP_COMP_6 0xe0002020 -#define CYREG_FPB_FP_COMP_7 0xe0002024 -#define CYREG_FPB_PID4 0xe0002fd0 -#define CYREG_FPB_PID5 0xe0002fd4 -#define CYREG_FPB_PID6 0xe0002fd8 -#define CYREG_FPB_PID7 0xe0002fdc -#define CYREG_FPB_PID0 0xe0002fe0 -#define CYREG_FPB_PID1 0xe0002fe4 -#define CYREG_FPB_PID2 0xe0002fe8 -#define CYREG_FPB_PID3 0xe0002fec -#define CYREG_FPB_CID0 0xe0002ff0 -#define CYREG_FPB_CID1 0xe0002ff4 -#define CYREG_FPB_CID2 0xe0002ff8 -#define CYREG_FPB_CID3 0xe0002ffc -#define CYDEV_NVIC_BASE 0xe000e000 -#define CYDEV_NVIC_SIZE 0x00000d3c -#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004 -#define CYREG_NVIC_SYSTICK_CTL 0xe000e010 -#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014 -#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018 -#define CYREG_NVIC_SYSTICK_CAL 0xe000e01c -#define CYREG_NVIC_SETENA0 0xe000e100 -#define CYREG_NVIC_CLRENA0 0xe000e180 -#define CYREG_NVIC_SETPEND0 0xe000e200 -#define CYREG_NVIC_CLRPEND0 0xe000e280 -#define CYREG_NVIC_ACTIVE0 0xe000e300 -#define CYREG_NVIC_PRI_0 0xe000e400 -#define CYREG_NVIC_PRI_1 0xe000e401 -#define CYREG_NVIC_PRI_2 0xe000e402 -#define CYREG_NVIC_PRI_3 0xe000e403 -#define CYREG_NVIC_PRI_4 0xe000e404 -#define CYREG_NVIC_PRI_5 0xe000e405 -#define CYREG_NVIC_PRI_6 0xe000e406 -#define CYREG_NVIC_PRI_7 0xe000e407 -#define CYREG_NVIC_PRI_8 0xe000e408 -#define CYREG_NVIC_PRI_9 0xe000e409 -#define CYREG_NVIC_PRI_10 0xe000e40a -#define CYREG_NVIC_PRI_11 0xe000e40b -#define CYREG_NVIC_PRI_12 0xe000e40c -#define CYREG_NVIC_PRI_13 0xe000e40d -#define CYREG_NVIC_PRI_14 0xe000e40e -#define CYREG_NVIC_PRI_15 0xe000e40f -#define CYREG_NVIC_PRI_16 0xe000e410 -#define CYREG_NVIC_PRI_17 0xe000e411 -#define CYREG_NVIC_PRI_18 0xe000e412 -#define CYREG_NVIC_PRI_19 0xe000e413 -#define CYREG_NVIC_PRI_20 0xe000e414 -#define CYREG_NVIC_PRI_21 0xe000e415 -#define CYREG_NVIC_PRI_22 0xe000e416 -#define CYREG_NVIC_PRI_23 0xe000e417 -#define CYREG_NVIC_PRI_24 0xe000e418 -#define CYREG_NVIC_PRI_25 0xe000e419 -#define CYREG_NVIC_PRI_26 0xe000e41a -#define CYREG_NVIC_PRI_27 0xe000e41b -#define CYREG_NVIC_PRI_28 0xe000e41c -#define CYREG_NVIC_PRI_29 0xe000e41d -#define CYREG_NVIC_PRI_30 0xe000e41e -#define CYREG_NVIC_PRI_31 0xe000e41f -#define CYREG_NVIC_CPUID_BASE 0xe000ed00 -#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04 -#define CYREG_NVIC_VECT_OFFSET 0xe000ed08 -#define CYREG_NVIC_APPLN_INTR 0xe000ed0c -#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10 -#define CYREG_NVIC_CFG_CONTROL 0xe000ed14 -#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 -#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c -#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 -#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24 -#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 -#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29 -#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2a -#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2c -#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 -#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 -#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38 -#define CYDEV_CORE_DBG_BASE 0xe000edf0 -#define CYDEV_CORE_DBG_SIZE 0x00000010 -#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0 -#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4 -#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8 -#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfc -#define CYDEV_TPIU_BASE 0xe0040000 -#define CYDEV_TPIU_SIZE 0x00001000 -#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 -#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 -#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 -#define CYREG_TPIU_PROTOCOL 0xe00400f0 -#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300 -#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304 -#define CYREG_TPIU_TRIGGER 0xe0040ee8 -#define CYREG_TPIU_ITETMDATA 0xe0040eec -#define CYREG_TPIU_ITATBCTR2 0xe0040ef0 -#define CYREG_TPIU_ITATBCTR0 0xe0040ef8 -#define CYREG_TPIU_ITITMDATA 0xe0040efc -#define CYREG_TPIU_ITCTRL 0xe0040f00 -#define CYREG_TPIU_DEVID 0xe0040fc8 -#define CYREG_TPIU_DEVTYPE 0xe0040fcc -#define CYREG_TPIU_PID4 0xe0040fd0 -#define CYREG_TPIU_PID5 0xe0040fd4 -#define CYREG_TPIU_PID6 0xe0040fd8 -#define CYREG_TPIU_PID7 0xe0040fdc -#define CYREG_TPIU_PID0 0xe0040fe0 -#define CYREG_TPIU_PID1 0xe0040fe4 -#define CYREG_TPIU_PID2 0xe0040fe8 -#define CYREG_TPIU_PID3 0xe0040fec -#define CYREG_TPIU_CID0 0xe0040ff0 -#define CYREG_TPIU_CID1 0xe0040ff4 -#define CYREG_TPIU_CID2 0xe0040ff8 -#define CYREG_TPIU_CID3 0xe0040ffc -#define CYDEV_ETM_BASE 0xe0041000 -#define CYDEV_ETM_SIZE 0x00001000 -#define CYREG_ETM_CTL 0xe0041000 -#define CYREG_ETM_CFG_CODE 0xe0041004 -#define CYREG_ETM_TRIG_EVENT 0xe0041008 -#define CYREG_ETM_STATUS 0xe0041010 -#define CYREG_ETM_SYS_CFG 0xe0041014 -#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020 -#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024 -#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102c -#define CYREG_ETM_SYNC_FREQ 0xe00411e0 -#define CYREG_ETM_ETM_ID 0xe00411e4 -#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8 -#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 -#define CYREG_ETM_CS_TRACE_ID 0xe0041200 -#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300 -#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304 -#define CYREG_ETM_PDSR 0xe0041314 -#define CYREG_ETM_ITMISCIN 0xe0041ee0 -#define CYREG_ETM_ITTRIGOUT 0xe0041ee8 -#define CYREG_ETM_ITATBCTR2 0xe0041ef0 -#define CYREG_ETM_ITATBCTR0 0xe0041ef8 -#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00 -#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0 -#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4 -#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0 -#define CYREG_ETM_LOCK_STATUS 0xe0041fb4 -#define CYREG_ETM_AUTH_STATUS 0xe0041fb8 -#define CYREG_ETM_DEV_TYPE 0xe0041fcc -#define CYREG_ETM_PID4 0xe0041fd0 -#define CYREG_ETM_PID5 0xe0041fd4 -#define CYREG_ETM_PID6 0xe0041fd8 -#define CYREG_ETM_PID7 0xe0041fdc -#define CYREG_ETM_PID0 0xe0041fe0 -#define CYREG_ETM_PID1 0xe0041fe4 -#define CYREG_ETM_PID2 0xe0041fe8 -#define CYREG_ETM_PID3 0xe0041fec -#define CYREG_ETM_CID0 0xe0041ff0 -#define CYREG_ETM_CID1 0xe0041ff4 -#define CYREG_ETM_CID2 0xe0041ff8 -#define CYREG_ETM_CID3 0xe0041ffc -#define CYDEV_ROM_TABLE_BASE 0xe00ff000 -#define CYDEV_ROM_TABLE_SIZE 0x00001000 -#define CYREG_ROM_TABLE_NVIC 0xe00ff000 -#define CYREG_ROM_TABLE_DWT 0xe00ff004 -#define CYREG_ROM_TABLE_FPB 0xe00ff008 -#define CYREG_ROM_TABLE_ITM 0xe00ff00c -#define CYREG_ROM_TABLE_TPIU 0xe00ff010 -#define CYREG_ROM_TABLE_ETM 0xe00ff014 -#define CYREG_ROM_TABLE_END 0xe00ff018 -#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffcc -#define CYREG_ROM_TABLE_PID4 0xe00fffd0 -#define CYREG_ROM_TABLE_PID5 0xe00fffd4 -#define CYREG_ROM_TABLE_PID6 0xe00fffd8 -#define CYREG_ROM_TABLE_PID7 0xe00fffdc -#define CYREG_ROM_TABLE_PID0 0xe00fffe0 -#define CYREG_ROM_TABLE_PID1 0xe00fffe4 -#define CYREG_ROM_TABLE_PID2 0xe00fffe8 -#define CYREG_ROM_TABLE_PID3 0xe00fffec -#define CYREG_ROM_TABLE_CID0 0xe00ffff0 -#define CYREG_ROM_TABLE_CID1 0xe00ffff4 -#define CYREG_ROM_TABLE_CID2 0xe00ffff8 -#define CYREG_ROM_TABLE_CID3 0xe00ffffc -#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE -#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE -#define CYDEV_FLS_SECTOR_SIZE 0x00010000 -#define CYDEV_FLS_ROW_SIZE 0x00000100 -#define CYDEV_ECC_SECTOR_SIZE 0x00002000 -#define CYDEV_ECC_ROW_SIZE 0x00000020 -#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 -#define CYDEV_EEPROM_ROW_SIZE 0x00000010 -#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE -#define CYCLK_LD_DISABLE 0x00000004 -#define CYCLK_LD_SYNC_EN 0x00000002 -#define CYCLK_LD_LOAD 0x00000001 -#define CYCLK_PIPE 0x00000080 -#define CYCLK_SSS 0x00000040 -#define CYCLK_EARLY 0x00000020 -#define CYCLK_DUTY 0x00000010 -#define CYCLK_SYNC 0x00000008 -#define CYCLK_SRC_SEL_CLK_SYNC_D 0 -#define CYCLK_SRC_SEL_SYNC_DIG 0 -#define CYCLK_SRC_SEL_IMO 1 -#define CYCLK_SRC_SEL_XTAL_MHZ 2 -#define CYCLK_SRC_SEL_XTALM 2 -#define CYCLK_SRC_SEL_ILO 3 -#define CYCLK_SRC_SEL_PLL 4 -#define CYCLK_SRC_SEL_XTAL_KHZ 5 -#define CYCLK_SRC_SEL_XTALK 5 -#define CYCLK_SRC_SEL_DSI_G 6 -#define CYCLK_SRC_SEL_DSI_D 7 -#define CYCLK_SRC_SEL_CLK_SYNC_A 0 -#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc deleted file mode 100755 index 4ed74ed..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv.inc +++ /dev/null @@ -1,16039 +0,0 @@ -; -; FILENAME: cydevicerv.inc -; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.0 Component Pack 7 -; -; DESCRIPTION: -; This file provides all of the address values for the entire PSoC device. -; -;------------------------------------------------------------------------------- -; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying -; the software package with which this file was provided. -;------------------------------------------------------------------------------- - - IF :LNOT::DEF:CYDEV_FLASH_BASE -CYDEV_FLASH_BASE EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLASH_SIZE -CYDEV_FLASH_SIZE EQU 0x00020000 - ENDIF - IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE -CYDEV_FLASH_DATA_MBASE EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE -CYDEV_FLASH_DATA_MSIZE EQU 0x00020000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_BASE -CYDEV_SRAM_BASE EQU 0x1fffc000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_SIZE -CYDEV_SRAM_SIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE -CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE -CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE -CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE -CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE -CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE -CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE -CYDEV_SRAM_CODE_MBASE EQU 0x1fffc000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE -CYDEV_SRAM_CODE_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE -CYDEV_SRAM_DATA_MBASE EQU 0x20000000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE -CYDEV_SRAM_DATA_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE -CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE -CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE -CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE -CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE -CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE -CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_BASE -CYDEV_DMA_BASE EQU 0x20008000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SIZE -CYDEV_DMA_SIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE -CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE -CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE -CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE -CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE -CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE -CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE -CYDEV_DMA_SRAM_MBASE EQU 0x2000f000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE -CYDEV_DMA_SRAM_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_BASE -CYDEV_CLKDIST_BASE EQU 0x40004000 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_SIZE -CYDEV_CLKDIST_SIZE EQU 0x00000110 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_CR -CYDEV_CLKDIST_CR EQU 0x40004000 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_LD -CYDEV_CLKDIST_LD EQU 0x40004001 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_WRK0 -CYDEV_CLKDIST_WRK0 EQU 0x40004002 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_WRK1 -CYDEV_CLKDIST_WRK1 EQU 0x40004003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0 -CYDEV_CLKDIST_MSTR0 EQU 0x40004004 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1 -CYDEV_CLKDIST_MSTR1 EQU 0x40004005 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0 -CYDEV_CLKDIST_BCFG0 EQU 0x40004006 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1 -CYDEV_CLKDIST_BCFG1 EQU 0x40004007 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2 -CYDEV_CLKDIST_BCFG2 EQU 0x40004008 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_UCFG -CYDEV_CLKDIST_UCFG EQU 0x40004009 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DLY0 -CYDEV_CLKDIST_DLY0 EQU 0x4000400a - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DLY1 -CYDEV_CLKDIST_DLY1 EQU 0x4000400b - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DMASK -CYDEV_CLKDIST_DMASK EQU 0x40004010 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_AMASK -CYDEV_CLKDIST_AMASK EQU 0x40004014 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE -CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE -CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0 -CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1 -CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2 -CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE -CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE -CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0 -CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1 -CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2 -CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE -CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE -CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0 -CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1 -CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2 -CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE -CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE -CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0 -CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1 -CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2 -CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE -CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE -CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0 -CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1 -CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2 -CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE -CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE -CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0 -CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1 -CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2 -CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE -CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE -CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0 -CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1 -CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2 -CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE -CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE -CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0 -CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1 -CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2 -CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE -CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE -CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0 -CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1 -CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2 -CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3 -CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE -CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE -CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0 -CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1 -CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2 -CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3 -CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE -CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE -CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0 -CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1 -CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2 -CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3 -CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE -CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE -CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0 -CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1 -CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2 -CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3 -CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_BASE -CYDEV_FASTCLK_BASE EQU 0x40004200 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_SIZE -CYDEV_FASTCLK_SIZE EQU 0x00000026 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE -CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE -CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR -CYDEV_FASTCLK_IMO_CR EQU 0x40004200 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE -CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE -CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR -CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0 -CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1 -CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE -CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE -CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0 -CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1 -CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P -CYDEV_FASTCLK_PLL_P EQU 0x40004222 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q -CYDEV_FASTCLK_PLL_Q EQU 0x40004223 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR -CYDEV_FASTCLK_PLL_SR EQU 0x40004225 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_BASE -CYDEV_SLOWCLK_BASE EQU 0x40004300 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE -CYDEV_SLOWCLK_SIZE EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE -CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE -CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0 -CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1 -CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE -CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE -CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR -CYDEV_SLOWCLK_X32_CR EQU 0x40004308 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG -CYDEV_SLOWCLK_X32_CFG EQU 0x40004309 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST -CYDEV_SLOWCLK_X32_TST EQU 0x4000430a - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_BASE -CYDEV_BOOST_BASE EQU 0x40004320 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_SIZE -CYDEV_BOOST_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_CR0 -CYDEV_BOOST_CR0 EQU 0x40004320 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_CR1 -CYDEV_BOOST_CR1 EQU 0x40004321 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_CR2 -CYDEV_BOOST_CR2 EQU 0x40004322 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_CR3 -CYDEV_BOOST_CR3 EQU 0x40004323 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_SR -CYDEV_BOOST_SR EQU 0x40004324 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_CR4 -CYDEV_BOOST_CR4 EQU 0x40004325 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_SR2 -CYDEV_BOOST_SR2 EQU 0x40004326 - ENDIF - IF :LNOT::DEF:CYDEV_PWRSYS_BASE -CYDEV_PWRSYS_BASE EQU 0x40004330 - ENDIF - IF :LNOT::DEF:CYDEV_PWRSYS_SIZE -CYDEV_PWRSYS_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_PWRSYS_CR0 -CYDEV_PWRSYS_CR0 EQU 0x40004330 - ENDIF - IF :LNOT::DEF:CYDEV_PWRSYS_CR1 -CYDEV_PWRSYS_CR1 EQU 0x40004331 - ENDIF - IF :LNOT::DEF:CYDEV_PM_BASE -CYDEV_PM_BASE EQU 0x40004380 - ENDIF - IF :LNOT::DEF:CYDEV_PM_SIZE -CYDEV_PM_SIZE EQU 0x00000057 - ENDIF - IF :LNOT::DEF:CYDEV_PM_TW_CFG0 -CYDEV_PM_TW_CFG0 EQU 0x40004380 - ENDIF - IF :LNOT::DEF:CYDEV_PM_TW_CFG1 -CYDEV_PM_TW_CFG1 EQU 0x40004381 - ENDIF - IF :LNOT::DEF:CYDEV_PM_TW_CFG2 -CYDEV_PM_TW_CFG2 EQU 0x40004382 - ENDIF - IF :LNOT::DEF:CYDEV_PM_WDT_CFG -CYDEV_PM_WDT_CFG EQU 0x40004383 - ENDIF - IF :LNOT::DEF:CYDEV_PM_WDT_CR -CYDEV_PM_WDT_CR EQU 0x40004384 - ENDIF - IF :LNOT::DEF:CYDEV_PM_INT_SR -CYDEV_PM_INT_SR EQU 0x40004390 - ENDIF - IF :LNOT::DEF:CYDEV_PM_MODE_CFG0 -CYDEV_PM_MODE_CFG0 EQU 0x40004391 - ENDIF - IF :LNOT::DEF:CYDEV_PM_MODE_CFG1 -CYDEV_PM_MODE_CFG1 EQU 0x40004392 - ENDIF - IF :LNOT::DEF:CYDEV_PM_MODE_CSR -CYDEV_PM_MODE_CSR EQU 0x40004393 - ENDIF - IF :LNOT::DEF:CYDEV_PM_USB_CR0 -CYDEV_PM_USB_CR0 EQU 0x40004394 - ENDIF - IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0 -CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398 - ENDIF - IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1 -CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399 - ENDIF - IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2 -CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_BASE -CYDEV_PM_ACT_BASE EQU 0x400043a0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_SIZE -CYDEV_PM_ACT_SIZE EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG0 -CYDEV_PM_ACT_CFG0 EQU 0x400043a0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG1 -CYDEV_PM_ACT_CFG1 EQU 0x400043a1 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG2 -CYDEV_PM_ACT_CFG2 EQU 0x400043a2 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG3 -CYDEV_PM_ACT_CFG3 EQU 0x400043a3 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG4 -CYDEV_PM_ACT_CFG4 EQU 0x400043a4 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG5 -CYDEV_PM_ACT_CFG5 EQU 0x400043a5 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG6 -CYDEV_PM_ACT_CFG6 EQU 0x400043a6 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG7 -CYDEV_PM_ACT_CFG7 EQU 0x400043a7 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG8 -CYDEV_PM_ACT_CFG8 EQU 0x400043a8 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG9 -CYDEV_PM_ACT_CFG9 EQU 0x400043a9 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG10 -CYDEV_PM_ACT_CFG10 EQU 0x400043aa - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG11 -CYDEV_PM_ACT_CFG11 EQU 0x400043ab - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG12 -CYDEV_PM_ACT_CFG12 EQU 0x400043ac - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_CFG13 -CYDEV_PM_ACT_CFG13 EQU 0x400043ad - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_BASE -CYDEV_PM_STBY_BASE EQU 0x400043b0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_SIZE -CYDEV_PM_STBY_SIZE EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG0 -CYDEV_PM_STBY_CFG0 EQU 0x400043b0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG1 -CYDEV_PM_STBY_CFG1 EQU 0x400043b1 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG2 -CYDEV_PM_STBY_CFG2 EQU 0x400043b2 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG3 -CYDEV_PM_STBY_CFG3 EQU 0x400043b3 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG4 -CYDEV_PM_STBY_CFG4 EQU 0x400043b4 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG5 -CYDEV_PM_STBY_CFG5 EQU 0x400043b5 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG6 -CYDEV_PM_STBY_CFG6 EQU 0x400043b6 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG7 -CYDEV_PM_STBY_CFG7 EQU 0x400043b7 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG8 -CYDEV_PM_STBY_CFG8 EQU 0x400043b8 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG9 -CYDEV_PM_STBY_CFG9 EQU 0x400043b9 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG10 -CYDEV_PM_STBY_CFG10 EQU 0x400043ba - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG11 -CYDEV_PM_STBY_CFG11 EQU 0x400043bb - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG12 -CYDEV_PM_STBY_CFG12 EQU 0x400043bc - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_CFG13 -CYDEV_PM_STBY_CFG13 EQU 0x400043bd - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE -CYDEV_PM_AVAIL_BASE EQU 0x400043c0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE -CYDEV_PM_AVAIL_SIZE EQU 0x00000017 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0 -CYDEV_PM_AVAIL_CR0 EQU 0x400043c0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1 -CYDEV_PM_AVAIL_CR1 EQU 0x400043c1 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2 -CYDEV_PM_AVAIL_CR2 EQU 0x400043c2 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3 -CYDEV_PM_AVAIL_CR3 EQU 0x400043c3 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4 -CYDEV_PM_AVAIL_CR4 EQU 0x400043c4 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5 -CYDEV_PM_AVAIL_CR5 EQU 0x400043c5 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6 -CYDEV_PM_AVAIL_CR6 EQU 0x400043c6 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0 -CYDEV_PM_AVAIL_SR0 EQU 0x400043d0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1 -CYDEV_PM_AVAIL_SR1 EQU 0x400043d1 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2 -CYDEV_PM_AVAIL_SR2 EQU 0x400043d2 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3 -CYDEV_PM_AVAIL_SR3 EQU 0x400043d3 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4 -CYDEV_PM_AVAIL_SR4 EQU 0x400043d4 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5 -CYDEV_PM_AVAIL_SR5 EQU 0x400043d5 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6 -CYDEV_PM_AVAIL_SR6 EQU 0x400043d6 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_BASE -CYDEV_PICU_BASE EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SIZE -CYDEV_PICU_SIZE EQU 0x000000b0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE -CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE -CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE -CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE -CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE -CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE -CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE -CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE -CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE -CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE -CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE -CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE -CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE -CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE -CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE -CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE -CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE -CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE -CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE -CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE -CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 -CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_BASE -CYDEV_PICU_STAT_BASE EQU 0x40004580 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE -CYDEV_PICU_STAT_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE -CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE -CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT -CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE -CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE -CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT -CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE -CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE -CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT -CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE -CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE -CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT -CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE -CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE -CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT -CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE -CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE -CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT -CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE -CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE -CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT -CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE -CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE -CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT -CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE -CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE -CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT -CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE -CYDEV_PICU_SNAP_BASE EQU 0x40004590 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE -CYDEV_PICU_SNAP_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE -CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE -CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP -CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE -CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE -CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP -CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE -CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE -CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP -CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE -CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE -CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP -CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE -CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE -CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP -CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE -CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE -CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP -CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE -CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE -CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP -CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE -CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE -CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP -CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE -CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE -CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15 -CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE -CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE -CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE -CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE -CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE -CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE -CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE -CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE -CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE -CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE -CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE -CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE -CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE -CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE -CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE -CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE -CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE -CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE -CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE -CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE -CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR -CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_BASE -CYDEV_MFGCFG_BASE EQU 0x40004600 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_SIZE -CYDEV_MFGCFG_SIZE EQU 0x000000ed - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE -CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE -CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE -CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE -CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR -CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE -CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE -CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR -CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE -CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE -CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR -CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE -CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE -CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR -CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE -CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE -CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 -CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE -CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE -CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 -CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE -CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE -CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 -CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE -CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE -CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0 -CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE -CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE -CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0 -CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE -CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 -CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 -CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE -CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 -CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 -CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE -CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 -CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 -CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE -CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 -CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 -CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE -CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE -CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0 -CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1 -CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE -CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE -CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0 -CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1 -CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE -CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE -CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0 -CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1 -CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE -CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE -CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0 -CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1 -CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE -CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE -CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0 -CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1 -CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR -CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR -CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR -CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0 -CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1 -CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR -CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR -CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2 -CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3 -CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE -CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE -CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0 -CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1 -CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE -CYDEV_MFGCFG_X32_BASE EQU 0x40004698 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE -CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR -CYDEV_MFGCFG_X32_TR EQU 0x40004698 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE -CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE -CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0 -CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1 -CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN -CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M -CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2 -CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE -CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE -CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR -CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_DLY -CYDEV_MFGCFG_DLY EQU 0x400046c0 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE -CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE -CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR -CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE -CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE -CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR -CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0 -CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG -CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE -CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE -CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR -CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID -CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec - ENDIF - IF :LNOT::DEF:CYDEV_RESET_BASE -CYDEV_RESET_BASE EQU 0x400046f0 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_SIZE -CYDEV_RESET_SIZE EQU 0x0000000f - ENDIF - IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0 -CYDEV_RESET_IPOR_CR0 EQU 0x400046f0 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1 -CYDEV_RESET_IPOR_CR1 EQU 0x400046f1 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2 -CYDEV_RESET_IPOR_CR2 EQU 0x400046f2 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3 -CYDEV_RESET_IPOR_CR3 EQU 0x400046f3 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_CR0 -CYDEV_RESET_CR0 EQU 0x400046f4 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_CR1 -CYDEV_RESET_CR1 EQU 0x400046f5 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_CR2 -CYDEV_RESET_CR2 EQU 0x400046f6 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_CR3 -CYDEV_RESET_CR3 EQU 0x400046f7 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_CR4 -CYDEV_RESET_CR4 EQU 0x400046f8 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_CR5 -CYDEV_RESET_CR5 EQU 0x400046f9 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_SR0 -CYDEV_RESET_SR0 EQU 0x400046fa - ENDIF - IF :LNOT::DEF:CYDEV_RESET_SR1 -CYDEV_RESET_SR1 EQU 0x400046fb - ENDIF - IF :LNOT::DEF:CYDEV_RESET_SR2 -CYDEV_RESET_SR2 EQU 0x400046fc - ENDIF - IF :LNOT::DEF:CYDEV_RESET_SR3 -CYDEV_RESET_SR3 EQU 0x400046fd - ENDIF - IF :LNOT::DEF:CYDEV_RESET_TR -CYDEV_RESET_TR EQU 0x400046fe - ENDIF - IF :LNOT::DEF:CYDEV_SPC_BASE -CYDEV_SPC_BASE EQU 0x40004700 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_SIZE -CYDEV_SPC_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR -CYDEV_SPC_FM_EE_CR EQU 0x40004700 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT -CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_EE_SCR -CYDEV_SPC_EE_SCR EQU 0x40004702 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_EE_ERR -CYDEV_SPC_EE_ERR EQU 0x40004703 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_CPU_DATA -CYDEV_SPC_CPU_DATA EQU 0x40004720 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_DMA_DATA -CYDEV_SPC_DMA_DATA EQU 0x40004721 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_SR -CYDEV_SPC_SR EQU 0x40004722 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_CR -CYDEV_SPC_CR EQU 0x40004723 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE -CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE -CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE -CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE -CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_BASE -CYDEV_CACHE_BASE EQU 0x40004800 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_SIZE -CYDEV_CACHE_SIZE EQU 0x0000009c - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_CC_CTL -CYDEV_CACHE_CC_CTL EQU 0x40004800 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR -CYDEV_CACHE_ECC_CORR EQU 0x40004880 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR -CYDEV_CACHE_ECC_ERR EQU 0x40004888 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR -CYDEV_CACHE_FLASH_ERR EQU 0x40004890 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_HITMISS -CYDEV_CACHE_HITMISS EQU 0x40004898 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_BASE -CYDEV_I2C_BASE EQU 0x40004900 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_SIZE -CYDEV_I2C_SIZE EQU 0x000000e1 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_XCFG -CYDEV_I2C_XCFG EQU 0x400049c8 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_ADR -CYDEV_I2C_ADR EQU 0x400049ca - ENDIF - IF :LNOT::DEF:CYDEV_I2C_CFG -CYDEV_I2C_CFG EQU 0x400049d6 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_CSR -CYDEV_I2C_CSR EQU 0x400049d7 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_D -CYDEV_I2C_D EQU 0x400049d8 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_MCSR -CYDEV_I2C_MCSR EQU 0x400049d9 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1 -CYDEV_I2C_CLK_DIV1 EQU 0x400049db - ENDIF - IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2 -CYDEV_I2C_CLK_DIV2 EQU 0x400049dc - ENDIF - IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR -CYDEV_I2C_TMOUT_CSR EQU 0x400049dd - ENDIF - IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR -CYDEV_I2C_TMOUT_SR EQU 0x400049de - ENDIF - IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0 -CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df - ENDIF - IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1 -CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_BASE -CYDEV_DEC_BASE EQU 0x40004e00 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_SIZE -CYDEV_DEC_SIZE EQU 0x00000015 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_CR -CYDEV_DEC_CR EQU 0x40004e00 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_SR -CYDEV_DEC_SR EQU 0x40004e01 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_SHIFT1 -CYDEV_DEC_SHIFT1 EQU 0x40004e02 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_SHIFT2 -CYDEV_DEC_SHIFT2 EQU 0x40004e03 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_DR2 -CYDEV_DEC_DR2 EQU 0x40004e04 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_DR2H -CYDEV_DEC_DR2H EQU 0x40004e05 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_DR1 -CYDEV_DEC_DR1 EQU 0x40004e06 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_OCOR -CYDEV_DEC_OCOR EQU 0x40004e08 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_OCORM -CYDEV_DEC_OCORM EQU 0x40004e09 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_OCORH -CYDEV_DEC_OCORH EQU 0x40004e0a - ENDIF - IF :LNOT::DEF:CYDEV_DEC_GCOR -CYDEV_DEC_GCOR EQU 0x40004e0c - ENDIF - IF :LNOT::DEF:CYDEV_DEC_GCORH -CYDEV_DEC_GCORH EQU 0x40004e0d - ENDIF - IF :LNOT::DEF:CYDEV_DEC_GVAL -CYDEV_DEC_GVAL EQU 0x40004e0e - ENDIF - IF :LNOT::DEF:CYDEV_DEC_OUTSAMP -CYDEV_DEC_OUTSAMP EQU 0x40004e10 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM -CYDEV_DEC_OUTSAMPM EQU 0x40004e11 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH -CYDEV_DEC_OUTSAMPH EQU 0x40004e12 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS -CYDEV_DEC_OUTSAMPS EQU 0x40004e13 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_COHER -CYDEV_DEC_COHER EQU 0x40004e14 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_BASE -CYDEV_TMR0_BASE EQU 0x40004f00 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_SIZE -CYDEV_TMR0_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_CFG0 -CYDEV_TMR0_CFG0 EQU 0x40004f00 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_CFG1 -CYDEV_TMR0_CFG1 EQU 0x40004f01 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_CFG2 -CYDEV_TMR0_CFG2 EQU 0x40004f02 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_SR0 -CYDEV_TMR0_SR0 EQU 0x40004f03 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_PER0 -CYDEV_TMR0_PER0 EQU 0x40004f04 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_PER1 -CYDEV_TMR0_PER1 EQU 0x40004f05 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0 -CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1 -CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_CAP0 -CYDEV_TMR0_CAP0 EQU 0x40004f08 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_CAP1 -CYDEV_TMR0_CAP1 EQU 0x40004f09 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_RT0 -CYDEV_TMR0_RT0 EQU 0x40004f0a - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_RT1 -CYDEV_TMR0_RT1 EQU 0x40004f0b - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_BASE -CYDEV_TMR1_BASE EQU 0x40004f0c - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_SIZE -CYDEV_TMR1_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_CFG0 -CYDEV_TMR1_CFG0 EQU 0x40004f0c - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_CFG1 -CYDEV_TMR1_CFG1 EQU 0x40004f0d - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_CFG2 -CYDEV_TMR1_CFG2 EQU 0x40004f0e - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_SR0 -CYDEV_TMR1_SR0 EQU 0x40004f0f - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_PER0 -CYDEV_TMR1_PER0 EQU 0x40004f10 - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_PER1 -CYDEV_TMR1_PER1 EQU 0x40004f11 - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0 -CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12 - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1 -CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13 - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_CAP0 -CYDEV_TMR1_CAP0 EQU 0x40004f14 - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_CAP1 -CYDEV_TMR1_CAP1 EQU 0x40004f15 - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_RT0 -CYDEV_TMR1_RT0 EQU 0x40004f16 - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_RT1 -CYDEV_TMR1_RT1 EQU 0x40004f17 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_BASE -CYDEV_TMR2_BASE EQU 0x40004f18 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_SIZE -CYDEV_TMR2_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_CFG0 -CYDEV_TMR2_CFG0 EQU 0x40004f18 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_CFG1 -CYDEV_TMR2_CFG1 EQU 0x40004f19 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_CFG2 -CYDEV_TMR2_CFG2 EQU 0x40004f1a - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_SR0 -CYDEV_TMR2_SR0 EQU 0x40004f1b - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_PER0 -CYDEV_TMR2_PER0 EQU 0x40004f1c - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_PER1 -CYDEV_TMR2_PER1 EQU 0x40004f1d - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0 -CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1 -CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_CAP0 -CYDEV_TMR2_CAP0 EQU 0x40004f20 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_CAP1 -CYDEV_TMR2_CAP1 EQU 0x40004f21 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_RT0 -CYDEV_TMR2_RT0 EQU 0x40004f22 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_RT1 -CYDEV_TMR2_RT1 EQU 0x40004f23 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_BASE -CYDEV_TMR3_BASE EQU 0x40004f24 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_SIZE -CYDEV_TMR3_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_CFG0 -CYDEV_TMR3_CFG0 EQU 0x40004f24 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_CFG1 -CYDEV_TMR3_CFG1 EQU 0x40004f25 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_CFG2 -CYDEV_TMR3_CFG2 EQU 0x40004f26 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_SR0 -CYDEV_TMR3_SR0 EQU 0x40004f27 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_PER0 -CYDEV_TMR3_PER0 EQU 0x40004f28 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_PER1 -CYDEV_TMR3_PER1 EQU 0x40004f29 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0 -CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1 -CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_CAP0 -CYDEV_TMR3_CAP0 EQU 0x40004f2c - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_CAP1 -CYDEV_TMR3_CAP1 EQU 0x40004f2d - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_RT0 -CYDEV_TMR3_RT0 EQU 0x40004f2e - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_RT1 -CYDEV_TMR3_RT1 EQU 0x40004f2f - ENDIF - IF :LNOT::DEF:CYDEV_IO_BASE -CYDEV_IO_BASE EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYDEV_IO_SIZE -CYDEV_IO_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_BASE -CYDEV_IO_PC_BASE EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_SIZE -CYDEV_IO_PC_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE -CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE -CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0 -CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1 -CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2 -CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3 -CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4 -CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5 -CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6 -CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7 -CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE -CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE -CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0 -CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1 -CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2 -CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3 -CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4 -CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5 -CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6 -CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7 -CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE -CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE -CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0 -CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1 -CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2 -CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3 -CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4 -CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5 -CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6 -CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7 -CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE -CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE -CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0 -CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1 -CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2 -CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3 -CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4 -CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5 -CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6 -CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7 -CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE -CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE -CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0 -CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1 -CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2 -CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3 -CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4 -CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5 -CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6 -CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7 -CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE -CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE -CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0 -CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1 -CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2 -CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3 -CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4 -CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5 -CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6 -CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7 -CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE -CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE -CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0 -CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1 -CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2 -CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3 -CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4 -CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5 -CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6 -CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7 -CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE -CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE -CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0 -CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1 -CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2 -CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3 -CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4 -CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5 -CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6 -CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7 -CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE -CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE -CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0 -CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1 -CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2 -CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3 -CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4 -CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5 -CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE -CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE -CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0 -CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1 -CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_BASE -CYDEV_IO_DR_BASE EQU 0x40005080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_SIZE -CYDEV_IO_DR_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE -CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE -CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS -CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE -CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE -CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS -CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE -CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE -CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS -CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE -CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE -CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS -CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE -CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE -CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS -CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE -CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE -CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS -CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE -CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE -CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS -CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE -CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE -CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS -CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE -CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE -CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS -CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_BASE -CYDEV_IO_PS_BASE EQU 0x40005090 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_SIZE -CYDEV_IO_PS_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE -CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE -CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS -CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE -CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE -CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS -CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE -CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE -CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS -CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE -CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE -CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS -CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE -CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE -CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS -CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE -CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE -CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS -CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE -CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE -CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS -CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE -CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE -CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS -CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE -CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE -CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS -CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_BASE -CYDEV_IO_PRT_BASE EQU 0x40005100 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_SIZE -CYDEV_IO_PRT_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE -CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE -CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR -CYDEV_IO_PRT_PRT0_DR EQU 0x40005100 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS -CYDEV_IO_PRT_PRT0_PS EQU 0x40005101 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0 -CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1 -CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2 -CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW -CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP -CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE -CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS -CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL -CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT -CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK -CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX -CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG -CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG -CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN -CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE -CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE -CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR -CYDEV_IO_PRT_PRT1_DR EQU 0x40005110 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS -CYDEV_IO_PRT_PRT1_PS EQU 0x40005111 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0 -CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1 -CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2 -CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW -CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP -CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE -CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS -CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL -CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT -CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK -CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX -CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG -CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG -CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN -CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE -CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE -CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR -CYDEV_IO_PRT_PRT2_DR EQU 0x40005120 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS -CYDEV_IO_PRT_PRT2_PS EQU 0x40005121 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0 -CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1 -CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2 -CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW -CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP -CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE -CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS -CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL -CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT -CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK -CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX -CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG -CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG -CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN -CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE -CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE -CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR -CYDEV_IO_PRT_PRT3_DR EQU 0x40005130 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS -CYDEV_IO_PRT_PRT3_PS EQU 0x40005131 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0 -CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1 -CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2 -CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW -CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP -CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE -CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS -CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL -CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT -CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK -CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX -CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG -CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG -CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN -CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE -CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE -CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR -CYDEV_IO_PRT_PRT4_DR EQU 0x40005140 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS -CYDEV_IO_PRT_PRT4_PS EQU 0x40005141 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0 -CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1 -CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2 -CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW -CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP -CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE -CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS -CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL -CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT -CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK -CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX -CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG -CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG -CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN -CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE -CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE -CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR -CYDEV_IO_PRT_PRT5_DR EQU 0x40005150 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS -CYDEV_IO_PRT_PRT5_PS EQU 0x40005151 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0 -CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1 -CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2 -CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW -CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP -CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE -CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS -CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL -CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT -CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK -CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX -CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG -CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG -CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN -CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE -CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE -CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR -CYDEV_IO_PRT_PRT6_DR EQU 0x40005160 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS -CYDEV_IO_PRT_PRT6_PS EQU 0x40005161 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0 -CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1 -CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2 -CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW -CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP -CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE -CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS -CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL -CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT -CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK -CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX -CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG -CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG -CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN -CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE -CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE -CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR -CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS -CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0 -CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1 -CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2 -CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW -CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP -CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE -CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS -CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN -CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT -CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK -CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ -CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG -CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG -CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF -CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE -CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE -CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR -CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS -CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0 -CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1 -CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2 -CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW -CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP -CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE -CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS -CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL -CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT -CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK -CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX -CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG -CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG -CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN -CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_BASE -CYDEV_PRTDSI_BASE EQU 0x40005200 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_SIZE -CYDEV_PRTDSI_SIZE EQU 0x0000007f - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE -CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE -CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0 -CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1 -CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0 -CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1 -CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN -CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT -CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL -CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE -CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE -CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0 -CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1 -CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0 -CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1 -CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN -CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT -CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL -CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE -CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE -CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0 -CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1 -CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0 -CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1 -CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN -CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT -CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL -CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE -CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE -CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0 -CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1 -CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0 -CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1 -CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN -CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT -CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL -CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE -CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE -CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0 -CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1 -CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0 -CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1 -CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN -CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT -CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL -CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE -CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE -CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0 -CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1 -CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0 -CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1 -CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN -CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT -CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL -CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE -CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE -CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0 -CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1 -CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0 -CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1 -CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN -CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT -CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL -CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE -CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE -CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0 -CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1 -CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0 -CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1 -CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN -CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT -CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE -CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE -CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0 -CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1 -CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0 -CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1 -CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN -CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT -CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL -CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_BASE -CYDEV_EMIF_BASE EQU 0x40005400 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_SIZE -CYDEV_EMIF_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_NO_UDB -CYDEV_EMIF_NO_UDB EQU 0x40005400 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES -CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN -CYDEV_EMIF_MEM_DWN EQU 0x40005402 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV -CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN -CYDEV_EMIF_CLOCK_EN EQU 0x40005404 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE -CYDEV_EMIF_EM_TYPE EQU 0x40005405 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES -CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_BASE -CYDEV_ANAIF_BASE EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_SIZE -CYDEV_ANAIF_SIZE EQU 0x000003a9 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE -CYDEV_ANAIF_CFG_BASE EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE -CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE -CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE -CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0 -CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1 -CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2 -CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE -CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE -CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0 -CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1 -CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2 -CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE -CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE -CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0 -CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1 -CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2 -CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE -CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE -CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0 -CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1 -CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2 -CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE -CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE -CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0 -CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1 -CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST -CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE -CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE -CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0 -CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1 -CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST -CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE -CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE -CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0 -CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1 -CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST -CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE -CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE -CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0 -CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1 -CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST -CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE -CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE -CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR -CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE -CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE -CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR -CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE -CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE -CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR -CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE -CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE -CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR -CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE -CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE -CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR -CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX -CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE -CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE -CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR -CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX -CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE -CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE -CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR -CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX -CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE -CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE -CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR -CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX -CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE -CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE -CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR -CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD -CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE -CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE -CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR -CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD -CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE -CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE -CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR -CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD -CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE -CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE -CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR -CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD -CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE -CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE -CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0 -CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1 -CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE -CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE -CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR -CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE -CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE -CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG -CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE -CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE -CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0 -CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD -CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0 -CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1 -CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE -CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE -CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0 -CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1 -CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE -CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE -CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0 -CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1 -CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE -CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE -CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0 -CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1 -CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE -CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE -CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0 -CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD -CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE -CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE -CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0 -CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD -CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE -CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE -CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0 -CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE -CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE -CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0 -CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1 -CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2 -CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3 -CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4 -CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5 -CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6 -CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7 -CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8 -CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9 -CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10 -CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11 -CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12 -CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13 -CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14 -CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15 -CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16 -CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17 -CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0 -CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1 -CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2 -CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3 -CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0 -CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1 -CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0 -CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1 -CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0 -CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1 -CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2 -CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3 -CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC -CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1 -CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE -CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE -CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0 -CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1 -CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2 -CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3 -CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4 -CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5 -CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6 -CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE -CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE -CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0 -CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1 -CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2 -CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3 -CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4 -CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5 -CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6 -CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE -CYDEV_ANAIF_RT_BASE EQU 0x40005a00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE -CYDEV_ANAIF_RT_SIZE EQU 0x00000162 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE -CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE -CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0 -CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2 -CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3 -CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4 -CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6 -CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7 -CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8 -CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10 -CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK -CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST -CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE -CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE -CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0 -CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2 -CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3 -CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4 -CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6 -CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7 -CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8 -CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10 -CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK -CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST -CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE -CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE -CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0 -CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2 -CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3 -CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4 -CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6 -CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7 -CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8 -CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10 -CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK -CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST -CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE -CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE -CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0 -CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2 -CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3 -CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4 -CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6 -CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7 -CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8 -CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10 -CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK -CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST -CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE -CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE -CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0 -CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2 -CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3 -CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4 -CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE -CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE -CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE -CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0 -CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2 -CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3 -CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4 -CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE -CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE -CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE -CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0 -CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2 -CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3 -CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4 -CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE -CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE -CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE -CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0 -CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2 -CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3 -CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4 -CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE -CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE -CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE -CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0 -CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2 -CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3 -CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4 -CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6 -CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK -CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE -CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE -CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0 -CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2 -CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3 -CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4 -CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6 -CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK -CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE -CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE -CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0 -CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2 -CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3 -CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4 -CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6 -CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK -CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE -CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE -CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0 -CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2 -CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3 -CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4 -CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6 -CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK -CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE -CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE -CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0 -CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2 -CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3 -CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4 -CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6 -CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK -CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE -CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE -CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0 -CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2 -CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3 -CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4 -CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6 -CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK -CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE -CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE -CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0 -CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2 -CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3 -CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4 -CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6 -CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK -CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE -CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE -CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX -CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW -CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE -CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE -CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX -CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW -CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE -CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE -CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX -CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW -CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE -CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE -CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX -CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW -CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE -CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE -CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0 -CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1 -CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2 -CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3 -CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4 -CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE -CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE -CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC -CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE -CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE -CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0 -CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2 -CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3 -CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE -CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE -CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0 -CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1 -CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2 -CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3 -CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4 -CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5 -CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE -CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE -CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE -CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE -CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D -CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE -CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE -CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D -CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE -CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE -CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D -CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE -CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE -CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D -CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE -CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE -CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0 -CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1 -CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE -CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE -CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR -CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1 -CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK -CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK -CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR -CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE -CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE -CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK -CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST -CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE -CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE -CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR -CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1 -CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK -CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV -CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR -CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE -CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE -CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0 -CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1 -CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE -CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE -CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0 -CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1 -CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE -CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE -CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF -CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_BASE -CYDEV_USB_BASE EQU 0x40006000 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIZE -CYDEV_USB_SIZE EQU 0x00000300 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR0 -CYDEV_USB_EP0_DR0 EQU 0x40006000 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR1 -CYDEV_USB_EP0_DR1 EQU 0x40006001 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR2 -CYDEV_USB_EP0_DR2 EQU 0x40006002 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR3 -CYDEV_USB_EP0_DR3 EQU 0x40006003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR4 -CYDEV_USB_EP0_DR4 EQU 0x40006004 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR5 -CYDEV_USB_EP0_DR5 EQU 0x40006005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR6 -CYDEV_USB_EP0_DR6 EQU 0x40006006 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_DR7 -CYDEV_USB_EP0_DR7 EQU 0x40006007 - ENDIF - IF :LNOT::DEF:CYDEV_USB_CR0 -CYDEV_USB_CR0 EQU 0x40006008 - ENDIF - IF :LNOT::DEF:CYDEV_USB_CR1 -CYDEV_USB_CR1 EQU 0x40006009 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN -CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR -CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE -CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE -CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0 -CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1 -CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0 -CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e - ENDIF - IF :LNOT::DEF:CYDEV_USB_USBIO_CR0 -CYDEV_USB_USBIO_CR0 EQU 0x40006010 - ENDIF - IF :LNOT::DEF:CYDEV_USB_USBIO_CR1 -CYDEV_USB_USBIO_CR1 EQU 0x40006012 - ENDIF - IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG -CYDEV_USB_DYN_RECONFIG EQU 0x40006014 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SOF0 -CYDEV_USB_SOF0 EQU 0x40006018 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SOF1 -CYDEV_USB_SOF1 EQU 0x40006019 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE -CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE -CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0 -CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1 -CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0 -CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_CR -CYDEV_USB_EP0_CR EQU 0x40006028 - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP0_CNT -CYDEV_USB_EP0_CNT EQU 0x40006029 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE -CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE -CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0 -CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1 -CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0 -CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE -CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE -CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0 -CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1 -CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0 -CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE -CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE -CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0 -CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1 -CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0 -CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE -CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE -CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0 -CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1 -CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0 -CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE -CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE -CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0 -CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1 -CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0 -CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE -CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE -CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0 -CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1 -CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0 -CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE -CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE -CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG -CYDEV_USB_ARB_EP1_CFG EQU 0x40006080 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN -CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR -CYDEV_USB_ARB_EP1_SR EQU 0x40006082 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE -CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE -CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA -CYDEV_USB_ARB_RW1_WA EQU 0x40006084 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB -CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA -CYDEV_USB_ARB_RW1_RA EQU 0x40006086 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB -CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR -CYDEV_USB_ARB_RW1_DR EQU 0x40006088 - ENDIF - IF :LNOT::DEF:CYDEV_USB_BUF_SIZE -CYDEV_USB_BUF_SIZE EQU 0x4000608c - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE -CYDEV_USB_EP_ACTIVE EQU 0x4000608e - ENDIF - IF :LNOT::DEF:CYDEV_USB_EP_TYPE -CYDEV_USB_EP_TYPE EQU 0x4000608f - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE -CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE -CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG -CYDEV_USB_ARB_EP2_CFG EQU 0x40006090 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN -CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR -CYDEV_USB_ARB_EP2_SR EQU 0x40006092 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE -CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE -CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA -CYDEV_USB_ARB_RW2_WA EQU 0x40006094 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB -CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA -CYDEV_USB_ARB_RW2_RA EQU 0x40006096 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB -CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR -CYDEV_USB_ARB_RW2_DR EQU 0x40006098 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_CFG -CYDEV_USB_ARB_CFG EQU 0x4000609c - ENDIF - IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN -CYDEV_USB_USB_CLK_EN EQU 0x4000609d - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN -CYDEV_USB_ARB_INT_EN EQU 0x4000609e - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR -CYDEV_USB_ARB_INT_SR EQU 0x4000609f - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE -CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE -CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG -CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN -CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR -CYDEV_USB_ARB_EP3_SR EQU 0x400060a2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE -CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE -CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA -CYDEV_USB_ARB_RW3_WA EQU 0x400060a4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB -CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA -CYDEV_USB_ARB_RW3_RA EQU 0x400060a6 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB -CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR -CYDEV_USB_ARB_RW3_DR EQU 0x400060a8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_CWA -CYDEV_USB_CWA EQU 0x400060ac - ENDIF - IF :LNOT::DEF:CYDEV_USB_CWA_MSB -CYDEV_USB_CWA_MSB EQU 0x400060ad - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE -CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE -CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG -CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN -CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR -CYDEV_USB_ARB_EP4_SR EQU 0x400060b2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE -CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE -CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA -CYDEV_USB_ARB_RW4_WA EQU 0x400060b4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB -CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA -CYDEV_USB_ARB_RW4_RA EQU 0x400060b6 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB -CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR -CYDEV_USB_ARB_RW4_DR EQU 0x400060b8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_DMA_THRES -CYDEV_USB_DMA_THRES EQU 0x400060bc - ENDIF - IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB -CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE -CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE -CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG -CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN -CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR -CYDEV_USB_ARB_EP5_SR EQU 0x400060c2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE -CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE -CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA -CYDEV_USB_ARB_RW5_WA EQU 0x400060c4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB -CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA -CYDEV_USB_ARB_RW5_RA EQU 0x400060c6 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB -CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR -CYDEV_USB_ARB_RW5_DR EQU 0x400060c8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT -CYDEV_USB_BUS_RST_CNT EQU 0x400060cc - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE -CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE -CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG -CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN -CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR -CYDEV_USB_ARB_EP6_SR EQU 0x400060d2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE -CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE -CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA -CYDEV_USB_ARB_RW6_WA EQU 0x400060d4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB -CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA -CYDEV_USB_ARB_RW6_RA EQU 0x400060d6 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB -CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR -CYDEV_USB_ARB_RW6_DR EQU 0x400060d8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE -CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE -CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG -CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN -CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR -CYDEV_USB_ARB_EP7_SR EQU 0x400060e2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE -CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE -CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA -CYDEV_USB_ARB_RW7_WA EQU 0x400060e4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB -CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA -CYDEV_USB_ARB_RW7_RA EQU 0x400060e6 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB -CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR -CYDEV_USB_ARB_RW7_DR EQU 0x400060e8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE -CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE -CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG -CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN -CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR -CYDEV_USB_ARB_EP8_SR EQU 0x400060f2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE -CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE -CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA -CYDEV_USB_ARB_RW8_WA EQU 0x400060f4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB -CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA -CYDEV_USB_ARB_RW8_RA EQU 0x400060f6 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB -CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR -CYDEV_USB_ARB_RW8_DR EQU 0x400060f8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_MEM_BASE -CYDEV_USB_MEM_BASE EQU 0x40006100 - ENDIF - IF :LNOT::DEF:CYDEV_USB_MEM_SIZE -CYDEV_USB_MEM_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE -CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100 - ENDIF - IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE -CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_BASE -CYDEV_UWRK_BASE EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_SIZE -CYDEV_UWRK_SIZE EQU 0x00000b60 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE -CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE -CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE -CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE -CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0 -CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0 -CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0 -CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0 -CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0 -CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0 -CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0 -CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0 -CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0 -CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0 -CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0 -CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0 -CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0 -CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0 -CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0 -CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0 -CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1 -CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1 -CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1 -CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1 -CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1 -CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1 -CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1 -CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1 -CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1 -CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1 -CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1 -CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1 -CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1 -CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1 -CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1 -CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1 -CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0 -CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0 -CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0 -CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0 -CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0 -CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0 -CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0 -CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0 -CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0 -CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0 -CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0 -CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0 -CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0 -CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0 -CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0 -CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0 -CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1 -CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1 -CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1 -CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1 -CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1 -CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1 -CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1 -CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1 -CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1 -CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1 -CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1 -CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1 -CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1 -CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1 -CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1 -CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1 -CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0 -CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0 -CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0 -CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0 -CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0 -CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0 -CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0 -CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0 -CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0 -CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0 -CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0 -CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0 -CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0 -CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0 -CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0 -CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0 -CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1 -CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1 -CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1 -CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1 -CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1 -CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1 -CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1 -CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1 -CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1 -CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1 -CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1 -CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1 -CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1 -CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1 -CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1 -CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1 -CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST -CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST -CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST -CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST -CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST -CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST -CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST -CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST -CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST -CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST -CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST -CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST -CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST -CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST -CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST -CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST -CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL -CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL -CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL -CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL -CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL -CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL -CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL -CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL -CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL -CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL -CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL -CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL -CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL -CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL -CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL -CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL -CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK -CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK -CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK -CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK -CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK -CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK -CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK -CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK -CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK -CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK -CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK -CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK -CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK -CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK -CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK -CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK -CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL -CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL -CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL -CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL -CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL -CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL -CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL -CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL -CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL -CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL -CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL -CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL -CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL -CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL -CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL -CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL -CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC -CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC -CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC -CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC -CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC -CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC -CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC -CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC -CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC -CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC -CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC -CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC -CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC -CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC -CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC -CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC -CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE -CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE -CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0 -CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0 -CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0 -CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0 -CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0 -CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0 -CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0 -CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0 -CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1 -CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1 -CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1 -CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1 -CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1 -CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1 -CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1 -CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1 -CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0 -CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0 -CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0 -CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0 -CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0 -CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0 -CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0 -CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0 -CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1 -CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1 -CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1 -CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1 -CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1 -CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1 -CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1 -CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1 -CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0 -CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0 -CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0 -CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0 -CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0 -CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0 -CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0 -CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0 -CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1 -CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1 -CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1 -CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1 -CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1 -CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1 -CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1 -CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1 -CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST -CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST -CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST -CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST -CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST -CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST -CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST -CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST -CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL -CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL -CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL -CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL -CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL -CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL -CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL -CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL -CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK -CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK -CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK -CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK -CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK -CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK -CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK -CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK -CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL -CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL -CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL -CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL -CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL -CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL -CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL -CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL -CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC -CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC -CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC -CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC -CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC -CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC -CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC -CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC -CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE -CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE -CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE -CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE -CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE -CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE -CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 -CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE -CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE -CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 -CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL -CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 -CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE -CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE -CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE -CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE -CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC -CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE -CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE -CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC -CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_BASE -CYDEV_PHUB_BASE EQU 0x40007000 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_SIZE -CYDEV_PHUB_SIZE EQU 0x00000c00 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFG -CYDEV_PHUB_CFG EQU 0x40007000 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_ERR -CYDEV_PHUB_ERR EQU 0x40007004 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR -CYDEV_PHUB_ERR_ADR EQU 0x40007008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE -CYDEV_PHUB_CH0_BASE EQU 0x40007010 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE -CYDEV_PHUB_CH0_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG -CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION -CYDEV_PHUB_CH0_ACTION EQU 0x40007014 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS -CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE -CYDEV_PHUB_CH1_BASE EQU 0x40007020 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE -CYDEV_PHUB_CH1_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG -CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION -CYDEV_PHUB_CH1_ACTION EQU 0x40007024 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS -CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE -CYDEV_PHUB_CH2_BASE EQU 0x40007030 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE -CYDEV_PHUB_CH2_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG -CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION -CYDEV_PHUB_CH2_ACTION EQU 0x40007034 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS -CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE -CYDEV_PHUB_CH3_BASE EQU 0x40007040 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE -CYDEV_PHUB_CH3_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG -CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION -CYDEV_PHUB_CH3_ACTION EQU 0x40007044 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS -CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE -CYDEV_PHUB_CH4_BASE EQU 0x40007050 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE -CYDEV_PHUB_CH4_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG -CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION -CYDEV_PHUB_CH4_ACTION EQU 0x40007054 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS -CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE -CYDEV_PHUB_CH5_BASE EQU 0x40007060 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE -CYDEV_PHUB_CH5_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG -CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION -CYDEV_PHUB_CH5_ACTION EQU 0x40007064 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS -CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE -CYDEV_PHUB_CH6_BASE EQU 0x40007070 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE -CYDEV_PHUB_CH6_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG -CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION -CYDEV_PHUB_CH6_ACTION EQU 0x40007074 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS -CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE -CYDEV_PHUB_CH7_BASE EQU 0x40007080 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE -CYDEV_PHUB_CH7_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG -CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION -CYDEV_PHUB_CH7_ACTION EQU 0x40007084 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS -CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE -CYDEV_PHUB_CH8_BASE EQU 0x40007090 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE -CYDEV_PHUB_CH8_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG -CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION -CYDEV_PHUB_CH8_ACTION EQU 0x40007094 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS -CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE -CYDEV_PHUB_CH9_BASE EQU 0x400070a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE -CYDEV_PHUB_CH9_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG -CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION -CYDEV_PHUB_CH9_ACTION EQU 0x400070a4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS -CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE -CYDEV_PHUB_CH10_BASE EQU 0x400070b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE -CYDEV_PHUB_CH10_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG -CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION -CYDEV_PHUB_CH10_ACTION EQU 0x400070b4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS -CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE -CYDEV_PHUB_CH11_BASE EQU 0x400070c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE -CYDEV_PHUB_CH11_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG -CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION -CYDEV_PHUB_CH11_ACTION EQU 0x400070c4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS -CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE -CYDEV_PHUB_CH12_BASE EQU 0x400070d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE -CYDEV_PHUB_CH12_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG -CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION -CYDEV_PHUB_CH12_ACTION EQU 0x400070d4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS -CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE -CYDEV_PHUB_CH13_BASE EQU 0x400070e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE -CYDEV_PHUB_CH13_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG -CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION -CYDEV_PHUB_CH13_ACTION EQU 0x400070e4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS -CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE -CYDEV_PHUB_CH14_BASE EQU 0x400070f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE -CYDEV_PHUB_CH14_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG -CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION -CYDEV_PHUB_CH14_ACTION EQU 0x400070f4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS -CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE -CYDEV_PHUB_CH15_BASE EQU 0x40007100 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE -CYDEV_PHUB_CH15_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG -CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION -CYDEV_PHUB_CH15_ACTION EQU 0x40007104 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS -CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE -CYDEV_PHUB_CH16_BASE EQU 0x40007110 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE -CYDEV_PHUB_CH16_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG -CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION -CYDEV_PHUB_CH16_ACTION EQU 0x40007114 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS -CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE -CYDEV_PHUB_CH17_BASE EQU 0x40007120 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE -CYDEV_PHUB_CH17_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG -CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION -CYDEV_PHUB_CH17_ACTION EQU 0x40007124 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS -CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE -CYDEV_PHUB_CH18_BASE EQU 0x40007130 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE -CYDEV_PHUB_CH18_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG -CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION -CYDEV_PHUB_CH18_ACTION EQU 0x40007134 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS -CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE -CYDEV_PHUB_CH19_BASE EQU 0x40007140 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE -CYDEV_PHUB_CH19_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG -CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION -CYDEV_PHUB_CH19_ACTION EQU 0x40007144 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS -CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE -CYDEV_PHUB_CH20_BASE EQU 0x40007150 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE -CYDEV_PHUB_CH20_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG -CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION -CYDEV_PHUB_CH20_ACTION EQU 0x40007154 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS -CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE -CYDEV_PHUB_CH21_BASE EQU 0x40007160 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE -CYDEV_PHUB_CH21_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG -CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION -CYDEV_PHUB_CH21_ACTION EQU 0x40007164 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS -CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE -CYDEV_PHUB_CH22_BASE EQU 0x40007170 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE -CYDEV_PHUB_CH22_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG -CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION -CYDEV_PHUB_CH22_ACTION EQU 0x40007174 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS -CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE -CYDEV_PHUB_CH23_BASE EQU 0x40007180 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE -CYDEV_PHUB_CH23_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG -CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION -CYDEV_PHUB_CH23_ACTION EQU 0x40007184 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS -CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE -CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE -CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0 -CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1 -CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE -CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE -CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0 -CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1 -CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE -CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE -CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0 -CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1 -CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE -CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE -CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0 -CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1 -CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE -CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE -CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0 -CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1 -CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE -CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE -CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0 -CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1 -CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE -CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE -CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0 -CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1 -CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE -CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE -CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0 -CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1 -CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE -CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE -CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0 -CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1 -CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE -CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE -CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0 -CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1 -CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE -CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE -CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0 -CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1 -CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE -CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE -CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0 -CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1 -CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE -CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE -CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0 -CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1 -CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE -CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE -CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0 -CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1 -CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE -CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE -CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0 -CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1 -CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE -CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE -CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0 -CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1 -CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE -CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE -CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0 -CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1 -CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE -CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE -CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0 -CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1 -CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE -CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE -CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0 -CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1 -CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE -CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE -CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0 -CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1 -CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE -CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE -CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0 -CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1 -CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE -CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE -CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0 -CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1 -CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE -CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE -CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0 -CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1 -CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE -CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE -CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0 -CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1 -CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE -CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE -CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0 -CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1 -CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE -CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE -CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0 -CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1 -CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE -CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE -CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0 -CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1 -CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE -CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE -CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0 -CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1 -CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE -CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE -CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0 -CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1 -CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE -CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE -CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0 -CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1 -CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE -CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE -CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0 -CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1 -CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE -CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE -CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0 -CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1 -CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE -CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE -CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0 -CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1 -CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE -CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE -CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0 -CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1 -CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE -CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE -CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0 -CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1 -CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE -CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE -CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0 -CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1 -CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE -CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE -CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0 -CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1 -CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE -CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE -CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0 -CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1 -CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE -CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE -CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0 -CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1 -CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE -CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE -CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0 -CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1 -CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE -CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE -CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0 -CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1 -CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE -CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE -CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0 -CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1 -CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE -CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE -CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0 -CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1 -CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE -CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE -CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0 -CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1 -CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE -CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE -CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0 -CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1 -CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE -CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE -CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0 -CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1 -CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE -CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE -CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0 -CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1 -CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE -CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE -CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0 -CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1 -CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE -CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE -CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0 -CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1 -CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE -CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE -CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0 -CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1 -CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE -CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE -CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0 -CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1 -CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE -CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE -CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0 -CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1 -CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE -CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE -CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0 -CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1 -CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE -CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE -CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0 -CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1 -CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE -CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE -CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0 -CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1 -CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE -CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE -CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0 -CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1 -CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE -CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE -CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0 -CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1 -CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE -CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE -CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0 -CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1 -CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE -CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE -CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0 -CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1 -CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE -CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE -CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0 -CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1 -CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE -CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE -CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0 -CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1 -CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE -CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE -CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0 -CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1 -CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE -CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE -CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0 -CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1 -CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE -CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE -CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0 -CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1 -CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE -CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE -CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0 -CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1 -CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE -CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE -CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0 -CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1 -CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE -CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE -CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0 -CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1 -CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE -CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE -CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0 -CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1 -CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE -CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE -CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0 -CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1 -CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE -CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE -CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0 -CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1 -CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE -CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE -CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0 -CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1 -CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE -CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE -CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0 -CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1 -CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE -CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE -CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0 -CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1 -CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE -CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE -CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0 -CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1 -CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE -CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE -CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0 -CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1 -CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE -CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE -CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0 -CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1 -CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE -CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE -CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0 -CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1 -CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE -CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE -CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0 -CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1 -CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE -CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE -CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0 -CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1 -CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE -CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE -CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0 -CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1 -CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE -CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE -CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0 -CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1 -CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE -CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE -CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0 -CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1 -CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE -CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE -CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0 -CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1 -CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE -CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE -CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0 -CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1 -CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE -CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE -CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0 -CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1 -CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE -CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE -CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0 -CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1 -CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE -CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE -CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0 -CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1 -CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE -CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE -CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0 -CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1 -CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE -CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE -CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0 -CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1 -CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE -CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE -CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0 -CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1 -CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE -CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE -CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0 -CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1 -CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE -CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE -CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0 -CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1 -CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE -CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE -CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0 -CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1 -CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE -CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE -CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0 -CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1 -CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE -CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE -CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0 -CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1 -CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE -CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE -CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0 -CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1 -CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE -CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE -CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0 -CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1 -CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE -CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE -CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0 -CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1 -CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE -CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE -CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0 -CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1 -CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE -CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE -CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0 -CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1 -CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE -CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE -CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0 -CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1 -CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE -CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE -CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0 -CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1 -CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE -CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE -CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0 -CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1 -CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE -CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE -CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0 -CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1 -CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE -CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE -CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0 -CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1 -CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE -CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE -CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0 -CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1 -CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE -CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE -CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0 -CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1 -CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE -CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE -CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0 -CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1 -CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE -CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE -CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0 -CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1 -CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE -CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE -CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0 -CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1 -CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE -CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE -CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0 -CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1 -CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE -CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE -CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0 -CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1 -CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE -CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE -CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0 -CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1 -CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE -CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE -CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0 -CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1 -CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE -CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE -CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0 -CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1 -CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE -CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE -CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0 -CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1 -CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE -CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE -CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0 -CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1 -CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE -CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE -CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0 -CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1 -CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE -CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE -CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0 -CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1 -CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE -CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE -CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0 -CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1 -CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE -CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE -CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0 -CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1 -CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE -CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE -CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0 -CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1 -CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE -CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE -CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0 -CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1 -CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE -CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE -CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0 -CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1 -CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE -CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE -CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0 -CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1 -CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE -CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE -CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0 -CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1 -CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE -CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE -CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0 -CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1 -CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE -CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE -CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0 -CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1 -CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE -CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE -CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0 -CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1 -CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE -CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE -CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0 -CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1 -CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE -CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE -CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0 -CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1 -CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE -CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE -CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0 -CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1 -CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE -CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE -CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0 -CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1 -CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE -CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE -CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0 -CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1 -CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE -CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE -CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0 -CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1 -CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE -CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE -CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0 -CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1 -CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE -CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE -CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0 -CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1 -CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE -CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE -CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0 -CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1 -CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE -CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE -CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0 -CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1 -CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE -CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE -CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0 -CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1 -CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE -CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE -CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0 -CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1 -CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE -CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE -CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0 -CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1 -CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE -CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE -CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0 -CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1 -CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE -CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE -CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0 -CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1 -CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE -CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE -CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0 -CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1 -CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE -CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE -CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0 -CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1 -CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE -CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE -CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0 -CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1 -CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE -CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE -CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0 -CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1 -CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE -CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE -CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0 -CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1 -CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE -CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE -CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0 -CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1 -CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE -CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE -CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0 -CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1 -CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE -CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE -CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0 -CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1 -CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc - ENDIF - IF :LNOT::DEF:CYDEV_EE_BASE -CYDEV_EE_BASE EQU 0x40008000 - ENDIF - IF :LNOT::DEF:CYDEV_EE_SIZE -CYDEV_EE_SIZE EQU 0x00000800 - ENDIF - IF :LNOT::DEF:CYDEV_EE_DATA_MBASE -CYDEV_EE_DATA_MBASE EQU 0x40008000 - ENDIF - IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE -CYDEV_EE_DATA_MSIZE EQU 0x00000800 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_BASE -CYDEV_CAN0_BASE EQU 0x4000a000 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_SIZE -CYDEV_CAN0_SIZE EQU 0x000002a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE -CYDEV_CAN0_CSR_BASE EQU 0x4000a000 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE -CYDEV_CAN0_CSR_SIZE EQU 0x00000018 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR -CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN -CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR -CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR -CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD -CYDEV_CAN0_CSR_CMD EQU 0x4000a010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG -CYDEV_CAN0_CSR_CFG EQU 0x4000a014 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE -CYDEV_CAN0_TX0_BASE EQU 0x4000a020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE -CYDEV_CAN0_TX0_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD -CYDEV_CAN0_TX0_CMD EQU 0x4000a020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_ID -CYDEV_CAN0_TX0_ID EQU 0x4000a024 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_DH -CYDEV_CAN0_TX0_DH EQU 0x4000a028 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_DL -CYDEV_CAN0_TX0_DL EQU 0x4000a02c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE -CYDEV_CAN0_TX1_BASE EQU 0x4000a030 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE -CYDEV_CAN0_TX1_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD -CYDEV_CAN0_TX1_CMD EQU 0x4000a030 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_ID -CYDEV_CAN0_TX1_ID EQU 0x4000a034 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_DH -CYDEV_CAN0_TX1_DH EQU 0x4000a038 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_DL -CYDEV_CAN0_TX1_DL EQU 0x4000a03c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE -CYDEV_CAN0_TX2_BASE EQU 0x4000a040 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE -CYDEV_CAN0_TX2_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD -CYDEV_CAN0_TX2_CMD EQU 0x4000a040 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_ID -CYDEV_CAN0_TX2_ID EQU 0x4000a044 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_DH -CYDEV_CAN0_TX2_DH EQU 0x4000a048 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_DL -CYDEV_CAN0_TX2_DL EQU 0x4000a04c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE -CYDEV_CAN0_TX3_BASE EQU 0x4000a050 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE -CYDEV_CAN0_TX3_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD -CYDEV_CAN0_TX3_CMD EQU 0x4000a050 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_ID -CYDEV_CAN0_TX3_ID EQU 0x4000a054 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_DH -CYDEV_CAN0_TX3_DH EQU 0x4000a058 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_DL -CYDEV_CAN0_TX3_DL EQU 0x4000a05c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE -CYDEV_CAN0_TX4_BASE EQU 0x4000a060 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE -CYDEV_CAN0_TX4_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD -CYDEV_CAN0_TX4_CMD EQU 0x4000a060 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_ID -CYDEV_CAN0_TX4_ID EQU 0x4000a064 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_DH -CYDEV_CAN0_TX4_DH EQU 0x4000a068 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_DL -CYDEV_CAN0_TX4_DL EQU 0x4000a06c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE -CYDEV_CAN0_TX5_BASE EQU 0x4000a070 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE -CYDEV_CAN0_TX5_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD -CYDEV_CAN0_TX5_CMD EQU 0x4000a070 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_ID -CYDEV_CAN0_TX5_ID EQU 0x4000a074 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_DH -CYDEV_CAN0_TX5_DH EQU 0x4000a078 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_DL -CYDEV_CAN0_TX5_DL EQU 0x4000a07c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE -CYDEV_CAN0_TX6_BASE EQU 0x4000a080 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE -CYDEV_CAN0_TX6_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD -CYDEV_CAN0_TX6_CMD EQU 0x4000a080 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_ID -CYDEV_CAN0_TX6_ID EQU 0x4000a084 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_DH -CYDEV_CAN0_TX6_DH EQU 0x4000a088 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_DL -CYDEV_CAN0_TX6_DL EQU 0x4000a08c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE -CYDEV_CAN0_TX7_BASE EQU 0x4000a090 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE -CYDEV_CAN0_TX7_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD -CYDEV_CAN0_TX7_CMD EQU 0x4000a090 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_ID -CYDEV_CAN0_TX7_ID EQU 0x4000a094 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_DH -CYDEV_CAN0_TX7_DH EQU 0x4000a098 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_DL -CYDEV_CAN0_TX7_DL EQU 0x4000a09c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE -CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE -CYDEV_CAN0_RX0_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD -CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_ID -CYDEV_CAN0_RX0_ID EQU 0x4000a0a4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_DH -CYDEV_CAN0_RX0_DH EQU 0x4000a0a8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_DL -CYDEV_CAN0_RX0_DL EQU 0x4000a0ac - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR -CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR -CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD -CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD -CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE -CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE -CYDEV_CAN0_RX1_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD -CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_ID -CYDEV_CAN0_RX1_ID EQU 0x4000a0c4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_DH -CYDEV_CAN0_RX1_DH EQU 0x4000a0c8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_DL -CYDEV_CAN0_RX1_DL EQU 0x4000a0cc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR -CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR -CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD -CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD -CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE -CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE -CYDEV_CAN0_RX2_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD -CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_ID -CYDEV_CAN0_RX2_ID EQU 0x4000a0e4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_DH -CYDEV_CAN0_RX2_DH EQU 0x4000a0e8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_DL -CYDEV_CAN0_RX2_DL EQU 0x4000a0ec - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR -CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR -CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD -CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD -CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE -CYDEV_CAN0_RX3_BASE EQU 0x4000a100 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE -CYDEV_CAN0_RX3_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD -CYDEV_CAN0_RX3_CMD EQU 0x4000a100 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_ID -CYDEV_CAN0_RX3_ID EQU 0x4000a104 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_DH -CYDEV_CAN0_RX3_DH EQU 0x4000a108 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_DL -CYDEV_CAN0_RX3_DL EQU 0x4000a10c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR -CYDEV_CAN0_RX3_AMR EQU 0x4000a110 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR -CYDEV_CAN0_RX3_ACR EQU 0x4000a114 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD -CYDEV_CAN0_RX3_AMRD EQU 0x4000a118 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD -CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE -CYDEV_CAN0_RX4_BASE EQU 0x4000a120 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE -CYDEV_CAN0_RX4_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD -CYDEV_CAN0_RX4_CMD EQU 0x4000a120 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_ID -CYDEV_CAN0_RX4_ID EQU 0x4000a124 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_DH -CYDEV_CAN0_RX4_DH EQU 0x4000a128 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_DL -CYDEV_CAN0_RX4_DL EQU 0x4000a12c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR -CYDEV_CAN0_RX4_AMR EQU 0x4000a130 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR -CYDEV_CAN0_RX4_ACR EQU 0x4000a134 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD -CYDEV_CAN0_RX4_AMRD EQU 0x4000a138 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD -CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE -CYDEV_CAN0_RX5_BASE EQU 0x4000a140 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE -CYDEV_CAN0_RX5_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD -CYDEV_CAN0_RX5_CMD EQU 0x4000a140 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_ID -CYDEV_CAN0_RX5_ID EQU 0x4000a144 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_DH -CYDEV_CAN0_RX5_DH EQU 0x4000a148 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_DL -CYDEV_CAN0_RX5_DL EQU 0x4000a14c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR -CYDEV_CAN0_RX5_AMR EQU 0x4000a150 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR -CYDEV_CAN0_RX5_ACR EQU 0x4000a154 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD -CYDEV_CAN0_RX5_AMRD EQU 0x4000a158 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD -CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE -CYDEV_CAN0_RX6_BASE EQU 0x4000a160 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE -CYDEV_CAN0_RX6_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD -CYDEV_CAN0_RX6_CMD EQU 0x4000a160 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_ID -CYDEV_CAN0_RX6_ID EQU 0x4000a164 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_DH -CYDEV_CAN0_RX6_DH EQU 0x4000a168 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_DL -CYDEV_CAN0_RX6_DL EQU 0x4000a16c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR -CYDEV_CAN0_RX6_AMR EQU 0x4000a170 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR -CYDEV_CAN0_RX6_ACR EQU 0x4000a174 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD -CYDEV_CAN0_RX6_AMRD EQU 0x4000a178 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD -CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE -CYDEV_CAN0_RX7_BASE EQU 0x4000a180 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE -CYDEV_CAN0_RX7_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD -CYDEV_CAN0_RX7_CMD EQU 0x4000a180 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_ID -CYDEV_CAN0_RX7_ID EQU 0x4000a184 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_DH -CYDEV_CAN0_RX7_DH EQU 0x4000a188 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_DL -CYDEV_CAN0_RX7_DL EQU 0x4000a18c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR -CYDEV_CAN0_RX7_AMR EQU 0x4000a190 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR -CYDEV_CAN0_RX7_ACR EQU 0x4000a194 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD -CYDEV_CAN0_RX7_AMRD EQU 0x4000a198 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD -CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE -CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE -CYDEV_CAN0_RX8_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD -CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_ID -CYDEV_CAN0_RX8_ID EQU 0x4000a1a4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_DH -CYDEV_CAN0_RX8_DH EQU 0x4000a1a8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_DL -CYDEV_CAN0_RX8_DL EQU 0x4000a1ac - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR -CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR -CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD -CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD -CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE -CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE -CYDEV_CAN0_RX9_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD -CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_ID -CYDEV_CAN0_RX9_ID EQU 0x4000a1c4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_DH -CYDEV_CAN0_RX9_DH EQU 0x4000a1c8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_DL -CYDEV_CAN0_RX9_DL EQU 0x4000a1cc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR -CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR -CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD -CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD -CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE -CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE -CYDEV_CAN0_RX10_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD -CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_ID -CYDEV_CAN0_RX10_ID EQU 0x4000a1e4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_DH -CYDEV_CAN0_RX10_DH EQU 0x4000a1e8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_DL -CYDEV_CAN0_RX10_DL EQU 0x4000a1ec - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR -CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR -CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD -CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD -CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE -CYDEV_CAN0_RX11_BASE EQU 0x4000a200 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE -CYDEV_CAN0_RX11_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD -CYDEV_CAN0_RX11_CMD EQU 0x4000a200 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_ID -CYDEV_CAN0_RX11_ID EQU 0x4000a204 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_DH -CYDEV_CAN0_RX11_DH EQU 0x4000a208 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_DL -CYDEV_CAN0_RX11_DL EQU 0x4000a20c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR -CYDEV_CAN0_RX11_AMR EQU 0x4000a210 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR -CYDEV_CAN0_RX11_ACR EQU 0x4000a214 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD -CYDEV_CAN0_RX11_AMRD EQU 0x4000a218 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD -CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE -CYDEV_CAN0_RX12_BASE EQU 0x4000a220 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE -CYDEV_CAN0_RX12_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD -CYDEV_CAN0_RX12_CMD EQU 0x4000a220 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_ID -CYDEV_CAN0_RX12_ID EQU 0x4000a224 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_DH -CYDEV_CAN0_RX12_DH EQU 0x4000a228 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_DL -CYDEV_CAN0_RX12_DL EQU 0x4000a22c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR -CYDEV_CAN0_RX12_AMR EQU 0x4000a230 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR -CYDEV_CAN0_RX12_ACR EQU 0x4000a234 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD -CYDEV_CAN0_RX12_AMRD EQU 0x4000a238 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD -CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE -CYDEV_CAN0_RX13_BASE EQU 0x4000a240 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE -CYDEV_CAN0_RX13_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD -CYDEV_CAN0_RX13_CMD EQU 0x4000a240 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_ID -CYDEV_CAN0_RX13_ID EQU 0x4000a244 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_DH -CYDEV_CAN0_RX13_DH EQU 0x4000a248 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_DL -CYDEV_CAN0_RX13_DL EQU 0x4000a24c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR -CYDEV_CAN0_RX13_AMR EQU 0x4000a250 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR -CYDEV_CAN0_RX13_ACR EQU 0x4000a254 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD -CYDEV_CAN0_RX13_AMRD EQU 0x4000a258 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD -CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE -CYDEV_CAN0_RX14_BASE EQU 0x4000a260 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE -CYDEV_CAN0_RX14_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD -CYDEV_CAN0_RX14_CMD EQU 0x4000a260 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_ID -CYDEV_CAN0_RX14_ID EQU 0x4000a264 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_DH -CYDEV_CAN0_RX14_DH EQU 0x4000a268 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_DL -CYDEV_CAN0_RX14_DL EQU 0x4000a26c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR -CYDEV_CAN0_RX14_AMR EQU 0x4000a270 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR -CYDEV_CAN0_RX14_ACR EQU 0x4000a274 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD -CYDEV_CAN0_RX14_AMRD EQU 0x4000a278 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD -CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE -CYDEV_CAN0_RX15_BASE EQU 0x4000a280 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE -CYDEV_CAN0_RX15_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD -CYDEV_CAN0_RX15_CMD EQU 0x4000a280 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_ID -CYDEV_CAN0_RX15_ID EQU 0x4000a284 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_DH -CYDEV_CAN0_RX15_DH EQU 0x4000a288 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_DL -CYDEV_CAN0_RX15_DL EQU 0x4000a28c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR -CYDEV_CAN0_RX15_AMR EQU 0x4000a290 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR -CYDEV_CAN0_RX15_ACR EQU 0x4000a294 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD -CYDEV_CAN0_RX15_AMRD EQU 0x4000a298 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD -CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_BASE -CYDEV_DFB0_BASE EQU 0x4000c000 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_SIZE -CYDEV_DFB0_SIZE EQU 0x000007b5 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE -CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE -CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE -CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE -CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE -CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE -CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE -CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE -CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE -CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE -CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE -CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE -CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE -CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE -CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE -CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE -CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE -CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE -CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE -CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE -CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE -CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE -CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE -CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE -CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CR -CYDEV_DFB0_CR EQU 0x4000c780 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_SR -CYDEV_DFB0_SR EQU 0x4000c784 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_RAM_EN -CYDEV_DFB0_RAM_EN EQU 0x4000c788 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR -CYDEV_DFB0_RAM_DIR EQU 0x4000c78c - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_SEMA -CYDEV_DFB0_SEMA EQU 0x4000c790 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL -CYDEV_DFB0_DSI_CTRL EQU 0x4000c794 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL -CYDEV_DFB0_INT_CTRL EQU 0x4000c798 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL -CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_STAGEA -CYDEV_DFB0_STAGEA EQU 0x4000c7a0 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_STAGEAM -CYDEV_DFB0_STAGEAM EQU 0x4000c7a1 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_STAGEAH -CYDEV_DFB0_STAGEAH EQU 0x4000c7a2 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_STAGEB -CYDEV_DFB0_STAGEB EQU 0x4000c7a4 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_STAGEBM -CYDEV_DFB0_STAGEBM EQU 0x4000c7a5 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_STAGEBH -CYDEV_DFB0_STAGEBH EQU 0x4000c7a6 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDA -CYDEV_DFB0_HOLDA EQU 0x4000c7a8 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDAM -CYDEV_DFB0_HOLDAM EQU 0x4000c7a9 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDAH -CYDEV_DFB0_HOLDAH EQU 0x4000c7aa - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDAS -CYDEV_DFB0_HOLDAS EQU 0x4000c7ab - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDB -CYDEV_DFB0_HOLDB EQU 0x4000c7ac - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDBM -CYDEV_DFB0_HOLDBM EQU 0x4000c7ad - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDBH -CYDEV_DFB0_HOLDBH EQU 0x4000c7ae - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_HOLDBS -CYDEV_DFB0_HOLDBS EQU 0x4000c7af - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_COHER -CYDEV_DFB0_COHER EQU 0x4000c7b0 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DALIGN -CYDEV_DFB0_DALIGN EQU 0x4000c7b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BASE -CYDEV_UCFG_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_SIZE -CYDEV_UCFG_SIZE EQU 0x00005040 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_BASE -CYDEV_UCFG_B0_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE -CYDEV_UCFG_B0_SIZE EQU 0x00000fef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE -CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE -CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE -CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE -CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0 -CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1 -CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2 -CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3 -CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4 -CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5 -CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6 -CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7 -CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8 -CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9 -CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10 -CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11 -CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0 -CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1 -CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2 -CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3 -CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0 -CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1 -CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2 -CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3 -CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4 -CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5 -CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6 -CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7 -CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8 -CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9 -CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10 -CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11 -CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12 -CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13 -CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14 -CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15 -CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16 -CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17 -CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18 -CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19 -CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20 -CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21 -CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22 -CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23 -CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24 -CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25 -CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26 -CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27 -CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28 -CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29 -CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30 -CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31 -CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0 -CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1 -CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2 -CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3 -CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4 -CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5 -CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6 -CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7 -CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE -CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE -CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0 -CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1 -CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2 -CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3 -CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4 -CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5 -CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6 -CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7 -CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8 -CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9 -CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10 -CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11 -CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0 -CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1 -CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2 -CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3 -CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0 -CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1 -CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2 -CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3 -CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4 -CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5 -CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6 -CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7 -CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8 -CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9 -CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10 -CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11 -CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12 -CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13 -CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14 -CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15 -CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16 -CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17 -CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18 -CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19 -CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20 -CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21 -CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22 -CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23 -CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24 -CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25 -CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26 -CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27 -CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28 -CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29 -CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30 -CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31 -CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0 -CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1 -CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2 -CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3 -CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4 -CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5 -CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6 -CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7 -CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE -CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE -CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE -CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE -CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE -CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE -CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0 -CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1 -CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2 -CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3 -CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4 -CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5 -CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6 -CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7 -CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8 -CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9 -CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10 -CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11 -CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0 -CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1 -CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2 -CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3 -CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0 -CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1 -CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2 -CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3 -CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4 -CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5 -CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6 -CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7 -CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8 -CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9 -CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10 -CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11 -CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12 -CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13 -CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14 -CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15 -CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16 -CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17 -CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18 -CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19 -CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20 -CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21 -CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22 -CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23 -CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24 -CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25 -CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26 -CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27 -CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28 -CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29 -CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30 -CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31 -CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0 -CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1 -CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2 -CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3 -CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4 -CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5 -CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6 -CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7 -CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE -CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE -CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0 -CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1 -CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2 -CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3 -CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4 -CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5 -CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6 -CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7 -CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8 -CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9 -CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10 -CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11 -CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0 -CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1 -CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2 -CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3 -CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0 -CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1 -CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2 -CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3 -CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4 -CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5 -CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6 -CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7 -CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8 -CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9 -CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10 -CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11 -CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12 -CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13 -CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14 -CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15 -CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16 -CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17 -CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18 -CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19 -CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20 -CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21 -CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22 -CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23 -CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24 -CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25 -CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26 -CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27 -CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28 -CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29 -CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30 -CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31 -CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0 -CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1 -CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2 -CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3 -CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4 -CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5 -CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6 -CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7 -CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE -CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE -CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE -CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE -CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE -CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE -CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0 -CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1 -CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2 -CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3 -CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4 -CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5 -CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6 -CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7 -CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8 -CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9 -CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10 -CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11 -CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0 -CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1 -CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2 -CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3 -CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0 -CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1 -CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2 -CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3 -CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4 -CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5 -CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6 -CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7 -CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8 -CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9 -CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10 -CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11 -CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12 -CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13 -CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14 -CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15 -CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16 -CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17 -CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18 -CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19 -CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20 -CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21 -CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22 -CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23 -CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24 -CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25 -CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26 -CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27 -CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28 -CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29 -CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30 -CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31 -CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0 -CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1 -CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2 -CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3 -CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4 -CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5 -CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6 -CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7 -CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE -CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE -CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0 -CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1 -CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2 -CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3 -CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4 -CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5 -CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6 -CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7 -CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8 -CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9 -CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10 -CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11 -CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0 -CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1 -CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2 -CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3 -CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0 -CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1 -CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2 -CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3 -CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4 -CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5 -CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6 -CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7 -CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8 -CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9 -CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10 -CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11 -CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12 -CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13 -CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14 -CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15 -CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16 -CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17 -CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18 -CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19 -CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20 -CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21 -CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22 -CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23 -CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24 -CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25 -CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26 -CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27 -CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28 -CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29 -CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30 -CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31 -CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0 -CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1 -CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2 -CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3 -CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4 -CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5 -CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6 -CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7 -CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE -CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE -CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE -CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE -CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE -CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE -CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0 -CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1 -CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2 -CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3 -CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4 -CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5 -CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6 -CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7 -CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8 -CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9 -CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10 -CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11 -CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0 -CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1 -CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2 -CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3 -CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0 -CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1 -CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2 -CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3 -CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4 -CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5 -CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6 -CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7 -CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8 -CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9 -CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10 -CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11 -CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12 -CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13 -CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14 -CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15 -CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16 -CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17 -CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18 -CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19 -CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20 -CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21 -CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22 -CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23 -CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24 -CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25 -CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26 -CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27 -CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28 -CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29 -CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30 -CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31 -CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0 -CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1 -CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2 -CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3 -CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4 -CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5 -CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6 -CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7 -CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE -CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE -CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0 -CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1 -CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2 -CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3 -CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4 -CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5 -CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6 -CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7 -CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8 -CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9 -CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10 -CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11 -CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0 -CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1 -CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2 -CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3 -CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0 -CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1 -CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2 -CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3 -CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4 -CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5 -CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6 -CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7 -CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8 -CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9 -CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10 -CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11 -CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12 -CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13 -CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14 -CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15 -CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16 -CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17 -CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18 -CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19 -CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20 -CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21 -CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22 -CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23 -CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24 -CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25 -CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26 -CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27 -CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28 -CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29 -CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30 -CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31 -CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0 -CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1 -CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2 -CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3 -CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4 -CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5 -CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6 -CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7 -CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE -CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE -CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE -CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE -CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE -CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE -CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0 -CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1 -CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2 -CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3 -CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4 -CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5 -CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6 -CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7 -CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8 -CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9 -CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10 -CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11 -CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0 -CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1 -CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2 -CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3 -CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0 -CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1 -CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2 -CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3 -CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4 -CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5 -CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6 -CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7 -CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8 -CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9 -CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10 -CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11 -CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12 -CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13 -CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14 -CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15 -CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16 -CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17 -CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18 -CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19 -CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20 -CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21 -CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22 -CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23 -CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24 -CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25 -CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26 -CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27 -CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28 -CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29 -CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30 -CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31 -CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0 -CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1 -CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2 -CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3 -CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4 -CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5 -CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6 -CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7 -CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE -CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE -CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0 -CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1 -CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2 -CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3 -CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4 -CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5 -CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6 -CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7 -CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8 -CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9 -CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10 -CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11 -CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0 -CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1 -CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2 -CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3 -CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0 -CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1 -CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2 -CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3 -CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4 -CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5 -CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6 -CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7 -CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8 -CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9 -CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10 -CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11 -CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12 -CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13 -CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14 -CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15 -CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16 -CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17 -CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18 -CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19 -CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20 -CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21 -CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22 -CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23 -CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24 -CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25 -CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26 -CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27 -CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28 -CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29 -CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30 -CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31 -CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0 -CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1 -CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2 -CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3 -CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4 -CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5 -CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6 -CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7 -CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE -CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE -CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE -CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE -CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE -CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE -CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0 -CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1 -CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2 -CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3 -CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4 -CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5 -CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6 -CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7 -CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8 -CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9 -CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10 -CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11 -CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0 -CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1 -CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2 -CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3 -CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0 -CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1 -CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2 -CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3 -CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4 -CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5 -CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6 -CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7 -CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8 -CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9 -CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10 -CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11 -CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12 -CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13 -CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14 -CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15 -CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16 -CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17 -CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18 -CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19 -CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20 -CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21 -CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22 -CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23 -CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24 -CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25 -CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26 -CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27 -CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28 -CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29 -CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30 -CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31 -CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0 -CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1 -CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2 -CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3 -CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4 -CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5 -CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6 -CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7 -CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE -CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE -CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0 -CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1 -CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2 -CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3 -CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4 -CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5 -CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6 -CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7 -CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8 -CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9 -CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10 -CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11 -CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0 -CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1 -CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2 -CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3 -CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0 -CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1 -CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2 -CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3 -CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4 -CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5 -CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6 -CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7 -CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8 -CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9 -CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10 -CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11 -CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12 -CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13 -CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14 -CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15 -CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16 -CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17 -CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18 -CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19 -CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20 -CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21 -CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22 -CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23 -CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24 -CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25 -CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26 -CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27 -CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28 -CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29 -CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30 -CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31 -CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0 -CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1 -CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2 -CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3 -CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4 -CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5 -CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6 -CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7 -CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE -CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE -CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE -CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE -CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE -CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE -CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0 -CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1 -CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2 -CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3 -CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4 -CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5 -CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6 -CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7 -CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8 -CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9 -CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10 -CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11 -CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0 -CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1 -CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2 -CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3 -CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0 -CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1 -CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2 -CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3 -CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4 -CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5 -CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6 -CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7 -CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8 -CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9 -CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10 -CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11 -CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12 -CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13 -CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14 -CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15 -CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16 -CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17 -CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18 -CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19 -CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20 -CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21 -CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22 -CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23 -CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24 -CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25 -CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26 -CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27 -CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28 -CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29 -CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30 -CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31 -CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0 -CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1 -CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2 -CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3 -CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4 -CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5 -CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6 -CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7 -CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE -CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE -CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0 -CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1 -CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2 -CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3 -CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4 -CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5 -CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6 -CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7 -CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8 -CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9 -CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10 -CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11 -CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0 -CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1 -CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2 -CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3 -CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0 -CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1 -CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2 -CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3 -CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4 -CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5 -CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6 -CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7 -CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8 -CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9 -CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10 -CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11 -CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12 -CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13 -CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14 -CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15 -CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16 -CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17 -CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18 -CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19 -CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20 -CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21 -CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22 -CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23 -CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24 -CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25 -CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26 -CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27 -CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28 -CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29 -CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30 -CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31 -CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0 -CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1 -CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2 -CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3 -CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4 -CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5 -CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6 -CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7 -CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE -CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE -CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE -CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE -CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE -CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE -CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0 -CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1 -CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2 -CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3 -CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4 -CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5 -CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6 -CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7 -CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8 -CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9 -CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10 -CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11 -CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0 -CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1 -CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2 -CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3 -CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB -CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS -CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0 -CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1 -CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2 -CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3 -CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4 -CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5 -CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6 -CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7 -CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8 -CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9 -CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10 -CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11 -CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12 -CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13 -CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14 -CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15 -CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16 -CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17 -CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18 -CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19 -CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20 -CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21 -CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22 -CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23 -CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24 -CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25 -CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26 -CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27 -CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28 -CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29 -CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30 -CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31 -CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0 -CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1 -CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2 -CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3 -CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4 -CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5 -CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6 -CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7 -CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE -CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE -CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0 -CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1 -CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2 -CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3 -CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4 -CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5 -CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6 -CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7 -CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8 -CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9 -CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10 -CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11 -CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0 -CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1 -CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2 -CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3 -CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB -CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS -CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0 -CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1 -CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2 -CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3 -CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4 -CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5 -CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6 -CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7 -CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8 -CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9 -CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10 -CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11 -CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12 -CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13 -CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14 -CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15 -CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16 -CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17 -CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18 -CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19 -CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20 -CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21 -CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22 -CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23 -CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24 -CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25 -CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26 -CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27 -CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28 -CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29 -CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30 -CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31 -CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0 -CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1 -CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2 -CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3 -CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4 -CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5 -CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6 -CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7 -CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE -CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE -CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_BASE -CYDEV_UCFG_B1_BASE EQU 0x40011000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE -CYDEV_UCFG_B1_SIZE EQU 0x00000fef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE -CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE -CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE -CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE -CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0 -CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1 -CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2 -CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3 -CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4 -CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5 -CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6 -CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7 -CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8 -CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9 -CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10 -CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11 -CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0 -CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1 -CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2 -CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3 -CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB -CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS -CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0 -CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1 -CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2 -CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3 -CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4 -CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5 -CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6 -CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7 -CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8 -CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9 -CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10 -CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11 -CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12 -CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13 -CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14 -CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15 -CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16 -CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17 -CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18 -CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19 -CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20 -CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21 -CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22 -CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23 -CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24 -CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25 -CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26 -CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27 -CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28 -CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29 -CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30 -CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31 -CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0 -CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1 -CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2 -CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3 -CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4 -CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5 -CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6 -CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7 -CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE -CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE -CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0 -CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1 -CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2 -CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3 -CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4 -CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5 -CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6 -CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7 -CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8 -CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9 -CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10 -CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11 -CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0 -CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1 -CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2 -CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3 -CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB -CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS -CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0 -CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1 -CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2 -CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3 -CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4 -CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5 -CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6 -CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7 -CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8 -CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9 -CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10 -CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11 -CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12 -CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13 -CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14 -CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15 -CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16 -CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17 -CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18 -CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19 -CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20 -CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21 -CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22 -CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23 -CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24 -CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25 -CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26 -CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27 -CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28 -CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29 -CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30 -CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31 -CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0 -CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1 -CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2 -CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3 -CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4 -CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5 -CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6 -CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7 -CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE -CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE -CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE -CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE -CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE -CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE -CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0 -CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1 -CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2 -CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3 -CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4 -CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5 -CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6 -CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7 -CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8 -CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9 -CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10 -CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11 -CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0 -CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1 -CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2 -CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3 -CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB -CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS -CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0 -CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1 -CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2 -CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3 -CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4 -CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5 -CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6 -CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7 -CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8 -CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9 -CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10 -CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11 -CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12 -CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13 -CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14 -CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15 -CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16 -CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17 -CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18 -CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19 -CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20 -CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21 -CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22 -CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23 -CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24 -CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25 -CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26 -CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27 -CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28 -CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29 -CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30 -CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31 -CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0 -CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1 -CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2 -CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3 -CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4 -CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5 -CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6 -CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7 -CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE -CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE -CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0 -CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1 -CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2 -CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3 -CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4 -CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5 -CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6 -CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7 -CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8 -CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9 -CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10 -CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11 -CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0 -CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1 -CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2 -CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3 -CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB -CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS -CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0 -CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1 -CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2 -CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3 -CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4 -CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5 -CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6 -CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7 -CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8 -CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9 -CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10 -CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11 -CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12 -CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13 -CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14 -CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15 -CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16 -CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17 -CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18 -CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19 -CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20 -CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21 -CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22 -CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23 -CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24 -CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25 -CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26 -CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27 -CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28 -CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29 -CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30 -CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31 -CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0 -CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1 -CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2 -CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3 -CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4 -CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5 -CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6 -CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7 -CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE -CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE -CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE -CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE -CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE -CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE -CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0 -CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1 -CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2 -CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3 -CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4 -CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5 -CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6 -CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7 -CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8 -CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9 -CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10 -CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11 -CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0 -CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1 -CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2 -CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3 -CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB -CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS -CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0 -CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1 -CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2 -CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3 -CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4 -CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5 -CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6 -CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7 -CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8 -CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9 -CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10 -CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11 -CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12 -CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13 -CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14 -CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15 -CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16 -CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17 -CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18 -CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19 -CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20 -CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21 -CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22 -CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23 -CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24 -CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25 -CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26 -CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27 -CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28 -CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29 -CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30 -CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31 -CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0 -CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1 -CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2 -CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3 -CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4 -CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5 -CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6 -CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7 -CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE -CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE -CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0 -CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1 -CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2 -CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3 -CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4 -CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5 -CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6 -CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7 -CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8 -CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9 -CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10 -CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11 -CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0 -CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1 -CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2 -CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3 -CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB -CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS -CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0 -CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1 -CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2 -CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3 -CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4 -CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5 -CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6 -CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7 -CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8 -CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9 -CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10 -CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11 -CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12 -CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13 -CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14 -CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15 -CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16 -CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17 -CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18 -CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19 -CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20 -CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21 -CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22 -CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23 -CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24 -CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25 -CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26 -CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27 -CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28 -CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29 -CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30 -CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31 -CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0 -CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1 -CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2 -CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3 -CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4 -CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5 -CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6 -CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7 -CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE -CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE -CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE -CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE -CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE -CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE -CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0 -CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1 -CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2 -CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3 -CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4 -CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5 -CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6 -CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7 -CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8 -CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9 -CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10 -CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11 -CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0 -CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1 -CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2 -CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3 -CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB -CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS -CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0 -CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1 -CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2 -CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3 -CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4 -CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5 -CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6 -CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7 -CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8 -CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9 -CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10 -CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11 -CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12 -CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13 -CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14 -CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15 -CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16 -CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17 -CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18 -CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19 -CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20 -CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21 -CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22 -CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23 -CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24 -CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25 -CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26 -CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27 -CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28 -CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29 -CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30 -CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31 -CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0 -CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1 -CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2 -CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3 -CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4 -CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5 -CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6 -CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7 -CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE -CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE -CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0 -CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1 -CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2 -CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3 -CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4 -CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5 -CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6 -CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7 -CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8 -CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9 -CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10 -CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11 -CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0 -CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1 -CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2 -CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3 -CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST -CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB -CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET -CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS -CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0 -CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1 -CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2 -CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3 -CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4 -CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5 -CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6 -CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7 -CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8 -CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9 -CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10 -CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11 -CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12 -CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13 -CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14 -CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15 -CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16 -CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17 -CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18 -CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19 -CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20 -CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21 -CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22 -CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23 -CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24 -CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25 -CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26 -CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27 -CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28 -CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29 -CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30 -CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31 -CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0 -CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1 -CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2 -CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3 -CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4 -CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5 -CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6 -CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7 -CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE -CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE -CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE -CYDEV_UCFG_DSI0_BASE EQU 0x40014000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE -CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE -CYDEV_UCFG_DSI1_BASE EQU 0x40014100 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE -CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE -CYDEV_UCFG_DSI2_BASE EQU 0x40014200 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE -CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE -CYDEV_UCFG_DSI3_BASE EQU 0x40014300 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE -CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE -CYDEV_UCFG_DSI4_BASE EQU 0x40014400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE -CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE -CYDEV_UCFG_DSI5_BASE EQU 0x40014500 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE -CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE -CYDEV_UCFG_DSI6_BASE EQU 0x40014600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE -CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE -CYDEV_UCFG_DSI7_BASE EQU 0x40014700 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE -CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE -CYDEV_UCFG_DSI8_BASE EQU 0x40014800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE -CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE -CYDEV_UCFG_DSI9_BASE EQU 0x40014900 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE -CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE -CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE -CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE -CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE -CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE -CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE -CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN -CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN -CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG -CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL -CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3 -CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0 -CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0 -CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1 -CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1 -CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2 -CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2 -CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3 -CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3 -CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE -CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE -CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN -CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN -CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG -CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL -CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3 -CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0 -CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0 -CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1 -CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1 -CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2 -CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2 -CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3 -CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3 -CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_BASE -CYDEV_IDMUX_BASE EQU 0x40015100 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_SIZE -CYDEV_IDMUX_SIZE EQU 0x00000016 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0 -CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1 -CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2 -CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3 -CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4 -CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5 -CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6 -CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7 -CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0 -CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1 -CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2 -CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3 -CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4 -CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5 -CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115 - ENDIF - IF :LNOT::DEF:CYDEV_CACHERAM_BASE -CYDEV_CACHERAM_BASE EQU 0x40030000 - ENDIF - IF :LNOT::DEF:CYDEV_CACHERAM_SIZE -CYDEV_CACHERAM_SIZE EQU 0x00000400 - ENDIF - IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE -CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000 - ENDIF - IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE -CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_BASE -CYDEV_SFR_BASE EQU 0x40050100 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_SIZE -CYDEV_SFR_SIZE EQU 0x000000fb - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO0 -CYDEV_SFR_GPIO0 EQU 0x40050180 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD0 -CYDEV_SFR_GPIRD0 EQU 0x40050189 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL -CYDEV_SFR_GPIO0_SEL EQU 0x4005018a - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO1 -CYDEV_SFR_GPIO1 EQU 0x40050190 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD1 -CYDEV_SFR_GPIRD1 EQU 0x40050191 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO2 -CYDEV_SFR_GPIO2 EQU 0x40050198 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD2 -CYDEV_SFR_GPIRD2 EQU 0x40050199 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL -CYDEV_SFR_GPIO2_SEL EQU 0x4005019a - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL -CYDEV_SFR_GPIO1_SEL EQU 0x400501a2 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO3 -CYDEV_SFR_GPIO3 EQU 0x400501b0 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD3 -CYDEV_SFR_GPIRD3 EQU 0x400501b1 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL -CYDEV_SFR_GPIO3_SEL EQU 0x400501b2 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO4 -CYDEV_SFR_GPIO4 EQU 0x400501c0 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD4 -CYDEV_SFR_GPIRD4 EQU 0x400501c1 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL -CYDEV_SFR_GPIO4_SEL EQU 0x400501c2 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO5 -CYDEV_SFR_GPIO5 EQU 0x400501c8 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD5 -CYDEV_SFR_GPIRD5 EQU 0x400501c9 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL -CYDEV_SFR_GPIO5_SEL EQU 0x400501ca - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO6 -CYDEV_SFR_GPIO6 EQU 0x400501d8 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD6 -CYDEV_SFR_GPIRD6 EQU 0x400501d9 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL -CYDEV_SFR_GPIO6_SEL EQU 0x400501da - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO12 -CYDEV_SFR_GPIO12 EQU 0x400501e8 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD12 -CYDEV_SFR_GPIRD12 EQU 0x400501e9 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL -CYDEV_SFR_GPIO12_SEL EQU 0x400501f2 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO15 -CYDEV_SFR_GPIO15 EQU 0x400501f8 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIRD15 -CYDEV_SFR_GPIRD15 EQU 0x400501f9 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL -CYDEV_SFR_GPIO15_SEL EQU 0x400501fa - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_BASE -CYDEV_P3BA_BASE EQU 0x40050300 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_SIZE -CYDEV_P3BA_SIZE EQU 0x0000002b - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_Y_START -CYDEV_P3BA_Y_START EQU 0x40050300 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_YROLL -CYDEV_P3BA_YROLL EQU 0x40050301 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_YCFG -CYDEV_P3BA_YCFG EQU 0x40050302 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_X_START1 -CYDEV_P3BA_X_START1 EQU 0x40050303 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_X_START2 -CYDEV_P3BA_X_START2 EQU 0x40050304 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_XROLL1 -CYDEV_P3BA_XROLL1 EQU 0x40050305 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_XROLL2 -CYDEV_P3BA_XROLL2 EQU 0x40050306 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_XINC -CYDEV_P3BA_XINC EQU 0x40050307 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_XCFG -CYDEV_P3BA_XCFG EQU 0x40050308 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1 -CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2 -CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3 -CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1 -CYDEV_P3BA_ABSADDR1 EQU 0x4005030c - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2 -CYDEV_P3BA_ABSADDR2 EQU 0x4005030d - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3 -CYDEV_P3BA_ABSADDR3 EQU 0x4005030e - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4 -CYDEV_P3BA_ABSADDR4 EQU 0x4005030f - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_DATCFG1 -CYDEV_P3BA_DATCFG1 EQU 0x40050310 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_DATCFG2 -CYDEV_P3BA_DATCFG2 EQU 0x40050311 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1 -CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2 -CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3 -CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4 -CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1 -CYDEV_P3BA_DATA_REG1 EQU 0x40050318 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2 -CYDEV_P3BA_DATA_REG2 EQU 0x40050319 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3 -CYDEV_P3BA_DATA_REG3 EQU 0x4005031a - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4 -CYDEV_P3BA_DATA_REG4 EQU 0x4005031b - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1 -CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2 -CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3 -CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4 -CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1 -CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2 -CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3 -CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4 -CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_BIST_EN -CYDEV_P3BA_BIST_EN EQU 0x40050324 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR -CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1 -CYDEV_P3BA_SEQCFG1 EQU 0x40050326 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2 -CYDEV_P3BA_SEQCFG2 EQU 0x40050327 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_Y_CURR -CYDEV_P3BA_Y_CURR EQU 0x40050328 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_X_CURR1 -CYDEV_P3BA_X_CURR1 EQU 0x40050329 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_X_CURR2 -CYDEV_P3BA_X_CURR2 EQU 0x4005032a - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_BASE -CYDEV_PANTHER_BASE EQU 0x40080000 - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_SIZE -CYDEV_PANTHER_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG -CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000 - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE -CYDEV_PANTHER_WAITPIPE EQU 0x40080004 - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG -CYDEV_PANTHER_TRACE_CFG EQU 0x40080008 - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG -CYDEV_PANTHER_DBG_CFG EQU 0x4008000c - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT -CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID -CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c - ENDIF - IF :LNOT::DEF:CYDEV_FLSECC_BASE -CYDEV_FLSECC_BASE EQU 0x48000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSECC_SIZE -CYDEV_FLSECC_SIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE -CYDEV_FLSECC_DATA_MBASE EQU 0x48000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE -CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_BASE -CYDEV_FLSHID_BASE EQU 0x49000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_SIZE -CYDEV_FLSHID_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE -CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE -CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE -CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE -CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE -CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE -CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC -CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC -CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM -CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB -CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB -CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK -CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR -CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR -CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ -CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ -CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ -CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ -CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ -CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ -CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ -CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB -CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS -CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS -CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS -CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS -CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS -CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS -CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS -CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS -CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1 -CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2 -CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3 -CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4 -CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5 -CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6 -CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7 -CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8 -CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1 -CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2 -CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3 -CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4 -CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5 -CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6 -CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7 -CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8 -CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1 -CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2 -CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3 -CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4 -CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5 -CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6 -CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7 -CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8 -CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1 -CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2 -CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3 -CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4 -CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5 -CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6 -CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7 -CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8 -CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1 -CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2 -CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3 -CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4 -CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5 -CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6 -CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7 -CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8 -CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE -CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE -CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1 -CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0 -CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0 -CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0 -CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0 -CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1 -CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1 -CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1 -CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1 -CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM -CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce - ENDIF - IF :LNOT::DEF:CYDEV_EXTMEM_BASE -CYDEV_EXTMEM_BASE EQU 0x60000000 - ENDIF - IF :LNOT::DEF:CYDEV_EXTMEM_SIZE -CYDEV_EXTMEM_SIZE EQU 0x00800000 - ENDIF - IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE -CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000 - ENDIF - IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE -CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_BASE -CYDEV_ITM_BASE EQU 0xe0000000 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_SIZE -CYDEV_ITM_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_TRACE_EN -CYDEV_ITM_TRACE_EN EQU 0xe0000e00 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE -CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL -CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS -CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS -CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID4 -CYDEV_ITM_PID4 EQU 0xe0000fd0 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID5 -CYDEV_ITM_PID5 EQU 0xe0000fd4 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID6 -CYDEV_ITM_PID6 EQU 0xe0000fd8 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID7 -CYDEV_ITM_PID7 EQU 0xe0000fdc - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID0 -CYDEV_ITM_PID0 EQU 0xe0000fe0 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID1 -CYDEV_ITM_PID1 EQU 0xe0000fe4 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID2 -CYDEV_ITM_PID2 EQU 0xe0000fe8 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_PID3 -CYDEV_ITM_PID3 EQU 0xe0000fec - ENDIF - IF :LNOT::DEF:CYDEV_ITM_CID0 -CYDEV_ITM_CID0 EQU 0xe0000ff0 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_CID1 -CYDEV_ITM_CID1 EQU 0xe0000ff4 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_CID2 -CYDEV_ITM_CID2 EQU 0xe0000ff8 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_CID3 -CYDEV_ITM_CID3 EQU 0xe0000ffc - ENDIF - IF :LNOT::DEF:CYDEV_DWT_BASE -CYDEV_DWT_BASE EQU 0xe0001000 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_SIZE -CYDEV_DWT_SIZE EQU 0x0000005c - ENDIF - IF :LNOT::DEF:CYDEV_DWT_CTRL -CYDEV_DWT_CTRL EQU 0xe0001000 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT -CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT -CYDEV_DWT_CPI_COUNT EQU 0xe0001008 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT -CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c - ENDIF - IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT -CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT -CYDEV_DWT_LSU_COUNT EQU 0xe0001014 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT -CYDEV_DWT_FOLD_COUNT EQU 0xe0001018 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE -CYDEV_DWT_PC_SAMPLE EQU 0xe000101c - ENDIF - IF :LNOT::DEF:CYDEV_DWT_COMP_0 -CYDEV_DWT_COMP_0 EQU 0xe0001020 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_MASK_0 -CYDEV_DWT_MASK_0 EQU 0xe0001024 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0 -CYDEV_DWT_FUNCTION_0 EQU 0xe0001028 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_COMP_1 -CYDEV_DWT_COMP_1 EQU 0xe0001030 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_MASK_1 -CYDEV_DWT_MASK_1 EQU 0xe0001034 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1 -CYDEV_DWT_FUNCTION_1 EQU 0xe0001038 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_COMP_2 -CYDEV_DWT_COMP_2 EQU 0xe0001040 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_MASK_2 -CYDEV_DWT_MASK_2 EQU 0xe0001044 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2 -CYDEV_DWT_FUNCTION_2 EQU 0xe0001048 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_COMP_3 -CYDEV_DWT_COMP_3 EQU 0xe0001050 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_MASK_3 -CYDEV_DWT_MASK_3 EQU 0xe0001054 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3 -CYDEV_DWT_FUNCTION_3 EQU 0xe0001058 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_BASE -CYDEV_FPB_BASE EQU 0xe0002000 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_SIZE -CYDEV_FPB_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_CTRL -CYDEV_FPB_CTRL EQU 0xe0002000 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_REMAP -CYDEV_FPB_REMAP EQU 0xe0002004 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0 -CYDEV_FPB_FP_COMP_0 EQU 0xe0002008 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1 -CYDEV_FPB_FP_COMP_1 EQU 0xe000200c - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2 -CYDEV_FPB_FP_COMP_2 EQU 0xe0002010 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3 -CYDEV_FPB_FP_COMP_3 EQU 0xe0002014 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4 -CYDEV_FPB_FP_COMP_4 EQU 0xe0002018 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5 -CYDEV_FPB_FP_COMP_5 EQU 0xe000201c - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6 -CYDEV_FPB_FP_COMP_6 EQU 0xe0002020 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7 -CYDEV_FPB_FP_COMP_7 EQU 0xe0002024 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID4 -CYDEV_FPB_PID4 EQU 0xe0002fd0 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID5 -CYDEV_FPB_PID5 EQU 0xe0002fd4 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID6 -CYDEV_FPB_PID6 EQU 0xe0002fd8 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID7 -CYDEV_FPB_PID7 EQU 0xe0002fdc - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID0 -CYDEV_FPB_PID0 EQU 0xe0002fe0 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID1 -CYDEV_FPB_PID1 EQU 0xe0002fe4 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID2 -CYDEV_FPB_PID2 EQU 0xe0002fe8 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_PID3 -CYDEV_FPB_PID3 EQU 0xe0002fec - ENDIF - IF :LNOT::DEF:CYDEV_FPB_CID0 -CYDEV_FPB_CID0 EQU 0xe0002ff0 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_CID1 -CYDEV_FPB_CID1 EQU 0xe0002ff4 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_CID2 -CYDEV_FPB_CID2 EQU 0xe0002ff8 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_CID3 -CYDEV_FPB_CID3 EQU 0xe0002ffc - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_BASE -CYDEV_NVIC_BASE EQU 0xe000e000 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SIZE -CYDEV_NVIC_SIZE EQU 0x00000d3c - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE -CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL -CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD -CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT -CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL -CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SETENA0 -CYDEV_NVIC_SETENA0 EQU 0xe000e100 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_CLRENA0 -CYDEV_NVIC_CLRENA0 EQU 0xe000e180 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SETPEND0 -CYDEV_NVIC_SETPEND0 EQU 0xe000e200 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0 -CYDEV_NVIC_CLRPEND0 EQU 0xe000e280 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0 -CYDEV_NVIC_ACTIVE0 EQU 0xe000e300 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_0 -CYDEV_NVIC_PRI_0 EQU 0xe000e400 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_1 -CYDEV_NVIC_PRI_1 EQU 0xe000e401 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_2 -CYDEV_NVIC_PRI_2 EQU 0xe000e402 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_3 -CYDEV_NVIC_PRI_3 EQU 0xe000e403 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_4 -CYDEV_NVIC_PRI_4 EQU 0xe000e404 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_5 -CYDEV_NVIC_PRI_5 EQU 0xe000e405 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_6 -CYDEV_NVIC_PRI_6 EQU 0xe000e406 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_7 -CYDEV_NVIC_PRI_7 EQU 0xe000e407 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_8 -CYDEV_NVIC_PRI_8 EQU 0xe000e408 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_9 -CYDEV_NVIC_PRI_9 EQU 0xe000e409 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_10 -CYDEV_NVIC_PRI_10 EQU 0xe000e40a - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_11 -CYDEV_NVIC_PRI_11 EQU 0xe000e40b - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_12 -CYDEV_NVIC_PRI_12 EQU 0xe000e40c - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_13 -CYDEV_NVIC_PRI_13 EQU 0xe000e40d - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_14 -CYDEV_NVIC_PRI_14 EQU 0xe000e40e - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_15 -CYDEV_NVIC_PRI_15 EQU 0xe000e40f - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_16 -CYDEV_NVIC_PRI_16 EQU 0xe000e410 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_17 -CYDEV_NVIC_PRI_17 EQU 0xe000e411 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_18 -CYDEV_NVIC_PRI_18 EQU 0xe000e412 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_19 -CYDEV_NVIC_PRI_19 EQU 0xe000e413 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_20 -CYDEV_NVIC_PRI_20 EQU 0xe000e414 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_21 -CYDEV_NVIC_PRI_21 EQU 0xe000e415 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_22 -CYDEV_NVIC_PRI_22 EQU 0xe000e416 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_23 -CYDEV_NVIC_PRI_23 EQU 0xe000e417 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_24 -CYDEV_NVIC_PRI_24 EQU 0xe000e418 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_25 -CYDEV_NVIC_PRI_25 EQU 0xe000e419 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_26 -CYDEV_NVIC_PRI_26 EQU 0xe000e41a - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_27 -CYDEV_NVIC_PRI_27 EQU 0xe000e41b - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_28 -CYDEV_NVIC_PRI_28 EQU 0xe000e41c - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_29 -CYDEV_NVIC_PRI_29 EQU 0xe000e41d - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_30 -CYDEV_NVIC_PRI_30 EQU 0xe000e41e - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_PRI_31 -CYDEV_NVIC_PRI_31 EQU 0xe000e41f - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE -CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE -CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET -CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR -CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL -CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL -CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 -CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 -CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 -CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR -CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS -CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS -CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS -CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS -CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS -CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD -CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD -CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_BASE -CYDEV_CORE_DBG_BASE EQU 0xe000edf0 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE -CYDEV_CORE_DBG_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS -CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL -CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA -CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL -CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_BASE -CYDEV_TPIU_BASE EQU 0xe0040000 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_SIZE -CYDEV_TPIU_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ -CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ -CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER -CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL -CYDEV_TPIU_PROTOCOL EQU 0xe00400f0 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT -CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL -CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_TRIGGER -CYDEV_TPIU_TRIGGER EQU 0xe0040ee8 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA -CYDEV_TPIU_ITETMDATA EQU 0xe0040eec - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2 -CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0 -CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA -CYDEV_TPIU_ITITMDATA EQU 0xe0040efc - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_ITCTRL -CYDEV_TPIU_ITCTRL EQU 0xe0040f00 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_DEVID -CYDEV_TPIU_DEVID EQU 0xe0040fc8 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE -CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID4 -CYDEV_TPIU_PID4 EQU 0xe0040fd0 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID5 -CYDEV_TPIU_PID5 EQU 0xe0040fd4 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID6 -CYDEV_TPIU_PID6 EQU 0xe0040fd8 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID7 -CYDEV_TPIU_PID7 EQU 0xe0040fdc - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID0 -CYDEV_TPIU_PID0 EQU 0xe0040fe0 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID1 -CYDEV_TPIU_PID1 EQU 0xe0040fe4 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID2 -CYDEV_TPIU_PID2 EQU 0xe0040fe8 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_PID3 -CYDEV_TPIU_PID3 EQU 0xe0040fec - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_CID0 -CYDEV_TPIU_CID0 EQU 0xe0040ff0 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_CID1 -CYDEV_TPIU_CID1 EQU 0xe0040ff4 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_CID2 -CYDEV_TPIU_CID2 EQU 0xe0040ff8 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_CID3 -CYDEV_TPIU_CID3 EQU 0xe0040ffc - ENDIF - IF :LNOT::DEF:CYDEV_ETM_BASE -CYDEV_ETM_BASE EQU 0xe0041000 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_SIZE -CYDEV_ETM_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CTL -CYDEV_ETM_CTL EQU 0xe0041000 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CFG_CODE -CYDEV_ETM_CFG_CODE EQU 0xe0041004 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT -CYDEV_ETM_TRIG_EVENT EQU 0xe0041008 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_STATUS -CYDEV_ETM_STATUS EQU 0xe0041010 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_SYS_CFG -CYDEV_ETM_SYS_CFG EQU 0xe0041014 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT -CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1 -CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL -CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c - ENDIF - IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ -CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_ETM_ID -CYDEV_ETM_ETM_ID EQU 0xe00411e4 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT -CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL -CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID -CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS -CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS -CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PDSR -CYDEV_ETM_PDSR EQU 0xe0041314 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_ITMISCIN -CYDEV_ETM_ITMISCIN EQU 0xe0041ee0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT -CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2 -CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0 -CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL -CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET -CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR -CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS -CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS -CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS -CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE -CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID4 -CYDEV_ETM_PID4 EQU 0xe0041fd0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID5 -CYDEV_ETM_PID5 EQU 0xe0041fd4 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID6 -CYDEV_ETM_PID6 EQU 0xe0041fd8 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID7 -CYDEV_ETM_PID7 EQU 0xe0041fdc - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID0 -CYDEV_ETM_PID0 EQU 0xe0041fe0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID1 -CYDEV_ETM_PID1 EQU 0xe0041fe4 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID2 -CYDEV_ETM_PID2 EQU 0xe0041fe8 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_PID3 -CYDEV_ETM_PID3 EQU 0xe0041fec - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CID0 -CYDEV_ETM_CID0 EQU 0xe0041ff0 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CID1 -CYDEV_ETM_CID1 EQU 0xe0041ff4 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CID2 -CYDEV_ETM_CID2 EQU 0xe0041ff8 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_CID3 -CYDEV_ETM_CID3 EQU 0xe0041ffc - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE -CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE -CYDEV_ROM_TABLE_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC -CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT -CYDEV_ROM_TABLE_DWT EQU 0xe00ff004 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB -CYDEV_ROM_TABLE_FPB EQU 0xe00ff008 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM -CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU -CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM -CYDEV_ROM_TABLE_ETM EQU 0xe00ff014 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_END -CYDEV_ROM_TABLE_END EQU 0xe00ff018 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE -CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4 -CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5 -CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6 -CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7 -CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0 -CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1 -CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2 -CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3 -CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0 -CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1 -CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2 -CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3 -CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc - ENDIF - IF :LNOT::DEF:CYDEV_FLS_SIZE -CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE - ENDIF - IF :LNOT::DEF:CYDEV_ECC_BASE -CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE - ENDIF - IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE -CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 - ENDIF - IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE -CYDEV_FLS_ROW_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE -CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE -CYDEV_ECC_ROW_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE -CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 - ENDIF - IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE -CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PERIPH_BASE -CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE - ENDIF - IF :LNOT::DEF:CYCLK_LD_DISABLE -CYCLK_LD_DISABLE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYCLK_LD_SYNC_EN -CYCLK_LD_SYNC_EN EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYCLK_LD_LOAD -CYCLK_LD_LOAD EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYCLK_PIPE -CYCLK_PIPE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYCLK_SSS -CYCLK_SSS EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYCLK_EARLY -CYCLK_EARLY EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYCLK_DUTY -CYCLK_DUTY EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYCLK_SYNC -CYCLK_SYNC EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D -CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG -CYCLK_SRC_SEL_SYNC_DIG EQU 0 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_IMO -CYCLK_SRC_SEL_IMO EQU 1 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ -CYCLK_SRC_SEL_XTAL_MHZ EQU 2 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM -CYCLK_SRC_SEL_XTALM EQU 2 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_ILO -CYCLK_SRC_SEL_ILO EQU 3 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_PLL -CYCLK_SRC_SEL_PLL EQU 4 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ -CYCLK_SRC_SEL_XTAL_KHZ EQU 5 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK -CYCLK_SRC_SEL_XTALK EQU 5 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G -CYCLK_SRC_SEL_DSI_G EQU 6 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D -CYCLK_SRC_SEL_DSI_D EQU 7 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A -CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A -CYCLK_SRC_SEL_DSI_A EQU 7 - ENDIF - END diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc deleted file mode 100755 index d4d800c..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydevicerv_trm.inc +++ /dev/null @@ -1,16039 +0,0 @@ -; -; FILENAME: cydevicerv_trm.inc -; -; PSoC Creator 3.0 Component Pack 7 -; -; DESCRIPTION: -; This file provides all of the address values for the entire PSoC device. -; -;------------------------------------------------------------------------------- -; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -; You may use this file only in accordance with the license, terms, conditions, -; disclaimers, and limitations in the end user license agreement accompanying -; the software package with which this file was provided. -;------------------------------------------------------------------------------- - - IF :LNOT::DEF:CYDEV_FLASH_BASE -CYDEV_FLASH_BASE EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLASH_SIZE -CYDEV_FLASH_SIZE EQU 0x00020000 - ENDIF - IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE -CYREG_FLASH_DATA_MBASE EQU 0x00000000 - ENDIF - IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE -CYREG_FLASH_DATA_MSIZE EQU 0x00020000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_BASE -CYDEV_SRAM_BASE EQU 0x1fffc000 - ENDIF - IF :LNOT::DEF:CYDEV_SRAM_SIZE -CYDEV_SRAM_SIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE -CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE -CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE -CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE -CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE -CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE -CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE -CYREG_SRAM_CODE_MBASE EQU 0x1fffc000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE -CYREG_SRAM_CODE_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE -CYREG_SRAM_DATA_MBASE EQU 0x20000000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE -CYREG_SRAM_DATA_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE -CYREG_SRAM_DATA16K_MBASE EQU 0x20001000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE -CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE -CYREG_SRAM_DATA32K_MBASE EQU 0x20002000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE -CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE -CYREG_SRAM_DATA64K_MBASE EQU 0x20004000 - ENDIF - IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE -CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_BASE -CYDEV_DMA_BASE EQU 0x20008000 - ENDIF - IF :LNOT::DEF:CYDEV_DMA_SIZE -CYDEV_DMA_SIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE -CYREG_DMA_SRAM64K_MBASE EQU 0x20008000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE -CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE -CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE -CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE -CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE -CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE -CYREG_DMA_SRAM_MBASE EQU 0x2000f000 - ENDIF - IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE -CYREG_DMA_SRAM_MSIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_BASE -CYDEV_CLKDIST_BASE EQU 0x40004000 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_SIZE -CYDEV_CLKDIST_SIZE EQU 0x00000110 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_CR -CYREG_CLKDIST_CR EQU 0x40004000 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_LD -CYREG_CLKDIST_LD EQU 0x40004001 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_WRK0 -CYREG_CLKDIST_WRK0 EQU 0x40004002 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_WRK1 -CYREG_CLKDIST_WRK1 EQU 0x40004003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_MSTR0 -CYREG_CLKDIST_MSTR0 EQU 0x40004004 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_MSTR1 -CYREG_CLKDIST_MSTR1 EQU 0x40004005 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_BCFG0 -CYREG_CLKDIST_BCFG0 EQU 0x40004006 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_BCFG1 -CYREG_CLKDIST_BCFG1 EQU 0x40004007 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_BCFG2 -CYREG_CLKDIST_BCFG2 EQU 0x40004008 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_UCFG -CYREG_CLKDIST_UCFG EQU 0x40004009 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DLY0 -CYREG_CLKDIST_DLY0 EQU 0x4000400a - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DLY1 -CYREG_CLKDIST_DLY1 EQU 0x4000400b - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DMASK -CYREG_CLKDIST_DMASK EQU 0x40004010 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_AMASK -CYREG_CLKDIST_AMASK EQU 0x40004014 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE -CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE -CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0 -CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1 -CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2 -CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE -CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE -CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0 -CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1 -CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2 -CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE -CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE -CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0 -CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1 -CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2 -CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE -CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE -CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0 -CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1 -CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2 -CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE -CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE -CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0 -CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1 -CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2 -CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE -CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE -CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0 -CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1 -CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2 -CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE -CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE -CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0 -CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1 -CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2 -CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE -CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE -CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0 -CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1 -CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2 -CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE -CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE -CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0 -CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1 -CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2 -CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3 -CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE -CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE -CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0 -CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1 -CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2 -CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3 -CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE -CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE -CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0 -CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1 -CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2 -CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3 -CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE -CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c - ENDIF - IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE -CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0 -CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1 -CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2 -CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e - ENDIF - IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3 -CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_BASE -CYDEV_FASTCLK_BASE EQU 0x40004200 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_SIZE -CYDEV_FASTCLK_SIZE EQU 0x00000026 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE -CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE -CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR -CYREG_FASTCLK_IMO_CR EQU 0x40004200 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE -CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE -CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR -CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0 -CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1 -CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE -CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 - ENDIF - IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE -CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0 -CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1 -CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_PLL_P -CYREG_FASTCLK_PLL_P EQU 0x40004222 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q -CYREG_FASTCLK_PLL_Q EQU 0x40004223 - ENDIF - IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR -CYREG_FASTCLK_PLL_SR EQU 0x40004225 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_BASE -CYDEV_SLOWCLK_BASE EQU 0x40004300 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE -CYDEV_SLOWCLK_SIZE EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE -CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE -CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0 -CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300 - ENDIF - IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1 -CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE -CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 - ENDIF - IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE -CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR -CYREG_SLOWCLK_X32_CR EQU 0x40004308 - ENDIF - IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG -CYREG_SLOWCLK_X32_CFG EQU 0x40004309 - ENDIF - IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST -CYREG_SLOWCLK_X32_TST EQU 0x4000430a - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_BASE -CYDEV_BOOST_BASE EQU 0x40004320 - ENDIF - IF :LNOT::DEF:CYDEV_BOOST_SIZE -CYDEV_BOOST_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_BOOST_CR0 -CYREG_BOOST_CR0 EQU 0x40004320 - ENDIF - IF :LNOT::DEF:CYREG_BOOST_CR1 -CYREG_BOOST_CR1 EQU 0x40004321 - ENDIF - IF :LNOT::DEF:CYREG_BOOST_CR2 -CYREG_BOOST_CR2 EQU 0x40004322 - ENDIF - IF :LNOT::DEF:CYREG_BOOST_CR3 -CYREG_BOOST_CR3 EQU 0x40004323 - ENDIF - IF :LNOT::DEF:CYREG_BOOST_SR -CYREG_BOOST_SR EQU 0x40004324 - ENDIF - IF :LNOT::DEF:CYREG_BOOST_CR4 -CYREG_BOOST_CR4 EQU 0x40004325 - ENDIF - IF :LNOT::DEF:CYREG_BOOST_SR2 -CYREG_BOOST_SR2 EQU 0x40004326 - ENDIF - IF :LNOT::DEF:CYDEV_PWRSYS_BASE -CYDEV_PWRSYS_BASE EQU 0x40004330 - ENDIF - IF :LNOT::DEF:CYDEV_PWRSYS_SIZE -CYDEV_PWRSYS_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_CR0 -CYREG_PWRSYS_CR0 EQU 0x40004330 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_CR1 -CYREG_PWRSYS_CR1 EQU 0x40004331 - ENDIF - IF :LNOT::DEF:CYDEV_PM_BASE -CYDEV_PM_BASE EQU 0x40004380 - ENDIF - IF :LNOT::DEF:CYDEV_PM_SIZE -CYDEV_PM_SIZE EQU 0x00000057 - ENDIF - IF :LNOT::DEF:CYREG_PM_TW_CFG0 -CYREG_PM_TW_CFG0 EQU 0x40004380 - ENDIF - IF :LNOT::DEF:CYREG_PM_TW_CFG1 -CYREG_PM_TW_CFG1 EQU 0x40004381 - ENDIF - IF :LNOT::DEF:CYREG_PM_TW_CFG2 -CYREG_PM_TW_CFG2 EQU 0x40004382 - ENDIF - IF :LNOT::DEF:CYREG_PM_WDT_CFG -CYREG_PM_WDT_CFG EQU 0x40004383 - ENDIF - IF :LNOT::DEF:CYREG_PM_WDT_CR -CYREG_PM_WDT_CR EQU 0x40004384 - ENDIF - IF :LNOT::DEF:CYREG_PM_INT_SR -CYREG_PM_INT_SR EQU 0x40004390 - ENDIF - IF :LNOT::DEF:CYREG_PM_MODE_CFG0 -CYREG_PM_MODE_CFG0 EQU 0x40004391 - ENDIF - IF :LNOT::DEF:CYREG_PM_MODE_CFG1 -CYREG_PM_MODE_CFG1 EQU 0x40004392 - ENDIF - IF :LNOT::DEF:CYREG_PM_MODE_CSR -CYREG_PM_MODE_CSR EQU 0x40004393 - ENDIF - IF :LNOT::DEF:CYREG_PM_USB_CR0 -CYREG_PM_USB_CR0 EQU 0x40004394 - ENDIF - IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0 -CYREG_PM_WAKEUP_CFG0 EQU 0x40004398 - ENDIF - IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1 -CYREG_PM_WAKEUP_CFG1 EQU 0x40004399 - ENDIF - IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2 -CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_BASE -CYDEV_PM_ACT_BASE EQU 0x400043a0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_ACT_SIZE -CYDEV_PM_ACT_SIZE EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG0 -CYREG_PM_ACT_CFG0 EQU 0x400043a0 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG1 -CYREG_PM_ACT_CFG1 EQU 0x400043a1 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG2 -CYREG_PM_ACT_CFG2 EQU 0x400043a2 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG3 -CYREG_PM_ACT_CFG3 EQU 0x400043a3 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG4 -CYREG_PM_ACT_CFG4 EQU 0x400043a4 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG5 -CYREG_PM_ACT_CFG5 EQU 0x400043a5 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG6 -CYREG_PM_ACT_CFG6 EQU 0x400043a6 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG7 -CYREG_PM_ACT_CFG7 EQU 0x400043a7 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG8 -CYREG_PM_ACT_CFG8 EQU 0x400043a8 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG9 -CYREG_PM_ACT_CFG9 EQU 0x400043a9 - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG10 -CYREG_PM_ACT_CFG10 EQU 0x400043aa - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG11 -CYREG_PM_ACT_CFG11 EQU 0x400043ab - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG12 -CYREG_PM_ACT_CFG12 EQU 0x400043ac - ENDIF - IF :LNOT::DEF:CYREG_PM_ACT_CFG13 -CYREG_PM_ACT_CFG13 EQU 0x400043ad - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_BASE -CYDEV_PM_STBY_BASE EQU 0x400043b0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_STBY_SIZE -CYDEV_PM_STBY_SIZE EQU 0x0000000e - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG0 -CYREG_PM_STBY_CFG0 EQU 0x400043b0 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG1 -CYREG_PM_STBY_CFG1 EQU 0x400043b1 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG2 -CYREG_PM_STBY_CFG2 EQU 0x400043b2 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG3 -CYREG_PM_STBY_CFG3 EQU 0x400043b3 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG4 -CYREG_PM_STBY_CFG4 EQU 0x400043b4 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG5 -CYREG_PM_STBY_CFG5 EQU 0x400043b5 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG6 -CYREG_PM_STBY_CFG6 EQU 0x400043b6 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG7 -CYREG_PM_STBY_CFG7 EQU 0x400043b7 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG8 -CYREG_PM_STBY_CFG8 EQU 0x400043b8 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG9 -CYREG_PM_STBY_CFG9 EQU 0x400043b9 - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG10 -CYREG_PM_STBY_CFG10 EQU 0x400043ba - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG11 -CYREG_PM_STBY_CFG11 EQU 0x400043bb - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG12 -CYREG_PM_STBY_CFG12 EQU 0x400043bc - ENDIF - IF :LNOT::DEF:CYREG_PM_STBY_CFG13 -CYREG_PM_STBY_CFG13 EQU 0x400043bd - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE -CYDEV_PM_AVAIL_BASE EQU 0x400043c0 - ENDIF - IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE -CYDEV_PM_AVAIL_SIZE EQU 0x00000017 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_CR0 -CYREG_PM_AVAIL_CR0 EQU 0x400043c0 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_CR1 -CYREG_PM_AVAIL_CR1 EQU 0x400043c1 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_CR2 -CYREG_PM_AVAIL_CR2 EQU 0x400043c2 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_CR3 -CYREG_PM_AVAIL_CR3 EQU 0x400043c3 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_CR4 -CYREG_PM_AVAIL_CR4 EQU 0x400043c4 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_CR5 -CYREG_PM_AVAIL_CR5 EQU 0x400043c5 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_CR6 -CYREG_PM_AVAIL_CR6 EQU 0x400043c6 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_SR0 -CYREG_PM_AVAIL_SR0 EQU 0x400043d0 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_SR1 -CYREG_PM_AVAIL_SR1 EQU 0x400043d1 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_SR2 -CYREG_PM_AVAIL_SR2 EQU 0x400043d2 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_SR3 -CYREG_PM_AVAIL_SR3 EQU 0x400043d3 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_SR4 -CYREG_PM_AVAIL_SR4 EQU 0x400043d4 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_SR5 -CYREG_PM_AVAIL_SR5 EQU 0x400043d5 - ENDIF - IF :LNOT::DEF:CYREG_PM_AVAIL_SR6 -CYREG_PM_AVAIL_SR6 EQU 0x400043d6 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_BASE -CYDEV_PICU_BASE EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SIZE -CYDEV_PICU_SIZE EQU 0x000000b0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE -CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE -CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE -CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE -CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE0 -CYREG_PICU0_INTTYPE0 EQU 0x40004500 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE1 -CYREG_PICU0_INTTYPE1 EQU 0x40004501 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE2 -CYREG_PICU0_INTTYPE2 EQU 0x40004502 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE3 -CYREG_PICU0_INTTYPE3 EQU 0x40004503 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE4 -CYREG_PICU0_INTTYPE4 EQU 0x40004504 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE5 -CYREG_PICU0_INTTYPE5 EQU 0x40004505 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE6 -CYREG_PICU0_INTTYPE6 EQU 0x40004506 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTTYPE7 -CYREG_PICU0_INTTYPE7 EQU 0x40004507 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE -CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE -CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE0 -CYREG_PICU1_INTTYPE0 EQU 0x40004508 - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE1 -CYREG_PICU1_INTTYPE1 EQU 0x40004509 - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE2 -CYREG_PICU1_INTTYPE2 EQU 0x4000450a - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE3 -CYREG_PICU1_INTTYPE3 EQU 0x4000450b - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE4 -CYREG_PICU1_INTTYPE4 EQU 0x4000450c - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE5 -CYREG_PICU1_INTTYPE5 EQU 0x4000450d - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE6 -CYREG_PICU1_INTTYPE6 EQU 0x4000450e - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTTYPE7 -CYREG_PICU1_INTTYPE7 EQU 0x4000450f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE -CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE -CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE0 -CYREG_PICU2_INTTYPE0 EQU 0x40004510 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE1 -CYREG_PICU2_INTTYPE1 EQU 0x40004511 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE2 -CYREG_PICU2_INTTYPE2 EQU 0x40004512 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE3 -CYREG_PICU2_INTTYPE3 EQU 0x40004513 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE4 -CYREG_PICU2_INTTYPE4 EQU 0x40004514 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE5 -CYREG_PICU2_INTTYPE5 EQU 0x40004515 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE6 -CYREG_PICU2_INTTYPE6 EQU 0x40004516 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTTYPE7 -CYREG_PICU2_INTTYPE7 EQU 0x40004517 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE -CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE -CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE0 -CYREG_PICU3_INTTYPE0 EQU 0x40004518 - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE1 -CYREG_PICU3_INTTYPE1 EQU 0x40004519 - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE2 -CYREG_PICU3_INTTYPE2 EQU 0x4000451a - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE3 -CYREG_PICU3_INTTYPE3 EQU 0x4000451b - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE4 -CYREG_PICU3_INTTYPE4 EQU 0x4000451c - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE5 -CYREG_PICU3_INTTYPE5 EQU 0x4000451d - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE6 -CYREG_PICU3_INTTYPE6 EQU 0x4000451e - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTTYPE7 -CYREG_PICU3_INTTYPE7 EQU 0x4000451f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE -CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE -CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE0 -CYREG_PICU4_INTTYPE0 EQU 0x40004520 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE1 -CYREG_PICU4_INTTYPE1 EQU 0x40004521 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE2 -CYREG_PICU4_INTTYPE2 EQU 0x40004522 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE3 -CYREG_PICU4_INTTYPE3 EQU 0x40004523 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE4 -CYREG_PICU4_INTTYPE4 EQU 0x40004524 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE5 -CYREG_PICU4_INTTYPE5 EQU 0x40004525 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE6 -CYREG_PICU4_INTTYPE6 EQU 0x40004526 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTTYPE7 -CYREG_PICU4_INTTYPE7 EQU 0x40004527 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE -CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE -CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE0 -CYREG_PICU5_INTTYPE0 EQU 0x40004528 - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE1 -CYREG_PICU5_INTTYPE1 EQU 0x40004529 - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE2 -CYREG_PICU5_INTTYPE2 EQU 0x4000452a - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE3 -CYREG_PICU5_INTTYPE3 EQU 0x4000452b - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE4 -CYREG_PICU5_INTTYPE4 EQU 0x4000452c - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE5 -CYREG_PICU5_INTTYPE5 EQU 0x4000452d - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE6 -CYREG_PICU5_INTTYPE6 EQU 0x4000452e - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTTYPE7 -CYREG_PICU5_INTTYPE7 EQU 0x4000452f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE -CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE -CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE0 -CYREG_PICU6_INTTYPE0 EQU 0x40004530 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE1 -CYREG_PICU6_INTTYPE1 EQU 0x40004531 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE2 -CYREG_PICU6_INTTYPE2 EQU 0x40004532 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE3 -CYREG_PICU6_INTTYPE3 EQU 0x40004533 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE4 -CYREG_PICU6_INTTYPE4 EQU 0x40004534 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE5 -CYREG_PICU6_INTTYPE5 EQU 0x40004535 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE6 -CYREG_PICU6_INTTYPE6 EQU 0x40004536 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTTYPE7 -CYREG_PICU6_INTTYPE7 EQU 0x40004537 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE -CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE -CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE0 -CYREG_PICU12_INTTYPE0 EQU 0x40004560 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE1 -CYREG_PICU12_INTTYPE1 EQU 0x40004561 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE2 -CYREG_PICU12_INTTYPE2 EQU 0x40004562 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE3 -CYREG_PICU12_INTTYPE3 EQU 0x40004563 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE4 -CYREG_PICU12_INTTYPE4 EQU 0x40004564 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE5 -CYREG_PICU12_INTTYPE5 EQU 0x40004565 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE6 -CYREG_PICU12_INTTYPE6 EQU 0x40004566 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTTYPE7 -CYREG_PICU12_INTTYPE7 EQU 0x40004567 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE -CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE -CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE0 -CYREG_PICU15_INTTYPE0 EQU 0x40004578 - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE1 -CYREG_PICU15_INTTYPE1 EQU 0x40004579 - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE2 -CYREG_PICU15_INTTYPE2 EQU 0x4000457a - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE3 -CYREG_PICU15_INTTYPE3 EQU 0x4000457b - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE4 -CYREG_PICU15_INTTYPE4 EQU 0x4000457c - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE5 -CYREG_PICU15_INTTYPE5 EQU 0x4000457d - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE6 -CYREG_PICU15_INTTYPE6 EQU 0x4000457e - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTTYPE7 -CYREG_PICU15_INTTYPE7 EQU 0x4000457f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_BASE -CYDEV_PICU_STAT_BASE EQU 0x40004580 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE -CYDEV_PICU_STAT_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE -CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE -CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_INTSTAT -CYREG_PICU0_INTSTAT EQU 0x40004580 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE -CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE -CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU1_INTSTAT -CYREG_PICU1_INTSTAT EQU 0x40004581 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE -CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE -CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_INTSTAT -CYREG_PICU2_INTSTAT EQU 0x40004582 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE -CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE -CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU3_INTSTAT -CYREG_PICU3_INTSTAT EQU 0x40004583 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE -CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE -CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_INTSTAT -CYREG_PICU4_INTSTAT EQU 0x40004584 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE -CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE -CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU5_INTSTAT -CYREG_PICU5_INTSTAT EQU 0x40004585 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE -CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE -CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_INTSTAT -CYREG_PICU6_INTSTAT EQU 0x40004586 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE -CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE -CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_INTSTAT -CYREG_PICU12_INTSTAT EQU 0x4000458c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE -CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE -CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU15_INTSTAT -CYREG_PICU15_INTSTAT EQU 0x4000458f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE -CYDEV_PICU_SNAP_BASE EQU 0x40004590 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE -CYDEV_PICU_SNAP_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE -CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE -CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_SNAP -CYREG_PICU0_SNAP EQU 0x40004590 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE -CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE -CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU1_SNAP -CYREG_PICU1_SNAP EQU 0x40004591 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE -CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE -CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_SNAP -CYREG_PICU2_SNAP EQU 0x40004592 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE -CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE -CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU3_SNAP -CYREG_PICU3_SNAP EQU 0x40004593 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE -CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE -CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_SNAP -CYREG_PICU4_SNAP EQU 0x40004594 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE -CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE -CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU5_SNAP -CYREG_PICU5_SNAP EQU 0x40004595 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE -CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE -CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_SNAP -CYREG_PICU6_SNAP EQU 0x40004596 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE -CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE -CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_SNAP -CYREG_PICU12_SNAP EQU 0x4000459c - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE -CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE -CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU_15_SNAP_15 -CYREG_PICU_15_SNAP_15 EQU 0x4000459f - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE -CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE -CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE -CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE -CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR -CYREG_PICU0_DISABLE_COR EQU 0x400045a0 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE -CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE -CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR -CYREG_PICU1_DISABLE_COR EQU 0x400045a1 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE -CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE -CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR -CYREG_PICU2_DISABLE_COR EQU 0x400045a2 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE -CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE -CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR -CYREG_PICU3_DISABLE_COR EQU 0x400045a3 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE -CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE -CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR -CYREG_PICU4_DISABLE_COR EQU 0x400045a4 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE -CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE -CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR -CYREG_PICU5_DISABLE_COR EQU 0x400045a5 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE -CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE -CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR -CYREG_PICU6_DISABLE_COR EQU 0x400045a6 - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE -CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE -CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR -CYREG_PICU12_DISABLE_COR EQU 0x400045ac - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE -CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af - ENDIF - IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE -CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR -CYREG_PICU15_DISABLE_COR EQU 0x400045af - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_BASE -CYDEV_MFGCFG_BASE EQU 0x40004600 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_SIZE -CYDEV_MFGCFG_SIZE EQU 0x000000ed - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE -CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE -CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE -CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE -CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_TR -CYREG_DAC0_TR EQU 0x40004608 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE -CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE -CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC1_TR -CYREG_DAC1_TR EQU 0x40004609 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE -CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE -CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_TR -CYREG_DAC2_TR EQU 0x4000460a - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE -CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE -CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC3_TR -CYREG_DAC3_TR EQU 0x4000460b - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE -CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE -CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0 -CYREG_NPUMP_DSM_TR0 EQU 0x40004610 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE -CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE -CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_NPUMP_SC_TR0 -CYREG_NPUMP_SC_TR0 EQU 0x40004611 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE -CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE -CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0 -CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE -CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE -CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_TR0 -CYREG_SAR0_TR0 EQU 0x40004614 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE -CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE -CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_TR0 -CYREG_SAR1_TR0 EQU 0x40004616 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE -CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP0_TR0 -CYREG_OPAMP0_TR0 EQU 0x40004620 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP0_TR1 -CYREG_OPAMP0_TR1 EQU 0x40004621 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE -CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP1_TR0 -CYREG_OPAMP1_TR0 EQU 0x40004622 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP1_TR1 -CYREG_OPAMP1_TR1 EQU 0x40004623 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE -CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP2_TR0 -CYREG_OPAMP2_TR0 EQU 0x40004624 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP2_TR1 -CYREG_OPAMP2_TR1 EQU 0x40004625 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE -CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE -CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP3_TR0 -CYREG_OPAMP3_TR0 EQU 0x40004626 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP3_TR1 -CYREG_OPAMP3_TR1 EQU 0x40004627 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE -CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE -CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_TR0 -CYREG_CMP0_TR0 EQU 0x40004630 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_TR1 -CYREG_CMP0_TR1 EQU 0x40004631 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE -CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE -CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CMP1_TR0 -CYREG_CMP1_TR0 EQU 0x40004632 - ENDIF - IF :LNOT::DEF:CYREG_CMP1_TR1 -CYREG_CMP1_TR1 EQU 0x40004633 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE -CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE -CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_TR0 -CYREG_CMP2_TR0 EQU 0x40004634 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_TR1 -CYREG_CMP2_TR1 EQU 0x40004635 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE -CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE -CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CMP3_TR0 -CYREG_CMP3_TR0 EQU 0x40004636 - ENDIF - IF :LNOT::DEF:CYREG_CMP3_TR1 -CYREG_CMP3_TR1 EQU 0x40004637 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE -CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE -CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0 -CYREG_PWRSYS_HIB_TR0 EQU 0x40004680 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1 -CYREG_PWRSYS_HIB_TR1 EQU 0x40004681 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR -CYREG_PWRSYS_I2C_TR EQU 0x40004682 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR -CYREG_PWRSYS_SLP_TR EQU 0x40004683 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR -CYREG_PWRSYS_BUZZ_TR EQU 0x40004684 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0 -CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1 -CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR -CYREG_PWRSYS_BREF_TR EQU 0x40004687 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_BG_TR -CYREG_PWRSYS_BG_TR EQU 0x40004688 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2 -CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689 - ENDIF - IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3 -CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE -CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE -CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_ILO_TR0 -CYREG_ILO_TR0 EQU 0x40004690 - ENDIF - IF :LNOT::DEF:CYREG_ILO_TR1 -CYREG_ILO_TR1 EQU 0x40004691 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE -CYDEV_MFGCFG_X32_BASE EQU 0x40004698 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE -CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_X32_TR -CYREG_X32_TR EQU 0x40004698 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE -CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE -CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_IMO_TR0 -CYREG_IMO_TR0 EQU 0x400046a0 - ENDIF - IF :LNOT::DEF:CYREG_IMO_TR1 -CYREG_IMO_TR1 EQU 0x400046a1 - ENDIF - IF :LNOT::DEF:CYREG_IMO_GAIN -CYREG_IMO_GAIN EQU 0x400046a2 - ENDIF - IF :LNOT::DEF:CYREG_IMO_C36M -CYREG_IMO_C36M EQU 0x400046a3 - ENDIF - IF :LNOT::DEF:CYREG_IMO_TR2 -CYREG_IMO_TR2 EQU 0x400046a4 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE -CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE -CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_XMHZ_TR -CYREG_XMHZ_TR EQU 0x400046a8 - ENDIF - IF :LNOT::DEF:CYREG_MFGCFG_DLY -CYREG_MFGCFG_DLY EQU 0x400046c0 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE -CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE -CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR -CYREG_MLOGIC_DMPSTR EQU 0x400046e2 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE -CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE -CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR -CYREG_MLOGIC_SEG_CR EQU 0x400046e4 - ENDIF - IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0 -CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5 - ENDIF - IF :LNOT::DEF:CYREG_MLOGIC_DEBUG -CYREG_MLOGIC_DEBUG EQU 0x400046e8 - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE -CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea - ENDIF - IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE -CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR -CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea - ENDIF - IF :LNOT::DEF:CYREG_MLOGIC_REV_ID -CYREG_MLOGIC_REV_ID EQU 0x400046ec - ENDIF - IF :LNOT::DEF:CYDEV_RESET_BASE -CYDEV_RESET_BASE EQU 0x400046f0 - ENDIF - IF :LNOT::DEF:CYDEV_RESET_SIZE -CYDEV_RESET_SIZE EQU 0x0000000f - ENDIF - IF :LNOT::DEF:CYREG_RESET_IPOR_CR0 -CYREG_RESET_IPOR_CR0 EQU 0x400046f0 - ENDIF - IF :LNOT::DEF:CYREG_RESET_IPOR_CR1 -CYREG_RESET_IPOR_CR1 EQU 0x400046f1 - ENDIF - IF :LNOT::DEF:CYREG_RESET_IPOR_CR2 -CYREG_RESET_IPOR_CR2 EQU 0x400046f2 - ENDIF - IF :LNOT::DEF:CYREG_RESET_IPOR_CR3 -CYREG_RESET_IPOR_CR3 EQU 0x400046f3 - ENDIF - IF :LNOT::DEF:CYREG_RESET_CR0 -CYREG_RESET_CR0 EQU 0x400046f4 - ENDIF - IF :LNOT::DEF:CYREG_RESET_CR1 -CYREG_RESET_CR1 EQU 0x400046f5 - ENDIF - IF :LNOT::DEF:CYREG_RESET_CR2 -CYREG_RESET_CR2 EQU 0x400046f6 - ENDIF - IF :LNOT::DEF:CYREG_RESET_CR3 -CYREG_RESET_CR3 EQU 0x400046f7 - ENDIF - IF :LNOT::DEF:CYREG_RESET_CR4 -CYREG_RESET_CR4 EQU 0x400046f8 - ENDIF - IF :LNOT::DEF:CYREG_RESET_CR5 -CYREG_RESET_CR5 EQU 0x400046f9 - ENDIF - IF :LNOT::DEF:CYREG_RESET_SR0 -CYREG_RESET_SR0 EQU 0x400046fa - ENDIF - IF :LNOT::DEF:CYREG_RESET_SR1 -CYREG_RESET_SR1 EQU 0x400046fb - ENDIF - IF :LNOT::DEF:CYREG_RESET_SR2 -CYREG_RESET_SR2 EQU 0x400046fc - ENDIF - IF :LNOT::DEF:CYREG_RESET_SR3 -CYREG_RESET_SR3 EQU 0x400046fd - ENDIF - IF :LNOT::DEF:CYREG_RESET_TR -CYREG_RESET_TR EQU 0x400046fe - ENDIF - IF :LNOT::DEF:CYDEV_SPC_BASE -CYDEV_SPC_BASE EQU 0x40004700 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_SIZE -CYDEV_SPC_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYREG_SPC_FM_EE_CR -CYREG_SPC_FM_EE_CR EQU 0x40004700 - ENDIF - IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT -CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701 - ENDIF - IF :LNOT::DEF:CYREG_SPC_EE_SCR -CYREG_SPC_EE_SCR EQU 0x40004702 - ENDIF - IF :LNOT::DEF:CYREG_SPC_EE_ERR -CYREG_SPC_EE_ERR EQU 0x40004703 - ENDIF - IF :LNOT::DEF:CYREG_SPC_CPU_DATA -CYREG_SPC_CPU_DATA EQU 0x40004720 - ENDIF - IF :LNOT::DEF:CYREG_SPC_DMA_DATA -CYREG_SPC_DMA_DATA EQU 0x40004721 - ENDIF - IF :LNOT::DEF:CYREG_SPC_SR -CYREG_SPC_SR EQU 0x40004722 - ENDIF - IF :LNOT::DEF:CYREG_SPC_CR -CYREG_SPC_CR EQU 0x40004723 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE -CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 - ENDIF - IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE -CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE -CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 - ENDIF - IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE -CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_BASE -CYDEV_CACHE_BASE EQU 0x40004800 - ENDIF - IF :LNOT::DEF:CYDEV_CACHE_SIZE -CYDEV_CACHE_SIZE EQU 0x0000009c - ENDIF - IF :LNOT::DEF:CYREG_CACHE_CC_CTL -CYREG_CACHE_CC_CTL EQU 0x40004800 - ENDIF - IF :LNOT::DEF:CYREG_CACHE_ECC_CORR -CYREG_CACHE_ECC_CORR EQU 0x40004880 - ENDIF - IF :LNOT::DEF:CYREG_CACHE_ECC_ERR -CYREG_CACHE_ECC_ERR EQU 0x40004888 - ENDIF - IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR -CYREG_CACHE_FLASH_ERR EQU 0x40004890 - ENDIF - IF :LNOT::DEF:CYREG_CACHE_HITMISS -CYREG_CACHE_HITMISS EQU 0x40004898 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_BASE -CYDEV_I2C_BASE EQU 0x40004900 - ENDIF - IF :LNOT::DEF:CYDEV_I2C_SIZE -CYDEV_I2C_SIZE EQU 0x000000e1 - ENDIF - IF :LNOT::DEF:CYREG_I2C_XCFG -CYREG_I2C_XCFG EQU 0x400049c8 - ENDIF - IF :LNOT::DEF:CYREG_I2C_ADR -CYREG_I2C_ADR EQU 0x400049ca - ENDIF - IF :LNOT::DEF:CYREG_I2C_CFG -CYREG_I2C_CFG EQU 0x400049d6 - ENDIF - IF :LNOT::DEF:CYREG_I2C_CSR -CYREG_I2C_CSR EQU 0x400049d7 - ENDIF - IF :LNOT::DEF:CYREG_I2C_D -CYREG_I2C_D EQU 0x400049d8 - ENDIF - IF :LNOT::DEF:CYREG_I2C_MCSR -CYREG_I2C_MCSR EQU 0x400049d9 - ENDIF - IF :LNOT::DEF:CYREG_I2C_CLK_DIV1 -CYREG_I2C_CLK_DIV1 EQU 0x400049db - ENDIF - IF :LNOT::DEF:CYREG_I2C_CLK_DIV2 -CYREG_I2C_CLK_DIV2 EQU 0x400049dc - ENDIF - IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR -CYREG_I2C_TMOUT_CSR EQU 0x400049dd - ENDIF - IF :LNOT::DEF:CYREG_I2C_TMOUT_SR -CYREG_I2C_TMOUT_SR EQU 0x400049de - ENDIF - IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0 -CYREG_I2C_TMOUT_CFG0 EQU 0x400049df - ENDIF - IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1 -CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_BASE -CYDEV_DEC_BASE EQU 0x40004e00 - ENDIF - IF :LNOT::DEF:CYDEV_DEC_SIZE -CYDEV_DEC_SIZE EQU 0x00000015 - ENDIF - IF :LNOT::DEF:CYREG_DEC_CR -CYREG_DEC_CR EQU 0x40004e00 - ENDIF - IF :LNOT::DEF:CYREG_DEC_SR -CYREG_DEC_SR EQU 0x40004e01 - ENDIF - IF :LNOT::DEF:CYREG_DEC_SHIFT1 -CYREG_DEC_SHIFT1 EQU 0x40004e02 - ENDIF - IF :LNOT::DEF:CYREG_DEC_SHIFT2 -CYREG_DEC_SHIFT2 EQU 0x40004e03 - ENDIF - IF :LNOT::DEF:CYREG_DEC_DR2 -CYREG_DEC_DR2 EQU 0x40004e04 - ENDIF - IF :LNOT::DEF:CYREG_DEC_DR2H -CYREG_DEC_DR2H EQU 0x40004e05 - ENDIF - IF :LNOT::DEF:CYREG_DEC_DR1 -CYREG_DEC_DR1 EQU 0x40004e06 - ENDIF - IF :LNOT::DEF:CYREG_DEC_OCOR -CYREG_DEC_OCOR EQU 0x40004e08 - ENDIF - IF :LNOT::DEF:CYREG_DEC_OCORM -CYREG_DEC_OCORM EQU 0x40004e09 - ENDIF - IF :LNOT::DEF:CYREG_DEC_OCORH -CYREG_DEC_OCORH EQU 0x40004e0a - ENDIF - IF :LNOT::DEF:CYREG_DEC_GCOR -CYREG_DEC_GCOR EQU 0x40004e0c - ENDIF - IF :LNOT::DEF:CYREG_DEC_GCORH -CYREG_DEC_GCORH EQU 0x40004e0d - ENDIF - IF :LNOT::DEF:CYREG_DEC_GVAL -CYREG_DEC_GVAL EQU 0x40004e0e - ENDIF - IF :LNOT::DEF:CYREG_DEC_OUTSAMP -CYREG_DEC_OUTSAMP EQU 0x40004e10 - ENDIF - IF :LNOT::DEF:CYREG_DEC_OUTSAMPM -CYREG_DEC_OUTSAMPM EQU 0x40004e11 - ENDIF - IF :LNOT::DEF:CYREG_DEC_OUTSAMPH -CYREG_DEC_OUTSAMPH EQU 0x40004e12 - ENDIF - IF :LNOT::DEF:CYREG_DEC_OUTSAMPS -CYREG_DEC_OUTSAMPS EQU 0x40004e13 - ENDIF - IF :LNOT::DEF:CYREG_DEC_COHER -CYREG_DEC_COHER EQU 0x40004e14 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_BASE -CYDEV_TMR0_BASE EQU 0x40004f00 - ENDIF - IF :LNOT::DEF:CYDEV_TMR0_SIZE -CYDEV_TMR0_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_TMR0_CFG0 -CYREG_TMR0_CFG0 EQU 0x40004f00 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_CFG1 -CYREG_TMR0_CFG1 EQU 0x40004f01 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_CFG2 -CYREG_TMR0_CFG2 EQU 0x40004f02 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_SR0 -CYREG_TMR0_SR0 EQU 0x40004f03 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_PER0 -CYREG_TMR0_PER0 EQU 0x40004f04 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_PER1 -CYREG_TMR0_PER1 EQU 0x40004f05 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0 -CYREG_TMR0_CNT_CMP0 EQU 0x40004f06 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1 -CYREG_TMR0_CNT_CMP1 EQU 0x40004f07 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_CAP0 -CYREG_TMR0_CAP0 EQU 0x40004f08 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_CAP1 -CYREG_TMR0_CAP1 EQU 0x40004f09 - ENDIF - IF :LNOT::DEF:CYREG_TMR0_RT0 -CYREG_TMR0_RT0 EQU 0x40004f0a - ENDIF - IF :LNOT::DEF:CYREG_TMR0_RT1 -CYREG_TMR0_RT1 EQU 0x40004f0b - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_BASE -CYDEV_TMR1_BASE EQU 0x40004f0c - ENDIF - IF :LNOT::DEF:CYDEV_TMR1_SIZE -CYDEV_TMR1_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_TMR1_CFG0 -CYREG_TMR1_CFG0 EQU 0x40004f0c - ENDIF - IF :LNOT::DEF:CYREG_TMR1_CFG1 -CYREG_TMR1_CFG1 EQU 0x40004f0d - ENDIF - IF :LNOT::DEF:CYREG_TMR1_CFG2 -CYREG_TMR1_CFG2 EQU 0x40004f0e - ENDIF - IF :LNOT::DEF:CYREG_TMR1_SR0 -CYREG_TMR1_SR0 EQU 0x40004f0f - ENDIF - IF :LNOT::DEF:CYREG_TMR1_PER0 -CYREG_TMR1_PER0 EQU 0x40004f10 - ENDIF - IF :LNOT::DEF:CYREG_TMR1_PER1 -CYREG_TMR1_PER1 EQU 0x40004f11 - ENDIF - IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0 -CYREG_TMR1_CNT_CMP0 EQU 0x40004f12 - ENDIF - IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1 -CYREG_TMR1_CNT_CMP1 EQU 0x40004f13 - ENDIF - IF :LNOT::DEF:CYREG_TMR1_CAP0 -CYREG_TMR1_CAP0 EQU 0x40004f14 - ENDIF - IF :LNOT::DEF:CYREG_TMR1_CAP1 -CYREG_TMR1_CAP1 EQU 0x40004f15 - ENDIF - IF :LNOT::DEF:CYREG_TMR1_RT0 -CYREG_TMR1_RT0 EQU 0x40004f16 - ENDIF - IF :LNOT::DEF:CYREG_TMR1_RT1 -CYREG_TMR1_RT1 EQU 0x40004f17 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_BASE -CYDEV_TMR2_BASE EQU 0x40004f18 - ENDIF - IF :LNOT::DEF:CYDEV_TMR2_SIZE -CYDEV_TMR2_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_TMR2_CFG0 -CYREG_TMR2_CFG0 EQU 0x40004f18 - ENDIF - IF :LNOT::DEF:CYREG_TMR2_CFG1 -CYREG_TMR2_CFG1 EQU 0x40004f19 - ENDIF - IF :LNOT::DEF:CYREG_TMR2_CFG2 -CYREG_TMR2_CFG2 EQU 0x40004f1a - ENDIF - IF :LNOT::DEF:CYREG_TMR2_SR0 -CYREG_TMR2_SR0 EQU 0x40004f1b - ENDIF - IF :LNOT::DEF:CYREG_TMR2_PER0 -CYREG_TMR2_PER0 EQU 0x40004f1c - ENDIF - IF :LNOT::DEF:CYREG_TMR2_PER1 -CYREG_TMR2_PER1 EQU 0x40004f1d - ENDIF - IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0 -CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e - ENDIF - IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1 -CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f - ENDIF - IF :LNOT::DEF:CYREG_TMR2_CAP0 -CYREG_TMR2_CAP0 EQU 0x40004f20 - ENDIF - IF :LNOT::DEF:CYREG_TMR2_CAP1 -CYREG_TMR2_CAP1 EQU 0x40004f21 - ENDIF - IF :LNOT::DEF:CYREG_TMR2_RT0 -CYREG_TMR2_RT0 EQU 0x40004f22 - ENDIF - IF :LNOT::DEF:CYREG_TMR2_RT1 -CYREG_TMR2_RT1 EQU 0x40004f23 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_BASE -CYDEV_TMR3_BASE EQU 0x40004f24 - ENDIF - IF :LNOT::DEF:CYDEV_TMR3_SIZE -CYDEV_TMR3_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_TMR3_CFG0 -CYREG_TMR3_CFG0 EQU 0x40004f24 - ENDIF - IF :LNOT::DEF:CYREG_TMR3_CFG1 -CYREG_TMR3_CFG1 EQU 0x40004f25 - ENDIF - IF :LNOT::DEF:CYREG_TMR3_CFG2 -CYREG_TMR3_CFG2 EQU 0x40004f26 - ENDIF - IF :LNOT::DEF:CYREG_TMR3_SR0 -CYREG_TMR3_SR0 EQU 0x40004f27 - ENDIF - IF :LNOT::DEF:CYREG_TMR3_PER0 -CYREG_TMR3_PER0 EQU 0x40004f28 - ENDIF - IF :LNOT::DEF:CYREG_TMR3_PER1 -CYREG_TMR3_PER1 EQU 0x40004f29 - ENDIF - IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0 -CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a - ENDIF - IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1 -CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b - ENDIF - IF :LNOT::DEF:CYREG_TMR3_CAP0 -CYREG_TMR3_CAP0 EQU 0x40004f2c - ENDIF - IF :LNOT::DEF:CYREG_TMR3_CAP1 -CYREG_TMR3_CAP1 EQU 0x40004f2d - ENDIF - IF :LNOT::DEF:CYREG_TMR3_RT0 -CYREG_TMR3_RT0 EQU 0x40004f2e - ENDIF - IF :LNOT::DEF:CYREG_TMR3_RT1 -CYREG_TMR3_RT1 EQU 0x40004f2f - ENDIF - IF :LNOT::DEF:CYDEV_IO_BASE -CYDEV_IO_BASE EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYDEV_IO_SIZE -CYDEV_IO_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_BASE -CYDEV_IO_PC_BASE EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_SIZE -CYDEV_IO_PC_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE -CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE -CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC0 -CYREG_PRT0_PC0 EQU 0x40005000 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC1 -CYREG_PRT0_PC1 EQU 0x40005001 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC2 -CYREG_PRT0_PC2 EQU 0x40005002 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC3 -CYREG_PRT0_PC3 EQU 0x40005003 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC4 -CYREG_PRT0_PC4 EQU 0x40005004 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC5 -CYREG_PRT0_PC5 EQU 0x40005005 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC6 -CYREG_PRT0_PC6 EQU 0x40005006 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PC7 -CYREG_PRT0_PC7 EQU 0x40005007 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE -CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE -CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC0 -CYREG_PRT1_PC0 EQU 0x40005008 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC1 -CYREG_PRT1_PC1 EQU 0x40005009 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC2 -CYREG_PRT1_PC2 EQU 0x4000500a - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC3 -CYREG_PRT1_PC3 EQU 0x4000500b - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC4 -CYREG_PRT1_PC4 EQU 0x4000500c - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC5 -CYREG_PRT1_PC5 EQU 0x4000500d - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC6 -CYREG_PRT1_PC6 EQU 0x4000500e - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PC7 -CYREG_PRT1_PC7 EQU 0x4000500f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE -CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE -CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC0 -CYREG_PRT2_PC0 EQU 0x40005010 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC1 -CYREG_PRT2_PC1 EQU 0x40005011 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC2 -CYREG_PRT2_PC2 EQU 0x40005012 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC3 -CYREG_PRT2_PC3 EQU 0x40005013 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC4 -CYREG_PRT2_PC4 EQU 0x40005014 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC5 -CYREG_PRT2_PC5 EQU 0x40005015 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC6 -CYREG_PRT2_PC6 EQU 0x40005016 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PC7 -CYREG_PRT2_PC7 EQU 0x40005017 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE -CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE -CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC0 -CYREG_PRT3_PC0 EQU 0x40005018 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC1 -CYREG_PRT3_PC1 EQU 0x40005019 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC2 -CYREG_PRT3_PC2 EQU 0x4000501a - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC3 -CYREG_PRT3_PC3 EQU 0x4000501b - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC4 -CYREG_PRT3_PC4 EQU 0x4000501c - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC5 -CYREG_PRT3_PC5 EQU 0x4000501d - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC6 -CYREG_PRT3_PC6 EQU 0x4000501e - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PC7 -CYREG_PRT3_PC7 EQU 0x4000501f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE -CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE -CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC0 -CYREG_PRT4_PC0 EQU 0x40005020 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC1 -CYREG_PRT4_PC1 EQU 0x40005021 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC2 -CYREG_PRT4_PC2 EQU 0x40005022 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC3 -CYREG_PRT4_PC3 EQU 0x40005023 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC4 -CYREG_PRT4_PC4 EQU 0x40005024 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC5 -CYREG_PRT4_PC5 EQU 0x40005025 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC6 -CYREG_PRT4_PC6 EQU 0x40005026 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PC7 -CYREG_PRT4_PC7 EQU 0x40005027 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE -CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE -CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC0 -CYREG_PRT5_PC0 EQU 0x40005028 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC1 -CYREG_PRT5_PC1 EQU 0x40005029 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC2 -CYREG_PRT5_PC2 EQU 0x4000502a - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC3 -CYREG_PRT5_PC3 EQU 0x4000502b - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC4 -CYREG_PRT5_PC4 EQU 0x4000502c - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC5 -CYREG_PRT5_PC5 EQU 0x4000502d - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC6 -CYREG_PRT5_PC6 EQU 0x4000502e - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PC7 -CYREG_PRT5_PC7 EQU 0x4000502f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE -CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE -CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC0 -CYREG_PRT6_PC0 EQU 0x40005030 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC1 -CYREG_PRT6_PC1 EQU 0x40005031 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC2 -CYREG_PRT6_PC2 EQU 0x40005032 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC3 -CYREG_PRT6_PC3 EQU 0x40005033 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC4 -CYREG_PRT6_PC4 EQU 0x40005034 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC5 -CYREG_PRT6_PC5 EQU 0x40005035 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC6 -CYREG_PRT6_PC6 EQU 0x40005036 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PC7 -CYREG_PRT6_PC7 EQU 0x40005037 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE -CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE -CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC0 -CYREG_PRT12_PC0 EQU 0x40005060 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC1 -CYREG_PRT12_PC1 EQU 0x40005061 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC2 -CYREG_PRT12_PC2 EQU 0x40005062 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC3 -CYREG_PRT12_PC3 EQU 0x40005063 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC4 -CYREG_PRT12_PC4 EQU 0x40005064 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC5 -CYREG_PRT12_PC5 EQU 0x40005065 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC6 -CYREG_PRT12_PC6 EQU 0x40005066 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PC7 -CYREG_PRT12_PC7 EQU 0x40005067 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE -CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE -CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0 -CYREG_IO_PC_PRT15_PC0 EQU 0x40005078 - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1 -CYREG_IO_PC_PRT15_PC1 EQU 0x40005079 - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2 -CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3 -CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4 -CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5 -CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE -CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e - ENDIF - IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE -CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0 -CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e - ENDIF - IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1 -CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_BASE -CYDEV_IO_DR_BASE EQU 0x40005080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_SIZE -CYDEV_IO_DR_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE -CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE -CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS -CYREG_PRT0_DR_ALIAS EQU 0x40005080 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE -CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE -CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS -CYREG_PRT1_DR_ALIAS EQU 0x40005081 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE -CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE -CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS -CYREG_PRT2_DR_ALIAS EQU 0x40005082 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE -CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE -CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS -CYREG_PRT3_DR_ALIAS EQU 0x40005083 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE -CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE -CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS -CYREG_PRT4_DR_ALIAS EQU 0x40005084 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE -CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE -CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS -CYREG_PRT5_DR_ALIAS EQU 0x40005085 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE -CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE -CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS -CYREG_PRT6_DR_ALIAS EQU 0x40005086 - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE -CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE -CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS -CYREG_PRT12_DR_ALIAS EQU 0x4000508c - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE -CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f - ENDIF - IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE -CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS -CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_BASE -CYDEV_IO_PS_BASE EQU 0x40005090 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_SIZE -CYDEV_IO_PS_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE -CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE -CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS -CYREG_PRT0_PS_ALIAS EQU 0x40005090 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE -CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE -CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS -CYREG_PRT1_PS_ALIAS EQU 0x40005091 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE -CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE -CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS -CYREG_PRT2_PS_ALIAS EQU 0x40005092 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE -CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE -CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS -CYREG_PRT3_PS_ALIAS EQU 0x40005093 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE -CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE -CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS -CYREG_PRT4_PS_ALIAS EQU 0x40005094 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE -CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE -CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS -CYREG_PRT5_PS_ALIAS EQU 0x40005095 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE -CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE -CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS -CYREG_PRT6_PS_ALIAS EQU 0x40005096 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE -CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE -CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS -CYREG_PRT12_PS_ALIAS EQU 0x4000509c - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE -CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE -CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS -CYREG_PRT15_PS15_ALIAS EQU 0x4000509f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_BASE -CYDEV_IO_PRT_BASE EQU 0x40005100 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_SIZE -CYDEV_IO_PRT_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE -CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE -CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_DR -CYREG_PRT0_DR EQU 0x40005100 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PS -CYREG_PRT0_PS EQU 0x40005101 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_DM0 -CYREG_PRT0_DM0 EQU 0x40005102 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_DM1 -CYREG_PRT0_DM1 EQU 0x40005103 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_DM2 -CYREG_PRT0_DM2 EQU 0x40005104 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_SLW -CYREG_PRT0_SLW EQU 0x40005105 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_BYP -CYREG_PRT0_BYP EQU 0x40005106 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_BIE -CYREG_PRT0_BIE EQU 0x40005107 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_INP_DIS -CYREG_PRT0_INP_DIS EQU 0x40005108 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_CTL -CYREG_PRT0_CTL EQU 0x40005109 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_PRT -CYREG_PRT0_PRT EQU 0x4000510a - ENDIF - IF :LNOT::DEF:CYREG_PRT0_BIT_MASK -CYREG_PRT0_BIT_MASK EQU 0x4000510b - ENDIF - IF :LNOT::DEF:CYREG_PRT0_AMUX -CYREG_PRT0_AMUX EQU 0x4000510c - ENDIF - IF :LNOT::DEF:CYREG_PRT0_AG -CYREG_PRT0_AG EQU 0x4000510d - ENDIF - IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG -CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e - ENDIF - IF :LNOT::DEF:CYREG_PRT0_LCD_EN -CYREG_PRT0_LCD_EN EQU 0x4000510f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE -CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE -CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_DR -CYREG_PRT1_DR EQU 0x40005110 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PS -CYREG_PRT1_PS EQU 0x40005111 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_DM0 -CYREG_PRT1_DM0 EQU 0x40005112 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_DM1 -CYREG_PRT1_DM1 EQU 0x40005113 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_DM2 -CYREG_PRT1_DM2 EQU 0x40005114 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_SLW -CYREG_PRT1_SLW EQU 0x40005115 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_BYP -CYREG_PRT1_BYP EQU 0x40005116 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_BIE -CYREG_PRT1_BIE EQU 0x40005117 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_INP_DIS -CYREG_PRT1_INP_DIS EQU 0x40005118 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_CTL -CYREG_PRT1_CTL EQU 0x40005119 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_PRT -CYREG_PRT1_PRT EQU 0x4000511a - ENDIF - IF :LNOT::DEF:CYREG_PRT1_BIT_MASK -CYREG_PRT1_BIT_MASK EQU 0x4000511b - ENDIF - IF :LNOT::DEF:CYREG_PRT1_AMUX -CYREG_PRT1_AMUX EQU 0x4000511c - ENDIF - IF :LNOT::DEF:CYREG_PRT1_AG -CYREG_PRT1_AG EQU 0x4000511d - ENDIF - IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG -CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e - ENDIF - IF :LNOT::DEF:CYREG_PRT1_LCD_EN -CYREG_PRT1_LCD_EN EQU 0x4000511f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE -CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE -CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_DR -CYREG_PRT2_DR EQU 0x40005120 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PS -CYREG_PRT2_PS EQU 0x40005121 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_DM0 -CYREG_PRT2_DM0 EQU 0x40005122 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_DM1 -CYREG_PRT2_DM1 EQU 0x40005123 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_DM2 -CYREG_PRT2_DM2 EQU 0x40005124 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_SLW -CYREG_PRT2_SLW EQU 0x40005125 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_BYP -CYREG_PRT2_BYP EQU 0x40005126 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_BIE -CYREG_PRT2_BIE EQU 0x40005127 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_INP_DIS -CYREG_PRT2_INP_DIS EQU 0x40005128 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_CTL -CYREG_PRT2_CTL EQU 0x40005129 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_PRT -CYREG_PRT2_PRT EQU 0x4000512a - ENDIF - IF :LNOT::DEF:CYREG_PRT2_BIT_MASK -CYREG_PRT2_BIT_MASK EQU 0x4000512b - ENDIF - IF :LNOT::DEF:CYREG_PRT2_AMUX -CYREG_PRT2_AMUX EQU 0x4000512c - ENDIF - IF :LNOT::DEF:CYREG_PRT2_AG -CYREG_PRT2_AG EQU 0x4000512d - ENDIF - IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG -CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e - ENDIF - IF :LNOT::DEF:CYREG_PRT2_LCD_EN -CYREG_PRT2_LCD_EN EQU 0x4000512f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE -CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE -CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_DR -CYREG_PRT3_DR EQU 0x40005130 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PS -CYREG_PRT3_PS EQU 0x40005131 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_DM0 -CYREG_PRT3_DM0 EQU 0x40005132 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_DM1 -CYREG_PRT3_DM1 EQU 0x40005133 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_DM2 -CYREG_PRT3_DM2 EQU 0x40005134 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_SLW -CYREG_PRT3_SLW EQU 0x40005135 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_BYP -CYREG_PRT3_BYP EQU 0x40005136 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_BIE -CYREG_PRT3_BIE EQU 0x40005137 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_INP_DIS -CYREG_PRT3_INP_DIS EQU 0x40005138 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_CTL -CYREG_PRT3_CTL EQU 0x40005139 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_PRT -CYREG_PRT3_PRT EQU 0x4000513a - ENDIF - IF :LNOT::DEF:CYREG_PRT3_BIT_MASK -CYREG_PRT3_BIT_MASK EQU 0x4000513b - ENDIF - IF :LNOT::DEF:CYREG_PRT3_AMUX -CYREG_PRT3_AMUX EQU 0x4000513c - ENDIF - IF :LNOT::DEF:CYREG_PRT3_AG -CYREG_PRT3_AG EQU 0x4000513d - ENDIF - IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG -CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e - ENDIF - IF :LNOT::DEF:CYREG_PRT3_LCD_EN -CYREG_PRT3_LCD_EN EQU 0x4000513f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE -CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE -CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_DR -CYREG_PRT4_DR EQU 0x40005140 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PS -CYREG_PRT4_PS EQU 0x40005141 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_DM0 -CYREG_PRT4_DM0 EQU 0x40005142 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_DM1 -CYREG_PRT4_DM1 EQU 0x40005143 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_DM2 -CYREG_PRT4_DM2 EQU 0x40005144 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_SLW -CYREG_PRT4_SLW EQU 0x40005145 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_BYP -CYREG_PRT4_BYP EQU 0x40005146 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_BIE -CYREG_PRT4_BIE EQU 0x40005147 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_INP_DIS -CYREG_PRT4_INP_DIS EQU 0x40005148 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_CTL -CYREG_PRT4_CTL EQU 0x40005149 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_PRT -CYREG_PRT4_PRT EQU 0x4000514a - ENDIF - IF :LNOT::DEF:CYREG_PRT4_BIT_MASK -CYREG_PRT4_BIT_MASK EQU 0x4000514b - ENDIF - IF :LNOT::DEF:CYREG_PRT4_AMUX -CYREG_PRT4_AMUX EQU 0x4000514c - ENDIF - IF :LNOT::DEF:CYREG_PRT4_AG -CYREG_PRT4_AG EQU 0x4000514d - ENDIF - IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG -CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e - ENDIF - IF :LNOT::DEF:CYREG_PRT4_LCD_EN -CYREG_PRT4_LCD_EN EQU 0x4000514f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE -CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE -CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_DR -CYREG_PRT5_DR EQU 0x40005150 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PS -CYREG_PRT5_PS EQU 0x40005151 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_DM0 -CYREG_PRT5_DM0 EQU 0x40005152 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_DM1 -CYREG_PRT5_DM1 EQU 0x40005153 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_DM2 -CYREG_PRT5_DM2 EQU 0x40005154 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_SLW -CYREG_PRT5_SLW EQU 0x40005155 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_BYP -CYREG_PRT5_BYP EQU 0x40005156 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_BIE -CYREG_PRT5_BIE EQU 0x40005157 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_INP_DIS -CYREG_PRT5_INP_DIS EQU 0x40005158 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_CTL -CYREG_PRT5_CTL EQU 0x40005159 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_PRT -CYREG_PRT5_PRT EQU 0x4000515a - ENDIF - IF :LNOT::DEF:CYREG_PRT5_BIT_MASK -CYREG_PRT5_BIT_MASK EQU 0x4000515b - ENDIF - IF :LNOT::DEF:CYREG_PRT5_AMUX -CYREG_PRT5_AMUX EQU 0x4000515c - ENDIF - IF :LNOT::DEF:CYREG_PRT5_AG -CYREG_PRT5_AG EQU 0x4000515d - ENDIF - IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG -CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e - ENDIF - IF :LNOT::DEF:CYREG_PRT5_LCD_EN -CYREG_PRT5_LCD_EN EQU 0x4000515f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE -CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE -CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_DR -CYREG_PRT6_DR EQU 0x40005160 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PS -CYREG_PRT6_PS EQU 0x40005161 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_DM0 -CYREG_PRT6_DM0 EQU 0x40005162 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_DM1 -CYREG_PRT6_DM1 EQU 0x40005163 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_DM2 -CYREG_PRT6_DM2 EQU 0x40005164 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_SLW -CYREG_PRT6_SLW EQU 0x40005165 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_BYP -CYREG_PRT6_BYP EQU 0x40005166 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_BIE -CYREG_PRT6_BIE EQU 0x40005167 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_INP_DIS -CYREG_PRT6_INP_DIS EQU 0x40005168 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_CTL -CYREG_PRT6_CTL EQU 0x40005169 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_PRT -CYREG_PRT6_PRT EQU 0x4000516a - ENDIF - IF :LNOT::DEF:CYREG_PRT6_BIT_MASK -CYREG_PRT6_BIT_MASK EQU 0x4000516b - ENDIF - IF :LNOT::DEF:CYREG_PRT6_AMUX -CYREG_PRT6_AMUX EQU 0x4000516c - ENDIF - IF :LNOT::DEF:CYREG_PRT6_AG -CYREG_PRT6_AG EQU 0x4000516d - ENDIF - IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG -CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e - ENDIF - IF :LNOT::DEF:CYREG_PRT6_LCD_EN -CYREG_PRT6_LCD_EN EQU 0x4000516f - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE -CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE -CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_DR -CYREG_PRT12_DR EQU 0x400051c0 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PS -CYREG_PRT12_PS EQU 0x400051c1 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_DM0 -CYREG_PRT12_DM0 EQU 0x400051c2 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_DM1 -CYREG_PRT12_DM1 EQU 0x400051c3 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_DM2 -CYREG_PRT12_DM2 EQU 0x400051c4 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_SLW -CYREG_PRT12_SLW EQU 0x400051c5 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_BYP -CYREG_PRT12_BYP EQU 0x400051c6 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_BIE -CYREG_PRT12_BIE EQU 0x400051c7 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_INP_DIS -CYREG_PRT12_INP_DIS EQU 0x400051c8 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN -CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_PRT -CYREG_PRT12_PRT EQU 0x400051ca - ENDIF - IF :LNOT::DEF:CYREG_PRT12_BIT_MASK -CYREG_PRT12_BIT_MASK EQU 0x400051cb - ENDIF - IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ -CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc - ENDIF - IF :LNOT::DEF:CYREG_PRT12_AG -CYREG_PRT12_AG EQU 0x400051cd - ENDIF - IF :LNOT::DEF:CYREG_PRT12_SIO_CFG -CYREG_PRT12_SIO_CFG EQU 0x400051ce - ENDIF - IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF -CYREG_PRT12_SIO_DIFF EQU 0x400051cf - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE -CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 - ENDIF - IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE -CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_DR -CYREG_PRT15_DR EQU 0x400051f0 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_PS -CYREG_PRT15_PS EQU 0x400051f1 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_DM0 -CYREG_PRT15_DM0 EQU 0x400051f2 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_DM1 -CYREG_PRT15_DM1 EQU 0x400051f3 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_DM2 -CYREG_PRT15_DM2 EQU 0x400051f4 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_SLW -CYREG_PRT15_SLW EQU 0x400051f5 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_BYP -CYREG_PRT15_BYP EQU 0x400051f6 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_BIE -CYREG_PRT15_BIE EQU 0x400051f7 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_INP_DIS -CYREG_PRT15_INP_DIS EQU 0x400051f8 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_CTL -CYREG_PRT15_CTL EQU 0x400051f9 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_PRT -CYREG_PRT15_PRT EQU 0x400051fa - ENDIF - IF :LNOT::DEF:CYREG_PRT15_BIT_MASK -CYREG_PRT15_BIT_MASK EQU 0x400051fb - ENDIF - IF :LNOT::DEF:CYREG_PRT15_AMUX -CYREG_PRT15_AMUX EQU 0x400051fc - ENDIF - IF :LNOT::DEF:CYREG_PRT15_AG -CYREG_PRT15_AG EQU 0x400051fd - ENDIF - IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG -CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe - ENDIF - IF :LNOT::DEF:CYREG_PRT15_LCD_EN -CYREG_PRT15_LCD_EN EQU 0x400051ff - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_BASE -CYDEV_PRTDSI_BASE EQU 0x40005200 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_SIZE -CYDEV_PRTDSI_SIZE EQU 0x0000007f - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE -CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE -CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0 -CYREG_PRT0_OUT_SEL0 EQU 0x40005200 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1 -CYREG_PRT0_OUT_SEL1 EQU 0x40005201 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_OE_SEL0 -CYREG_PRT0_OE_SEL0 EQU 0x40005202 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_OE_SEL1 -CYREG_PRT0_OE_SEL1 EQU 0x40005203 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN -CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT -CYREG_PRT0_SYNC_OUT EQU 0x40005205 - ENDIF - IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL -CYREG_PRT0_CAPS_SEL EQU 0x40005206 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE -CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE -CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0 -CYREG_PRT1_OUT_SEL0 EQU 0x40005208 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1 -CYREG_PRT1_OUT_SEL1 EQU 0x40005209 - ENDIF - IF :LNOT::DEF:CYREG_PRT1_OE_SEL0 -CYREG_PRT1_OE_SEL0 EQU 0x4000520a - ENDIF - IF :LNOT::DEF:CYREG_PRT1_OE_SEL1 -CYREG_PRT1_OE_SEL1 EQU 0x4000520b - ENDIF - IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN -CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c - ENDIF - IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT -CYREG_PRT1_SYNC_OUT EQU 0x4000520d - ENDIF - IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL -CYREG_PRT1_CAPS_SEL EQU 0x4000520e - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE -CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE -CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0 -CYREG_PRT2_OUT_SEL0 EQU 0x40005210 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1 -CYREG_PRT2_OUT_SEL1 EQU 0x40005211 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_OE_SEL0 -CYREG_PRT2_OE_SEL0 EQU 0x40005212 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_OE_SEL1 -CYREG_PRT2_OE_SEL1 EQU 0x40005213 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN -CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT -CYREG_PRT2_SYNC_OUT EQU 0x40005215 - ENDIF - IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL -CYREG_PRT2_CAPS_SEL EQU 0x40005216 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE -CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE -CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0 -CYREG_PRT3_OUT_SEL0 EQU 0x40005218 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1 -CYREG_PRT3_OUT_SEL1 EQU 0x40005219 - ENDIF - IF :LNOT::DEF:CYREG_PRT3_OE_SEL0 -CYREG_PRT3_OE_SEL0 EQU 0x4000521a - ENDIF - IF :LNOT::DEF:CYREG_PRT3_OE_SEL1 -CYREG_PRT3_OE_SEL1 EQU 0x4000521b - ENDIF - IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN -CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c - ENDIF - IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT -CYREG_PRT3_SYNC_OUT EQU 0x4000521d - ENDIF - IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL -CYREG_PRT3_CAPS_SEL EQU 0x4000521e - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE -CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE -CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0 -CYREG_PRT4_OUT_SEL0 EQU 0x40005220 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1 -CYREG_PRT4_OUT_SEL1 EQU 0x40005221 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_OE_SEL0 -CYREG_PRT4_OE_SEL0 EQU 0x40005222 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_OE_SEL1 -CYREG_PRT4_OE_SEL1 EQU 0x40005223 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN -CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT -CYREG_PRT4_SYNC_OUT EQU 0x40005225 - ENDIF - IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL -CYREG_PRT4_CAPS_SEL EQU 0x40005226 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE -CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE -CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0 -CYREG_PRT5_OUT_SEL0 EQU 0x40005228 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1 -CYREG_PRT5_OUT_SEL1 EQU 0x40005229 - ENDIF - IF :LNOT::DEF:CYREG_PRT5_OE_SEL0 -CYREG_PRT5_OE_SEL0 EQU 0x4000522a - ENDIF - IF :LNOT::DEF:CYREG_PRT5_OE_SEL1 -CYREG_PRT5_OE_SEL1 EQU 0x4000522b - ENDIF - IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN -CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c - ENDIF - IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT -CYREG_PRT5_SYNC_OUT EQU 0x4000522d - ENDIF - IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL -CYREG_PRT5_CAPS_SEL EQU 0x4000522e - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE -CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE -CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0 -CYREG_PRT6_OUT_SEL0 EQU 0x40005230 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1 -CYREG_PRT6_OUT_SEL1 EQU 0x40005231 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_OE_SEL0 -CYREG_PRT6_OE_SEL0 EQU 0x40005232 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_OE_SEL1 -CYREG_PRT6_OE_SEL1 EQU 0x40005233 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN -CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT -CYREG_PRT6_SYNC_OUT EQU 0x40005235 - ENDIF - IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL -CYREG_PRT6_CAPS_SEL EQU 0x40005236 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE -CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE -CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0 -CYREG_PRT12_OUT_SEL0 EQU 0x40005260 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1 -CYREG_PRT12_OUT_SEL1 EQU 0x40005261 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_OE_SEL0 -CYREG_PRT12_OE_SEL0 EQU 0x40005262 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_OE_SEL1 -CYREG_PRT12_OE_SEL1 EQU 0x40005263 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN -CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264 - ENDIF - IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT -CYREG_PRT12_SYNC_OUT EQU 0x40005265 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE -CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 - ENDIF - IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE -CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0 -CYREG_PRT15_OUT_SEL0 EQU 0x40005278 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1 -CYREG_PRT15_OUT_SEL1 EQU 0x40005279 - ENDIF - IF :LNOT::DEF:CYREG_PRT15_OE_SEL0 -CYREG_PRT15_OE_SEL0 EQU 0x4000527a - ENDIF - IF :LNOT::DEF:CYREG_PRT15_OE_SEL1 -CYREG_PRT15_OE_SEL1 EQU 0x4000527b - ENDIF - IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN -CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c - ENDIF - IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT -CYREG_PRT15_SYNC_OUT EQU 0x4000527d - ENDIF - IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL -CYREG_PRT15_CAPS_SEL EQU 0x4000527e - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_BASE -CYDEV_EMIF_BASE EQU 0x40005400 - ENDIF - IF :LNOT::DEF:CYDEV_EMIF_SIZE -CYDEV_EMIF_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_EMIF_NO_UDB -CYREG_EMIF_NO_UDB EQU 0x40005400 - ENDIF - IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES -CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401 - ENDIF - IF :LNOT::DEF:CYREG_EMIF_MEM_DWN -CYREG_EMIF_MEM_DWN EQU 0x40005402 - ENDIF - IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV -CYREG_EMIF_MEMCLK_DIV EQU 0x40005403 - ENDIF - IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN -CYREG_EMIF_CLOCK_EN EQU 0x40005404 - ENDIF - IF :LNOT::DEF:CYREG_EMIF_EM_TYPE -CYREG_EMIF_EM_TYPE EQU 0x40005405 - ENDIF - IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES -CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_BASE -CYDEV_ANAIF_BASE EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_SIZE -CYDEV_ANAIF_SIZE EQU 0x000003a9 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE -CYDEV_ANAIF_CFG_BASE EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE -CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE -CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE -CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_SC0_CR0 -CYREG_SC0_CR0 EQU 0x40005800 - ENDIF - IF :LNOT::DEF:CYREG_SC0_CR1 -CYREG_SC0_CR1 EQU 0x40005801 - ENDIF - IF :LNOT::DEF:CYREG_SC0_CR2 -CYREG_SC0_CR2 EQU 0x40005802 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE -CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE -CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_SC1_CR0 -CYREG_SC1_CR0 EQU 0x40005804 - ENDIF - IF :LNOT::DEF:CYREG_SC1_CR1 -CYREG_SC1_CR1 EQU 0x40005805 - ENDIF - IF :LNOT::DEF:CYREG_SC1_CR2 -CYREG_SC1_CR2 EQU 0x40005806 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE -CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE -CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_SC2_CR0 -CYREG_SC2_CR0 EQU 0x40005808 - ENDIF - IF :LNOT::DEF:CYREG_SC2_CR1 -CYREG_SC2_CR1 EQU 0x40005809 - ENDIF - IF :LNOT::DEF:CYREG_SC2_CR2 -CYREG_SC2_CR2 EQU 0x4000580a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE -CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE -CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_SC3_CR0 -CYREG_SC3_CR0 EQU 0x4000580c - ENDIF - IF :LNOT::DEF:CYREG_SC3_CR1 -CYREG_SC3_CR1 EQU 0x4000580d - ENDIF - IF :LNOT::DEF:CYREG_SC3_CR2 -CYREG_SC3_CR2 EQU 0x4000580e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE -CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE -CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_CR0 -CYREG_DAC0_CR0 EQU 0x40005820 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_CR1 -CYREG_DAC0_CR1 EQU 0x40005821 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_TST -CYREG_DAC0_TST EQU 0x40005822 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE -CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE -CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_DAC1_CR0 -CYREG_DAC1_CR0 EQU 0x40005824 - ENDIF - IF :LNOT::DEF:CYREG_DAC1_CR1 -CYREG_DAC1_CR1 EQU 0x40005825 - ENDIF - IF :LNOT::DEF:CYREG_DAC1_TST -CYREG_DAC1_TST EQU 0x40005826 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE -CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE -CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_CR0 -CYREG_DAC2_CR0 EQU 0x40005828 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_CR1 -CYREG_DAC2_CR1 EQU 0x40005829 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_TST -CYREG_DAC2_TST EQU 0x4000582a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE -CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE -CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_DAC3_CR0 -CYREG_DAC3_CR0 EQU 0x4000582c - ENDIF - IF :LNOT::DEF:CYREG_DAC3_CR1 -CYREG_DAC3_CR1 EQU 0x4000582d - ENDIF - IF :LNOT::DEF:CYREG_DAC3_TST -CYREG_DAC3_TST EQU 0x4000582e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE -CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE -CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_CR -CYREG_CMP0_CR EQU 0x40005840 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE -CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE -CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_CMP1_CR -CYREG_CMP1_CR EQU 0x40005841 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE -CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE -CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_CR -CYREG_CMP2_CR EQU 0x40005842 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE -CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE -CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_CMP3_CR -CYREG_CMP3_CR EQU 0x40005843 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE -CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE -CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_LUT0_CR -CYREG_LUT0_CR EQU 0x40005848 - ENDIF - IF :LNOT::DEF:CYREG_LUT0_MX -CYREG_LUT0_MX EQU 0x40005849 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE -CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE -CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_LUT1_CR -CYREG_LUT1_CR EQU 0x4000584a - ENDIF - IF :LNOT::DEF:CYREG_LUT1_MX -CYREG_LUT1_MX EQU 0x4000584b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE -CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE -CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_LUT2_CR -CYREG_LUT2_CR EQU 0x4000584c - ENDIF - IF :LNOT::DEF:CYREG_LUT2_MX -CYREG_LUT2_MX EQU 0x4000584d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE -CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE -CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_LUT3_CR -CYREG_LUT3_CR EQU 0x4000584e - ENDIF - IF :LNOT::DEF:CYREG_LUT3_MX -CYREG_LUT3_MX EQU 0x4000584f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE -CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE -CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP0_CR -CYREG_OPAMP0_CR EQU 0x40005858 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP0_RSVD -CYREG_OPAMP0_RSVD EQU 0x40005859 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE -CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE -CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP1_CR -CYREG_OPAMP1_CR EQU 0x4000585a - ENDIF - IF :LNOT::DEF:CYREG_OPAMP1_RSVD -CYREG_OPAMP1_RSVD EQU 0x4000585b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE -CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE -CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP2_CR -CYREG_OPAMP2_CR EQU 0x4000585c - ENDIF - IF :LNOT::DEF:CYREG_OPAMP2_RSVD -CYREG_OPAMP2_RSVD EQU 0x4000585d - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE -CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE -CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP3_CR -CYREG_OPAMP3_CR EQU 0x4000585e - ENDIF - IF :LNOT::DEF:CYREG_OPAMP3_RSVD -CYREG_OPAMP3_RSVD EQU 0x4000585f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE -CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE -CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_LCDDAC_CR0 -CYREG_LCDDAC_CR0 EQU 0x40005868 - ENDIF - IF :LNOT::DEF:CYREG_LCDDAC_CR1 -CYREG_LCDDAC_CR1 EQU 0x40005869 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE -CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE -CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_LCDDRV_CR -CYREG_LCDDRV_CR EQU 0x4000586a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE -CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE -CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_LCDTMR_CFG -CYREG_LCDTMR_CFG EQU 0x4000586b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE -CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE -CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYREG_BG_CR0 -CYREG_BG_CR0 EQU 0x4000586c - ENDIF - IF :LNOT::DEF:CYREG_BG_RSVD -CYREG_BG_RSVD EQU 0x4000586d - ENDIF - IF :LNOT::DEF:CYREG_BG_DFT0 -CYREG_BG_DFT0 EQU 0x4000586e - ENDIF - IF :LNOT::DEF:CYREG_BG_DFT1 -CYREG_BG_DFT1 EQU 0x4000586f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE -CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE -CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CAPSL_CFG0 -CYREG_CAPSL_CFG0 EQU 0x40005870 - ENDIF - IF :LNOT::DEF:CYREG_CAPSL_CFG1 -CYREG_CAPSL_CFG1 EQU 0x40005871 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE -CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE -CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CAPSR_CFG0 -CYREG_CAPSR_CFG0 EQU 0x40005872 - ENDIF - IF :LNOT::DEF:CYREG_CAPSR_CFG1 -CYREG_CAPSR_CFG1 EQU 0x40005873 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE -CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE -CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_PUMP_CR0 -CYREG_PUMP_CR0 EQU 0x40005876 - ENDIF - IF :LNOT::DEF:CYREG_PUMP_CR1 -CYREG_PUMP_CR1 EQU 0x40005877 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE -CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE -CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_LPF0_CR0 -CYREG_LPF0_CR0 EQU 0x40005878 - ENDIF - IF :LNOT::DEF:CYREG_LPF0_RSVD -CYREG_LPF0_RSVD EQU 0x40005879 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE -CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE -CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_LPF1_CR0 -CYREG_LPF1_CR0 EQU 0x4000587a - ENDIF - IF :LNOT::DEF:CYREG_LPF1_RSVD -CYREG_LPF1_RSVD EQU 0x4000587b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE -CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE -CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0 -CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE -CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE -CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR0 -CYREG_DSM0_CR0 EQU 0x40005880 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR1 -CYREG_DSM0_CR1 EQU 0x40005881 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR2 -CYREG_DSM0_CR2 EQU 0x40005882 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR3 -CYREG_DSM0_CR3 EQU 0x40005883 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR4 -CYREG_DSM0_CR4 EQU 0x40005884 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR5 -CYREG_DSM0_CR5 EQU 0x40005885 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR6 -CYREG_DSM0_CR6 EQU 0x40005886 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR7 -CYREG_DSM0_CR7 EQU 0x40005887 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR8 -CYREG_DSM0_CR8 EQU 0x40005888 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR9 -CYREG_DSM0_CR9 EQU 0x40005889 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR10 -CYREG_DSM0_CR10 EQU 0x4000588a - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR11 -CYREG_DSM0_CR11 EQU 0x4000588b - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR12 -CYREG_DSM0_CR12 EQU 0x4000588c - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR13 -CYREG_DSM0_CR13 EQU 0x4000588d - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR14 -CYREG_DSM0_CR14 EQU 0x4000588e - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR15 -CYREG_DSM0_CR15 EQU 0x4000588f - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR16 -CYREG_DSM0_CR16 EQU 0x40005890 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CR17 -CYREG_DSM0_CR17 EQU 0x40005891 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_REF0 -CYREG_DSM0_REF0 EQU 0x40005892 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_REF1 -CYREG_DSM0_REF1 EQU 0x40005893 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_REF2 -CYREG_DSM0_REF2 EQU 0x40005894 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_REF3 -CYREG_DSM0_REF3 EQU 0x40005895 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_DEM0 -CYREG_DSM0_DEM0 EQU 0x40005896 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_DEM1 -CYREG_DSM0_DEM1 EQU 0x40005897 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_TST0 -CYREG_DSM0_TST0 EQU 0x40005898 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_TST1 -CYREG_DSM0_TST1 EQU 0x40005899 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_BUF0 -CYREG_DSM0_BUF0 EQU 0x4000589a - ENDIF - IF :LNOT::DEF:CYREG_DSM0_BUF1 -CYREG_DSM0_BUF1 EQU 0x4000589b - ENDIF - IF :LNOT::DEF:CYREG_DSM0_BUF2 -CYREG_DSM0_BUF2 EQU 0x4000589c - ENDIF - IF :LNOT::DEF:CYREG_DSM0_BUF3 -CYREG_DSM0_BUF3 EQU 0x4000589d - ENDIF - IF :LNOT::DEF:CYREG_DSM0_MISC -CYREG_DSM0_MISC EQU 0x4000589e - ENDIF - IF :LNOT::DEF:CYREG_DSM0_RSVD1 -CYREG_DSM0_RSVD1 EQU 0x4000589f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE -CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE -CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CSR0 -CYREG_SAR0_CSR0 EQU 0x40005900 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CSR1 -CYREG_SAR0_CSR1 EQU 0x40005901 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CSR2 -CYREG_SAR0_CSR2 EQU 0x40005902 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CSR3 -CYREG_SAR0_CSR3 EQU 0x40005903 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CSR4 -CYREG_SAR0_CSR4 EQU 0x40005904 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CSR5 -CYREG_SAR0_CSR5 EQU 0x40005905 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CSR6 -CYREG_SAR0_CSR6 EQU 0x40005906 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE -CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE -CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CSR0 -CYREG_SAR1_CSR0 EQU 0x40005908 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CSR1 -CYREG_SAR1_CSR1 EQU 0x40005909 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CSR2 -CYREG_SAR1_CSR2 EQU 0x4000590a - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CSR3 -CYREG_SAR1_CSR3 EQU 0x4000590b - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CSR4 -CYREG_SAR1_CSR4 EQU 0x4000590c - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CSR5 -CYREG_SAR1_CSR5 EQU 0x4000590d - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CSR6 -CYREG_SAR1_CSR6 EQU 0x4000590e - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE -CYDEV_ANAIF_RT_BASE EQU 0x40005a00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE -CYDEV_ANAIF_RT_SIZE EQU 0x00000162 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE -CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE -CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW0 -CYREG_SC0_SW0 EQU 0x40005a00 - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW2 -CYREG_SC0_SW2 EQU 0x40005a02 - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW3 -CYREG_SC0_SW3 EQU 0x40005a03 - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW4 -CYREG_SC0_SW4 EQU 0x40005a04 - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW6 -CYREG_SC0_SW6 EQU 0x40005a06 - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW7 -CYREG_SC0_SW7 EQU 0x40005a07 - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW8 -CYREG_SC0_SW8 EQU 0x40005a08 - ENDIF - IF :LNOT::DEF:CYREG_SC0_SW10 -CYREG_SC0_SW10 EQU 0x40005a0a - ENDIF - IF :LNOT::DEF:CYREG_SC0_CLK -CYREG_SC0_CLK EQU 0x40005a0b - ENDIF - IF :LNOT::DEF:CYREG_SC0_BST -CYREG_SC0_BST EQU 0x40005a0c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE -CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE -CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW0 -CYREG_SC1_SW0 EQU 0x40005a10 - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW2 -CYREG_SC1_SW2 EQU 0x40005a12 - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW3 -CYREG_SC1_SW3 EQU 0x40005a13 - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW4 -CYREG_SC1_SW4 EQU 0x40005a14 - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW6 -CYREG_SC1_SW6 EQU 0x40005a16 - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW7 -CYREG_SC1_SW7 EQU 0x40005a17 - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW8 -CYREG_SC1_SW8 EQU 0x40005a18 - ENDIF - IF :LNOT::DEF:CYREG_SC1_SW10 -CYREG_SC1_SW10 EQU 0x40005a1a - ENDIF - IF :LNOT::DEF:CYREG_SC1_CLK -CYREG_SC1_CLK EQU 0x40005a1b - ENDIF - IF :LNOT::DEF:CYREG_SC1_BST -CYREG_SC1_BST EQU 0x40005a1c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE -CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE -CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW0 -CYREG_SC2_SW0 EQU 0x40005a20 - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW2 -CYREG_SC2_SW2 EQU 0x40005a22 - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW3 -CYREG_SC2_SW3 EQU 0x40005a23 - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW4 -CYREG_SC2_SW4 EQU 0x40005a24 - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW6 -CYREG_SC2_SW6 EQU 0x40005a26 - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW7 -CYREG_SC2_SW7 EQU 0x40005a27 - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW8 -CYREG_SC2_SW8 EQU 0x40005a28 - ENDIF - IF :LNOT::DEF:CYREG_SC2_SW10 -CYREG_SC2_SW10 EQU 0x40005a2a - ENDIF - IF :LNOT::DEF:CYREG_SC2_CLK -CYREG_SC2_CLK EQU 0x40005a2b - ENDIF - IF :LNOT::DEF:CYREG_SC2_BST -CYREG_SC2_BST EQU 0x40005a2c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE -CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE -CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW0 -CYREG_SC3_SW0 EQU 0x40005a30 - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW2 -CYREG_SC3_SW2 EQU 0x40005a32 - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW3 -CYREG_SC3_SW3 EQU 0x40005a33 - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW4 -CYREG_SC3_SW4 EQU 0x40005a34 - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW6 -CYREG_SC3_SW6 EQU 0x40005a36 - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW7 -CYREG_SC3_SW7 EQU 0x40005a37 - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW8 -CYREG_SC3_SW8 EQU 0x40005a38 - ENDIF - IF :LNOT::DEF:CYREG_SC3_SW10 -CYREG_SC3_SW10 EQU 0x40005a3a - ENDIF - IF :LNOT::DEF:CYREG_SC3_CLK -CYREG_SC3_CLK EQU 0x40005a3b - ENDIF - IF :LNOT::DEF:CYREG_SC3_BST -CYREG_SC3_BST EQU 0x40005a3c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE -CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE -CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_SW0 -CYREG_DAC0_SW0 EQU 0x40005a80 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_SW2 -CYREG_DAC0_SW2 EQU 0x40005a82 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_SW3 -CYREG_DAC0_SW3 EQU 0x40005a83 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_SW4 -CYREG_DAC0_SW4 EQU 0x40005a84 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_STROBE -CYREG_DAC0_STROBE EQU 0x40005a87 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE -CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE -CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_DAC1_SW0 -CYREG_DAC1_SW0 EQU 0x40005a88 - ENDIF - IF :LNOT::DEF:CYREG_DAC1_SW2 -CYREG_DAC1_SW2 EQU 0x40005a8a - ENDIF - IF :LNOT::DEF:CYREG_DAC1_SW3 -CYREG_DAC1_SW3 EQU 0x40005a8b - ENDIF - IF :LNOT::DEF:CYREG_DAC1_SW4 -CYREG_DAC1_SW4 EQU 0x40005a8c - ENDIF - IF :LNOT::DEF:CYREG_DAC1_STROBE -CYREG_DAC1_STROBE EQU 0x40005a8f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE -CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE -CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_SW0 -CYREG_DAC2_SW0 EQU 0x40005a90 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_SW2 -CYREG_DAC2_SW2 EQU 0x40005a92 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_SW3 -CYREG_DAC2_SW3 EQU 0x40005a93 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_SW4 -CYREG_DAC2_SW4 EQU 0x40005a94 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_STROBE -CYREG_DAC2_STROBE EQU 0x40005a97 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE -CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE -CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_DAC3_SW0 -CYREG_DAC3_SW0 EQU 0x40005a98 - ENDIF - IF :LNOT::DEF:CYREG_DAC3_SW2 -CYREG_DAC3_SW2 EQU 0x40005a9a - ENDIF - IF :LNOT::DEF:CYREG_DAC3_SW3 -CYREG_DAC3_SW3 EQU 0x40005a9b - ENDIF - IF :LNOT::DEF:CYREG_DAC3_SW4 -CYREG_DAC3_SW4 EQU 0x40005a9c - ENDIF - IF :LNOT::DEF:CYREG_DAC3_STROBE -CYREG_DAC3_STROBE EQU 0x40005a9f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE -CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE -CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_SW0 -CYREG_CMP0_SW0 EQU 0x40005ac0 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_SW2 -CYREG_CMP0_SW2 EQU 0x40005ac2 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_SW3 -CYREG_CMP0_SW3 EQU 0x40005ac3 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_SW4 -CYREG_CMP0_SW4 EQU 0x40005ac4 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_SW6 -CYREG_CMP0_SW6 EQU 0x40005ac6 - ENDIF - IF :LNOT::DEF:CYREG_CMP0_CLK -CYREG_CMP0_CLK EQU 0x40005ac7 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE -CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE -CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_CMP1_SW0 -CYREG_CMP1_SW0 EQU 0x40005ac8 - ENDIF - IF :LNOT::DEF:CYREG_CMP1_SW2 -CYREG_CMP1_SW2 EQU 0x40005aca - ENDIF - IF :LNOT::DEF:CYREG_CMP1_SW3 -CYREG_CMP1_SW3 EQU 0x40005acb - ENDIF - IF :LNOT::DEF:CYREG_CMP1_SW4 -CYREG_CMP1_SW4 EQU 0x40005acc - ENDIF - IF :LNOT::DEF:CYREG_CMP1_SW6 -CYREG_CMP1_SW6 EQU 0x40005ace - ENDIF - IF :LNOT::DEF:CYREG_CMP1_CLK -CYREG_CMP1_CLK EQU 0x40005acf - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE -CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE -CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_SW0 -CYREG_CMP2_SW0 EQU 0x40005ad0 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_SW2 -CYREG_CMP2_SW2 EQU 0x40005ad2 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_SW3 -CYREG_CMP2_SW3 EQU 0x40005ad3 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_SW4 -CYREG_CMP2_SW4 EQU 0x40005ad4 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_SW6 -CYREG_CMP2_SW6 EQU 0x40005ad6 - ENDIF - IF :LNOT::DEF:CYREG_CMP2_CLK -CYREG_CMP2_CLK EQU 0x40005ad7 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE -CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE -CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_CMP3_SW0 -CYREG_CMP3_SW0 EQU 0x40005ad8 - ENDIF - IF :LNOT::DEF:CYREG_CMP3_SW2 -CYREG_CMP3_SW2 EQU 0x40005ada - ENDIF - IF :LNOT::DEF:CYREG_CMP3_SW3 -CYREG_CMP3_SW3 EQU 0x40005adb - ENDIF - IF :LNOT::DEF:CYREG_CMP3_SW4 -CYREG_CMP3_SW4 EQU 0x40005adc - ENDIF - IF :LNOT::DEF:CYREG_CMP3_SW6 -CYREG_CMP3_SW6 EQU 0x40005ade - ENDIF - IF :LNOT::DEF:CYREG_CMP3_CLK -CYREG_CMP3_CLK EQU 0x40005adf - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE -CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE -CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_SW0 -CYREG_DSM0_SW0 EQU 0x40005b00 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_SW2 -CYREG_DSM0_SW2 EQU 0x40005b02 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_SW3 -CYREG_DSM0_SW3 EQU 0x40005b03 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_SW4 -CYREG_DSM0_SW4 EQU 0x40005b04 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_SW6 -CYREG_DSM0_SW6 EQU 0x40005b06 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_CLK -CYREG_DSM0_CLK EQU 0x40005b07 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE -CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE -CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_SW0 -CYREG_SAR0_SW0 EQU 0x40005b20 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_SW2 -CYREG_SAR0_SW2 EQU 0x40005b22 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_SW3 -CYREG_SAR0_SW3 EQU 0x40005b23 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_SW4 -CYREG_SAR0_SW4 EQU 0x40005b24 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_SW6 -CYREG_SAR0_SW6 EQU 0x40005b26 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_CLK -CYREG_SAR0_CLK EQU 0x40005b27 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE -CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE -CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_SW0 -CYREG_SAR1_SW0 EQU 0x40005b28 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_SW2 -CYREG_SAR1_SW2 EQU 0x40005b2a - ENDIF - IF :LNOT::DEF:CYREG_SAR1_SW3 -CYREG_SAR1_SW3 EQU 0x40005b2b - ENDIF - IF :LNOT::DEF:CYREG_SAR1_SW4 -CYREG_SAR1_SW4 EQU 0x40005b2c - ENDIF - IF :LNOT::DEF:CYREG_SAR1_SW6 -CYREG_SAR1_SW6 EQU 0x40005b2e - ENDIF - IF :LNOT::DEF:CYREG_SAR1_CLK -CYREG_SAR1_CLK EQU 0x40005b2f - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE -CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE -CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP0_MX -CYREG_OPAMP0_MX EQU 0x40005b40 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP0_SW -CYREG_OPAMP0_SW EQU 0x40005b41 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE -CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE -CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP1_MX -CYREG_OPAMP1_MX EQU 0x40005b42 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP1_SW -CYREG_OPAMP1_SW EQU 0x40005b43 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE -CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE -CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP2_MX -CYREG_OPAMP2_MX EQU 0x40005b44 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP2_SW -CYREG_OPAMP2_SW EQU 0x40005b45 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE -CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE -CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP3_MX -CYREG_OPAMP3_MX EQU 0x40005b46 - ENDIF - IF :LNOT::DEF:CYREG_OPAMP3_SW -CYREG_OPAMP3_SW EQU 0x40005b47 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE -CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE -CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_LCDDAC_SW0 -CYREG_LCDDAC_SW0 EQU 0x40005b50 - ENDIF - IF :LNOT::DEF:CYREG_LCDDAC_SW1 -CYREG_LCDDAC_SW1 EQU 0x40005b51 - ENDIF - IF :LNOT::DEF:CYREG_LCDDAC_SW2 -CYREG_LCDDAC_SW2 EQU 0x40005b52 - ENDIF - IF :LNOT::DEF:CYREG_LCDDAC_SW3 -CYREG_LCDDAC_SW3 EQU 0x40005b53 - ENDIF - IF :LNOT::DEF:CYREG_LCDDAC_SW4 -CYREG_LCDDAC_SW4 EQU 0x40005b54 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE -CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE -CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_SC_MISC -CYREG_SC_MISC EQU 0x40005b56 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE -CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE -CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYREG_BUS_SW0 -CYREG_BUS_SW0 EQU 0x40005b58 - ENDIF - IF :LNOT::DEF:CYREG_BUS_SW2 -CYREG_BUS_SW2 EQU 0x40005b5a - ENDIF - IF :LNOT::DEF:CYREG_BUS_SW3 -CYREG_BUS_SW3 EQU 0x40005b5b - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE -CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE -CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 - ENDIF - IF :LNOT::DEF:CYREG_DFT_CR0 -CYREG_DFT_CR0 EQU 0x40005b5c - ENDIF - IF :LNOT::DEF:CYREG_DFT_CR1 -CYREG_DFT_CR1 EQU 0x40005b5d - ENDIF - IF :LNOT::DEF:CYREG_DFT_CR2 -CYREG_DFT_CR2 EQU 0x40005b5e - ENDIF - IF :LNOT::DEF:CYREG_DFT_CR3 -CYREG_DFT_CR3 EQU 0x40005b5f - ENDIF - IF :LNOT::DEF:CYREG_DFT_CR4 -CYREG_DFT_CR4 EQU 0x40005b60 - ENDIF - IF :LNOT::DEF:CYREG_DFT_CR5 -CYREG_DFT_CR5 EQU 0x40005b61 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE -CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE -CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE -CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE -CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC0_D -CYREG_DAC0_D EQU 0x40005b80 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE -CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE -CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC1_D -CYREG_DAC1_D EQU 0x40005b81 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE -CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE -CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC2_D -CYREG_DAC2_D EQU 0x40005b82 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE -CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE -CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_DAC3_D -CYREG_DAC3_D EQU 0x40005b83 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE -CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE -CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_OUT0 -CYREG_DSM0_OUT0 EQU 0x40005b88 - ENDIF - IF :LNOT::DEF:CYREG_DSM0_OUT1 -CYREG_DSM0_OUT1 EQU 0x40005b89 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE -CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE -CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_LUT_SR -CYREG_LUT_SR EQU 0x40005b90 - ENDIF - IF :LNOT::DEF:CYREG_LUT_WRK1 -CYREG_LUT_WRK1 EQU 0x40005b91 - ENDIF - IF :LNOT::DEF:CYREG_LUT_MSK -CYREG_LUT_MSK EQU 0x40005b92 - ENDIF - IF :LNOT::DEF:CYREG_LUT_CLK -CYREG_LUT_CLK EQU 0x40005b93 - ENDIF - IF :LNOT::DEF:CYREG_LUT_CPTR -CYREG_LUT_CPTR EQU 0x40005b94 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE -CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE -CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_CMP_WRK -CYREG_CMP_WRK EQU 0x40005b96 - ENDIF - IF :LNOT::DEF:CYREG_CMP_TST -CYREG_CMP_TST EQU 0x40005b97 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE -CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE -CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_SC_SR -CYREG_SC_SR EQU 0x40005b98 - ENDIF - IF :LNOT::DEF:CYREG_SC_WRK1 -CYREG_SC_WRK1 EQU 0x40005b99 - ENDIF - IF :LNOT::DEF:CYREG_SC_MSK -CYREG_SC_MSK EQU 0x40005b9a - ENDIF - IF :LNOT::DEF:CYREG_SC_CMPINV -CYREG_SC_CMPINV EQU 0x40005b9b - ENDIF - IF :LNOT::DEF:CYREG_SC_CPTR -CYREG_SC_CPTR EQU 0x40005b9c - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE -CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE -CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_WRK0 -CYREG_SAR0_WRK0 EQU 0x40005ba0 - ENDIF - IF :LNOT::DEF:CYREG_SAR0_WRK1 -CYREG_SAR0_WRK1 EQU 0x40005ba1 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE -CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE -CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_WRK0 -CYREG_SAR1_WRK0 EQU 0x40005ba2 - ENDIF - IF :LNOT::DEF:CYREG_SAR1_WRK1 -CYREG_SAR1_WRK1 EQU 0x40005ba3 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE -CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 - ENDIF - IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE -CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF -CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_BASE -CYDEV_USB_BASE EQU 0x40006000 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIZE -CYDEV_USB_SIZE EQU 0x00000300 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR0 -CYREG_USB_EP0_DR0 EQU 0x40006000 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR1 -CYREG_USB_EP0_DR1 EQU 0x40006001 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR2 -CYREG_USB_EP0_DR2 EQU 0x40006002 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR3 -CYREG_USB_EP0_DR3 EQU 0x40006003 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR4 -CYREG_USB_EP0_DR4 EQU 0x40006004 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR5 -CYREG_USB_EP0_DR5 EQU 0x40006005 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR6 -CYREG_USB_EP0_DR6 EQU 0x40006006 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_DR7 -CYREG_USB_EP0_DR7 EQU 0x40006007 - ENDIF - IF :LNOT::DEF:CYREG_USB_CR0 -CYREG_USB_CR0 EQU 0x40006008 - ENDIF - IF :LNOT::DEF:CYREG_USB_CR1 -CYREG_USB_CR1 EQU 0x40006009 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN -CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR -CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE -CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE -CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0 -CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1 -CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0 -CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e - ENDIF - IF :LNOT::DEF:CYREG_USB_USBIO_CR0 -CYREG_USB_USBIO_CR0 EQU 0x40006010 - ENDIF - IF :LNOT::DEF:CYREG_USB_USBIO_CR1 -CYREG_USB_USBIO_CR1 EQU 0x40006012 - ENDIF - IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG -CYREG_USB_DYN_RECONFIG EQU 0x40006014 - ENDIF - IF :LNOT::DEF:CYREG_USB_SOF0 -CYREG_USB_SOF0 EQU 0x40006018 - ENDIF - IF :LNOT::DEF:CYREG_USB_SOF1 -CYREG_USB_SOF1 EQU 0x40006019 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE -CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE -CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0 -CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1 -CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0 -CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_CR -CYREG_USB_EP0_CR EQU 0x40006028 - ENDIF - IF :LNOT::DEF:CYREG_USB_EP0_CNT -CYREG_USB_EP0_CNT EQU 0x40006029 - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE -CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE -CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0 -CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1 -CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0 -CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE -CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE -CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0 -CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1 -CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0 -CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE -CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE -CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0 -CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1 -CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0 -CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE -CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE -CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0 -CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1 -CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0 -CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE -CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE -CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0 -CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1 -CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0 -CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE -CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c - ENDIF - IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE -CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0 -CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1 -CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d - ENDIF - IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0 -CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE -CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE -CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG -CYREG_USB_ARB_EP1_CFG EQU 0x40006080 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN -CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR -CYREG_USB_ARB_EP1_SR EQU 0x40006082 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE -CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE -CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA -CYREG_USB_ARB_RW1_WA EQU 0x40006084 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB -CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA -CYREG_USB_ARB_RW1_RA EQU 0x40006086 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB -CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR -CYREG_USB_ARB_RW1_DR EQU 0x40006088 - ENDIF - IF :LNOT::DEF:CYREG_USB_BUF_SIZE -CYREG_USB_BUF_SIZE EQU 0x4000608c - ENDIF - IF :LNOT::DEF:CYREG_USB_EP_ACTIVE -CYREG_USB_EP_ACTIVE EQU 0x4000608e - ENDIF - IF :LNOT::DEF:CYREG_USB_EP_TYPE -CYREG_USB_EP_TYPE EQU 0x4000608f - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE -CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE -CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG -CYREG_USB_ARB_EP2_CFG EQU 0x40006090 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN -CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR -CYREG_USB_ARB_EP2_SR EQU 0x40006092 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE -CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE -CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA -CYREG_USB_ARB_RW2_WA EQU 0x40006094 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB -CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA -CYREG_USB_ARB_RW2_RA EQU 0x40006096 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB -CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR -CYREG_USB_ARB_RW2_DR EQU 0x40006098 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_CFG -CYREG_USB_ARB_CFG EQU 0x4000609c - ENDIF - IF :LNOT::DEF:CYREG_USB_USB_CLK_EN -CYREG_USB_USB_CLK_EN EQU 0x4000609d - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_INT_EN -CYREG_USB_ARB_INT_EN EQU 0x4000609e - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_INT_SR -CYREG_USB_ARB_INT_SR EQU 0x4000609f - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE -CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE -CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG -CYREG_USB_ARB_EP3_CFG EQU 0x400060a0 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN -CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR -CYREG_USB_ARB_EP3_SR EQU 0x400060a2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE -CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE -CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA -CYREG_USB_ARB_RW3_WA EQU 0x400060a4 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB -CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA -CYREG_USB_ARB_RW3_RA EQU 0x400060a6 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB -CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR -CYREG_USB_ARB_RW3_DR EQU 0x400060a8 - ENDIF - IF :LNOT::DEF:CYREG_USB_CWA -CYREG_USB_CWA EQU 0x400060ac - ENDIF - IF :LNOT::DEF:CYREG_USB_CWA_MSB -CYREG_USB_CWA_MSB EQU 0x400060ad - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE -CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE -CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG -CYREG_USB_ARB_EP4_CFG EQU 0x400060b0 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN -CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR -CYREG_USB_ARB_EP4_SR EQU 0x400060b2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE -CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE -CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA -CYREG_USB_ARB_RW4_WA EQU 0x400060b4 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB -CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA -CYREG_USB_ARB_RW4_RA EQU 0x400060b6 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB -CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR -CYREG_USB_ARB_RW4_DR EQU 0x400060b8 - ENDIF - IF :LNOT::DEF:CYREG_USB_DMA_THRES -CYREG_USB_DMA_THRES EQU 0x400060bc - ENDIF - IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB -CYREG_USB_DMA_THRES_MSB EQU 0x400060bd - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE -CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE -CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG -CYREG_USB_ARB_EP5_CFG EQU 0x400060c0 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN -CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR -CYREG_USB_ARB_EP5_SR EQU 0x400060c2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE -CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE -CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA -CYREG_USB_ARB_RW5_WA EQU 0x400060c4 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB -CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA -CYREG_USB_ARB_RW5_RA EQU 0x400060c6 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB -CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR -CYREG_USB_ARB_RW5_DR EQU 0x400060c8 - ENDIF - IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT -CYREG_USB_BUS_RST_CNT EQU 0x400060cc - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE -CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE -CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG -CYREG_USB_ARB_EP6_CFG EQU 0x400060d0 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN -CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR -CYREG_USB_ARB_EP6_SR EQU 0x400060d2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE -CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE -CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA -CYREG_USB_ARB_RW6_WA EQU 0x400060d4 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB -CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA -CYREG_USB_ARB_RW6_RA EQU 0x400060d6 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB -CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR -CYREG_USB_ARB_RW6_DR EQU 0x400060d8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE -CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE -CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG -CYREG_USB_ARB_EP7_CFG EQU 0x400060e0 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN -CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR -CYREG_USB_ARB_EP7_SR EQU 0x400060e2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE -CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE -CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA -CYREG_USB_ARB_RW7_WA EQU 0x400060e4 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB -CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA -CYREG_USB_ARB_RW7_RA EQU 0x400060e6 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB -CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR -CYREG_USB_ARB_RW7_DR EQU 0x400060e8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE -CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE -CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG -CYREG_USB_ARB_EP8_CFG EQU 0x400060f0 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN -CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR -CYREG_USB_ARB_EP8_SR EQU 0x400060f2 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE -CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 - ENDIF - IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE -CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA -CYREG_USB_ARB_RW8_WA EQU 0x400060f4 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB -CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA -CYREG_USB_ARB_RW8_RA EQU 0x400060f6 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB -CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7 - ENDIF - IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR -CYREG_USB_ARB_RW8_DR EQU 0x400060f8 - ENDIF - IF :LNOT::DEF:CYDEV_USB_MEM_BASE -CYDEV_USB_MEM_BASE EQU 0x40006100 - ENDIF - IF :LNOT::DEF:CYDEV_USB_MEM_SIZE -CYDEV_USB_MEM_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE -CYREG_USB_MEM_DATA_MBASE EQU 0x40006100 - ENDIF - IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE -CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_BASE -CYDEV_UWRK_BASE EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_SIZE -CYDEV_UWRK_SIZE EQU 0x00000b60 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE -CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE -CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE -CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE -CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_A0 -CYREG_B0_UDB00_A0 EQU 0x40006400 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_A0 -CYREG_B0_UDB01_A0 EQU 0x40006401 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_A0 -CYREG_B0_UDB02_A0 EQU 0x40006402 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_A0 -CYREG_B0_UDB03_A0 EQU 0x40006403 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_A0 -CYREG_B0_UDB04_A0 EQU 0x40006404 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_A0 -CYREG_B0_UDB05_A0 EQU 0x40006405 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_A0 -CYREG_B0_UDB06_A0 EQU 0x40006406 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_A0 -CYREG_B0_UDB07_A0 EQU 0x40006407 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_A0 -CYREG_B0_UDB08_A0 EQU 0x40006408 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_A0 -CYREG_B0_UDB09_A0 EQU 0x40006409 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_A0 -CYREG_B0_UDB10_A0 EQU 0x4000640a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_A0 -CYREG_B0_UDB11_A0 EQU 0x4000640b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_A0 -CYREG_B0_UDB12_A0 EQU 0x4000640c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_A0 -CYREG_B0_UDB13_A0 EQU 0x4000640d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_A0 -CYREG_B0_UDB14_A0 EQU 0x4000640e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_A0 -CYREG_B0_UDB15_A0 EQU 0x4000640f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_A1 -CYREG_B0_UDB00_A1 EQU 0x40006410 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_A1 -CYREG_B0_UDB01_A1 EQU 0x40006411 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_A1 -CYREG_B0_UDB02_A1 EQU 0x40006412 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_A1 -CYREG_B0_UDB03_A1 EQU 0x40006413 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_A1 -CYREG_B0_UDB04_A1 EQU 0x40006414 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_A1 -CYREG_B0_UDB05_A1 EQU 0x40006415 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_A1 -CYREG_B0_UDB06_A1 EQU 0x40006416 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_A1 -CYREG_B0_UDB07_A1 EQU 0x40006417 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_A1 -CYREG_B0_UDB08_A1 EQU 0x40006418 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_A1 -CYREG_B0_UDB09_A1 EQU 0x40006419 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_A1 -CYREG_B0_UDB10_A1 EQU 0x4000641a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_A1 -CYREG_B0_UDB11_A1 EQU 0x4000641b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_A1 -CYREG_B0_UDB12_A1 EQU 0x4000641c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_A1 -CYREG_B0_UDB13_A1 EQU 0x4000641d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_A1 -CYREG_B0_UDB14_A1 EQU 0x4000641e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_A1 -CYREG_B0_UDB15_A1 EQU 0x4000641f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_D0 -CYREG_B0_UDB00_D0 EQU 0x40006420 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_D0 -CYREG_B0_UDB01_D0 EQU 0x40006421 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_D0 -CYREG_B0_UDB02_D0 EQU 0x40006422 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_D0 -CYREG_B0_UDB03_D0 EQU 0x40006423 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_D0 -CYREG_B0_UDB04_D0 EQU 0x40006424 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_D0 -CYREG_B0_UDB05_D0 EQU 0x40006425 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_D0 -CYREG_B0_UDB06_D0 EQU 0x40006426 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_D0 -CYREG_B0_UDB07_D0 EQU 0x40006427 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_D0 -CYREG_B0_UDB08_D0 EQU 0x40006428 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_D0 -CYREG_B0_UDB09_D0 EQU 0x40006429 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_D0 -CYREG_B0_UDB10_D0 EQU 0x4000642a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_D0 -CYREG_B0_UDB11_D0 EQU 0x4000642b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_D0 -CYREG_B0_UDB12_D0 EQU 0x4000642c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_D0 -CYREG_B0_UDB13_D0 EQU 0x4000642d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_D0 -CYREG_B0_UDB14_D0 EQU 0x4000642e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_D0 -CYREG_B0_UDB15_D0 EQU 0x4000642f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_D1 -CYREG_B0_UDB00_D1 EQU 0x40006430 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_D1 -CYREG_B0_UDB01_D1 EQU 0x40006431 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_D1 -CYREG_B0_UDB02_D1 EQU 0x40006432 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_D1 -CYREG_B0_UDB03_D1 EQU 0x40006433 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_D1 -CYREG_B0_UDB04_D1 EQU 0x40006434 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_D1 -CYREG_B0_UDB05_D1 EQU 0x40006435 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_D1 -CYREG_B0_UDB06_D1 EQU 0x40006436 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_D1 -CYREG_B0_UDB07_D1 EQU 0x40006437 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_D1 -CYREG_B0_UDB08_D1 EQU 0x40006438 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_D1 -CYREG_B0_UDB09_D1 EQU 0x40006439 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_D1 -CYREG_B0_UDB10_D1 EQU 0x4000643a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_D1 -CYREG_B0_UDB11_D1 EQU 0x4000643b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_D1 -CYREG_B0_UDB12_D1 EQU 0x4000643c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_D1 -CYREG_B0_UDB13_D1 EQU 0x4000643d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_D1 -CYREG_B0_UDB14_D1 EQU 0x4000643e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_D1 -CYREG_B0_UDB15_D1 EQU 0x4000643f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_F0 -CYREG_B0_UDB00_F0 EQU 0x40006440 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_F0 -CYREG_B0_UDB01_F0 EQU 0x40006441 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_F0 -CYREG_B0_UDB02_F0 EQU 0x40006442 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_F0 -CYREG_B0_UDB03_F0 EQU 0x40006443 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_F0 -CYREG_B0_UDB04_F0 EQU 0x40006444 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_F0 -CYREG_B0_UDB05_F0 EQU 0x40006445 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_F0 -CYREG_B0_UDB06_F0 EQU 0x40006446 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_F0 -CYREG_B0_UDB07_F0 EQU 0x40006447 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_F0 -CYREG_B0_UDB08_F0 EQU 0x40006448 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_F0 -CYREG_B0_UDB09_F0 EQU 0x40006449 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_F0 -CYREG_B0_UDB10_F0 EQU 0x4000644a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_F0 -CYREG_B0_UDB11_F0 EQU 0x4000644b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_F0 -CYREG_B0_UDB12_F0 EQU 0x4000644c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_F0 -CYREG_B0_UDB13_F0 EQU 0x4000644d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_F0 -CYREG_B0_UDB14_F0 EQU 0x4000644e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_F0 -CYREG_B0_UDB15_F0 EQU 0x4000644f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_F1 -CYREG_B0_UDB00_F1 EQU 0x40006450 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_F1 -CYREG_B0_UDB01_F1 EQU 0x40006451 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_F1 -CYREG_B0_UDB02_F1 EQU 0x40006452 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_F1 -CYREG_B0_UDB03_F1 EQU 0x40006453 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_F1 -CYREG_B0_UDB04_F1 EQU 0x40006454 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_F1 -CYREG_B0_UDB05_F1 EQU 0x40006455 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_F1 -CYREG_B0_UDB06_F1 EQU 0x40006456 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_F1 -CYREG_B0_UDB07_F1 EQU 0x40006457 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_F1 -CYREG_B0_UDB08_F1 EQU 0x40006458 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_F1 -CYREG_B0_UDB09_F1 EQU 0x40006459 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_F1 -CYREG_B0_UDB10_F1 EQU 0x4000645a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_F1 -CYREG_B0_UDB11_F1 EQU 0x4000645b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_F1 -CYREG_B0_UDB12_F1 EQU 0x4000645c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_F1 -CYREG_B0_UDB13_F1 EQU 0x4000645d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_F1 -CYREG_B0_UDB14_F1 EQU 0x4000645e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_F1 -CYREG_B0_UDB15_F1 EQU 0x4000645f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_ST -CYREG_B0_UDB00_ST EQU 0x40006460 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_ST -CYREG_B0_UDB01_ST EQU 0x40006461 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_ST -CYREG_B0_UDB02_ST EQU 0x40006462 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_ST -CYREG_B0_UDB03_ST EQU 0x40006463 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_ST -CYREG_B0_UDB04_ST EQU 0x40006464 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_ST -CYREG_B0_UDB05_ST EQU 0x40006465 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_ST -CYREG_B0_UDB06_ST EQU 0x40006466 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_ST -CYREG_B0_UDB07_ST EQU 0x40006467 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_ST -CYREG_B0_UDB08_ST EQU 0x40006468 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_ST -CYREG_B0_UDB09_ST EQU 0x40006469 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_ST -CYREG_B0_UDB10_ST EQU 0x4000646a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_ST -CYREG_B0_UDB11_ST EQU 0x4000646b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_ST -CYREG_B0_UDB12_ST EQU 0x4000646c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_ST -CYREG_B0_UDB13_ST EQU 0x4000646d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_ST -CYREG_B0_UDB14_ST EQU 0x4000646e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_ST -CYREG_B0_UDB15_ST EQU 0x4000646f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_CTL -CYREG_B0_UDB00_CTL EQU 0x40006470 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_CTL -CYREG_B0_UDB01_CTL EQU 0x40006471 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_CTL -CYREG_B0_UDB02_CTL EQU 0x40006472 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_CTL -CYREG_B0_UDB03_CTL EQU 0x40006473 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_CTL -CYREG_B0_UDB04_CTL EQU 0x40006474 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_CTL -CYREG_B0_UDB05_CTL EQU 0x40006475 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_CTL -CYREG_B0_UDB06_CTL EQU 0x40006476 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_CTL -CYREG_B0_UDB07_CTL EQU 0x40006477 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_CTL -CYREG_B0_UDB08_CTL EQU 0x40006478 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_CTL -CYREG_B0_UDB09_CTL EQU 0x40006479 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_CTL -CYREG_B0_UDB10_CTL EQU 0x4000647a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_CTL -CYREG_B0_UDB11_CTL EQU 0x4000647b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_CTL -CYREG_B0_UDB12_CTL EQU 0x4000647c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_CTL -CYREG_B0_UDB13_CTL EQU 0x4000647d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_CTL -CYREG_B0_UDB14_CTL EQU 0x4000647e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_CTL -CYREG_B0_UDB15_CTL EQU 0x4000647f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_MSK -CYREG_B0_UDB00_MSK EQU 0x40006480 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_MSK -CYREG_B0_UDB01_MSK EQU 0x40006481 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_MSK -CYREG_B0_UDB02_MSK EQU 0x40006482 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_MSK -CYREG_B0_UDB03_MSK EQU 0x40006483 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_MSK -CYREG_B0_UDB04_MSK EQU 0x40006484 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_MSK -CYREG_B0_UDB05_MSK EQU 0x40006485 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_MSK -CYREG_B0_UDB06_MSK EQU 0x40006486 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_MSK -CYREG_B0_UDB07_MSK EQU 0x40006487 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_MSK -CYREG_B0_UDB08_MSK EQU 0x40006488 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_MSK -CYREG_B0_UDB09_MSK EQU 0x40006489 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_MSK -CYREG_B0_UDB10_MSK EQU 0x4000648a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_MSK -CYREG_B0_UDB11_MSK EQU 0x4000648b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_MSK -CYREG_B0_UDB12_MSK EQU 0x4000648c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_MSK -CYREG_B0_UDB13_MSK EQU 0x4000648d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_MSK -CYREG_B0_UDB14_MSK EQU 0x4000648e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_MSK -CYREG_B0_UDB15_MSK EQU 0x4000648f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_ACTL -CYREG_B0_UDB00_ACTL EQU 0x40006490 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_ACTL -CYREG_B0_UDB01_ACTL EQU 0x40006491 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_ACTL -CYREG_B0_UDB02_ACTL EQU 0x40006492 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_ACTL -CYREG_B0_UDB03_ACTL EQU 0x40006493 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_ACTL -CYREG_B0_UDB04_ACTL EQU 0x40006494 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_ACTL -CYREG_B0_UDB05_ACTL EQU 0x40006495 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_ACTL -CYREG_B0_UDB06_ACTL EQU 0x40006496 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_ACTL -CYREG_B0_UDB07_ACTL EQU 0x40006497 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_ACTL -CYREG_B0_UDB08_ACTL EQU 0x40006498 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_ACTL -CYREG_B0_UDB09_ACTL EQU 0x40006499 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_ACTL -CYREG_B0_UDB10_ACTL EQU 0x4000649a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_ACTL -CYREG_B0_UDB11_ACTL EQU 0x4000649b - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_ACTL -CYREG_B0_UDB12_ACTL EQU 0x4000649c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_ACTL -CYREG_B0_UDB13_ACTL EQU 0x4000649d - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_ACTL -CYREG_B0_UDB14_ACTL EQU 0x4000649e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_ACTL -CYREG_B0_UDB15_ACTL EQU 0x4000649f - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_MC -CYREG_B0_UDB00_MC EQU 0x400064a0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_MC -CYREG_B0_UDB01_MC EQU 0x400064a1 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_MC -CYREG_B0_UDB02_MC EQU 0x400064a2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_MC -CYREG_B0_UDB03_MC EQU 0x400064a3 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_MC -CYREG_B0_UDB04_MC EQU 0x400064a4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_MC -CYREG_B0_UDB05_MC EQU 0x400064a5 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_MC -CYREG_B0_UDB06_MC EQU 0x400064a6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_MC -CYREG_B0_UDB07_MC EQU 0x400064a7 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_MC -CYREG_B0_UDB08_MC EQU 0x400064a8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_MC -CYREG_B0_UDB09_MC EQU 0x400064a9 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_MC -CYREG_B0_UDB10_MC EQU 0x400064aa - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_MC -CYREG_B0_UDB11_MC EQU 0x400064ab - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_MC -CYREG_B0_UDB12_MC EQU 0x400064ac - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_MC -CYREG_B0_UDB13_MC EQU 0x400064ad - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_MC -CYREG_B0_UDB14_MC EQU 0x400064ae - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_MC -CYREG_B0_UDB15_MC EQU 0x400064af - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE -CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE -CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_A0 -CYREG_B1_UDB04_A0 EQU 0x40006504 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_A0 -CYREG_B1_UDB05_A0 EQU 0x40006505 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_A0 -CYREG_B1_UDB06_A0 EQU 0x40006506 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_A0 -CYREG_B1_UDB07_A0 EQU 0x40006507 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_A0 -CYREG_B1_UDB08_A0 EQU 0x40006508 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_A0 -CYREG_B1_UDB09_A0 EQU 0x40006509 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_A0 -CYREG_B1_UDB10_A0 EQU 0x4000650a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_A0 -CYREG_B1_UDB11_A0 EQU 0x4000650b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_A1 -CYREG_B1_UDB04_A1 EQU 0x40006514 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_A1 -CYREG_B1_UDB05_A1 EQU 0x40006515 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_A1 -CYREG_B1_UDB06_A1 EQU 0x40006516 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_A1 -CYREG_B1_UDB07_A1 EQU 0x40006517 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_A1 -CYREG_B1_UDB08_A1 EQU 0x40006518 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_A1 -CYREG_B1_UDB09_A1 EQU 0x40006519 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_A1 -CYREG_B1_UDB10_A1 EQU 0x4000651a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_A1 -CYREG_B1_UDB11_A1 EQU 0x4000651b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_D0 -CYREG_B1_UDB04_D0 EQU 0x40006524 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_D0 -CYREG_B1_UDB05_D0 EQU 0x40006525 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_D0 -CYREG_B1_UDB06_D0 EQU 0x40006526 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_D0 -CYREG_B1_UDB07_D0 EQU 0x40006527 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_D0 -CYREG_B1_UDB08_D0 EQU 0x40006528 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_D0 -CYREG_B1_UDB09_D0 EQU 0x40006529 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_D0 -CYREG_B1_UDB10_D0 EQU 0x4000652a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_D0 -CYREG_B1_UDB11_D0 EQU 0x4000652b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_D1 -CYREG_B1_UDB04_D1 EQU 0x40006534 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_D1 -CYREG_B1_UDB05_D1 EQU 0x40006535 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_D1 -CYREG_B1_UDB06_D1 EQU 0x40006536 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_D1 -CYREG_B1_UDB07_D1 EQU 0x40006537 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_D1 -CYREG_B1_UDB08_D1 EQU 0x40006538 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_D1 -CYREG_B1_UDB09_D1 EQU 0x40006539 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_D1 -CYREG_B1_UDB10_D1 EQU 0x4000653a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_D1 -CYREG_B1_UDB11_D1 EQU 0x4000653b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_F0 -CYREG_B1_UDB04_F0 EQU 0x40006544 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_F0 -CYREG_B1_UDB05_F0 EQU 0x40006545 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_F0 -CYREG_B1_UDB06_F0 EQU 0x40006546 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_F0 -CYREG_B1_UDB07_F0 EQU 0x40006547 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_F0 -CYREG_B1_UDB08_F0 EQU 0x40006548 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_F0 -CYREG_B1_UDB09_F0 EQU 0x40006549 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_F0 -CYREG_B1_UDB10_F0 EQU 0x4000654a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_F0 -CYREG_B1_UDB11_F0 EQU 0x4000654b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_F1 -CYREG_B1_UDB04_F1 EQU 0x40006554 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_F1 -CYREG_B1_UDB05_F1 EQU 0x40006555 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_F1 -CYREG_B1_UDB06_F1 EQU 0x40006556 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_F1 -CYREG_B1_UDB07_F1 EQU 0x40006557 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_F1 -CYREG_B1_UDB08_F1 EQU 0x40006558 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_F1 -CYREG_B1_UDB09_F1 EQU 0x40006559 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_F1 -CYREG_B1_UDB10_F1 EQU 0x4000655a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_F1 -CYREG_B1_UDB11_F1 EQU 0x4000655b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_ST -CYREG_B1_UDB04_ST EQU 0x40006564 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_ST -CYREG_B1_UDB05_ST EQU 0x40006565 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_ST -CYREG_B1_UDB06_ST EQU 0x40006566 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_ST -CYREG_B1_UDB07_ST EQU 0x40006567 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_ST -CYREG_B1_UDB08_ST EQU 0x40006568 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_ST -CYREG_B1_UDB09_ST EQU 0x40006569 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_ST -CYREG_B1_UDB10_ST EQU 0x4000656a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_ST -CYREG_B1_UDB11_ST EQU 0x4000656b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_CTL -CYREG_B1_UDB04_CTL EQU 0x40006574 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_CTL -CYREG_B1_UDB05_CTL EQU 0x40006575 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_CTL -CYREG_B1_UDB06_CTL EQU 0x40006576 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_CTL -CYREG_B1_UDB07_CTL EQU 0x40006577 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_CTL -CYREG_B1_UDB08_CTL EQU 0x40006578 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_CTL -CYREG_B1_UDB09_CTL EQU 0x40006579 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_CTL -CYREG_B1_UDB10_CTL EQU 0x4000657a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_CTL -CYREG_B1_UDB11_CTL EQU 0x4000657b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_MSK -CYREG_B1_UDB04_MSK EQU 0x40006584 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_MSK -CYREG_B1_UDB05_MSK EQU 0x40006585 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_MSK -CYREG_B1_UDB06_MSK EQU 0x40006586 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_MSK -CYREG_B1_UDB07_MSK EQU 0x40006587 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_MSK -CYREG_B1_UDB08_MSK EQU 0x40006588 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_MSK -CYREG_B1_UDB09_MSK EQU 0x40006589 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_MSK -CYREG_B1_UDB10_MSK EQU 0x4000658a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_MSK -CYREG_B1_UDB11_MSK EQU 0x4000658b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_ACTL -CYREG_B1_UDB04_ACTL EQU 0x40006594 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_ACTL -CYREG_B1_UDB05_ACTL EQU 0x40006595 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_ACTL -CYREG_B1_UDB06_ACTL EQU 0x40006596 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_ACTL -CYREG_B1_UDB07_ACTL EQU 0x40006597 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_ACTL -CYREG_B1_UDB08_ACTL EQU 0x40006598 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_ACTL -CYREG_B1_UDB09_ACTL EQU 0x40006599 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_ACTL -CYREG_B1_UDB10_ACTL EQU 0x4000659a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_ACTL -CYREG_B1_UDB11_ACTL EQU 0x4000659b - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_MC -CYREG_B1_UDB04_MC EQU 0x400065a4 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_MC -CYREG_B1_UDB05_MC EQU 0x400065a5 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_MC -CYREG_B1_UDB06_MC EQU 0x400065a6 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_MC -CYREG_B1_UDB07_MC EQU 0x400065a7 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_MC -CYREG_B1_UDB08_MC EQU 0x400065a8 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_MC -CYREG_B1_UDB09_MC EQU 0x400065a9 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_MC -CYREG_B1_UDB10_MC EQU 0x400065aa - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_MC -CYREG_B1_UDB11_MC EQU 0x400065ab - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE -CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE -CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE -CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE -CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE -CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE -CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1 -CYREG_B0_UDB00_A0_A1 EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1 -CYREG_B0_UDB01_A0_A1 EQU 0x40006802 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1 -CYREG_B0_UDB02_A0_A1 EQU 0x40006804 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1 -CYREG_B0_UDB03_A0_A1 EQU 0x40006806 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1 -CYREG_B0_UDB04_A0_A1 EQU 0x40006808 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1 -CYREG_B0_UDB05_A0_A1 EQU 0x4000680a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1 -CYREG_B0_UDB06_A0_A1 EQU 0x4000680c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1 -CYREG_B0_UDB07_A0_A1 EQU 0x4000680e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1 -CYREG_B0_UDB08_A0_A1 EQU 0x40006810 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1 -CYREG_B0_UDB09_A0_A1 EQU 0x40006812 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1 -CYREG_B0_UDB10_A0_A1 EQU 0x40006814 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1 -CYREG_B0_UDB11_A0_A1 EQU 0x40006816 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1 -CYREG_B0_UDB12_A0_A1 EQU 0x40006818 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1 -CYREG_B0_UDB13_A0_A1 EQU 0x4000681a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1 -CYREG_B0_UDB14_A0_A1 EQU 0x4000681c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1 -CYREG_B0_UDB15_A0_A1 EQU 0x4000681e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1 -CYREG_B0_UDB00_D0_D1 EQU 0x40006840 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1 -CYREG_B0_UDB01_D0_D1 EQU 0x40006842 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1 -CYREG_B0_UDB02_D0_D1 EQU 0x40006844 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1 -CYREG_B0_UDB03_D0_D1 EQU 0x40006846 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1 -CYREG_B0_UDB04_D0_D1 EQU 0x40006848 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1 -CYREG_B0_UDB05_D0_D1 EQU 0x4000684a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1 -CYREG_B0_UDB06_D0_D1 EQU 0x4000684c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1 -CYREG_B0_UDB07_D0_D1 EQU 0x4000684e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1 -CYREG_B0_UDB08_D0_D1 EQU 0x40006850 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1 -CYREG_B0_UDB09_D0_D1 EQU 0x40006852 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1 -CYREG_B0_UDB10_D0_D1 EQU 0x40006854 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1 -CYREG_B0_UDB11_D0_D1 EQU 0x40006856 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1 -CYREG_B0_UDB12_D0_D1 EQU 0x40006858 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1 -CYREG_B0_UDB13_D0_D1 EQU 0x4000685a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1 -CYREG_B0_UDB14_D0_D1 EQU 0x4000685c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1 -CYREG_B0_UDB15_D0_D1 EQU 0x4000685e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1 -CYREG_B0_UDB00_F0_F1 EQU 0x40006880 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1 -CYREG_B0_UDB01_F0_F1 EQU 0x40006882 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1 -CYREG_B0_UDB02_F0_F1 EQU 0x40006884 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1 -CYREG_B0_UDB03_F0_F1 EQU 0x40006886 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1 -CYREG_B0_UDB04_F0_F1 EQU 0x40006888 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1 -CYREG_B0_UDB05_F0_F1 EQU 0x4000688a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1 -CYREG_B0_UDB06_F0_F1 EQU 0x4000688c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1 -CYREG_B0_UDB07_F0_F1 EQU 0x4000688e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1 -CYREG_B0_UDB08_F0_F1 EQU 0x40006890 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1 -CYREG_B0_UDB09_F0_F1 EQU 0x40006892 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1 -CYREG_B0_UDB10_F0_F1 EQU 0x40006894 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1 -CYREG_B0_UDB11_F0_F1 EQU 0x40006896 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1 -CYREG_B0_UDB12_F0_F1 EQU 0x40006898 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1 -CYREG_B0_UDB13_F0_F1 EQU 0x4000689a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1 -CYREG_B0_UDB14_F0_F1 EQU 0x4000689c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1 -CYREG_B0_UDB15_F0_F1 EQU 0x4000689e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL -CYREG_B0_UDB00_ST_CTL EQU 0x400068c0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL -CYREG_B0_UDB01_ST_CTL EQU 0x400068c2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL -CYREG_B0_UDB02_ST_CTL EQU 0x400068c4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL -CYREG_B0_UDB03_ST_CTL EQU 0x400068c6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL -CYREG_B0_UDB04_ST_CTL EQU 0x400068c8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL -CYREG_B0_UDB05_ST_CTL EQU 0x400068ca - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL -CYREG_B0_UDB06_ST_CTL EQU 0x400068cc - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL -CYREG_B0_UDB07_ST_CTL EQU 0x400068ce - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL -CYREG_B0_UDB08_ST_CTL EQU 0x400068d0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL -CYREG_B0_UDB09_ST_CTL EQU 0x400068d2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL -CYREG_B0_UDB10_ST_CTL EQU 0x400068d4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL -CYREG_B0_UDB11_ST_CTL EQU 0x400068d6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL -CYREG_B0_UDB12_ST_CTL EQU 0x400068d8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL -CYREG_B0_UDB13_ST_CTL EQU 0x400068da - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL -CYREG_B0_UDB14_ST_CTL EQU 0x400068dc - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL -CYREG_B0_UDB15_ST_CTL EQU 0x400068de - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL -CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL -CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL -CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL -CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL -CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL -CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL -CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL -CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL -CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL -CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL -CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL -CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL -CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL -CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL -CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL -CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_MC_00 -CYREG_B0_UDB00_MC_00 EQU 0x40006940 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_MC_00 -CYREG_B0_UDB01_MC_00 EQU 0x40006942 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_MC_00 -CYREG_B0_UDB02_MC_00 EQU 0x40006944 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_MC_00 -CYREG_B0_UDB03_MC_00 EQU 0x40006946 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_MC_00 -CYREG_B0_UDB04_MC_00 EQU 0x40006948 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_MC_00 -CYREG_B0_UDB05_MC_00 EQU 0x4000694a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_MC_00 -CYREG_B0_UDB06_MC_00 EQU 0x4000694c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_MC_00 -CYREG_B0_UDB07_MC_00 EQU 0x4000694e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_MC_00 -CYREG_B0_UDB08_MC_00 EQU 0x40006950 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_MC_00 -CYREG_B0_UDB09_MC_00 EQU 0x40006952 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_MC_00 -CYREG_B0_UDB10_MC_00 EQU 0x40006954 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_MC_00 -CYREG_B0_UDB11_MC_00 EQU 0x40006956 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_MC_00 -CYREG_B0_UDB12_MC_00 EQU 0x40006958 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_MC_00 -CYREG_B0_UDB13_MC_00 EQU 0x4000695a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_MC_00 -CYREG_B0_UDB14_MC_00 EQU 0x4000695c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB15_MC_00 -CYREG_B0_UDB15_MC_00 EQU 0x4000695e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE -CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE -CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1 -CYREG_B1_UDB04_A0_A1 EQU 0x40006a08 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1 -CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1 -CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1 -CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1 -CYREG_B1_UDB08_A0_A1 EQU 0x40006a10 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1 -CYREG_B1_UDB09_A0_A1 EQU 0x40006a12 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1 -CYREG_B1_UDB10_A0_A1 EQU 0x40006a14 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1 -CYREG_B1_UDB11_A0_A1 EQU 0x40006a16 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1 -CYREG_B1_UDB04_D0_D1 EQU 0x40006a48 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1 -CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1 -CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1 -CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1 -CYREG_B1_UDB08_D0_D1 EQU 0x40006a50 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1 -CYREG_B1_UDB09_D0_D1 EQU 0x40006a52 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1 -CYREG_B1_UDB10_D0_D1 EQU 0x40006a54 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1 -CYREG_B1_UDB11_D0_D1 EQU 0x40006a56 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1 -CYREG_B1_UDB04_F0_F1 EQU 0x40006a88 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1 -CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1 -CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1 -CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1 -CYREG_B1_UDB08_F0_F1 EQU 0x40006a90 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1 -CYREG_B1_UDB09_F0_F1 EQU 0x40006a92 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1 -CYREG_B1_UDB10_F0_F1 EQU 0x40006a94 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1 -CYREG_B1_UDB11_F0_F1 EQU 0x40006a96 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL -CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL -CYREG_B1_UDB05_ST_CTL EQU 0x40006aca - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL -CYREG_B1_UDB06_ST_CTL EQU 0x40006acc - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL -CYREG_B1_UDB07_ST_CTL EQU 0x40006ace - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL -CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL -CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL -CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL -CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL -CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL -CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL -CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL -CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL -CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL -CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL -CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL -CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_MC_00 -CYREG_B1_UDB04_MC_00 EQU 0x40006b48 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_MC_00 -CYREG_B1_UDB05_MC_00 EQU 0x40006b4a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_MC_00 -CYREG_B1_UDB06_MC_00 EQU 0x40006b4c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_MC_00 -CYREG_B1_UDB07_MC_00 EQU 0x40006b4e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_MC_00 -CYREG_B1_UDB08_MC_00 EQU 0x40006b50 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_MC_00 -CYREG_B1_UDB09_MC_00 EQU 0x40006b52 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_MC_00 -CYREG_B1_UDB10_MC_00 EQU 0x40006b54 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_MC_00 -CYREG_B1_UDB11_MC_00 EQU 0x40006b56 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE -CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE -CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE -CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE -CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_A0 -CYREG_B0_UDB00_01_A0 EQU 0x40006800 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_A0 -CYREG_B0_UDB01_02_A0 EQU 0x40006802 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_A0 -CYREG_B0_UDB02_03_A0 EQU 0x40006804 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_A0 -CYREG_B0_UDB03_04_A0 EQU 0x40006806 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_A0 -CYREG_B0_UDB04_05_A0 EQU 0x40006808 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_A0 -CYREG_B0_UDB05_06_A0 EQU 0x4000680a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_A0 -CYREG_B0_UDB06_07_A0 EQU 0x4000680c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_A0 -CYREG_B0_UDB07_08_A0 EQU 0x4000680e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_A0 -CYREG_B0_UDB08_09_A0 EQU 0x40006810 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_A0 -CYREG_B0_UDB09_10_A0 EQU 0x40006812 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_A0 -CYREG_B0_UDB10_11_A0 EQU 0x40006814 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_A0 -CYREG_B0_UDB11_12_A0 EQU 0x40006816 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_A0 -CYREG_B0_UDB12_13_A0 EQU 0x40006818 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_A0 -CYREG_B0_UDB13_14_A0 EQU 0x4000681a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_A0 -CYREG_B0_UDB14_15_A0 EQU 0x4000681c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_A1 -CYREG_B0_UDB00_01_A1 EQU 0x40006820 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_A1 -CYREG_B0_UDB01_02_A1 EQU 0x40006822 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_A1 -CYREG_B0_UDB02_03_A1 EQU 0x40006824 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_A1 -CYREG_B0_UDB03_04_A1 EQU 0x40006826 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_A1 -CYREG_B0_UDB04_05_A1 EQU 0x40006828 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_A1 -CYREG_B0_UDB05_06_A1 EQU 0x4000682a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_A1 -CYREG_B0_UDB06_07_A1 EQU 0x4000682c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_A1 -CYREG_B0_UDB07_08_A1 EQU 0x4000682e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_A1 -CYREG_B0_UDB08_09_A1 EQU 0x40006830 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_A1 -CYREG_B0_UDB09_10_A1 EQU 0x40006832 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_A1 -CYREG_B0_UDB10_11_A1 EQU 0x40006834 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_A1 -CYREG_B0_UDB11_12_A1 EQU 0x40006836 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_A1 -CYREG_B0_UDB12_13_A1 EQU 0x40006838 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_A1 -CYREG_B0_UDB13_14_A1 EQU 0x4000683a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_A1 -CYREG_B0_UDB14_15_A1 EQU 0x4000683c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_D0 -CYREG_B0_UDB00_01_D0 EQU 0x40006840 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_D0 -CYREG_B0_UDB01_02_D0 EQU 0x40006842 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_D0 -CYREG_B0_UDB02_03_D0 EQU 0x40006844 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_D0 -CYREG_B0_UDB03_04_D0 EQU 0x40006846 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_D0 -CYREG_B0_UDB04_05_D0 EQU 0x40006848 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_D0 -CYREG_B0_UDB05_06_D0 EQU 0x4000684a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_D0 -CYREG_B0_UDB06_07_D0 EQU 0x4000684c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_D0 -CYREG_B0_UDB07_08_D0 EQU 0x4000684e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_D0 -CYREG_B0_UDB08_09_D0 EQU 0x40006850 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_D0 -CYREG_B0_UDB09_10_D0 EQU 0x40006852 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_D0 -CYREG_B0_UDB10_11_D0 EQU 0x40006854 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_D0 -CYREG_B0_UDB11_12_D0 EQU 0x40006856 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_D0 -CYREG_B0_UDB12_13_D0 EQU 0x40006858 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_D0 -CYREG_B0_UDB13_14_D0 EQU 0x4000685a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_D0 -CYREG_B0_UDB14_15_D0 EQU 0x4000685c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_D1 -CYREG_B0_UDB00_01_D1 EQU 0x40006860 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_D1 -CYREG_B0_UDB01_02_D1 EQU 0x40006862 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_D1 -CYREG_B0_UDB02_03_D1 EQU 0x40006864 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_D1 -CYREG_B0_UDB03_04_D1 EQU 0x40006866 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_D1 -CYREG_B0_UDB04_05_D1 EQU 0x40006868 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_D1 -CYREG_B0_UDB05_06_D1 EQU 0x4000686a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_D1 -CYREG_B0_UDB06_07_D1 EQU 0x4000686c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_D1 -CYREG_B0_UDB07_08_D1 EQU 0x4000686e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_D1 -CYREG_B0_UDB08_09_D1 EQU 0x40006870 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_D1 -CYREG_B0_UDB09_10_D1 EQU 0x40006872 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_D1 -CYREG_B0_UDB10_11_D1 EQU 0x40006874 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_D1 -CYREG_B0_UDB11_12_D1 EQU 0x40006876 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_D1 -CYREG_B0_UDB12_13_D1 EQU 0x40006878 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_D1 -CYREG_B0_UDB13_14_D1 EQU 0x4000687a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_D1 -CYREG_B0_UDB14_15_D1 EQU 0x4000687c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_F0 -CYREG_B0_UDB00_01_F0 EQU 0x40006880 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_F0 -CYREG_B0_UDB01_02_F0 EQU 0x40006882 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_F0 -CYREG_B0_UDB02_03_F0 EQU 0x40006884 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_F0 -CYREG_B0_UDB03_04_F0 EQU 0x40006886 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_F0 -CYREG_B0_UDB04_05_F0 EQU 0x40006888 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_F0 -CYREG_B0_UDB05_06_F0 EQU 0x4000688a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_F0 -CYREG_B0_UDB06_07_F0 EQU 0x4000688c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_F0 -CYREG_B0_UDB07_08_F0 EQU 0x4000688e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_F0 -CYREG_B0_UDB08_09_F0 EQU 0x40006890 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_F0 -CYREG_B0_UDB09_10_F0 EQU 0x40006892 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_F0 -CYREG_B0_UDB10_11_F0 EQU 0x40006894 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_F0 -CYREG_B0_UDB11_12_F0 EQU 0x40006896 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_F0 -CYREG_B0_UDB12_13_F0 EQU 0x40006898 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_F0 -CYREG_B0_UDB13_14_F0 EQU 0x4000689a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_F0 -CYREG_B0_UDB14_15_F0 EQU 0x4000689c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_F1 -CYREG_B0_UDB00_01_F1 EQU 0x400068a0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_F1 -CYREG_B0_UDB01_02_F1 EQU 0x400068a2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_F1 -CYREG_B0_UDB02_03_F1 EQU 0x400068a4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_F1 -CYREG_B0_UDB03_04_F1 EQU 0x400068a6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_F1 -CYREG_B0_UDB04_05_F1 EQU 0x400068a8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_F1 -CYREG_B0_UDB05_06_F1 EQU 0x400068aa - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_F1 -CYREG_B0_UDB06_07_F1 EQU 0x400068ac - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_F1 -CYREG_B0_UDB07_08_F1 EQU 0x400068ae - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_F1 -CYREG_B0_UDB08_09_F1 EQU 0x400068b0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_F1 -CYREG_B0_UDB09_10_F1 EQU 0x400068b2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_F1 -CYREG_B0_UDB10_11_F1 EQU 0x400068b4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_F1 -CYREG_B0_UDB11_12_F1 EQU 0x400068b6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_F1 -CYREG_B0_UDB12_13_F1 EQU 0x400068b8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_F1 -CYREG_B0_UDB13_14_F1 EQU 0x400068ba - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_F1 -CYREG_B0_UDB14_15_F1 EQU 0x400068bc - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_ST -CYREG_B0_UDB00_01_ST EQU 0x400068c0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_ST -CYREG_B0_UDB01_02_ST EQU 0x400068c2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_ST -CYREG_B0_UDB02_03_ST EQU 0x400068c4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_ST -CYREG_B0_UDB03_04_ST EQU 0x400068c6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_ST -CYREG_B0_UDB04_05_ST EQU 0x400068c8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_ST -CYREG_B0_UDB05_06_ST EQU 0x400068ca - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_ST -CYREG_B0_UDB06_07_ST EQU 0x400068cc - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_ST -CYREG_B0_UDB07_08_ST EQU 0x400068ce - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_ST -CYREG_B0_UDB08_09_ST EQU 0x400068d0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_ST -CYREG_B0_UDB09_10_ST EQU 0x400068d2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_ST -CYREG_B0_UDB10_11_ST EQU 0x400068d4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_ST -CYREG_B0_UDB11_12_ST EQU 0x400068d6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_ST -CYREG_B0_UDB12_13_ST EQU 0x400068d8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_ST -CYREG_B0_UDB13_14_ST EQU 0x400068da - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_ST -CYREG_B0_UDB14_15_ST EQU 0x400068dc - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL -CYREG_B0_UDB00_01_CTL EQU 0x400068e0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL -CYREG_B0_UDB01_02_CTL EQU 0x400068e2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL -CYREG_B0_UDB02_03_CTL EQU 0x400068e4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL -CYREG_B0_UDB03_04_CTL EQU 0x400068e6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL -CYREG_B0_UDB04_05_CTL EQU 0x400068e8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL -CYREG_B0_UDB05_06_CTL EQU 0x400068ea - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL -CYREG_B0_UDB06_07_CTL EQU 0x400068ec - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL -CYREG_B0_UDB07_08_CTL EQU 0x400068ee - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL -CYREG_B0_UDB08_09_CTL EQU 0x400068f0 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL -CYREG_B0_UDB09_10_CTL EQU 0x400068f2 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL -CYREG_B0_UDB10_11_CTL EQU 0x400068f4 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL -CYREG_B0_UDB11_12_CTL EQU 0x400068f6 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL -CYREG_B0_UDB12_13_CTL EQU 0x400068f8 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL -CYREG_B0_UDB13_14_CTL EQU 0x400068fa - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL -CYREG_B0_UDB14_15_CTL EQU 0x400068fc - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK -CYREG_B0_UDB00_01_MSK EQU 0x40006900 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK -CYREG_B0_UDB01_02_MSK EQU 0x40006902 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK -CYREG_B0_UDB02_03_MSK EQU 0x40006904 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK -CYREG_B0_UDB03_04_MSK EQU 0x40006906 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK -CYREG_B0_UDB04_05_MSK EQU 0x40006908 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK -CYREG_B0_UDB05_06_MSK EQU 0x4000690a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK -CYREG_B0_UDB06_07_MSK EQU 0x4000690c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK -CYREG_B0_UDB07_08_MSK EQU 0x4000690e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK -CYREG_B0_UDB08_09_MSK EQU 0x40006910 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK -CYREG_B0_UDB09_10_MSK EQU 0x40006912 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK -CYREG_B0_UDB10_11_MSK EQU 0x40006914 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK -CYREG_B0_UDB11_12_MSK EQU 0x40006916 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK -CYREG_B0_UDB12_13_MSK EQU 0x40006918 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK -CYREG_B0_UDB13_14_MSK EQU 0x4000691a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK -CYREG_B0_UDB14_15_MSK EQU 0x4000691c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL -CYREG_B0_UDB00_01_ACTL EQU 0x40006920 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL -CYREG_B0_UDB01_02_ACTL EQU 0x40006922 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL -CYREG_B0_UDB02_03_ACTL EQU 0x40006924 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL -CYREG_B0_UDB03_04_ACTL EQU 0x40006926 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL -CYREG_B0_UDB04_05_ACTL EQU 0x40006928 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL -CYREG_B0_UDB05_06_ACTL EQU 0x4000692a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL -CYREG_B0_UDB06_07_ACTL EQU 0x4000692c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL -CYREG_B0_UDB07_08_ACTL EQU 0x4000692e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL -CYREG_B0_UDB08_09_ACTL EQU 0x40006930 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL -CYREG_B0_UDB09_10_ACTL EQU 0x40006932 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL -CYREG_B0_UDB10_11_ACTL EQU 0x40006934 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL -CYREG_B0_UDB11_12_ACTL EQU 0x40006936 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL -CYREG_B0_UDB12_13_ACTL EQU 0x40006938 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL -CYREG_B0_UDB13_14_ACTL EQU 0x4000693a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL -CYREG_B0_UDB14_15_ACTL EQU 0x4000693c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB00_01_MC -CYREG_B0_UDB00_01_MC EQU 0x40006940 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB01_02_MC -CYREG_B0_UDB01_02_MC EQU 0x40006942 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB02_03_MC -CYREG_B0_UDB02_03_MC EQU 0x40006944 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB03_04_MC -CYREG_B0_UDB03_04_MC EQU 0x40006946 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB04_05_MC -CYREG_B0_UDB04_05_MC EQU 0x40006948 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB05_06_MC -CYREG_B0_UDB05_06_MC EQU 0x4000694a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB06_07_MC -CYREG_B0_UDB06_07_MC EQU 0x4000694c - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB07_08_MC -CYREG_B0_UDB07_08_MC EQU 0x4000694e - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB08_09_MC -CYREG_B0_UDB08_09_MC EQU 0x40006950 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB09_10_MC -CYREG_B0_UDB09_10_MC EQU 0x40006952 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB10_11_MC -CYREG_B0_UDB10_11_MC EQU 0x40006954 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB11_12_MC -CYREG_B0_UDB11_12_MC EQU 0x40006956 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB12_13_MC -CYREG_B0_UDB12_13_MC EQU 0x40006958 - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB13_14_MC -CYREG_B0_UDB13_14_MC EQU 0x4000695a - ENDIF - IF :LNOT::DEF:CYREG_B0_UDB14_15_MC -CYREG_B0_UDB14_15_MC EQU 0x4000695c - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE -CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 - ENDIF - IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE -CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_A0 -CYREG_B1_UDB04_05_A0 EQU 0x40006a08 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_A0 -CYREG_B1_UDB05_06_A0 EQU 0x40006a0a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_A0 -CYREG_B1_UDB06_07_A0 EQU 0x40006a0c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_A0 -CYREG_B1_UDB07_08_A0 EQU 0x40006a0e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_A0 -CYREG_B1_UDB08_09_A0 EQU 0x40006a10 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_A0 -CYREG_B1_UDB09_10_A0 EQU 0x40006a12 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_A0 -CYREG_B1_UDB10_11_A0 EQU 0x40006a14 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_A0 -CYREG_B1_UDB11_12_A0 EQU 0x40006a16 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_A1 -CYREG_B1_UDB04_05_A1 EQU 0x40006a28 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_A1 -CYREG_B1_UDB05_06_A1 EQU 0x40006a2a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_A1 -CYREG_B1_UDB06_07_A1 EQU 0x40006a2c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_A1 -CYREG_B1_UDB07_08_A1 EQU 0x40006a2e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_A1 -CYREG_B1_UDB08_09_A1 EQU 0x40006a30 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_A1 -CYREG_B1_UDB09_10_A1 EQU 0x40006a32 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_A1 -CYREG_B1_UDB10_11_A1 EQU 0x40006a34 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_A1 -CYREG_B1_UDB11_12_A1 EQU 0x40006a36 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_D0 -CYREG_B1_UDB04_05_D0 EQU 0x40006a48 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_D0 -CYREG_B1_UDB05_06_D0 EQU 0x40006a4a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_D0 -CYREG_B1_UDB06_07_D0 EQU 0x40006a4c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_D0 -CYREG_B1_UDB07_08_D0 EQU 0x40006a4e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_D0 -CYREG_B1_UDB08_09_D0 EQU 0x40006a50 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_D0 -CYREG_B1_UDB09_10_D0 EQU 0x40006a52 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_D0 -CYREG_B1_UDB10_11_D0 EQU 0x40006a54 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_D0 -CYREG_B1_UDB11_12_D0 EQU 0x40006a56 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_D1 -CYREG_B1_UDB04_05_D1 EQU 0x40006a68 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_D1 -CYREG_B1_UDB05_06_D1 EQU 0x40006a6a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_D1 -CYREG_B1_UDB06_07_D1 EQU 0x40006a6c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_D1 -CYREG_B1_UDB07_08_D1 EQU 0x40006a6e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_D1 -CYREG_B1_UDB08_09_D1 EQU 0x40006a70 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_D1 -CYREG_B1_UDB09_10_D1 EQU 0x40006a72 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_D1 -CYREG_B1_UDB10_11_D1 EQU 0x40006a74 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_D1 -CYREG_B1_UDB11_12_D1 EQU 0x40006a76 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_F0 -CYREG_B1_UDB04_05_F0 EQU 0x40006a88 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_F0 -CYREG_B1_UDB05_06_F0 EQU 0x40006a8a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_F0 -CYREG_B1_UDB06_07_F0 EQU 0x40006a8c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_F0 -CYREG_B1_UDB07_08_F0 EQU 0x40006a8e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_F0 -CYREG_B1_UDB08_09_F0 EQU 0x40006a90 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_F0 -CYREG_B1_UDB09_10_F0 EQU 0x40006a92 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_F0 -CYREG_B1_UDB10_11_F0 EQU 0x40006a94 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_F0 -CYREG_B1_UDB11_12_F0 EQU 0x40006a96 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_F1 -CYREG_B1_UDB04_05_F1 EQU 0x40006aa8 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_F1 -CYREG_B1_UDB05_06_F1 EQU 0x40006aaa - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_F1 -CYREG_B1_UDB06_07_F1 EQU 0x40006aac - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_F1 -CYREG_B1_UDB07_08_F1 EQU 0x40006aae - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_F1 -CYREG_B1_UDB08_09_F1 EQU 0x40006ab0 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_F1 -CYREG_B1_UDB09_10_F1 EQU 0x40006ab2 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_F1 -CYREG_B1_UDB10_11_F1 EQU 0x40006ab4 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_F1 -CYREG_B1_UDB11_12_F1 EQU 0x40006ab6 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_ST -CYREG_B1_UDB04_05_ST EQU 0x40006ac8 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_ST -CYREG_B1_UDB05_06_ST EQU 0x40006aca - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_ST -CYREG_B1_UDB06_07_ST EQU 0x40006acc - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_ST -CYREG_B1_UDB07_08_ST EQU 0x40006ace - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_ST -CYREG_B1_UDB08_09_ST EQU 0x40006ad0 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_ST -CYREG_B1_UDB09_10_ST EQU 0x40006ad2 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_ST -CYREG_B1_UDB10_11_ST EQU 0x40006ad4 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_ST -CYREG_B1_UDB11_12_ST EQU 0x40006ad6 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL -CYREG_B1_UDB04_05_CTL EQU 0x40006ae8 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL -CYREG_B1_UDB05_06_CTL EQU 0x40006aea - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL -CYREG_B1_UDB06_07_CTL EQU 0x40006aec - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL -CYREG_B1_UDB07_08_CTL EQU 0x40006aee - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL -CYREG_B1_UDB08_09_CTL EQU 0x40006af0 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL -CYREG_B1_UDB09_10_CTL EQU 0x40006af2 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL -CYREG_B1_UDB10_11_CTL EQU 0x40006af4 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL -CYREG_B1_UDB11_12_CTL EQU 0x40006af6 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK -CYREG_B1_UDB04_05_MSK EQU 0x40006b08 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK -CYREG_B1_UDB05_06_MSK EQU 0x40006b0a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK -CYREG_B1_UDB06_07_MSK EQU 0x40006b0c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK -CYREG_B1_UDB07_08_MSK EQU 0x40006b0e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK -CYREG_B1_UDB08_09_MSK EQU 0x40006b10 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK -CYREG_B1_UDB09_10_MSK EQU 0x40006b12 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK -CYREG_B1_UDB10_11_MSK EQU 0x40006b14 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK -CYREG_B1_UDB11_12_MSK EQU 0x40006b16 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL -CYREG_B1_UDB04_05_ACTL EQU 0x40006b28 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL -CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL -CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL -CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL -CYREG_B1_UDB08_09_ACTL EQU 0x40006b30 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL -CYREG_B1_UDB09_10_ACTL EQU 0x40006b32 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL -CYREG_B1_UDB10_11_ACTL EQU 0x40006b34 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL -CYREG_B1_UDB11_12_ACTL EQU 0x40006b36 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB04_05_MC -CYREG_B1_UDB04_05_MC EQU 0x40006b48 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB05_06_MC -CYREG_B1_UDB05_06_MC EQU 0x40006b4a - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB06_07_MC -CYREG_B1_UDB06_07_MC EQU 0x40006b4c - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB07_08_MC -CYREG_B1_UDB07_08_MC EQU 0x40006b4e - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB08_09_MC -CYREG_B1_UDB08_09_MC EQU 0x40006b50 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB09_10_MC -CYREG_B1_UDB09_10_MC EQU 0x40006b52 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB10_11_MC -CYREG_B1_UDB10_11_MC EQU 0x40006b54 - ENDIF - IF :LNOT::DEF:CYREG_B1_UDB11_12_MC -CYREG_B1_UDB11_12_MC EQU 0x40006b56 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_BASE -CYDEV_PHUB_BASE EQU 0x40007000 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_SIZE -CYDEV_PHUB_SIZE EQU 0x00000c00 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFG -CYREG_PHUB_CFG EQU 0x40007000 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_ERR -CYREG_PHUB_ERR EQU 0x40007004 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_ERR_ADR -CYREG_PHUB_ERR_ADR EQU 0x40007008 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE -CYDEV_PHUB_CH0_BASE EQU 0x40007010 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE -CYDEV_PHUB_CH0_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG -CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION -CYREG_PHUB_CH0_ACTION EQU 0x40007014 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS -CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE -CYDEV_PHUB_CH1_BASE EQU 0x40007020 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE -CYDEV_PHUB_CH1_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG -CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION -CYREG_PHUB_CH1_ACTION EQU 0x40007024 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS -CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE -CYDEV_PHUB_CH2_BASE EQU 0x40007030 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE -CYDEV_PHUB_CH2_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG -CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION -CYREG_PHUB_CH2_ACTION EQU 0x40007034 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS -CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE -CYDEV_PHUB_CH3_BASE EQU 0x40007040 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE -CYDEV_PHUB_CH3_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG -CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION -CYREG_PHUB_CH3_ACTION EQU 0x40007044 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS -CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE -CYDEV_PHUB_CH4_BASE EQU 0x40007050 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE -CYDEV_PHUB_CH4_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG -CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION -CYREG_PHUB_CH4_ACTION EQU 0x40007054 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS -CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE -CYDEV_PHUB_CH5_BASE EQU 0x40007060 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE -CYDEV_PHUB_CH5_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG -CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION -CYREG_PHUB_CH5_ACTION EQU 0x40007064 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS -CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE -CYDEV_PHUB_CH6_BASE EQU 0x40007070 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE -CYDEV_PHUB_CH6_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG -CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION -CYREG_PHUB_CH6_ACTION EQU 0x40007074 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS -CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE -CYDEV_PHUB_CH7_BASE EQU 0x40007080 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE -CYDEV_PHUB_CH7_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG -CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION -CYREG_PHUB_CH7_ACTION EQU 0x40007084 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS -CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE -CYDEV_PHUB_CH8_BASE EQU 0x40007090 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE -CYDEV_PHUB_CH8_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG -CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION -CYREG_PHUB_CH8_ACTION EQU 0x40007094 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS -CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE -CYDEV_PHUB_CH9_BASE EQU 0x400070a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE -CYDEV_PHUB_CH9_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG -CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION -CYREG_PHUB_CH9_ACTION EQU 0x400070a4 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS -CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE -CYDEV_PHUB_CH10_BASE EQU 0x400070b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE -CYDEV_PHUB_CH10_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG -CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION -CYREG_PHUB_CH10_ACTION EQU 0x400070b4 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS -CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE -CYDEV_PHUB_CH11_BASE EQU 0x400070c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE -CYDEV_PHUB_CH11_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG -CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION -CYREG_PHUB_CH11_ACTION EQU 0x400070c4 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS -CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE -CYDEV_PHUB_CH12_BASE EQU 0x400070d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE -CYDEV_PHUB_CH12_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG -CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION -CYREG_PHUB_CH12_ACTION EQU 0x400070d4 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS -CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE -CYDEV_PHUB_CH13_BASE EQU 0x400070e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE -CYDEV_PHUB_CH13_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG -CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION -CYREG_PHUB_CH13_ACTION EQU 0x400070e4 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS -CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE -CYDEV_PHUB_CH14_BASE EQU 0x400070f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE -CYDEV_PHUB_CH14_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG -CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION -CYREG_PHUB_CH14_ACTION EQU 0x400070f4 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS -CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE -CYDEV_PHUB_CH15_BASE EQU 0x40007100 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE -CYDEV_PHUB_CH15_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG -CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION -CYREG_PHUB_CH15_ACTION EQU 0x40007104 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS -CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE -CYDEV_PHUB_CH16_BASE EQU 0x40007110 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE -CYDEV_PHUB_CH16_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG -CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION -CYREG_PHUB_CH16_ACTION EQU 0x40007114 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS -CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE -CYDEV_PHUB_CH17_BASE EQU 0x40007120 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE -CYDEV_PHUB_CH17_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG -CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION -CYREG_PHUB_CH17_ACTION EQU 0x40007124 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS -CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE -CYDEV_PHUB_CH18_BASE EQU 0x40007130 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE -CYDEV_PHUB_CH18_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG -CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION -CYREG_PHUB_CH18_ACTION EQU 0x40007134 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS -CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE -CYDEV_PHUB_CH19_BASE EQU 0x40007140 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE -CYDEV_PHUB_CH19_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG -CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION -CYREG_PHUB_CH19_ACTION EQU 0x40007144 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS -CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE -CYDEV_PHUB_CH20_BASE EQU 0x40007150 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE -CYDEV_PHUB_CH20_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG -CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION -CYREG_PHUB_CH20_ACTION EQU 0x40007154 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS -CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE -CYDEV_PHUB_CH21_BASE EQU 0x40007160 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE -CYDEV_PHUB_CH21_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG -CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION -CYREG_PHUB_CH21_ACTION EQU 0x40007164 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS -CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE -CYDEV_PHUB_CH22_BASE EQU 0x40007170 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE -CYDEV_PHUB_CH22_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG -CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION -CYREG_PHUB_CH22_ACTION EQU 0x40007174 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS -CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE -CYDEV_PHUB_CH23_BASE EQU 0x40007180 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE -CYDEV_PHUB_CH23_SIZE EQU 0x0000000c - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG -CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION -CYREG_PHUB_CH23_ACTION EQU 0x40007184 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS -CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE -CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE -CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0 -CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1 -CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE -CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE -CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0 -CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1 -CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE -CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE -CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0 -CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1 -CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE -CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE -CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0 -CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1 -CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE -CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE -CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0 -CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1 -CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE -CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE -CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0 -CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1 -CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE -CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE -CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0 -CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1 -CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE -CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE -CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0 -CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1 -CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE -CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE -CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0 -CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1 -CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE -CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE -CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0 -CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1 -CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE -CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE -CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0 -CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1 -CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE -CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE -CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0 -CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1 -CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE -CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE -CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0 -CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1 -CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE -CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE -CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0 -CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1 -CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE -CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE -CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0 -CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1 -CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE -CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE -CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0 -CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1 -CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE -CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE -CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0 -CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1 -CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE -CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE -CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0 -CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1 -CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE -CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE -CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0 -CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1 -CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE -CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE -CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0 -CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1 -CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE -CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE -CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0 -CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1 -CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE -CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE -CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0 -CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1 -CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE -CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE -CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0 -CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1 -CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE -CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE -CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0 -CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1 -CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE -CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE -CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0 -CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1 -CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE -CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE -CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0 -CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1 -CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE -CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE -CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0 -CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1 -CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE -CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE -CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0 -CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1 -CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE -CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE -CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0 -CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1 -CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE -CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE -CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0 -CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1 -CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE -CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE -CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0 -CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1 -CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE -CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE -CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0 -CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1 -CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE -CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE -CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0 -CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1 -CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE -CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE -CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0 -CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1 -CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE -CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE -CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0 -CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1 -CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE -CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE -CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0 -CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1 -CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE -CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE -CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0 -CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1 -CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE -CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE -CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0 -CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1 -CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE -CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE -CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0 -CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1 -CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE -CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE -CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0 -CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1 -CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE -CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE -CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0 -CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1 -CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE -CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE -CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0 -CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1 -CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE -CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE -CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0 -CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1 -CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE -CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE -CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0 -CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1 -CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE -CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE -CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0 -CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1 -CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE -CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE -CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0 -CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1 -CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE -CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE -CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0 -CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1 -CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE -CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE -CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0 -CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1 -CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE -CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE -CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0 -CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1 -CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE -CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE -CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0 -CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1 -CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE -CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE -CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0 -CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1 -CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE -CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE -CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0 -CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1 -CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE -CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE -CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0 -CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1 -CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE -CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE -CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0 -CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1 -CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE -CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE -CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0 -CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1 -CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE -CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE -CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0 -CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1 -CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE -CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE -CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0 -CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1 -CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE -CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE -CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0 -CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1 -CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE -CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE -CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0 -CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1 -CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE -CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE -CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0 -CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1 -CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE -CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE -CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0 -CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1 -CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE -CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE -CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0 -CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1 -CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE -CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE -CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0 -CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1 -CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE -CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE -CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0 -CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1 -CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE -CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE -CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0 -CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1 -CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE -CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE -CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0 -CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1 -CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE -CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE -CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0 -CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1 -CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE -CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE -CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0 -CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1 -CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE -CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE -CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0 -CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1 -CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE -CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE -CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0 -CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1 -CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE -CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE -CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0 -CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1 -CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE -CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE -CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0 -CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1 -CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE -CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE -CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0 -CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1 -CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE -CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE -CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0 -CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1 -CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE -CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE -CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0 -CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1 -CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE -CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE -CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0 -CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1 -CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE -CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE -CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0 -CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1 -CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE -CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE -CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0 -CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1 -CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE -CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE -CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0 -CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1 -CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE -CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE -CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0 -CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1 -CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE -CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE -CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0 -CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1 -CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE -CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE -CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0 -CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1 -CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE -CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE -CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0 -CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1 -CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE -CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE -CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0 -CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1 -CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE -CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE -CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0 -CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1 -CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE -CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE -CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0 -CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1 -CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE -CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE -CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0 -CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1 -CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE -CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE -CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0 -CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1 -CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE -CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE -CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0 -CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1 -CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE -CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE -CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0 -CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1 -CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE -CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE -CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0 -CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1 -CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE -CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE -CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0 -CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1 -CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE -CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE -CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0 -CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1 -CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE -CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE -CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0 -CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1 -CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE -CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE -CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0 -CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1 -CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE -CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE -CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0 -CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1 -CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE -CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE -CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0 -CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1 -CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE -CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE -CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0 -CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1 -CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE -CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE -CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0 -CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1 -CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE -CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE -CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0 -CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1 -CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE -CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE -CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0 -CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1 -CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE -CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE -CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0 -CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1 -CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE -CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE -CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0 -CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1 -CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE -CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE -CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0 -CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1 -CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE -CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE -CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0 -CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1 -CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE -CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE -CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0 -CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1 -CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE -CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE -CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0 -CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1 -CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE -CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE -CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0 -CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1 -CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE -CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE -CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0 -CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1 -CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE -CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE -CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0 -CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1 -CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE -CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE -CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0 -CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1 -CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE -CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE -CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0 -CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1 -CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE -CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE -CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0 -CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1 -CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE -CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE -CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0 -CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1 -CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE -CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE -CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0 -CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1 -CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE -CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE -CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0 -CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1 -CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE -CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE -CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0 -CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1 -CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE -CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE -CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0 -CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1 -CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE -CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE -CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0 -CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1 -CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE -CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE -CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0 -CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1 -CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE -CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE -CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0 -CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1 -CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE -CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE -CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0 -CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1 -CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE -CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE -CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0 -CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1 -CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE -CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE -CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0 -CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1 -CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE -CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE -CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0 -CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1 -CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE -CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE -CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0 -CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1 -CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE -CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE -CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0 -CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1 -CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE -CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE -CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0 -CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1 -CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE -CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE -CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0 -CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1 -CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE -CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE -CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0 -CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1 -CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE -CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE -CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0 -CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1 -CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE -CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE -CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0 -CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1 -CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE -CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE -CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0 -CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1 -CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE -CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE -CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0 -CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1 -CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE -CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE -CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0 -CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1 -CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE -CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE -CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0 -CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1 -CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE -CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE -CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0 -CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1 -CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE -CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE -CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0 -CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1 -CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE -CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE -CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0 -CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1 -CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE -CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE -CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0 -CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1 -CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE -CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE -CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0 -CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1 -CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE -CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE -CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0 -CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1 -CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE -CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE -CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0 -CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1 -CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE -CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE -CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0 -CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1 -CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE -CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE -CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0 -CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1 -CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE -CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE -CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0 -CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1 -CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE -CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE -CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0 -CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1 -CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE -CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE -CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0 -CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1 -CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE -CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE -CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0 -CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1 -CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE -CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE -CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0 -CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1 -CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE -CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE -CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0 -CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1 -CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE -CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 - ENDIF - IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE -CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0 -CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 - ENDIF - IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1 -CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc - ENDIF - IF :LNOT::DEF:CYDEV_EE_BASE -CYDEV_EE_BASE EQU 0x40008000 - ENDIF - IF :LNOT::DEF:CYDEV_EE_SIZE -CYDEV_EE_SIZE EQU 0x00000800 - ENDIF - IF :LNOT::DEF:CYREG_EE_DATA_MBASE -CYREG_EE_DATA_MBASE EQU 0x40008000 - ENDIF - IF :LNOT::DEF:CYREG_EE_DATA_MSIZE -CYREG_EE_DATA_MSIZE EQU 0x00000800 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_BASE -CYDEV_CAN0_BASE EQU 0x4000a000 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_SIZE -CYDEV_CAN0_SIZE EQU 0x000002a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE -CYDEV_CAN0_CSR_BASE EQU 0x4000a000 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE -CYDEV_CAN0_CSR_SIZE EQU 0x00000018 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR -CYREG_CAN0_CSR_INT_SR EQU 0x4000a000 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN -CYREG_CAN0_CSR_INT_EN EQU 0x4000a004 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR -CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR -CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_CSR_CMD -CYREG_CAN0_CSR_CMD EQU 0x4000a010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_CSR_CFG -CYREG_CAN0_CSR_CFG EQU 0x4000a014 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE -CYDEV_CAN0_TX0_BASE EQU 0x4000a020 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE -CYDEV_CAN0_TX0_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX0_CMD -CYREG_CAN0_TX0_CMD EQU 0x4000a020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX0_ID -CYREG_CAN0_TX0_ID EQU 0x4000a024 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX0_DH -CYREG_CAN0_TX0_DH EQU 0x4000a028 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX0_DL -CYREG_CAN0_TX0_DL EQU 0x4000a02c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE -CYDEV_CAN0_TX1_BASE EQU 0x4000a030 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE -CYDEV_CAN0_TX1_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX1_CMD -CYREG_CAN0_TX1_CMD EQU 0x4000a030 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX1_ID -CYREG_CAN0_TX1_ID EQU 0x4000a034 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX1_DH -CYREG_CAN0_TX1_DH EQU 0x4000a038 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX1_DL -CYREG_CAN0_TX1_DL EQU 0x4000a03c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE -CYDEV_CAN0_TX2_BASE EQU 0x4000a040 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE -CYDEV_CAN0_TX2_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX2_CMD -CYREG_CAN0_TX2_CMD EQU 0x4000a040 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX2_ID -CYREG_CAN0_TX2_ID EQU 0x4000a044 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX2_DH -CYREG_CAN0_TX2_DH EQU 0x4000a048 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX2_DL -CYREG_CAN0_TX2_DL EQU 0x4000a04c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE -CYDEV_CAN0_TX3_BASE EQU 0x4000a050 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE -CYDEV_CAN0_TX3_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX3_CMD -CYREG_CAN0_TX3_CMD EQU 0x4000a050 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX3_ID -CYREG_CAN0_TX3_ID EQU 0x4000a054 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX3_DH -CYREG_CAN0_TX3_DH EQU 0x4000a058 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX3_DL -CYREG_CAN0_TX3_DL EQU 0x4000a05c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE -CYDEV_CAN0_TX4_BASE EQU 0x4000a060 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE -CYDEV_CAN0_TX4_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX4_CMD -CYREG_CAN0_TX4_CMD EQU 0x4000a060 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX4_ID -CYREG_CAN0_TX4_ID EQU 0x4000a064 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX4_DH -CYREG_CAN0_TX4_DH EQU 0x4000a068 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX4_DL -CYREG_CAN0_TX4_DL EQU 0x4000a06c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE -CYDEV_CAN0_TX5_BASE EQU 0x4000a070 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE -CYDEV_CAN0_TX5_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX5_CMD -CYREG_CAN0_TX5_CMD EQU 0x4000a070 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX5_ID -CYREG_CAN0_TX5_ID EQU 0x4000a074 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX5_DH -CYREG_CAN0_TX5_DH EQU 0x4000a078 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX5_DL -CYREG_CAN0_TX5_DL EQU 0x4000a07c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE -CYDEV_CAN0_TX6_BASE EQU 0x4000a080 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE -CYDEV_CAN0_TX6_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX6_CMD -CYREG_CAN0_TX6_CMD EQU 0x4000a080 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX6_ID -CYREG_CAN0_TX6_ID EQU 0x4000a084 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX6_DH -CYREG_CAN0_TX6_DH EQU 0x4000a088 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX6_DL -CYREG_CAN0_TX6_DL EQU 0x4000a08c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE -CYDEV_CAN0_TX7_BASE EQU 0x4000a090 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE -CYDEV_CAN0_TX7_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX7_CMD -CYREG_CAN0_TX7_CMD EQU 0x4000a090 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX7_ID -CYREG_CAN0_TX7_ID EQU 0x4000a094 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX7_DH -CYREG_CAN0_TX7_DH EQU 0x4000a098 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_TX7_DL -CYREG_CAN0_TX7_DL EQU 0x4000a09c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE -CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE -CYDEV_CAN0_RX0_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_CMD -CYREG_CAN0_RX0_CMD EQU 0x4000a0a0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_ID -CYREG_CAN0_RX0_ID EQU 0x4000a0a4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_DH -CYREG_CAN0_RX0_DH EQU 0x4000a0a8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_DL -CYREG_CAN0_RX0_DL EQU 0x4000a0ac - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_AMR -CYREG_CAN0_RX0_AMR EQU 0x4000a0b0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_ACR -CYREG_CAN0_RX0_ACR EQU 0x4000a0b4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD -CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD -CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE -CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE -CYDEV_CAN0_RX1_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_CMD -CYREG_CAN0_RX1_CMD EQU 0x4000a0c0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_ID -CYREG_CAN0_RX1_ID EQU 0x4000a0c4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_DH -CYREG_CAN0_RX1_DH EQU 0x4000a0c8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_DL -CYREG_CAN0_RX1_DL EQU 0x4000a0cc - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_AMR -CYREG_CAN0_RX1_AMR EQU 0x4000a0d0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_ACR -CYREG_CAN0_RX1_ACR EQU 0x4000a0d4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD -CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD -CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE -CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE -CYDEV_CAN0_RX2_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_CMD -CYREG_CAN0_RX2_CMD EQU 0x4000a0e0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_ID -CYREG_CAN0_RX2_ID EQU 0x4000a0e4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_DH -CYREG_CAN0_RX2_DH EQU 0x4000a0e8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_DL -CYREG_CAN0_RX2_DL EQU 0x4000a0ec - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_AMR -CYREG_CAN0_RX2_AMR EQU 0x4000a0f0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_ACR -CYREG_CAN0_RX2_ACR EQU 0x4000a0f4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD -CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD -CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE -CYDEV_CAN0_RX3_BASE EQU 0x4000a100 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE -CYDEV_CAN0_RX3_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_CMD -CYREG_CAN0_RX3_CMD EQU 0x4000a100 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_ID -CYREG_CAN0_RX3_ID EQU 0x4000a104 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_DH -CYREG_CAN0_RX3_DH EQU 0x4000a108 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_DL -CYREG_CAN0_RX3_DL EQU 0x4000a10c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_AMR -CYREG_CAN0_RX3_AMR EQU 0x4000a110 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_ACR -CYREG_CAN0_RX3_ACR EQU 0x4000a114 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD -CYREG_CAN0_RX3_AMRD EQU 0x4000a118 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD -CYREG_CAN0_RX3_ACRD EQU 0x4000a11c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE -CYDEV_CAN0_RX4_BASE EQU 0x4000a120 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE -CYDEV_CAN0_RX4_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_CMD -CYREG_CAN0_RX4_CMD EQU 0x4000a120 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_ID -CYREG_CAN0_RX4_ID EQU 0x4000a124 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_DH -CYREG_CAN0_RX4_DH EQU 0x4000a128 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_DL -CYREG_CAN0_RX4_DL EQU 0x4000a12c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_AMR -CYREG_CAN0_RX4_AMR EQU 0x4000a130 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_ACR -CYREG_CAN0_RX4_ACR EQU 0x4000a134 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD -CYREG_CAN0_RX4_AMRD EQU 0x4000a138 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD -CYREG_CAN0_RX4_ACRD EQU 0x4000a13c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE -CYDEV_CAN0_RX5_BASE EQU 0x4000a140 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE -CYDEV_CAN0_RX5_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_CMD -CYREG_CAN0_RX5_CMD EQU 0x4000a140 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_ID -CYREG_CAN0_RX5_ID EQU 0x4000a144 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_DH -CYREG_CAN0_RX5_DH EQU 0x4000a148 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_DL -CYREG_CAN0_RX5_DL EQU 0x4000a14c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_AMR -CYREG_CAN0_RX5_AMR EQU 0x4000a150 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_ACR -CYREG_CAN0_RX5_ACR EQU 0x4000a154 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD -CYREG_CAN0_RX5_AMRD EQU 0x4000a158 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD -CYREG_CAN0_RX5_ACRD EQU 0x4000a15c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE -CYDEV_CAN0_RX6_BASE EQU 0x4000a160 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE -CYDEV_CAN0_RX6_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_CMD -CYREG_CAN0_RX6_CMD EQU 0x4000a160 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_ID -CYREG_CAN0_RX6_ID EQU 0x4000a164 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_DH -CYREG_CAN0_RX6_DH EQU 0x4000a168 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_DL -CYREG_CAN0_RX6_DL EQU 0x4000a16c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_AMR -CYREG_CAN0_RX6_AMR EQU 0x4000a170 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_ACR -CYREG_CAN0_RX6_ACR EQU 0x4000a174 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD -CYREG_CAN0_RX6_AMRD EQU 0x4000a178 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD -CYREG_CAN0_RX6_ACRD EQU 0x4000a17c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE -CYDEV_CAN0_RX7_BASE EQU 0x4000a180 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE -CYDEV_CAN0_RX7_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_CMD -CYREG_CAN0_RX7_CMD EQU 0x4000a180 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_ID -CYREG_CAN0_RX7_ID EQU 0x4000a184 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_DH -CYREG_CAN0_RX7_DH EQU 0x4000a188 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_DL -CYREG_CAN0_RX7_DL EQU 0x4000a18c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_AMR -CYREG_CAN0_RX7_AMR EQU 0x4000a190 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_ACR -CYREG_CAN0_RX7_ACR EQU 0x4000a194 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD -CYREG_CAN0_RX7_AMRD EQU 0x4000a198 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD -CYREG_CAN0_RX7_ACRD EQU 0x4000a19c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE -CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE -CYDEV_CAN0_RX8_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_CMD -CYREG_CAN0_RX8_CMD EQU 0x4000a1a0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_ID -CYREG_CAN0_RX8_ID EQU 0x4000a1a4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_DH -CYREG_CAN0_RX8_DH EQU 0x4000a1a8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_DL -CYREG_CAN0_RX8_DL EQU 0x4000a1ac - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_AMR -CYREG_CAN0_RX8_AMR EQU 0x4000a1b0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_ACR -CYREG_CAN0_RX8_ACR EQU 0x4000a1b4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD -CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD -CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE -CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE -CYDEV_CAN0_RX9_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_CMD -CYREG_CAN0_RX9_CMD EQU 0x4000a1c0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_ID -CYREG_CAN0_RX9_ID EQU 0x4000a1c4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_DH -CYREG_CAN0_RX9_DH EQU 0x4000a1c8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_DL -CYREG_CAN0_RX9_DL EQU 0x4000a1cc - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_AMR -CYREG_CAN0_RX9_AMR EQU 0x4000a1d0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_ACR -CYREG_CAN0_RX9_ACR EQU 0x4000a1d4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD -CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD -CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE -CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE -CYDEV_CAN0_RX10_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_CMD -CYREG_CAN0_RX10_CMD EQU 0x4000a1e0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_ID -CYREG_CAN0_RX10_ID EQU 0x4000a1e4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_DH -CYREG_CAN0_RX10_DH EQU 0x4000a1e8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_DL -CYREG_CAN0_RX10_DL EQU 0x4000a1ec - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_AMR -CYREG_CAN0_RX10_AMR EQU 0x4000a1f0 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_ACR -CYREG_CAN0_RX10_ACR EQU 0x4000a1f4 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD -CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD -CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE -CYDEV_CAN0_RX11_BASE EQU 0x4000a200 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE -CYDEV_CAN0_RX11_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_CMD -CYREG_CAN0_RX11_CMD EQU 0x4000a200 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_ID -CYREG_CAN0_RX11_ID EQU 0x4000a204 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_DH -CYREG_CAN0_RX11_DH EQU 0x4000a208 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_DL -CYREG_CAN0_RX11_DL EQU 0x4000a20c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_AMR -CYREG_CAN0_RX11_AMR EQU 0x4000a210 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_ACR -CYREG_CAN0_RX11_ACR EQU 0x4000a214 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD -CYREG_CAN0_RX11_AMRD EQU 0x4000a218 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD -CYREG_CAN0_RX11_ACRD EQU 0x4000a21c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE -CYDEV_CAN0_RX12_BASE EQU 0x4000a220 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE -CYDEV_CAN0_RX12_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_CMD -CYREG_CAN0_RX12_CMD EQU 0x4000a220 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_ID -CYREG_CAN0_RX12_ID EQU 0x4000a224 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_DH -CYREG_CAN0_RX12_DH EQU 0x4000a228 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_DL -CYREG_CAN0_RX12_DL EQU 0x4000a22c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_AMR -CYREG_CAN0_RX12_AMR EQU 0x4000a230 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_ACR -CYREG_CAN0_RX12_ACR EQU 0x4000a234 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD -CYREG_CAN0_RX12_AMRD EQU 0x4000a238 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD -CYREG_CAN0_RX12_ACRD EQU 0x4000a23c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE -CYDEV_CAN0_RX13_BASE EQU 0x4000a240 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE -CYDEV_CAN0_RX13_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_CMD -CYREG_CAN0_RX13_CMD EQU 0x4000a240 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_ID -CYREG_CAN0_RX13_ID EQU 0x4000a244 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_DH -CYREG_CAN0_RX13_DH EQU 0x4000a248 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_DL -CYREG_CAN0_RX13_DL EQU 0x4000a24c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_AMR -CYREG_CAN0_RX13_AMR EQU 0x4000a250 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_ACR -CYREG_CAN0_RX13_ACR EQU 0x4000a254 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD -CYREG_CAN0_RX13_AMRD EQU 0x4000a258 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD -CYREG_CAN0_RX13_ACRD EQU 0x4000a25c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE -CYDEV_CAN0_RX14_BASE EQU 0x4000a260 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE -CYDEV_CAN0_RX14_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_CMD -CYREG_CAN0_RX14_CMD EQU 0x4000a260 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_ID -CYREG_CAN0_RX14_ID EQU 0x4000a264 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_DH -CYREG_CAN0_RX14_DH EQU 0x4000a268 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_DL -CYREG_CAN0_RX14_DL EQU 0x4000a26c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_AMR -CYREG_CAN0_RX14_AMR EQU 0x4000a270 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_ACR -CYREG_CAN0_RX14_ACR EQU 0x4000a274 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD -CYREG_CAN0_RX14_AMRD EQU 0x4000a278 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD -CYREG_CAN0_RX14_ACRD EQU 0x4000a27c - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE -CYDEV_CAN0_RX15_BASE EQU 0x4000a280 - ENDIF - IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE -CYDEV_CAN0_RX15_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_CMD -CYREG_CAN0_RX15_CMD EQU 0x4000a280 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_ID -CYREG_CAN0_RX15_ID EQU 0x4000a284 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_DH -CYREG_CAN0_RX15_DH EQU 0x4000a288 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_DL -CYREG_CAN0_RX15_DL EQU 0x4000a28c - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_AMR -CYREG_CAN0_RX15_AMR EQU 0x4000a290 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_ACR -CYREG_CAN0_RX15_ACR EQU 0x4000a294 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD -CYREG_CAN0_RX15_AMRD EQU 0x4000a298 - ENDIF - IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD -CYREG_CAN0_RX15_ACRD EQU 0x4000a29c - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_BASE -CYDEV_DFB0_BASE EQU 0x4000c000 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_SIZE -CYDEV_DFB0_SIZE EQU 0x000007b5 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE -CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE -CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE -CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE -CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE -CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE -CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE -CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE -CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE -CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE -CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE -CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE -CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE -CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE -CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE -CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE -CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE -CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE -CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE -CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE -CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE -CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 - ENDIF - IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE -CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE -CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE -CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_CR -CYREG_DFB0_CR EQU 0x4000c780 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_SR -CYREG_DFB0_SR EQU 0x4000c784 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_RAM_EN -CYREG_DFB0_RAM_EN EQU 0x4000c788 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_RAM_DIR -CYREG_DFB0_RAM_DIR EQU 0x4000c78c - ENDIF - IF :LNOT::DEF:CYREG_DFB0_SEMA -CYREG_DFB0_SEMA EQU 0x4000c790 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL -CYREG_DFB0_DSI_CTRL EQU 0x4000c794 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_INT_CTRL -CYREG_DFB0_INT_CTRL EQU 0x4000c798 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL -CYREG_DFB0_DMA_CTRL EQU 0x4000c79c - ENDIF - IF :LNOT::DEF:CYREG_DFB0_STAGEA -CYREG_DFB0_STAGEA EQU 0x4000c7a0 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_STAGEAM -CYREG_DFB0_STAGEAM EQU 0x4000c7a1 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_STAGEAH -CYREG_DFB0_STAGEAH EQU 0x4000c7a2 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_STAGEB -CYREG_DFB0_STAGEB EQU 0x4000c7a4 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_STAGEBM -CYREG_DFB0_STAGEBM EQU 0x4000c7a5 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_STAGEBH -CYREG_DFB0_STAGEBH EQU 0x4000c7a6 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDA -CYREG_DFB0_HOLDA EQU 0x4000c7a8 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDAM -CYREG_DFB0_HOLDAM EQU 0x4000c7a9 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDAH -CYREG_DFB0_HOLDAH EQU 0x4000c7aa - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDAS -CYREG_DFB0_HOLDAS EQU 0x4000c7ab - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDB -CYREG_DFB0_HOLDB EQU 0x4000c7ac - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDBM -CYREG_DFB0_HOLDBM EQU 0x4000c7ad - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDBH -CYREG_DFB0_HOLDBH EQU 0x4000c7ae - ENDIF - IF :LNOT::DEF:CYREG_DFB0_HOLDBS -CYREG_DFB0_HOLDBS EQU 0x4000c7af - ENDIF - IF :LNOT::DEF:CYREG_DFB0_COHER -CYREG_DFB0_COHER EQU 0x4000c7b0 - ENDIF - IF :LNOT::DEF:CYREG_DFB0_DALIGN -CYREG_DFB0_DALIGN EQU 0x4000c7b4 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BASE -CYDEV_UCFG_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_SIZE -CYDEV_UCFG_SIZE EQU 0x00005040 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_BASE -CYDEV_UCFG_B0_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE -CYDEV_UCFG_B0_SIZE EQU 0x00000fef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE -CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE -CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE -CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE -CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0 -CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1 -CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2 -CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3 -CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4 -CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5 -CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6 -CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7 -CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8 -CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9 -CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10 -CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11 -CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0 -CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1 -CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2 -CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3 -CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST -CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB -CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET -CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS -CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0 -CYREG_B0_P0_U0_CFG0 EQU 0x40010040 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1 -CYREG_B0_P0_U0_CFG1 EQU 0x40010041 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2 -CYREG_B0_P0_U0_CFG2 EQU 0x40010042 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3 -CYREG_B0_P0_U0_CFG3 EQU 0x40010043 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4 -CYREG_B0_P0_U0_CFG4 EQU 0x40010044 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5 -CYREG_B0_P0_U0_CFG5 EQU 0x40010045 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6 -CYREG_B0_P0_U0_CFG6 EQU 0x40010046 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7 -CYREG_B0_P0_U0_CFG7 EQU 0x40010047 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8 -CYREG_B0_P0_U0_CFG8 EQU 0x40010048 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9 -CYREG_B0_P0_U0_CFG9 EQU 0x40010049 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10 -CYREG_B0_P0_U0_CFG10 EQU 0x4001004a - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11 -CYREG_B0_P0_U0_CFG11 EQU 0x4001004b - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12 -CYREG_B0_P0_U0_CFG12 EQU 0x4001004c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13 -CYREG_B0_P0_U0_CFG13 EQU 0x4001004d - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14 -CYREG_B0_P0_U0_CFG14 EQU 0x4001004e - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15 -CYREG_B0_P0_U0_CFG15 EQU 0x4001004f - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16 -CYREG_B0_P0_U0_CFG16 EQU 0x40010050 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17 -CYREG_B0_P0_U0_CFG17 EQU 0x40010051 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18 -CYREG_B0_P0_U0_CFG18 EQU 0x40010052 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19 -CYREG_B0_P0_U0_CFG19 EQU 0x40010053 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20 -CYREG_B0_P0_U0_CFG20 EQU 0x40010054 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21 -CYREG_B0_P0_U0_CFG21 EQU 0x40010055 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22 -CYREG_B0_P0_U0_CFG22 EQU 0x40010056 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23 -CYREG_B0_P0_U0_CFG23 EQU 0x40010057 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24 -CYREG_B0_P0_U0_CFG24 EQU 0x40010058 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25 -CYREG_B0_P0_U0_CFG25 EQU 0x40010059 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26 -CYREG_B0_P0_U0_CFG26 EQU 0x4001005a - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27 -CYREG_B0_P0_U0_CFG27 EQU 0x4001005b - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28 -CYREG_B0_P0_U0_CFG28 EQU 0x4001005c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29 -CYREG_B0_P0_U0_CFG29 EQU 0x4001005d - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30 -CYREG_B0_P0_U0_CFG30 EQU 0x4001005e - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31 -CYREG_B0_P0_U0_CFG31 EQU 0x4001005f - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0 -CYREG_B0_P0_U0_DCFG0 EQU 0x40010060 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1 -CYREG_B0_P0_U0_DCFG1 EQU 0x40010062 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2 -CYREG_B0_P0_U0_DCFG2 EQU 0x40010064 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3 -CYREG_B0_P0_U0_DCFG3 EQU 0x40010066 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4 -CYREG_B0_P0_U0_DCFG4 EQU 0x40010068 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5 -CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6 -CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7 -CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE -CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE -CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0 -CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1 -CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2 -CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3 -CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4 -CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5 -CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6 -CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7 -CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8 -CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9 -CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10 -CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11 -CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0 -CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1 -CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2 -CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3 -CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST -CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB -CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET -CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS -CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0 -CYREG_B0_P0_U1_CFG0 EQU 0x400100c0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1 -CYREG_B0_P0_U1_CFG1 EQU 0x400100c1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2 -CYREG_B0_P0_U1_CFG2 EQU 0x400100c2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3 -CYREG_B0_P0_U1_CFG3 EQU 0x400100c3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4 -CYREG_B0_P0_U1_CFG4 EQU 0x400100c4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5 -CYREG_B0_P0_U1_CFG5 EQU 0x400100c5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6 -CYREG_B0_P0_U1_CFG6 EQU 0x400100c6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7 -CYREG_B0_P0_U1_CFG7 EQU 0x400100c7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8 -CYREG_B0_P0_U1_CFG8 EQU 0x400100c8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9 -CYREG_B0_P0_U1_CFG9 EQU 0x400100c9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10 -CYREG_B0_P0_U1_CFG10 EQU 0x400100ca - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11 -CYREG_B0_P0_U1_CFG11 EQU 0x400100cb - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12 -CYREG_B0_P0_U1_CFG12 EQU 0x400100cc - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13 -CYREG_B0_P0_U1_CFG13 EQU 0x400100cd - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14 -CYREG_B0_P0_U1_CFG14 EQU 0x400100ce - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15 -CYREG_B0_P0_U1_CFG15 EQU 0x400100cf - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16 -CYREG_B0_P0_U1_CFG16 EQU 0x400100d0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17 -CYREG_B0_P0_U1_CFG17 EQU 0x400100d1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18 -CYREG_B0_P0_U1_CFG18 EQU 0x400100d2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19 -CYREG_B0_P0_U1_CFG19 EQU 0x400100d3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20 -CYREG_B0_P0_U1_CFG20 EQU 0x400100d4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21 -CYREG_B0_P0_U1_CFG21 EQU 0x400100d5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22 -CYREG_B0_P0_U1_CFG22 EQU 0x400100d6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23 -CYREG_B0_P0_U1_CFG23 EQU 0x400100d7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24 -CYREG_B0_P0_U1_CFG24 EQU 0x400100d8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25 -CYREG_B0_P0_U1_CFG25 EQU 0x400100d9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26 -CYREG_B0_P0_U1_CFG26 EQU 0x400100da - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27 -CYREG_B0_P0_U1_CFG27 EQU 0x400100db - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28 -CYREG_B0_P0_U1_CFG28 EQU 0x400100dc - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29 -CYREG_B0_P0_U1_CFG29 EQU 0x400100dd - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30 -CYREG_B0_P0_U1_CFG30 EQU 0x400100de - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31 -CYREG_B0_P0_U1_CFG31 EQU 0x400100df - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0 -CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1 -CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2 -CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3 -CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4 -CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5 -CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6 -CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec - ENDIF - IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7 -CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE -CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE -CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE -CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE -CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE -CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE -CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0 -CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1 -CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2 -CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3 -CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4 -CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5 -CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6 -CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7 -CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8 -CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9 -CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10 -CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11 -CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0 -CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1 -CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2 -CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3 -CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST -CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB -CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET -CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS -CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0 -CYREG_B0_P1_U0_CFG0 EQU 0x40010240 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1 -CYREG_B0_P1_U0_CFG1 EQU 0x40010241 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2 -CYREG_B0_P1_U0_CFG2 EQU 0x40010242 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3 -CYREG_B0_P1_U0_CFG3 EQU 0x40010243 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4 -CYREG_B0_P1_U0_CFG4 EQU 0x40010244 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5 -CYREG_B0_P1_U0_CFG5 EQU 0x40010245 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6 -CYREG_B0_P1_U0_CFG6 EQU 0x40010246 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7 -CYREG_B0_P1_U0_CFG7 EQU 0x40010247 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8 -CYREG_B0_P1_U0_CFG8 EQU 0x40010248 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9 -CYREG_B0_P1_U0_CFG9 EQU 0x40010249 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10 -CYREG_B0_P1_U0_CFG10 EQU 0x4001024a - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11 -CYREG_B0_P1_U0_CFG11 EQU 0x4001024b - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12 -CYREG_B0_P1_U0_CFG12 EQU 0x4001024c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13 -CYREG_B0_P1_U0_CFG13 EQU 0x4001024d - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14 -CYREG_B0_P1_U0_CFG14 EQU 0x4001024e - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15 -CYREG_B0_P1_U0_CFG15 EQU 0x4001024f - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16 -CYREG_B0_P1_U0_CFG16 EQU 0x40010250 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17 -CYREG_B0_P1_U0_CFG17 EQU 0x40010251 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18 -CYREG_B0_P1_U0_CFG18 EQU 0x40010252 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19 -CYREG_B0_P1_U0_CFG19 EQU 0x40010253 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20 -CYREG_B0_P1_U0_CFG20 EQU 0x40010254 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21 -CYREG_B0_P1_U0_CFG21 EQU 0x40010255 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22 -CYREG_B0_P1_U0_CFG22 EQU 0x40010256 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23 -CYREG_B0_P1_U0_CFG23 EQU 0x40010257 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24 -CYREG_B0_P1_U0_CFG24 EQU 0x40010258 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25 -CYREG_B0_P1_U0_CFG25 EQU 0x40010259 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26 -CYREG_B0_P1_U0_CFG26 EQU 0x4001025a - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27 -CYREG_B0_P1_U0_CFG27 EQU 0x4001025b - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28 -CYREG_B0_P1_U0_CFG28 EQU 0x4001025c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29 -CYREG_B0_P1_U0_CFG29 EQU 0x4001025d - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30 -CYREG_B0_P1_U0_CFG30 EQU 0x4001025e - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31 -CYREG_B0_P1_U0_CFG31 EQU 0x4001025f - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0 -CYREG_B0_P1_U0_DCFG0 EQU 0x40010260 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1 -CYREG_B0_P1_U0_DCFG1 EQU 0x40010262 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2 -CYREG_B0_P1_U0_DCFG2 EQU 0x40010264 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3 -CYREG_B0_P1_U0_DCFG3 EQU 0x40010266 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4 -CYREG_B0_P1_U0_DCFG4 EQU 0x40010268 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5 -CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6 -CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7 -CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE -CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE -CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0 -CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1 -CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2 -CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3 -CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4 -CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5 -CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6 -CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7 -CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8 -CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9 -CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10 -CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11 -CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0 -CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1 -CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2 -CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3 -CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST -CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB -CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET -CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS -CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0 -CYREG_B0_P1_U1_CFG0 EQU 0x400102c0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1 -CYREG_B0_P1_U1_CFG1 EQU 0x400102c1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2 -CYREG_B0_P1_U1_CFG2 EQU 0x400102c2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3 -CYREG_B0_P1_U1_CFG3 EQU 0x400102c3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4 -CYREG_B0_P1_U1_CFG4 EQU 0x400102c4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5 -CYREG_B0_P1_U1_CFG5 EQU 0x400102c5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6 -CYREG_B0_P1_U1_CFG6 EQU 0x400102c6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7 -CYREG_B0_P1_U1_CFG7 EQU 0x400102c7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8 -CYREG_B0_P1_U1_CFG8 EQU 0x400102c8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9 -CYREG_B0_P1_U1_CFG9 EQU 0x400102c9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10 -CYREG_B0_P1_U1_CFG10 EQU 0x400102ca - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11 -CYREG_B0_P1_U1_CFG11 EQU 0x400102cb - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12 -CYREG_B0_P1_U1_CFG12 EQU 0x400102cc - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13 -CYREG_B0_P1_U1_CFG13 EQU 0x400102cd - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14 -CYREG_B0_P1_U1_CFG14 EQU 0x400102ce - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15 -CYREG_B0_P1_U1_CFG15 EQU 0x400102cf - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16 -CYREG_B0_P1_U1_CFG16 EQU 0x400102d0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17 -CYREG_B0_P1_U1_CFG17 EQU 0x400102d1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18 -CYREG_B0_P1_U1_CFG18 EQU 0x400102d2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19 -CYREG_B0_P1_U1_CFG19 EQU 0x400102d3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20 -CYREG_B0_P1_U1_CFG20 EQU 0x400102d4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21 -CYREG_B0_P1_U1_CFG21 EQU 0x400102d5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22 -CYREG_B0_P1_U1_CFG22 EQU 0x400102d6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23 -CYREG_B0_P1_U1_CFG23 EQU 0x400102d7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24 -CYREG_B0_P1_U1_CFG24 EQU 0x400102d8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25 -CYREG_B0_P1_U1_CFG25 EQU 0x400102d9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26 -CYREG_B0_P1_U1_CFG26 EQU 0x400102da - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27 -CYREG_B0_P1_U1_CFG27 EQU 0x400102db - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28 -CYREG_B0_P1_U1_CFG28 EQU 0x400102dc - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29 -CYREG_B0_P1_U1_CFG29 EQU 0x400102dd - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30 -CYREG_B0_P1_U1_CFG30 EQU 0x400102de - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31 -CYREG_B0_P1_U1_CFG31 EQU 0x400102df - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0 -CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1 -CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2 -CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3 -CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4 -CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5 -CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6 -CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec - ENDIF - IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7 -CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE -CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE -CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE -CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE -CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE -CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE -CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0 -CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1 -CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2 -CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3 -CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4 -CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5 -CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6 -CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7 -CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8 -CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9 -CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10 -CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11 -CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0 -CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1 -CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2 -CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3 -CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST -CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB -CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET -CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS -CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0 -CYREG_B0_P2_U0_CFG0 EQU 0x40010440 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1 -CYREG_B0_P2_U0_CFG1 EQU 0x40010441 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2 -CYREG_B0_P2_U0_CFG2 EQU 0x40010442 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3 -CYREG_B0_P2_U0_CFG3 EQU 0x40010443 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4 -CYREG_B0_P2_U0_CFG4 EQU 0x40010444 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5 -CYREG_B0_P2_U0_CFG5 EQU 0x40010445 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6 -CYREG_B0_P2_U0_CFG6 EQU 0x40010446 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7 -CYREG_B0_P2_U0_CFG7 EQU 0x40010447 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8 -CYREG_B0_P2_U0_CFG8 EQU 0x40010448 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9 -CYREG_B0_P2_U0_CFG9 EQU 0x40010449 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10 -CYREG_B0_P2_U0_CFG10 EQU 0x4001044a - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11 -CYREG_B0_P2_U0_CFG11 EQU 0x4001044b - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12 -CYREG_B0_P2_U0_CFG12 EQU 0x4001044c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13 -CYREG_B0_P2_U0_CFG13 EQU 0x4001044d - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14 -CYREG_B0_P2_U0_CFG14 EQU 0x4001044e - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15 -CYREG_B0_P2_U0_CFG15 EQU 0x4001044f - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16 -CYREG_B0_P2_U0_CFG16 EQU 0x40010450 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17 -CYREG_B0_P2_U0_CFG17 EQU 0x40010451 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18 -CYREG_B0_P2_U0_CFG18 EQU 0x40010452 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19 -CYREG_B0_P2_U0_CFG19 EQU 0x40010453 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20 -CYREG_B0_P2_U0_CFG20 EQU 0x40010454 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21 -CYREG_B0_P2_U0_CFG21 EQU 0x40010455 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22 -CYREG_B0_P2_U0_CFG22 EQU 0x40010456 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23 -CYREG_B0_P2_U0_CFG23 EQU 0x40010457 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24 -CYREG_B0_P2_U0_CFG24 EQU 0x40010458 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25 -CYREG_B0_P2_U0_CFG25 EQU 0x40010459 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26 -CYREG_B0_P2_U0_CFG26 EQU 0x4001045a - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27 -CYREG_B0_P2_U0_CFG27 EQU 0x4001045b - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28 -CYREG_B0_P2_U0_CFG28 EQU 0x4001045c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29 -CYREG_B0_P2_U0_CFG29 EQU 0x4001045d - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30 -CYREG_B0_P2_U0_CFG30 EQU 0x4001045e - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31 -CYREG_B0_P2_U0_CFG31 EQU 0x4001045f - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0 -CYREG_B0_P2_U0_DCFG0 EQU 0x40010460 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1 -CYREG_B0_P2_U0_DCFG1 EQU 0x40010462 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2 -CYREG_B0_P2_U0_DCFG2 EQU 0x40010464 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3 -CYREG_B0_P2_U0_DCFG3 EQU 0x40010466 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4 -CYREG_B0_P2_U0_DCFG4 EQU 0x40010468 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5 -CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6 -CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7 -CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE -CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE -CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0 -CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1 -CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2 -CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3 -CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4 -CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5 -CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6 -CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7 -CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8 -CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9 -CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10 -CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11 -CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0 -CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1 -CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2 -CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3 -CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST -CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB -CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET -CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS -CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0 -CYREG_B0_P2_U1_CFG0 EQU 0x400104c0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1 -CYREG_B0_P2_U1_CFG1 EQU 0x400104c1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2 -CYREG_B0_P2_U1_CFG2 EQU 0x400104c2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3 -CYREG_B0_P2_U1_CFG3 EQU 0x400104c3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4 -CYREG_B0_P2_U1_CFG4 EQU 0x400104c4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5 -CYREG_B0_P2_U1_CFG5 EQU 0x400104c5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6 -CYREG_B0_P2_U1_CFG6 EQU 0x400104c6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7 -CYREG_B0_P2_U1_CFG7 EQU 0x400104c7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8 -CYREG_B0_P2_U1_CFG8 EQU 0x400104c8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9 -CYREG_B0_P2_U1_CFG9 EQU 0x400104c9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10 -CYREG_B0_P2_U1_CFG10 EQU 0x400104ca - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11 -CYREG_B0_P2_U1_CFG11 EQU 0x400104cb - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12 -CYREG_B0_P2_U1_CFG12 EQU 0x400104cc - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13 -CYREG_B0_P2_U1_CFG13 EQU 0x400104cd - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14 -CYREG_B0_P2_U1_CFG14 EQU 0x400104ce - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15 -CYREG_B0_P2_U1_CFG15 EQU 0x400104cf - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16 -CYREG_B0_P2_U1_CFG16 EQU 0x400104d0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17 -CYREG_B0_P2_U1_CFG17 EQU 0x400104d1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18 -CYREG_B0_P2_U1_CFG18 EQU 0x400104d2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19 -CYREG_B0_P2_U1_CFG19 EQU 0x400104d3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20 -CYREG_B0_P2_U1_CFG20 EQU 0x400104d4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21 -CYREG_B0_P2_U1_CFG21 EQU 0x400104d5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22 -CYREG_B0_P2_U1_CFG22 EQU 0x400104d6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23 -CYREG_B0_P2_U1_CFG23 EQU 0x400104d7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24 -CYREG_B0_P2_U1_CFG24 EQU 0x400104d8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25 -CYREG_B0_P2_U1_CFG25 EQU 0x400104d9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26 -CYREG_B0_P2_U1_CFG26 EQU 0x400104da - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27 -CYREG_B0_P2_U1_CFG27 EQU 0x400104db - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28 -CYREG_B0_P2_U1_CFG28 EQU 0x400104dc - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29 -CYREG_B0_P2_U1_CFG29 EQU 0x400104dd - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30 -CYREG_B0_P2_U1_CFG30 EQU 0x400104de - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31 -CYREG_B0_P2_U1_CFG31 EQU 0x400104df - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0 -CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1 -CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2 -CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3 -CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4 -CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5 -CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6 -CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec - ENDIF - IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7 -CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE -CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE -CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE -CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE -CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE -CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE -CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0 -CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1 -CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2 -CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3 -CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4 -CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5 -CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6 -CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7 -CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8 -CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9 -CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10 -CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11 -CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0 -CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1 -CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2 -CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3 -CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST -CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB -CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET -CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS -CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0 -CYREG_B0_P3_U0_CFG0 EQU 0x40010640 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1 -CYREG_B0_P3_U0_CFG1 EQU 0x40010641 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2 -CYREG_B0_P3_U0_CFG2 EQU 0x40010642 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3 -CYREG_B0_P3_U0_CFG3 EQU 0x40010643 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4 -CYREG_B0_P3_U0_CFG4 EQU 0x40010644 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5 -CYREG_B0_P3_U0_CFG5 EQU 0x40010645 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6 -CYREG_B0_P3_U0_CFG6 EQU 0x40010646 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7 -CYREG_B0_P3_U0_CFG7 EQU 0x40010647 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8 -CYREG_B0_P3_U0_CFG8 EQU 0x40010648 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9 -CYREG_B0_P3_U0_CFG9 EQU 0x40010649 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10 -CYREG_B0_P3_U0_CFG10 EQU 0x4001064a - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11 -CYREG_B0_P3_U0_CFG11 EQU 0x4001064b - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12 -CYREG_B0_P3_U0_CFG12 EQU 0x4001064c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13 -CYREG_B0_P3_U0_CFG13 EQU 0x4001064d - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14 -CYREG_B0_P3_U0_CFG14 EQU 0x4001064e - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15 -CYREG_B0_P3_U0_CFG15 EQU 0x4001064f - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16 -CYREG_B0_P3_U0_CFG16 EQU 0x40010650 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17 -CYREG_B0_P3_U0_CFG17 EQU 0x40010651 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18 -CYREG_B0_P3_U0_CFG18 EQU 0x40010652 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19 -CYREG_B0_P3_U0_CFG19 EQU 0x40010653 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20 -CYREG_B0_P3_U0_CFG20 EQU 0x40010654 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21 -CYREG_B0_P3_U0_CFG21 EQU 0x40010655 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22 -CYREG_B0_P3_U0_CFG22 EQU 0x40010656 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23 -CYREG_B0_P3_U0_CFG23 EQU 0x40010657 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24 -CYREG_B0_P3_U0_CFG24 EQU 0x40010658 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25 -CYREG_B0_P3_U0_CFG25 EQU 0x40010659 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26 -CYREG_B0_P3_U0_CFG26 EQU 0x4001065a - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27 -CYREG_B0_P3_U0_CFG27 EQU 0x4001065b - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28 -CYREG_B0_P3_U0_CFG28 EQU 0x4001065c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29 -CYREG_B0_P3_U0_CFG29 EQU 0x4001065d - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30 -CYREG_B0_P3_U0_CFG30 EQU 0x4001065e - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31 -CYREG_B0_P3_U0_CFG31 EQU 0x4001065f - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0 -CYREG_B0_P3_U0_DCFG0 EQU 0x40010660 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1 -CYREG_B0_P3_U0_DCFG1 EQU 0x40010662 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2 -CYREG_B0_P3_U0_DCFG2 EQU 0x40010664 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3 -CYREG_B0_P3_U0_DCFG3 EQU 0x40010666 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4 -CYREG_B0_P3_U0_DCFG4 EQU 0x40010668 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5 -CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6 -CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7 -CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE -CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE -CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0 -CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1 -CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2 -CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3 -CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4 -CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5 -CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6 -CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7 -CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8 -CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9 -CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10 -CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11 -CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0 -CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1 -CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2 -CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3 -CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST -CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB -CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET -CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS -CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0 -CYREG_B0_P3_U1_CFG0 EQU 0x400106c0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1 -CYREG_B0_P3_U1_CFG1 EQU 0x400106c1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2 -CYREG_B0_P3_U1_CFG2 EQU 0x400106c2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3 -CYREG_B0_P3_U1_CFG3 EQU 0x400106c3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4 -CYREG_B0_P3_U1_CFG4 EQU 0x400106c4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5 -CYREG_B0_P3_U1_CFG5 EQU 0x400106c5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6 -CYREG_B0_P3_U1_CFG6 EQU 0x400106c6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7 -CYREG_B0_P3_U1_CFG7 EQU 0x400106c7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8 -CYREG_B0_P3_U1_CFG8 EQU 0x400106c8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9 -CYREG_B0_P3_U1_CFG9 EQU 0x400106c9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10 -CYREG_B0_P3_U1_CFG10 EQU 0x400106ca - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11 -CYREG_B0_P3_U1_CFG11 EQU 0x400106cb - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12 -CYREG_B0_P3_U1_CFG12 EQU 0x400106cc - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13 -CYREG_B0_P3_U1_CFG13 EQU 0x400106cd - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14 -CYREG_B0_P3_U1_CFG14 EQU 0x400106ce - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15 -CYREG_B0_P3_U1_CFG15 EQU 0x400106cf - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16 -CYREG_B0_P3_U1_CFG16 EQU 0x400106d0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17 -CYREG_B0_P3_U1_CFG17 EQU 0x400106d1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18 -CYREG_B0_P3_U1_CFG18 EQU 0x400106d2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19 -CYREG_B0_P3_U1_CFG19 EQU 0x400106d3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20 -CYREG_B0_P3_U1_CFG20 EQU 0x400106d4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21 -CYREG_B0_P3_U1_CFG21 EQU 0x400106d5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22 -CYREG_B0_P3_U1_CFG22 EQU 0x400106d6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23 -CYREG_B0_P3_U1_CFG23 EQU 0x400106d7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24 -CYREG_B0_P3_U1_CFG24 EQU 0x400106d8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25 -CYREG_B0_P3_U1_CFG25 EQU 0x400106d9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26 -CYREG_B0_P3_U1_CFG26 EQU 0x400106da - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27 -CYREG_B0_P3_U1_CFG27 EQU 0x400106db - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28 -CYREG_B0_P3_U1_CFG28 EQU 0x400106dc - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29 -CYREG_B0_P3_U1_CFG29 EQU 0x400106dd - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30 -CYREG_B0_P3_U1_CFG30 EQU 0x400106de - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31 -CYREG_B0_P3_U1_CFG31 EQU 0x400106df - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0 -CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1 -CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2 -CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3 -CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4 -CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5 -CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6 -CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec - ENDIF - IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7 -CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE -CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE -CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE -CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE -CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE -CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE -CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0 -CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1 -CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2 -CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3 -CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4 -CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5 -CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6 -CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7 -CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8 -CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9 -CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10 -CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11 -CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0 -CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1 -CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2 -CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3 -CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST -CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB -CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET -CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS -CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0 -CYREG_B0_P4_U0_CFG0 EQU 0x40010840 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1 -CYREG_B0_P4_U0_CFG1 EQU 0x40010841 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2 -CYREG_B0_P4_U0_CFG2 EQU 0x40010842 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3 -CYREG_B0_P4_U0_CFG3 EQU 0x40010843 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4 -CYREG_B0_P4_U0_CFG4 EQU 0x40010844 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5 -CYREG_B0_P4_U0_CFG5 EQU 0x40010845 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6 -CYREG_B0_P4_U0_CFG6 EQU 0x40010846 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7 -CYREG_B0_P4_U0_CFG7 EQU 0x40010847 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8 -CYREG_B0_P4_U0_CFG8 EQU 0x40010848 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9 -CYREG_B0_P4_U0_CFG9 EQU 0x40010849 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10 -CYREG_B0_P4_U0_CFG10 EQU 0x4001084a - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11 -CYREG_B0_P4_U0_CFG11 EQU 0x4001084b - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12 -CYREG_B0_P4_U0_CFG12 EQU 0x4001084c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13 -CYREG_B0_P4_U0_CFG13 EQU 0x4001084d - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14 -CYREG_B0_P4_U0_CFG14 EQU 0x4001084e - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15 -CYREG_B0_P4_U0_CFG15 EQU 0x4001084f - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16 -CYREG_B0_P4_U0_CFG16 EQU 0x40010850 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17 -CYREG_B0_P4_U0_CFG17 EQU 0x40010851 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18 -CYREG_B0_P4_U0_CFG18 EQU 0x40010852 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19 -CYREG_B0_P4_U0_CFG19 EQU 0x40010853 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20 -CYREG_B0_P4_U0_CFG20 EQU 0x40010854 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21 -CYREG_B0_P4_U0_CFG21 EQU 0x40010855 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22 -CYREG_B0_P4_U0_CFG22 EQU 0x40010856 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23 -CYREG_B0_P4_U0_CFG23 EQU 0x40010857 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24 -CYREG_B0_P4_U0_CFG24 EQU 0x40010858 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25 -CYREG_B0_P4_U0_CFG25 EQU 0x40010859 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26 -CYREG_B0_P4_U0_CFG26 EQU 0x4001085a - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27 -CYREG_B0_P4_U0_CFG27 EQU 0x4001085b - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28 -CYREG_B0_P4_U0_CFG28 EQU 0x4001085c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29 -CYREG_B0_P4_U0_CFG29 EQU 0x4001085d - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30 -CYREG_B0_P4_U0_CFG30 EQU 0x4001085e - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31 -CYREG_B0_P4_U0_CFG31 EQU 0x4001085f - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0 -CYREG_B0_P4_U0_DCFG0 EQU 0x40010860 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1 -CYREG_B0_P4_U0_DCFG1 EQU 0x40010862 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2 -CYREG_B0_P4_U0_DCFG2 EQU 0x40010864 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3 -CYREG_B0_P4_U0_DCFG3 EQU 0x40010866 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4 -CYREG_B0_P4_U0_DCFG4 EQU 0x40010868 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5 -CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6 -CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7 -CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE -CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE -CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0 -CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1 -CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2 -CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3 -CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4 -CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5 -CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6 -CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7 -CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8 -CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9 -CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10 -CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11 -CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0 -CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1 -CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2 -CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3 -CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST -CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB -CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET -CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS -CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0 -CYREG_B0_P4_U1_CFG0 EQU 0x400108c0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1 -CYREG_B0_P4_U1_CFG1 EQU 0x400108c1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2 -CYREG_B0_P4_U1_CFG2 EQU 0x400108c2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3 -CYREG_B0_P4_U1_CFG3 EQU 0x400108c3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4 -CYREG_B0_P4_U1_CFG4 EQU 0x400108c4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5 -CYREG_B0_P4_U1_CFG5 EQU 0x400108c5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6 -CYREG_B0_P4_U1_CFG6 EQU 0x400108c6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7 -CYREG_B0_P4_U1_CFG7 EQU 0x400108c7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8 -CYREG_B0_P4_U1_CFG8 EQU 0x400108c8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9 -CYREG_B0_P4_U1_CFG9 EQU 0x400108c9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10 -CYREG_B0_P4_U1_CFG10 EQU 0x400108ca - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11 -CYREG_B0_P4_U1_CFG11 EQU 0x400108cb - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12 -CYREG_B0_P4_U1_CFG12 EQU 0x400108cc - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13 -CYREG_B0_P4_U1_CFG13 EQU 0x400108cd - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14 -CYREG_B0_P4_U1_CFG14 EQU 0x400108ce - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15 -CYREG_B0_P4_U1_CFG15 EQU 0x400108cf - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16 -CYREG_B0_P4_U1_CFG16 EQU 0x400108d0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17 -CYREG_B0_P4_U1_CFG17 EQU 0x400108d1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18 -CYREG_B0_P4_U1_CFG18 EQU 0x400108d2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19 -CYREG_B0_P4_U1_CFG19 EQU 0x400108d3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20 -CYREG_B0_P4_U1_CFG20 EQU 0x400108d4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21 -CYREG_B0_P4_U1_CFG21 EQU 0x400108d5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22 -CYREG_B0_P4_U1_CFG22 EQU 0x400108d6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23 -CYREG_B0_P4_U1_CFG23 EQU 0x400108d7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24 -CYREG_B0_P4_U1_CFG24 EQU 0x400108d8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25 -CYREG_B0_P4_U1_CFG25 EQU 0x400108d9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26 -CYREG_B0_P4_U1_CFG26 EQU 0x400108da - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27 -CYREG_B0_P4_U1_CFG27 EQU 0x400108db - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28 -CYREG_B0_P4_U1_CFG28 EQU 0x400108dc - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29 -CYREG_B0_P4_U1_CFG29 EQU 0x400108dd - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30 -CYREG_B0_P4_U1_CFG30 EQU 0x400108de - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31 -CYREG_B0_P4_U1_CFG31 EQU 0x400108df - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0 -CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1 -CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2 -CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3 -CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4 -CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5 -CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6 -CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec - ENDIF - IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7 -CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE -CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE -CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE -CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE -CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE -CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE -CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0 -CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1 -CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2 -CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3 -CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4 -CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5 -CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6 -CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7 -CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8 -CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9 -CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10 -CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11 -CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0 -CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1 -CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2 -CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3 -CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST -CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB -CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET -CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS -CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0 -CYREG_B0_P5_U0_CFG0 EQU 0x40010a40 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1 -CYREG_B0_P5_U0_CFG1 EQU 0x40010a41 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2 -CYREG_B0_P5_U0_CFG2 EQU 0x40010a42 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3 -CYREG_B0_P5_U0_CFG3 EQU 0x40010a43 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4 -CYREG_B0_P5_U0_CFG4 EQU 0x40010a44 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5 -CYREG_B0_P5_U0_CFG5 EQU 0x40010a45 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6 -CYREG_B0_P5_U0_CFG6 EQU 0x40010a46 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7 -CYREG_B0_P5_U0_CFG7 EQU 0x40010a47 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8 -CYREG_B0_P5_U0_CFG8 EQU 0x40010a48 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9 -CYREG_B0_P5_U0_CFG9 EQU 0x40010a49 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10 -CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11 -CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12 -CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13 -CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14 -CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15 -CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16 -CYREG_B0_P5_U0_CFG16 EQU 0x40010a50 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17 -CYREG_B0_P5_U0_CFG17 EQU 0x40010a51 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18 -CYREG_B0_P5_U0_CFG18 EQU 0x40010a52 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19 -CYREG_B0_P5_U0_CFG19 EQU 0x40010a53 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20 -CYREG_B0_P5_U0_CFG20 EQU 0x40010a54 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21 -CYREG_B0_P5_U0_CFG21 EQU 0x40010a55 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22 -CYREG_B0_P5_U0_CFG22 EQU 0x40010a56 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23 -CYREG_B0_P5_U0_CFG23 EQU 0x40010a57 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24 -CYREG_B0_P5_U0_CFG24 EQU 0x40010a58 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25 -CYREG_B0_P5_U0_CFG25 EQU 0x40010a59 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26 -CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27 -CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28 -CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29 -CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30 -CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31 -CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0 -CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1 -CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2 -CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3 -CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4 -CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5 -CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6 -CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7 -CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE -CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE -CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0 -CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1 -CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2 -CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3 -CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4 -CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5 -CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6 -CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7 -CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8 -CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9 -CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10 -CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11 -CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0 -CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1 -CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2 -CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3 -CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST -CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB -CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET -CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS -CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0 -CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1 -CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2 -CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3 -CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4 -CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5 -CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6 -CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7 -CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8 -CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9 -CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10 -CYREG_B0_P5_U1_CFG10 EQU 0x40010aca - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11 -CYREG_B0_P5_U1_CFG11 EQU 0x40010acb - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12 -CYREG_B0_P5_U1_CFG12 EQU 0x40010acc - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13 -CYREG_B0_P5_U1_CFG13 EQU 0x40010acd - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14 -CYREG_B0_P5_U1_CFG14 EQU 0x40010ace - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15 -CYREG_B0_P5_U1_CFG15 EQU 0x40010acf - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16 -CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17 -CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18 -CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19 -CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20 -CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21 -CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22 -CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23 -CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24 -CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25 -CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26 -CYREG_B0_P5_U1_CFG26 EQU 0x40010ada - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27 -CYREG_B0_P5_U1_CFG27 EQU 0x40010adb - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28 -CYREG_B0_P5_U1_CFG28 EQU 0x40010adc - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29 -CYREG_B0_P5_U1_CFG29 EQU 0x40010add - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30 -CYREG_B0_P5_U1_CFG30 EQU 0x40010ade - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31 -CYREG_B0_P5_U1_CFG31 EQU 0x40010adf - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0 -CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1 -CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2 -CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3 -CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4 -CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5 -CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6 -CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec - ENDIF - IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7 -CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE -CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE -CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE -CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE -CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE -CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE -CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0 -CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1 -CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2 -CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3 -CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4 -CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5 -CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6 -CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7 -CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8 -CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9 -CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10 -CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11 -CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0 -CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1 -CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2 -CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3 -CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST -CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB -CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET -CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS -CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0 -CYREG_B0_P6_U0_CFG0 EQU 0x40010c40 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1 -CYREG_B0_P6_U0_CFG1 EQU 0x40010c41 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2 -CYREG_B0_P6_U0_CFG2 EQU 0x40010c42 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3 -CYREG_B0_P6_U0_CFG3 EQU 0x40010c43 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4 -CYREG_B0_P6_U0_CFG4 EQU 0x40010c44 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5 -CYREG_B0_P6_U0_CFG5 EQU 0x40010c45 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6 -CYREG_B0_P6_U0_CFG6 EQU 0x40010c46 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7 -CYREG_B0_P6_U0_CFG7 EQU 0x40010c47 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8 -CYREG_B0_P6_U0_CFG8 EQU 0x40010c48 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9 -CYREG_B0_P6_U0_CFG9 EQU 0x40010c49 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10 -CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11 -CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12 -CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13 -CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14 -CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15 -CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16 -CYREG_B0_P6_U0_CFG16 EQU 0x40010c50 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17 -CYREG_B0_P6_U0_CFG17 EQU 0x40010c51 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18 -CYREG_B0_P6_U0_CFG18 EQU 0x40010c52 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19 -CYREG_B0_P6_U0_CFG19 EQU 0x40010c53 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20 -CYREG_B0_P6_U0_CFG20 EQU 0x40010c54 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21 -CYREG_B0_P6_U0_CFG21 EQU 0x40010c55 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22 -CYREG_B0_P6_U0_CFG22 EQU 0x40010c56 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23 -CYREG_B0_P6_U0_CFG23 EQU 0x40010c57 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24 -CYREG_B0_P6_U0_CFG24 EQU 0x40010c58 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25 -CYREG_B0_P6_U0_CFG25 EQU 0x40010c59 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26 -CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27 -CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28 -CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29 -CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30 -CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31 -CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0 -CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1 -CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2 -CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3 -CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4 -CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5 -CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6 -CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7 -CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE -CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE -CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0 -CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1 -CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2 -CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3 -CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4 -CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5 -CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6 -CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7 -CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8 -CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9 -CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10 -CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11 -CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0 -CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1 -CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2 -CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3 -CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST -CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB -CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET -CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS -CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0 -CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1 -CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2 -CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3 -CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4 -CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5 -CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6 -CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7 -CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8 -CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9 -CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10 -CYREG_B0_P6_U1_CFG10 EQU 0x40010cca - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11 -CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12 -CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13 -CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14 -CYREG_B0_P6_U1_CFG14 EQU 0x40010cce - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15 -CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16 -CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17 -CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18 -CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19 -CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20 -CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21 -CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22 -CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23 -CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24 -CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25 -CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26 -CYREG_B0_P6_U1_CFG26 EQU 0x40010cda - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27 -CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28 -CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29 -CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30 -CYREG_B0_P6_U1_CFG30 EQU 0x40010cde - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31 -CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0 -CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1 -CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2 -CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3 -CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4 -CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5 -CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6 -CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec - ENDIF - IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7 -CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE -CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE -CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE -CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE -CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE -CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE -CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0 -CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1 -CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2 -CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3 -CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4 -CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5 -CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6 -CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7 -CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8 -CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9 -CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10 -CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11 -CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0 -CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1 -CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2 -CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3 -CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST -CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB -CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET -CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS -CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0 -CYREG_B0_P7_U0_CFG0 EQU 0x40010e40 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1 -CYREG_B0_P7_U0_CFG1 EQU 0x40010e41 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2 -CYREG_B0_P7_U0_CFG2 EQU 0x40010e42 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3 -CYREG_B0_P7_U0_CFG3 EQU 0x40010e43 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4 -CYREG_B0_P7_U0_CFG4 EQU 0x40010e44 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5 -CYREG_B0_P7_U0_CFG5 EQU 0x40010e45 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6 -CYREG_B0_P7_U0_CFG6 EQU 0x40010e46 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7 -CYREG_B0_P7_U0_CFG7 EQU 0x40010e47 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8 -CYREG_B0_P7_U0_CFG8 EQU 0x40010e48 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9 -CYREG_B0_P7_U0_CFG9 EQU 0x40010e49 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10 -CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11 -CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12 -CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13 -CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14 -CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15 -CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16 -CYREG_B0_P7_U0_CFG16 EQU 0x40010e50 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17 -CYREG_B0_P7_U0_CFG17 EQU 0x40010e51 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18 -CYREG_B0_P7_U0_CFG18 EQU 0x40010e52 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19 -CYREG_B0_P7_U0_CFG19 EQU 0x40010e53 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20 -CYREG_B0_P7_U0_CFG20 EQU 0x40010e54 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21 -CYREG_B0_P7_U0_CFG21 EQU 0x40010e55 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22 -CYREG_B0_P7_U0_CFG22 EQU 0x40010e56 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23 -CYREG_B0_P7_U0_CFG23 EQU 0x40010e57 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24 -CYREG_B0_P7_U0_CFG24 EQU 0x40010e58 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25 -CYREG_B0_P7_U0_CFG25 EQU 0x40010e59 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26 -CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27 -CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28 -CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29 -CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30 -CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31 -CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0 -CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1 -CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2 -CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3 -CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4 -CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5 -CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6 -CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7 -CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE -CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE -CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0 -CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1 -CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2 -CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3 -CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4 -CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5 -CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6 -CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7 -CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8 -CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9 -CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10 -CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11 -CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0 -CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1 -CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2 -CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3 -CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST -CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB -CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET -CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS -CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0 -CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1 -CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2 -CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3 -CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4 -CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5 -CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6 -CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7 -CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8 -CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9 -CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10 -CYREG_B0_P7_U1_CFG10 EQU 0x40010eca - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11 -CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12 -CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13 -CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14 -CYREG_B0_P7_U1_CFG14 EQU 0x40010ece - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15 -CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16 -CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17 -CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18 -CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19 -CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20 -CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21 -CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22 -CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23 -CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24 -CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25 -CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26 -CYREG_B0_P7_U1_CFG26 EQU 0x40010eda - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27 -CYREG_B0_P7_U1_CFG27 EQU 0x40010edb - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28 -CYREG_B0_P7_U1_CFG28 EQU 0x40010edc - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29 -CYREG_B0_P7_U1_CFG29 EQU 0x40010edd - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30 -CYREG_B0_P7_U1_CFG30 EQU 0x40010ede - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31 -CYREG_B0_P7_U1_CFG31 EQU 0x40010edf - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0 -CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1 -CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2 -CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3 -CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4 -CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8 - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5 -CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6 -CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec - ENDIF - IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7 -CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE -CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE -CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_BASE -CYDEV_UCFG_B1_BASE EQU 0x40011000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE -CYDEV_UCFG_B1_SIZE EQU 0x00000fef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE -CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE -CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE -CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE -CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0 -CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1 -CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2 -CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3 -CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4 -CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5 -CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6 -CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7 -CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8 -CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9 -CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10 -CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11 -CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0 -CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1 -CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2 -CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3 -CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST -CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB -CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET -CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS -CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0 -CYREG_B1_P2_U0_CFG0 EQU 0x40011440 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1 -CYREG_B1_P2_U0_CFG1 EQU 0x40011441 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2 -CYREG_B1_P2_U0_CFG2 EQU 0x40011442 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3 -CYREG_B1_P2_U0_CFG3 EQU 0x40011443 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4 -CYREG_B1_P2_U0_CFG4 EQU 0x40011444 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5 -CYREG_B1_P2_U0_CFG5 EQU 0x40011445 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6 -CYREG_B1_P2_U0_CFG6 EQU 0x40011446 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7 -CYREG_B1_P2_U0_CFG7 EQU 0x40011447 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8 -CYREG_B1_P2_U0_CFG8 EQU 0x40011448 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9 -CYREG_B1_P2_U0_CFG9 EQU 0x40011449 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10 -CYREG_B1_P2_U0_CFG10 EQU 0x4001144a - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11 -CYREG_B1_P2_U0_CFG11 EQU 0x4001144b - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12 -CYREG_B1_P2_U0_CFG12 EQU 0x4001144c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13 -CYREG_B1_P2_U0_CFG13 EQU 0x4001144d - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14 -CYREG_B1_P2_U0_CFG14 EQU 0x4001144e - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15 -CYREG_B1_P2_U0_CFG15 EQU 0x4001144f - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16 -CYREG_B1_P2_U0_CFG16 EQU 0x40011450 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17 -CYREG_B1_P2_U0_CFG17 EQU 0x40011451 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18 -CYREG_B1_P2_U0_CFG18 EQU 0x40011452 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19 -CYREG_B1_P2_U0_CFG19 EQU 0x40011453 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20 -CYREG_B1_P2_U0_CFG20 EQU 0x40011454 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21 -CYREG_B1_P2_U0_CFG21 EQU 0x40011455 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22 -CYREG_B1_P2_U0_CFG22 EQU 0x40011456 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23 -CYREG_B1_P2_U0_CFG23 EQU 0x40011457 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24 -CYREG_B1_P2_U0_CFG24 EQU 0x40011458 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25 -CYREG_B1_P2_U0_CFG25 EQU 0x40011459 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26 -CYREG_B1_P2_U0_CFG26 EQU 0x4001145a - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27 -CYREG_B1_P2_U0_CFG27 EQU 0x4001145b - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28 -CYREG_B1_P2_U0_CFG28 EQU 0x4001145c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29 -CYREG_B1_P2_U0_CFG29 EQU 0x4001145d - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30 -CYREG_B1_P2_U0_CFG30 EQU 0x4001145e - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31 -CYREG_B1_P2_U0_CFG31 EQU 0x4001145f - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0 -CYREG_B1_P2_U0_DCFG0 EQU 0x40011460 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1 -CYREG_B1_P2_U0_DCFG1 EQU 0x40011462 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2 -CYREG_B1_P2_U0_DCFG2 EQU 0x40011464 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3 -CYREG_B1_P2_U0_DCFG3 EQU 0x40011466 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4 -CYREG_B1_P2_U0_DCFG4 EQU 0x40011468 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5 -CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6 -CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7 -CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE -CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE -CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0 -CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1 -CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2 -CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3 -CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4 -CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5 -CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6 -CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7 -CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8 -CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9 -CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10 -CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11 -CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0 -CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1 -CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2 -CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3 -CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST -CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB -CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET -CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS -CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0 -CYREG_B1_P2_U1_CFG0 EQU 0x400114c0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1 -CYREG_B1_P2_U1_CFG1 EQU 0x400114c1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2 -CYREG_B1_P2_U1_CFG2 EQU 0x400114c2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3 -CYREG_B1_P2_U1_CFG3 EQU 0x400114c3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4 -CYREG_B1_P2_U1_CFG4 EQU 0x400114c4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5 -CYREG_B1_P2_U1_CFG5 EQU 0x400114c5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6 -CYREG_B1_P2_U1_CFG6 EQU 0x400114c6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7 -CYREG_B1_P2_U1_CFG7 EQU 0x400114c7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8 -CYREG_B1_P2_U1_CFG8 EQU 0x400114c8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9 -CYREG_B1_P2_U1_CFG9 EQU 0x400114c9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10 -CYREG_B1_P2_U1_CFG10 EQU 0x400114ca - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11 -CYREG_B1_P2_U1_CFG11 EQU 0x400114cb - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12 -CYREG_B1_P2_U1_CFG12 EQU 0x400114cc - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13 -CYREG_B1_P2_U1_CFG13 EQU 0x400114cd - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14 -CYREG_B1_P2_U1_CFG14 EQU 0x400114ce - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15 -CYREG_B1_P2_U1_CFG15 EQU 0x400114cf - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16 -CYREG_B1_P2_U1_CFG16 EQU 0x400114d0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17 -CYREG_B1_P2_U1_CFG17 EQU 0x400114d1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18 -CYREG_B1_P2_U1_CFG18 EQU 0x400114d2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19 -CYREG_B1_P2_U1_CFG19 EQU 0x400114d3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20 -CYREG_B1_P2_U1_CFG20 EQU 0x400114d4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21 -CYREG_B1_P2_U1_CFG21 EQU 0x400114d5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22 -CYREG_B1_P2_U1_CFG22 EQU 0x400114d6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23 -CYREG_B1_P2_U1_CFG23 EQU 0x400114d7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24 -CYREG_B1_P2_U1_CFG24 EQU 0x400114d8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25 -CYREG_B1_P2_U1_CFG25 EQU 0x400114d9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26 -CYREG_B1_P2_U1_CFG26 EQU 0x400114da - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27 -CYREG_B1_P2_U1_CFG27 EQU 0x400114db - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28 -CYREG_B1_P2_U1_CFG28 EQU 0x400114dc - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29 -CYREG_B1_P2_U1_CFG29 EQU 0x400114dd - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30 -CYREG_B1_P2_U1_CFG30 EQU 0x400114de - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31 -CYREG_B1_P2_U1_CFG31 EQU 0x400114df - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0 -CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1 -CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2 -CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3 -CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4 -CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5 -CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6 -CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec - ENDIF - IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7 -CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE -CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE -CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE -CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE -CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE -CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE -CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0 -CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1 -CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2 -CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3 -CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4 -CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5 -CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6 -CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7 -CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8 -CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9 -CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10 -CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11 -CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0 -CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1 -CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2 -CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3 -CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST -CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB -CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET -CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS -CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0 -CYREG_B1_P3_U0_CFG0 EQU 0x40011640 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1 -CYREG_B1_P3_U0_CFG1 EQU 0x40011641 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2 -CYREG_B1_P3_U0_CFG2 EQU 0x40011642 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3 -CYREG_B1_P3_U0_CFG3 EQU 0x40011643 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4 -CYREG_B1_P3_U0_CFG4 EQU 0x40011644 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5 -CYREG_B1_P3_U0_CFG5 EQU 0x40011645 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6 -CYREG_B1_P3_U0_CFG6 EQU 0x40011646 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7 -CYREG_B1_P3_U0_CFG7 EQU 0x40011647 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8 -CYREG_B1_P3_U0_CFG8 EQU 0x40011648 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9 -CYREG_B1_P3_U0_CFG9 EQU 0x40011649 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10 -CYREG_B1_P3_U0_CFG10 EQU 0x4001164a - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11 -CYREG_B1_P3_U0_CFG11 EQU 0x4001164b - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12 -CYREG_B1_P3_U0_CFG12 EQU 0x4001164c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13 -CYREG_B1_P3_U0_CFG13 EQU 0x4001164d - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14 -CYREG_B1_P3_U0_CFG14 EQU 0x4001164e - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15 -CYREG_B1_P3_U0_CFG15 EQU 0x4001164f - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16 -CYREG_B1_P3_U0_CFG16 EQU 0x40011650 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17 -CYREG_B1_P3_U0_CFG17 EQU 0x40011651 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18 -CYREG_B1_P3_U0_CFG18 EQU 0x40011652 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19 -CYREG_B1_P3_U0_CFG19 EQU 0x40011653 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20 -CYREG_B1_P3_U0_CFG20 EQU 0x40011654 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21 -CYREG_B1_P3_U0_CFG21 EQU 0x40011655 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22 -CYREG_B1_P3_U0_CFG22 EQU 0x40011656 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23 -CYREG_B1_P3_U0_CFG23 EQU 0x40011657 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24 -CYREG_B1_P3_U0_CFG24 EQU 0x40011658 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25 -CYREG_B1_P3_U0_CFG25 EQU 0x40011659 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26 -CYREG_B1_P3_U0_CFG26 EQU 0x4001165a - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27 -CYREG_B1_P3_U0_CFG27 EQU 0x4001165b - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28 -CYREG_B1_P3_U0_CFG28 EQU 0x4001165c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29 -CYREG_B1_P3_U0_CFG29 EQU 0x4001165d - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30 -CYREG_B1_P3_U0_CFG30 EQU 0x4001165e - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31 -CYREG_B1_P3_U0_CFG31 EQU 0x4001165f - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0 -CYREG_B1_P3_U0_DCFG0 EQU 0x40011660 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1 -CYREG_B1_P3_U0_DCFG1 EQU 0x40011662 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2 -CYREG_B1_P3_U0_DCFG2 EQU 0x40011664 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3 -CYREG_B1_P3_U0_DCFG3 EQU 0x40011666 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4 -CYREG_B1_P3_U0_DCFG4 EQU 0x40011668 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5 -CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6 -CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7 -CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE -CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE -CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0 -CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1 -CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2 -CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3 -CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4 -CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5 -CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6 -CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7 -CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8 -CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9 -CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10 -CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11 -CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0 -CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1 -CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2 -CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3 -CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST -CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB -CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET -CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS -CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0 -CYREG_B1_P3_U1_CFG0 EQU 0x400116c0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1 -CYREG_B1_P3_U1_CFG1 EQU 0x400116c1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2 -CYREG_B1_P3_U1_CFG2 EQU 0x400116c2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3 -CYREG_B1_P3_U1_CFG3 EQU 0x400116c3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4 -CYREG_B1_P3_U1_CFG4 EQU 0x400116c4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5 -CYREG_B1_P3_U1_CFG5 EQU 0x400116c5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6 -CYREG_B1_P3_U1_CFG6 EQU 0x400116c6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7 -CYREG_B1_P3_U1_CFG7 EQU 0x400116c7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8 -CYREG_B1_P3_U1_CFG8 EQU 0x400116c8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9 -CYREG_B1_P3_U1_CFG9 EQU 0x400116c9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10 -CYREG_B1_P3_U1_CFG10 EQU 0x400116ca - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11 -CYREG_B1_P3_U1_CFG11 EQU 0x400116cb - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12 -CYREG_B1_P3_U1_CFG12 EQU 0x400116cc - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13 -CYREG_B1_P3_U1_CFG13 EQU 0x400116cd - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14 -CYREG_B1_P3_U1_CFG14 EQU 0x400116ce - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15 -CYREG_B1_P3_U1_CFG15 EQU 0x400116cf - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16 -CYREG_B1_P3_U1_CFG16 EQU 0x400116d0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17 -CYREG_B1_P3_U1_CFG17 EQU 0x400116d1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18 -CYREG_B1_P3_U1_CFG18 EQU 0x400116d2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19 -CYREG_B1_P3_U1_CFG19 EQU 0x400116d3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20 -CYREG_B1_P3_U1_CFG20 EQU 0x400116d4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21 -CYREG_B1_P3_U1_CFG21 EQU 0x400116d5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22 -CYREG_B1_P3_U1_CFG22 EQU 0x400116d6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23 -CYREG_B1_P3_U1_CFG23 EQU 0x400116d7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24 -CYREG_B1_P3_U1_CFG24 EQU 0x400116d8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25 -CYREG_B1_P3_U1_CFG25 EQU 0x400116d9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26 -CYREG_B1_P3_U1_CFG26 EQU 0x400116da - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27 -CYREG_B1_P3_U1_CFG27 EQU 0x400116db - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28 -CYREG_B1_P3_U1_CFG28 EQU 0x400116dc - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29 -CYREG_B1_P3_U1_CFG29 EQU 0x400116dd - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30 -CYREG_B1_P3_U1_CFG30 EQU 0x400116de - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31 -CYREG_B1_P3_U1_CFG31 EQU 0x400116df - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0 -CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1 -CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2 -CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3 -CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4 -CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5 -CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6 -CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec - ENDIF - IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7 -CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE -CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE -CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE -CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE -CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE -CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE -CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0 -CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1 -CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2 -CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3 -CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4 -CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5 -CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6 -CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7 -CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8 -CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9 -CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10 -CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11 -CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0 -CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1 -CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2 -CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3 -CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST -CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB -CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET -CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS -CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0 -CYREG_B1_P4_U0_CFG0 EQU 0x40011840 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1 -CYREG_B1_P4_U0_CFG1 EQU 0x40011841 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2 -CYREG_B1_P4_U0_CFG2 EQU 0x40011842 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3 -CYREG_B1_P4_U0_CFG3 EQU 0x40011843 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4 -CYREG_B1_P4_U0_CFG4 EQU 0x40011844 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5 -CYREG_B1_P4_U0_CFG5 EQU 0x40011845 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6 -CYREG_B1_P4_U0_CFG6 EQU 0x40011846 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7 -CYREG_B1_P4_U0_CFG7 EQU 0x40011847 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8 -CYREG_B1_P4_U0_CFG8 EQU 0x40011848 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9 -CYREG_B1_P4_U0_CFG9 EQU 0x40011849 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10 -CYREG_B1_P4_U0_CFG10 EQU 0x4001184a - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11 -CYREG_B1_P4_U0_CFG11 EQU 0x4001184b - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12 -CYREG_B1_P4_U0_CFG12 EQU 0x4001184c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13 -CYREG_B1_P4_U0_CFG13 EQU 0x4001184d - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14 -CYREG_B1_P4_U0_CFG14 EQU 0x4001184e - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15 -CYREG_B1_P4_U0_CFG15 EQU 0x4001184f - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16 -CYREG_B1_P4_U0_CFG16 EQU 0x40011850 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17 -CYREG_B1_P4_U0_CFG17 EQU 0x40011851 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18 -CYREG_B1_P4_U0_CFG18 EQU 0x40011852 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19 -CYREG_B1_P4_U0_CFG19 EQU 0x40011853 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20 -CYREG_B1_P4_U0_CFG20 EQU 0x40011854 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21 -CYREG_B1_P4_U0_CFG21 EQU 0x40011855 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22 -CYREG_B1_P4_U0_CFG22 EQU 0x40011856 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23 -CYREG_B1_P4_U0_CFG23 EQU 0x40011857 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24 -CYREG_B1_P4_U0_CFG24 EQU 0x40011858 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25 -CYREG_B1_P4_U0_CFG25 EQU 0x40011859 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26 -CYREG_B1_P4_U0_CFG26 EQU 0x4001185a - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27 -CYREG_B1_P4_U0_CFG27 EQU 0x4001185b - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28 -CYREG_B1_P4_U0_CFG28 EQU 0x4001185c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29 -CYREG_B1_P4_U0_CFG29 EQU 0x4001185d - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30 -CYREG_B1_P4_U0_CFG30 EQU 0x4001185e - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31 -CYREG_B1_P4_U0_CFG31 EQU 0x4001185f - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0 -CYREG_B1_P4_U0_DCFG0 EQU 0x40011860 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1 -CYREG_B1_P4_U0_DCFG1 EQU 0x40011862 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2 -CYREG_B1_P4_U0_DCFG2 EQU 0x40011864 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3 -CYREG_B1_P4_U0_DCFG3 EQU 0x40011866 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4 -CYREG_B1_P4_U0_DCFG4 EQU 0x40011868 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5 -CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6 -CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7 -CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE -CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE -CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0 -CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1 -CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2 -CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3 -CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4 -CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5 -CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6 -CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7 -CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8 -CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9 -CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10 -CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11 -CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0 -CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1 -CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2 -CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3 -CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST -CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB -CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET -CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS -CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0 -CYREG_B1_P4_U1_CFG0 EQU 0x400118c0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1 -CYREG_B1_P4_U1_CFG1 EQU 0x400118c1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2 -CYREG_B1_P4_U1_CFG2 EQU 0x400118c2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3 -CYREG_B1_P4_U1_CFG3 EQU 0x400118c3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4 -CYREG_B1_P4_U1_CFG4 EQU 0x400118c4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5 -CYREG_B1_P4_U1_CFG5 EQU 0x400118c5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6 -CYREG_B1_P4_U1_CFG6 EQU 0x400118c6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7 -CYREG_B1_P4_U1_CFG7 EQU 0x400118c7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8 -CYREG_B1_P4_U1_CFG8 EQU 0x400118c8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9 -CYREG_B1_P4_U1_CFG9 EQU 0x400118c9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10 -CYREG_B1_P4_U1_CFG10 EQU 0x400118ca - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11 -CYREG_B1_P4_U1_CFG11 EQU 0x400118cb - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12 -CYREG_B1_P4_U1_CFG12 EQU 0x400118cc - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13 -CYREG_B1_P4_U1_CFG13 EQU 0x400118cd - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14 -CYREG_B1_P4_U1_CFG14 EQU 0x400118ce - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15 -CYREG_B1_P4_U1_CFG15 EQU 0x400118cf - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16 -CYREG_B1_P4_U1_CFG16 EQU 0x400118d0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17 -CYREG_B1_P4_U1_CFG17 EQU 0x400118d1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18 -CYREG_B1_P4_U1_CFG18 EQU 0x400118d2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19 -CYREG_B1_P4_U1_CFG19 EQU 0x400118d3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20 -CYREG_B1_P4_U1_CFG20 EQU 0x400118d4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21 -CYREG_B1_P4_U1_CFG21 EQU 0x400118d5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22 -CYREG_B1_P4_U1_CFG22 EQU 0x400118d6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23 -CYREG_B1_P4_U1_CFG23 EQU 0x400118d7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24 -CYREG_B1_P4_U1_CFG24 EQU 0x400118d8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25 -CYREG_B1_P4_U1_CFG25 EQU 0x400118d9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26 -CYREG_B1_P4_U1_CFG26 EQU 0x400118da - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27 -CYREG_B1_P4_U1_CFG27 EQU 0x400118db - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28 -CYREG_B1_P4_U1_CFG28 EQU 0x400118dc - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29 -CYREG_B1_P4_U1_CFG29 EQU 0x400118dd - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30 -CYREG_B1_P4_U1_CFG30 EQU 0x400118de - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31 -CYREG_B1_P4_U1_CFG31 EQU 0x400118df - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0 -CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1 -CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2 -CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3 -CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4 -CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5 -CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6 -CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec - ENDIF - IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7 -CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE -CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE -CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE -CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE -CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE -CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE -CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0 -CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1 -CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2 -CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3 -CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4 -CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5 -CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6 -CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7 -CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8 -CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9 -CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10 -CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11 -CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0 -CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1 -CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2 -CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3 -CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST -CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB -CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET -CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS -CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0 -CYREG_B1_P5_U0_CFG0 EQU 0x40011a40 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1 -CYREG_B1_P5_U0_CFG1 EQU 0x40011a41 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2 -CYREG_B1_P5_U0_CFG2 EQU 0x40011a42 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3 -CYREG_B1_P5_U0_CFG3 EQU 0x40011a43 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4 -CYREG_B1_P5_U0_CFG4 EQU 0x40011a44 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5 -CYREG_B1_P5_U0_CFG5 EQU 0x40011a45 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6 -CYREG_B1_P5_U0_CFG6 EQU 0x40011a46 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7 -CYREG_B1_P5_U0_CFG7 EQU 0x40011a47 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8 -CYREG_B1_P5_U0_CFG8 EQU 0x40011a48 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9 -CYREG_B1_P5_U0_CFG9 EQU 0x40011a49 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10 -CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11 -CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12 -CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13 -CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14 -CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15 -CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16 -CYREG_B1_P5_U0_CFG16 EQU 0x40011a50 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17 -CYREG_B1_P5_U0_CFG17 EQU 0x40011a51 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18 -CYREG_B1_P5_U0_CFG18 EQU 0x40011a52 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19 -CYREG_B1_P5_U0_CFG19 EQU 0x40011a53 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20 -CYREG_B1_P5_U0_CFG20 EQU 0x40011a54 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21 -CYREG_B1_P5_U0_CFG21 EQU 0x40011a55 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22 -CYREG_B1_P5_U0_CFG22 EQU 0x40011a56 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23 -CYREG_B1_P5_U0_CFG23 EQU 0x40011a57 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24 -CYREG_B1_P5_U0_CFG24 EQU 0x40011a58 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25 -CYREG_B1_P5_U0_CFG25 EQU 0x40011a59 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26 -CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27 -CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28 -CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29 -CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30 -CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31 -CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0 -CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1 -CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2 -CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3 -CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4 -CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5 -CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6 -CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7 -CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE -CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE -CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0 -CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1 -CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2 -CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3 -CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4 -CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5 -CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6 -CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7 -CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8 -CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9 -CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10 -CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11 -CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0 -CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1 -CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2 -CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3 -CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST -CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB -CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET -CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS -CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0 -CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1 -CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2 -CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3 -CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4 -CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5 -CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6 -CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7 -CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8 -CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9 -CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10 -CYREG_B1_P5_U1_CFG10 EQU 0x40011aca - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11 -CYREG_B1_P5_U1_CFG11 EQU 0x40011acb - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12 -CYREG_B1_P5_U1_CFG12 EQU 0x40011acc - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13 -CYREG_B1_P5_U1_CFG13 EQU 0x40011acd - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14 -CYREG_B1_P5_U1_CFG14 EQU 0x40011ace - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15 -CYREG_B1_P5_U1_CFG15 EQU 0x40011acf - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16 -CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17 -CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18 -CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19 -CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20 -CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21 -CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22 -CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23 -CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24 -CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25 -CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26 -CYREG_B1_P5_U1_CFG26 EQU 0x40011ada - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27 -CYREG_B1_P5_U1_CFG27 EQU 0x40011adb - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28 -CYREG_B1_P5_U1_CFG28 EQU 0x40011adc - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29 -CYREG_B1_P5_U1_CFG29 EQU 0x40011add - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30 -CYREG_B1_P5_U1_CFG30 EQU 0x40011ade - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31 -CYREG_B1_P5_U1_CFG31 EQU 0x40011adf - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0 -CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1 -CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2 -CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3 -CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4 -CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8 - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5 -CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6 -CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec - ENDIF - IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7 -CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE -CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE -CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE -CYDEV_UCFG_DSI0_BASE EQU 0x40014000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE -CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE -CYDEV_UCFG_DSI1_BASE EQU 0x40014100 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE -CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE -CYDEV_UCFG_DSI2_BASE EQU 0x40014200 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE -CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE -CYDEV_UCFG_DSI3_BASE EQU 0x40014300 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE -CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE -CYDEV_UCFG_DSI4_BASE EQU 0x40014400 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE -CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE -CYDEV_UCFG_DSI5_BASE EQU 0x40014500 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE -CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE -CYDEV_UCFG_DSI6_BASE EQU 0x40014600 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE -CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE -CYDEV_UCFG_DSI7_BASE EQU 0x40014700 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE -CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE -CYDEV_UCFG_DSI8_BASE EQU 0x40014800 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE -CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE -CYDEV_UCFG_DSI9_BASE EQU 0x40014900 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE -CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE -CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE -CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE -CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE -CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE -CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE -CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN -CYREG_BCTL0_MDCLK_EN EQU 0x40015000 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN -CYREG_BCTL0_MBCLK_EN EQU 0x40015001 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG -CYREG_BCTL0_WAIT_CFG EQU 0x40015002 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL -CYREG_BCTL0_BANK_CTL EQU 0x40015003 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3 -CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0 -CYREG_BCTL0_DCLK_EN0 EQU 0x40015008 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0 -CYREG_BCTL0_BCLK_EN0 EQU 0x40015009 - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1 -CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1 -CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2 -CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2 -CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3 -CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e - ENDIF - IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3 -CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE -CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 - ENDIF - IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE -CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN -CYREG_BCTL1_MDCLK_EN EQU 0x40015010 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN -CYREG_BCTL1_MBCLK_EN EQU 0x40015011 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG -CYREG_BCTL1_WAIT_CFG EQU 0x40015012 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL -CYREG_BCTL1_BANK_CTL EQU 0x40015013 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3 -CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0 -CYREG_BCTL1_DCLK_EN0 EQU 0x40015018 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0 -CYREG_BCTL1_BCLK_EN0 EQU 0x40015019 - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1 -CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1 -CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2 -CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2 -CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3 -CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e - ENDIF - IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3 -CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_BASE -CYDEV_IDMUX_BASE EQU 0x40015100 - ENDIF - IF :LNOT::DEF:CYDEV_IDMUX_SIZE -CYDEV_IDMUX_SIZE EQU 0x00000016 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0 -CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1 -CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2 -CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3 -CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4 -CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5 -CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6 -CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7 -CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0 -CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1 -CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2 -CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3 -CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4 -CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114 - ENDIF - IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5 -CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115 - ENDIF - IF :LNOT::DEF:CYDEV_CACHERAM_BASE -CYDEV_CACHERAM_BASE EQU 0x40030000 - ENDIF - IF :LNOT::DEF:CYDEV_CACHERAM_SIZE -CYDEV_CACHERAM_SIZE EQU 0x00000400 - ENDIF - IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE -CYREG_CACHERAM_DATA_MBASE EQU 0x40030000 - ENDIF - IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE -CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_BASE -CYDEV_SFR_BASE EQU 0x40050100 - ENDIF - IF :LNOT::DEF:CYDEV_SFR_SIZE -CYDEV_SFR_SIZE EQU 0x000000fb - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO0 -CYREG_SFR_GPIO0 EQU 0x40050180 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD0 -CYREG_SFR_GPIRD0 EQU 0x40050189 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL -CYREG_SFR_GPIO0_SEL EQU 0x4005018a - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO1 -CYREG_SFR_GPIO1 EQU 0x40050190 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD1 -CYREG_SFR_GPIRD1 EQU 0x40050191 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO2 -CYREG_SFR_GPIO2 EQU 0x40050198 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD2 -CYREG_SFR_GPIRD2 EQU 0x40050199 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL -CYREG_SFR_GPIO2_SEL EQU 0x4005019a - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL -CYREG_SFR_GPIO1_SEL EQU 0x400501a2 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO3 -CYREG_SFR_GPIO3 EQU 0x400501b0 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD3 -CYREG_SFR_GPIRD3 EQU 0x400501b1 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL -CYREG_SFR_GPIO3_SEL EQU 0x400501b2 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO4 -CYREG_SFR_GPIO4 EQU 0x400501c0 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD4 -CYREG_SFR_GPIRD4 EQU 0x400501c1 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL -CYREG_SFR_GPIO4_SEL EQU 0x400501c2 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO5 -CYREG_SFR_GPIO5 EQU 0x400501c8 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD5 -CYREG_SFR_GPIRD5 EQU 0x400501c9 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL -CYREG_SFR_GPIO5_SEL EQU 0x400501ca - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO6 -CYREG_SFR_GPIO6 EQU 0x400501d8 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD6 -CYREG_SFR_GPIRD6 EQU 0x400501d9 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL -CYREG_SFR_GPIO6_SEL EQU 0x400501da - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO12 -CYREG_SFR_GPIO12 EQU 0x400501e8 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD12 -CYREG_SFR_GPIRD12 EQU 0x400501e9 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL -CYREG_SFR_GPIO12_SEL EQU 0x400501f2 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO15 -CYREG_SFR_GPIO15 EQU 0x400501f8 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIRD15 -CYREG_SFR_GPIRD15 EQU 0x400501f9 - ENDIF - IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL -CYREG_SFR_GPIO15_SEL EQU 0x400501fa - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_BASE -CYDEV_P3BA_BASE EQU 0x40050300 - ENDIF - IF :LNOT::DEF:CYDEV_P3BA_SIZE -CYDEV_P3BA_SIZE EQU 0x0000002b - ENDIF - IF :LNOT::DEF:CYREG_P3BA_Y_START -CYREG_P3BA_Y_START EQU 0x40050300 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_YROLL -CYREG_P3BA_YROLL EQU 0x40050301 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_YCFG -CYREG_P3BA_YCFG EQU 0x40050302 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_X_START1 -CYREG_P3BA_X_START1 EQU 0x40050303 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_X_START2 -CYREG_P3BA_X_START2 EQU 0x40050304 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_XROLL1 -CYREG_P3BA_XROLL1 EQU 0x40050305 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_XROLL2 -CYREG_P3BA_XROLL2 EQU 0x40050306 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_XINC -CYREG_P3BA_XINC EQU 0x40050307 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_XCFG -CYREG_P3BA_XCFG EQU 0x40050308 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1 -CYREG_P3BA_OFFSETADDR1 EQU 0x40050309 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2 -CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a - ENDIF - IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3 -CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b - ENDIF - IF :LNOT::DEF:CYREG_P3BA_ABSADDR1 -CYREG_P3BA_ABSADDR1 EQU 0x4005030c - ENDIF - IF :LNOT::DEF:CYREG_P3BA_ABSADDR2 -CYREG_P3BA_ABSADDR2 EQU 0x4005030d - ENDIF - IF :LNOT::DEF:CYREG_P3BA_ABSADDR3 -CYREG_P3BA_ABSADDR3 EQU 0x4005030e - ENDIF - IF :LNOT::DEF:CYREG_P3BA_ABSADDR4 -CYREG_P3BA_ABSADDR4 EQU 0x4005030f - ENDIF - IF :LNOT::DEF:CYREG_P3BA_DATCFG1 -CYREG_P3BA_DATCFG1 EQU 0x40050310 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_DATCFG2 -CYREG_P3BA_DATCFG2 EQU 0x40050311 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1 -CYREG_P3BA_CMP_RSLT1 EQU 0x40050314 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2 -CYREG_P3BA_CMP_RSLT2 EQU 0x40050315 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3 -CYREG_P3BA_CMP_RSLT3 EQU 0x40050316 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4 -CYREG_P3BA_CMP_RSLT4 EQU 0x40050317 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_DATA_REG1 -CYREG_P3BA_DATA_REG1 EQU 0x40050318 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_DATA_REG2 -CYREG_P3BA_DATA_REG2 EQU 0x40050319 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_DATA_REG3 -CYREG_P3BA_DATA_REG3 EQU 0x4005031a - ENDIF - IF :LNOT::DEF:CYREG_P3BA_DATA_REG4 -CYREG_P3BA_DATA_REG4 EQU 0x4005031b - ENDIF - IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1 -CYREG_P3BA_EXP_DATA1 EQU 0x4005031c - ENDIF - IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2 -CYREG_P3BA_EXP_DATA2 EQU 0x4005031d - ENDIF - IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3 -CYREG_P3BA_EXP_DATA3 EQU 0x4005031e - ENDIF - IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4 -CYREG_P3BA_EXP_DATA4 EQU 0x4005031f - ENDIF - IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1 -CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2 -CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3 -CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4 -CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_BIST_EN -CYREG_P3BA_BIST_EN EQU 0x40050324 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR -CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_SEQCFG1 -CYREG_P3BA_SEQCFG1 EQU 0x40050326 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_SEQCFG2 -CYREG_P3BA_SEQCFG2 EQU 0x40050327 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_Y_CURR -CYREG_P3BA_Y_CURR EQU 0x40050328 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_X_CURR1 -CYREG_P3BA_X_CURR1 EQU 0x40050329 - ENDIF - IF :LNOT::DEF:CYREG_P3BA_X_CURR2 -CYREG_P3BA_X_CURR2 EQU 0x4005032a - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_BASE -CYDEV_PANTHER_BASE EQU 0x40080000 - ENDIF - IF :LNOT::DEF:CYDEV_PANTHER_SIZE -CYDEV_PANTHER_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG -CYREG_PANTHER_STCALIB_CFG EQU 0x40080000 - ENDIF - IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE -CYREG_PANTHER_WAITPIPE EQU 0x40080004 - ENDIF - IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG -CYREG_PANTHER_TRACE_CFG EQU 0x40080008 - ENDIF - IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG -CYREG_PANTHER_DBG_CFG EQU 0x4008000c - ENDIF - IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT -CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 - ENDIF - IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID -CYREG_PANTHER_DEVICE_ID EQU 0x4008001c - ENDIF - IF :LNOT::DEF:CYDEV_FLSECC_BASE -CYDEV_FLSECC_BASE EQU 0x48000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSECC_SIZE -CYDEV_FLSECC_SIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE -CYREG_FLSECC_DATA_MBASE EQU 0x48000000 - ENDIF - IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE -CYREG_FLSECC_DATA_MSIZE EQU 0x00008000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_BASE -CYDEV_FLSHID_BASE EQU 0x49000000 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_SIZE -CYDEV_FLSHID_SIZE EQU 0x00000200 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE -CYREG_FLSHID_RSVD_MBASE EQU 0x49000000 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE -CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE -CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE -CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE -CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE -CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC -CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC -CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM -CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB -CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB -CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK -CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR -CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR -CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ -CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ -CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ -CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ -CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ -CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ -CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ -CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB -CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS -CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS -CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS -CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS -CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS -CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS -CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS -CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS -CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1 -CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2 -CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3 -CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4 -CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5 -CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6 -CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7 -CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8 -CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1 -CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2 -CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3 -CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4 -CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5 -CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6 -CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7 -CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8 -CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1 -CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2 -CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3 -CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4 -CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5 -CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6 -CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7 -CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8 -CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1 -CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2 -CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3 -CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4 -CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5 -CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6 -CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7 -CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8 -CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1 -CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2 -CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3 -CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4 -CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5 -CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6 -CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7 -CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8 -CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE -CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 - ENDIF - IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE -CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1 -CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0 -CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0 -CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0 -CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0 -CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1 -CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1 -CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1 -CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1 -CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba - ENDIF - IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM -CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce - ENDIF - IF :LNOT::DEF:CYDEV_EXTMEM_BASE -CYDEV_EXTMEM_BASE EQU 0x60000000 - ENDIF - IF :LNOT::DEF:CYDEV_EXTMEM_SIZE -CYDEV_EXTMEM_SIZE EQU 0x00800000 - ENDIF - IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE -CYREG_EXTMEM_DATA_MBASE EQU 0x60000000 - ENDIF - IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE -CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_BASE -CYDEV_ITM_BASE EQU 0xe0000000 - ENDIF - IF :LNOT::DEF:CYDEV_ITM_SIZE -CYDEV_ITM_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_ITM_TRACE_EN -CYREG_ITM_TRACE_EN EQU 0xe0000e00 - ENDIF - IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE -CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 - ENDIF - IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL -CYREG_ITM_TRACE_CTRL EQU 0xe0000e80 - ENDIF - IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS -CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0 - ENDIF - IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS -CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4 - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID4 -CYREG_ITM_PID4 EQU 0xe0000fd0 - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID5 -CYREG_ITM_PID5 EQU 0xe0000fd4 - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID6 -CYREG_ITM_PID6 EQU 0xe0000fd8 - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID7 -CYREG_ITM_PID7 EQU 0xe0000fdc - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID0 -CYREG_ITM_PID0 EQU 0xe0000fe0 - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID1 -CYREG_ITM_PID1 EQU 0xe0000fe4 - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID2 -CYREG_ITM_PID2 EQU 0xe0000fe8 - ENDIF - IF :LNOT::DEF:CYREG_ITM_PID3 -CYREG_ITM_PID3 EQU 0xe0000fec - ENDIF - IF :LNOT::DEF:CYREG_ITM_CID0 -CYREG_ITM_CID0 EQU 0xe0000ff0 - ENDIF - IF :LNOT::DEF:CYREG_ITM_CID1 -CYREG_ITM_CID1 EQU 0xe0000ff4 - ENDIF - IF :LNOT::DEF:CYREG_ITM_CID2 -CYREG_ITM_CID2 EQU 0xe0000ff8 - ENDIF - IF :LNOT::DEF:CYREG_ITM_CID3 -CYREG_ITM_CID3 EQU 0xe0000ffc - ENDIF - IF :LNOT::DEF:CYDEV_DWT_BASE -CYDEV_DWT_BASE EQU 0xe0001000 - ENDIF - IF :LNOT::DEF:CYDEV_DWT_SIZE -CYDEV_DWT_SIZE EQU 0x0000005c - ENDIF - IF :LNOT::DEF:CYREG_DWT_CTRL -CYREG_DWT_CTRL EQU 0xe0001000 - ENDIF - IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT -CYREG_DWT_CYCLE_COUNT EQU 0xe0001004 - ENDIF - IF :LNOT::DEF:CYREG_DWT_CPI_COUNT -CYREG_DWT_CPI_COUNT EQU 0xe0001008 - ENDIF - IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT -CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c - ENDIF - IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT -CYREG_DWT_SLEEP_COUNT EQU 0xe0001010 - ENDIF - IF :LNOT::DEF:CYREG_DWT_LSU_COUNT -CYREG_DWT_LSU_COUNT EQU 0xe0001014 - ENDIF - IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT -CYREG_DWT_FOLD_COUNT EQU 0xe0001018 - ENDIF - IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE -CYREG_DWT_PC_SAMPLE EQU 0xe000101c - ENDIF - IF :LNOT::DEF:CYREG_DWT_COMP_0 -CYREG_DWT_COMP_0 EQU 0xe0001020 - ENDIF - IF :LNOT::DEF:CYREG_DWT_MASK_0 -CYREG_DWT_MASK_0 EQU 0xe0001024 - ENDIF - IF :LNOT::DEF:CYREG_DWT_FUNCTION_0 -CYREG_DWT_FUNCTION_0 EQU 0xe0001028 - ENDIF - IF :LNOT::DEF:CYREG_DWT_COMP_1 -CYREG_DWT_COMP_1 EQU 0xe0001030 - ENDIF - IF :LNOT::DEF:CYREG_DWT_MASK_1 -CYREG_DWT_MASK_1 EQU 0xe0001034 - ENDIF - IF :LNOT::DEF:CYREG_DWT_FUNCTION_1 -CYREG_DWT_FUNCTION_1 EQU 0xe0001038 - ENDIF - IF :LNOT::DEF:CYREG_DWT_COMP_2 -CYREG_DWT_COMP_2 EQU 0xe0001040 - ENDIF - IF :LNOT::DEF:CYREG_DWT_MASK_2 -CYREG_DWT_MASK_2 EQU 0xe0001044 - ENDIF - IF :LNOT::DEF:CYREG_DWT_FUNCTION_2 -CYREG_DWT_FUNCTION_2 EQU 0xe0001048 - ENDIF - IF :LNOT::DEF:CYREG_DWT_COMP_3 -CYREG_DWT_COMP_3 EQU 0xe0001050 - ENDIF - IF :LNOT::DEF:CYREG_DWT_MASK_3 -CYREG_DWT_MASK_3 EQU 0xe0001054 - ENDIF - IF :LNOT::DEF:CYREG_DWT_FUNCTION_3 -CYREG_DWT_FUNCTION_3 EQU 0xe0001058 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_BASE -CYDEV_FPB_BASE EQU 0xe0002000 - ENDIF - IF :LNOT::DEF:CYDEV_FPB_SIZE -CYDEV_FPB_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_FPB_CTRL -CYREG_FPB_CTRL EQU 0xe0002000 - ENDIF - IF :LNOT::DEF:CYREG_FPB_REMAP -CYREG_FPB_REMAP EQU 0xe0002004 - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_0 -CYREG_FPB_FP_COMP_0 EQU 0xe0002008 - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_1 -CYREG_FPB_FP_COMP_1 EQU 0xe000200c - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_2 -CYREG_FPB_FP_COMP_2 EQU 0xe0002010 - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_3 -CYREG_FPB_FP_COMP_3 EQU 0xe0002014 - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_4 -CYREG_FPB_FP_COMP_4 EQU 0xe0002018 - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_5 -CYREG_FPB_FP_COMP_5 EQU 0xe000201c - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_6 -CYREG_FPB_FP_COMP_6 EQU 0xe0002020 - ENDIF - IF :LNOT::DEF:CYREG_FPB_FP_COMP_7 -CYREG_FPB_FP_COMP_7 EQU 0xe0002024 - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID4 -CYREG_FPB_PID4 EQU 0xe0002fd0 - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID5 -CYREG_FPB_PID5 EQU 0xe0002fd4 - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID6 -CYREG_FPB_PID6 EQU 0xe0002fd8 - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID7 -CYREG_FPB_PID7 EQU 0xe0002fdc - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID0 -CYREG_FPB_PID0 EQU 0xe0002fe0 - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID1 -CYREG_FPB_PID1 EQU 0xe0002fe4 - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID2 -CYREG_FPB_PID2 EQU 0xe0002fe8 - ENDIF - IF :LNOT::DEF:CYREG_FPB_PID3 -CYREG_FPB_PID3 EQU 0xe0002fec - ENDIF - IF :LNOT::DEF:CYREG_FPB_CID0 -CYREG_FPB_CID0 EQU 0xe0002ff0 - ENDIF - IF :LNOT::DEF:CYREG_FPB_CID1 -CYREG_FPB_CID1 EQU 0xe0002ff4 - ENDIF - IF :LNOT::DEF:CYREG_FPB_CID2 -CYREG_FPB_CID2 EQU 0xe0002ff8 - ENDIF - IF :LNOT::DEF:CYREG_FPB_CID3 -CYREG_FPB_CID3 EQU 0xe0002ffc - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_BASE -CYDEV_NVIC_BASE EQU 0xe000e000 - ENDIF - IF :LNOT::DEF:CYDEV_NVIC_SIZE -CYDEV_NVIC_SIZE EQU 0x00000d3c - ENDIF - IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE -CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL -CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD -CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT -CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL -CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SETENA0 -CYREG_NVIC_SETENA0 EQU 0xe000e100 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_CLRENA0 -CYREG_NVIC_CLRENA0 EQU 0xe000e180 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SETPEND0 -CYREG_NVIC_SETPEND0 EQU 0xe000e200 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_CLRPEND0 -CYREG_NVIC_CLRPEND0 EQU 0xe000e280 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_ACTIVE0 -CYREG_NVIC_ACTIVE0 EQU 0xe000e300 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_0 -CYREG_NVIC_PRI_0 EQU 0xe000e400 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_1 -CYREG_NVIC_PRI_1 EQU 0xe000e401 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_2 -CYREG_NVIC_PRI_2 EQU 0xe000e402 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_3 -CYREG_NVIC_PRI_3 EQU 0xe000e403 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_4 -CYREG_NVIC_PRI_4 EQU 0xe000e404 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_5 -CYREG_NVIC_PRI_5 EQU 0xe000e405 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_6 -CYREG_NVIC_PRI_6 EQU 0xe000e406 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_7 -CYREG_NVIC_PRI_7 EQU 0xe000e407 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_8 -CYREG_NVIC_PRI_8 EQU 0xe000e408 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_9 -CYREG_NVIC_PRI_9 EQU 0xe000e409 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_10 -CYREG_NVIC_PRI_10 EQU 0xe000e40a - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_11 -CYREG_NVIC_PRI_11 EQU 0xe000e40b - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_12 -CYREG_NVIC_PRI_12 EQU 0xe000e40c - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_13 -CYREG_NVIC_PRI_13 EQU 0xe000e40d - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_14 -CYREG_NVIC_PRI_14 EQU 0xe000e40e - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_15 -CYREG_NVIC_PRI_15 EQU 0xe000e40f - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_16 -CYREG_NVIC_PRI_16 EQU 0xe000e410 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_17 -CYREG_NVIC_PRI_17 EQU 0xe000e411 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_18 -CYREG_NVIC_PRI_18 EQU 0xe000e412 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_19 -CYREG_NVIC_PRI_19 EQU 0xe000e413 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_20 -CYREG_NVIC_PRI_20 EQU 0xe000e414 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_21 -CYREG_NVIC_PRI_21 EQU 0xe000e415 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_22 -CYREG_NVIC_PRI_22 EQU 0xe000e416 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_23 -CYREG_NVIC_PRI_23 EQU 0xe000e417 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_24 -CYREG_NVIC_PRI_24 EQU 0xe000e418 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_25 -CYREG_NVIC_PRI_25 EQU 0xe000e419 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_26 -CYREG_NVIC_PRI_26 EQU 0xe000e41a - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_27 -CYREG_NVIC_PRI_27 EQU 0xe000e41b - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_28 -CYREG_NVIC_PRI_28 EQU 0xe000e41c - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_29 -CYREG_NVIC_PRI_29 EQU 0xe000e41d - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_30 -CYREG_NVIC_PRI_30 EQU 0xe000e41e - ENDIF - IF :LNOT::DEF:CYREG_NVIC_PRI_31 -CYREG_NVIC_PRI_31 EQU 0xe000e41f - ENDIF - IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE -CYREG_NVIC_CPUID_BASE EQU 0xe000ed00 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE -CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET -CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR -CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL -CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL -CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7 -CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11 -CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15 -CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR -CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS -CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS -CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS -CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a - ENDIF - IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS -CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c - ENDIF - IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS -CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD -CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 - ENDIF - IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD -CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_BASE -CYDEV_CORE_DBG_BASE EQU 0xe000edf0 - ENDIF - IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE -CYDEV_CORE_DBG_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS -CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 - ENDIF - IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL -CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 - ENDIF - IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA -CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 - ENDIF - IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL -CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_BASE -CYDEV_TPIU_BASE EQU 0xe0040000 - ENDIF - IF :LNOT::DEF:CYDEV_TPIU_SIZE -CYDEV_TPIU_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ -CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ -CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER -CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PROTOCOL -CYREG_TPIU_PROTOCOL EQU 0xe00400f0 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT -CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL -CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_TRIGGER -CYREG_TPIU_TRIGGER EQU 0xe0040ee8 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_ITETMDATA -CYREG_TPIU_ITETMDATA EQU 0xe0040eec - ENDIF - IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2 -CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0 -CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_ITITMDATA -CYREG_TPIU_ITITMDATA EQU 0xe0040efc - ENDIF - IF :LNOT::DEF:CYREG_TPIU_ITCTRL -CYREG_TPIU_ITCTRL EQU 0xe0040f00 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_DEVID -CYREG_TPIU_DEVID EQU 0xe0040fc8 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_DEVTYPE -CYREG_TPIU_DEVTYPE EQU 0xe0040fcc - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID4 -CYREG_TPIU_PID4 EQU 0xe0040fd0 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID5 -CYREG_TPIU_PID5 EQU 0xe0040fd4 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID6 -CYREG_TPIU_PID6 EQU 0xe0040fd8 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID7 -CYREG_TPIU_PID7 EQU 0xe0040fdc - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID0 -CYREG_TPIU_PID0 EQU 0xe0040fe0 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID1 -CYREG_TPIU_PID1 EQU 0xe0040fe4 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID2 -CYREG_TPIU_PID2 EQU 0xe0040fe8 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_PID3 -CYREG_TPIU_PID3 EQU 0xe0040fec - ENDIF - IF :LNOT::DEF:CYREG_TPIU_CID0 -CYREG_TPIU_CID0 EQU 0xe0040ff0 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_CID1 -CYREG_TPIU_CID1 EQU 0xe0040ff4 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_CID2 -CYREG_TPIU_CID2 EQU 0xe0040ff8 - ENDIF - IF :LNOT::DEF:CYREG_TPIU_CID3 -CYREG_TPIU_CID3 EQU 0xe0040ffc - ENDIF - IF :LNOT::DEF:CYDEV_ETM_BASE -CYDEV_ETM_BASE EQU 0xe0041000 - ENDIF - IF :LNOT::DEF:CYDEV_ETM_SIZE -CYDEV_ETM_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CTL -CYREG_ETM_CTL EQU 0xe0041000 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CFG_CODE -CYREG_ETM_CFG_CODE EQU 0xe0041004 - ENDIF - IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT -CYREG_ETM_TRIG_EVENT EQU 0xe0041008 - ENDIF - IF :LNOT::DEF:CYREG_ETM_STATUS -CYREG_ETM_STATUS EQU 0xe0041010 - ENDIF - IF :LNOT::DEF:CYREG_ETM_SYS_CFG -CYREG_ETM_SYS_CFG EQU 0xe0041014 - ENDIF - IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT -CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020 - ENDIF - IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1 -CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 - ENDIF - IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL -CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c - ENDIF - IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ -CYREG_ETM_SYNC_FREQ EQU 0xe00411e0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_ETM_ID -CYREG_ETM_ETM_ID EQU 0xe00411e4 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT -CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8 - ENDIF - IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL -CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID -CYREG_ETM_CS_TRACE_ID EQU 0xe0041200 - ENDIF - IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS -CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300 - ENDIF - IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS -CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304 - ENDIF - IF :LNOT::DEF:CYREG_ETM_PDSR -CYREG_ETM_PDSR EQU 0xe0041314 - ENDIF - IF :LNOT::DEF:CYREG_ETM_ITMISCIN -CYREG_ETM_ITMISCIN EQU 0xe0041ee0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT -CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8 - ENDIF - IF :LNOT::DEF:CYREG_ETM_ITATBCTR2 -CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_ITATBCTR0 -CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8 - ENDIF - IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL -CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET -CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR -CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4 - ENDIF - IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS -CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS -CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4 - ENDIF - IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS -CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8 - ENDIF - IF :LNOT::DEF:CYREG_ETM_DEV_TYPE -CYREG_ETM_DEV_TYPE EQU 0xe0041fcc - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID4 -CYREG_ETM_PID4 EQU 0xe0041fd0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID5 -CYREG_ETM_PID5 EQU 0xe0041fd4 - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID6 -CYREG_ETM_PID6 EQU 0xe0041fd8 - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID7 -CYREG_ETM_PID7 EQU 0xe0041fdc - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID0 -CYREG_ETM_PID0 EQU 0xe0041fe0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID1 -CYREG_ETM_PID1 EQU 0xe0041fe4 - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID2 -CYREG_ETM_PID2 EQU 0xe0041fe8 - ENDIF - IF :LNOT::DEF:CYREG_ETM_PID3 -CYREG_ETM_PID3 EQU 0xe0041fec - ENDIF - IF :LNOT::DEF:CYREG_ETM_CID0 -CYREG_ETM_CID0 EQU 0xe0041ff0 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CID1 -CYREG_ETM_CID1 EQU 0xe0041ff4 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CID2 -CYREG_ETM_CID2 EQU 0xe0041ff8 - ENDIF - IF :LNOT::DEF:CYREG_ETM_CID3 -CYREG_ETM_CID3 EQU 0xe0041ffc - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE -CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 - ENDIF - IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE -CYDEV_ROM_TABLE_SIZE EQU 0x00001000 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC -CYREG_ROM_TABLE_NVIC EQU 0xe00ff000 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_DWT -CYREG_ROM_TABLE_DWT EQU 0xe00ff004 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_FPB -CYREG_ROM_TABLE_FPB EQU 0xe00ff008 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_ITM -CYREG_ROM_TABLE_ITM EQU 0xe00ff00c - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU -CYREG_ROM_TABLE_TPIU EQU 0xe00ff010 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_ETM -CYREG_ROM_TABLE_ETM EQU 0xe00ff014 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_END -CYREG_ROM_TABLE_END EQU 0xe00ff018 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE -CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID4 -CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID5 -CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID6 -CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID7 -CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID0 -CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID1 -CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID2 -CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_PID3 -CYREG_ROM_TABLE_PID3 EQU 0xe00fffec - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_CID0 -CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_CID1 -CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_CID2 -CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8 - ENDIF - IF :LNOT::DEF:CYREG_ROM_TABLE_CID3 -CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc - ENDIF - IF :LNOT::DEF:CYDEV_FLS_SIZE -CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE - ENDIF - IF :LNOT::DEF:CYDEV_ECC_BASE -CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE - ENDIF - IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE -CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 - ENDIF - IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE -CYDEV_FLS_ROW_SIZE EQU 0x00000100 - ENDIF - IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE -CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 - ENDIF - IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE -CYDEV_ECC_ROW_SIZE EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE -CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 - ENDIF - IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE -CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYDEV_PERIPH_BASE -CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE - ENDIF - IF :LNOT::DEF:CYCLK_LD_DISABLE -CYCLK_LD_DISABLE EQU 0x00000004 - ENDIF - IF :LNOT::DEF:CYCLK_LD_SYNC_EN -CYCLK_LD_SYNC_EN EQU 0x00000002 - ENDIF - IF :LNOT::DEF:CYCLK_LD_LOAD -CYCLK_LD_LOAD EQU 0x00000001 - ENDIF - IF :LNOT::DEF:CYCLK_PIPE -CYCLK_PIPE EQU 0x00000080 - ENDIF - IF :LNOT::DEF:CYCLK_SSS -CYCLK_SSS EQU 0x00000040 - ENDIF - IF :LNOT::DEF:CYCLK_EARLY -CYCLK_EARLY EQU 0x00000020 - ENDIF - IF :LNOT::DEF:CYCLK_DUTY -CYCLK_DUTY EQU 0x00000010 - ENDIF - IF :LNOT::DEF:CYCLK_SYNC -CYCLK_SYNC EQU 0x00000008 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D -CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG -CYCLK_SRC_SEL_SYNC_DIG EQU 0 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_IMO -CYCLK_SRC_SEL_IMO EQU 1 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ -CYCLK_SRC_SEL_XTAL_MHZ EQU 2 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM -CYCLK_SRC_SEL_XTALM EQU 2 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_ILO -CYCLK_SRC_SEL_ILO EQU 3 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_PLL -CYCLK_SRC_SEL_PLL EQU 4 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ -CYCLK_SRC_SEL_XTAL_KHZ EQU 5 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK -CYCLK_SRC_SEL_XTALK EQU 5 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G -CYCLK_SRC_SEL_DSI_G EQU 6 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D -CYCLK_SRC_SEL_DSI_D EQU 7 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A -CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 - ENDIF - IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A -CYCLK_SRC_SEL_DSI_A EQU 7 - ENDIF - END diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydisabledsheets.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydisabledsheets.h deleted file mode 100755 index 7b6355f..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cydisabledsheets.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef INCLUDED_CYDISABLEDSHEETS_H -#define INCLUDED_CYDISABLEDSHEETS_H - - -#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h deleted file mode 100755 index c8ba646..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter.h +++ /dev/null @@ -1,1409 +0,0 @@ -#ifndef INCLUDED_CYFITTER_H -#define INCLUDED_CYFITTER_H -#include -#include - -/* USBFS_bus_reset */ -#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_bus_reset__INTC_MASK 0x800000u -#define USBFS_bus_reset__INTC_NUMBER 23u -#define USBFS_bus_reset__INTC_PRIOR_NUM 7u -#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 -#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_arb_int */ -#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_arb_int__INTC_MASK 0x400000u -#define USBFS_arb_int__INTC_NUMBER 22u -#define USBFS_arb_int__INTC_PRIOR_NUM 7u -#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 -#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_sof_int__INTC_MASK 0x200000u -#define USBFS_sof_int__INTC_NUMBER 21u -#define USBFS_sof_int__INTC_PRIOR_NUM 7u -#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 -#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_Out_DBx */ -#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__0__MASK 0x08u -#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3 -#define SCSI_Out_DBx__0__PORT 6u -#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__0__SHIFT 3 -#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__1__MASK 0x04u -#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2 -#define SCSI_Out_DBx__1__PORT 6u -#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__1__SHIFT 2 -#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__2__MASK 0x02u -#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1 -#define SCSI_Out_DBx__2__PORT 6u -#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__2__SHIFT 1 -#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__3__MASK 0x01u -#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0 -#define SCSI_Out_DBx__3__PORT 6u -#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__3__SHIFT 0 -#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__4__MASK 0x80u -#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7 -#define SCSI_Out_DBx__4__PORT 4u -#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__4__SHIFT 7 -#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW -#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__5__MASK 0x40u -#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6 -#define SCSI_Out_DBx__5__PORT 4u -#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__5__SHIFT 6 -#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW -#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__6__MASK 0x20u -#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5 -#define SCSI_Out_DBx__6__PORT 4u -#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__6__SHIFT 5 -#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW -#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__7__MASK 0x10u -#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4 -#define SCSI_Out_DBx__7__PORT 4u -#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__7__SHIFT 4 -#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW -#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__DB0__MASK 0x08u -#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3 -#define SCSI_Out_DBx__DB0__PORT 6u -#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB0__SHIFT 3 -#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__DB1__MASK 0x04u -#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2 -#define SCSI_Out_DBx__DB1__PORT 6u -#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB1__SHIFT 2 -#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__DB2__MASK 0x02u -#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1 -#define SCSI_Out_DBx__DB2__PORT 6u -#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB2__SHIFT 1 -#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG -#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX -#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE -#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP -#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL -#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0 -#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1 -#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2 -#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR -#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Out_DBx__DB3__MASK 0x01u -#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0 -#define SCSI_Out_DBx__DB3__PORT 6u -#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT -#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB3__SHIFT 0 -#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW -#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__DB4__MASK 0x80u -#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7 -#define SCSI_Out_DBx__DB4__PORT 4u -#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB4__SHIFT 7 -#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW -#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__DB5__MASK 0x40u -#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6 -#define SCSI_Out_DBx__DB5__PORT 4u -#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB5__SHIFT 6 -#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW -#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__DB6__MASK 0x20u -#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5 -#define SCSI_Out_DBx__DB6__PORT 4u -#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB6__SHIFT 5 -#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW -#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG -#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX -#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE -#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP -#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL -#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0 -#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1 -#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2 -#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR -#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out_DBx__DB7__MASK 0x10u -#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4 -#define SCSI_Out_DBx__DB7__PORT 4u -#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT -#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB7__SHIFT 4 -#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW - -/* USBFS_dp_int */ -#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_dp_int__INTC_MASK 0x1000u -#define USBFS_dp_int__INTC_NUMBER 12u -#define USBFS_dp_int__INTC_PRIOR_NUM 7u -#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 -#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_0__INTC_MASK 0x1000000u -#define USBFS_ep_0__INTC_NUMBER 24u -#define USBFS_ep_0__INTC_PRIOR_NUM 7u -#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 -#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x01u -#define USBFS_ep_1__INTC_NUMBER 0u -#define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0 -#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x02u -#define USBFS_ep_2__INTC_NUMBER 1u -#define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1 -#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SD_PULLUP */ -#define SD_PULLUP__0__MASK 0x02u -#define SD_PULLUP__0__PC CYREG_PRT3_PC1 -#define SD_PULLUP__0__PORT 3u -#define SD_PULLUP__0__SHIFT 1 -#define SD_PULLUP__1__MASK 0x04u -#define SD_PULLUP__1__PC CYREG_PRT3_PC2 -#define SD_PULLUP__1__PORT 3u -#define SD_PULLUP__1__SHIFT 2 -#define SD_PULLUP__2__MASK 0x08u -#define SD_PULLUP__2__PC CYREG_PRT3_PC3 -#define SD_PULLUP__2__PORT 3u -#define SD_PULLUP__2__SHIFT 3 -#define SD_PULLUP__3__MASK 0x10u -#define SD_PULLUP__3__PC CYREG_PRT3_PC4 -#define SD_PULLUP__3__PORT 3u -#define SD_PULLUP__3__SHIFT 4 -#define SD_PULLUP__4__MASK 0x20u -#define SD_PULLUP__4__PC CYREG_PRT3_PC5 -#define SD_PULLUP__4__PORT 3u -#define SD_PULLUP__4__SHIFT 5 -#define SD_PULLUP__AG CYREG_PRT3_AG -#define SD_PULLUP__AMUX CYREG_PRT3_AMUX -#define SD_PULLUP__BIE CYREG_PRT3_BIE -#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_PULLUP__BYP CYREG_PRT3_BYP -#define SD_PULLUP__CTL CYREG_PRT3_CTL -#define SD_PULLUP__DM0 CYREG_PRT3_DM0 -#define SD_PULLUP__DM1 CYREG_PRT3_DM1 -#define SD_PULLUP__DM2 CYREG_PRT3_DM2 -#define SD_PULLUP__DR CYREG_PRT3_DR -#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS -#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN -#define SD_PULLUP__MASK 0x3Eu -#define SD_PULLUP__PORT 3u -#define SD_PULLUP__PRT CYREG_PRT3_PRT -#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_PULLUP__PS CYREG_PRT3_PS -#define SD_PULLUP__SHIFT 1 -#define SD_PULLUP__SLW CYREG_PRT3_SLW - -/* USBFS_USB */ -#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG -#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG -#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN -#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR -#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG -#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN -#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR -#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG -#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN -#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR -#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG -#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN -#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR -#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG -#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN -#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR -#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG -#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN -#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR -#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG -#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN -#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR -#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG -#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN -#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR -#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN -#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR -#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR -#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA -#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB -#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA -#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB -#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR -#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA -#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB -#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA -#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB -#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR -#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA -#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB -#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA -#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB -#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR -#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA -#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB -#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA -#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB -#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR -#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA -#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB -#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA -#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB -#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR -#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA -#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB -#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA -#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB -#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR -#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA -#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB -#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA -#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB -#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR -#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA -#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB -#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA -#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB -#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE -#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT -#define USBFS_USB__CR0 CYREG_USB_CR0 -#define USBFS_USB__CR1 CYREG_USB_CR1 -#define USBFS_USB__CWA CYREG_USB_CWA -#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB -#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES -#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB -#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG -#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT -#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR -#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 -#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 -#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 -#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 -#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 -#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 -#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 -#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 -#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE -#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE -#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE -#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 -#define USBFS_USB__PM_ACT_MSK 0x01u -#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 -#define USBFS_USB__PM_STBY_MSK 0x01u -#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 -#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 -#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 -#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 -#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 -#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 -#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 -#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 -#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 -#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 -#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 -#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 -#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 -#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 -#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 -#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 -#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 -#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 -#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 -#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 -#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 -#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 -#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 -#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 -#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN -#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR -#define USBFS_USB__SOF0 CYREG_USB_SOF0 -#define USBFS_USB__SOF1 CYREG_USB_SOF1 -#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 -#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 -#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN - -/* SCSI_Out */ -#define SCSI_Out__0__AG CYREG_PRT4_AG -#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX -#define SCSI_Out__0__BIE CYREG_PRT4_BIE -#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out__0__BYP CYREG_PRT4_BYP -#define SCSI_Out__0__CTL CYREG_PRT4_CTL -#define SCSI_Out__0__DM0 CYREG_PRT4_DM0 -#define SCSI_Out__0__DM1 CYREG_PRT4_DM1 -#define SCSI_Out__0__DM2 CYREG_PRT4_DM2 -#define SCSI_Out__0__DR CYREG_PRT4_DR -#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out__0__MASK 0x08u -#define SCSI_Out__0__PC CYREG_PRT4_PC3 -#define SCSI_Out__0__PORT 4u -#define SCSI_Out__0__PRT CYREG_PRT4_PRT -#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out__0__PS CYREG_PRT4_PS -#define SCSI_Out__0__SHIFT 3 -#define SCSI_Out__0__SLW CYREG_PRT4_SLW -#define SCSI_Out__1__AG CYREG_PRT4_AG -#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX -#define SCSI_Out__1__BIE CYREG_PRT4_BIE -#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out__1__BYP CYREG_PRT4_BYP -#define SCSI_Out__1__CTL CYREG_PRT4_CTL -#define SCSI_Out__1__DM0 CYREG_PRT4_DM0 -#define SCSI_Out__1__DM1 CYREG_PRT4_DM1 -#define SCSI_Out__1__DM2 CYREG_PRT4_DM2 -#define SCSI_Out__1__DR CYREG_PRT4_DR -#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out__1__MASK 0x04u -#define SCSI_Out__1__PC CYREG_PRT4_PC2 -#define SCSI_Out__1__PORT 4u -#define SCSI_Out__1__PRT CYREG_PRT4_PRT -#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out__1__PS CYREG_PRT4_PS -#define SCSI_Out__1__SHIFT 2 -#define SCSI_Out__1__SLW CYREG_PRT4_SLW -#define SCSI_Out__2__AG CYREG_PRT0_AG -#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__2__BIE CYREG_PRT0_BIE -#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__2__BYP CYREG_PRT0_BYP -#define SCSI_Out__2__CTL CYREG_PRT0_CTL -#define SCSI_Out__2__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__2__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__2__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__2__DR CYREG_PRT0_DR -#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__2__MASK 0x80u -#define SCSI_Out__2__PC CYREG_PRT0_PC7 -#define SCSI_Out__2__PORT 0u -#define SCSI_Out__2__PRT CYREG_PRT0_PRT -#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__2__PS CYREG_PRT0_PS -#define SCSI_Out__2__SHIFT 7 -#define SCSI_Out__2__SLW CYREG_PRT0_SLW -#define SCSI_Out__3__AG CYREG_PRT0_AG -#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__3__BIE CYREG_PRT0_BIE -#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__3__BYP CYREG_PRT0_BYP -#define SCSI_Out__3__CTL CYREG_PRT0_CTL -#define SCSI_Out__3__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__3__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__3__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__3__DR CYREG_PRT0_DR -#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__3__MASK 0x40u -#define SCSI_Out__3__PC CYREG_PRT0_PC6 -#define SCSI_Out__3__PORT 0u -#define SCSI_Out__3__PRT CYREG_PRT0_PRT -#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__3__PS CYREG_PRT0_PS -#define SCSI_Out__3__SHIFT 6 -#define SCSI_Out__3__SLW CYREG_PRT0_SLW -#define SCSI_Out__4__AG CYREG_PRT0_AG -#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__4__BIE CYREG_PRT0_BIE -#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__4__BYP CYREG_PRT0_BYP -#define SCSI_Out__4__CTL CYREG_PRT0_CTL -#define SCSI_Out__4__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__4__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__4__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__4__DR CYREG_PRT0_DR -#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__4__MASK 0x20u -#define SCSI_Out__4__PC CYREG_PRT0_PC5 -#define SCSI_Out__4__PORT 0u -#define SCSI_Out__4__PRT CYREG_PRT0_PRT -#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__4__PS CYREG_PRT0_PS -#define SCSI_Out__4__SHIFT 5 -#define SCSI_Out__4__SLW CYREG_PRT0_SLW -#define SCSI_Out__5__AG CYREG_PRT0_AG -#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__5__BIE CYREG_PRT0_BIE -#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__5__BYP CYREG_PRT0_BYP -#define SCSI_Out__5__CTL CYREG_PRT0_CTL -#define SCSI_Out__5__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__5__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__5__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__5__DR CYREG_PRT0_DR -#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__5__MASK 0x10u -#define SCSI_Out__5__PC CYREG_PRT0_PC4 -#define SCSI_Out__5__PORT 0u -#define SCSI_Out__5__PRT CYREG_PRT0_PRT -#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__5__PS CYREG_PRT0_PS -#define SCSI_Out__5__SHIFT 4 -#define SCSI_Out__5__SLW CYREG_PRT0_SLW -#define SCSI_Out__6__AG CYREG_PRT0_AG -#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__6__BIE CYREG_PRT0_BIE -#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__6__BYP CYREG_PRT0_BYP -#define SCSI_Out__6__CTL CYREG_PRT0_CTL -#define SCSI_Out__6__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__6__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__6__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__6__DR CYREG_PRT0_DR -#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__6__MASK 0x08u -#define SCSI_Out__6__PC CYREG_PRT0_PC3 -#define SCSI_Out__6__PORT 0u -#define SCSI_Out__6__PRT CYREG_PRT0_PRT -#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__6__PS CYREG_PRT0_PS -#define SCSI_Out__6__SHIFT 3 -#define SCSI_Out__6__SLW CYREG_PRT0_SLW -#define SCSI_Out__7__AG CYREG_PRT0_AG -#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__7__BIE CYREG_PRT0_BIE -#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__7__BYP CYREG_PRT0_BYP -#define SCSI_Out__7__CTL CYREG_PRT0_CTL -#define SCSI_Out__7__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__7__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__7__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__7__DR CYREG_PRT0_DR -#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__7__MASK 0x04u -#define SCSI_Out__7__PC CYREG_PRT0_PC2 -#define SCSI_Out__7__PORT 0u -#define SCSI_Out__7__PRT CYREG_PRT0_PRT -#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__7__PS CYREG_PRT0_PS -#define SCSI_Out__7__SHIFT 2 -#define SCSI_Out__7__SLW CYREG_PRT0_SLW -#define SCSI_Out__8__AG CYREG_PRT0_AG -#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__8__BIE CYREG_PRT0_BIE -#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__8__BYP CYREG_PRT0_BYP -#define SCSI_Out__8__CTL CYREG_PRT0_CTL -#define SCSI_Out__8__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__8__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__8__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__8__DR CYREG_PRT0_DR -#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__8__MASK 0x02u -#define SCSI_Out__8__PC CYREG_PRT0_PC1 -#define SCSI_Out__8__PORT 0u -#define SCSI_Out__8__PRT CYREG_PRT0_PRT -#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__8__PS CYREG_PRT0_PS -#define SCSI_Out__8__SHIFT 1 -#define SCSI_Out__8__SLW CYREG_PRT0_SLW -#define SCSI_Out__9__AG CYREG_PRT0_AG -#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__9__BIE CYREG_PRT0_BIE -#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__9__BYP CYREG_PRT0_BYP -#define SCSI_Out__9__CTL CYREG_PRT0_CTL -#define SCSI_Out__9__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__9__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__9__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__9__DR CYREG_PRT0_DR -#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__9__MASK 0x01u -#define SCSI_Out__9__PC CYREG_PRT0_PC0 -#define SCSI_Out__9__PORT 0u -#define SCSI_Out__9__PRT CYREG_PRT0_PRT -#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__9__PS CYREG_PRT0_PS -#define SCSI_Out__9__SHIFT 0 -#define SCSI_Out__9__SLW CYREG_PRT0_SLW -#define SCSI_Out__ACK__AG CYREG_PRT0_AG -#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE -#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP -#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL -#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__ACK__DR CYREG_PRT0_DR -#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__ACK__MASK 0x40u -#define SCSI_Out__ACK__PC CYREG_PRT0_PC6 -#define SCSI_Out__ACK__PORT 0u -#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT -#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__ACK__PS CYREG_PRT0_PS -#define SCSI_Out__ACK__SHIFT 6 -#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW -#define SCSI_Out__ATN__AG CYREG_PRT4_AG -#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX -#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE -#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP -#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL -#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0 -#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1 -#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2 -#define SCSI_Out__ATN__DR CYREG_PRT4_DR -#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out__ATN__MASK 0x04u -#define SCSI_Out__ATN__PC CYREG_PRT4_PC2 -#define SCSI_Out__ATN__PORT 4u -#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT -#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out__ATN__PS CYREG_PRT4_PS -#define SCSI_Out__ATN__SHIFT 2 -#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW -#define SCSI_Out__BSY__AG CYREG_PRT0_AG -#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE -#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP -#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL -#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__BSY__DR CYREG_PRT0_DR -#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__BSY__MASK 0x80u -#define SCSI_Out__BSY__PC CYREG_PRT0_PC7 -#define SCSI_Out__BSY__PORT 0u -#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT -#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__BSY__PS CYREG_PRT0_PS -#define SCSI_Out__BSY__SHIFT 7 -#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW -#define SCSI_Out__CD__AG CYREG_PRT0_AG -#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__CD__BIE CYREG_PRT0_BIE -#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__CD__BYP CYREG_PRT0_BYP -#define SCSI_Out__CD__CTL CYREG_PRT0_CTL -#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__CD__DR CYREG_PRT0_DR -#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__CD__MASK 0x04u -#define SCSI_Out__CD__PC CYREG_PRT0_PC2 -#define SCSI_Out__CD__PORT 0u -#define SCSI_Out__CD__PRT CYREG_PRT0_PRT -#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__CD__PS CYREG_PRT0_PS -#define SCSI_Out__CD__SHIFT 2 -#define SCSI_Out__CD__SLW CYREG_PRT0_SLW -#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG -#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX -#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE -#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP -#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL -#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0 -#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1 -#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2 -#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR -#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Out__DBP_raw__MASK 0x08u -#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3 -#define SCSI_Out__DBP_raw__PORT 4u -#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT -#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS -#define SCSI_Out__DBP_raw__SHIFT 3 -#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW -#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG -#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE -#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP -#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL -#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR -#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__IO_raw__MASK 0x01u -#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0 -#define SCSI_Out__IO_raw__PORT 0u -#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT -#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS -#define SCSI_Out__IO_raw__SHIFT 0 -#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW -#define SCSI_Out__MSG__AG CYREG_PRT0_AG -#define SCSI_Out__MSG__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__MSG__BIE CYREG_PRT0_BIE -#define SCSI_Out__MSG__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__MSG__BYP CYREG_PRT0_BYP -#define SCSI_Out__MSG__CTL CYREG_PRT0_CTL -#define SCSI_Out__MSG__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__MSG__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__MSG__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__MSG__DR CYREG_PRT0_DR -#define SCSI_Out__MSG__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__MSG__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__MSG__MASK 0x10u -#define SCSI_Out__MSG__PC CYREG_PRT0_PC4 -#define SCSI_Out__MSG__PORT 0u -#define SCSI_Out__MSG__PRT CYREG_PRT0_PRT -#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__MSG__PS CYREG_PRT0_PS -#define SCSI_Out__MSG__SHIFT 4 -#define SCSI_Out__MSG__SLW CYREG_PRT0_SLW -#define SCSI_Out__REQ__AG CYREG_PRT0_AG -#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE -#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP -#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL -#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__REQ__DR CYREG_PRT0_DR -#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__REQ__MASK 0x02u -#define SCSI_Out__REQ__PC CYREG_PRT0_PC1 -#define SCSI_Out__REQ__PORT 0u -#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT -#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__REQ__PS CYREG_PRT0_PS -#define SCSI_Out__REQ__SHIFT 1 -#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW -#define SCSI_Out__RST__AG CYREG_PRT0_AG -#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__RST__BIE CYREG_PRT0_BIE -#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__RST__BYP CYREG_PRT0_BYP -#define SCSI_Out__RST__CTL CYREG_PRT0_CTL -#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__RST__DR CYREG_PRT0_DR -#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__RST__MASK 0x20u -#define SCSI_Out__RST__PC CYREG_PRT0_PC5 -#define SCSI_Out__RST__PORT 0u -#define SCSI_Out__RST__PRT CYREG_PRT0_PRT -#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__RST__PS CYREG_PRT0_PS -#define SCSI_Out__RST__SHIFT 5 -#define SCSI_Out__RST__SLW CYREG_PRT0_SLW -#define SCSI_Out__SEL__AG CYREG_PRT0_AG -#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX -#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE -#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP -#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL -#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0 -#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1 -#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2 -#define SCSI_Out__SEL__DR CYREG_PRT0_DR -#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_Out__SEL__MASK 0x08u -#define SCSI_Out__SEL__PC CYREG_PRT0_PC3 -#define SCSI_Out__SEL__PORT 0u -#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT -#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_Out__SEL__PS CYREG_PRT0_PS -#define SCSI_Out__SEL__SHIFT 3 -#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW - -/* USBFS_Dm */ -#define USBFS_Dm__0__MASK 0x80u -#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 -#define USBFS_Dm__0__PORT 15u -#define USBFS_Dm__0__SHIFT 7 -#define USBFS_Dm__AG CYREG_PRT15_AG -#define USBFS_Dm__AMUX CYREG_PRT15_AMUX -#define USBFS_Dm__BIE CYREG_PRT15_BIE -#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dm__BYP CYREG_PRT15_BYP -#define USBFS_Dm__CTL CYREG_PRT15_CTL -#define USBFS_Dm__DM0 CYREG_PRT15_DM0 -#define USBFS_Dm__DM1 CYREG_PRT15_DM1 -#define USBFS_Dm__DM2 CYREG_PRT15_DM2 -#define USBFS_Dm__DR CYREG_PRT15_DR -#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dm__MASK 0x80u -#define USBFS_Dm__PORT 15u -#define USBFS_Dm__PRT CYREG_PRT15_PRT -#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dm__PS CYREG_PRT15_PS -#define USBFS_Dm__SHIFT 7 -#define USBFS_Dm__SLW CYREG_PRT15_SLW - -/* USBFS_Dp */ -#define USBFS_Dp__0__MASK 0x40u -#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 -#define USBFS_Dp__0__PORT 15u -#define USBFS_Dp__0__SHIFT 6 -#define USBFS_Dp__AG CYREG_PRT15_AG -#define USBFS_Dp__AMUX CYREG_PRT15_AMUX -#define USBFS_Dp__BIE CYREG_PRT15_BIE -#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dp__BYP CYREG_PRT15_BYP -#define USBFS_Dp__CTL CYREG_PRT15_CTL -#define USBFS_Dp__DM0 CYREG_PRT15_DM0 -#define USBFS_Dp__DM1 CYREG_PRT15_DM1 -#define USBFS_Dp__DM2 CYREG_PRT15_DM2 -#define USBFS_Dp__DR CYREG_PRT15_DR -#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT -#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dp__MASK 0x40u -#define USBFS_Dp__PORT 15u -#define USBFS_Dp__PRT CYREG_PRT15_PRT -#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dp__PS CYREG_PRT15_PS -#define USBFS_Dp__SHIFT 6 -#define USBFS_Dp__SLW CYREG_PRT15_SLW -#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 - -/* Miscellaneous */ -/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ -#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0 -#define CYDEV_DEBUGGING_DPS_SWD_SWV 6 -#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 -#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 -#define CYDEV_CONFIG_FASTBOOT_ENABLED 1 -#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u -#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u -#define CYDEV_CHIP_MEMBER_5B 4u -#define CYDEV_CHIP_FAMILY_PSOC5 3u -#define CYDEV_CHIP_DIE_PSOC5LP 4u -#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP -#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1 -#define BCLK__BUS_CLK__HZ 64000000U -#define BCLK__BUS_CLK__KHZ 64000U -#define BCLK__BUS_CLK__MHZ 64U -#define CYDEV_BOOTLOADER_APPLICATIONS 1u -#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0 -#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1 -#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS -#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT -#define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PANTHER 3u -#define CYDEV_CHIP_DIE_PSOC4A 2u -#define CYDEV_CHIP_DIE_UNKNOWN 0u -#define CYDEV_CHIP_FAMILY_PSOC3 1u -#define CYDEV_CHIP_FAMILY_PSOC4 2u -#define CYDEV_CHIP_FAMILY_UNKNOWN 0u -#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 -#define CYDEV_CHIP_JTAG_ID 0x2E133069u -#define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 2u -#define CYDEV_CHIP_MEMBER_5A 3u -#define CYDEV_CHIP_MEMBER_UNKNOWN 0u -#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B -#define CYDEV_CHIP_REVISION_3A_ES1 0u -#define CYDEV_CHIP_REVISION_3A_ES2 1u -#define CYDEV_CHIP_REVISION_3A_ES3 3u -#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u -#define CYDEV_CHIP_REVISION_4A_ES0 17u -#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u -#define CYDEV_CHIP_REVISION_5A_ES0 0u -#define CYDEV_CHIP_REVISION_5A_ES1 1u -#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u -#define CYDEV_CHIP_REVISION_5B_ES0 0u -#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION -#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION -#define CYDEV_CHIP_REV_LEOPARD_ES1 0u -#define CYDEV_CHIP_REV_LEOPARD_ES2 1u -#define CYDEV_CHIP_REV_LEOPARD_ES3 3u -#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u -#define CYDEV_CHIP_REV_PANTHER_ES0 0u -#define CYDEV_CHIP_REV_PANTHER_ES1 1u -#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u -#define CYDEV_CHIP_REV_PSOC4A_ES0 17u -#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u -#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u -#define CYDEV_CONFIGURATION_COMPRESSED 1 -#define CYDEV_CONFIGURATION_DMA 0 -#define CYDEV_CONFIGURATION_ECC 0 -#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED -#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED -#define CYDEV_CONFIGURATION_MODE_DMA 2 -#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 -#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn -#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 -#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 -#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV -#define CYDEV_DEBUGGING_DPS_Disable 3 -#define CYDEV_DEBUGGING_DPS_JTAG_4 1 -#define CYDEV_DEBUGGING_DPS_JTAG_5 0 -#define CYDEV_DEBUGGING_DPS_SWD 2 -#define CYDEV_DEBUGGING_ENABLE 1 -#define CYDEV_DEBUGGING_XRES 0 -#define CYDEV_DEBUG_ENABLE_MASK 0x20u -#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG -#define CYDEV_DMA_CHANNELS_AVAILABLE 24u -#define CYDEV_ECC_ENABLE 0 -#define CYDEV_HEAP_SIZE 0x0800 -#define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x00000000u -#define CYDEV_PROJ_TYPE 1 -#define CYDEV_PROJ_TYPE_BOOTLOADER 1 -#define CYDEV_PROJ_TYPE_LOADABLE 2 -#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 -#define CYDEV_PROJ_TYPE_STANDARD 0 -#define CYDEV_PROTECTION_ENABLE 0 -#define CYDEV_STACK_SIZE 0x2000 -#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP -#define CYDEV_USE_BUNDLED_CMSIS 1 -#define CYDEV_VARIABLE_VDDA 0 -#define CYDEV_VDDA 5.0 -#define CYDEV_VDDA_MV 5000 -#define CYDEV_VDDD 5.0 -#define CYDEV_VDDD_MV 5000 -#define CYDEV_VDDIO0 5.0 -#define CYDEV_VDDIO0_MV 5000 -#define CYDEV_VDDIO1 5.0 -#define CYDEV_VDDIO1_MV 5000 -#define CYDEV_VDDIO2 5.0 -#define CYDEV_VDDIO2_MV 5000 -#define CYDEV_VDDIO3 5.0 -#define CYDEV_VDDIO3_MV 5000 -#define CYDEV_VIO0 5 -#define CYDEV_VIO0_MV 5000 -#define CYDEV_VIO1 5 -#define CYDEV_VIO1_MV 5000 -#define CYDEV_VIO2 5 -#define CYDEV_VIO2_MV 5000 -#define CYDEV_VIO3 5 -#define CYDEV_VIO3_MV 5000 -#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO -#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS -#define DMA_CHANNELS_USED__MASK0 0x00000000u -#define CYDEV_BOOTLOADER_ENABLE 1 - -#endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c deleted file mode 100755 index c15b7b6..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.c +++ /dev/null @@ -1,435 +0,0 @@ -/******************************************************************************* -* FILENAME: cyfitter_cfg.c -* PSoC Creator 3.0 Component Pack 7 -* -* Description: -* This file is automatically generated by PSoC Creator with device -* initialization code. Except for the user defined sections in -* CyClockStartupError(), this file should not be modified. -* -******************************************************************************** -* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#define CY_NEED_CYCLOCKSTARTUPERROR 1 - - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) - #define CYPACKED - #define CYPACKED_ATTR __attribute__ ((packed)) - #define CYALIGNED __attribute__ ((aligned)) - #define CY_CFG_UNUSED __attribute__ ((unused)) - #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) - - #if defined(__ARMCC_VERSION) - #define CY_CFG_MEMORY_BARRIER() __memory_changed() - #else - #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() - #endif - -#elif defined(__ICCARM__) - #include - - #define CYPACKED __packed - #define CYPACKED_ATTR - #define CYALIGNED _Pragma("data_alignment=4") - #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") - #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") - - #define CY_CFG_MEMORY_BARRIER() __DMB() - -#else - #error Unsupported toolchain -#endif - - -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n); -CY_CFG_UNUSED -static void CYMEMZERO(void *s, size_t n) -{ - (void)memset(s, 0, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPY(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); -CY_CFG_UNUSED -static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) -{ - (void)memcpy(dest, src, n); -} - - - -/* Clock startup error codes */ -#define CYCLOCKSTART_NO_ERROR 0u -#define CYCLOCKSTART_XTAL_ERROR 1u -#define CYCLOCKSTART_32KHZ_ERROR 2u -#define CYCLOCKSTART_PLL_ERROR 3u - -#ifdef CY_NEED_CYCLOCKSTARTUPERROR -/******************************************************************************* -* Function Name: CyClockStartupError -******************************************************************************** -* Summary: -* If an error is encountered during clock configuration (crystal startup error, -* PLL lock error, etc.), the system will end up here. Unless reimplemented by -* the customer, this function will stop in an infinite loop. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ -CY_CFG_UNUSED -static void CyClockStartupError(uint8 errorCode); -CY_CFG_UNUSED -static void CyClockStartupError(uint8 errorCode) -{ - /* To remove the compiler warning if errorCode not used. */ - errorCode = errorCode; - - /* `#START CyClockStartupError` */ - - /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ - /* we will end up here to allow the customer to implement something to */ - /* deal with the clock condition. */ - - /* `#END` */ - - /* If nothing else, stop here since the clocks have not started */ - /* correctly. */ - while(1) {} -} -#endif - -#define CY_CFG_BASE_ADDR_COUNT 12u -CYPACKED typedef struct -{ - uint8 offset; - uint8 value; -} CYPACKED_ATTR cy_cfg_addrvalue_t; - - - -/******************************************************************************* -* Function Name: cfg_write_bytes32 -******************************************************************************** -* Summary: -* This function is used for setting up the chip configuration areas that -* contain relatively sparse data. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); -static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) -{ - /* For 32-bit little-endian architectures */ - uint32 i, j = 0u; - for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) - { - uint32 baseAddr = addr_table[i]; - uint8 count = (uint8)baseAddr; - baseAddr &= 0xFFFFFF00u; - while (count != 0u) - { - CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value); - j++; - count--; - } - } -} - -/******************************************************************************* -* Function Name: ClockSetup -******************************************************************************** -* -* Summary: -* Performs the initialization of all of the clocks in the device based on the -* settings in the Clock tab of the DWR. This includes enabling the requested -* clocks and setting the necessary dividers to produce the desired frequency. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ -static void ClockSetup(void); -static void ClockSetup(void) -{ - uint32 timeout; - uint8 pllLock; - - - /* Configure ILO based on settings from Clock DWR */ - CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); - - /* Configure IMO based on settings from Clock DWR */ - CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); - - /* Configure PLL based on settings from Clock DWR */ - CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); - /* Wait up to 250us for the PLL to lock */ - pllLock = 0u; - for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) - { - pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); - CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ - } - /* If we ran out of time the PLL didn't lock so go to the error function */ - if (timeout == 0u) - { - CyClockStartupError(CYCLOCKSTART_PLL_ERROR); - } - - /* Configure Bus/Master Clock based on settings from Clock DWR */ - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); - - /* Configure USB Clock based on settings from Clock DWR */ - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); -} - - -/* Analog API Functions */ - - -/******************************************************************************* -* Function Name: AnalogSetDefault -******************************************************************************** -* -* Summary: -* Sets up the analog portions of the chip to default values based on chip -* configuration options from the project. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ -static void AnalogSetDefault(void); -static void AnalogSetDefault(void) -{ - uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); - CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); -} - - -/******************************************************************************* -* Function Name: SetAnalogRoutingPumps -******************************************************************************** -* -* Summary: -* Enables or disables the analog pumps feeding analog routing switches. -* Intended to be called at startup, based on the Vdda system configuration; -* may be called during operation when the user informs us that the Vdda voltage -* crossed the pump threshold. -* -* Parameters: -* enabled - 1 to enable the pumps, 0 to disable the pumps -* -* Return: -* void -* -*******************************************************************************/ -void SetAnalogRoutingPumps(uint8 enabled) -{ - uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); - if (enabled != 0u) - { - regValue |= 0x00u; - } - else - { - regValue &= (uint8)~0x00u; - } - CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); -} - -#define CY_AMUX_UNUSED CYREG_BOOST_SR - - -/******************************************************************************* -* Function Name: cyfitter_cfg -******************************************************************************** -* Summary: -* This function is called by the start-up code for the selected device. It -* performs all of the necessary device configuration based on the design -* settings. This includes settings from the Design Wide Resources (DWR) such -* as Clocks and Pins as well as any component configuration that is necessary. -* -* Parameters: -* void -* -* Return: -* void -* -*******************************************************************************/ - -void cyfitter_cfg(void) -{ - /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */ - static const uint8 CYCODE BS_IOPINS0_0_VAL[] = { - 0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - - /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ - static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; - - /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ - static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { - 0x00u, 0x3Eu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - - /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ - static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { - 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - - /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ - static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { - 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - -#ifdef CYGlobalIntDisable - /* Disable interrupts by default. Let user enable if/when they want. */ - CYGlobalIntDisable -#endif - - - /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); - /* Setup clocks based on selections from Clock DWR */ - ClockSetup(); - /* Enable/Disable Debug functionality based on settings from System DWR */ - CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); - - { - static const uint32 CYCODE cy_cfg_addr_table[] = { - 0x40004501u, /* Base address: 0x40004500 Count: 1 */ - 0x40005202u, /* Base address: 0x40005200 Count: 2 */ - 0x40011701u, /* Base address: 0x40011700 Count: 1 */ - 0x40011901u, /* Base address: 0x40011900 Count: 1 */ - 0x40014003u, /* Base address: 0x40014000 Count: 3 */ - 0x40014102u, /* Base address: 0x40014100 Count: 2 */ - 0x40014202u, /* Base address: 0x40014200 Count: 2 */ - 0x40014302u, /* Base address: 0x40014300 Count: 2 */ - 0x40014703u, /* Base address: 0x40014700 Count: 3 */ - 0x40014803u, /* Base address: 0x40014800 Count: 3 */ - 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ - 0x40015101u, /* Base address: 0x40015100 Count: 1 */ - }; - - static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { - {0x7Eu, 0x02u}, - {0x1Cu, 0x3Eu}, - {0x7Cu, 0x40u}, - {0xEEu, 0x0Au}, - {0xEEu, 0x0Au}, - {0x33u, 0x80u}, - {0x36u, 0x40u}, - {0xCCu, 0x30u}, - {0xA6u, 0x40u}, - {0xA7u, 0x80u}, - {0xA6u, 0x40u}, - {0xA7u, 0x80u}, - {0xA6u, 0x40u}, - {0xA7u, 0x80u}, - {0x08u, 0x08u}, - {0x0Fu, 0x40u}, - {0xC2u, 0x0Cu}, - {0xAEu, 0x40u}, - {0xAFu, 0x80u}, - {0xEEu, 0x50u}, - {0xACu, 0x08u}, - {0xAFu, 0x40u}, - {0x00u, 0x0Au}, - }; - - - - CYPACKED typedef struct { - void CYFAR *address; - uint16 size; - } CYPACKED_ATTR cfg_memset_t; - - static const cfg_memset_t CYCODE cfg_memset_list [] = { - /* address, size */ - {(void CYFAR *)(CYREG_PRT1_DR), 32u}, - {(void CYFAR *)(CYREG_PRT5_DR), 16u}, - {(void CYFAR *)(CYREG_PRT12_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, - {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, - {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, - {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, - }; - - uint8 CYDATA i; - - /* Zero out critical memory blocks before beginning configuration */ - for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) - { - const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; - CYMEMZERO(ms->address, (uint32)(ms->size)); - } - - cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); - - /* Enable digital routing */ - CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); - CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); - - /* Enable UDB array */ - CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); - CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); - } - - /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ - CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); - CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); - CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); - CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); - CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); - - /* Switch Boost to the precision bandgap reference from its internal reference */ - CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u)); - - /* Perform basic analog initialization to defaults */ - AnalogSetDefault(); - - /* Configure alternate active mode */ - CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u); -} diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h deleted file mode 100755 index 9481fd3..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitter_cfg.h +++ /dev/null @@ -1,28 +0,0 @@ -/******************************************************************************* -* FILENAME: cyfitter_cfg.h -* PSoC Creator 3.0 Component Pack 7 -* -* Description: -* This file is automatically generated by PSoC Creator. -* -******************************************************************************** -* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - -#ifndef CYFITTER_CFG_H -#define CYFITTER_CFG_H - -#include - -extern void cyfitter_cfg(void); - -/* Analog Set/Unset methods */ -extern void SetAnalogRoutingPumps(uint8 enabled); - - -#endif /* CYFITTER_CFG_H */ - -/*[]*/ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc deleted file mode 100755 index e370ffa..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfittergnu.inc +++ /dev/null @@ -1,1402 +0,0 @@ -.ifndef INCLUDED_CYFITTERGNU_INC -.set INCLUDED_CYFITTERGNU_INC, 1 -.include "cydevicegnu.inc" -.include "cydevicegnu_trm.inc" - -/* USBFS_bus_reset */ -.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_bus_reset__INTC_MASK, 0x800000 -.set USBFS_bus_reset__INTC_NUMBER, 23 -.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 -.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 -.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_arb_int */ -.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_arb_int__INTC_MASK, 0x400000 -.set USBFS_arb_int__INTC_NUMBER, 22 -.set USBFS_arb_int__INTC_PRIOR_NUM, 7 -.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 -.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_sof_int__INTC_MASK, 0x200000 -.set USBFS_sof_int__INTC_NUMBER, 21 -.set USBFS_sof_int__INTC_PRIOR_NUM, 7 -.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 -.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_Out_DBx */ -.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__0__MASK, 0x08 -.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3 -.set SCSI_Out_DBx__0__PORT, 6 -.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__0__SHIFT, 3 -.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__1__MASK, 0x04 -.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2 -.set SCSI_Out_DBx__1__PORT, 6 -.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__1__SHIFT, 2 -.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__2__MASK, 0x02 -.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1 -.set SCSI_Out_DBx__2__PORT, 6 -.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__2__SHIFT, 1 -.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__3__MASK, 0x01 -.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0 -.set SCSI_Out_DBx__3__PORT, 6 -.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__3__SHIFT, 0 -.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__4__MASK, 0x80 -.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7 -.set SCSI_Out_DBx__4__PORT, 4 -.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__4__SHIFT, 7 -.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW -.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__5__MASK, 0x40 -.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6 -.set SCSI_Out_DBx__5__PORT, 4 -.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__5__SHIFT, 6 -.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW -.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__6__MASK, 0x20 -.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5 -.set SCSI_Out_DBx__6__PORT, 4 -.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__6__SHIFT, 5 -.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW -.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__7__MASK, 0x10 -.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4 -.set SCSI_Out_DBx__7__PORT, 4 -.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__7__SHIFT, 4 -.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW -.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__DB0__MASK, 0x08 -.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3 -.set SCSI_Out_DBx__DB0__PORT, 6 -.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__DB0__SHIFT, 3 -.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__DB1__MASK, 0x04 -.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2 -.set SCSI_Out_DBx__DB1__PORT, 6 -.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__DB1__SHIFT, 2 -.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__DB2__MASK, 0x02 -.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1 -.set SCSI_Out_DBx__DB2__PORT, 6 -.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__DB2__SHIFT, 1 -.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG -.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX -.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE -.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP -.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL -.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0 -.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1 -.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2 -.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR -.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Out_DBx__DB3__MASK, 0x01 -.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0 -.set SCSI_Out_DBx__DB3__PORT, 6 -.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT -.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS -.set SCSI_Out_DBx__DB3__SHIFT, 0 -.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW -.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__DB4__MASK, 0x80 -.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7 -.set SCSI_Out_DBx__DB4__PORT, 4 -.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__DB4__SHIFT, 7 -.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW -.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__DB5__MASK, 0x40 -.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6 -.set SCSI_Out_DBx__DB5__PORT, 4 -.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__DB5__SHIFT, 6 -.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW -.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__DB6__MASK, 0x20 -.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5 -.set SCSI_Out_DBx__DB6__PORT, 4 -.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__DB6__SHIFT, 5 -.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW -.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG -.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE -.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP -.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL -.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0 -.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1 -.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2 -.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR -.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out_DBx__DB7__MASK, 0x10 -.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4 -.set SCSI_Out_DBx__DB7__PORT, 4 -.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT -.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS -.set SCSI_Out_DBx__DB7__SHIFT, 4 -.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW - -/* USBFS_dp_int */ -.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_dp_int__INTC_MASK, 0x1000 -.set USBFS_dp_int__INTC_NUMBER, 12 -.set USBFS_dp_int__INTC_PRIOR_NUM, 7 -.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 -.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_0__INTC_MASK, 0x1000000 -.set USBFS_ep_0__INTC_NUMBER, 24 -.set USBFS_ep_0__INTC_PRIOR_NUM, 7 -.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 -.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x01 -.set USBFS_ep_1__INTC_NUMBER, 0 -.set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 -.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x02 -.set USBFS_ep_2__INTC_NUMBER, 1 -.set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 -.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SD_PULLUP */ -.set SD_PULLUP__0__MASK, 0x02 -.set SD_PULLUP__0__PC, CYREG_PRT3_PC1 -.set SD_PULLUP__0__PORT, 3 -.set SD_PULLUP__0__SHIFT, 1 -.set SD_PULLUP__1__MASK, 0x04 -.set SD_PULLUP__1__PC, CYREG_PRT3_PC2 -.set SD_PULLUP__1__PORT, 3 -.set SD_PULLUP__1__SHIFT, 2 -.set SD_PULLUP__2__MASK, 0x08 -.set SD_PULLUP__2__PC, CYREG_PRT3_PC3 -.set SD_PULLUP__2__PORT, 3 -.set SD_PULLUP__2__SHIFT, 3 -.set SD_PULLUP__3__MASK, 0x10 -.set SD_PULLUP__3__PC, CYREG_PRT3_PC4 -.set SD_PULLUP__3__PORT, 3 -.set SD_PULLUP__3__SHIFT, 4 -.set SD_PULLUP__4__MASK, 0x20 -.set SD_PULLUP__4__PC, CYREG_PRT3_PC5 -.set SD_PULLUP__4__PORT, 3 -.set SD_PULLUP__4__SHIFT, 5 -.set SD_PULLUP__AG, CYREG_PRT3_AG -.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX -.set SD_PULLUP__BIE, CYREG_PRT3_BIE -.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_PULLUP__BYP, CYREG_PRT3_BYP -.set SD_PULLUP__CTL, CYREG_PRT3_CTL -.set SD_PULLUP__DM0, CYREG_PRT3_DM0 -.set SD_PULLUP__DM1, CYREG_PRT3_DM1 -.set SD_PULLUP__DM2, CYREG_PRT3_DM2 -.set SD_PULLUP__DR, CYREG_PRT3_DR -.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_PULLUP__MASK, 0x3E -.set SD_PULLUP__PORT, 3 -.set SD_PULLUP__PRT, CYREG_PRT3_PRT -.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_PULLUP__PS, CYREG_PRT3_PS -.set SD_PULLUP__SHIFT, 1 -.set SD_PULLUP__SLW, CYREG_PRT3_SLW - -/* USBFS_USB */ -.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG -.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG -.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN -.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR -.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG -.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN -.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR -.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG -.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN -.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR -.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG -.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN -.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR -.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG -.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN -.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR -.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG -.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN -.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR -.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG -.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN -.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR -.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG -.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN -.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR -.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN -.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR -.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR -.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA -.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB -.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA -.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB -.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR -.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA -.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB -.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA -.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB -.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR -.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA -.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB -.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA -.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB -.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR -.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA -.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB -.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA -.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB -.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR -.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA -.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB -.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA -.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB -.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR -.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA -.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB -.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA -.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB -.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR -.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA -.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB -.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA -.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB -.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR -.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA -.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB -.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA -.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB -.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE -.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT -.set USBFS_USB__CR0, CYREG_USB_CR0 -.set USBFS_USB__CR1, CYREG_USB_CR1 -.set USBFS_USB__CWA, CYREG_USB_CWA -.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB -.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES -.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB -.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG -.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT -.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR -.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 -.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 -.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 -.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 -.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 -.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 -.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 -.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 -.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE -.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE -.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE -.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 -.set USBFS_USB__PM_ACT_MSK, 0x01 -.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 -.set USBFS_USB__PM_STBY_MSK, 0x01 -.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 -.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 -.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 -.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 -.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 -.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 -.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 -.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 -.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 -.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 -.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 -.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 -.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 -.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 -.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 -.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 -.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 -.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 -.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 -.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 -.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 -.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 -.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 -.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 -.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN -.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR -.set USBFS_USB__SOF0, CYREG_USB_SOF0 -.set USBFS_USB__SOF1, CYREG_USB_SOF1 -.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 -.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 -.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN - -/* SCSI_Out */ -.set SCSI_Out__0__AG, CYREG_PRT4_AG -.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out__0__BIE, CYREG_PRT4_BIE -.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out__0__BYP, CYREG_PRT4_BYP -.set SCSI_Out__0__CTL, CYREG_PRT4_CTL -.set SCSI_Out__0__DM0, CYREG_PRT4_DM0 -.set SCSI_Out__0__DM1, CYREG_PRT4_DM1 -.set SCSI_Out__0__DM2, CYREG_PRT4_DM2 -.set SCSI_Out__0__DR, CYREG_PRT4_DR -.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out__0__MASK, 0x08 -.set SCSI_Out__0__PC, CYREG_PRT4_PC3 -.set SCSI_Out__0__PORT, 4 -.set SCSI_Out__0__PRT, CYREG_PRT4_PRT -.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out__0__PS, CYREG_PRT4_PS -.set SCSI_Out__0__SHIFT, 3 -.set SCSI_Out__0__SLW, CYREG_PRT4_SLW -.set SCSI_Out__1__AG, CYREG_PRT4_AG -.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out__1__BIE, CYREG_PRT4_BIE -.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out__1__BYP, CYREG_PRT4_BYP -.set SCSI_Out__1__CTL, CYREG_PRT4_CTL -.set SCSI_Out__1__DM0, CYREG_PRT4_DM0 -.set SCSI_Out__1__DM1, CYREG_PRT4_DM1 -.set SCSI_Out__1__DM2, CYREG_PRT4_DM2 -.set SCSI_Out__1__DR, CYREG_PRT4_DR -.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out__1__MASK, 0x04 -.set SCSI_Out__1__PC, CYREG_PRT4_PC2 -.set SCSI_Out__1__PORT, 4 -.set SCSI_Out__1__PRT, CYREG_PRT4_PRT -.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out__1__PS, CYREG_PRT4_PS -.set SCSI_Out__1__SHIFT, 2 -.set SCSI_Out__1__SLW, CYREG_PRT4_SLW -.set SCSI_Out__2__AG, CYREG_PRT0_AG -.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__2__BIE, CYREG_PRT0_BIE -.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__2__BYP, CYREG_PRT0_BYP -.set SCSI_Out__2__CTL, CYREG_PRT0_CTL -.set SCSI_Out__2__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__2__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__2__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__2__DR, CYREG_PRT0_DR -.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__2__MASK, 0x80 -.set SCSI_Out__2__PC, CYREG_PRT0_PC7 -.set SCSI_Out__2__PORT, 0 -.set SCSI_Out__2__PRT, CYREG_PRT0_PRT -.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__2__PS, CYREG_PRT0_PS -.set SCSI_Out__2__SHIFT, 7 -.set SCSI_Out__2__SLW, CYREG_PRT0_SLW -.set SCSI_Out__3__AG, CYREG_PRT0_AG -.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__3__BIE, CYREG_PRT0_BIE -.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__3__BYP, CYREG_PRT0_BYP -.set SCSI_Out__3__CTL, CYREG_PRT0_CTL -.set SCSI_Out__3__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__3__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__3__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__3__DR, CYREG_PRT0_DR -.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__3__MASK, 0x40 -.set SCSI_Out__3__PC, CYREG_PRT0_PC6 -.set SCSI_Out__3__PORT, 0 -.set SCSI_Out__3__PRT, CYREG_PRT0_PRT -.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__3__PS, CYREG_PRT0_PS -.set SCSI_Out__3__SHIFT, 6 -.set SCSI_Out__3__SLW, CYREG_PRT0_SLW -.set SCSI_Out__4__AG, CYREG_PRT0_AG -.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__4__BIE, CYREG_PRT0_BIE -.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__4__BYP, CYREG_PRT0_BYP -.set SCSI_Out__4__CTL, CYREG_PRT0_CTL -.set SCSI_Out__4__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__4__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__4__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__4__DR, CYREG_PRT0_DR -.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__4__MASK, 0x20 -.set SCSI_Out__4__PC, CYREG_PRT0_PC5 -.set SCSI_Out__4__PORT, 0 -.set SCSI_Out__4__PRT, CYREG_PRT0_PRT -.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__4__PS, CYREG_PRT0_PS -.set SCSI_Out__4__SHIFT, 5 -.set SCSI_Out__4__SLW, CYREG_PRT0_SLW -.set SCSI_Out__5__AG, CYREG_PRT0_AG -.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__5__BIE, CYREG_PRT0_BIE -.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__5__BYP, CYREG_PRT0_BYP -.set SCSI_Out__5__CTL, CYREG_PRT0_CTL -.set SCSI_Out__5__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__5__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__5__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__5__DR, CYREG_PRT0_DR -.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__5__MASK, 0x10 -.set SCSI_Out__5__PC, CYREG_PRT0_PC4 -.set SCSI_Out__5__PORT, 0 -.set SCSI_Out__5__PRT, CYREG_PRT0_PRT -.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__5__PS, CYREG_PRT0_PS -.set SCSI_Out__5__SHIFT, 4 -.set SCSI_Out__5__SLW, CYREG_PRT0_SLW -.set SCSI_Out__6__AG, CYREG_PRT0_AG -.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__6__BIE, CYREG_PRT0_BIE -.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__6__BYP, CYREG_PRT0_BYP -.set SCSI_Out__6__CTL, CYREG_PRT0_CTL -.set SCSI_Out__6__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__6__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__6__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__6__DR, CYREG_PRT0_DR -.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__6__MASK, 0x08 -.set SCSI_Out__6__PC, CYREG_PRT0_PC3 -.set SCSI_Out__6__PORT, 0 -.set SCSI_Out__6__PRT, CYREG_PRT0_PRT -.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__6__PS, CYREG_PRT0_PS -.set SCSI_Out__6__SHIFT, 3 -.set SCSI_Out__6__SLW, CYREG_PRT0_SLW -.set SCSI_Out__7__AG, CYREG_PRT0_AG -.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__7__BIE, CYREG_PRT0_BIE -.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__7__BYP, CYREG_PRT0_BYP -.set SCSI_Out__7__CTL, CYREG_PRT0_CTL -.set SCSI_Out__7__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__7__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__7__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__7__DR, CYREG_PRT0_DR -.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__7__MASK, 0x04 -.set SCSI_Out__7__PC, CYREG_PRT0_PC2 -.set SCSI_Out__7__PORT, 0 -.set SCSI_Out__7__PRT, CYREG_PRT0_PRT -.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__7__PS, CYREG_PRT0_PS -.set SCSI_Out__7__SHIFT, 2 -.set SCSI_Out__7__SLW, CYREG_PRT0_SLW -.set SCSI_Out__8__AG, CYREG_PRT0_AG -.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__8__BIE, CYREG_PRT0_BIE -.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__8__BYP, CYREG_PRT0_BYP -.set SCSI_Out__8__CTL, CYREG_PRT0_CTL -.set SCSI_Out__8__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__8__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__8__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__8__DR, CYREG_PRT0_DR -.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__8__MASK, 0x02 -.set SCSI_Out__8__PC, CYREG_PRT0_PC1 -.set SCSI_Out__8__PORT, 0 -.set SCSI_Out__8__PRT, CYREG_PRT0_PRT -.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__8__PS, CYREG_PRT0_PS -.set SCSI_Out__8__SHIFT, 1 -.set SCSI_Out__8__SLW, CYREG_PRT0_SLW -.set SCSI_Out__9__AG, CYREG_PRT0_AG -.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__9__BIE, CYREG_PRT0_BIE -.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__9__BYP, CYREG_PRT0_BYP -.set SCSI_Out__9__CTL, CYREG_PRT0_CTL -.set SCSI_Out__9__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__9__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__9__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__9__DR, CYREG_PRT0_DR -.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__9__MASK, 0x01 -.set SCSI_Out__9__PC, CYREG_PRT0_PC0 -.set SCSI_Out__9__PORT, 0 -.set SCSI_Out__9__PRT, CYREG_PRT0_PRT -.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__9__PS, CYREG_PRT0_PS -.set SCSI_Out__9__SHIFT, 0 -.set SCSI_Out__9__SLW, CYREG_PRT0_SLW -.set SCSI_Out__ACK__AG, CYREG_PRT0_AG -.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE -.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP -.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL -.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__ACK__DR, CYREG_PRT0_DR -.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__ACK__MASK, 0x40 -.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6 -.set SCSI_Out__ACK__PORT, 0 -.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT -.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__ACK__PS, CYREG_PRT0_PS -.set SCSI_Out__ACK__SHIFT, 6 -.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW -.set SCSI_Out__ATN__AG, CYREG_PRT4_AG -.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE -.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP -.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL -.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0 -.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1 -.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2 -.set SCSI_Out__ATN__DR, CYREG_PRT4_DR -.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out__ATN__MASK, 0x04 -.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2 -.set SCSI_Out__ATN__PORT, 4 -.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT -.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out__ATN__PS, CYREG_PRT4_PS -.set SCSI_Out__ATN__SHIFT, 2 -.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW -.set SCSI_Out__BSY__AG, CYREG_PRT0_AG -.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE -.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP -.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL -.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__BSY__DR, CYREG_PRT0_DR -.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__BSY__MASK, 0x80 -.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7 -.set SCSI_Out__BSY__PORT, 0 -.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT -.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__BSY__PS, CYREG_PRT0_PS -.set SCSI_Out__BSY__SHIFT, 7 -.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW -.set SCSI_Out__CD__AG, CYREG_PRT0_AG -.set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__CD__BIE, CYREG_PRT0_BIE -.set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__CD__BYP, CYREG_PRT0_BYP -.set SCSI_Out__CD__CTL, CYREG_PRT0_CTL -.set SCSI_Out__CD__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__CD__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__CD__DR, CYREG_PRT0_DR -.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__CD__MASK, 0x04 -.set SCSI_Out__CD__PC, CYREG_PRT0_PC2 -.set SCSI_Out__CD__PORT, 0 -.set SCSI_Out__CD__PRT, CYREG_PRT0_PRT -.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__CD__PS, CYREG_PRT0_PS -.set SCSI_Out__CD__SHIFT, 2 -.set SCSI_Out__CD__SLW, CYREG_PRT0_SLW -.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG -.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX -.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE -.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP -.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL -.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0 -.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1 -.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2 -.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR -.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Out__DBP_raw__MASK, 0x08 -.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3 -.set SCSI_Out__DBP_raw__PORT, 4 -.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT -.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS -.set SCSI_Out__DBP_raw__SHIFT, 3 -.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW -.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG -.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE -.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP -.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL -.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR -.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__IO_raw__MASK, 0x01 -.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0 -.set SCSI_Out__IO_raw__PORT, 0 -.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT -.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS -.set SCSI_Out__IO_raw__SHIFT, 0 -.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW -.set SCSI_Out__MSG__AG, CYREG_PRT0_AG -.set SCSI_Out__MSG__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__MSG__BIE, CYREG_PRT0_BIE -.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__MSG__BYP, CYREG_PRT0_BYP -.set SCSI_Out__MSG__CTL, CYREG_PRT0_CTL -.set SCSI_Out__MSG__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__MSG__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__MSG__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__MSG__DR, CYREG_PRT0_DR -.set SCSI_Out__MSG__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__MSG__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__MSG__MASK, 0x10 -.set SCSI_Out__MSG__PC, CYREG_PRT0_PC4 -.set SCSI_Out__MSG__PORT, 0 -.set SCSI_Out__MSG__PRT, CYREG_PRT0_PRT -.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__MSG__PS, CYREG_PRT0_PS -.set SCSI_Out__MSG__SHIFT, 4 -.set SCSI_Out__MSG__SLW, CYREG_PRT0_SLW -.set SCSI_Out__REQ__AG, CYREG_PRT0_AG -.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE -.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP -.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL -.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__REQ__DR, CYREG_PRT0_DR -.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__REQ__MASK, 0x02 -.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1 -.set SCSI_Out__REQ__PORT, 0 -.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT -.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__REQ__PS, CYREG_PRT0_PS -.set SCSI_Out__REQ__SHIFT, 1 -.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW -.set SCSI_Out__RST__AG, CYREG_PRT0_AG -.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE -.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP -.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL -.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__RST__DR, CYREG_PRT0_DR -.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__RST__MASK, 0x20 -.set SCSI_Out__RST__PC, CYREG_PRT0_PC5 -.set SCSI_Out__RST__PORT, 0 -.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT -.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__RST__PS, CYREG_PRT0_PS -.set SCSI_Out__RST__SHIFT, 5 -.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW -.set SCSI_Out__SEL__AG, CYREG_PRT0_AG -.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX -.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE -.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP -.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL -.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 -.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 -.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 -.set SCSI_Out__SEL__DR, CYREG_PRT0_DR -.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_Out__SEL__MASK, 0x08 -.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3 -.set SCSI_Out__SEL__PORT, 0 -.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT -.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_Out__SEL__PS, CYREG_PRT0_PS -.set SCSI_Out__SEL__SHIFT, 3 -.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW - -/* USBFS_Dm */ -.set USBFS_Dm__0__MASK, 0x80 -.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 -.set USBFS_Dm__0__PORT, 15 -.set USBFS_Dm__0__SHIFT, 7 -.set USBFS_Dm__AG, CYREG_PRT15_AG -.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dm__BIE, CYREG_PRT15_BIE -.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dm__BYP, CYREG_PRT15_BYP -.set USBFS_Dm__CTL, CYREG_PRT15_CTL -.set USBFS_Dm__DM0, CYREG_PRT15_DM0 -.set USBFS_Dm__DM1, CYREG_PRT15_DM1 -.set USBFS_Dm__DM2, CYREG_PRT15_DM2 -.set USBFS_Dm__DR, CYREG_PRT15_DR -.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dm__MASK, 0x80 -.set USBFS_Dm__PORT, 15 -.set USBFS_Dm__PRT, CYREG_PRT15_PRT -.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dm__PS, CYREG_PRT15_PS -.set USBFS_Dm__SHIFT, 7 -.set USBFS_Dm__SLW, CYREG_PRT15_SLW - -/* USBFS_Dp */ -.set USBFS_Dp__0__MASK, 0x40 -.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 -.set USBFS_Dp__0__PORT, 15 -.set USBFS_Dp__0__SHIFT, 6 -.set USBFS_Dp__AG, CYREG_PRT15_AG -.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dp__BIE, CYREG_PRT15_BIE -.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dp__BYP, CYREG_PRT15_BYP -.set USBFS_Dp__CTL, CYREG_PRT15_CTL -.set USBFS_Dp__DM0, CYREG_PRT15_DM0 -.set USBFS_Dp__DM1, CYREG_PRT15_DM1 -.set USBFS_Dp__DM2, CYREG_PRT15_DM2 -.set USBFS_Dp__DR, CYREG_PRT15_DR -.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT -.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dp__MASK, 0x40 -.set USBFS_Dp__PORT, 15 -.set USBFS_Dp__PRT, CYREG_PRT15_PRT -.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dp__PS, CYREG_PRT15_PS -.set USBFS_Dp__SHIFT, 6 -.set USBFS_Dp__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 - -/* Miscellaneous */ -/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ -.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0 -.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 -.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 -.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 -.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 -.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 -.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 -.set CYDEV_CHIP_MEMBER_5B, 4 -.set CYDEV_CHIP_FAMILY_PSOC5, 3 -.set CYDEV_CHIP_DIE_PSOC5LP, 4 -.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP -.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1 -.set BCLK__BUS_CLK__HZ, 64000000 -.set BCLK__BUS_CLK__KHZ, 64000 -.set BCLK__BUS_CLK__MHZ, 64 -.set CYDEV_BOOTLOADER_APPLICATIONS, 1 -.set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0 -.set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1 -.set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS -.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT -.set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PANTHER, 3 -.set CYDEV_CHIP_DIE_PSOC4A, 2 -.set CYDEV_CHIP_DIE_UNKNOWN, 0 -.set CYDEV_CHIP_FAMILY_PSOC3, 1 -.set CYDEV_CHIP_FAMILY_PSOC4, 2 -.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 -.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 -.set CYDEV_CHIP_JTAG_ID, 0x2E133069 -.set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 2 -.set CYDEV_CHIP_MEMBER_5A, 3 -.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 -.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B -.set CYDEV_CHIP_REVISION_3A_ES1, 0 -.set CYDEV_CHIP_REVISION_3A_ES2, 1 -.set CYDEV_CHIP_REVISION_3A_ES3, 3 -.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 -.set CYDEV_CHIP_REVISION_4A_ES0, 17 -.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 -.set CYDEV_CHIP_REVISION_5A_ES0, 0 -.set CYDEV_CHIP_REVISION_5A_ES1, 1 -.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 -.set CYDEV_CHIP_REVISION_5B_ES0, 0 -.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION -.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION -.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 -.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 -.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 -.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 -.set CYDEV_CHIP_REV_PANTHER_ES0, 0 -.set CYDEV_CHIP_REV_PANTHER_ES1, 1 -.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 -.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 -.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 -.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 -.set CYDEV_CONFIGURATION_COMPRESSED, 1 -.set CYDEV_CONFIGURATION_DMA, 0 -.set CYDEV_CONFIGURATION_ECC, 0 -.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED -.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED -.set CYDEV_CONFIGURATION_MODE_DMA, 2 -.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 -.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn -.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 -.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 -.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV -.set CYDEV_DEBUGGING_DPS_Disable, 3 -.set CYDEV_DEBUGGING_DPS_JTAG_4, 1 -.set CYDEV_DEBUGGING_DPS_JTAG_5, 0 -.set CYDEV_DEBUGGING_DPS_SWD, 2 -.set CYDEV_DEBUGGING_ENABLE, 1 -.set CYDEV_DEBUGGING_XRES, 0 -.set CYDEV_DEBUG_ENABLE_MASK, 0x20 -.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG -.set CYDEV_DMA_CHANNELS_AVAILABLE, 24 -.set CYDEV_ECC_ENABLE, 0 -.set CYDEV_HEAP_SIZE, 0x0800 -.set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x00000000 -.set CYDEV_PROJ_TYPE, 1 -.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 -.set CYDEV_PROJ_TYPE_LOADABLE, 2 -.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 -.set CYDEV_PROJ_TYPE_STANDARD, 0 -.set CYDEV_PROTECTION_ENABLE, 0 -.set CYDEV_STACK_SIZE, 0x2000 -.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 -.set CYDEV_USE_BUNDLED_CMSIS, 1 -.set CYDEV_VARIABLE_VDDA, 0 -.set CYDEV_VDDA_MV, 5000 -.set CYDEV_VDDD_MV, 5000 -.set CYDEV_VDDIO0_MV, 5000 -.set CYDEV_VDDIO1_MV, 5000 -.set CYDEV_VDDIO2_MV, 5000 -.set CYDEV_VDDIO3_MV, 5000 -.set CYDEV_VIO0, 5 -.set CYDEV_VIO0_MV, 5000 -.set CYDEV_VIO1, 5 -.set CYDEV_VIO1_MV, 5000 -.set CYDEV_VIO2, 5 -.set CYDEV_VIO2_MV, 5000 -.set CYDEV_VIO3, 5 -.set CYDEV_VIO3_MV, 5000 -.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO -.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS -.set DMA_CHANNELS_USED__MASK0, 0x00000000 -.set CYDEV_BOOTLOADER_ENABLE, 1 -.endif diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc deleted file mode 100755 index fb84c62..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitteriar.inc +++ /dev/null @@ -1,1403 +0,0 @@ -#ifndef INCLUDED_CYFITTERIAR_INC -#define INCLUDED_CYFITTERIAR_INC - INCLUDE cydeviceiar.inc - INCLUDE cydeviceiar_trm.inc - -/* USBFS_bus_reset */ -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_arb_int */ -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 7 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_sof_int */ -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_Out_DBx */ -SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__0__MASK EQU 0x08 -SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3 -SCSI_Out_DBx__0__PORT EQU 6 -SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__0__SHIFT EQU 3 -SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__1__MASK EQU 0x04 -SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2 -SCSI_Out_DBx__1__PORT EQU 6 -SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__1__SHIFT EQU 2 -SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__2__MASK EQU 0x02 -SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1 -SCSI_Out_DBx__2__PORT EQU 6 -SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__2__SHIFT EQU 1 -SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__3__MASK EQU 0x01 -SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0 -SCSI_Out_DBx__3__PORT EQU 6 -SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__3__SHIFT EQU 0 -SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__4__MASK EQU 0x80 -SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7 -SCSI_Out_DBx__4__PORT EQU 4 -SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__4__SHIFT EQU 7 -SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__5__MASK EQU 0x40 -SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6 -SCSI_Out_DBx__5__PORT EQU 4 -SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__5__SHIFT EQU 6 -SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__6__MASK EQU 0x20 -SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5 -SCSI_Out_DBx__6__PORT EQU 4 -SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__6__SHIFT EQU 5 -SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__7__MASK EQU 0x10 -SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4 -SCSI_Out_DBx__7__PORT EQU 4 -SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__7__SHIFT EQU 4 -SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB0__MASK EQU 0x08 -SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3 -SCSI_Out_DBx__DB0__PORT EQU 6 -SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB0__SHIFT EQU 3 -SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB1__MASK EQU 0x04 -SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2 -SCSI_Out_DBx__DB1__PORT EQU 6 -SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB1__SHIFT EQU 2 -SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB2__MASK EQU 0x02 -SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1 -SCSI_Out_DBx__DB2__PORT EQU 6 -SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB2__SHIFT EQU 1 -SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB3__MASK EQU 0x01 -SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0 -SCSI_Out_DBx__DB3__PORT EQU 6 -SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB3__SHIFT EQU 0 -SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB4__MASK EQU 0x80 -SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7 -SCSI_Out_DBx__DB4__PORT EQU 4 -SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB4__SHIFT EQU 7 -SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB5__MASK EQU 0x40 -SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6 -SCSI_Out_DBx__DB5__PORT EQU 4 -SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB5__SHIFT EQU 6 -SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB6__MASK EQU 0x20 -SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5 -SCSI_Out_DBx__DB6__PORT EQU 4 -SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB6__SHIFT EQU 5 -SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB7__MASK EQU 0x10 -SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4 -SCSI_Out_DBx__DB7__PORT EQU 4 -SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB7__SHIFT EQU 4 -SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW - -/* USBFS_dp_int */ -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_0 */ -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_1 */ -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x01 -USBFS_ep_1__INTC_NUMBER EQU 0 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* USBFS_ep_2 */ -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x02 -USBFS_ep_2__INTC_NUMBER EQU 1 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SD_PULLUP */ -SD_PULLUP__0__MASK EQU 0x02 -SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 -SD_PULLUP__0__PORT EQU 3 -SD_PULLUP__0__SHIFT EQU 1 -SD_PULLUP__1__MASK EQU 0x04 -SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 -SD_PULLUP__1__PORT EQU 3 -SD_PULLUP__1__SHIFT EQU 2 -SD_PULLUP__2__MASK EQU 0x08 -SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 -SD_PULLUP__2__PORT EQU 3 -SD_PULLUP__2__SHIFT EQU 3 -SD_PULLUP__3__MASK EQU 0x10 -SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 -SD_PULLUP__3__PORT EQU 3 -SD_PULLUP__3__SHIFT EQU 4 -SD_PULLUP__4__MASK EQU 0x20 -SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 -SD_PULLUP__4__PORT EQU 3 -SD_PULLUP__4__SHIFT EQU 5 -SD_PULLUP__AG EQU CYREG_PRT3_AG -SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX -SD_PULLUP__BIE EQU CYREG_PRT3_BIE -SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_PULLUP__BYP EQU CYREG_PRT3_BYP -SD_PULLUP__CTL EQU CYREG_PRT3_CTL -SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 -SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 -SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 -SD_PULLUP__DR EQU CYREG_PRT3_DR -SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_PULLUP__MASK EQU 0x3E -SD_PULLUP__PORT EQU 3 -SD_PULLUP__PRT EQU CYREG_PRT3_PRT -SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_PULLUP__PS EQU CYREG_PRT3_PS -SD_PULLUP__SHIFT EQU 1 -SD_PULLUP__SLW EQU CYREG_PRT3_SLW - -/* USBFS_USB */ -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN - -/* SCSI_Out */ -SCSI_Out__0__AG EQU CYREG_PRT4_AG -SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__0__BIE EQU CYREG_PRT4_BIE -SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__0__BYP EQU CYREG_PRT4_BYP -SCSI_Out__0__CTL EQU CYREG_PRT4_CTL -SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__0__DR EQU CYREG_PRT4_DR -SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__0__MASK EQU 0x08 -SCSI_Out__0__PC EQU CYREG_PRT4_PC3 -SCSI_Out__0__PORT EQU 4 -SCSI_Out__0__PRT EQU CYREG_PRT4_PRT -SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__0__PS EQU CYREG_PRT4_PS -SCSI_Out__0__SHIFT EQU 3 -SCSI_Out__0__SLW EQU CYREG_PRT4_SLW -SCSI_Out__1__AG EQU CYREG_PRT4_AG -SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__1__BIE EQU CYREG_PRT4_BIE -SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__1__BYP EQU CYREG_PRT4_BYP -SCSI_Out__1__CTL EQU CYREG_PRT4_CTL -SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__1__DR EQU CYREG_PRT4_DR -SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__1__MASK EQU 0x04 -SCSI_Out__1__PC EQU CYREG_PRT4_PC2 -SCSI_Out__1__PORT EQU 4 -SCSI_Out__1__PRT EQU CYREG_PRT4_PRT -SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__1__PS EQU CYREG_PRT4_PS -SCSI_Out__1__SHIFT EQU 2 -SCSI_Out__1__SLW EQU CYREG_PRT4_SLW -SCSI_Out__2__AG EQU CYREG_PRT0_AG -SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__2__BIE EQU CYREG_PRT0_BIE -SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__2__BYP EQU CYREG_PRT0_BYP -SCSI_Out__2__CTL EQU CYREG_PRT0_CTL -SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__2__DR EQU CYREG_PRT0_DR -SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__2__MASK EQU 0x80 -SCSI_Out__2__PC EQU CYREG_PRT0_PC7 -SCSI_Out__2__PORT EQU 0 -SCSI_Out__2__PRT EQU CYREG_PRT0_PRT -SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__2__PS EQU CYREG_PRT0_PS -SCSI_Out__2__SHIFT EQU 7 -SCSI_Out__2__SLW EQU CYREG_PRT0_SLW -SCSI_Out__3__AG EQU CYREG_PRT0_AG -SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__3__BIE EQU CYREG_PRT0_BIE -SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__3__BYP EQU CYREG_PRT0_BYP -SCSI_Out__3__CTL EQU CYREG_PRT0_CTL -SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__3__DR EQU CYREG_PRT0_DR -SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__3__MASK EQU 0x40 -SCSI_Out__3__PC EQU CYREG_PRT0_PC6 -SCSI_Out__3__PORT EQU 0 -SCSI_Out__3__PRT EQU CYREG_PRT0_PRT -SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__3__PS EQU CYREG_PRT0_PS -SCSI_Out__3__SHIFT EQU 6 -SCSI_Out__3__SLW EQU CYREG_PRT0_SLW -SCSI_Out__4__AG EQU CYREG_PRT0_AG -SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__4__BIE EQU CYREG_PRT0_BIE -SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__4__BYP EQU CYREG_PRT0_BYP -SCSI_Out__4__CTL EQU CYREG_PRT0_CTL -SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__4__DR EQU CYREG_PRT0_DR -SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__4__MASK EQU 0x20 -SCSI_Out__4__PC EQU CYREG_PRT0_PC5 -SCSI_Out__4__PORT EQU 0 -SCSI_Out__4__PRT EQU CYREG_PRT0_PRT -SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__4__PS EQU CYREG_PRT0_PS -SCSI_Out__4__SHIFT EQU 5 -SCSI_Out__4__SLW EQU CYREG_PRT0_SLW -SCSI_Out__5__AG EQU CYREG_PRT0_AG -SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__5__BIE EQU CYREG_PRT0_BIE -SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__5__BYP EQU CYREG_PRT0_BYP -SCSI_Out__5__CTL EQU CYREG_PRT0_CTL -SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__5__DR EQU CYREG_PRT0_DR -SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__5__MASK EQU 0x10 -SCSI_Out__5__PC EQU CYREG_PRT0_PC4 -SCSI_Out__5__PORT EQU 0 -SCSI_Out__5__PRT EQU CYREG_PRT0_PRT -SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__5__PS EQU CYREG_PRT0_PS -SCSI_Out__5__SHIFT EQU 4 -SCSI_Out__5__SLW EQU CYREG_PRT0_SLW -SCSI_Out__6__AG EQU CYREG_PRT0_AG -SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__6__BIE EQU CYREG_PRT0_BIE -SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__6__BYP EQU CYREG_PRT0_BYP -SCSI_Out__6__CTL EQU CYREG_PRT0_CTL -SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__6__DR EQU CYREG_PRT0_DR -SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__6__MASK EQU 0x08 -SCSI_Out__6__PC EQU CYREG_PRT0_PC3 -SCSI_Out__6__PORT EQU 0 -SCSI_Out__6__PRT EQU CYREG_PRT0_PRT -SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__6__PS EQU CYREG_PRT0_PS -SCSI_Out__6__SHIFT EQU 3 -SCSI_Out__6__SLW EQU CYREG_PRT0_SLW -SCSI_Out__7__AG EQU CYREG_PRT0_AG -SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__7__BIE EQU CYREG_PRT0_BIE -SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__7__BYP EQU CYREG_PRT0_BYP -SCSI_Out__7__CTL EQU CYREG_PRT0_CTL -SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__7__DR EQU CYREG_PRT0_DR -SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__7__MASK EQU 0x04 -SCSI_Out__7__PC EQU CYREG_PRT0_PC2 -SCSI_Out__7__PORT EQU 0 -SCSI_Out__7__PRT EQU CYREG_PRT0_PRT -SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__7__PS EQU CYREG_PRT0_PS -SCSI_Out__7__SHIFT EQU 2 -SCSI_Out__7__SLW EQU CYREG_PRT0_SLW -SCSI_Out__8__AG EQU CYREG_PRT0_AG -SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__8__BIE EQU CYREG_PRT0_BIE -SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__8__BYP EQU CYREG_PRT0_BYP -SCSI_Out__8__CTL EQU CYREG_PRT0_CTL -SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__8__DR EQU CYREG_PRT0_DR -SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__8__MASK EQU 0x02 -SCSI_Out__8__PC EQU CYREG_PRT0_PC1 -SCSI_Out__8__PORT EQU 0 -SCSI_Out__8__PRT EQU CYREG_PRT0_PRT -SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__8__PS EQU CYREG_PRT0_PS -SCSI_Out__8__SHIFT EQU 1 -SCSI_Out__8__SLW EQU CYREG_PRT0_SLW -SCSI_Out__9__AG EQU CYREG_PRT0_AG -SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__9__BIE EQU CYREG_PRT0_BIE -SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__9__BYP EQU CYREG_PRT0_BYP -SCSI_Out__9__CTL EQU CYREG_PRT0_CTL -SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__9__DR EQU CYREG_PRT0_DR -SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__9__MASK EQU 0x01 -SCSI_Out__9__PC EQU CYREG_PRT0_PC0 -SCSI_Out__9__PORT EQU 0 -SCSI_Out__9__PRT EQU CYREG_PRT0_PRT -SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__9__PS EQU CYREG_PRT0_PS -SCSI_Out__9__SHIFT EQU 0 -SCSI_Out__9__SLW EQU CYREG_PRT0_SLW -SCSI_Out__ACK__AG EQU CYREG_PRT0_AG -SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE -SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP -SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL -SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__ACK__DR EQU CYREG_PRT0_DR -SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__ACK__MASK EQU 0x40 -SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6 -SCSI_Out__ACK__PORT EQU 0 -SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT -SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__ACK__PS EQU CYREG_PRT0_PS -SCSI_Out__ACK__SHIFT EQU 6 -SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW -SCSI_Out__ATN__AG EQU CYREG_PRT4_AG -SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE -SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP -SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL -SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__ATN__DR EQU CYREG_PRT4_DR -SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__ATN__MASK EQU 0x04 -SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2 -SCSI_Out__ATN__PORT EQU 4 -SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT -SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__ATN__PS EQU CYREG_PRT4_PS -SCSI_Out__ATN__SHIFT EQU 2 -SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW -SCSI_Out__BSY__AG EQU CYREG_PRT0_AG -SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE -SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP -SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL -SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__BSY__DR EQU CYREG_PRT0_DR -SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__BSY__MASK EQU 0x80 -SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7 -SCSI_Out__BSY__PORT EQU 0 -SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT -SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__BSY__PS EQU CYREG_PRT0_PS -SCSI_Out__BSY__SHIFT EQU 7 -SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW -SCSI_Out__CD__AG EQU CYREG_PRT0_AG -SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE -SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP -SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL -SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__CD__DR EQU CYREG_PRT0_DR -SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__CD__MASK EQU 0x04 -SCSI_Out__CD__PC EQU CYREG_PRT0_PC2 -SCSI_Out__CD__PORT EQU 0 -SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT -SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__CD__PS EQU CYREG_PRT0_PS -SCSI_Out__CD__SHIFT EQU 2 -SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW -SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG -SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE -SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP -SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL -SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR -SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__DBP_raw__MASK EQU 0x08 -SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3 -SCSI_Out__DBP_raw__PORT EQU 4 -SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT -SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS -SCSI_Out__DBP_raw__SHIFT EQU 3 -SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW -SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG -SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE -SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP -SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL -SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR -SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__IO_raw__MASK EQU 0x01 -SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0 -SCSI_Out__IO_raw__PORT EQU 0 -SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT -SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS -SCSI_Out__IO_raw__SHIFT EQU 0 -SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW -SCSI_Out__MSG__AG EQU CYREG_PRT0_AG -SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE -SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP -SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL -SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__MSG__DR EQU CYREG_PRT0_DR -SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__MSG__MASK EQU 0x10 -SCSI_Out__MSG__PC EQU CYREG_PRT0_PC4 -SCSI_Out__MSG__PORT EQU 0 -SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT -SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__MSG__PS EQU CYREG_PRT0_PS -SCSI_Out__MSG__SHIFT EQU 4 -SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW -SCSI_Out__REQ__AG EQU CYREG_PRT0_AG -SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE -SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP -SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL -SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__REQ__DR EQU CYREG_PRT0_DR -SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__REQ__MASK EQU 0x02 -SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1 -SCSI_Out__REQ__PORT EQU 0 -SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT -SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__REQ__PS EQU CYREG_PRT0_PS -SCSI_Out__REQ__SHIFT EQU 1 -SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW -SCSI_Out__RST__AG EQU CYREG_PRT0_AG -SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE -SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP -SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL -SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__RST__DR EQU CYREG_PRT0_DR -SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__RST__MASK EQU 0x20 -SCSI_Out__RST__PC EQU CYREG_PRT0_PC5 -SCSI_Out__RST__PORT EQU 0 -SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT -SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__RST__PS EQU CYREG_PRT0_PS -SCSI_Out__RST__SHIFT EQU 5 -SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW -SCSI_Out__SEL__AG EQU CYREG_PRT0_AG -SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE -SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP -SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL -SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__SEL__DR EQU CYREG_PRT0_DR -SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__SEL__MASK EQU 0x08 -SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3 -SCSI_Out__SEL__PORT EQU 0 -SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT -SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__SEL__PS EQU CYREG_PRT0_PS -SCSI_Out__SEL__SHIFT EQU 3 -SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -/* USBFS_Dm */ -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -/* USBFS_Dp */ -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -/* Miscellaneous */ -/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */ -CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0 -CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 -CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 -CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 -CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 -CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 -CYDEV_CHIP_MEMBER_5B EQU 4 -CYDEV_CHIP_FAMILY_PSOC5 EQU 3 -CYDEV_CHIP_DIE_PSOC5LP EQU 4 -CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP -CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1 -BCLK__BUS_CLK__HZ EQU 64000000 -BCLK__BUS_CLK__KHZ EQU 64000 -BCLK__BUS_CLK__MHZ EQU 64 -CYDEV_BOOTLOADER_APPLICATIONS EQU 1 -CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0 -CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1 -CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS -CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT -CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PANTHER EQU 3 -CYDEV_CHIP_DIE_PSOC4A EQU 2 -CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_PSOC3 EQU 1 -CYDEV_CHIP_FAMILY_PSOC4 EQU 2 -CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 -CYDEV_CHIP_JTAG_ID EQU 0x2E133069 -CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 2 -CYDEV_CHIP_MEMBER_5A EQU 3 -CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 -CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B -CYDEV_CHIP_REVISION_3A_ES1 EQU 0 -CYDEV_CHIP_REVISION_3A_ES2 EQU 1 -CYDEV_CHIP_REVISION_3A_ES3 EQU 3 -CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 -CYDEV_CHIP_REVISION_4A_ES0 EQU 17 -CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_5A_ES0 EQU 0 -CYDEV_CHIP_REVISION_5A_ES1 EQU 1 -CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 -CYDEV_CHIP_REVISION_5B_ES0 EQU 0 -CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION -CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION -CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 -CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 -CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 -CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 -CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 -CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 -CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 -CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 -CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 -CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 -CYDEV_CONFIGURATION_COMPRESSED EQU 1 -CYDEV_CONFIGURATION_DMA EQU 0 -CYDEV_CONFIGURATION_ECC EQU 0 -CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED -CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED -CYDEV_CONFIGURATION_MODE_DMA EQU 2 -CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 -CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn -CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 -CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 -CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV -CYDEV_DEBUGGING_DPS_Disable EQU 3 -CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 -CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 -CYDEV_DEBUGGING_DPS_SWD EQU 2 -CYDEV_DEBUGGING_ENABLE EQU 1 -CYDEV_DEBUGGING_XRES EQU 0 -CYDEV_DEBUG_ENABLE_MASK EQU 0x20 -CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG -CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 -CYDEV_ECC_ENABLE EQU 0 -CYDEV_HEAP_SIZE EQU 0x0800 -CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000000 -CYDEV_PROJ_TYPE EQU 1 -CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 -CYDEV_PROJ_TYPE_LOADABLE EQU 2 -CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 -CYDEV_PROJ_TYPE_STANDARD EQU 0 -CYDEV_PROTECTION_ENABLE EQU 0 -CYDEV_STACK_SIZE EQU 0x2000 -CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 -CYDEV_USE_BUNDLED_CMSIS EQU 1 -CYDEV_VARIABLE_VDDA EQU 0 -CYDEV_VDDA_MV EQU 5000 -CYDEV_VDDD_MV EQU 5000 -CYDEV_VDDIO0_MV EQU 5000 -CYDEV_VDDIO1_MV EQU 5000 -CYDEV_VDDIO2_MV EQU 5000 -CYDEV_VDDIO3_MV EQU 5000 -CYDEV_VIO0 EQU 5 -CYDEV_VIO0_MV EQU 5000 -CYDEV_VIO1 EQU 5 -CYDEV_VIO1_MV EQU 5000 -CYDEV_VIO2 EQU 5 -CYDEV_VIO2_MV EQU 5000 -CYDEV_VIO3 EQU 5 -CYDEV_VIO3_MV EQU 5000 -CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO -CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS -DMA_CHANNELS_USED__MASK0 EQU 0x00000000 -CYDEV_BOOTLOADER_ENABLE EQU 1 - -#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc deleted file mode 100755 index 2f81aaf..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyfitterrv.inc +++ /dev/null @@ -1,1403 +0,0 @@ - IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC -INCLUDED_CYFITTERRV_INC EQU 1 - GET cydevicerv.inc - GET cydevicerv_trm.inc - -; USBFS_bus_reset -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_arb_int -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 7 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_sof_int -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_Out_DBx -SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__0__MASK EQU 0x08 -SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3 -SCSI_Out_DBx__0__PORT EQU 6 -SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__0__SHIFT EQU 3 -SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__1__MASK EQU 0x04 -SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2 -SCSI_Out_DBx__1__PORT EQU 6 -SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__1__SHIFT EQU 2 -SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__2__MASK EQU 0x02 -SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1 -SCSI_Out_DBx__2__PORT EQU 6 -SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__2__SHIFT EQU 1 -SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__3__MASK EQU 0x01 -SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0 -SCSI_Out_DBx__3__PORT EQU 6 -SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__3__SHIFT EQU 0 -SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__4__MASK EQU 0x80 -SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7 -SCSI_Out_DBx__4__PORT EQU 4 -SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__4__SHIFT EQU 7 -SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__5__MASK EQU 0x40 -SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6 -SCSI_Out_DBx__5__PORT EQU 4 -SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__5__SHIFT EQU 6 -SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__6__MASK EQU 0x20 -SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5 -SCSI_Out_DBx__6__PORT EQU 4 -SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__6__SHIFT EQU 5 -SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__7__MASK EQU 0x10 -SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4 -SCSI_Out_DBx__7__PORT EQU 4 -SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__7__SHIFT EQU 4 -SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB0__MASK EQU 0x08 -SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3 -SCSI_Out_DBx__DB0__PORT EQU 6 -SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB0__SHIFT EQU 3 -SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB1__MASK EQU 0x04 -SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2 -SCSI_Out_DBx__DB1__PORT EQU 6 -SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB1__SHIFT EQU 2 -SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB2__MASK EQU 0x02 -SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1 -SCSI_Out_DBx__DB2__PORT EQU 6 -SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB2__SHIFT EQU 1 -SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG -SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX -SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE -SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP -SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL -SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0 -SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1 -SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2 -SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR -SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Out_DBx__DB3__MASK EQU 0x01 -SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0 -SCSI_Out_DBx__DB3__PORT EQU 6 -SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT -SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS -SCSI_Out_DBx__DB3__SHIFT EQU 0 -SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW -SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB4__MASK EQU 0x80 -SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7 -SCSI_Out_DBx__DB4__PORT EQU 4 -SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB4__SHIFT EQU 7 -SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB5__MASK EQU 0x40 -SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6 -SCSI_Out_DBx__DB5__PORT EQU 4 -SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB5__SHIFT EQU 6 -SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB6__MASK EQU 0x20 -SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5 -SCSI_Out_DBx__DB6__PORT EQU 4 -SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB6__SHIFT EQU 5 -SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW -SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG -SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE -SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP -SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL -SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR -SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out_DBx__DB7__MASK EQU 0x10 -SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4 -SCSI_Out_DBx__DB7__PORT EQU 4 -SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT -SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS -SCSI_Out_DBx__DB7__SHIFT EQU 4 -SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW - -; USBFS_dp_int -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_1 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x01 -USBFS_ep_1__INTC_NUMBER EQU 0 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; USBFS_ep_2 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x02 -USBFS_ep_2__INTC_NUMBER EQU 1 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SD_PULLUP -SD_PULLUP__0__MASK EQU 0x02 -SD_PULLUP__0__PC EQU CYREG_PRT3_PC1 -SD_PULLUP__0__PORT EQU 3 -SD_PULLUP__0__SHIFT EQU 1 -SD_PULLUP__1__MASK EQU 0x04 -SD_PULLUP__1__PC EQU CYREG_PRT3_PC2 -SD_PULLUP__1__PORT EQU 3 -SD_PULLUP__1__SHIFT EQU 2 -SD_PULLUP__2__MASK EQU 0x08 -SD_PULLUP__2__PC EQU CYREG_PRT3_PC3 -SD_PULLUP__2__PORT EQU 3 -SD_PULLUP__2__SHIFT EQU 3 -SD_PULLUP__3__MASK EQU 0x10 -SD_PULLUP__3__PC EQU CYREG_PRT3_PC4 -SD_PULLUP__3__PORT EQU 3 -SD_PULLUP__3__SHIFT EQU 4 -SD_PULLUP__4__MASK EQU 0x20 -SD_PULLUP__4__PC EQU CYREG_PRT3_PC5 -SD_PULLUP__4__PORT EQU 3 -SD_PULLUP__4__SHIFT EQU 5 -SD_PULLUP__AG EQU CYREG_PRT3_AG -SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX -SD_PULLUP__BIE EQU CYREG_PRT3_BIE -SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_PULLUP__BYP EQU CYREG_PRT3_BYP -SD_PULLUP__CTL EQU CYREG_PRT3_CTL -SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 -SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 -SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 -SD_PULLUP__DR EQU CYREG_PRT3_DR -SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_PULLUP__MASK EQU 0x3E -SD_PULLUP__PORT EQU 3 -SD_PULLUP__PRT EQU CYREG_PRT3_PRT -SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_PULLUP__PS EQU CYREG_PRT3_PS -SD_PULLUP__SHIFT EQU 1 -SD_PULLUP__SLW EQU CYREG_PRT3_SLW - -; USBFS_USB -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN - -; SCSI_Out -SCSI_Out__0__AG EQU CYREG_PRT4_AG -SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__0__BIE EQU CYREG_PRT4_BIE -SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__0__BYP EQU CYREG_PRT4_BYP -SCSI_Out__0__CTL EQU CYREG_PRT4_CTL -SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__0__DR EQU CYREG_PRT4_DR -SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__0__MASK EQU 0x08 -SCSI_Out__0__PC EQU CYREG_PRT4_PC3 -SCSI_Out__0__PORT EQU 4 -SCSI_Out__0__PRT EQU CYREG_PRT4_PRT -SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__0__PS EQU CYREG_PRT4_PS -SCSI_Out__0__SHIFT EQU 3 -SCSI_Out__0__SLW EQU CYREG_PRT4_SLW -SCSI_Out__1__AG EQU CYREG_PRT4_AG -SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__1__BIE EQU CYREG_PRT4_BIE -SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__1__BYP EQU CYREG_PRT4_BYP -SCSI_Out__1__CTL EQU CYREG_PRT4_CTL -SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__1__DR EQU CYREG_PRT4_DR -SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__1__MASK EQU 0x04 -SCSI_Out__1__PC EQU CYREG_PRT4_PC2 -SCSI_Out__1__PORT EQU 4 -SCSI_Out__1__PRT EQU CYREG_PRT4_PRT -SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__1__PS EQU CYREG_PRT4_PS -SCSI_Out__1__SHIFT EQU 2 -SCSI_Out__1__SLW EQU CYREG_PRT4_SLW -SCSI_Out__2__AG EQU CYREG_PRT0_AG -SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__2__BIE EQU CYREG_PRT0_BIE -SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__2__BYP EQU CYREG_PRT0_BYP -SCSI_Out__2__CTL EQU CYREG_PRT0_CTL -SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__2__DR EQU CYREG_PRT0_DR -SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__2__MASK EQU 0x80 -SCSI_Out__2__PC EQU CYREG_PRT0_PC7 -SCSI_Out__2__PORT EQU 0 -SCSI_Out__2__PRT EQU CYREG_PRT0_PRT -SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__2__PS EQU CYREG_PRT0_PS -SCSI_Out__2__SHIFT EQU 7 -SCSI_Out__2__SLW EQU CYREG_PRT0_SLW -SCSI_Out__3__AG EQU CYREG_PRT0_AG -SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__3__BIE EQU CYREG_PRT0_BIE -SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__3__BYP EQU CYREG_PRT0_BYP -SCSI_Out__3__CTL EQU CYREG_PRT0_CTL -SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__3__DR EQU CYREG_PRT0_DR -SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__3__MASK EQU 0x40 -SCSI_Out__3__PC EQU CYREG_PRT0_PC6 -SCSI_Out__3__PORT EQU 0 -SCSI_Out__3__PRT EQU CYREG_PRT0_PRT -SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__3__PS EQU CYREG_PRT0_PS -SCSI_Out__3__SHIFT EQU 6 -SCSI_Out__3__SLW EQU CYREG_PRT0_SLW -SCSI_Out__4__AG EQU CYREG_PRT0_AG -SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__4__BIE EQU CYREG_PRT0_BIE -SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__4__BYP EQU CYREG_PRT0_BYP -SCSI_Out__4__CTL EQU CYREG_PRT0_CTL -SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__4__DR EQU CYREG_PRT0_DR -SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__4__MASK EQU 0x20 -SCSI_Out__4__PC EQU CYREG_PRT0_PC5 -SCSI_Out__4__PORT EQU 0 -SCSI_Out__4__PRT EQU CYREG_PRT0_PRT -SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__4__PS EQU CYREG_PRT0_PS -SCSI_Out__4__SHIFT EQU 5 -SCSI_Out__4__SLW EQU CYREG_PRT0_SLW -SCSI_Out__5__AG EQU CYREG_PRT0_AG -SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__5__BIE EQU CYREG_PRT0_BIE -SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__5__BYP EQU CYREG_PRT0_BYP -SCSI_Out__5__CTL EQU CYREG_PRT0_CTL -SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__5__DR EQU CYREG_PRT0_DR -SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__5__MASK EQU 0x10 -SCSI_Out__5__PC EQU CYREG_PRT0_PC4 -SCSI_Out__5__PORT EQU 0 -SCSI_Out__5__PRT EQU CYREG_PRT0_PRT -SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__5__PS EQU CYREG_PRT0_PS -SCSI_Out__5__SHIFT EQU 4 -SCSI_Out__5__SLW EQU CYREG_PRT0_SLW -SCSI_Out__6__AG EQU CYREG_PRT0_AG -SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__6__BIE EQU CYREG_PRT0_BIE -SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__6__BYP EQU CYREG_PRT0_BYP -SCSI_Out__6__CTL EQU CYREG_PRT0_CTL -SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__6__DR EQU CYREG_PRT0_DR -SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__6__MASK EQU 0x08 -SCSI_Out__6__PC EQU CYREG_PRT0_PC3 -SCSI_Out__6__PORT EQU 0 -SCSI_Out__6__PRT EQU CYREG_PRT0_PRT -SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__6__PS EQU CYREG_PRT0_PS -SCSI_Out__6__SHIFT EQU 3 -SCSI_Out__6__SLW EQU CYREG_PRT0_SLW -SCSI_Out__7__AG EQU CYREG_PRT0_AG -SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__7__BIE EQU CYREG_PRT0_BIE -SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__7__BYP EQU CYREG_PRT0_BYP -SCSI_Out__7__CTL EQU CYREG_PRT0_CTL -SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__7__DR EQU CYREG_PRT0_DR -SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__7__MASK EQU 0x04 -SCSI_Out__7__PC EQU CYREG_PRT0_PC2 -SCSI_Out__7__PORT EQU 0 -SCSI_Out__7__PRT EQU CYREG_PRT0_PRT -SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__7__PS EQU CYREG_PRT0_PS -SCSI_Out__7__SHIFT EQU 2 -SCSI_Out__7__SLW EQU CYREG_PRT0_SLW -SCSI_Out__8__AG EQU CYREG_PRT0_AG -SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__8__BIE EQU CYREG_PRT0_BIE -SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__8__BYP EQU CYREG_PRT0_BYP -SCSI_Out__8__CTL EQU CYREG_PRT0_CTL -SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__8__DR EQU CYREG_PRT0_DR -SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__8__MASK EQU 0x02 -SCSI_Out__8__PC EQU CYREG_PRT0_PC1 -SCSI_Out__8__PORT EQU 0 -SCSI_Out__8__PRT EQU CYREG_PRT0_PRT -SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__8__PS EQU CYREG_PRT0_PS -SCSI_Out__8__SHIFT EQU 1 -SCSI_Out__8__SLW EQU CYREG_PRT0_SLW -SCSI_Out__9__AG EQU CYREG_PRT0_AG -SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__9__BIE EQU CYREG_PRT0_BIE -SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__9__BYP EQU CYREG_PRT0_BYP -SCSI_Out__9__CTL EQU CYREG_PRT0_CTL -SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__9__DR EQU CYREG_PRT0_DR -SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__9__MASK EQU 0x01 -SCSI_Out__9__PC EQU CYREG_PRT0_PC0 -SCSI_Out__9__PORT EQU 0 -SCSI_Out__9__PRT EQU CYREG_PRT0_PRT -SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__9__PS EQU CYREG_PRT0_PS -SCSI_Out__9__SHIFT EQU 0 -SCSI_Out__9__SLW EQU CYREG_PRT0_SLW -SCSI_Out__ACK__AG EQU CYREG_PRT0_AG -SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE -SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP -SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL -SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__ACK__DR EQU CYREG_PRT0_DR -SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__ACK__MASK EQU 0x40 -SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6 -SCSI_Out__ACK__PORT EQU 0 -SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT -SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__ACK__PS EQU CYREG_PRT0_PS -SCSI_Out__ACK__SHIFT EQU 6 -SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW -SCSI_Out__ATN__AG EQU CYREG_PRT4_AG -SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE -SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP -SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL -SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__ATN__DR EQU CYREG_PRT4_DR -SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__ATN__MASK EQU 0x04 -SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2 -SCSI_Out__ATN__PORT EQU 4 -SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT -SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__ATN__PS EQU CYREG_PRT4_PS -SCSI_Out__ATN__SHIFT EQU 2 -SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW -SCSI_Out__BSY__AG EQU CYREG_PRT0_AG -SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE -SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP -SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL -SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__BSY__DR EQU CYREG_PRT0_DR -SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__BSY__MASK EQU 0x80 -SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7 -SCSI_Out__BSY__PORT EQU 0 -SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT -SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__BSY__PS EQU CYREG_PRT0_PS -SCSI_Out__BSY__SHIFT EQU 7 -SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW -SCSI_Out__CD__AG EQU CYREG_PRT0_AG -SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE -SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP -SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL -SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__CD__DR EQU CYREG_PRT0_DR -SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__CD__MASK EQU 0x04 -SCSI_Out__CD__PC EQU CYREG_PRT0_PC2 -SCSI_Out__CD__PORT EQU 0 -SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT -SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__CD__PS EQU CYREG_PRT0_PS -SCSI_Out__CD__SHIFT EQU 2 -SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW -SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG -SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX -SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE -SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP -SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL -SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0 -SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1 -SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2 -SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR -SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Out__DBP_raw__MASK EQU 0x08 -SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3 -SCSI_Out__DBP_raw__PORT EQU 4 -SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT -SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS -SCSI_Out__DBP_raw__SHIFT EQU 3 -SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW -SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG -SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE -SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP -SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL -SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR -SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__IO_raw__MASK EQU 0x01 -SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0 -SCSI_Out__IO_raw__PORT EQU 0 -SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT -SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS -SCSI_Out__IO_raw__SHIFT EQU 0 -SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW -SCSI_Out__MSG__AG EQU CYREG_PRT0_AG -SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE -SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP -SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL -SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__MSG__DR EQU CYREG_PRT0_DR -SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__MSG__MASK EQU 0x10 -SCSI_Out__MSG__PC EQU CYREG_PRT0_PC4 -SCSI_Out__MSG__PORT EQU 0 -SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT -SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__MSG__PS EQU CYREG_PRT0_PS -SCSI_Out__MSG__SHIFT EQU 4 -SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW -SCSI_Out__REQ__AG EQU CYREG_PRT0_AG -SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE -SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP -SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL -SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__REQ__DR EQU CYREG_PRT0_DR -SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__REQ__MASK EQU 0x02 -SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1 -SCSI_Out__REQ__PORT EQU 0 -SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT -SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__REQ__PS EQU CYREG_PRT0_PS -SCSI_Out__REQ__SHIFT EQU 1 -SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW -SCSI_Out__RST__AG EQU CYREG_PRT0_AG -SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE -SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP -SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL -SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__RST__DR EQU CYREG_PRT0_DR -SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__RST__MASK EQU 0x20 -SCSI_Out__RST__PC EQU CYREG_PRT0_PC5 -SCSI_Out__RST__PORT EQU 0 -SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT -SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__RST__PS EQU CYREG_PRT0_PS -SCSI_Out__RST__SHIFT EQU 5 -SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW -SCSI_Out__SEL__AG EQU CYREG_PRT0_AG -SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX -SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE -SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP -SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL -SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 -SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 -SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 -SCSI_Out__SEL__DR EQU CYREG_PRT0_DR -SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_Out__SEL__MASK EQU 0x08 -SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3 -SCSI_Out__SEL__PORT EQU 0 -SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT -SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_Out__SEL__PS EQU CYREG_PRT0_PS -SCSI_Out__SEL__SHIFT EQU 3 -SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW - -; USBFS_Dm -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW - -; USBFS_Dp -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 - -; Miscellaneous -; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release -CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0 -CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 -CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 -CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 -CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 -CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 -CYDEV_CHIP_MEMBER_5B EQU 4 -CYDEV_CHIP_FAMILY_PSOC5 EQU 3 -CYDEV_CHIP_DIE_PSOC5LP EQU 4 -CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP -CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1 -BCLK__BUS_CLK__HZ EQU 64000000 -BCLK__BUS_CLK__KHZ EQU 64000 -BCLK__BUS_CLK__MHZ EQU 64 -CYDEV_BOOTLOADER_APPLICATIONS EQU 1 -CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0 -CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1 -CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS -CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT -CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PANTHER EQU 3 -CYDEV_CHIP_DIE_PSOC4A EQU 2 -CYDEV_CHIP_DIE_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_PSOC3 EQU 1 -CYDEV_CHIP_FAMILY_PSOC4 EQU 2 -CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 -CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 -CYDEV_CHIP_JTAG_ID EQU 0x2E133069 -CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 2 -CYDEV_CHIP_MEMBER_5A EQU 3 -CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 -CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B -CYDEV_CHIP_REVISION_3A_ES1 EQU 0 -CYDEV_CHIP_REVISION_3A_ES2 EQU 1 -CYDEV_CHIP_REVISION_3A_ES3 EQU 3 -CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 -CYDEV_CHIP_REVISION_4A_ES0 EQU 17 -CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 -CYDEV_CHIP_REVISION_5A_ES0 EQU 0 -CYDEV_CHIP_REVISION_5A_ES1 EQU 1 -CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 -CYDEV_CHIP_REVISION_5B_ES0 EQU 0 -CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION -CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION -CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 -CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 -CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 -CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 -CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 -CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 -CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 -CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 -CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 -CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 -CYDEV_CONFIGURATION_COMPRESSED EQU 1 -CYDEV_CONFIGURATION_DMA EQU 0 -CYDEV_CONFIGURATION_ECC EQU 0 -CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED -CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED -CYDEV_CONFIGURATION_MODE_DMA EQU 2 -CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 -CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn -CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 -CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 -CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV -CYDEV_DEBUGGING_DPS_Disable EQU 3 -CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 -CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 -CYDEV_DEBUGGING_DPS_SWD EQU 2 -CYDEV_DEBUGGING_ENABLE EQU 1 -CYDEV_DEBUGGING_XRES EQU 0 -CYDEV_DEBUG_ENABLE_MASK EQU 0x20 -CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG -CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 -CYDEV_ECC_ENABLE EQU 0 -CYDEV_HEAP_SIZE EQU 0x0800 -CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000000 -CYDEV_PROJ_TYPE EQU 1 -CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 -CYDEV_PROJ_TYPE_LOADABLE EQU 2 -CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 -CYDEV_PROJ_TYPE_STANDARD EQU 0 -CYDEV_PROTECTION_ENABLE EQU 0 -CYDEV_STACK_SIZE EQU 0x2000 -CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 -CYDEV_USE_BUNDLED_CMSIS EQU 1 -CYDEV_VARIABLE_VDDA EQU 0 -CYDEV_VDDA_MV EQU 5000 -CYDEV_VDDD_MV EQU 5000 -CYDEV_VDDIO0_MV EQU 5000 -CYDEV_VDDIO1_MV EQU 5000 -CYDEV_VDDIO2_MV EQU 5000 -CYDEV_VDDIO3_MV EQU 5000 -CYDEV_VIO0 EQU 5 -CYDEV_VIO0_MV EQU 5000 -CYDEV_VIO1 EQU 5 -CYDEV_VIO1_MV EQU 5000 -CYDEV_VIO2 EQU 5 -CYDEV_VIO2_MV EQU 5000 -CYDEV_VIO3 EQU 5 -CYDEV_VIO3_MV EQU 5000 -CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO -CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS -DMA_CHANNELS_USED__MASK0 EQU 0x00000000 -CYDEV_BOOTLOADER_ENABLE EQU 1 - ENDIF - END diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c deleted file mode 100755 index 00c7240..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cymetadata.c +++ /dev/null @@ -1,108 +0,0 @@ -/******************************************************************************* -* FILENAME: cymetadata.c -* -* PSoC Creator 3.0 Component Pack 7 -* -* DESCRIPTION: -* This file defines all extra memory spaces that need to be included. -* This file is automatically generated by PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -********************************************************************************/ - - -#include "cytypes.h" - - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cyloadermeta"), used)) -#elif defined(__ICCARM__) -#pragma location=".cyloadermeta" -#else -#error "Unsupported toolchain" -#endif -const uint8 cy_meta_loader[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x01u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u -}; - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cyconfigecc"), used)) -#elif defined(__ICCARM__) -#pragma location=".cyconfigecc" -#else -#error "Unsupported toolchain" -#endif -const uint8 cy_meta_configecc[] = { - 0x00u -}; - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cycustnvl"), used)) -#elif defined(__ICCARM__) -#pragma location=".cycustnvl" -#else -#error "Unsupported toolchain" -#endif -const uint8 cy_meta_custnvl[] = { - 0x80u, 0x00u, 0x40u, 0x05u -}; - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cywolatch"), used)) -#elif defined(__ICCARM__) -#pragma location=".cywolatch" -#else -#error "Unsupported toolchain" -#endif -const uint8 cy_meta_wonvl[] = { - 0xBCu, 0x90u, 0xACu, 0xAFu -}; - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cyflashprotect"), used)) -#elif defined(__ICCARM__) -#pragma location=".cyflashprotect" -#else -#error "Unsupported toolchain" -#endif -const uint8 cy_meta_flashprotect[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u -}; - -#if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cymeta"), used)) -#elif defined(__ICCARM__) -#pragma location=".cymeta" -#else -#error "Unsupported toolchain" -#endif -const uint8 cy_metadata[] = { - 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u -}; diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cypins.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cypins.h deleted file mode 100755 index 3af7484..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cypins.h +++ /dev/null @@ -1,295 +0,0 @@ -/******************************************************************************* -* File Name: cypins.h -* Version 4.0 -* -* Description: -* This file contains the function prototypes and constants used for port/pin -* in access and control. -* -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOT_CYPINS_H) -#define CY_BOOT_CYPINS_H - -#include "cyfitter.h" -#include "cytypes.h" - - -/************************************** -* API Parameter Constants -**************************************/ - -#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u) -#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT)) -#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) - - -/* SetPinDriveMode */ -#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0) -#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1) -#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2) -#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3) -#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4) -#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5) -#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6) -#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7) - - -/************************************** -* Register Constants -**************************************/ - -/* Port Pin Configuration Register */ -#define CY_PINS_PC_DATAOUT (0x01u) -#define CY_PINS_PC_PIN_FASTSLEW (0xBFu) -#define CY_PINS_PC_PIN_SLOWSLEW (0x40u) -#define CY_PINS_PC_PIN_STATE (0x10u) -#define CY_PINS_PC_BIDIR_EN (0x20u) -#define CY_PINS_PC_SLEW (0x40u) -#define CY_PINS_PC_BYPASS (0x80u) - - -/************************************** -* Pin API Macros -**************************************/ - -/******************************************************************************* -* Macro Name: CyPins_ReadPin -******************************************************************************** -* -* Summary: -* Reads the current value on the pin (pin state, PS). -* -* Parameters: -* pinPC: Port pin configuration register (uint16). -* #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: -* CYREG_PRTx_PCy -* -* where x is a port number 0 - 15 and y is a pin number 0 - 7 -* -* Return: -* Pin state -* 0: Logic low value -* Non-0: Logic high value -* -*******************************************************************************/ -#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE ) - - -/******************************************************************************* -* Macro Name: CyPins_SetPin -******************************************************************************** -* -* Summary: -* Set the output value for the pin (data register, DR) to a logic high. -* -* Note that this only has an effect for pins configured as software pins that -* are not driven by hardware. -* -* Parameters: -* pinPC: Port pin configuration register (uint16). -* #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: -* CYREG_PRTx_PCy -* -* where x is a port number 0 - 15 and y is a pin number 0 - 7 -* -* Return: -* None -* -*******************************************************************************/ -#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) - - -/******************************************************************************* -* Macro Name: CyPins_ClearPin -******************************************************************************** -* -* Summary: -* This macro sets the state of the specified pin to 0 -* -* Parameters: -* pinPC: address of a Pin Configuration register. -* #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: -* CYREG_PRTx_PCy -* -* where x is a port number 0 - 15 and y is a pin number 0 - 7 -* -* Return: -* None -* -*******************************************************************************/ -#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) - - -/******************************************************************************* -* Macro Name: CyPins_SetPinDriveMode -******************************************************************************** -* -* Summary: -* Sets the drive mode for the pin (DM). -* -* Parameters: -* pinPC: Port pin configuration register (uint16) -* #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: -* CYREG_PRTx_PCy -* -* where x is a port number 0 - 15 and y is a pin number 0 - 7 -* -* mode: Desired drive mode -* -* Define Source -* PIN_DM_ALG_HIZ Analog HiZ -* PIN_DM_DIG_HIZ Digital HiZ -* PIN_DM_RES_UP Resistive pull up -* PIN_DM_RES_DWN Resistive pull down -* PIN_DM_OD_LO Open drain - drive low -* PIN_DM_OD_HI Open drain - drive high -* PIN_DM_STRONG Strong CMOS Output -* PIN_DM_RES_UPDWN Resistive pull up/down -* -* Return: -* None -* -*******************************************************************************/ -#define CyPins_SetPinDriveMode(pinPC, mode) \ - ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ - ((mode) & CY_PINS_PC_DRIVE_MODE_MASK)) - - -/******************************************************************************* -* Macro Name: CyPins_ReadPinDriveMode -******************************************************************************** -* -* Summary: -* Reads the drive mode for the pin (DM). -* -* Parameters: -* pinPC: Port pin configuration register (uint16) -* #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: -* CYREG_PRTx_PCy -* -* where x is a port number 0 - 15 and y is a pin number 0 - 7 -* -* -* Return: -* mode: Current drive mode for the pin -* -* Define Source -* PIN_DM_ALG_HIZ Analog HiZ -* PIN_DM_DIG_HIZ Digital HiZ -* PIN_DM_RES_UP Resistive pull up -* PIN_DM_RES_DWN Resistive pull down -* PIN_DM_OD_LO Open drain - drive low -* PIN_DM_OD_HI Open drain - drive high -* PIN_DM_STRONG Strong CMOS Output -* PIN_DM_RES_UPDWN Resistive pull up/down -* -*******************************************************************************/ -#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK) - - -/******************************************************************************* -* Macro Name: CyPins_FastSlew -******************************************************************************** -* -* Summary: -* Set the slew rate for the pin to fast edge rate. -* Note that this only applies for pins in strong output drive modes, -* not to resistive drive modes. -* -* Parameters: -* pinPC: address of a Pin Configuration register. -* #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: -* CYREG_PRTx_PCy -* -* where x is a port number 0 - 15 and y is a pin number 0 - 7 -* -* -* Return: -* None -* -*******************************************************************************/ -#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) - - -/******************************************************************************* -* Macro Name: CyPins_SlowSlew -******************************************************************************** -* -* Summary: -* Set the slew rate for the pin to slow edge rate. -* Note that this only applies for pins in strong output drive modes, -* not to resistive drive modes. -* -* Parameters: -* pinPC: address of a Pin Configuration register. -* #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: -* CYREG_PRTx_PCy -* -* where x is a port number 0 - 15 and y is a pin number 0 - 7 -* -* Return: -* None -* -*******************************************************************************/ -#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.30 -*******************************************************************************/ -#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT) -#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK) -#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0) -#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1) -#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2) -#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3) -#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4) -#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5) -#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6) -#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7) - -#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ) -#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ) -#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP) -#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN) -#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO) -#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI) -#define PIN_DM_STRONG (CY_PINS_DM_STRONG) -#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN) - -#define PC_DATAOUT (CY_PINS_PC_DATAOUT) -#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW) -#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW) -#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE) -#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN) -#define PC_SLEW (CY_PINS_PC_SLEW) -#define PC_BYPASS (CY_PINS_PC_BYPASS) - -#endif /* (CY_BOOT_CYPINS_H) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cytypes.h b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cytypes.h deleted file mode 100755 index c2a20ad..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cytypes.h +++ /dev/null @@ -1,438 +0,0 @@ -/******************************************************************************* -* FILENAME: cytypes.h -* Version 4.0 -* -* Description: -* CyTypes provides register access macros and approved types for use in -* firmware. -* -* Note: -* Due to endiannesses of the hardware and some compilers, the register -* access macros for big endian compilers use some library calls to arrange -* data the correct way. -* -* Register Access macros and functions perform their operations on an -* input of type pointer to void. The arguments passed to it should be -* pointers to the type associated with the register size. -* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_BOOT_CYTYPES_H) -#define CY_BOOT_CYTYPES_H - -#if defined(__C51__) - #include -#endif /* (__C51__) */ - -/* ARM and C99 or later */ -#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) - #include -#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ - -#include "cyfitter.h" - - -#if defined( __ICCARM__ ) - /* Suppress warning for multiple volatile variables in an expression. */ - /* This is common in component code and the usage is not order dependent. */ - #pragma diag_suppress=Pa082 -#endif /* defined( __ICCARM__ ) */ - - -/*************************************** -* Conditional Compilation Parameters -***************************************/ - - -/******************************************************************************* -* FAMILY encodes the overall architectural family -*******************************************************************************/ -#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) -#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) -#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) - - -/******************************************************************************* -* MEMBER encodes both the family and the detailed architecture -*******************************************************************************/ -#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) -#ifdef CYDEV_CHIP_MEMBER_4D - #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) - #define CY_PSOC4SF (CY_PSOC4D) -#else - #define CY_PSOC4D (0u != 0u) - #define CY_PSOC4SF (CY_PSOC4D) -#endif /* CYDEV_CHIP_MEMBER_4D */ - -#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) -#ifdef CYDEV_CHIP_MEMBER_5B - #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) -#else - #define CY_PSOC5LP (0u != 0u) -#endif /* CYDEV_CHIP_MEMBER_5B */ - - -/******************************************************************************* -* UDB revisions -*******************************************************************************/ -#define CY_UDB_V0 (CY_PSOC5A) -#define CY_UDB_V1 (!CY_UDB_V0) - - -/******************************************************************************* -* Base Types. Acceptable types from MISRA-C specifying signedness and size. -*******************************************************************************/ -typedef unsigned char uint8; -typedef unsigned short uint16; -typedef unsigned long uint32; -typedef signed char int8; -typedef signed short int16; -typedef signed long int32; -typedef float float32; - -#if(!CY_PSOC3) - - typedef double float64; - typedef long long int64; - typedef unsigned long long uint64; - -#endif /* (!CY_PSOC3) */ - -/* Signed or unsigned depending on the compiler selection */ -typedef char char8; - - -/******************************************************************************* -* Memory address functions prototypes -*******************************************************************************/ -#if(CY_PSOC3) - - /*************************************************************************** - * Prototypes for absolute memory address functions (cymem.a51) with built-in - * endian conversion. These functions should be called through the - * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. - ***************************************************************************/ - extern uint8 cyread8 (const volatile void far *addr); - extern void cywrite8 (volatile void far *addr, uint8 value); - - extern uint16 cyread16 (const volatile void far *addr); - extern uint16 cyread16_nodpx(const volatile void far *addr); - - extern void cywrite16 (volatile void far *addr, uint16 value); - extern void cywrite16_nodpx(volatile void far *addr, uint16 value); - - extern uint32 cyread24 (const volatile void far *addr); - extern uint32 cyread24_nodpx(const volatile void far *addr); - - extern void cywrite24 (volatile void far *addr, uint32 value); - extern void cywrite24_nodpx(volatile void far *addr, uint32 value); - - extern uint32 cyread32 (const volatile void far *addr); - extern uint32 cyread32_nodpx(const volatile void far *addr); - - extern void cywrite32 (volatile void far *addr, uint32 value); - extern void cywrite32_nodpx(volatile void far *addr, uint32 value); - - - /*************************************************************************** - * Memory access routines from cymem.a51 for the generated device - * configuration code. These functions may be subject to change in future - * revisions of the cy_boot component and they are not available for all - * devices. Most code should use memset or memcpy instead. - ***************************************************************************/ - void cymemzero(void far *addr, uint16 size); - void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; - void cyconfigcpycode(uint16 size, const void code *src, void far *dest); - - #define CYCONFIGCPY_DECLARED (1) - -#else - - /* Prototype for function to set a 24-bit register. Located at cyutils.c */ - extern void CySetReg24(uint32 volatile * addr, uint32 value); - - #if(CY_PSOC4) - - extern uint32 CyGetReg24(uint32 const volatile * addr); - - #endif /* (CY_PSOC4) */ - -#endif /* (CY_PSOC3) */ - - -/******************************************************************************* -* Memory model definitions. To allow code to be 8051-ARM agnostic. -*******************************************************************************/ -#if(CY_PSOC3) - - #define CYBDATA bdata - #define CYBIT bit - #define CYCODE code - #define CYCOMPACT compact - #define CYDATA data - #define CYFAR far - #define CYIDATA idata - #define CYLARGE large - #define CYPDATA pdata - #define CYREENTRANT reentrant - #define CYSMALL small - #define CYXDATA xdata - #define XDATA xdata - - #define CY_NOINIT - -#else - - #define CYBDATA - #define CYBIT uint8 - #define CYCODE - #define CYCOMPACT - #define CYDATA - #define CYFAR - #define CYIDATA - #define CYLARGE - #define CYPDATA - #define CYREENTRANT - #define CYSMALL - #define CYXDATA - #define XDATA - - #if defined(__ARMCC_VERSION) - #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) - #define CY_NORETURN __attribute__ ((noreturn)) - #define CY_SECTION(name) __attribute__ ((section(name))) - #define CY_ALIGN(align) __align(align) - #elif defined (__GNUC__) - #define CY_NOINIT __attribute__ ((section(".noinit"))) - #define CY_NORETURN __attribute__ ((noreturn)) - #define CY_SECTION(name) __attribute__ ((section(name))) - #define CY_ALIGN(align) __attribute__ ((aligned(align))) - #elif defined (__ICCARM__) - #define CY_NOINIT __no_init - #define CY_NORETURN __noreturn - #endif /* (__ARMCC_VERSION) */ - -#endif /* (CY_PSOC3) */ - - -#if(CY_PSOC3) - - /* 8051 naturally returns an 8 bit value. */ - typedef unsigned char cystatus; - -#else - - /* ARM naturally returns a 32 bit value. */ - typedef unsigned long cystatus; - -#endif /* (CY_PSOC3) */ - - -/******************************************************************************* -* Hardware Register Types. -*******************************************************************************/ -typedef volatile uint8 CYXDATA reg8; -typedef volatile uint16 CYXDATA reg16; -typedef volatile uint32 CYXDATA reg32; - - -/******************************************************************************* -* Interrupt Types and Macros -*******************************************************************************/ -#if(CY_PSOC3) - - #define CY_ISR(FuncName) void FuncName (void) interrupt 0 - #define CY_ISR_PROTO(FuncName) void FuncName (void) - typedef void (CYCODE * cyisraddress)(void); - -#else - - #define CY_ISR(FuncName) void FuncName (void) - #define CY_ISR_PROTO(FuncName) void FuncName (void) - typedef void (* cyisraddress)(void); - - #if defined (__ICCARM__) - typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; - #endif /* defined (__ICCARM__) */ - -#endif /* (CY_PSOC3) */ - - -/******************************************************************************* -* Register Access -*******************************************************************************/ -#if(CY_PSOC3) - - - /******************************************************************************* - * KEIL for the 8051 is a big endian compiler This causes problems as the on chip - * registers are little endian. Byte swapping for two and four byte registers is - * implemented in the functions below. This will require conditional compilation - * of function prototypes in code. - *******************************************************************************/ - - /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */ - - #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) - #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) - - #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) - #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) - - #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) - #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) - - #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) - #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) - - /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ - #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) - #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) - - #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) - #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) - - #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) - #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) - - #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) - #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) - -#else - - /* 8, 16, 24 and 32-bit register access macros */ - #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) - #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) - - #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) - #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) - - - #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) - #if(CY_PSOC4) - #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) - #else - #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) - #endif /* (CY_PSOC4) */ - - - #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) - #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) - - - /* To allow code to be 8051-ARM agnostic. */ - #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) - #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) - - #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) - #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) - - #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) - #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) - - #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) - #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) - -#endif /* (CY_PSOC3) */ - - - -/******************************************************************************* -* Data manipulation defines -*******************************************************************************/ - -/* Get 8 bits of a 16 bit value. */ -#define LO8(x) ((uint8) ((x) & 0xFFu)) -#define HI8(x) ((uint8) ((uint16)(x) >> 8)) - -/* Get 16 bits of a 32 bit value. */ -#define LO16(x) ((uint16) ((x) & 0xFFFFu)) -#define HI16(x) ((uint16) ((uint32)(x) >> 16)) - -/* Swap the byte ordering of a 32 bit value */ -#define CYSWAP_ENDIAN32(x) \ - ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) - -/* Swap the byte ordering of a 16 bit value */ -#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8))) - - -/******************************************************************************* -* Defines the standard return values used PSoC content. A function is -* not limited to these return values but can use them when returning standard -* error values. Return values can be overloaded if documented in the function -* header. On the 8051 a function can use a larger return type but still use the -* defined return codes. -* -* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - -* standard defined values; 0x80 - ... - user or content defined values. -*******************************************************************************/ -#define CYRET_SUCCESS (0x00u) /* Successful */ -#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ -#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ -#define CYRET_MEMORY (0x03u) /* Memory related failure */ -#define CYRET_LOCKED (0x04u) /* Resource lock failure */ -#define CYRET_EMPTY (0x05u) /* No more objects available */ -#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ -#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ -#define CYRET_FINISHED (0x08u) /* Operation completed */ -#define CYRET_CANCELED (0x09u) /* Operation canceled */ -#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ -#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ -#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ - - -/******************************************************************************* -* Intrinsic Defines: Processor NOP instruction -*******************************************************************************/ -#if(CY_PSOC3) - - #define CY_NOP _nop_() - -#else - - #if defined(__ARMCC_VERSION) - - /* RealView */ - #define CY_NOP __nop() - - #else - - /* GCC */ - #define CY_NOP __asm("NOP\n") - - #endif /* defined(__ARMCC_VERSION) */ - -#endif /* (CY_PSOC3) */ - - -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from cy_boot 3.10 -*******************************************************************************/ - -/* Device is PSoC 3 and the revision is ES2 or earlier */ -#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ - (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) - -/* Device is PSoC 3 and the revision is ES3 or later */ -#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ - (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) - -/* Device is PSoC 5 and the revision is ES1 or earlier */ -#define CY_PSOC5_ES1 (CY_PSOC5A && \ - (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) - -/* Device is PSoC 5 and the revision is ES2 or later */ -#define CY_PSOC5_ES2 (CY_PSOC5A && \ - (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) - -#endif /* CY_BOOT_CYTYPES_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyutils.c b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyutils.c deleted file mode 100755 index 0a11231..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/cyutils.c +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************************* -* FILENAME: cyutils.c -* Version 4.0 -* -* Description: -* CyUtils provides function to handle 24-bit value writes. -* -******************************************************************************** -* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "cytypes.h" - -#if (!CY_PSOC3) - - /*************************************************************************** - * Function Name: CySetReg24 - **************************************************************************** - * - * Summary: - * Writes the 24-bit value to the specified register. - * - * Parameters: - * addr : adress where data must be written - * value: data that must be written - * - * Return: - * None - * - * Reentrant: - * No - * - ***************************************************************************/ - void CySetReg24(uint32 volatile * addr, uint32 value) - { - uint8 volatile *tmpAddr; - - tmpAddr = (uint8 volatile *) addr; - - tmpAddr[0u] = (uint8) value; - tmpAddr[1u] = (uint8) (value >> 8u); - tmpAddr[2u] = (uint8) (value >> 16u); - } - - - #if(CY_PSOC4) - - /*************************************************************************** - * Function Name: CyGetReg24 - **************************************************************************** - * - * Summary: - * Reads the 24-bit value from the specified register. - * - * Parameters: - * addr : adress where data must be read - * - * Return: - * None - * - * Reentrant: - * No - * - ***************************************************************************/ - uint32 CyGetReg24(uint32 const volatile * addr) - { - uint8 const volatile *tmpAddr; - uint32 value; - - tmpAddr = (uint8 const volatile *) addr; - - value = (uint32) tmpAddr[0u]; - value |= ((uint32) tmpAddr[1u] << 8u ); - value |= ((uint32) tmpAddr[2u] << 16u); - - return(value); - } - - #endif /*(CY_PSOC4)*/ - -#endif /* (!CY_PSOC3) */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/device.lib b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/device.lib deleted file mode 100755 index a40c9b3..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/device.lib +++ /dev/null @@ -1,3094 +0,0 @@ -/* - Copyright Cypress Semiconductor Corporation, 2010-2011 -*/ -/*library (leopard) { - - timescale : 1ns; -*/ - - cell (clockblockcell) { - bundle (dclk) { - members (dclk_0, dclk_1, dclk_2, dclk_3, dclk_4, dclk_5, dclk_6, dclk_7); - direction : output; - } - bundle (dclk_glb) { - members (dclk_glb_0, dclk_glb_1, dclk_glb_2, dclk_glb_3, dclk_glb_4, dclk_glb_5, dclk_glb_6, dclk_glb_7); - direction : output; - } - bundle (aclk) { - members (aclk_0, aclk_1, aclk_2, aclk_3); - direction : output; - } - bundle (aclk_glb) { - members (aclk_glb_0, aclk_glb_1, aclk_glb_2, aclk_glb_3); - direction : output; - } - bundle (clk_a_dig) { - members (clk_a_dig_0, clk_a_dig_1, clk_a_dig_2, clk_a_dig_3); - direction : output; - } - bundle (clk_a_dig_glb) { - members (clk_a_dig_glb_0, clk_a_dig_glb_1, clk_a_dig_glb_2, clk_a_dig_glb_3); - direction : output; - } - pin (clk_bus) { direction : output; } - pin (clk_bus_glb) { direction : output; } - pin (clk_sync) { direction : output; } - pin (clk_32k_xtal) { direction : output; } - pin (clk_100k) { direction : output; } - pin (clk_32k) { direction : output; } - pin (clk_1k) { direction : output; } - pin (clk_usb) { direction : output; } - pin (imo) { direction : output; } - pin (ilo) { direction : output; } - pin (xtal) { direction : output; } - pin (pllout) { direction : output; } - pin (xmhz_xerr) { direction : output; } - pin (pll_lock_out) { direction : output; } - bundle (dsi_dig_div) { - members (dsi_dig_div_0, dsi_dig_div_1, dsi_dig_div_2, dsi_dig_div_3, dsi_dig_div_4, dsi_dig_div_5, dsi_dig_div_6, dsi_dig_div_7); - direction : input; - } - bundle (dsi_ana_div) { - members (dsi_ana_div_0, dsi_ana_div_1, dsi_ana_div_2, dsi_ana_div_3); - direction : input; - } - pin (dsi_glb_div) { direction : input; } - pin (dsi_clkin_div) { direction : input; } - } - - cell (carrycell) { - } - - cell (interrupt) { - pin (clock) { - direction : input; - clock : true; - } - pin (interrupt) { - direction : input; - } - } - - cell (logicalport) { - pin (interrupt) { - direction : output; - } - pin (precharge) { - direction : input; - } - } - - cell (iocell) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 16.2; - intrinsic_fall : 16.2; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 8.5; - intrinsic_fall : 8.5; - } - } - } - - cell (iocell_ireg) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 16.2; - intrinsic_fall : 16.2; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (iocell_oreg) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 16.5; - intrinsic_fall : 16.5; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 8.5; - intrinsic_fall : 8.5; - } - } - } - - cell (iocell_ioreg) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 12.8; - intrinsic_fall : 12.8; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 16.5; - intrinsic_fall : 16.5; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (iocell_lv) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 33.5; - intrinsic_fall : 33.5; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 11.83; - intrinsic_fall : 11.83; - } - } - } - - cell (iocell_ireg_lv) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 33.5; - intrinsic_fall : 33.5; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (iocell_oreg_lv) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 32.5; - intrinsic_fall : 32.5; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 11.83; - intrinsic_fall : 11.83; - } - } - } - - cell (iocell_ioreg_lv) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 32.5; - intrinsic_fall : 32.5; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (sio) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 17; - intrinsic_fall : 17; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 8.5; - intrinsic_fall : 8.5; - } - } - } - - cell (sio_ireg) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 17; - intrinsic_fall : 17; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (sio_oreg) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 16.5; - intrinsic_fall : 16.5; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 8.5; - intrinsic_fall : 8.5; - } - } - } - - cell (sio_ioreg) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 14.8; - intrinsic_fall : 14.8; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 16.5; - intrinsic_fall : 16.5; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (sio_lv) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 30.9; - intrinsic_fall : 30.9; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 11.83; - intrinsic_fall : 11.83; - } - } - } - - cell (sio_ireg_lv) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 30.9; - intrinsic_fall : 30.9; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (sio_oreg_lv) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 32.5; - intrinsic_fall : 32.5; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 11.83; - intrinsic_fall : 11.83; - } - } - } - - cell (sio_ioreg_lv) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 18.3; - intrinsic_fall : 18.3; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 32.5; - intrinsic_fall : 32.5; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (usbio) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 20; - intrinsic_fall : 20; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 8.5; - intrinsic_fall : 8.5; - } - } - } - - cell (usbio_ireg) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 20; - intrinsic_fall : 20; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (usbio_oreg) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 16.5; - intrinsic_fall : 16.5; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 8.5; - intrinsic_fall : 8.5; - } - } - } - - cell (usbio_ioreg) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 22; - intrinsic_fall : 22; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 16.5; - intrinsic_fall : 16.5; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (usbio_lv) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 50; - intrinsic_fall : 50; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 11.83; - intrinsic_fall : 11.83; - } - } - } - - cell (usbio_ireg_lv) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pin_input"; - intrinsic_rise : 50; - intrinsic_fall : 50; - } - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (usbio_oreg_lv) { - pin (in_clock) { - direction : input; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 32.5; - intrinsic_fall : 32.5; - } - } - pin (fb) { - direction : output; - function : "pad_in"; - timing() { - timing_type : combinational; - timing_sense : positive_unate; - related_pin : "pad_in"; - intrinsic_rise : 11.83; - intrinsic_fall : 11.83; - } - } - } - - cell (usbio_ioreg_lv) { - pin (in_clock) { - direction : input; - clock : true; - } - pin (in_clock_en) { - direction : input; - } - pin (in_reset) { - direction : input; - } - pin (out_clock) { - direction : input; - clock : true; - } - pin (out_clock_en) { - direction : input; - } - pin (out_reset) { - direction : input; - } - pin (pin_input) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "out_clock"; - intrinsic_rise : 5.83; - intrinsic_fall : 5.83; - } - } - pin (pa_out) { - direction : input; - } - pin (oe) { - direction : input; - } - pin (pad_in) { - direction : input; - } - pin (pad_out) { - direction : output; - timing() { - timing_type : three_state_enable; - timing_sense : positive_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - timing() { - timing_type : three_state_disable; - timing_sense : negative_unate; - related_pin : "oe"; - intrinsic_rise : 52; - intrinsic_fall : 52; - } - timing() { - timing_type : rising_edge; - related_pin : "out_clock"; - intrinsic_rise : 32.5; - intrinsic_fall : 32.5; - } - } - pin (fb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "in_clock"; - intrinsic_rise : 6.16; - intrinsic_fall : 6.16; - } - } - } - - cell (count7cell) { - pin (clock) { - direction : input; - clock : true; - } - pin (clock_n) { - direction : input; - clock : true; - } - pin (extclk) { - direction : input; - clock : true; - } - pin (extclk_n) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.1; - intrinsic_fall : 2.1; - } - timing() { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "clock_n"; - intrinsic_rise : 2.1; - intrinsic_fall : 2.1; - } - timing() { - timing_type : hold_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_rising; - related_pin : "extclk"; - intrinsic_rise : 0; - intrinsic_fall : 0; - } - timing() { - timing_type : hold_rising; - related_pin : "extclk"; - intrinsic_rise : 0.6; - intrinsic_fall : 0.6; - } - timing() { - timing_type : setup_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0; - intrinsic_fall : 0; - } - timing() { - timing_type : hold_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.6; - intrinsic_fall : 0.6; - } - } - pin (reset) { - direction : input; - timing() { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : recovery_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : recovery_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : recovery_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (load) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 4.22; - intrinsic_fall : 4.22; - } - timing() { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "clock_n"; - intrinsic_rise : 4.22; - intrinsic_fall : 4.22; - } - timing() { - timing_type : hold_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_rising; - related_pin : "extclk"; - intrinsic_rise : 6.22; - intrinsic_fall : 6.22; - } - timing() { - timing_type : hold_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "extclk_n"; - intrinsic_rise : 6.22; - intrinsic_fall : 6.22; - } - timing() { - timing_type : hold_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (enable) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 3.34; - intrinsic_fall : 3.34; - } - timing() { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "clock_n"; - intrinsic_rise : 3.34; - intrinsic_fall : 3.34; - } - timing() { - timing_type : hold_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_rising; - related_pin : "extclk"; - intrinsic_rise : 5.34; - intrinsic_fall : 5.34; - } - timing() { - timing_type : hold_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "extclk_n"; - intrinsic_rise : 5.34; - intrinsic_fall : 5.34; - } - timing() { - timing_type : hold_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - bundle (count) { - members (count_0, count_1, count_2, count_3, count_4, count_5, count_6); - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 2.11; - intrinsic_fall : 2.11; - } - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.92; - intrinsic_fall : 1.92; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 2.11; - intrinsic_fall : 2.11; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 1.92; - intrinsic_fall : 1.92; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 4.11; - intrinsic_fall : 4.11; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 3.92; - intrinsic_fall : 3.92; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 4.11; - intrinsic_fall : 4.11; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 3.92; - intrinsic_fall : 3.92; - } - timing() { - timing_type : clear; - timing_sense : negative_unate; - related_pin : "reset"; - intrinsic_rise : 7.57; - intrinsic_fall : 7.57; - } - timing() { - timing_type : clear; - timing_sense : negative_unate; - related_pin : "reset"; - intrinsic_rise : 6.24; - intrinsic_fall : 6.24; - } - } - pin (tc) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 2.58; - intrinsic_fall : 2.58; - } - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 2.04; - intrinsic_fall : 2.04; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 2.58; - intrinsic_fall : 2.58; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 2.04; - intrinsic_fall : 2.04; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 4.58; - intrinsic_fall : 4.58; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 4.04; - intrinsic_fall : 4.04; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 4.58; - intrinsic_fall : 4.58; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 4.04; - intrinsic_fall : 4.04; - } - timing() { - timing_type : preset; - timing_sense : positive_unate; - related_pin : "reset"; - intrinsic_rise : 8.02; - intrinsic_fall : 8.02; - } - timing() { - timing_type : preset; - timing_sense : positive_unate; - related_pin : "reset"; - intrinsic_rise : 6.19; - intrinsic_fall : 6.19; - } - } - } - - cell (count7cell_alt) { - pin (clock) { - direction : input; - clock : true; - } - pin (clock_n) { - direction : input; - clock : true; - } - pin (extclk) { - direction : input; - clock : true; - } - pin (extclk_n) { - direction : input; - clock : true; - } - pin (clk_en) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.1; - intrinsic_fall : 2.1; - } - timing() { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "clock_n"; - intrinsic_rise : 2.1; - intrinsic_fall : 2.1; - } - timing() { - timing_type : hold_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_rising; - related_pin : "extclk"; - intrinsic_rise : 0; - intrinsic_fall : 0; - } - timing() { - timing_type : hold_rising; - related_pin : "extclk"; - intrinsic_rise : 0.6; - intrinsic_fall : 0.6; - } - timing() { - timing_type : setup_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0; - intrinsic_fall : 0; - } - timing() { - timing_type : hold_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.6; - intrinsic_fall : 0.6; - } - } - pin (reset) { - direction : input; - timing() { - timing_type : recovery_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : recovery_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : recovery_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : recovery_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : removal_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (load) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 4.22; - intrinsic_fall : 4.22; - } - timing() { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "clock_n"; - intrinsic_rise : 4.22; - intrinsic_fall : 4.22; - } - timing() { - timing_type : hold_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_rising; - related_pin : "extclk"; - intrinsic_rise : 6.22; - intrinsic_fall : 6.22; - } - timing() { - timing_type : hold_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "extclk_n"; - intrinsic_rise : 6.22; - intrinsic_fall : 6.22; - } - timing() { - timing_type : hold_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - pin (enable) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 3.34; - intrinsic_fall : 3.34; - } - timing() { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "clock_n"; - intrinsic_rise : 3.34; - intrinsic_fall : 3.34; - } - timing() { - timing_type : hold_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_rising; - related_pin : "extclk"; - intrinsic_rise : 5.34; - intrinsic_fall : 5.34; - } - timing() { - timing_type : hold_rising; - related_pin : "extclk"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "extclk_n"; - intrinsic_rise : 5.34; - intrinsic_fall : 5.34; - } - timing() { - timing_type : hold_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - } - bundle (count) { - members (count_0, count_1, count_2, count_3, count_4, count_5, count_6); - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 2.11; - intrinsic_fall : 2.11; - } - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.92; - intrinsic_fall : 1.92; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 2.11; - intrinsic_fall : 2.11; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 1.92; - intrinsic_fall : 1.92; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 4.11; - intrinsic_fall : 4.11; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 3.92; - intrinsic_fall : 3.92; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 4.11; - intrinsic_fall : 4.11; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 3.92; - intrinsic_fall : 3.92; - } - timing() { - timing_type : clear; - timing_sense : negative_unate; - related_pin : "reset"; - intrinsic_rise : 7.57; - intrinsic_fall : 7.57; - } - timing() { - timing_type : clear; - timing_sense : negative_unate; - related_pin : "reset"; - intrinsic_rise : 6.24; - intrinsic_fall : 6.24; - } - } - pin (tc) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 3.58; - intrinsic_fall : 3.58; - } - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 2.04; - intrinsic_fall : 2.04; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 3.58; - intrinsic_fall : 3.58; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n"; - intrinsic_rise : 2.04; - intrinsic_fall : 2.04; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 5.58; - intrinsic_fall : 5.58; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk"; - intrinsic_rise : 4.04; - intrinsic_fall : 4.04; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 5.58; - intrinsic_fall : 5.58; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n"; - intrinsic_rise : 4.04; - intrinsic_fall : 4.04; - } - timing() { - timing_type : preset; - timing_sense : positive_unate; - related_pin : "reset"; - intrinsic_rise : 8.02; - intrinsic_fall : 8.02; - } - timing() { - timing_type : preset; - timing_sense : positive_unate; - related_pin : "reset"; - intrinsic_rise : 6.19; - intrinsic_fall : 6.19; - } - } - } - - cell (synccell) { - pin (clock) { - direction : input; - clock : true; - } - - pin (clock_n) { - direction : input; - clock : true; - } - - pin (extclk) { - direction : input; - clock : true; - } - - pin (extclk_n) { - direction : input; - clock : true; - } - - pin (clk_en) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "clock"; - intrinsic_rise : 2.1; - intrinsic_fall : 2.1; - } - timing() { - timing_type : hold_rising; - related_pin : "clock"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_falling; - related_pin : "clock_n"; - intrinsic_rise : 2.1; - intrinsic_fall : 2.1; - } - timing() { - timing_type : hold_falling; - related_pin : "clock_n"; - intrinsic_rise : 0.00; - intrinsic_fall : 0.00; - } - timing() { - timing_type : setup_rising; - related_pin : "extclk"; - intrinsic_rise : 0; - intrinsic_fall : 0; - } - timing() { - timing_type : hold_rising; - related_pin : "extclk"; - intrinsic_rise : 0.6; - intrinsic_fall : 0.6; - } - timing() { - timing_type : setup_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0; - intrinsic_fall : 0; - } - timing() { - timing_type : hold_falling; - related_pin : "extclk_n"; - intrinsic_rise : 0.6; - intrinsic_fall : 0.6; - } - } - - pin (in) { - direction : input; - } - - pin (out) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock" - intrinsic_rise : 1.48; - intrinsic_fall : 1.48; - } - timing() { - timing_type : rising_edge; - related_pin : "clock" - intrinsic_rise : 1; - intrinsic_fall : 1; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n" - intrinsic_rise : 1.48; - intrinsic_fall : 1.48; - } - timing() { - timing_type : falling_edge; - related_pin : "clock_n" - intrinsic_rise : 1; - intrinsic_fall : 1; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk" - intrinsic_rise : 3.48; - intrinsic_fall : 3.48; - } - timing() { - timing_type : rising_edge; - related_pin : "extclk" - intrinsic_rise : 3; - intrinsic_fall : 3; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n" - intrinsic_rise : 3.48; - intrinsic_fall : 3.48; - } - timing() { - timing_type : falling_edge; - related_pin : "extclk_n" - intrinsic_rise : 3; - intrinsic_fall : 3; - } - } - } - - cell (boostcell) { - pin (interrupt) { direction : output; } - } - - cell (cancell) { - pin (clock) { direction : input; clock: true; } - pin (can_rx) { direction : input; } - pin (can_tx) { direction : output; } - pin (can_tx_en) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (interrupt) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - } - - cell (comparatorcell) { - pin (out) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (clk_udb) { direction : input; } - pin (clock) { direction : input; clock: true; } - } - - cell (capsensecell) { - pin (lft) { direction : input; } - pin (rt) { direction : input; } - } - - cell (csabufcell) { - pin (swon) { direction : input; } - } - - cell (decimatorcell) { - pin (aclock) { direction : input; clock: true; } - pin (mod_dat_0) { direction : input; } - pin (mod_dat_1) { direction : input; } - pin (mod_dat_2) { direction : input; } - pin (mod_dat_3) { direction : input; } - pin (ext_start) { direction : input; } - pin (modrst) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (interrupt) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - } - - cell (dfbcell) { - pin (clock) { direction : input; clock: true; } - pin (in_1) { direction : input; } - pin (in_2) { direction : input; } - pin (out_1) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (out_2) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dmareq_1) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dmareq_2) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (interrupt) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - } - - cell (dsmodcell) { - pin (aclock) { direction : input; clock: true; } - pin (modbitin_udb) { direction : input; } - pin (reset_udb) { direction : input; } - pin (reset_dec) { direction : input; } - pin (dec_clock) { direction : output; } - pin (mod_dat_0) { direction : output; } - pin (mod_dat_1) { direction : output; } - pin (mod_dat_2) { direction : output; } - pin (mod_dat_3) { direction : output; } - pin (dout_udb_0) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dout_udb_1) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dout_udb_2) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dout_udb_3) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dout_udb_4) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dout_udb_5) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dout_udb_6) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (dout_udb_7) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "aclock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (extclk_cp_udb) { direction : input; } - pin (clk_udb) { direction : input; } - } - - cell (emifcell) { - pin (busclk) { direction : input; clock: true; } - pin (EM_clock) { direction : output; } - pin (EM_CEn) { direction : output; } - pin (EM_OEn) { direction : output; } - pin (EM_ADSCn) { direction : output; } - pin (EM_sleep) { direction : output; } - pin (EM_WRn) { direction : output; } - pin (dataport_OE) { direction : output; } - pin (dataport_OEn) { direction : output; } - pin (wr) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 6.83; - intrinsic_fall : 6.83; - } - } - pin (rd) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "busclk"; - intrinsic_rise : 7.35; - intrinsic_fall : 7.35; - } - } - pin (udb_stall) { direction : input; } - pin (udb_ready) { - direction : input; - timing() { - timing_type : setup_rising; - related_pin : "busclk"; - intrinsic_rise : 0; - intrinsic_fall : 0; - } - timing() { - timing_type : hold_rising; - related_pin : "busclk"; - intrinsic_rise : 2.9; - intrinsic_fall : 2.9; - } - } - } - - cell (i2ccell) { - pin (clock) { direction : input; clock: true; } - pin (scl_in) { direction : input; } - pin (sda_in) { direction : input; } - pin (scl_out) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (sda_out) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (interrupt) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - } - - cell (lcdctrlcell) { - pin (drive_en) { direction : input; } - pin (frame) { direction : input; } - pin (data_clk) { direction : input; } - pin (en_hi) { direction : input; } - pin (dac_dis) { direction : input; } - pin (chop_clk) { direction : input; } - pin (int_clr) { direction : input; } - pin (lp_ack_udb) { direction : input; } - pin (mode_1) { direction : input; } - pin (mode_2) { direction : input; } - pin (interrupt) { direction : output; } - } - - cell (cachecell) { - pin (interrupt) { direction : output; } - } - - cell (lvdcell) { - pin (interrupt) { direction : output; } - } - - cell (pmcell) { - pin (ctw_int) { direction : output; } - pin (ftw_int) { direction : output; } - pin (limact_int) { direction : output; } - pin (onepps_int) { direction : output; } - pin (pm_int) { direction : output; } - } - - cell (sarcell) { - pin (clock) { direction : input; clock: true; } - pin (pump_clock) { direction : input; } - pin (clk_udb) { direction : input; } - pin (sof_udb) { direction : input; } - pin (vp_ctl_udb_0) { direction : input; } - pin (vp_ctl_udb_1) { direction : input; } - pin (vp_ctl_udb_2) { direction : input; } - pin (vp_ctl_udb_3) { direction : input; } - pin (vn_ctl_udb_0) { direction : input; } - pin (vn_ctl_udb_1) { direction : input; } - pin (vn_ctl_udb_2) { direction : input; } - pin (vn_ctl_udb_3) { direction : input; } - bundle (data_out_udb) { - members (data_out_udb_0, data_out_udb_1, data_out_udb_2, data_out_udb_3, - data_out_udb_4, data_out_udb_5, data_out_udb_6, data_out_udb_7, - data_out_udb_8, data_out_udb_9, data_out_udb_10, data_out_udb_11); - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (eof_udb) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (irq) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (next) { - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - } - - cell (sccell) { - pin (aclk) { direction : input; } - pin (bst_clk) { direction : input; } - pin (clk_udb) { direction : input; } - pin (modout) { direction : output; } - pin (dyn_cntl_udb) { direction : input; } - } - - cell (spccell) { - pin (data_ready) { direction : output; } - pin (eeprom_fault_int) { direction : output; } - pin (idle) { direction : output; } - } - - cell (ssccell) { - pin (rst_n) { direction : input; } - pin (scli) { direction : input; } - pin (sdai) { direction : input; } - pin (csel) { direction : input; } - pin (sclo) { direction : output; } - pin (sdao) { direction : output; } - pin (irq) { direction : output; } - } - - cell (tfaultcell) { - pin (tfault_dsi) { direction : output; } - } - - cell (timercell) { - pin (clock) { direction : input; clock: true; } - pin (kill) { direction : input; } - pin (enable) { direction : input; } - pin (capture) { direction : input; } - pin (timer_reset) { direction : input; } - pin (tc){ - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (cmp){ - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - pin (irq){ - direction : output; - timing() { - timing_type : rising_edge; - related_pin : "clock"; - intrinsic_rise : 1.0; - intrinsic_fall : 1.0; - } - } - } - - cell (usbcell) { - pin (sof_int) { direction : output; } - pin (arb_int) { direction : output; } - pin (usb_int) { direction : output; } - pin (ord_int) { direction : output; } - pin (ept_int_0) { direction : output; } - pin (ept_int_1) { direction : output; } - pin (ept_int_2) { direction : output; } - pin (ept_int_3) { direction : output; } - pin (ept_int_4) { direction : output; } - pin (ept_int_5) { direction : output; } - pin (ept_int_6) { direction : output; } - pin (ept_int_7) { direction : output; } - pin (ept_int_8) { direction : output; } - pin (dma_req_0) { direction : output; } - pin (dma_req_1) { direction : output; } - pin (dma_req_2) { direction : output; } - pin (dma_req_3) { direction : output; } - pin (dma_req_4) { direction : output; } - pin (dma_req_5) { direction : output; } - pin (dma_req_6) { direction : output; } - pin (dma_req_7) { direction : output; } - pin (dma_termin) { direction : output; } - } - - cell (vidaccell) { - pin (data_0) { direction : input; } - pin (data_1) { direction : input; } - pin (data_2) { direction : input; } - pin (data_3) { direction : input; } - pin (data_4) { direction : input; } - pin (data_5) { direction : input; } - pin (data_6) { direction : input; } - pin (data_7) { direction : input; } - pin (strobe) { direction : input; } - pin (strobe_udb) { direction : input; } - pin (reset) { direction : input; } - pin (idir) { direction : input; } - pin (ioff) { direction : input; } - } - -/*}*/ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/eeprom.hex b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/eeprom.hex deleted file mode 100755 index e69de29..0000000 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt b/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt deleted file mode 100755 index df6ae4f..0000000 --- a/software/SCSI2SD/USB_Bootloader.cydsn/codegentemp/elab_dependencies.txt +++ /dev/null @@ -1,397 +0,0 @@ -W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\TopDesign\TopDesign.cysch -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cysym -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.pdf -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cycdx -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cystate -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60 -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS.h -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_audio.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_audio.h -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_boot.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_cdc.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_cdc.h -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_cls.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_descr.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_drv.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_episr.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_hid.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_hid.h -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_pm.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_std.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_vnd.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_cdc.inf -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_midi.c -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_midi.h -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_pvt.h -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\Properties\Resources.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyadvancedpage.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyadvancedpage.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyapicustomizer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyaudio.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyaudiodescriptorpage.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyaudiodescriptorpage.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cycdc.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cycdcdescriptorpage.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cycdcdescriptorpage.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cycustomizer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsconfig.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsconfig.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsdevice.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsdevice.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsendpoint.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsendpoint.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailshid.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailshid.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsinterface.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsinterface.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailslangid.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailslangid.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsstring.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsstring.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydevice.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydevicedescriptorpage.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydevicedescriptorpage.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyhiddescriptorpage.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyhiddescriptorpage.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportbase.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportbase.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportbits.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportbits.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportcustom.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportcustom.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportlist.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportlist.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportnumber.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportnumber.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportunit.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyreportunit.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cystringdescriptorpage.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cystringdescriptorpage.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cytemplates.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyusbdescriptor.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyusbparameters.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cyaudio2_0.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsepmngt.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cydetailsepmngt.Designer.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\Custom\cymidi.cs -C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC 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