From 9f5624ddd7bd57526ce102d602e3328912e88425 Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Tue, 21 Jul 2015 10:55:08 +1000 Subject: [PATCH] Performance fixes, scsi2sd-util crash fixes, scsi2 config option. --- CHANGELOG | 15 + readme.txt | 4 +- software/SCSI2SD/src/disk.c | 27 +- software/SCSI2SD/src/inquiry.c | 22 +- software/SCSI2SD/src/mode.c | 5 +- software/SCSI2SD/src/scsi.c | 8 +- software/SCSI2SD/src/scsiPhy.c | 42 +- software/SCSI2SD/src/sd.c | 31 +- .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.c | 63 + .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.h | 42 + .../Generated_Source/PSoC5/SDCard.h | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 211 +- .../Generated_Source/PSoC5/cyfitter_cfg.c | 3006 ++++++++-------- .../Generated_Source/PSoC5/cyfittergnu.inc | 211 +- .../Generated_Source/PSoC5/cyfitteriar.inc | 211 +- .../Generated_Source/PSoC5/cyfitterrv.inc | 211 +- .../Generated_Source/PSoC5/project.h | 1 + .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx | 134 +- .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 266976 -> 272065 bytes .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj | 30 + software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd | 347 +- .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 241015 -> 247731 bytes .../v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v | 73 +- .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.c | 63 + .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.h | 42 + .../Generated_Source/PSoC5/SDCard.h | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 358 +- .../Generated_Source/PSoC5/cyfitter_cfg.c | 3056 +++++++++-------- .../Generated_Source/PSoC5/cyfittergnu.inc | 358 +- .../Generated_Source/PSoC5/cyfitteriar.inc | 358 +- .../Generated_Source/PSoC5/cyfitterrv.inc | 358 +- .../Generated_Source/PSoC5/project.h | 1 + .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx | 186 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr | Bin 139728 -> 143571 bytes .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 270212 -> 272976 bytes .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj | 60 + software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd | 1089 +++--- .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 238671 -> 248124 bytes software/include/scsi2sd.h | 1 + software/scsi2sd-util/ConfigUtil.cc | 25 +- software/scsi2sd-util/TargetPanel.cc | 21 +- software/scsi2sd-util/TargetPanel.hh | 2 + software/scsi2sd-util/scsi2sd-util.cc | 41 +- 43 files changed, 5768 insertions(+), 4953 deletions(-) create mode 100644 software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c create mode 100644 software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h create mode 100644 software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c create mode 100644 software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h diff --git a/CHANGELOG b/CHANGELOG index 5620134..f0e0e7f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,18 @@ +201507XX 4.4 + - Added configuration option to allow SCSI2 mode. This option is OFF by + default, and should only be enabled when using the SCSI2SD with a SCSI2 host + controller. Extra timing delays are added in the default SCSI1/SASI mode to + work with slow hardware. + - Modified hot-swap card detection to work with longer (60cm) microSD to SD + cables. + - Fixed off-by-one error in scsi2sd-util "Auto" sector start feature. + - Fixed crashes and stalls of scsi2sd-util after saving/loading options + to/from the device + - Fixed synchronous transfer request negotiation. + SCSI2SD now negotiates back to async transfers instead of simply + rejecting the message. + - Fixed INQUIRY response to commands lacking an allocation length. + 20150614 4.3 - Added configurable disk geometry. - Added configuration import/export function to scsi2sd-util diff --git a/readme.txt b/readme.txt index 4664ced..fe3254d 100644 --- a/readme.txt +++ b/readme.txt @@ -78,7 +78,7 @@ Compatibility Atari TT030 System V Atari MEGA STE needs J3 TERMPWR jumper - 1GB limit (--blocks=2048000) + 1GB limit (--blocks=2048000). The OS will fail to read the boot sector if the disk is >= 1GB. Sharp X68000 SASI models supported. See gamesx.com for information on building a custom cable. needs J3 TERMPWR jumper @@ -118,7 +118,7 @@ Samplers EMU E6400 w/ EOS2.80f EMU Emax2 Ensoniq ASR-X, ASR-10 (from v3.4, 2GB size limit) - ASR-20 Requires TERMPWR jumper. + ASR-10 Requires TERMPWR jumper (applies to pre. 5.0 SCSI2SD boards only) ASR-X resets when writing to devices > 2Gb. Kurzweil K2000R See kurzweil.com for size limits which a dependant on the OS version. Older OS versions have a 1GB limit. diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index a2f5cc6..a4251d5 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -527,14 +527,24 @@ void scsiDiskPoll() // systick timer interrupt saves us on the event of a race. int scsiBusy = scsiDMABusy(); int sdBusy = sdDMABusy(); - if (scsiBusy && sdBusy) __WFI(); + while (scsiBusy && sdBusy) + { + __WFI(); + scsiBusy = scsiDMABusy(); + sdBusy = sdDMABusy(); + } if (sdActive && !sdBusy && sdReadSectorDMAPoll()) { sdActive = 0; prep++; } - else if (!sdActive && + + // Usually SD is slower than the SCSI interface. + // Prioritise starting the read of the next sector over starting a + // SCSI transfer for the last sector + // ie. NO "else" HERE. + if (!sdActive && (prep - i < buffers) && (prep < totalSDSectors)) { @@ -555,7 +565,7 @@ void scsiDiskPoll() scsiActive = 0; ++i; } - else if (!scsiActive && ((prep - i) > 0)) + if (!scsiActive && ((prep - i) > 0)) { int dmaBytes = SD_SECTOR_SIZE; if ((i % sdPerScsi) == (sdPerScsi - 1)) @@ -603,14 +613,19 @@ void scsiDiskPoll() // systick timer interrupt saves us on the event of a race. int scsiBusy = scsiDMABusy(); int sdBusy = sdDMABusy(); - if (scsiBusy && sdBusy) __WFI(); + while (scsiBusy && sdBusy) + { + __WFI(); + scsiBusy = scsiDMABusy(); + sdBusy = sdDMABusy(); + } if (sdActive && !sdBusy && sdWriteSectorDMAPoll(i == (totalSDSectors - 1))) { sdActive = 0; i++; } - else if (!sdActive && ((prep - i) > 0)) + if (!sdActive && ((prep - i) > 0)) { // Start an SD transfer if we have space. sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]); @@ -625,7 +640,7 @@ void scsiDiskPoll() ++prep; lastActivityTime = now; } - else if (!scsiActive && + if (!scsiActive && ((prep - i) < buffers) && (prep < totalSDSectors) && likely(!scsiDisconnected)) diff --git a/software/SCSI2SD/src/inquiry.c b/software/SCSI2SD/src/inquiry.c index 51dd319..cf9bab7 100755 --- a/software/SCSI2SD/src/inquiry.c +++ b/software/SCSI2SD/src/inquiry.c @@ -98,8 +98,10 @@ void scsiInquiry() uint8 evpd = scsiDev.cdb[1] & 1; // enable vital product data. uint8 pageCode = scsiDev.cdb[2]; uint32 allocationLength = scsiDev.cdb[4]; + + // SASI standard, X3T9.3_185_RevE states that 0 == 256 bytes if (allocationLength == 0) allocationLength = 256; - + if (!evpd) { if (pageCode) @@ -171,6 +173,7 @@ void scsiInquiry() // with zeroes. This only seems to happen for Inquiry responses, and not // other commands that also supply an allocation length such as Mode Sense or // Request Sense. + // (See below for exception to this rule when 0 allocation length) if (scsiDev.dataLen < allocationLength) { memset( @@ -178,9 +181,20 @@ void scsiInquiry() 0, allocationLength - scsiDev.dataLen); } - // Spec 8.2.5 requires us to simply truncate the response if it's too big. - scsiDev.dataLen = allocationLength; - + if (scsiDev.cdb[4] == 0 && scsiDev.dataLen < allocationLength) + { + // Only send back the minimum number of bytes. + // Don't forcably send back 256 bytes, as that may cause problems + // with some machines (SGI Iris Indigo running IRIX) + // scsiDev.dataLen is already the correct value. + } + else + { + // Spec 8.2.5 requires us to simply truncate the response if it's + // too big. + scsiDev.dataLen = allocationLength; + } + // Set the device type as needed. switch (scsiDev.target->cfg->deviceType) { diff --git a/software/SCSI2SD/src/mode.c b/software/SCSI2SD/src/mode.c index 17ead1c..2eb3c50 100755 --- a/software/SCSI2SD/src/mode.c +++ b/software/SCSI2SD/src/mode.c @@ -551,7 +551,10 @@ int scsiModeCommand() int pc = scsiDev.cdb[2] >> 6; // Page Control int pageCode = scsiDev.cdb[2] & 0x3F; int allocLength = scsiDev.cdb[4]; - if (allocLength == 0) allocLength = 256; + + // SCSI1 standard: (CCS X3T9.2/86-52) + // "An Allocation Length of zero indicates that no MODE SENSE data shall + // be transferred. This condition shall not be considered as an error." doModeSense(1, dbd, pc, pageCode, allocLength); } else if (command == 0x5A) diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index e8aa0aa..d8f5d7c 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -560,6 +560,10 @@ static void process_SelectionPhase() target->unitAttention = 0; scsiDev.compatMode = COMPAT_SCSI1; } + else if (!(target->cfg->flags & CONFIG_ENABLE_SCSI2)) + { + scsiDev.compatMode = COMPAT_SCSI1; + } else if (scsiDev.compatMode == COMPAT_UNKNOWN) { scsiDev.compatMode = COMPAT_SCSI2; @@ -723,7 +727,7 @@ static void process_MessageOut() // Discard bytes. extmsg[i] = scsiReadByte(); } - + if (extmsg[0] == 3 && msgLen == 2) // Wide Data Request { // Negotiate down to 8bit @@ -731,7 +735,7 @@ static void process_MessageOut() static const uint8_t WDTR[] = {0x01, 0x02, 0x03, 0x00}; scsiWrite(WDTR, sizeof(WDTR)); } - else if (extmsg[0] == 1 && msgLen == 5) // Synchronous data request + else if (extmsg[0] == 1 && msgLen == 3) // Synchronous data request { // Negotiate back to async scsiEnterPhase(MESSAGE_IN); diff --git a/software/SCSI2SD/src/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c index dd3a579..08e774c 100755 --- a/software/SCSI2SD/src/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -25,8 +25,9 @@ #define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG) -// DMA controller can't handle any more bytes. -#define MAX_DMA_BYTES 4095 +// DMA controller can't handle any more than 4095 bytes, +// but we round down to nearest multiple of 4 bytes.. +#define MAX_DMA_BYTES 4088 // Private DMA variables. static int dmaInProgress = 0; @@ -235,7 +236,8 @@ scsiRead(uint8_t* data, uint32_t count) } else { - scsiReadDMA(data, count); + uint32_t alignedCount = count & 0xFFFFFFF8; + scsiReadDMA(data, alignedCount); // Wait for the next DMA interrupt (or the 1ms systick) // It's beneficial to halt the processor to @@ -243,7 +245,15 @@ scsiRead(uint8_t* data, uint32_t count) __WFI(); trace(trace_spinReadDMAPoll); - while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {}; + while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) + { + __WFI(); + }; + + if (count > alignedCount) + { + scsiReadPIO(data + alignedCount, count - alignedCount); + } } } @@ -363,7 +373,8 @@ scsiWrite(const uint8_t* data, uint32_t count) } else { - scsiWriteDMA(data, count); + uint32_t alignedCount = count & 0xFFFFFFF8; + scsiWriteDMA(data, alignedCount); // Wait for the next DMA interrupt (or the 1ms systick) // It's beneficial to halt the processor to @@ -371,7 +382,15 @@ scsiWrite(const uint8_t* data, uint32_t count) __WFI(); trace(trace_spinWriteDMAPoll); - while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {}; + while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) + { + __WFI(); + }; + + if (count > alignedCount) + { + scsiWritePIO(data + alignedCount, count - alignedCount); + } } } @@ -452,7 +471,7 @@ static void scsiPhyInitDMA() { scsiDmaRxChan = SCSI_RX_DMA_DmaInitialize( - 1, // Bytes per burst + 4, // Bytes per burst 1, // request per burst HI16(CYDEV_PERIPH_BASE), HI16(CYDEV_SRAM_BASE) @@ -460,7 +479,7 @@ static void scsiPhyInitDMA() scsiDmaTxChan = SCSI_TX_DMA_DmaInitialize( - 1, // Bytes per burst + 4, // Bytes per burst 1, // request per burst HI16(CYDEV_SRAM_BASE), HI16(CYDEV_PERIPH_BASE) @@ -486,6 +505,13 @@ void scsiPhyInit() SCSI_SEL_ISR_StartEx(scsiSelectionISR); +/* + // Disable the glitch filter for ACK to improve performance. + // TODO NEED SOME CONFIG + SCSI_Glitch_Ctl_Write(1); + CY_SET_REG8(scsiTarget_datapath__D0_REG, 0); +*/ + } // 1 = DBx error diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index fdc2b7d..e11e8b6 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -41,16 +41,18 @@ static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL; static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL; // Dummy location for DMA to send unchecked CRC bytes to -static uint8 discardBuffer; +static uint8 discardBuffer __attribute__((aligned(4))); // 2 bytes CRC, response, 8bits to close the clock.. // "NCR" time is up to 8 bytes. -static uint8_t writeResponseBuffer[8]; +static uint8_t writeResponseBuffer[8] __attribute__((aligned(4))); -static uint8_t writeStartToken = 0xFC; +// Padded with a dummy byte just to allow the tx DMA channel to +// use 2-byte bursts for performance. +static uint8_t writeStartToken[2] __attribute__((aligned(4))) = {0xFF, 0xFC}; // Source of dummy SPI bytes for DMA -static uint8 dummyBuffer = 0xFF; +static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF}; volatile uint8_t sdRxDMAComplete; volatile uint8_t sdTxDMAComplete; @@ -109,7 +111,8 @@ static uint16_t sdDoCommand( // send is static as the address must remain consistent for the static // DMA descriptors to work. - static uint8_t send[7]; + // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel. + static uint8_t send[6] __attribute__((aligned(4))); send[0] = cmd | 0x40; send[1] = param >> 24; send[2] = param >> 16; @@ -123,7 +126,6 @@ static uint16_t sdDoCommand( { send[5] = 1; // stop bit } - send[6] = 0xFF; // Result code or stuff byte. static uint8_t dmaRxTd = CY_DMA_INVALID_TD; static uint8_t dmaTxTd = CY_DMA_INVALID_TD; @@ -161,7 +163,7 @@ static uint16_t sdDoCommand( // The DMA controller is a bit trigger-happy. It will retain // a drq request that was triggered while the channel was // disabled. - CyDmaClearPendingDrq(sdDMATxChan); + CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ); CyDmaClearPendingDrq(sdDMARxChan); // There is no flow control, so we must ensure we can read the bytes @@ -172,7 +174,7 @@ static uint16_t sdDoCommand( trace(trace_spinSDDMA); while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); } - uint16_t response = discardBuffer; + uint16_t response = sdSpiByte(0xFF); // Result code or stuff byte if (unlikely(cmd == SD_STOP_TRANSMISSION)) { // Stuff byte is required for this command only. @@ -313,7 +315,7 @@ dmaReadSector(uint8_t* outputBuffer) // The DMA controller is a bit trigger-happy. It will retain // a drq request that was triggered while the channel was // disabled. - CyDmaClearPendingDrq(sdDMATxChan); + CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ); CyDmaClearPendingDrq(sdDMARxChan); // There is no flow control, so we must ensure we can read the bytes @@ -423,7 +425,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer) // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte // We need to do this without stopping the clock - CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR); + CyDmaTdSetConfiguration(dmaTxTd[0], 2, dmaTxTd[1], TD_INC_SRC_ADR); CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR)); CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR); @@ -431,7 +433,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer) CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN); CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR)); - CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0); + CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 4, dmaRxTd[1], 0); CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR); CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer)); @@ -443,7 +445,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer) // The DMA controller is a bit trigger-happy. It will retain // a drq request that was triggered while the channel was // disabled. - CyDmaClearPendingDrq(sdDMATxChan); + CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ); CyDmaClearPendingDrq(sdDMARxChan); sdTxDMAComplete = 0; @@ -733,7 +735,7 @@ static void sdInitDMA() { sdDMATxChan = SD_TX_DMA_DmaInitialize( - 1, // Bytes per burst + 2, // Bytes per burst 1, // request per burst HI16(CYDEV_SRAM_BASE), HI16(CYDEV_PERIPH_BASE) @@ -898,7 +900,8 @@ void sdPoll() SD_CS_Write(0); SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ); - CyDelayCycles(64); + // Delay extended to work with 60cm cables running cards at 2.85V + CyDelayCycles(128); uint8_t cs = SD_CS_Read(); SD_CS_SetDriveMode(SD_CS_DM_STRONG) ; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c new file mode 100644 index 0000000..8c80437 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl.c +* Version 1.70 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Glitch_Ctl.h" + +#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_Write(uint8 control) +{ + SCSI_Glitch_Ctl_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_Glitch_Ctl_Read(void) +{ + return SCSI_Glitch_Ctl_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h new file mode 100644 index 0000000..bcd7650 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl.h +* Version 1.70 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ +#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H + +#include "cytypes.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_Glitch_Ctl_Write(uint8 control) ; +uint8 SCSI_Glitch_Ctl_Read(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_Glitch_Ctl_Control (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_Glitch_Ctl_Control_PTR ( (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h index 124adc7..adee8b3 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -146,8 +146,8 @@ extern uint8 SDCard_initVar; ***************************************/ #define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT)) -#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) -#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \ +#define SDCard_INT_ON_TX_EMPTY ((uint8) (1u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \ SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) #define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT)) #define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT)) diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index bda3f9f..ebd35c1 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -381,34 +381,34 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -416,9 +416,9 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -436,8 +436,6 @@ #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u @@ -1877,15 +1875,6 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1898,37 +1887,37 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -2728,8 +2717,6 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2737,9 +2724,9 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST /* Debug_Timer_Interrupt */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2860,8 +2847,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2869,49 +2856,67 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK -#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK + +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 8829a4f..77d7a0e 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 40u +#define CY_CFG_BASE_ADDR_COUNT 42u CYPACKED typedef struct { uint8 offset; @@ -383,92 +383,96 @@ void cyfitter_cfg(void) 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010036u, /* Base address: 0x40010000 Count: 54 */ - 0x4001013Du, /* Base address: 0x40010100 Count: 61 */ + 0x40010039u, /* Base address: 0x40010000 Count: 57 */ + 0x40010135u, /* Base address: 0x40010100 Count: 53 */ 0x40010243u, /* Base address: 0x40010200 Count: 67 */ - 0x40010358u, /* Base address: 0x40010300 Count: 88 */ - 0x40010448u, /* Base address: 0x40010400 Count: 72 */ - 0x40010555u, /* Base address: 0x40010500 Count: 85 */ - 0x4001064Cu, /* Base address: 0x40010600 Count: 76 */ - 0x40010746u, /* Base address: 0x40010700 Count: 70 */ - 0x4001083Fu, /* Base address: 0x40010800 Count: 63 */ - 0x40010948u, /* Base address: 0x40010900 Count: 72 */ - 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */ - 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */ - 0x40010C42u, /* Base address: 0x40010C00 Count: 66 */ - 0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */ - 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */ - 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */ - 0x4001142Cu, /* Base address: 0x40011400 Count: 44 */ - 0x40011550u, /* Base address: 0x40011500 Count: 80 */ - 0x4001163Eu, /* Base address: 0x40011600 Count: 62 */ - 0x4001173Fu, /* Base address: 0x40011700 Count: 63 */ - 0x40011904u, /* Base address: 0x40011900 Count: 4 */ - 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ + 0x40010354u, /* Base address: 0x40010300 Count: 84 */ + 0x4001043Fu, /* Base address: 0x40010400 Count: 63 */ + 0x40010551u, /* Base address: 0x40010500 Count: 81 */ + 0x4001064Au, /* Base address: 0x40010600 Count: 74 */ + 0x4001074Du, /* Base address: 0x40010700 Count: 77 */ + 0x40010804u, /* Base address: 0x40010800 Count: 4 */ + 0x4001091Eu, /* Base address: 0x40010900 Count: 30 */ + 0x40010A54u, /* Base address: 0x40010A00 Count: 84 */ + 0x40010B53u, /* Base address: 0x40010B00 Count: 83 */ + 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */ + 0x40010D52u, /* Base address: 0x40010D00 Count: 82 */ + 0x40010E42u, /* Base address: 0x40010E00 Count: 66 */ + 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ + 0x4001145Du, /* Base address: 0x40011400 Count: 93 */ + 0x40011552u, /* Base address: 0x40011500 Count: 82 */ + 0x40011653u, /* Base address: 0x40011600 Count: 83 */ + 0x40011744u, /* Base address: 0x40011700 Count: 68 */ + 0x40011912u, /* Base address: 0x40011900 Count: 18 */ + 0x40011A4Au, /* Base address: 0x40011A00 Count: 74 */ + 0x40011B47u, /* Base address: 0x40011B00 Count: 71 */ 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ - 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */ + 0x4001411Du, /* Base address: 0x40014100 Count: 29 */ 0x40014211u, /* Base address: 0x40014200 Count: 17 */ - 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ - 0x40014411u, /* Base address: 0x40014400 Count: 17 */ + 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */ + 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ 0x40014517u, /* Base address: 0x40014500 Count: 23 */ - 0x40014608u, /* Base address: 0x40014600 Count: 8 */ - 0x4001470Du, /* Base address: 0x40014700 Count: 13 */ - 0x40014806u, /* Base address: 0x40014800 Count: 6 */ - 0x40014908u, /* Base address: 0x40014900 Count: 8 */ + 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */ + 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */ + 0x4001480Eu, /* Base address: 0x40014800 Count: 14 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */ 0x40014D04u, /* Base address: 0x40014D00 Count: 4 */ - 0x40015002u, /* Base address: 0x40015000 Count: 2 */ + 0x40015005u, /* Base address: 0x40015000 Count: 5 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x4Bu}, - {0x00u, 0x11u}, - {0x01u, 0x02u}, + {0x0Au, 0x1Bu}, + {0x00u, 0x14u}, + {0x01u, 0x11u}, {0x18u, 0x08u}, {0x19u, 0x04u}, {0x1Cu, 0x71u}, - {0x20u, 0xA0u}, - {0x21u, 0x68u}, + {0x20u, 0x60u}, + {0x21u, 0xA0u}, {0x2Cu, 0x0Eu}, - {0x30u, 0x0Au}, - {0x31u, 0x0Cu}, + {0x30u, 0x06u}, + {0x31u, 0x03u}, {0x34u, 0x80u}, {0x7Cu, 0x40u}, {0x20u, 0x02u}, - {0x84u, 0x0Fu}, - {0x00u, 0x80u}, - {0x04u, 0x10u}, - {0x0Cu, 0x02u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x28u}, - {0x10u, 0x01u}, - {0x14u, 0x32u}, - {0x15u, 0x04u}, - {0x16u, 0x44u}, - {0x1Au, 0x04u}, - {0x1Du, 0x08u}, - {0x24u, 0x4Cu}, - {0x26u, 0x32u}, - {0x29u, 0x01u}, - {0x2Eu, 0x7Eu}, - {0x30u, 0x0Eu}, - {0x31u, 0x08u}, - {0x32u, 0x70u}, - {0x33u, 0x04u}, - {0x34u, 0x01u}, - {0x35u, 0x01u}, - {0x36u, 0x80u}, - {0x37u, 0x02u}, + {0x85u, 0x0Fu}, + {0x00u, 0x01u}, + {0x02u, 0x02u}, + {0x04u, 0x04u}, + {0x05u, 0x04u}, + {0x14u, 0x02u}, + {0x15u, 0x08u}, + {0x16u, 0x01u}, + {0x18u, 0x02u}, + {0x1Au, 0x01u}, + {0x1Cu, 0x10u}, + {0x21u, 0x01u}, + {0x24u, 0x02u}, + {0x26u, 0x01u}, + {0x2Bu, 0x02u}, + {0x2Cu, 0x02u}, + {0x2Eu, 0x09u}, + {0x30u, 0x03u}, + {0x31u, 0x04u}, + {0x32u, 0x08u}, + {0x33u, 0x08u}, + {0x34u, 0x04u}, + {0x35u, 0x02u}, + {0x36u, 0x10u}, + {0x37u, 0x01u}, + {0x3Au, 0x02u}, {0x3Eu, 0x50u}, - {0x3Fu, 0x55u}, - {0x40u, 0x42u}, - {0x41u, 0x03u}, + {0x3Fu, 0x45u}, + {0x40u, 0x34u}, + {0x41u, 0x06u}, {0x42u, 0x50u}, - {0x45u, 0xF2u}, - {0x46u, 0xCDu}, - {0x47u, 0x0Eu}, + {0x45u, 0xCDu}, + {0x46u, 0xE2u}, + {0x47u, 0x0Fu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, @@ -479,7 +483,7 @@ void cyfitter_cfg(void) {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x99u}, {0x5Du, 0x01u}, {0x5Fu, 0x01u}, {0x62u, 0xC0u}, @@ -487,132 +491,125 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x88u, 0x01u}, - {0xB6u, 0x01u}, - {0xBEu, 0x40u}, - {0xD8u, 0x04u}, + {0xADu, 0x01u}, + {0xB3u, 0x01u}, + {0xBFu, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x41u}, - {0x03u, 0x10u}, - {0x05u, 0x10u}, - {0x0Au, 0x10u}, - {0x0Bu, 0x44u}, + {0x01u, 0x02u}, + {0x02u, 0x10u}, + {0x09u, 0x80u}, + {0x0Au, 0x18u}, {0x11u, 0x40u}, {0x12u, 0x20u}, - {0x18u, 0x40u}, - {0x19u, 0x48u}, - {0x1Au, 0x10u}, - {0x1Bu, 0x12u}, - {0x1Du, 0x80u}, - {0x20u, 0x04u}, + {0x19u, 0x12u}, + {0x1Au, 0x12u}, + {0x1Bu, 0x04u}, {0x21u, 0x02u}, - {0x23u, 0x22u}, - {0x2Bu, 0x04u}, - {0x31u, 0x04u}, - {0x32u, 0x80u}, - {0x3Au, 0x40u}, - {0x41u, 0x10u}, - {0x42u, 0x10u}, - {0x43u, 0x02u}, - {0x48u, 0x01u}, - {0x49u, 0x02u}, - {0x4Bu, 0x04u}, - {0x50u, 0x10u}, - {0x52u, 0x04u}, - {0x53u, 0x80u}, - {0x59u, 0x40u}, - {0x5Au, 0x08u}, - {0x5Bu, 0x22u}, - {0x60u, 0x04u}, - {0x61u, 0x82u}, - {0x63u, 0x20u}, - {0x68u, 0x90u}, - {0x69u, 0x10u}, - {0x6Au, 0x80u}, - {0x70u, 0x60u}, - {0x72u, 0x40u}, - {0x73u, 0x10u}, - {0x81u, 0x02u}, - {0x83u, 0x10u}, - {0x85u, 0x40u}, - {0x88u, 0x40u}, - {0x89u, 0x08u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x10u}, - {0xC0u, 0x4Du}, - {0xC2u, 0x0Eu}, + {0x22u, 0xA8u}, + {0x27u, 0x10u}, + {0x2Bu, 0x44u}, + {0x2Fu, 0x01u}, + {0x31u, 0x08u}, + {0x3Au, 0x04u}, + {0x41u, 0x04u}, + {0x43u, 0x01u}, + {0x48u, 0xD4u}, + {0x49u, 0x04u}, + {0x4Au, 0x01u}, + {0x50u, 0x40u}, + {0x53u, 0xA4u}, + {0x5Au, 0x46u}, + {0x5Bu, 0x10u}, + {0x61u, 0x12u}, + {0x62u, 0x88u}, + {0x69u, 0x86u}, + {0x6Bu, 0x08u}, + {0x6Cu, 0x30u}, + {0x6Eu, 0x08u}, + {0x6Fu, 0x0Au}, + {0x72u, 0x02u}, + {0x73u, 0x64u}, + {0x82u, 0x04u}, + {0x83u, 0x08u}, + {0x85u, 0x02u}, + {0x87u, 0x02u}, + {0x89u, 0x01u}, + {0x8Du, 0x40u}, + {0x8Fu, 0x20u}, + {0xC0u, 0x0Cu}, + {0xC2u, 0x07u}, {0xC4u, 0x05u}, - {0xCAu, 0x04u}, - {0xCCu, 0x0Au}, - {0xCEu, 0x08u}, - {0xD0u, 0x07u}, - {0xD2u, 0x08u}, + {0xCAu, 0x15u}, + {0xCCu, 0x02u}, + {0xCEu, 0x02u}, + {0xD0u, 0x03u}, + {0xD2u, 0x0Cu}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE0u, 0x06u}, - {0xE2u, 0x10u}, - {0xE4u, 0x04u}, - {0xE6u, 0x20u}, - {0x09u, 0x05u}, - {0x0Bu, 0x0Au}, - {0x0Du, 0x0Fu}, - {0x0Eu, 0x01u}, - {0x0Fu, 0xF0u}, - {0x10u, 0x01u}, - {0x12u, 0x02u}, - {0x15u, 0x60u}, - {0x17u, 0x90u}, - {0x19u, 0x30u}, - {0x1Bu, 0xC0u}, - {0x1Du, 0x06u}, - {0x1Fu, 0x09u}, - {0x21u, 0x03u}, - {0x23u, 0x0Cu}, - {0x25u, 0x50u}, - {0x26u, 0x02u}, - {0x27u, 0xA0u}, - {0x30u, 0x03u}, - {0x37u, 0xFFu}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x40u}, + {0xE4u, 0x0Cu}, + {0xE6u, 0x02u}, + {0x04u, 0x09u}, + {0x05u, 0x0Cu}, + {0x06u, 0x02u}, + {0x07u, 0x30u}, + {0x09u, 0x13u}, + {0x0Bu, 0x44u}, + {0x0Cu, 0x0Au}, + {0x0Du, 0x08u}, + {0x0Eu, 0x05u}, + {0x13u, 0x7Fu}, + {0x14u, 0x04u}, + {0x16u, 0x08u}, + {0x17u, 0x02u}, + {0x1Au, 0x07u}, + {0x1Du, 0x6Cu}, + {0x1Fu, 0x13u}, + {0x23u, 0x20u}, + {0x25u, 0x03u}, + {0x26u, 0x08u}, + {0x29u, 0x71u}, + {0x34u, 0x0Fu}, + {0x37u, 0x7Fu}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x83u, 0x1Fu}, - {0x85u, 0x3Fu}, - {0x86u, 0x70u}, - {0x87u, 0x40u}, - {0x89u, 0x03u}, - {0x8Cu, 0x44u}, - {0x8Du, 0x20u}, - {0x8Eu, 0x88u}, - {0x8Fu, 0x5Cu}, - {0x94u, 0x99u}, - {0x95u, 0x18u}, - {0x96u, 0x22u}, - {0x97u, 0x03u}, - {0x98u, 0xAAu}, - {0x9Au, 0x55u}, - {0x9Bu, 0x01u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x07u}, - {0x9Fu, 0x60u}, - {0xA1u, 0x02u}, - {0xA5u, 0x27u}, + {0x83u, 0x08u}, + {0x84u, 0x09u}, + {0x85u, 0x44u}, + {0x86u, 0x02u}, + {0x87u, 0x88u}, + {0x8Au, 0x07u}, + {0x8Bu, 0x07u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x80u}, + {0x8Fu, 0x80u}, + {0x90u, 0x20u}, + {0x94u, 0x10u}, + {0x97u, 0x70u}, + {0x99u, 0x99u}, + {0x9Au, 0x40u}, + {0x9Bu, 0x22u}, + {0x9Du, 0xAAu}, + {0x9Fu, 0x55u}, + {0xA0u, 0x0Au}, + {0xA2u, 0x05u}, {0xA6u, 0x08u}, - {0xA7u, 0x50u}, - {0xA9u, 0x80u}, - {0xAAu, 0x80u}, - {0xB3u, 0x80u}, - {0xB4u, 0xF0u}, + {0xA8u, 0x04u}, + {0xAAu, 0x08u}, + {0xAEu, 0x80u}, + {0xB0u, 0x20u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0xF0u}, + {0xB4u, 0x10u}, {0xB5u, 0x0Fu}, - {0xB6u, 0x0Fu}, - {0xB7u, 0x70u}, - {0xBBu, 0x80u}, - {0xBFu, 0x04u}, + {0xB6u, 0xC0u}, + {0xBEu, 0x51u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, @@ -620,1384 +617,1551 @@ void cyfitter_cfg(void) {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x03u, 0x20u}, - {0x05u, 0x40u}, + {0x00u, 0x04u}, + {0x03u, 0x0Au}, + {0x04u, 0x04u}, + {0x07u, 0x01u}, + {0x08u, 0x0Au}, {0x09u, 0x20u}, - {0x0Au, 0x12u}, - {0x0Cu, 0x02u}, - {0x0Fu, 0x80u}, - {0x10u, 0x20u}, - {0x13u, 0x10u}, - {0x17u, 0x04u}, + {0x0Cu, 0x10u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x10u}, + {0x12u, 0x82u}, + {0x13u, 0x14u}, + {0x17u, 0x08u}, {0x19u, 0x40u}, - {0x1Au, 0x02u}, - {0x1Bu, 0x30u}, - {0x1Cu, 0x80u}, - {0x20u, 0x06u}, - {0x21u, 0xB0u}, - {0x22u, 0x24u}, - {0x23u, 0x08u}, - {0x25u, 0x40u}, - {0x28u, 0x08u}, - {0x29u, 0x08u}, - {0x2Bu, 0x80u}, - {0x2Du, 0x01u}, - {0x2Eu, 0x04u}, - {0x31u, 0x80u}, - {0x32u, 0x08u}, - {0x33u, 0x10u}, - {0x34u, 0x10u}, - {0x35u, 0x40u}, - {0x37u, 0x04u}, - {0x38u, 0x64u}, + {0x1Au, 0x44u}, + {0x1Bu, 0x08u}, + {0x1Eu, 0x08u}, + {0x21u, 0x30u}, + {0x22u, 0x08u}, + {0x26u, 0x80u}, + {0x27u, 0x01u}, + {0x2Cu, 0x20u}, + {0x2Eu, 0x20u}, + {0x2Fu, 0x80u}, + {0x32u, 0x98u}, + {0x35u, 0x06u}, + {0x36u, 0x80u}, + {0x39u, 0xA8u}, {0x3Au, 0x02u}, - {0x3Fu, 0xA0u}, - {0x58u, 0x66u}, - {0x5Du, 0x80u}, - {0x5Fu, 0x20u}, - {0x61u, 0x04u}, - {0x62u, 0x80u}, - {0x63u, 0x48u}, - {0x65u, 0x30u}, - {0x66u, 0x40u}, - {0x67u, 0x02u}, - {0x6Du, 0x28u}, - {0x6Eu, 0x80u}, - {0x6Fu, 0x10u}, - {0x80u, 0x30u}, - {0x85u, 0x80u}, - {0x86u, 0x40u}, - {0x87u, 0xA0u}, - {0x88u, 0x42u}, - {0x8Au, 0x0Au}, - {0x8Du, 0x04u}, - {0x90u, 0x60u}, - {0x91u, 0x10u}, - {0x92u, 0xF0u}, - {0x93u, 0x14u}, - {0x94u, 0x01u}, - {0x95u, 0x60u}, - {0x96u, 0x08u}, - {0x97u, 0x40u}, - {0x99u, 0x08u}, - {0x9Du, 0x14u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x10u}, - {0xA0u, 0xA0u}, - {0xA3u, 0x82u}, - {0xA4u, 0x45u}, - {0xA5u, 0x40u}, - {0xA6u, 0xA0u}, - {0xA7u, 0x04u}, - {0xAAu, 0x04u}, - {0xACu, 0x14u}, - {0xADu, 0x10u}, - {0xB7u, 0x02u}, - {0xC0u, 0x85u}, - {0xC2u, 0x17u}, - {0xC4u, 0x26u}, - {0xCAu, 0xC7u}, - {0xCCu, 0x7Eu}, - {0xCEu, 0x3Fu}, - {0xD6u, 0x3Fu}, - {0xD8u, 0x3Fu}, - {0xE0u, 0x04u}, - {0xE2u, 0x0Au}, - {0xE4u, 0x08u}, - {0xE6u, 0x24u}, - {0xE8u, 0x0Bu}, - {0xEEu, 0x01u}, - {0x02u, 0x07u}, - {0x07u, 0x10u}, - {0x09u, 0x0Au}, - {0x0Bu, 0x05u}, - {0x0Cu, 0x44u}, - {0x0Du, 0x04u}, - {0x0Eu, 0x88u}, - {0x0Fu, 0x08u}, - {0x11u, 0x10u}, - {0x13u, 0x20u}, - {0x14u, 0x99u}, - {0x16u, 0x22u}, - {0x17u, 0x07u}, - {0x1Eu, 0x70u}, - {0x1Fu, 0x08u}, - {0x22u, 0x80u}, - {0x23u, 0x20u}, - {0x24u, 0xAAu}, - {0x25u, 0x09u}, - {0x26u, 0x55u}, - {0x27u, 0x02u}, - {0x2Au, 0x08u}, - {0x30u, 0x0Fu}, - {0x33u, 0x0Fu}, - {0x35u, 0x30u}, - {0x36u, 0xF0u}, + {0x3Cu, 0x88u}, {0x3Fu, 0x10u}, + {0x5Au, 0x80u}, + {0x5Bu, 0x26u}, + {0x5Fu, 0x80u}, + {0x61u, 0x80u}, + {0x62u, 0x14u}, + {0x63u, 0xA0u}, + {0x64u, 0x01u}, + {0x67u, 0x02u}, + {0x83u, 0x30u}, + {0x85u, 0x40u}, + {0x87u, 0x03u}, + {0x88u, 0x10u}, + {0x8Au, 0x10u}, + {0x8Bu, 0x02u}, + {0x90u, 0xA0u}, + {0x91u, 0x84u}, + {0x93u, 0x44u}, + {0x95u, 0x08u}, + {0x96u, 0x4Cu}, + {0x97u, 0x02u}, + {0x99u, 0x26u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x08u}, + {0x9Eu, 0x14u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x60u}, + {0xA2u, 0x20u}, + {0xA3u, 0x80u}, + {0xA4u, 0x04u}, + {0xA5u, 0x88u}, + {0xA6u, 0x01u}, + {0xA7u, 0x40u}, + {0xABu, 0xC0u}, + {0xACu, 0x10u}, + {0xADu, 0x20u}, + {0xAFu, 0x04u}, + {0xB0u, 0x80u}, + {0xB1u, 0x80u}, + {0xB7u, 0x20u}, + {0xC0u, 0xA7u}, + {0xC2u, 0x6Eu}, + {0xC4u, 0x2Fu}, + {0xCAu, 0xE0u}, + {0xCCu, 0xDEu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x1Fu}, + {0xE0u, 0x02u}, + {0xE2u, 0x01u}, + {0xE4u, 0x01u}, + {0xE6u, 0x02u}, + {0xE8u, 0x0Cu}, + {0xECu, 0x0Cu}, + {0xEEu, 0x82u}, + {0x04u, 0x02u}, + {0x05u, 0x0Bu}, + {0x07u, 0x90u}, + {0x09u, 0x20u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x03u}, + {0x0Cu, 0x02u}, + {0x0Fu, 0x04u}, + {0x12u, 0x20u}, + {0x15u, 0x08u}, + {0x16u, 0x08u}, + {0x19u, 0x21u}, + {0x1Au, 0x10u}, + {0x1Bu, 0x44u}, + {0x1Cu, 0x02u}, + {0x1Du, 0x14u}, + {0x1Fu, 0xABu}, + {0x20u, 0x02u}, + {0x21u, 0x40u}, + {0x23u, 0xBFu}, + {0x26u, 0x01u}, + {0x28u, 0x14u}, + {0x2Au, 0x28u}, + {0x2Bu, 0x0Eu}, + {0x30u, 0x02u}, + {0x32u, 0x0Cu}, + {0x33u, 0x1Fu}, + {0x34u, 0x01u}, + {0x35u, 0xE0u}, + {0x36u, 0x30u}, + {0x38u, 0x02u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x45u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Cu, 0x19u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x10u}, - {0x85u, 0x69u}, - {0x86u, 0x20u}, - {0x87u, 0x96u}, - {0x88u, 0x06u}, - {0x8Au, 0x09u}, - {0x8Bu, 0xFFu}, - {0x8Cu, 0x07u}, - {0x8Eu, 0x08u}, - {0x8Fu, 0xFFu}, - {0x90u, 0x03u}, - {0x91u, 0x0Fu}, - {0x92u, 0x0Cu}, - {0x93u, 0xF0u}, - {0x94u, 0x05u}, - {0x95u, 0xFFu}, - {0x96u, 0x0Au}, - {0x99u, 0xFFu}, - {0x9Au, 0x02u}, - {0xA2u, 0x10u}, - {0xA3u, 0xFFu}, - {0xA6u, 0x20u}, - {0xA8u, 0x01u}, - {0xA9u, 0x55u}, - {0xABu, 0xAAu}, - {0xADu, 0x33u}, - {0xAEu, 0x03u}, - {0xAFu, 0xCCu}, - {0xB0u, 0x0Fu}, - {0xB4u, 0x30u}, - {0xB7u, 0xFFu}, - {0xBAu, 0x02u}, - {0xBBu, 0x80u}, + {0x80u, 0x01u}, + {0x85u, 0x01u}, + {0x87u, 0x02u}, + {0x88u, 0x02u}, + {0x89u, 0x04u}, + {0x8Bu, 0x03u}, + {0x95u, 0x08u}, + {0x97u, 0x03u}, + {0x9Bu, 0x01u}, + {0x9Cu, 0x0Eu}, + {0x9Fu, 0x0Cu}, + {0xA4u, 0x08u}, + {0xAAu, 0x04u}, + {0xABu, 0x02u}, + {0xAEu, 0x0Eu}, + {0xB0u, 0x01u}, + {0xB1u, 0x0Fu}, + {0xB4u, 0x0Eu}, {0xBEu, 0x10u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x11u}, + {0xDCu, 0x09u}, {0xDFu, 0x01u}, {0x00u, 0x40u}, - {0x01u, 0x02u}, - {0x04u, 0x40u}, - {0x06u, 0x20u}, - {0x07u, 0x08u}, - {0x0Au, 0x12u}, - {0x0Eu, 0x90u}, - {0x0Fu, 0x04u}, + {0x02u, 0x10u}, + {0x03u, 0x08u}, + {0x05u, 0x02u}, + {0x06u, 0x08u}, + {0x08u, 0x10u}, + {0x09u, 0x02u}, + {0x0Au, 0x11u}, + {0x0Du, 0x40u}, {0x10u, 0x80u}, - {0x11u, 0x10u}, - {0x13u, 0x08u}, - {0x14u, 0x10u}, - {0x15u, 0x01u}, - {0x16u, 0x12u}, - {0x17u, 0x10u}, - {0x19u, 0x02u}, - {0x1Au, 0x02u}, - {0x1Du, 0x20u}, - {0x1Eu, 0x80u}, - {0x20u, 0x08u}, - {0x21u, 0x08u}, - {0x27u, 0x01u}, - {0x29u, 0x08u}, - {0x2Bu, 0x40u}, - {0x2Du, 0x20u}, - {0x2Eu, 0x02u}, - {0x2Fu, 0x01u}, - {0x30u, 0x02u}, - {0x31u, 0x08u}, - {0x32u, 0x40u}, - {0x36u, 0x28u}, - {0x37u, 0x01u}, - {0x38u, 0x48u}, - {0x39u, 0x20u}, - {0x3Cu, 0x40u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x08u}, - {0x5Bu, 0xA0u}, - {0x60u, 0x09u}, - {0x68u, 0x02u}, - {0x80u, 0x01u}, - {0x83u, 0x10u}, - {0x85u, 0x02u}, - {0x89u, 0x10u}, - {0x8Au, 0x40u}, - {0x8Cu, 0x24u}, - {0x8Du, 0x10u}, - {0x8Eu, 0x02u}, - {0x90u, 0x40u}, - {0x91u, 0x30u}, - {0x92u, 0xF0u}, - {0x93u, 0x46u}, - {0x94u, 0x01u}, - {0x95u, 0x01u}, - {0x99u, 0x28u}, - {0x9Bu, 0x98u}, - {0x9Cu, 0x18u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x80u}, - {0xA1u, 0x04u}, - {0xA2u, 0xA8u}, - {0xA3u, 0x06u}, - {0xA4u, 0x06u}, + {0x12u, 0x24u}, + {0x17u, 0x98u}, + {0x19u, 0x08u}, + {0x1Au, 0x88u}, + {0x1Bu, 0x40u}, + {0x1Du, 0x10u}, + {0x1Eu, 0x40u}, + {0x20u, 0x0Cu}, + {0x21u, 0x14u}, + {0x22u, 0x10u}, + {0x23u, 0x10u}, + {0x27u, 0x80u}, + {0x29u, 0x02u}, + {0x2Au, 0x20u}, + {0x2Cu, 0x08u}, + {0x31u, 0x04u}, + {0x32u, 0x90u}, + {0x36u, 0x10u}, + {0x37u, 0x88u}, + {0x38u, 0xA0u}, + {0x39u, 0x18u}, + {0x3Cu, 0x20u}, + {0x3Eu, 0x0Cu}, + {0x44u, 0x02u}, + {0x45u, 0x40u}, + {0x58u, 0x80u}, + {0x5Bu, 0x24u}, + {0x60u, 0x0Au}, + {0x61u, 0x08u}, + {0x82u, 0x40u}, + {0x83u, 0x04u}, + {0x86u, 0x02u}, + {0x88u, 0x04u}, + {0x89u, 0x14u}, + {0x8Du, 0x08u}, + {0x8Fu, 0x40u}, + {0x90u, 0xA0u}, + {0x91u, 0x04u}, + {0x93u, 0x40u}, + {0x94u, 0x04u}, + {0x95u, 0x08u}, + {0x96u, 0x28u}, + {0x97u, 0x10u}, + {0x98u, 0x11u}, + {0x99u, 0x26u}, + {0x9Cu, 0x0Au}, + {0x9Eu, 0x20u}, + {0xA1u, 0x20u}, + {0xA2u, 0xA0u}, + {0xA3u, 0x08u}, + {0xA4u, 0x04u}, + {0xA5u, 0x08u}, {0xA6u, 0x02u}, - {0xABu, 0xB0u}, - {0xACu, 0x04u}, - {0xB2u, 0x04u}, - {0xB3u, 0x08u}, - {0xB5u, 0x50u}, - {0xB6u, 0x02u}, - {0xC0u, 0xE9u}, - {0xC2u, 0x75u}, - {0xC4u, 0xFEu}, - {0xCAu, 0xB3u}, - {0xCCu, 0xEBu}, - {0xCEu, 0x7Eu}, - {0xD6u, 0x0Cu}, - {0xD8u, 0x0Cu}, - {0xE0u, 0x05u}, - {0xE2u, 0x20u}, - {0xE4u, 0x08u}, - {0xE6u, 0x80u}, - {0xEAu, 0x09u}, - {0xECu, 0x04u}, - {0xEEu, 0x10u}, + {0xAAu, 0x01u}, + {0xABu, 0x04u}, + {0xAEu, 0x08u}, + {0xAFu, 0x80u}, + {0xB6u, 0x40u}, + {0xC0u, 0x57u}, + {0xC2u, 0x8Fu}, + {0xC4u, 0xEEu}, + {0xCAu, 0x25u}, + {0xCCu, 0x7Eu}, + {0xCEu, 0x6Eu}, + {0xD6u, 0x0Eu}, + {0xD8u, 0x0Eu}, + {0xE0u, 0x02u}, + {0xE2u, 0x41u}, + {0xE8u, 0x08u}, + {0xEAu, 0x07u}, + {0xEEu, 0x41u}, {0x00u, 0x0Du}, - {0x04u, 0x01u}, - {0x05u, 0x0Fu}, - {0x06u, 0x32u}, - {0x08u, 0x62u}, - {0x09u, 0x03u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x0Cu}, + {0x04u, 0x0Du}, + {0x07u, 0xFFu}, + {0x08u, 0x0Du}, + {0x0Bu, 0xFFu}, + {0x0Du, 0x33u}, + {0x0Fu, 0xCCu}, {0x10u, 0x02u}, - {0x11u, 0x05u}, + {0x11u, 0x55u}, {0x12u, 0x0Du}, - {0x13u, 0x0Au}, - {0x14u, 0x0Du}, - {0x15u, 0x20u}, - {0x17u, 0x4Fu}, - {0x1Au, 0x10u}, - {0x1Cu, 0x02u}, - {0x1Eu, 0x54u}, - {0x1Fu, 0x70u}, + {0x13u, 0xAAu}, + {0x15u, 0x69u}, + {0x16u, 0x80u}, + {0x17u, 0x96u}, + {0x18u, 0x01u}, + {0x19u, 0x0Fu}, + {0x1Au, 0x32u}, + {0x1Bu, 0xF0u}, + {0x1Du, 0xFFu}, + {0x1Eu, 0x10u}, {0x20u, 0x0Du}, - {0x24u, 0x0Du}, - {0x25u, 0x06u}, - {0x27u, 0x09u}, - {0x29u, 0x10u}, - {0x2Bu, 0x2Fu}, + {0x23u, 0xFFu}, + {0x24u, 0x62u}, + {0x26u, 0x08u}, + {0x28u, 0x02u}, + {0x29u, 0xFFu}, + {0x2Au, 0x54u}, {0x2Cu, 0x0Du}, - {0x2Du, 0x40u}, - {0x2Fu, 0x1Fu}, {0x30u, 0x0Fu}, - {0x31u, 0x7Fu}, - {0x34u, 0x70u}, + {0x32u, 0x80u}, + {0x35u, 0xFFu}, + {0x36u, 0x70u}, {0x3Au, 0x02u}, - {0x54u, 0x01u}, + {0x3Bu, 0x20u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, {0x5Cu, 0x10u}, - {0x5Du, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0x96u}, - {0x82u, 0x69u}, - {0x85u, 0x02u}, - {0x87u, 0x11u}, + {0x80u, 0xFFu}, + {0x84u, 0x30u}, + {0x86u, 0xC0u}, + {0x87u, 0x80u}, {0x88u, 0x0Fu}, + {0x89u, 0x44u}, {0x8Au, 0xF0u}, - {0x8Du, 0x01u}, - {0x8Eu, 0xFFu}, - {0x8Fu, 0x02u}, - {0x90u, 0x55u}, - {0x92u, 0xAAu}, - {0x95u, 0x02u}, - {0x96u, 0xFFu}, - {0x97u, 0x05u}, - {0x99u, 0x02u}, - {0x9Au, 0xFFu}, - {0x9Bu, 0x09u}, - {0x9Cu, 0x33u}, - {0x9Du, 0x02u}, - {0x9Eu, 0xCCu}, - {0x9Fu, 0x01u}, - {0xA4u, 0xFFu}, - {0xA8u, 0xFFu}, - {0xB1u, 0x03u}, - {0xB3u, 0x08u}, - {0xB4u, 0xFFu}, - {0xB5u, 0x10u}, - {0xB7u, 0x04u}, - {0xBAu, 0x20u}, - {0xBBu, 0x02u}, - {0xD6u, 0x08u}, + {0x8Bu, 0x88u}, + {0x8Cu, 0xFFu}, + {0x8Fu, 0x08u}, + {0x90u, 0x50u}, + {0x92u, 0xA0u}, + {0x93u, 0x07u}, + {0x94u, 0x09u}, + {0x96u, 0x06u}, + {0x97u, 0x70u}, + {0x98u, 0x05u}, + {0x99u, 0x99u}, + {0x9Au, 0x0Au}, + {0x9Bu, 0x22u}, + {0x9Du, 0xAAu}, + {0x9Fu, 0x55u}, + {0xA4u, 0x03u}, + {0xA6u, 0x0Cu}, + {0xAAu, 0xFFu}, + {0xACu, 0x90u}, + {0xAEu, 0x60u}, + {0xB0u, 0xFFu}, + {0xB1u, 0x0Fu}, + {0xB3u, 0xF0u}, + {0xBEu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x91u}, - {0xDDu, 0x90u}, + {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x01u, 0x20u}, - {0x02u, 0x80u}, - {0x03u, 0x02u}, - {0x04u, 0x08u}, - {0x05u, 0x10u}, - {0x07u, 0x40u}, - {0x08u, 0x20u}, - {0x0Au, 0x10u}, - {0x0Bu, 0x41u}, - {0x0Cu, 0x08u}, - {0x0Eu, 0x8Au}, - {0x12u, 0x08u}, - {0x13u, 0x08u}, - {0x15u, 0x06u}, - {0x16u, 0x02u}, - {0x19u, 0x20u}, - {0x1Bu, 0x20u}, - {0x1Eu, 0x88u}, - {0x20u, 0x40u}, - {0x21u, 0x28u}, - {0x22u, 0x40u}, - {0x27u, 0x80u}, - {0x2Eu, 0x10u}, - {0x2Fu, 0x22u}, - {0x31u, 0x28u}, - {0x32u, 0x40u}, - {0x37u, 0x89u}, - {0x38u, 0x44u}, - {0x39u, 0x80u}, - {0x3Du, 0x28u}, + {0x00u, 0x04u}, + {0x01u, 0x80u}, + {0x02u, 0x44u}, + {0x03u, 0x08u}, + {0x04u, 0x28u}, + {0x07u, 0x40u}, + {0x08u, 0x14u}, + {0x09u, 0x02u}, + {0x0Cu, 0x08u}, + {0x0Eu, 0x46u}, + {0x10u, 0x20u}, + {0x11u, 0x10u}, + {0x12u, 0x01u}, + {0x15u, 0x41u}, + {0x17u, 0x18u}, + {0x18u, 0x40u}, + {0x1Eu, 0x62u}, + {0x21u, 0x08u}, + {0x22u, 0x01u}, + {0x26u, 0x20u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x20u}, + {0x31u, 0x08u}, + {0x32u, 0x91u}, + {0x34u, 0x09u}, + {0x36u, 0xA0u}, + {0x39u, 0x04u}, + {0x3Bu, 0x50u}, + {0x3Cu, 0x08u}, + {0x3Du, 0x80u}, + {0x3Fu, 0x10u}, {0x58u, 0x80u}, - {0x5Au, 0x20u}, - {0x5Fu, 0x80u}, - {0x60u, 0x04u}, - {0x63u, 0x01u}, - {0x83u, 0x40u}, - {0x8Au, 0x11u}, - {0x8Fu, 0x04u}, - {0x92u, 0x72u}, - {0x93u, 0x40u}, - {0x95u, 0x01u}, - {0x98u, 0xA0u}, - {0x99u, 0x08u}, - {0x9Bu, 0x09u}, - {0x9Eu, 0x10u}, - {0x9Fu, 0x04u}, - {0xA1u, 0x14u}, - {0xA2u, 0x88u}, - {0xA3u, 0x02u}, - {0xA6u, 0x02u}, - {0xA7u, 0x40u}, - {0xA8u, 0x02u}, - {0xAAu, 0x20u}, + {0x59u, 0x22u}, + {0x5Au, 0x08u}, + {0x63u, 0x02u}, + {0x80u, 0x80u}, + {0x85u, 0x10u}, + {0x88u, 0x20u}, + {0x89u, 0x08u}, + {0x8Au, 0x01u}, + {0x8Bu, 0x01u}, + {0x8Eu, 0x01u}, + {0x91u, 0x14u}, + {0x92u, 0x20u}, + {0x93u, 0x50u}, + {0x94u, 0x40u}, + {0x95u, 0x80u}, + {0x96u, 0x15u}, + {0x98u, 0x19u}, + {0x99u, 0x32u}, + {0x9Au, 0x20u}, + {0x9Eu, 0x14u}, + {0x9Fu, 0x18u}, + {0xA0u, 0x04u}, + {0xA1u, 0x40u}, + {0xA2u, 0x80u}, + {0xA4u, 0x98u}, + {0xA5u, 0x02u}, + {0xA6u, 0x12u}, + {0xAAu, 0x60u}, {0xABu, 0x20u}, {0xACu, 0x80u}, - {0xB1u, 0x28u}, - {0xB4u, 0x08u}, - {0xC0u, 0x7Bu}, - {0xC2u, 0xFFu}, - {0xC4u, 0xB6u}, - {0xCAu, 0x70u}, - {0xCCu, 0xDEu}, - {0xCEu, 0x6Au}, - {0xD6u, 0x1Cu}, - {0xD8u, 0x0Cu}, - {0xE2u, 0x44u}, - {0xE6u, 0xCAu}, - {0xE8u, 0x04u}, - {0xEAu, 0x01u}, - {0xEEu, 0x86u}, - {0x00u, 0x01u}, - {0x01u, 0x02u}, - {0x02u, 0x02u}, - {0x03u, 0x01u}, - {0x08u, 0x02u}, - {0x0Au, 0x01u}, - {0x0Cu, 0x04u}, - {0x0Eu, 0x08u}, - {0x15u, 0x02u}, - {0x16u, 0x20u}, - {0x17u, 0x01u}, - {0x19u, 0x02u}, - {0x1Au, 0x10u}, - {0x1Bu, 0x01u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x40u}, - {0x1Fu, 0x02u}, - {0x20u, 0x08u}, - {0x22u, 0x04u}, - {0x28u, 0x03u}, - {0x2Au, 0x0Cu}, - {0x2Du, 0x02u}, - {0x2Fu, 0x01u}, - {0x30u, 0x10u}, - {0x32u, 0x40u}, - {0x34u, 0x20u}, - {0x36u, 0x0Fu}, - {0x37u, 0x03u}, - {0x3Bu, 0x80u}, - {0x3Eu, 0x40u}, - {0x58u, 0x04u}, + {0xB1u, 0x08u}, + {0xB5u, 0x20u}, + {0xB7u, 0x08u}, + {0xC0u, 0x7Fu}, + {0xC2u, 0xFEu}, + {0xC4u, 0xF7u}, + {0xCAu, 0xA0u}, + {0xCCu, 0xFFu}, + {0xCEu, 0x7Eu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x08u}, + {0xE2u, 0x58u}, + {0xE6u, 0x01u}, + {0xEAu, 0x05u}, + {0xEEu, 0x02u}, + {0x39u, 0x80u}, + {0x3Fu, 0x40u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x99u}, {0x5Fu, 0x01u}, - {0x87u, 0x10u}, - {0x89u, 0x02u}, - {0x8Bu, 0x01u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x01u}, - {0x91u, 0x01u}, - {0x93u, 0x02u}, - {0x95u, 0x10u}, - {0x97u, 0x20u}, - {0x9Du, 0x04u}, - {0xA3u, 0x20u}, - {0xA5u, 0x08u}, - {0xA9u, 0x02u}, - {0xABu, 0x01u}, - {0xADu, 0x02u}, - {0xAFu, 0x01u}, - {0xB1u, 0x03u}, - {0xB3u, 0x08u}, - {0xB5u, 0x04u}, - {0xB7u, 0x30u}, - {0xBBu, 0x02u}, - {0xBFu, 0x40u}, - {0xD6u, 0x08u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x90u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x05u, 0x01u}, - {0x06u, 0x09u}, - {0x0Eu, 0x28u}, - {0x0Fu, 0x02u}, - {0x14u, 0x04u}, - {0x15u, 0x01u}, - {0x1Du, 0x40u}, - {0x1Eu, 0x28u}, - {0x1Fu, 0x01u}, - {0x21u, 0x42u}, - {0x22u, 0x04u}, - {0x23u, 0x48u}, - {0x25u, 0x80u}, - {0x26u, 0x80u}, - {0x28u, 0x02u}, - {0x29u, 0x10u}, - {0x2Bu, 0xA0u}, - {0x2Fu, 0x01u}, - {0x30u, 0x04u}, - {0x31u, 0x82u}, - {0x32u, 0x08u}, - {0x36u, 0x94u}, - {0x38u, 0x90u}, - {0x3Au, 0x08u}, - {0x3Fu, 0x02u}, - {0x58u, 0x80u}, - {0x5Du, 0x06u}, - {0x5Fu, 0x60u}, - {0x63u, 0x02u}, - {0x65u, 0x80u}, - {0x6Cu, 0x16u}, - {0x6Du, 0x41u}, - {0x6Fu, 0x80u}, - {0x74u, 0x80u}, - {0x76u, 0x95u}, - {0x80u, 0x80u}, - {0x86u, 0x04u}, - {0x8Au, 0x88u}, - {0x8Bu, 0x08u}, - {0x8Eu, 0x04u}, - {0x90u, 0x90u}, - {0x94u, 0x28u}, - {0x95u, 0xC0u}, - {0x98u, 0x02u}, - {0x99u, 0x91u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x10u}, - {0xA2u, 0x08u}, - {0xA3u, 0x20u}, - {0xA4u, 0x02u}, - {0xA8u, 0x80u}, - {0xAAu, 0x08u}, - {0xABu, 0x01u}, - {0xB0u, 0x40u}, - {0xB1u, 0x10u}, - {0xB2u, 0x80u}, - {0xB7u, 0x80u}, - {0xC0u, 0xD0u}, - {0xC2u, 0xE0u}, - {0xC4u, 0x50u}, - {0xCAu, 0x1Fu}, - {0xCCu, 0x7Bu}, - {0xCEu, 0x8Eu}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE0u, 0x20u}, - {0xE2u, 0x40u}, - {0xE6u, 0xF2u}, - {0xE8u, 0x40u}, + {0x24u, 0x02u}, + {0x7Au, 0x30u}, + {0x80u, 0x14u}, + {0x88u, 0x20u}, + {0x89u, 0x10u}, + {0x8Au, 0x08u}, + {0x8Cu, 0x01u}, + {0x90u, 0x10u}, + {0x91u, 0x02u}, + {0x94u, 0x08u}, + {0x95u, 0x01u}, + {0x97u, 0x01u}, + {0x98u, 0x28u}, + {0x9Au, 0x22u}, + {0x9Bu, 0x10u}, + {0x9Du, 0x0Bu}, + {0x9Eu, 0x18u}, + {0xA2u, 0x62u}, + {0xA4u, 0x80u}, + {0xABu, 0x02u}, + {0xB2u, 0x04u}, + {0xB6u, 0x01u}, + {0xB7u, 0x10u}, + {0xE0u, 0x24u}, + {0xE2u, 0xC8u}, + {0xE4u, 0x20u}, + {0xE8u, 0x10u}, {0xEAu, 0x01u}, - {0xECu, 0x20u}, + {0xECu, 0x60u}, {0xEEu, 0x02u}, - {0x03u, 0xFFu}, - {0x05u, 0x50u}, - {0x07u, 0xA0u}, - {0x09u, 0x30u}, - {0x0Bu, 0xC0u}, - {0x0Du, 0x06u}, + {0x00u, 0x04u}, + {0x02u, 0x08u}, + {0x04u, 0x02u}, + {0x06u, 0x01u}, + {0x07u, 0x20u}, + {0x08u, 0x01u}, + {0x09u, 0x04u}, + {0x0Au, 0x02u}, + {0x0Bu, 0x08u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x03u}, {0x0Eu, 0x01u}, - {0x0Fu, 0x09u}, - {0x11u, 0x60u}, - {0x12u, 0x04u}, - {0x13u, 0x90u}, - {0x17u, 0xFFu}, - {0x19u, 0x03u}, - {0x1Au, 0x08u}, - {0x1Bu, 0x0Cu}, - {0x1Du, 0x0Fu}, - {0x1Eu, 0x10u}, - {0x1Fu, 0xF0u}, - {0x20u, 0x01u}, - {0x21u, 0x05u}, - {0x22u, 0x02u}, - {0x23u, 0x0Au}, - {0x2Du, 0xFFu}, - {0x2Eu, 0x02u}, - {0x30u, 0x10u}, - {0x32u, 0x08u}, - {0x34u, 0x04u}, - {0x35u, 0xFFu}, - {0x36u, 0x03u}, - {0x3Eu, 0x40u}, + {0x0Fu, 0x0Cu}, + {0x11u, 0x02u}, + {0x12u, 0x20u}, + {0x13u, 0x01u}, + {0x14u, 0x02u}, + {0x16u, 0x01u}, + {0x1Au, 0x10u}, + {0x1Du, 0x08u}, + {0x1Fu, 0x04u}, + {0x21u, 0x01u}, + {0x22u, 0x08u}, + {0x23u, 0x02u}, + {0x24u, 0x02u}, + {0x26u, 0x01u}, + {0x27u, 0x10u}, + {0x2Au, 0x04u}, + {0x2Cu, 0x10u}, + {0x2Eu, 0x20u}, + {0x30u, 0x30u}, + {0x31u, 0x20u}, + {0x32u, 0x03u}, + {0x33u, 0x10u}, + {0x34u, 0x0Cu}, + {0x35u, 0x0Fu}, + {0x3Au, 0x08u}, + {0x3Eu, 0x11u}, {0x3Fu, 0x10u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x09u}, + {0x5Cu, 0x99u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x50u}, - {0x85u, 0xFFu}, - {0x86u, 0xA0u}, - {0x88u, 0x30u}, - {0x89u, 0x33u}, - {0x8Au, 0xC0u}, - {0x8Bu, 0xCCu}, - {0x8Cu, 0xFFu}, - {0x8Fu, 0xFFu}, - {0x90u, 0x90u}, - {0x91u, 0x0Fu}, - {0x92u, 0x60u}, - {0x93u, 0xF0u}, - {0x94u, 0x05u}, - {0x96u, 0x0Au}, - {0x97u, 0xFFu}, - {0x99u, 0x55u}, - {0x9Bu, 0xAAu}, - {0x9Cu, 0x0Fu}, - {0x9Du, 0xFFu}, - {0x9Eu, 0xF0u}, - {0xA0u, 0x09u}, - {0xA1u, 0x69u}, - {0xA2u, 0x06u}, - {0xA3u, 0x96u}, - {0xA4u, 0x03u}, - {0xA6u, 0x0Cu}, - {0xA7u, 0xFFu}, - {0xA8u, 0xFFu}, - {0xAEu, 0xFFu}, - {0xB1u, 0xFFu}, - {0xB6u, 0xFFu}, - {0xB8u, 0x02u}, - {0xBBu, 0x02u}, - {0xBEu, 0x41u}, + {0x81u, 0x60u}, + {0x83u, 0x90u}, + {0x84u, 0x03u}, + {0x85u, 0x03u}, + {0x86u, 0x0Cu}, + {0x87u, 0x0Cu}, + {0x88u, 0x06u}, + {0x89u, 0x06u}, + {0x8Au, 0x09u}, + {0x8Bu, 0x09u}, + {0x8Cu, 0x0Fu}, + {0x92u, 0x70u}, + {0x95u, 0x05u}, + {0x97u, 0x0Au}, + {0x98u, 0x20u}, + {0x99u, 0x50u}, + {0x9Au, 0x4Fu}, + {0x9Bu, 0xA0u}, + {0x9Cu, 0x05u}, + {0x9Du, 0x0Fu}, + {0x9Eu, 0x0Au}, + {0x9Fu, 0xF0u}, + {0xA1u, 0x30u}, + {0xA3u, 0xC0u}, + {0xA8u, 0x40u}, + {0xAAu, 0x1Fu}, + {0xACu, 0x10u}, + {0xAEu, 0x2Fu}, + {0xB0u, 0x7Fu}, + {0xB3u, 0xFFu}, + {0xBFu, 0x04u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x10u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x80u}, - {0x04u, 0x28u}, - {0x05u, 0x41u}, - {0x07u, 0x40u}, - {0x09u, 0x80u}, - {0x0Au, 0x44u}, - {0x0Cu, 0x82u}, - {0x0Eu, 0x20u}, - {0x10u, 0x80u}, - {0x11u, 0x40u}, - {0x14u, 0x14u}, - {0x16u, 0x81u}, - {0x18u, 0x92u}, - {0x19u, 0x10u}, - {0x1Au, 0x44u}, - {0x1Fu, 0x41u}, - {0x22u, 0x20u}, - {0x26u, 0x02u}, - {0x29u, 0x40u}, - {0x2Au, 0x02u}, - {0x2Fu, 0xA0u}, - {0x30u, 0x9Eu}, - {0x31u, 0x20u}, - {0x34u, 0x08u}, - {0x35u, 0xA0u}, - {0x36u, 0x02u}, - {0x38u, 0x28u}, - {0x3Au, 0x81u}, - {0x3Du, 0x20u}, - {0x3Fu, 0x84u}, + {0x00u, 0x10u}, + {0x01u, 0x08u}, + {0x02u, 0x42u}, + {0x03u, 0x80u}, + {0x04u, 0x08u}, + {0x06u, 0x02u}, + {0x07u, 0x08u}, + {0x08u, 0x22u}, + {0x09u, 0x28u}, + {0x0Cu, 0x20u}, + {0x0Eu, 0x42u}, + {0x10u, 0x08u}, + {0x11u, 0x41u}, + {0x13u, 0x04u}, + {0x14u, 0x05u}, + {0x18u, 0x90u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x02u}, + {0x1Eu, 0x40u}, + {0x21u, 0x08u}, + {0x22u, 0x22u}, + {0x27u, 0x10u}, + {0x29u, 0x18u}, + {0x2Au, 0x11u}, + {0x2Cu, 0x08u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x20u}, + {0x30u, 0x80u}, + {0x32u, 0x01u}, + {0x35u, 0x10u}, + {0x36u, 0x40u}, + {0x37u, 0x04u}, + {0x39u, 0x20u}, + {0x3Au, 0x40u}, + {0x3Bu, 0x04u}, + {0x3Eu, 0x08u}, + {0x3Fu, 0x21u}, {0x58u, 0x80u}, + {0x5Bu, 0x20u}, + {0x5Eu, 0x40u}, {0x60u, 0x02u}, - {0x61u, 0x80u}, - {0x81u, 0x10u}, - {0x82u, 0x01u}, - {0x84u, 0x80u}, - {0x86u, 0x12u}, - {0x8Bu, 0x04u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x02u}, - {0x8Fu, 0x60u}, - {0x90u, 0x40u}, - {0x94u, 0x2Au}, - {0x95u, 0xE0u}, - {0x97u, 0x80u}, - {0x98u, 0x08u}, - {0x99u, 0xA0u}, - {0x9Bu, 0x40u}, - {0x9Du, 0x40u}, + {0x62u, 0x80u}, + {0x63u, 0x04u}, + {0x69u, 0x40u}, + {0x7Au, 0x40u}, + {0x7Bu, 0x80u}, + {0x85u, 0x10u}, + {0x88u, 0x05u}, + {0x8Bu, 0x40u}, + {0x91u, 0x02u}, + {0x92u, 0x02u}, + {0x94u, 0x80u}, + {0x96u, 0x0Cu}, + {0x97u, 0x40u}, + {0x98u, 0x88u}, + {0x9Au, 0x22u}, + {0x9Bu, 0x2Cu}, + {0x9Cu, 0x06u}, + {0x9Du, 0x01u}, {0x9Eu, 0x10u}, - {0xA0u, 0x08u}, + {0xA0u, 0x20u}, {0xA1u, 0x20u}, - {0xA3u, 0x40u}, + {0xA2u, 0x41u}, {0xA4u, 0x80u}, - {0xA6u, 0x30u}, - {0xABu, 0x04u}, - {0xB2u, 0x10u}, - {0xB3u, 0x02u}, - {0xB4u, 0x40u}, - {0xB6u, 0x80u}, - {0xC0u, 0xE1u}, - {0xC2u, 0xBBu}, - {0xC4u, 0xF9u}, - {0xCAu, 0xC9u}, - {0xCCu, 0xFFu}, - {0xCEu, 0x7Fu}, - {0xD6u, 0x08u}, - {0xD8u, 0x08u}, - {0xE2u, 0x50u}, - {0xE4u, 0x20u}, - {0xE6u, 0x92u}, - {0xEAu, 0x49u}, - {0xECu, 0x80u}, - {0xEEu, 0x20u}, - {0x02u, 0x02u}, - {0x06u, 0x08u}, - {0x0Bu, 0x08u}, - {0x0Du, 0x04u}, - {0x0Fu, 0x08u}, - {0x15u, 0x09u}, - {0x17u, 0x02u}, - {0x1Au, 0x04u}, - {0x1Eu, 0x01u}, - {0x1Fu, 0x07u}, - {0x20u, 0x04u}, - {0x22u, 0x08u}, - {0x2Du, 0x0Au}, - {0x2Fu, 0x05u}, - {0x30u, 0x01u}, - {0x31u, 0x0Fu}, - {0x32u, 0x0Cu}, - {0x34u, 0x02u}, - {0x3Eu, 0x04u}, + {0xA6u, 0x80u}, + {0xA7u, 0x02u}, + {0xAAu, 0x40u}, + {0xACu, 0x80u}, + {0xAEu, 0x20u}, + {0xB6u, 0x40u}, + {0xC0u, 0xEFu}, + {0xC2u, 0xDEu}, + {0xC4u, 0xCFu}, + {0xCAu, 0x83u}, + {0xCCu, 0x79u}, + {0xCEu, 0xEEu}, + {0xD6u, 0x1Cu}, + {0xD8u, 0x0Cu}, + {0xE0u, 0x20u}, + {0xE2u, 0x01u}, + {0xE4u, 0xE0u}, + {0xEAu, 0x17u}, + {0xEEu, 0x42u}, + {0x00u, 0x08u}, + {0x01u, 0x33u}, + {0x02u, 0x16u}, + {0x03u, 0xCCu}, + {0x05u, 0xFFu}, + {0x06u, 0x40u}, + {0x09u, 0x0Fu}, + {0x0Au, 0x04u}, + {0x0Bu, 0xF0u}, + {0x0Eu, 0x07u}, + {0x0Fu, 0xFFu}, + {0x10u, 0x07u}, + {0x12u, 0x18u}, + {0x15u, 0x96u}, + {0x16u, 0x07u}, + {0x17u, 0x69u}, + {0x18u, 0x0Cu}, + {0x1Au, 0x13u}, + {0x1Bu, 0xFFu}, + {0x1Cu, 0x20u}, + {0x1Eu, 0x40u}, + {0x20u, 0x01u}, + {0x25u, 0x55u}, + {0x26u, 0x20u}, + {0x27u, 0xAAu}, + {0x28u, 0x0Fu}, + {0x2Au, 0x10u}, + {0x2Bu, 0xFFu}, + {0x2Cu, 0x01u}, + {0x2Du, 0xFFu}, + {0x2Eu, 0x02u}, + {0x30u, 0x1Fu}, + {0x34u, 0x60u}, + {0x35u, 0xFFu}, + {0x3Au, 0x02u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x19u}, + {0x5Cu, 0x11u}, {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x82u, 0x02u}, - {0x84u, 0x08u}, - {0x86u, 0x04u}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x08u}, - {0x8Eu, 0x04u}, - {0x90u, 0x02u}, - {0x92u, 0x01u}, - {0x94u, 0x02u}, - {0x96u, 0x01u}, - {0x97u, 0x08u}, - {0x9Bu, 0x01u}, - {0x9Cu, 0x04u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x08u}, - {0x9Fu, 0x02u}, - {0xA0u, 0x08u}, - {0xA2u, 0x04u}, - {0xA4u, 0x02u}, - {0xA6u, 0x01u}, - {0xA7u, 0x10u}, - {0xA8u, 0x02u}, - {0xAAu, 0x01u}, - {0xABu, 0x04u}, - {0xACu, 0x08u}, - {0xAEu, 0x04u}, - {0xB0u, 0x03u}, - {0xB1u, 0x04u}, - {0xB3u, 0x10u}, - {0xB5u, 0x08u}, - {0xB6u, 0x0Cu}, - {0xB7u, 0x03u}, - {0xBAu, 0x82u}, - {0xBFu, 0x40u}, + {0x82u, 0x10u}, + {0x85u, 0x02u}, + {0x87u, 0x01u}, + {0x8Cu, 0x10u}, + {0x90u, 0x10u}, + {0x92u, 0x60u}, + {0x93u, 0x04u}, + {0x98u, 0x3Au}, + {0x99u, 0x01u}, + {0x9Au, 0x45u}, + {0x9Bu, 0x02u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x07u}, + {0x9Fu, 0x01u}, + {0xA1u, 0x02u}, + {0xA3u, 0x01u}, + {0xA6u, 0x08u}, + {0xA8u, 0x24u}, + {0xAAu, 0x58u}, + {0xACu, 0x29u}, + {0xADu, 0x02u}, + {0xAEu, 0x52u}, + {0xAFu, 0x01u}, + {0xB0u, 0x70u}, + {0xB3u, 0x04u}, + {0xB5u, 0x03u}, + {0xB6u, 0x0Fu}, + {0xBAu, 0x02u}, + {0xBBu, 0x20u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x99u}, + {0xDCu, 0x91u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x88u}, - {0x02u, 0x80u}, - {0x05u, 0x01u}, - {0x06u, 0x10u}, - {0x08u, 0x02u}, - {0x0Au, 0x22u}, - {0x0Fu, 0x0Au}, - {0x12u, 0x4Au}, - {0x13u, 0x04u}, - {0x14u, 0x40u}, - {0x18u, 0x40u}, - {0x19u, 0x80u}, - {0x1Au, 0x03u}, - {0x1Cu, 0x88u}, - {0x1Du, 0x15u}, - {0x22u, 0x0Au}, - {0x23u, 0x06u}, - {0x27u, 0x40u}, - {0x28u, 0x10u}, - {0x29u, 0x10u}, + {0x00u, 0x02u}, + {0x03u, 0x02u}, + {0x04u, 0x80u}, + {0x05u, 0x10u}, + {0x06u, 0x90u}, + {0x0Au, 0x82u}, + {0x0Bu, 0x06u}, + {0x0Eu, 0x61u}, + {0x0Fu, 0x04u}, + {0x10u, 0x04u}, + {0x11u, 0x04u}, + {0x13u, 0x40u}, + {0x14u, 0x14u}, + {0x15u, 0x01u}, + {0x16u, 0x02u}, + {0x17u, 0x04u}, + {0x1Au, 0x82u}, + {0x1Eu, 0x40u}, + {0x1Fu, 0x10u}, + {0x21u, 0x28u}, + {0x25u, 0x10u}, + {0x27u, 0x08u}, + {0x29u, 0x82u}, + {0x2Cu, 0x04u}, + {0x2Eu, 0x04u}, {0x2Fu, 0x02u}, - {0x30u, 0xC0u}, - {0x31u, 0x20u}, - {0x32u, 0x08u}, - {0x34u, 0x08u}, - {0x37u, 0x40u}, - {0x38u, 0x20u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x80u}, - {0x58u, 0x10u}, - {0x5Au, 0x60u}, - {0x5Cu, 0x24u}, - {0x5Du, 0x02u}, - {0x5Fu, 0x80u}, - {0x62u, 0x40u}, - {0x63u, 0x02u}, - {0x64u, 0x01u}, - {0x80u, 0x04u}, - {0x81u, 0x40u}, - {0x85u, 0x02u}, + {0x31u, 0x21u}, + {0x32u, 0x80u}, + {0x35u, 0x04u}, + {0x36u, 0x10u}, + {0x38u, 0x08u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x80u}, + {0x3Fu, 0x45u}, + {0x59u, 0x40u}, + {0x63u, 0x01u}, + {0x6Cu, 0x02u}, + {0x6Eu, 0x80u}, + {0x81u, 0x04u}, + {0x84u, 0x20u}, + {0x86u, 0x04u}, + {0x87u, 0x04u}, + {0x88u, 0x0Au}, + {0x89u, 0x41u}, {0x8Au, 0x01u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x20u}, - {0x92u, 0x70u}, - {0x94u, 0x2Cu}, - {0x95u, 0x60u}, - {0x97u, 0x80u}, - {0x98u, 0x2Bu}, - {0x9Bu, 0x80u}, - {0x9Du, 0xC4u}, - {0x9Fu, 0x02u}, - {0xA0u, 0x08u}, - {0xA1u, 0x20u}, - {0xA3u, 0x40u}, - {0xA4u, 0x80u}, - {0xA6u, 0x30u}, - {0xA8u, 0x10u}, - {0xAAu, 0x40u}, - {0xABu, 0x80u}, - {0xACu, 0x20u}, - {0xADu, 0x01u}, - {0xB6u, 0x60u}, - {0xB7u, 0x40u}, - {0xC0u, 0x3Du}, - {0xC2u, 0xCDu}, - {0xC4u, 0x1Fu}, - {0xCAu, 0x16u}, - {0xCCu, 0x5Eu}, - {0xCEu, 0x34u}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE0u, 0x11u}, - {0xE2u, 0xAAu}, - {0xE6u, 0x84u}, - {0xEAu, 0x04u}, - {0xECu, 0x40u}, - {0x07u, 0x02u}, - {0x08u, 0x30u}, - {0x0Au, 0xC0u}, - {0x0Cu, 0x60u}, - {0x0Eu, 0x90u}, - {0x10u, 0xFFu}, - {0x14u, 0x05u}, - {0x16u, 0x0Au}, + {0x8Fu, 0x20u}, + {0x90u, 0x08u}, + {0x91u, 0x05u}, + {0x94u, 0x80u}, + {0x97u, 0x62u}, + {0x98u, 0x18u}, + {0x99u, 0x92u}, + {0x9Au, 0x02u}, + {0x9Cu, 0x06u}, + {0x9Du, 0x01u}, + {0xA0u, 0x01u}, + {0xA2u, 0x11u}, + {0xA4u, 0xAAu}, + {0xA5u, 0x08u}, + {0xA9u, 0x10u}, + {0xABu, 0x50u}, + {0xADu, 0x11u}, + {0xAEu, 0x01u}, + {0xB2u, 0x08u}, + {0xB3u, 0x08u}, + {0xB5u, 0x40u}, + {0xB6u, 0x40u}, + {0xC0u, 0xF9u}, + {0xC2u, 0xFBu}, + {0xC4u, 0xF7u}, + {0xCAu, 0x79u}, + {0xCCu, 0x6Du}, + {0xCEu, 0xF2u}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE0u, 0x20u}, + {0xE2u, 0x01u}, + {0xE4u, 0x28u}, + {0xE6u, 0x82u}, + {0xE8u, 0x60u}, + {0xECu, 0x80u}, + {0xEEu, 0x01u}, + {0x02u, 0x02u}, + {0x03u, 0x04u}, + {0x09u, 0x02u}, + {0x0Bu, 0x01u}, + {0x0Du, 0x01u}, + {0x0Fu, 0x02u}, + {0x11u, 0x04u}, + {0x12u, 0x01u}, + {0x13u, 0x08u}, + {0x15u, 0x02u}, + {0x16u, 0x04u}, {0x17u, 0x01u}, - {0x18u, 0x03u}, - {0x1Au, 0x0Cu}, - {0x1Du, 0x01u}, - {0x1Eu, 0xFFu}, - {0x1Fu, 0x02u}, - {0x20u, 0x0Fu}, - {0x22u, 0xF0u}, - {0x24u, 0x50u}, - {0x26u, 0xA0u}, - {0x28u, 0x06u}, - {0x2Au, 0x09u}, - {0x2Eu, 0xFFu}, - {0x2Fu, 0x04u}, - {0x30u, 0xFFu}, - {0x33u, 0x03u}, - {0x35u, 0x04u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x04u}, + {0x1Au, 0x08u}, + {0x1Fu, 0x08u}, + {0x21u, 0x02u}, + {0x23u, 0x01u}, + {0x29u, 0x02u}, + {0x2Bu, 0x01u}, + {0x30u, 0x08u}, + {0x31u, 0x03u}, + {0x32u, 0x04u}, + {0x34u, 0x01u}, + {0x36u, 0x02u}, + {0x37u, 0x0Cu}, + {0x3Bu, 0x02u}, + {0x3Fu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x90u}, + {0x5Cu, 0x99u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x83u, 0x10u}, - {0x84u, 0x50u}, - {0x86u, 0xA0u}, - {0x87u, 0x20u}, - {0x88u, 0x30u}, - {0x8Au, 0xC0u}, - {0x8Bu, 0x0Eu}, - {0x8Du, 0x01u}, - {0x8Eu, 0xFFu}, - {0x94u, 0x05u}, - {0x95u, 0x32u}, - {0x96u, 0x0Au}, - {0x97u, 0x04u}, - {0x98u, 0x03u}, - {0x99u, 0x01u}, - {0x9Au, 0x0Cu}, + {0x84u, 0x55u}, + {0x86u, 0xAAu}, + {0x88u, 0x33u}, + {0x8Au, 0xCCu}, + {0x8Bu, 0x08u}, + {0x8Cu, 0xFFu}, + {0x8Du, 0x19u}, + {0x8Fu, 0x02u}, + {0x92u, 0xFFu}, + {0x93u, 0x10u}, + {0x94u, 0x69u}, + {0x96u, 0x96u}, + {0x97u, 0x10u}, + {0x98u, 0xFFu}, + {0x9Bu, 0x07u}, {0x9Cu, 0x0Fu}, - {0x9Du, 0x01u}, {0x9Eu, 0xF0u}, - {0xA1u, 0x01u}, - {0xA2u, 0xFFu}, - {0xA5u, 0x34u}, + {0xA5u, 0x1Au}, {0xA6u, 0xFFu}, - {0xA7u, 0x0Au}, - {0xA8u, 0x09u}, - {0xA9u, 0x28u}, - {0xAAu, 0x06u}, - {0xABu, 0x10u}, - {0xACu, 0x90u}, - {0xAEu, 0x60u}, - {0xAFu, 0x20u}, - {0xB0u, 0xFFu}, - {0xB3u, 0x01u}, - {0xB5u, 0x1Eu}, - {0xB7u, 0x20u}, - {0xB9u, 0x08u}, - {0xBEu, 0x01u}, - {0xBFu, 0x44u}, + {0xA7u, 0x05u}, + {0xA9u, 0x14u}, + {0xAAu, 0xFFu}, + {0xABu, 0x08u}, + {0xB1u, 0x10u}, + {0xB3u, 0x0Fu}, + {0xB6u, 0xFFu}, + {0xBAu, 0x80u}, + {0xBFu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x10u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x01u, 0x40u}, - {0x02u, 0x04u}, - {0x04u, 0x28u}, - {0x05u, 0x40u}, - {0x06u, 0x14u}, - {0x09u, 0x1Au}, - {0x0Bu, 0x02u}, - {0x0Cu, 0x80u}, - {0x0Du, 0x28u}, - {0x0Eu, 0x20u}, - {0x10u, 0x86u}, - {0x12u, 0x10u}, - {0x14u, 0x04u}, - {0x15u, 0x60u}, - {0x17u, 0x09u}, - {0x18u, 0x40u}, - {0x1Eu, 0x80u}, - {0x22u, 0x10u}, - {0x23u, 0x20u}, - {0x24u, 0x10u}, - {0x25u, 0x30u}, - {0x26u, 0x80u}, - {0x28u, 0x02u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x80u}, - {0x2Eu, 0x20u}, - {0x2Fu, 0x40u}, - {0x30u, 0x80u}, + {0x01u, 0x02u}, + {0x04u, 0x80u}, + {0x06u, 0x08u}, + {0x07u, 0x11u}, + {0x08u, 0x02u}, + {0x09u, 0x08u}, + {0x0Au, 0x04u}, + {0x0Cu, 0x28u}, + {0x0Eu, 0x02u}, + {0x0Fu, 0x40u}, + {0x14u, 0x24u}, + {0x18u, 0x08u}, + {0x19u, 0x82u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x04u}, + {0x1Eu, 0x02u}, + {0x20u, 0x40u}, + {0x22u, 0x41u}, + {0x25u, 0x01u}, + {0x27u, 0x20u}, + {0x29u, 0x01u}, + {0x2Bu, 0x04u}, + {0x2Cu, 0x24u}, + {0x30u, 0x82u}, {0x31u, 0x08u}, - {0x34u, 0x08u}, - {0x36u, 0x60u}, - {0x38u, 0x08u}, - {0x3Cu, 0x44u}, - {0x3Du, 0x21u}, - {0x5Au, 0x80u}, - {0x60u, 0x02u}, - {0x65u, 0x40u}, - {0x67u, 0x02u}, - {0x78u, 0x01u}, - {0x7Au, 0x80u}, - {0x80u, 0x22u}, - {0x83u, 0x2Au}, - {0x84u, 0x08u}, - {0x85u, 0x02u}, - {0x87u, 0x01u}, - {0x88u, 0x08u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x10u}, - {0xC0u, 0xE3u}, - {0xC2u, 0xEFu}, - {0xC4u, 0xFFu}, - {0xCAu, 0xF8u}, - {0xCCu, 0x7Au}, - {0xCEu, 0xF2u}, - {0xD6u, 0x08u}, - {0xD8u, 0x08u}, - {0xE0u, 0x81u}, - {0xE2u, 0x50u}, - {0xE4u, 0x11u}, - {0x81u, 0x5Cu}, - {0x84u, 0x14u}, - {0x85u, 0x24u}, + {0x34u, 0x10u}, + {0x37u, 0x29u}, + {0x38u, 0x40u}, + {0x3Au, 0x10u}, + {0x3Bu, 0x02u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x40u}, + {0x45u, 0x01u}, + {0x46u, 0x40u}, + {0x59u, 0x20u}, + {0x5Bu, 0x40u}, + {0x5Du, 0x51u}, + {0x5Fu, 0x08u}, + {0x60u, 0x08u}, + {0x62u, 0x90u}, + {0x66u, 0x40u}, + {0x81u, 0x20u}, + {0x82u, 0x02u}, + {0x84u, 0x21u}, + {0x86u, 0x10u}, {0x87u, 0x10u}, - {0x88u, 0x3Fu}, - {0x89u, 0x50u}, - {0x8Au, 0x40u}, - {0x8Bu, 0x0Cu}, - {0x8Cu, 0x34u}, - {0x90u, 0x34u}, - {0x91u, 0x21u}, - {0x93u, 0x1Eu}, - {0x94u, 0x20u}, - {0x95u, 0x11u}, - {0x96u, 0x02u}, - {0x97u, 0x22u}, - {0x98u, 0x08u}, - {0x99u, 0x30u}, - {0x9Au, 0x75u}, - {0x9Bu, 0x0Fu}, - {0x9Cu, 0x4Bu}, - {0x9Eu, 0x30u}, - {0xA0u, 0x34u}, - {0xA1u, 0x5Cu}, - {0xA5u, 0x54u}, - {0xA6u, 0x34u}, - {0xA7u, 0x08u}, - {0xA8u, 0x14u}, - {0xA9u, 0x08u}, - {0xAAu, 0x20u}, - {0xADu, 0x0Cu}, - {0xAFu, 0x50u}, - {0xB3u, 0x30u}, - {0xB4u, 0x07u}, - {0xB5u, 0x0Fu}, - {0xB6u, 0x78u}, - {0xB7u, 0x40u}, + {0x89u, 0x04u}, + {0x8Eu, 0x90u}, + {0xC0u, 0xE8u}, + {0xC2u, 0xFEu}, + {0xC4u, 0x60u}, + {0xCAu, 0x65u}, + {0xCCu, 0xEBu}, + {0xCEu, 0x3Du}, + {0xD6u, 0xFCu}, + {0xD8u, 0x1Cu}, + {0xE0u, 0x20u}, + {0xE2u, 0x40u}, + {0xE4u, 0x10u}, + {0xE6u, 0x01u}, + {0x02u, 0x02u}, + {0x08u, 0x01u}, + {0x09u, 0x01u}, + {0x0Au, 0x02u}, + {0x1Eu, 0x01u}, + {0x32u, 0x03u}, + {0x35u, 0x01u}, + {0x3Eu, 0x04u}, + {0x40u, 0x36u}, + {0x41u, 0x02u}, + {0x42u, 0x10u}, + {0x44u, 0x05u}, + {0x45u, 0xDEu}, + {0x46u, 0xF0u}, + {0x47u, 0xCBu}, + {0x48u, 0x3Bu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x22u}, + {0x4Eu, 0xF0u}, + {0x4Fu, 0x08u}, + {0x50u, 0x04u}, + {0x54u, 0x40u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x90u}, + {0x5Fu, 0x01u}, + {0x62u, 0xC0u}, + {0x64u, 0x40u}, + {0x65u, 0x01u}, + {0x66u, 0x10u}, + {0x67u, 0x11u}, + {0x68u, 0xC0u}, + {0x69u, 0x01u}, + {0x6Bu, 0x11u}, + {0x6Cu, 0x40u}, + {0x6Du, 0x01u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x01u}, + {0x80u, 0x31u}, + {0x81u, 0xC1u}, + {0x84u, 0x01u}, + {0x85u, 0x07u}, + {0x86u, 0x30u}, + {0x87u, 0x18u}, + {0x88u, 0x43u}, + {0x89u, 0xC0u}, + {0x8Au, 0x3Cu}, + {0x8Cu, 0x31u}, + {0x8Du, 0x01u}, + {0x8Fu, 0xC0u}, + {0x90u, 0x30u}, + {0x92u, 0x01u}, + {0x93u, 0x40u}, + {0x94u, 0x06u}, + {0x95u, 0x22u}, + {0x96u, 0xB9u}, + {0x97u, 0x08u}, + {0x98u, 0x05u}, + {0x99u, 0x08u}, + {0x9Au, 0x4Au}, + {0x9Bu, 0x21u}, + {0x9Cu, 0xC0u}, + {0x9Du, 0xC1u}, + {0xA0u, 0x20u}, + {0xA1u, 0x04u}, + {0xA4u, 0x11u}, + {0xA5u, 0xC1u}, + {0xA6u, 0x20u}, + {0xA9u, 0x10u}, + {0xACu, 0x12u}, + {0xADu, 0x01u}, + {0xAEu, 0x01u}, + {0xB0u, 0x03u}, + {0xB1u, 0x3Fu}, + {0xB3u, 0x40u}, + {0xB4u, 0x3Cu}, + {0xB6u, 0xC4u}, + {0xB7u, 0x80u}, {0xB8u, 0x80u}, - {0xBAu, 0x30u}, - {0xBBu, 0x08u}, - {0xBFu, 0x40u}, + {0xB9u, 0x02u}, + {0xBAu, 0x02u}, + {0xBFu, 0x45u}, + {0xD6u, 0x02u}, + {0xD7u, 0x24u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x01u}, - {0x03u, 0x06u}, + {0x00u, 0x02u}, + {0x03u, 0x08u}, + {0x04u, 0x08u}, + {0x05u, 0x10u}, {0x06u, 0x02u}, - {0x07u, 0x14u}, - {0x09u, 0x20u}, - {0x0Bu, 0xA2u}, + {0x07u, 0x40u}, + {0x0Au, 0x02u}, {0x0Cu, 0x02u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x06u}, - {0x10u, 0x82u}, - {0x11u, 0x04u}, - {0x12u, 0x08u}, - {0x15u, 0x01u}, - {0x17u, 0x28u}, - {0x18u, 0x04u}, - {0x19u, 0x80u}, - {0x1Bu, 0x03u}, - {0x1Du, 0x10u}, + {0x0Du, 0x40u}, + {0x0Eu, 0x26u}, + {0x14u, 0x01u}, + {0x15u, 0x06u}, + {0x19u, 0x08u}, {0x1Eu, 0x06u}, - {0x1Fu, 0x70u}, - {0x21u, 0x20u}, - {0x24u, 0x29u}, - {0x25u, 0x04u}, - {0x26u, 0x08u}, - {0x27u, 0x15u}, - {0x29u, 0x01u}, - {0x2Bu, 0x21u}, - {0x2Cu, 0x02u}, - {0x2Du, 0x05u}, - {0x2Fu, 0x04u}, - {0x30u, 0x82u}, - {0x32u, 0x10u}, - {0x33u, 0x04u}, - {0x35u, 0x10u}, - {0x36u, 0x01u}, - {0x37u, 0x04u}, - {0x38u, 0x20u}, - {0x39u, 0x05u}, - {0x3Bu, 0x80u}, - {0x3Du, 0x08u}, - {0x3Eu, 0x12u}, - {0x40u, 0x01u}, - {0x43u, 0x24u}, - {0x49u, 0x05u}, - {0x4Au, 0x05u}, - {0x4Bu, 0x02u}, - {0x51u, 0x08u}, - {0x52u, 0x50u}, - {0x53u, 0x04u}, - {0x60u, 0x20u}, - {0x61u, 0x0Au}, - {0x68u, 0x0Au}, - {0x69u, 0x05u}, - {0x6Au, 0x30u}, - {0x6Bu, 0x68u}, - {0x70u, 0x80u}, - {0x72u, 0x02u}, - {0x8Eu, 0x04u}, - {0x94u, 0x08u}, - {0x95u, 0x04u}, - {0x96u, 0x10u}, - {0x97u, 0x82u}, - {0x9Cu, 0x20u}, - {0x9Du, 0x94u}, - {0x9Eu, 0x52u}, - {0x9Fu, 0x45u}, - {0xA1u, 0x02u}, - {0xA4u, 0x0Au}, - {0xA6u, 0x01u}, - {0xC0u, 0xEFu}, - {0xC2u, 0xFFu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0xFBu}, - {0xCCu, 0xEFu}, - {0xCEu, 0xEFu}, + {0x1Fu, 0x11u}, + {0x21u, 0x10u}, + {0x24u, 0x90u}, + {0x25u, 0x80u}, + {0x27u, 0x02u}, + {0x2Cu, 0x09u}, + {0x2Du, 0x04u}, + {0x2Fu, 0x41u}, + {0x35u, 0x02u}, + {0x36u, 0x14u}, + {0x37u, 0x40u}, + {0x39u, 0x10u}, + {0x3Du, 0xA0u}, + {0x3Eu, 0x06u}, + {0x41u, 0x88u}, + {0x42u, 0x04u}, + {0x49u, 0x86u}, + {0x4Au, 0x84u}, + {0x50u, 0x08u}, + {0x51u, 0x01u}, + {0x52u, 0x10u}, + {0x60u, 0x10u}, + {0x61u, 0x01u}, + {0x62u, 0x90u}, + {0x67u, 0x04u}, + {0x6Cu, 0x16u}, + {0x6Du, 0xE4u}, + {0x6Fu, 0x40u}, + {0x76u, 0x02u}, + {0x84u, 0x01u}, + {0x85u, 0x80u}, + {0x89u, 0x10u}, + {0x8Au, 0x06u}, + {0x8Cu, 0x04u}, + {0x92u, 0x02u}, + {0x93u, 0x84u}, + {0x94u, 0xACu}, + {0x95u, 0xE6u}, + {0x96u, 0x0Cu}, + {0x97u, 0x22u}, + {0x99u, 0x10u}, + {0x9Du, 0x0Du}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x42u}, + {0xA1u, 0x08u}, + {0xA2u, 0x14u}, + {0xA3u, 0x08u}, + {0xA4u, 0x08u}, + {0xA5u, 0x50u}, + {0xA6u, 0x02u}, + {0xA8u, 0x02u}, + {0xA9u, 0x82u}, + {0xADu, 0x29u}, + {0xB0u, 0x04u}, + {0xB2u, 0x90u}, + {0xB3u, 0x08u}, + {0xB4u, 0x40u}, + {0xC0u, 0xFAu}, + {0xC2u, 0xF1u}, + {0xC4u, 0xB0u}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF0u}, + {0xCEu, 0xF4u}, {0xD0u, 0x0Eu}, {0xD2u, 0x0Cu}, - {0xD8u, 0x01u}, - {0xE0u, 0x40u}, - {0x00u, 0x08u}, + {0xD8u, 0x2Fu}, + {0xE6u, 0x08u}, + {0xEAu, 0x05u}, + {0x00u, 0x34u}, + {0x01u, 0xC0u}, {0x03u, 0x01u}, - {0x04u, 0x01u}, - {0x07u, 0x0Cu}, - {0x08u, 0x04u}, - {0x09u, 0x60u}, - {0x11u, 0x14u}, - {0x12u, 0x08u}, - {0x13u, 0x43u}, - {0x14u, 0x08u}, - {0x15u, 0x11u}, - {0x17u, 0x22u}, - {0x18u, 0x07u}, - {0x19u, 0x28u}, - {0x1Bu, 0x13u}, - {0x1Eu, 0x02u}, - {0x22u, 0x08u}, - {0x24u, 0x08u}, - {0x2Au, 0x07u}, - {0x2Cu, 0x08u}, - {0x2Fu, 0x82u}, - {0x30u, 0x07u}, - {0x33u, 0x0Fu}, - {0x34u, 0x08u}, - {0x35u, 0x70u}, - {0x37u, 0x80u}, - {0x39u, 0x20u}, - {0x3Eu, 0x11u}, - {0x54u, 0x40u}, - {0x56u, 0x04u}, + {0x05u, 0x1Fu}, + {0x06u, 0x34u}, + {0x07u, 0x20u}, + {0x08u, 0x14u}, + {0x09u, 0xC0u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x08u}, + {0x0Cu, 0x80u}, + {0x0Du, 0x90u}, + {0x0Fu, 0x40u}, + {0x10u, 0x20u}, + {0x12u, 0x02u}, + {0x13u, 0x60u}, + {0x14u, 0x4Bu}, + {0x15u, 0x7Fu}, + {0x16u, 0x30u}, + {0x17u, 0x80u}, + {0x18u, 0x3Fu}, + {0x1Au, 0x40u}, + {0x1Bu, 0xFFu}, + {0x1Cu, 0x14u}, + {0x1Du, 0xC0u}, + {0x1Fu, 0x02u}, + {0x20u, 0x34u}, + {0x24u, 0x08u}, + {0x25u, 0xC0u}, + {0x26u, 0x75u}, + {0x27u, 0x04u}, + {0x28u, 0x80u}, + {0x2Bu, 0x9Fu}, + {0x2Cu, 0x34u}, + {0x2Du, 0x80u}, + {0x32u, 0x78u}, + {0x33u, 0xFFu}, + {0x34u, 0x07u}, + {0x36u, 0x80u}, + {0x38u, 0x88u}, + {0x3Au, 0x30u}, + {0x3Fu, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, - {0x82u, 0x07u}, - {0x84u, 0x09u}, - {0x85u, 0x09u}, - {0x86u, 0x02u}, - {0x87u, 0x06u}, - {0x8Cu, 0x04u}, - {0x8Du, 0x0Bu}, - {0x8Eu, 0x08u}, - {0x8Fu, 0x04u}, - {0x91u, 0x04u}, - {0x92u, 0x08u}, - {0x93u, 0x03u}, - {0xA4u, 0x0Au}, - {0xA6u, 0x05u}, - {0xA9u, 0x0Du}, - {0xABu, 0x02u}, - {0xB0u, 0x0Fu}, - {0xB1u, 0x07u}, - {0xB7u, 0x08u}, - {0xBBu, 0x02u}, - {0xBFu, 0x40u}, + {0x82u, 0xFFu}, + {0x84u, 0x30u}, + {0x86u, 0xC0u}, + {0x88u, 0x0Fu}, + {0x89u, 0x11u}, + {0x8Au, 0xF0u}, + {0x8Bu, 0x0Eu}, + {0x8Cu, 0x60u}, + {0x8Eu, 0x90u}, + {0x90u, 0x50u}, + {0x92u, 0xA0u}, + {0x94u, 0x06u}, + {0x95u, 0x1Bu}, + {0x96u, 0x09u}, + {0x97u, 0x04u}, + {0x98u, 0x05u}, + {0x99u, 0x04u}, + {0x9Au, 0x0Au}, + {0x9Bu, 0x03u}, + {0xA4u, 0x03u}, + {0xA6u, 0x0Cu}, + {0xA9u, 0x15u}, + {0xAAu, 0xFFu}, + {0xABu, 0x0Au}, + {0xACu, 0xFFu}, + {0xB1u, 0x08u}, + {0xB5u, 0x07u}, + {0xB6u, 0xFFu}, + {0xB7u, 0x10u}, + {0xBBu, 0x20u}, + {0xBEu, 0x40u}, + {0xBFu, 0x41u}, {0xD4u, 0x09u}, {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x01u, 0x0Bu}, - {0x03u, 0x02u}, - {0x04u, 0x08u}, - {0x05u, 0x10u}, + {0x00u, 0x44u}, + {0x02u, 0xC1u}, + {0x03u, 0x08u}, + {0x04u, 0xA8u}, {0x07u, 0x40u}, - {0x0Au, 0x40u}, - {0x0Cu, 0x02u}, - {0x0Du, 0x21u}, - {0x0Eu, 0x12u}, - {0x13u, 0x08u}, - {0x15u, 0x04u}, - {0x16u, 0x42u}, - {0x17u, 0x20u}, - {0x19u, 0x02u}, - {0x1Du, 0x01u}, - {0x1Fu, 0x10u}, - {0x21u, 0x02u}, - {0x23u, 0x01u}, - {0x24u, 0x01u}, - {0x25u, 0x34u}, + {0x08u, 0x54u}, + {0x09u, 0x02u}, + {0x0Bu, 0x02u}, + {0x0Cu, 0x40u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x24u}, + {0x10u, 0x22u}, + {0x11u, 0x10u}, + {0x15u, 0x41u}, + {0x17u, 0x28u}, + {0x1Au, 0x01u}, + {0x1Cu, 0x20u}, + {0x1Du, 0x18u}, + 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0x02u}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x40u}, - {0x91u, 0x04u}, - {0x94u, 0x40u}, - {0xA0u, 0x20u}, - {0xA4u, 0x08u}, - {0xA8u, 0x02u}, - {0xB5u, 0x80u}, + {0x02u, 0x02u}, + {0x03u, 0x20u}, + {0x04u, 0x80u}, + {0x07u, 0x80u}, + {0x09u, 0x10u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x20u}, + {0x0Fu, 0x20u}, + {0x80u, 0x40u}, + {0x87u, 0x90u}, + {0x8Bu, 0x20u}, + {0x8Fu, 0x04u}, + {0x93u, 0x40u}, + {0x9Bu, 0x06u}, + {0x9Eu, 0x01u}, + {0xA7u, 0xC0u}, + {0xA8u, 0x80u}, + {0xB7u, 0x40u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE0u, 0x02u}, - {0xE2u, 0x05u}, - {0xEAu, 0x08u}, - {0x85u, 0x04u}, - {0x88u, 0x02u}, - {0x91u, 0x04u}, - {0xA0u, 0x04u}, + {0xE2u, 0x01u}, + {0xE6u, 0x08u}, + {0xE8u, 0x08u}, + {0x82u, 0x02u}, + {0x8Fu, 0x40u}, + {0x96u, 0x40u}, + {0x9Bu, 0x02u}, + {0x9Eu, 0x01u}, {0xA1u, 0x10u}, - {0xA8u, 0x20u}, - {0xADu, 0x20u}, - {0xE6u, 0x01u}, - {0x09u, 0x20u}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x02u}, - {0x0Eu, 0x08u}, - {0x87u, 0x10u}, - {0x8Du, 0x20u}, - {0x8Eu, 0x04u}, - {0xA4u, 0x02u}, + {0xA2u, 0x02u}, + {0xA7u, 0x40u}, + {0xAAu, 0x40u}, + {0xABu, 0x80u}, + {0xACu, 0x20u}, + {0xAFu, 0x40u}, + {0xB7u, 0x10u}, + {0xE4u, 0x02u}, + {0xEAu, 0x08u}, + {0x09u, 0x08u}, + {0x0Au, 0x01u}, + {0x0Eu, 0x40u}, + {0x0Fu, 0x01u}, + {0x82u, 0x01u}, + {0x86u, 0x01u}, + {0x96u, 0x40u}, + {0x9Eu, 0x01u}, {0xA9u, 0x10u}, - {0xACu, 0x04u}, + {0xAFu, 0x02u}, {0xC2u, 0x0Fu}, - {0xE2u, 0x02u}, - {0xE6u, 0x02u}, - {0x83u, 0x40u}, - {0x98u, 0x20u}, - {0xA8u, 0x20u}, - {0xB4u, 0x04u}, + {0x81u, 0x04u}, + {0x86u, 0x08u}, + {0x96u, 0x08u}, + {0x99u, 0x20u}, + {0x9Eu, 0x08u}, + {0xA3u, 0x04u}, + {0xA5u, 0x04u}, + {0xABu, 0x04u}, + {0xAFu, 0x01u}, + {0xB4u, 0x20u}, {0xE2u, 0x20u}, + {0xE6u, 0x40u}, + {0xEAu, 0x40u}, {0xEEu, 0x20u}, - {0x04u, 0x02u}, - {0x57u, 0x40u}, - {0x58u, 0x20u}, - {0x8Cu, 0x01u}, - {0x98u, 0x20u}, - {0xA3u, 0x40u}, + {0x06u, 0x40u}, + {0x57u, 0x04u}, + {0x59u, 0x20u}, + {0x86u, 0x40u}, + {0x99u, 0x20u}, + {0xA3u, 0x04u}, + {0xAEu, 0x04u}, {0xC0u, 0x20u}, {0xD4u, 0xC0u}, - {0x01u, 0x04u}, - {0x89u, 0x04u}, + {0xE0u, 0x10u}, + {0xEEu, 0x10u}, + {0xADu, 0x08u}, + {0xB7u, 0x01u}, + {0xEEu, 0x08u}, + {0x02u, 0x40u}, + {0x8Au, 0x40u}, {0xC0u, 0x08u}, - {0xE2u, 0x04u}, - {0x10u, 0x03u}, - {0x1Au, 0x03u}, + {0xE6u, 0x01u}, + {0x10u, 0x01u}, + {0x11u, 0x01u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x01u}, + {0x1Du, 0x01u}, {0x00u, 0xFDu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, - {0x10u, 0x55u}, + {0x10u, 0x95u}, }; @@ -2019,30 +2183,18 @@ void cyfitter_cfg(void) {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0x01u, 0xC0u, 0x00u, 0x02u, 0x40u, 0xC0u, 0x00u, 0x04u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0x00u, 0x00u, 0xFFu, - 0x08u, 0x90u, 0x21u, 0x40u, 0x22u, 0x1Fu, 0x08u, 0x20u, 0x40u, 0xC0u, 0x00u, 0x08u, 0x10u, 0xC0u, 0x00u, 0x01u, - 0x01u, 0x00u, 0x00u, 0x9Fu, 0x01u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x60u, - 0x40u, 0x00u, 0x00u, 0x00u, 0x3Fu, 0xFFu, 0x08u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x10u, - 0x52u, 0x03u, 0x10u, 0x00u, 0x06u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, - 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 62eb76f..827126f 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -381,34 +381,34 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -416,9 +416,9 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -436,8 +436,6 @@ .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 @@ -1877,15 +1875,6 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1898,37 +1887,37 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -2728,8 +2717,6 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2737,9 +2724,9 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST /* Debug_Timer_Interrupt */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2860,8 +2847,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2869,49 +2856,67 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK -.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK + +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 0c155fc..1faaf51 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -436,8 +436,6 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 @@ -1877,15 +1875,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1898,37 +1887,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2728,8 +2717,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2737,9 +2724,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST /* Debug_Timer_Interrupt */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2860,8 +2847,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2869,49 +2856,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK + +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index ac8e851..88254b2 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -436,8 +436,6 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 @@ -1877,15 +1875,6 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1898,37 +1887,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2728,8 +2717,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2737,9 +2724,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST ; Debug_Timer_Interrupt Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2860,8 +2847,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2869,49 +2856,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK + +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 20a6a85..5778fb5 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -70,6 +70,7 @@ #include #include #include +#include #include #include #include diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index eec5673..3617afb 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,11 +1,42 @@ - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -64,54 +95,24 @@ - - - + - - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + @@ -138,38 +139,27 @@ + - - - + + + - - - + - + + + - - - - - - - - - - - - @@ -266,6 +256,20 @@ + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit 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+ + SCSI_Parity_Error_MASK_REG + No description available + 0x20 + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_STATUS_AUX_CTL_REG + No description available + 0x30 + 8 + read-write + 0 + 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + Debug_Timer No description available @@ -299,9 +454,9 @@ - SCSI_Out_Ctl + SCSI_Glitch_Ctl No description available - 0x40006474 + 0x4000647A 0 0x0 @@ -309,7 +464,7 @@ - SCSI_Out_Ctl_CONTROL_REG + SCSI_Glitch_Ctl_CONTROL_REG No description available 0x0 8 @@ -322,7 +477,7 @@ SCSI_Filtered No description available - 0x40006468 + 0x40006467 0 0x0 @@ -475,164 +630,9 @@ - SCSI_Parity_Error - No description available - 0x40006466 - - 0 - 0x0 - registers - - - - SCSI_Parity_Error_STATUS_REG - No description available - 0x0 - 8 - read-write - 0 - 0 - - - SCSI_Parity_Error_MASK_REG - No description available - 0x20 - 8 - read-write - 0 - 0 - - - SCSI_Parity_Error_STATUS_AUX_CTL_REG - No description available - 0x30 - 8 - read-write - 0 - 0 - - - FIFO0 - FIFO0 clear - 5 - 5 - read-write - - - ENABLED - Enable counter - 1 - - - DISABLED - Disable counter - 0 - - - - - INTRENBL - Enables or disables the Interrupt - 4 - 4 - read-write - - - ENABLED - Interrupt enabled - 1 - - - DISABLED - Interrupt disabled - 0 - - - - - FIFO1LEVEL - FIFO level - 3 - 3 - read-write - - - ENABLED - FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full - 1 - - - DISABLED - FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty - 0 - - - - - FIFO0LEVEL - FIFO level - 2 - 2 - read-write - - - ENABLED - FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full - 1 - - - DISABLED - FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty - 0 - - - - - FIFO1CLEAR - FIFO clear - 1 - 1 - read-write - - - ENABLED - Clear FIFO state - 1 - - - DISABLED - Normal FIFO operation - 0 - - - - - FIFO0CLEAR - FIFO clear - 0 - 0 - read-write - - - ENABLED - Clear FIFO state - 1 - - - DISABLED - Normal FIFO operation - 0 - - - - - - - - - SCSI_Out_Bits + SCSI_Out_Ctl No description available - 0x40006478 + 0x4000647C 0 0x0 @@ -640,7 +640,7 @@ - SCSI_Out_Bits_CONTROL_REG + SCSI_Out_Ctl_CONTROL_REG No description available 0x0 8 @@ -653,7 +653,7 @@ SCSI_CTL_PHASE No description available - 0x40006472 + 0x40006471 0 0x0 @@ -1155,5 +1155,26 @@ + + SCSI_Out_Bits + No description available + 0x4000657B + + 0 + 0x0 + registers + + + + SCSI_Out_Bits_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + \ No newline at end of file diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 977098ef03e24a9abeb8bcfa6195b22cf88ce9bd..0c893bf611359a1b8fb125157b7b1fa3590c75da 100755 GIT binary patch literal 247731 zcmeFa3%p)OS?~Yu(qN@67P(*D?OwE{G-PQVDy7)gxlQTs zP~1%}2f0Z*Hr*L{v=hbi1X%@KrLT$3cxQ2EVP}zmY*T1{XQ@J46+2(=mgvn2g|;eo ziHn<3n#G;%?zu(ZlZu_v^Ym{DeX1h3Kd7(Woy`t`{SI{sA9-}%yd%Ouf28A+Cqj-C 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zp*I@zytoaac*t8b>ur#;jSJ#X7ul$Z_$=AOZjxgF;?S2E^z$ib8iDG~5dd-Mj~VnU zacKHPnxFxQLtk#tZ%);ed1(>^5IP_->dLRwmWPSjML;tZspPYiOtIGI- z01$`%yg{FlhHkPE0K}oU81z^gy2-5q5Qo0epf{$Wo3syrIP@0{`k{C*FrWaYN&5hZ zL;s~ge>^qo=6W;$ap6@hXCu@20$G8K7+nB z1>GEI0T742-=H5&LpQB80CDIC4SGi!x@kcGh(kYW(9fr!o15?fh(mwdptr^)gn#*g YcDv9)aX}pFy9V|9X(+TUgyMq#1%}Z_VgLXD diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v index 850176a..97f07de 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v @@ -107,7 +107,7 @@ localparam STATE_FIFOLOAD = 3'b001; localparam STATE_TX = 3'b010; localparam STATE_DESKEW_INIT = 3'b011; localparam STATE_DESKEW = 3'b100; -// This state intentionally not used. +localparam STATE_WAIT_TIL_READY = 3'b101; localparam STATE_READY = 3'b110; localparam STATE_RX = 3'b111; @@ -166,13 +166,15 @@ wire f1_blk_stat; // Rx FIFO full wire txComplete = f0_blk_stat && (state == STATE_IDLE) && nACK; cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg ( - /* input */ .clock(op_clk), - /* input [04:00] */ .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat}) + .clock(op_clk), + .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat}) ); // DMA outputs -assign tx_intr = f0_bus_stat; -assign rx_intr = f1_bus_stat; +//assign tx_intr = f0_bus_stat; +assign tx_intr = f0_blk_stat; +//assign rx_intr = f1_bus_stat; +assign rx_intr = f1_blk_stat; ///////////////////////////////////////////////////////////////////////////// // State machine @@ -181,18 +183,15 @@ always @(posedge op_clk) begin case (state) STATE_IDLE: begin - // Check that SCSI initiator is ready, and input FIFO is not empty, - // and output FIFO is not full. - // Note that output FIFO is unused in TX mode. if (!nRST) state <= STATE_IDLE; - else if (nACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat)) + else if (!f0_blk_stat) // Input FIFO has some data state <= STATE_FIFOLOAD; else state <= STATE_IDLE; // Clear our output pins data <= 8'b0; - + REQReg <= 1'b0; fifoStore <= 1'b0; parityErrReg <= 1'b0; @@ -202,9 +201,13 @@ always @(posedge op_clk) begin if (!nRST) state <= STATE_IDLE; else if (IO == IO_WRITE) state <= STATE_TX; - else begin + + // Check that SCSI initiator is ready, and output FIFO is not full. + else if (nACK && !f1_blk_stat) begin state <= STATE_READY; REQReg <= 1'b1; + end else begin + state <= STATE_WAIT_TIL_READY; end STATE_TX: @@ -220,11 +223,25 @@ always @(posedge op_clk) begin STATE_DESKEW: if (!nRST) state <= STATE_IDLE; - else if(deskewComplete) begin + else if(deskewComplete && nACK) begin state <= STATE_READY; REQReg <= 1'b1; + end else if (deskewComplete) begin + state <= STATE_WAIT_TIL_READY; end else state <= STATE_DESKEW; + STATE_WAIT_TIL_READY: + if (!nRST) state <= STATE_IDLE; + + // Check that SCSI initiator is ready, and output FIFO is not full. + // Note that output FIFO is unused in TX mode. + else if (nACK && ((IO == IO_WRITE) || !f1_blk_stat)) begin + state <= STATE_READY; + REQReg <= 1'b1; + end else begin + state <= STATE_WAIT_TIL_READY; + end + STATE_READY: if (!nRST) state <= STATE_IDLE; else if (~nACK) begin @@ -255,56 +272,59 @@ end // D0 is used for the deskew count. // The data output is valid during the DESKEW_INIT phase as well, // so we subtract 1. -// D0 = [0.000000055 / (1 / clk)] - 1 +// SCSI-1 deskew + cable skew = 55ns +// D0 = [0.000000055 / (1 / clk)] - 1 = 2 +// SCSI-2 FAST deskew + cable skew = 25ns +// D0 = [0.000000025 / (1 / clk)] - 1 = 0 cy_psoc3_dp #(.d0_init(2), .cy_dpconfig( { `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/ + `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/ + `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/ + `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/ + `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/ `CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/ + `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/ + `CS_CMP_SEL_CFGA, /*CFGRAM5: WAIT TIL READY*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/ + `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/ - 8'hFF, 8'h00, /*CFG9: */ - 8'hFF, 8'hFF, /*CFG11-10: */ + `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/ + 8'hFF, 8'h00, /*CFG9: */ + 8'hFF, 8'hFF, /*CFG11-10: */ `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH, `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI, - `SC_SI_A_DEFSI, /*CFG13-12: */ + `SC_SI_A_DEFSI, /*CFG13-12: */ `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN, 1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS, `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN, `SC_FB_NOCHN, `SC_CMP1_NOCHN, - `SC_CMP0_NOCHN, /*CFG15-14: */ + `SC_CMP0_NOCHN, /*CFG15-14: */ 10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX, `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL, - `SC_WRK16CAT_DSBL /*CFG17-16: */ + `SC_WRK16CAT_DSBL /*CFG17-16: */ } )) datapath( /* input */ .reset(1'b0), @@ -361,3 +381,4 @@ endmodule //`#start footer` -- edit after this line, do not edit this line //`#end` -- edit above this line, do not edit this line + diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c new file mode 100644 index 0000000..8c80437 --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl.c +* Version 1.70 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Glitch_Ctl.h" + +#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_Write(uint8 control) +{ + SCSI_Glitch_Ctl_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_Glitch_Ctl_Read(void) +{ + return SCSI_Glitch_Ctl_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h new file mode 100644 index 0000000..bcd7650 --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl.h +* Version 1.70 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ +#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H + +#include "cytypes.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_Glitch_Ctl_Write(uint8 control) ; +uint8 SCSI_Glitch_Ctl_Read(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_Glitch_Ctl_Control (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_Glitch_Ctl_Control_PTR ( (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h index 3c59e78..9d6e8c9 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -146,8 +146,8 @@ extern uint8 SDCard_initVar; ***************************************/ #define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT)) -#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) -#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \ +#define SDCard_INT_ON_TX_EMPTY ((uint8) (1u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \ SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) #define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT)) #define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT)) diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index afbbeda..f1dba83 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -414,34 +414,34 @@ #define EXTLED__SLW CYREG_PRT0_SLW /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB09_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB09_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB09_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB09_10_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB09_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB09_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB09_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -449,34 +449,32 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB09_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB09_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB09_10_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB09_10_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB09_10_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB09_10_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB09_10_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB09_10_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB09_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB09_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB09_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB09_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB09_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB09_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB09_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB09_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB09_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB09_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -484,9 +482,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB10_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB10_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST /* SD_SCK */ #define SD_SCK__0__MASK 0x04u @@ -1844,15 +1842,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1865,37 +1863,37 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT5_AG @@ -2648,55 +2646,57 @@ #define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW /* scsiTarget */ -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2704,9 +2704,9 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST /* Debug_Timer_Interrupt */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2827,8 +2827,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2836,49 +2836,71 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK -#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB01_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB01_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK +#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK + +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 49abfff..06e85d1 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 40u +#define CY_CFG_BASE_ADDR_COUNT 41u CYPACKED typedef struct { uint8 offset; @@ -189,8 +189,8 @@ static void ClockSetup(void) /* Configure Digital Clocks based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u); @@ -383,1638 +383,1711 @@ void cyfitter_cfg(void) 0x40005210u, /* Base address: 0x40005200 Count: 16 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010041u, /* Base address: 0x40010000 Count: 65 */ - 0x40010141u, /* Base address: 0x40010100 Count: 65 */ - 0x40010259u, /* Base address: 0x40010200 Count: 89 */ - 0x40010351u, /* Base address: 0x40010300 Count: 81 */ - 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */ - 0x4001054Bu, /* Base address: 0x40010500 Count: 75 */ - 0x40010716u, /* Base address: 0x40010700 Count: 22 */ - 0x40010849u, /* Base address: 0x40010800 Count: 73 */ - 0x40010950u, /* Base address: 0x40010900 Count: 80 */ - 0x40010A3Cu, /* Base address: 0x40010A00 Count: 60 */ - 0x40010B5Bu, /* Base address: 0x40010B00 Count: 91 */ - 0x40010C4Bu, /* Base address: 0x40010C00 Count: 75 */ - 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */ - 0x40010E53u, /* Base address: 0x40010E00 Count: 83 */ - 0x40010F3Fu, /* Base address: 0x40010F00 Count: 63 */ - 0x40011505u, /* Base address: 0x40011500 Count: 5 */ - 0x40011711u, /* Base address: 0x40011700 Count: 17 */ - 0x4001181Cu, /* Base address: 0x40011800 Count: 28 */ - 0x40011950u, /* Base address: 0x40011900 Count: 80 */ - 0x40011A50u, /* Base address: 0x40011A00 Count: 80 */ - 0x40011B4Bu, /* Base address: 0x40011B00 Count: 75 */ - 0x40014018u, /* Base address: 0x40014000 Count: 24 */ - 0x40014117u, /* Base address: 0x40014100 Count: 23 */ - 0x40014218u, /* Base address: 0x40014200 Count: 24 */ + 0x40010048u, /* Base address: 0x40010000 Count: 72 */ + 0x40010145u, /* Base address: 0x40010100 Count: 69 */ + 0x40010244u, /* Base address: 0x40010200 Count: 68 */ + 0x40010362u, /* Base address: 0x40010300 Count: 98 */ + 0x4001044Cu, /* Base address: 0x40010400 Count: 76 */ + 0x4001055Eu, /* Base address: 0x40010500 Count: 94 */ + 0x4001064Bu, /* Base address: 0x40010600 Count: 75 */ + 0x40010759u, /* Base address: 0x40010700 Count: 89 */ + 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */ + 0x40010955u, /* Base address: 0x40010900 Count: 85 */ + 0x40010A47u, /* Base address: 0x40010A00 Count: 71 */ + 0x40010B58u, /* Base address: 0x40010B00 Count: 88 */ + 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */ + 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */ + 0x40010F08u, /* Base address: 0x40010F00 Count: 8 */ + 0x40011417u, /* Base address: 0x40011400 Count: 23 */ + 0x4001154Eu, /* Base address: 0x40011500 Count: 78 */ + 0x4001164Du, /* Base address: 0x40011600 Count: 77 */ + 0x4001175Bu, /* Base address: 0x40011700 Count: 91 */ + 0x40011918u, /* Base address: 0x40011900 Count: 24 */ + 0x40011A04u, /* Base address: 0x40011A00 Count: 4 */ + 0x40011B12u, /* Base address: 0x40011B00 Count: 18 */ + 0x40014015u, /* Base address: 0x40014000 Count: 21 */ + 0x4001411Du, /* Base address: 0x40014100 Count: 29 */ + 0x40014213u, /* Base address: 0x40014200 Count: 19 */ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */ - 0x40014410u, /* Base address: 0x40014400 Count: 16 */ - 0x4001451Au, /* Base address: 0x40014500 Count: 26 */ - 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */ - 0x40014715u, /* Base address: 0x40014700 Count: 21 */ - 0x40014805u, /* Base address: 0x40014800 Count: 5 */ - 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */ - 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */ - 0x40014D0Cu, /* Base address: 0x40014D00 Count: 12 */ - 0x40015004u, /* Base address: 0x40015000 Count: 4 */ + 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */ + 0x40014516u, /* Base address: 0x40014500 Count: 22 */ + 0x40014617u, /* Base address: 0x40014600 Count: 23 */ + 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */ + 0x4001480Au, /* Base address: 0x40014800 Count: 10 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C0Du, /* Base address: 0x40014C00 Count: 13 */ + 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */ + 0x40015002u, /* Base address: 0x40015000 Count: 2 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x4Bu}, - {0x00u, 0x04u}, - {0x01u, 0x48u}, + {0x0Au, 0x36u}, + {0x00u, 0x44u}, + {0x01u, 0x01u}, {0x04u, 0x31u}, - {0x10u, 0x88u}, - {0x11u, 0x84u}, - {0x18u, 0x08u}, - {0x19u, 0x04u}, + {0x10u, 0x48u}, + {0x11u, 0x0Cu}, + {0x18u, 0x04u}, + {0x19u, 0x08u}, {0x1Cu, 0x30u}, - {0x20u, 0x10u}, {0x21u, 0x10u}, {0x24u, 0x44u}, - {0x29u, 0x01u}, - {0x30u, 0x20u}, - {0x31u, 0x30u}, + {0x28u, 0x02u}, + {0x29u, 0x02u}, + {0x31u, 0x10u}, {0x78u, 0x20u}, + {0x79u, 0x20u}, {0x7Cu, 0x40u}, - {0x2Bu, 0x02u}, - {0x89u, 0x0Fu}, - {0x01u, 0x02u}, - {0x02u, 0x02u}, - {0x03u, 0x11u}, - {0x05u, 0x80u}, - {0x07u, 0x40u}, - {0x09u, 0x01u}, - {0x0Bu, 0x02u}, - {0x0Du, 0x40u}, - {0x0Fu, 0x80u}, - {0x11u, 0x13u}, - {0x12u, 0x04u}, - {0x13u, 0x2Cu}, - {0x15u, 0x80u}, - {0x17u, 0x40u}, - {0x19u, 0x80u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x40u}, - {0x1Du, 0x80u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x40u}, - {0x21u, 0x04u}, - {0x23u, 0x08u}, - {0x29u, 0x08u}, - {0x2Bu, 0x24u}, - {0x30u, 0x01u}, - {0x31u, 0xC0u}, + {0x20u, 0x02u}, + {0x86u, 0x0Fu}, + {0x00u, 0x01u}, + {0x01u, 0x03u}, + {0x03u, 0x0Cu}, + {0x07u, 0xFFu}, + {0x09u, 0x05u}, + {0x0Bu, 0x0Au}, + {0x0Du, 0xFFu}, + {0x10u, 0x08u}, + {0x11u, 0x60u}, + {0x13u, 0x90u}, + {0x15u, 0x0Fu}, + {0x17u, 0xF0u}, + {0x18u, 0x02u}, + {0x1Du, 0x06u}, + {0x1Fu, 0x09u}, + {0x21u, 0x30u}, + {0x23u, 0xC0u}, + {0x24u, 0x04u}, + {0x25u, 0x50u}, + {0x27u, 0xA0u}, + {0x2Bu, 0xFFu}, + {0x30u, 0x02u}, {0x32u, 0x04u}, - {0x33u, 0x30u}, - {0x34u, 0x08u}, - {0x35u, 0x0Fu}, - {0x36u, 0x02u}, - {0x3Bu, 0x02u}, - {0x3Fu, 0x14u}, - {0x56u, 0x08u}, + {0x34u, 0x01u}, + {0x36u, 0x08u}, + {0x37u, 0xFFu}, + {0x3Eu, 0x55u}, + {0x3Fu, 0x40u}, + {0x40u, 0x52u}, + {0x41u, 0x04u}, + {0x42u, 0x60u}, + {0x45u, 0xE2u}, + {0x46u, 0xCDu}, + {0x47u, 0x0Fu}, + {0x48u, 0x1Fu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Fu, 0x2Cu}, + {0x56u, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x99u}, - {0x5Du, 0x90u}, + {0x5Du, 0x01u}, {0x5Fu, 0x01u}, - {0x83u, 0x04u}, - {0x86u, 0x70u}, - {0x8Au, 0x08u}, - {0x8Cu, 0x99u}, - {0x8Eu, 0x22u}, - {0x8Fu, 0x01u}, - {0x93u, 0x08u}, - {0x98u, 0xAAu}, - {0x9Au, 0x55u}, - {0x9Bu, 0x02u}, - {0x9Eu, 0x07u}, - {0xA2u, 0x80u}, - {0xACu, 0x44u}, - {0xAEu, 0x88u}, - {0xB1u, 0x02u}, - {0xB3u, 0x01u}, - {0xB4u, 0xF0u}, - {0xB5u, 0x08u}, - {0xB6u, 0x0Fu}, - {0xB7u, 0x04u}, - {0xD8u, 0x04u}, + {0x62u, 0xC0u}, + {0x66u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x40u}, + {0x6Eu, 0x08u}, + {0x81u, 0x03u}, + {0x83u, 0x0Cu}, + {0x85u, 0xFFu}, + {0x89u, 0x05u}, + {0x8Bu, 0x0Au}, + {0x8Du, 0x30u}, + {0x8Fu, 0xC0u}, + {0x91u, 0x50u}, + {0x93u, 0xA0u}, + {0x95u, 0x0Fu}, + {0x97u, 0xF0u}, + {0x9Du, 0x09u}, + {0x9Fu, 0x06u}, + {0xA1u, 0x90u}, + {0xA3u, 0x60u}, + {0xABu, 0xFFu}, + {0xADu, 0xFFu}, + {0xB5u, 0xFFu}, + {0xBFu, 0x10u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x91u}, {0xDFu, 0x01u}, - {0x03u, 0x40u}, - {0x04u, 0x04u}, - {0x05u, 0x10u}, - {0x07u, 0x01u}, - {0x0Au, 0x89u}, - {0x0Cu, 0x80u}, - {0x0Eu, 0x02u}, - {0x0Fu, 0x04u}, - {0x15u, 0x02u}, - {0x16u, 0x01u}, - {0x19u, 0x80u}, - {0x1Au, 0xA8u}, - {0x1Cu, 0x04u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x10u}, - {0x20u, 0x08u}, - {0x21u, 0x18u}, - {0x22u, 0x02u}, - {0x23u, 0x40u}, - {0x24u, 0x80u}, - {0x25u, 0x64u}, - {0x26u, 0x20u}, - {0x27u, 0x50u}, + {0x00u, 0x80u}, + {0x01u, 0x40u}, + {0x02u, 0x40u}, + {0x08u, 0x20u}, + {0x09u, 0x02u}, + {0x12u, 0x10u}, + {0x18u, 0x01u}, + {0x19u, 0x09u}, + {0x1Bu, 0x20u}, + {0x21u, 0x80u}, + {0x24u, 0x08u}, {0x28u, 0x04u}, + {0x29u, 0x14u}, + {0x2Au, 0x01u}, {0x2Bu, 0x40u}, - {0x2Du, 0x01u}, - {0x2Eu, 0x02u}, + {0x2Cu, 0x04u}, + {0x2Du, 0x40u}, + {0x2Eu, 0x01u}, {0x30u, 0x02u}, - {0x32u, 0x54u}, - {0x34u, 0x02u}, - {0x36u, 0x20u}, - {0x39u, 0x08u}, - {0x3Au, 0x60u}, - {0x3Bu, 0x41u}, - {0x3Du, 0x80u}, - {0x3Fu, 0x02u}, - {0x58u, 0x80u}, - {0x5Du, 0x01u}, - {0x5Eu, 0x40u}, - {0x5Fu, 0x28u}, - {0x63u, 0x02u}, - {0x66u, 0x40u}, - {0x68u, 0x03u}, - {0x6Du, 0x04u}, - {0x6Fu, 0x2Au}, - {0x81u, 0x28u}, + {0x31u, 0x08u}, + {0x32u, 0x48u}, + {0x33u, 0x40u}, + {0x36u, 0x09u}, + {0x37u, 0x40u}, + {0x39u, 0x51u}, + {0x3Au, 0x08u}, + {0x3Du, 0x11u}, + {0x3Eu, 0x08u}, + {0x3Fu, 0x80u}, + {0x41u, 0x20u}, + {0x42u, 0x40u}, + {0x48u, 0x10u}, + {0x49u, 0x80u}, + {0x4Bu, 0x22u}, + {0x4Cu, 0x08u}, + {0x4Du, 0x20u}, + {0x50u, 0x28u}, + {0x52u, 0x80u}, + {0x53u, 0x80u}, + {0x59u, 0x42u}, + {0x5Au, 0x18u}, + {0x60u, 0x05u}, + {0x61u, 0x01u}, + {0x63u, 0x10u}, + {0x68u, 0x85u}, + {0x69u, 0x08u}, + {0x70u, 0x40u}, + {0x73u, 0x64u}, + {0x81u, 0x06u}, {0x82u, 0x01u}, - {0x87u, 0x0Au}, - {0x88u, 0x01u}, - {0x89u, 0x10u}, - {0x8Au, 0x20u}, - {0x8Bu, 0x10u}, - {0x8Cu, 0xC0u}, - {0x8Eu, 0x02u}, - {0x8Fu, 0x40u}, - {0xC0u, 0xE8u}, - {0xC2u, 0xCBu}, - {0xC4u, 0x90u}, - {0xCAu, 0x05u}, - {0xCCu, 0xAFu}, - {0xCEu, 0x9Fu}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE0u, 0x05u}, - {0xE4u, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x04u}, - {0x02u, 0x04u}, - {0x03u, 0x02u}, - {0x05u, 0x04u}, - {0x06u, 0x01u}, - {0x07u, 0x02u}, - {0x09u, 0x08u}, - {0x0Bu, 0x10u}, - {0x0Du, 0x04u}, - {0x0Fu, 0x02u}, - {0x10u, 0x04u}, - {0x11u, 0x10u}, - {0x12u, 0x08u}, - {0x13u, 0x08u}, - {0x15u, 0x10u}, - {0x17u, 0x08u}, - {0x19u, 0x02u}, - {0x1Au, 0x02u}, - {0x1Bu, 0x04u}, - {0x1Du, 0x10u}, - {0x1Fu, 0x08u}, - {0x20u, 0x08u}, - {0x22u, 0x04u}, - {0x24u, 0x08u}, - {0x25u, 0x04u}, - {0x26u, 0x04u}, - {0x27u, 0x02u}, - {0x28u, 0x08u}, - {0x2Au, 0x04u}, - {0x2Bu, 0x01u}, - {0x2Du, 0x10u}, - {0x2Fu, 0x08u}, - {0x30u, 0x0Cu}, - {0x33u, 0x06u}, - {0x34u, 0x01u}, - {0x35u, 0x18u}, - {0x36u, 0x02u}, - {0x37u, 0x01u}, - {0x3Au, 0x02u}, - {0x3Bu, 0x28u}, - {0x56u, 0x08u}, + {0x83u, 0x20u}, + {0x85u, 0x10u}, + {0x87u, 0x80u}, + {0x88u, 0x07u}, + {0x8Au, 0x01u}, + {0x8Eu, 0x40u}, + {0x8Fu, 0x80u}, + {0xC0u, 0x08u}, + {0xC2u, 0x0Au}, + {0xC4u, 0x04u}, + {0xCAu, 0xB7u}, + {0xCCu, 0xDBu}, + {0xCEu, 0xFFu}, + {0xD0u, 0x05u}, + {0xD2u, 0x0Cu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE2u, 0x42u}, + {0xE6u, 0x09u}, + {0x04u, 0x0Fu}, + {0x06u, 0xF0u}, + {0x0Bu, 0x03u}, + {0x0Cu, 0x06u}, + {0x0Eu, 0x09u}, + {0x10u, 0x05u}, + {0x12u, 0x0Au}, + {0x15u, 0x06u}, + {0x1Bu, 0x01u}, + {0x20u, 0x60u}, + {0x22u, 0x90u}, + {0x24u, 0x30u}, + {0x26u, 0xC0u}, + {0x27u, 0x05u}, + {0x28u, 0x03u}, + {0x2Au, 0x0Cu}, + {0x2Cu, 0x50u}, + {0x2Eu, 0xA0u}, + {0x30u, 0xFFu}, + {0x33u, 0x07u}, + {0x3Eu, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x99u}, - {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x90u}, - {0x82u, 0x60u}, - {0x84u, 0xFFu}, - {0x85u, 0xFFu}, - {0x88u, 0x50u}, - {0x8Au, 0xA0u}, - {0x8Bu, 0xFFu}, - {0x90u, 0xFFu}, - {0x91u, 0xFFu}, - {0x94u, 0x03u}, - {0x95u, 0x0Fu}, - {0x96u, 0x0Cu}, - {0x97u, 0xF0u}, - {0x98u, 0x05u}, - {0x9Au, 0x0Au}, - {0x9Du, 0x33u}, - {0x9Fu, 0xCCu}, - {0xA0u, 0x09u}, - {0xA2u, 0x06u}, - {0xA3u, 0xFFu}, - {0xA5u, 0x96u}, - {0xA6u, 0xFFu}, - {0xA7u, 0x69u}, - {0xA8u, 0x30u}, - {0xA9u, 0x55u}, - {0xAAu, 0xC0u}, - {0xABu, 0xAAu}, - {0xACu, 0x0Fu}, - {0xAEu, 0xF0u}, - {0xAFu, 0xFFu}, - {0xB2u, 0xFFu}, - {0xB3u, 0xFFu}, - {0xBBu, 0x08u}, - {0xBEu, 0x04u}, + {0x83u, 0x04u}, + {0x86u, 0x38u}, + {0x8Au, 0x10u}, + {0x8Cu, 0x2Cu}, + {0x8Du, 0x20u}, + {0x8Eu, 0x40u}, + {0x8Fu, 0x10u}, + {0x90u, 0x04u}, + {0x91u, 0x18u}, + {0x92u, 0x10u}, + {0x93u, 0x20u}, + {0x95u, 0x02u}, + {0x96u, 0x7Cu}, + {0x97u, 0x04u}, + {0x98u, 0x50u}, + {0x9Au, 0x2Cu}, + {0x9Cu, 0x02u}, + {0x9Fu, 0x02u}, + {0xA0u, 0x20u}, + {0xA5u, 0x20u}, + {0xA6u, 0x0Cu}, + {0xA7u, 0x10u}, + {0xA8u, 0x01u}, + {0xA9u, 0x01u}, + {0xACu, 0x80u}, + {0xB0u, 0x80u}, + {0xB1u, 0x30u}, + {0xB2u, 0x01u}, + {0xB3u, 0x01u}, + {0xB4u, 0x02u}, + {0xB5u, 0x06u}, + {0xB6u, 0x7Cu}, + {0xB7u, 0x08u}, + {0xBBu, 0x02u}, + {0xBEu, 0x15u}, + {0xBFu, 0x14u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x10u}, + {0xDCu, 0x91u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x02u, 0x40u}, - {0x03u, 0x04u}, - {0x05u, 0x01u}, - {0x07u, 0x10u}, + {0x00u, 0x28u}, + {0x01u, 0x80u}, + {0x04u, 0x40u}, + {0x05u, 0x04u}, + {0x08u, 0x04u}, {0x09u, 0x20u}, - {0x0Bu, 0xA0u}, - {0x0Eu, 0x48u}, - {0x10u, 0x82u}, - {0x11u, 0x04u}, - {0x12u, 0x04u}, - {0x15u, 0x10u}, - {0x16u, 0x20u}, - {0x17u, 0x02u}, - {0x18u, 0x10u}, - {0x1Eu, 0x46u}, - {0x22u, 0x08u}, - {0x25u, 0x10u}, - {0x27u, 0x2Au}, + {0x0Au, 0x40u}, + {0x0Bu, 0x01u}, + {0x0Fu, 0x80u}, + {0x11u, 0x08u}, + {0x12u, 0x86u}, + {0x14u, 0x01u}, + {0x15u, 0x20u}, + {0x16u, 0x80u}, + {0x17u, 0x08u}, + {0x18u, 0x04u}, + {0x19u, 0x80u}, + {0x1Au, 0x10u}, + {0x1Bu, 0x82u}, + {0x1Cu, 0x80u}, + {0x1Eu, 0x80u}, + {0x20u, 0x02u}, + {0x21u, 0x01u}, + {0x22u, 0x25u}, + {0x27u, 0x10u}, {0x28u, 0x08u}, - {0x29u, 0x08u}, - {0x2Au, 0x82u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x04u}, - {0x2Fu, 0x09u}, - {0x32u, 0x8Au}, - {0x35u, 0x40u}, - {0x36u, 0x05u}, - {0x37u, 0x20u}, - {0x38u, 0x20u}, - {0x3Bu, 0x04u}, - {0x3Du, 0xA8u}, - {0x3Fu, 0x02u}, - {0x5Bu, 0x40u}, - {0x5Du, 0x80u}, - {0x62u, 0x80u}, - {0x64u, 0x03u}, - {0x80u, 0x10u}, - {0x81u, 0x18u}, - {0x82u, 0x01u}, - {0x83u, 0x50u}, + {0x2Bu, 0x10u}, + {0x2Du, 0x08u}, + {0x31u, 0x0Cu}, + {0x32u, 0x41u}, + {0x36u, 0x08u}, + {0x37u, 0x10u}, + {0x39u, 0x40u}, + {0x3Au, 0x01u}, + {0x3Du, 0x20u}, + {0x41u, 0x10u}, + {0x43u, 0x20u}, + {0x5Au, 0x20u}, + {0x5Bu, 0x86u}, + {0x60u, 0x20u}, + {0x61u, 0x02u}, + {0x62u, 0x50u}, + {0x6Cu, 0x18u}, + {0x6Du, 0x08u}, + {0x6Eu, 0x08u}, + {0x6Fu, 0x01u}, + {0x7Du, 0x01u}, + {0x7Eu, 0x40u}, + {0x81u, 0x40u}, + {0x82u, 0x04u}, + {0x84u, 0x20u}, + {0x87u, 0x0Au}, {0x88u, 0x01u}, - {0x8Eu, 0x10u}, - {0x90u, 0x04u}, - {0x91u, 0x24u}, - {0x93u, 0x20u}, - {0x95u, 0x02u}, - {0x96u, 0x40u}, - {0x97u, 0x04u}, - {0x98u, 0x10u}, - {0x9Au, 0x02u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x06u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x01u}, - {0x9Fu, 0x29u}, - {0xA0u, 0x86u}, - {0xA1u, 0x45u}, - {0xA2u, 0x02u}, - {0xA3u, 0x01u}, - {0xA9u, 0x81u}, - {0xABu, 0x01u}, - {0xADu, 0x04u}, - {0xAEu, 0x01u}, - {0xB0u, 0x10u}, - {0xB2u, 0x02u}, - {0xB3u, 0x20u}, - {0xC0u, 0x3Eu}, - {0xC2u, 0x5Eu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0x7Fu}, - {0xCCu, 0xFBu}, - {0xCEu, 0xF6u}, - {0xD6u, 0x18u}, - {0xD8u, 0x18u}, + {0x8Bu, 0x12u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x44u}, + {0x8Fu, 0x04u}, + {0x90u, 0x88u}, + {0x91u, 0x18u}, + {0x93u, 0x46u}, + {0x94u, 0x04u}, + {0x95u, 0x01u}, + {0x96u, 0x58u}, + {0x97u, 0x10u}, + {0x99u, 0x20u}, + {0x9Au, 0x28u}, + {0x9Bu, 0xA0u}, + {0x9Cu, 0x20u}, + {0x9Du, 0x90u}, + {0x9Eu, 0x51u}, + {0x9Fu, 0x01u}, + {0xA0u, 0xB0u}, + {0xA1u, 0x80u}, + {0xA2u, 0x80u}, + {0xA4u, 0x40u}, + {0xA5u, 0x2Au}, + {0xA8u, 0x02u}, + {0xAAu, 0x08u}, + {0xACu, 0x10u}, + {0xADu, 0x48u}, + {0xAEu, 0x20u}, + {0xAFu, 0x11u}, + {0xB4u, 0x20u}, + {0xC0u, 0xA7u}, + {0xC2u, 0x1Fu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x46u}, + {0xCCu, 0x6Bu}, + {0xCEu, 0x29u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, {0xE0u, 0x01u}, - {0xE2u, 0x24u}, - {0xE6u, 0x05u}, - {0xE8u, 0x04u}, - {0xEAu, 0x09u}, - {0xEEu, 0x01u}, - {0x00u, 0x03u}, - {0x02u, 0x0Cu}, - {0x04u, 0x0Fu}, - {0x05u, 0x03u}, - {0x07u, 0x0Cu}, - {0x08u, 0x80u}, - {0x0Bu, 0xFFu}, - {0x0Cu, 0x80u}, - {0x0Du, 0xFFu}, - {0x10u, 0x10u}, - {0x11u, 0x0Fu}, - {0x12u, 0x2Fu}, - {0x13u, 0xF0u}, - {0x14u, 0x20u}, - {0x15u, 0x50u}, - {0x16u, 0x4Fu}, - {0x17u, 0xA0u}, - {0x19u, 0x05u}, + {0xE2u, 0x68u}, + {0xE4u, 0x09u}, + {0xE6u, 0x06u}, + {0xE8u, 0x09u}, + {0xEAu, 0x04u}, + {0xEEu, 0x13u}, + {0x00u, 0x44u}, + {0x02u, 0x88u}, + {0x09u, 0x03u}, + {0x0Du, 0x13u}, + {0x0Fu, 0x44u}, + {0x10u, 0x99u}, + {0x11u, 0x6Cu}, + {0x12u, 0x22u}, + {0x13u, 0x13u}, + {0x17u, 0x7Fu}, + {0x19u, 0x08u}, {0x1Au, 0x70u}, - {0x1Bu, 0x0Au}, - {0x1Cu, 0x80u}, - {0x1Du, 0x06u}, - {0x1Fu, 0x09u}, - {0x20u, 0x05u}, - {0x22u, 0x0Au}, - {0x24u, 0x80u}, - {0x25u, 0x30u}, - {0x27u, 0xC0u}, - {0x28u, 0x06u}, - {0x2Au, 0x09u}, - {0x2Bu, 0xFFu}, - {0x2Cu, 0x40u}, - {0x2Du, 0x60u}, - {0x2Eu, 0x1Fu}, - {0x2Fu, 0x90u}, - {0x31u, 0xFFu}, - {0x32u, 0x80u}, - {0x34u, 0x7Fu}, - {0x38u, 0x08u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x01u}, - {0x54u, 0x01u}, + {0x1Eu, 0x07u}, + {0x1Fu, 0x02u}, + {0x21u, 0x71u}, + {0x24u, 0xAAu}, + {0x26u, 0x55u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x20u}, + {0x2Du, 0x0Cu}, + {0x2Eu, 0x80u}, + {0x2Fu, 0x30u}, + {0x34u, 0xF0u}, + {0x35u, 0x7Fu}, + {0x36u, 0x0Fu}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, - {0x5Du, 0x10u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x82u, 0x08u}, - {0x85u, 0xFFu}, - {0x89u, 0x55u}, - {0x8Bu, 0xAAu}, - {0x8Eu, 0x01u}, - {0x8Fu, 0xFFu}, - {0x91u, 0xFFu}, - {0x95u, 0x33u}, - {0x97u, 0xCCu}, - {0x9Du, 0x0Fu}, - {0x9Fu, 0xF0u}, - {0xA3u, 0xFFu}, - {0xA5u, 0x69u}, - {0xA6u, 0x04u}, - {0xA7u, 0x96u}, - {0xAEu, 0x02u}, - {0xAFu, 0xFFu}, - {0xB0u, 0x04u}, - {0xB1u, 0xFFu}, - {0xB2u, 0x08u}, - {0xB4u, 0x01u}, - {0xB6u, 0x02u}, - {0xBBu, 0x02u}, - {0xD6u, 0x08u}, + {0x81u, 0x6Cu}, + {0x85u, 0x64u}, + {0x87u, 0x08u}, + {0x88u, 0xFFu}, + {0x8Cu, 0x06u}, + {0x8Eu, 0x09u}, + {0x91u, 0x6Cu}, + {0x92u, 0xFFu}, + {0x94u, 0x0Fu}, + {0x95u, 0x71u}, + {0x96u, 0xF0u}, + {0x97u, 0x82u}, + {0x99u, 0xC0u}, + {0x9Au, 0xFFu}, + {0x9Bu, 0x2Fu}, + {0x9Cu, 0x50u}, + {0x9Du, 0xA4u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x40u}, + {0xA0u, 0x03u}, + {0xA1u, 0x08u}, + {0xA2u, 0x0Cu}, + {0xA3u, 0x10u}, + {0xA4u, 0x60u}, + {0xA5u, 0x91u}, + {0xA6u, 0x90u}, + {0xA7u, 0x4Eu}, + {0xA8u, 0x05u}, + {0xA9u, 0x40u}, + {0xAAu, 0x0Au}, + {0xABu, 0x2Cu}, + {0xACu, 0x30u}, + {0xADu, 0x2Cu}, + {0xAEu, 0xC0u}, + {0xAFu, 0x40u}, + {0xB1u, 0xC0u}, + {0xB3u, 0x31u}, + {0xB4u, 0xFFu}, + {0xB5u, 0x0Fu}, + {0xBBu, 0x0Eu}, + {0xBEu, 0x10u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x19u}, - {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x10u}, - {0x01u, 0x84u}, - {0x02u, 0x10u}, - {0x03u, 0x40u}, - {0x05u, 0x41u}, - {0x09u, 0x0Au}, - {0x0Au, 0x0Au}, - {0x10u, 0x10u}, - {0x11u, 0x02u}, - {0x12u, 0x09u}, - {0x14u, 0x02u}, - {0x16u, 0x20u}, - {0x1Au, 0x28u}, - {0x1Du, 0x41u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x08u}, - {0x22u, 0x01u}, - {0x27u, 0x40u}, - {0x2Au, 0x54u}, + {0x03u, 0x80u}, + {0x06u, 0x08u}, + {0x07u, 0x02u}, + {0x08u, 0x01u}, + {0x0Au, 0x4Au}, + {0x0Du, 0x18u}, + {0x0Eu, 0x82u}, + {0x12u, 0x20u}, + {0x13u, 0x60u}, + {0x15u, 0x15u}, + {0x16u, 0x01u}, + {0x1Au, 0x0Au}, + {0x1Bu, 0x60u}, + {0x1Du, 0x10u}, + {0x21u, 0x20u}, + {0x22u, 0x20u}, + {0x25u, 0x10u}, + {0x26u, 0x08u}, + {0x27u, 0x58u}, + {0x28u, 0xC1u}, + {0x2Au, 0x20u}, + {0x2Cu, 0x02u}, {0x2Du, 0x08u}, - {0x2Eu, 0x82u}, - {0x30u, 0x82u}, - {0x31u, 0x20u}, - {0x33u, 0x04u}, - {0x36u, 0x02u}, - {0x37u, 0x48u}, - {0x38u, 0x04u}, + {0x2Fu, 0x48u}, + {0x30u, 0x24u}, + {0x31u, 0x01u}, + {0x32u, 0x80u}, + {0x37u, 0x59u}, + {0x38u, 0x20u}, {0x39u, 0xA0u}, - {0x3Bu, 0x80u}, - {0x3Fu, 0xA4u}, - {0x58u, 0x40u}, - {0x5Eu, 0x10u}, - {0x5Fu, 0x40u}, - {0x64u, 0x02u}, - {0x66u, 0x20u}, + {0x3Du, 0x02u}, + {0x3Eu, 0x04u}, + {0x41u, 0x40u}, + {0x43u, 0x80u}, + {0x58u, 0x10u}, + {0x59u, 0x84u}, + {0x5Au, 0x01u}, + {0x60u, 0x08u}, + {0x62u, 0x06u}, + {0x63u, 0x01u}, + {0x65u, 0x40u}, {0x67u, 0x02u}, - {0x81u, 0x10u}, - {0x83u, 0x04u}, - {0x85u, 0x08u}, - {0x87u, 0x04u}, - {0x8Eu, 0x04u}, - {0x90u, 0x14u}, - {0x91u, 0x24u}, - {0x92u, 0x10u}, - {0x95u, 0x02u}, - {0x97u, 0x86u}, - {0x98u, 0x10u}, - {0x9Au, 0x03u}, + {0x81u, 0x25u}, + {0x83u, 0x20u}, + {0x84u, 0x10u}, + {0x86u, 0x02u}, + {0x89u, 0x01u}, + {0x8Fu, 0x41u}, + {0x90u, 0xA8u}, + {0x91u, 0x5Au}, + {0x92u, 0x01u}, + {0x93u, 0x46u}, + {0x94u, 0x40u}, + {0x95u, 0x01u}, + {0x96u, 0x60u}, + {0x97u, 0x01u}, + {0x99u, 0x20u}, + {0x9Au, 0x28u}, + {0x9Bu, 0x20u}, {0x9Cu, 0x0Cu}, - {0x9Du, 0x51u}, - {0x9Eu, 0xE4u}, - {0x9Fu, 0x05u}, - {0xA0u, 0x82u}, - {0xA1u, 0x01u}, - {0xA2u, 0x0Au}, - {0xA3u, 0x50u}, - {0xA5u, 0x20u}, - {0xA6u, 0x04u}, - {0xA7u, 0x08u}, - {0xABu, 0x40u}, - {0xADu, 0x04u}, + {0x9Du, 0x08u}, + {0x9Eu, 0x85u}, + {0xA0u, 0xE0u}, + {0xA1u, 0x84u}, + {0xA2u, 0xC0u}, + {0xA3u, 0x80u}, + {0xA4u, 0x04u}, + {0xA5u, 0x38u}, + {0xA6u, 0x0Au}, + {0xA7u, 0x70u}, + {0xAAu, 0x20u}, + {0xABu, 0x10u}, + {0xAEu, 0x50u}, + {0xB0u, 0x01u}, + {0xB1u, 0x02u}, + {0xB2u, 0x01u}, + {0xB4u, 0x08u}, {0xB5u, 0x80u}, - {0xC0u, 0x9Fu}, - {0xC2u, 0x0Fu}, - {0xC4u, 0xAFu}, - {0xCAu, 0xDEu}, - {0xCCu, 0xDFu}, - {0xCEu, 0x7Eu}, - {0xD6u, 0x38u}, - {0xD8u, 0x30u}, - {0xE2u, 0x03u}, - {0xE6u, 0x0Du}, - {0xEAu, 0x09u}, - {0xECu, 0x40u}, - {0xEEu, 0x01u}, - {0x81u, 0x08u}, - {0x88u, 0x04u}, - {0x90u, 0x04u}, - {0x91u, 0x20u}, - {0x95u, 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{0xE0u, 0x10u}, + {0xE2u, 0x8Cu}, + {0xE4u, 0x40u}, + {0xE6u, 0x22u}, + {0xE8u, 0x40u}, + {0xEAu, 0x38u}, + {0xECu, 0x40u}, + {0xEEu, 0xA0u}, + {0x03u, 0x08u}, + {0x05u, 0x01u}, + {0x07u, 0x02u}, + {0x08u, 0x04u}, + {0x0Au, 0x09u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x01u}, + {0x14u, 0x08u}, + {0x16u, 0x04u}, + {0x1Du, 0x02u}, + {0x1Fu, 0x05u}, + {0x20u, 0x08u}, + {0x22u, 0x06u}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x02u}, + {0x31u, 0x04u}, + {0x33u, 0x08u}, + {0x34u, 0x0Cu}, + {0x35u, 0x03u}, + {0x36u, 0x03u}, + {0x3Au, 0x20u}, {0x3Bu, 0x20u}, - {0x3Eu, 0x41u}, - {0x3Fu, 0x01u}, + {0x3Eu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Cu, 0x99u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x0Du}, - {0x8Cu, 0x32u}, - {0x8Eu, 0x44u}, - {0x90u, 0x40u}, - {0x92u, 0x30u}, - {0x94u, 0x02u}, - {0x96u, 0x0Du}, - {0x98u, 0x11u}, - {0x9Au, 0x62u}, - {0x9Bu, 0x01u}, - {0x9Cu, 0x0Du}, - {0x9Du, 0x05u}, - {0x9Fu, 0x0Au}, - {0xA0u, 0x0Du}, - {0xA3u, 0x08u}, - {0xA4u, 0x0Du}, - {0xA7u, 0x04u}, - {0xA8u, 0x52u}, - {0xAAu, 0x28u}, - {0xABu, 0x02u}, - {0xACu, 0x0Du}, - {0xB0u, 0x70u}, - {0xB1u, 0x0Cu}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x03u}, - {0xBAu, 0x0Au}, - {0xBFu, 0x05u}, - {0xD6u, 0x08u}, + {0x82u, 0x01u}, + {0x84u, 0x34u}, + {0x88u, 0x34u}, + {0x89u, 0x04u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x02u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0x04u}, + {0x90u, 0x08u}, + {0x91u, 0x08u}, + {0x92u, 0x20u}, + {0x93u, 0x10u}, + {0x94u, 0x08u}, + {0x96u, 0x34u}, + {0x98u, 0x08u}, + {0x9Au, 0x10u}, + {0x9Cu, 0x34u}, + {0xA0u, 0x34u}, + {0xA3u, 0x10u}, + {0xA4u, 0x04u}, + {0xA6u, 0x08u}, + {0xAAu, 0x02u}, + {0xABu, 0x08u}, + {0xACu, 0x34u}, + {0xADu, 0x04u}, + {0xAFu, 0x03u}, + {0xB2u, 0x3Cu}, + {0xB3u, 0x18u}, + {0xB5u, 0x01u}, + {0xB6u, 0x03u}, + {0xB7u, 0x06u}, + {0xBAu, 0x08u}, + {0xBBu, 0x80u}, + {0xBEu, 0x40u}, + {0xBFu, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDDu, 0x90u}, + {0xDCu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x48u}, - {0x04u, 0x24u}, - {0x06u, 0x21u}, - {0x09u, 0x40u}, - {0x0Au, 0xA8u}, - {0x0Eu, 0x18u}, - {0x10u, 0x10u}, - {0x11u, 0x41u}, - {0x12u, 0x08u}, - {0x15u, 0x04u}, - {0x16u, 0x04u}, - {0x17u, 0x41u}, - {0x1Au, 0xA0u}, - {0x1Bu, 0x01u}, - {0x1Du, 0x30u}, - {0x1Eu, 0x18u}, - {0x1Fu, 0x51u}, - {0x21u, 0x04u}, - {0x22u, 0x02u}, - {0x24u, 0x08u}, - {0x26u, 0x01u}, - {0x27u, 0x18u}, - {0x29u, 0x22u}, - {0x2Bu, 0x20u}, - {0x2Eu, 0xA0u}, - {0x2Fu, 0x10u}, + {0x01u, 0x20u}, + {0x05u, 0x09u}, + {0x06u, 0x08u}, + {0x07u, 0x01u}, + {0x09u, 0x08u}, + {0x0Eu, 0x19u}, + {0x0Fu, 0x80u}, + {0x10u, 0x02u}, + {0x13u, 0x01u}, + {0x14u, 0x01u}, + {0x15u, 0x01u}, + {0x17u, 0x24u}, + {0x19u, 0x60u}, + {0x1Au, 0x02u}, + {0x1Bu, 0x20u}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x10u}, + {0x20u, 0x44u}, + {0x21u, 0x08u}, + {0x23u, 0x08u}, + {0x24u, 0x20u}, + {0x25u, 0x50u}, + {0x2Cu, 0x80u}, + {0x2Fu, 0x05u}, {0x32u, 0x80u}, - {0x33u, 0x10u}, - {0x37u, 0x59u}, - {0x3Cu, 0x20u}, - {0x3Du, 0x04u}, - {0x3Eu, 0x04u}, - {0x58u, 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{0x3Au, 0x20u}, - {0x3Eu, 0x44u}, - {0x3Fu, 0x10u}, + {0x1Cu, 0x55u}, + {0x1Du, 0x20u}, + {0x1Eu, 0xAAu}, + {0x1Fu, 0x07u}, + {0x20u, 0x33u}, + {0x22u, 0xCCu}, + {0x23u, 0x04u}, + {0x26u, 0xFFu}, + {0x29u, 0x6Cu}, + {0x2Au, 0xFFu}, + {0x2Bu, 0x93u}, + {0x2Du, 0x4Fu}, + {0x2Eu, 0xFFu}, + {0x2Fu, 0xB0u}, + {0x32u, 0xFFu}, + {0x35u, 0xE0u}, + {0x37u, 0x1Fu}, + {0x3Au, 0x08u}, + {0x3Bu, 0xA0u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x09u}, + {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x59u}, - {0x82u, 0xA2u}, - {0x85u, 0x55u}, - {0x86u, 0x20u}, - {0x87u, 0xAAu}, - {0x8Au, 0x30u}, - {0x8Bu, 0xFFu}, - {0x8Du, 0x69u}, - {0x8Fu, 0x96u}, - {0x90u, 0x30u}, - {0x91u, 0xFFu}, - {0x92u, 0xC0u}, - {0x95u, 0x0Fu}, - {0x96u, 0x07u}, - {0x97u, 0xF0u}, - {0x98u, 0x74u}, - {0x9Au, 0x88u}, - {0x9Bu, 0xFFu}, - {0x9Eu, 0x08u}, - {0x9Fu, 0xFFu}, - {0xA0u, 0x6Au}, - {0xA2u, 0x95u}, - {0xA5u, 0xFFu}, - {0xACu, 0x10u}, - {0xADu, 0x33u}, - {0xAFu, 0xCCu}, - {0xB0u, 0xF0u}, + {0x81u, 0x0Fu}, + {0x83u, 0xF0u}, + {0x86u, 0x07u}, + {0x87u, 0xFFu}, + {0x88u, 0x04u}, + {0x89u, 0xFFu}, + {0x8Au, 0x08u}, + {0x8Du, 0x33u}, + {0x8Fu, 0xCCu}, + {0x90u, 0x10u}, + {0x92u, 0x20u}, + {0x96u, 0x10u}, + {0x97u, 0xFFu}, + {0x99u, 0x69u}, + {0x9Bu, 0x96u}, + {0x9Du, 0xFFu}, + {0xA2u, 0x20u}, + {0xA3u, 0xFFu}, + {0xA4u, 0x0Au}, + {0xA6u, 0x05u}, + {0xA9u, 0x55u}, + {0xAAu, 0x08u}, + {0xABu, 0xAAu}, + {0xACu, 0x09u}, + {0xAEu, 0x02u}, {0xB2u, 0x0Fu}, - {0xB5u, 0xFFu}, - {0xBAu, 0x02u}, - {0xBBu, 0x20u}, + {0xB4u, 0x30u}, + {0xB7u, 0xFFu}, + {0xBBu, 0x80u}, + {0xBEu, 0x10u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x11u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x01u}, - {0x03u, 0x18u}, - {0x05u, 0x28u}, - {0x07u, 0x40u}, - {0x08u, 0x40u}, - {0x09u, 0x02u}, - {0x0Au, 0x18u}, - {0x0Bu, 0x10u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x89u}, - {0x10u, 0xA0u}, - {0x12u, 0x01u}, - {0x14u, 0x08u}, - {0x16u, 0x06u}, - {0x17u, 0x01u}, - {0x18u, 0x04u}, - {0x19u, 0x20u}, - {0x1Au, 0x28u}, - {0x1Bu, 0x70u}, + {0x01u, 0x08u}, + {0x02u, 0x08u}, + {0x05u, 0x40u}, + {0x06u, 0x20u}, + {0x08u, 0x02u}, + {0x0Au, 0x20u}, + {0x0Du, 0x48u}, + {0x0Fu, 0x08u}, + {0x11u, 0x18u}, + {0x12u, 0x41u}, + {0x16u, 0x01u}, + {0x17u, 0x19u}, + {0x18u, 0x10u}, + {0x19u, 0x08u}, + {0x1Au, 0x08u}, {0x1Du, 0x08u}, - {0x1Eu, 0x80u}, - {0x20u, 0x08u}, + {0x1Fu, 0x08u}, + {0x20u, 0x01u}, + {0x22u, 0x40u}, {0x26u, 0x20u}, - {0x27u, 0x08u}, - {0x28u, 0x40u}, - {0x2Au, 0x08u}, - {0x2Bu, 0x08u}, - {0x2Eu, 0x84u}, - {0x30u, 0x2Au}, - {0x35u, 0x10u}, - {0x37u, 0x49u}, - {0x38u, 0x80u}, - {0x3Au, 0x12u}, - {0x3Bu, 0x04u}, - {0x3Du, 0x03u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x28u}, - {0x45u, 0x10u}, - {0x47u, 0x20u}, - {0x5Bu, 0x80u}, - {0x5Cu, 0x08u}, - {0x5Du, 0x01u}, - {0x5Fu, 0x60u}, - {0x62u, 0x40u}, + {0x27u, 0x02u}, + {0x2Au, 0x11u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x20u}, + {0x2Fu, 0x02u}, + {0x30u, 0x20u}, + {0x31u, 0x40u}, + {0x32u, 0x08u}, + {0x35u, 0x40u}, + {0x36u, 0x24u}, + {0x37u, 0x02u}, + {0x38u, 0x05u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x80u}, + {0x3Cu, 0x04u}, + {0x3Eu, 0x02u}, + {0x3Fu, 0x80u}, + {0x5Bu, 0x40u}, + {0x5Eu, 0x10u}, + {0x5Fu, 0x40u}, + {0x62u, 0x80u}, + {0x64u, 0x08u}, {0x67u, 0x02u}, - {0x82u, 0x19u}, - {0x88u, 0x40u}, - {0x8Au, 0x90u}, - {0x8Bu, 0x18u}, - {0x8Cu, 0x81u}, - {0x8Fu, 0x20u}, - {0xC0u, 0x7Eu}, - {0xC2u, 0xFFu}, - {0xC4u, 0x9Du}, - {0xCAu, 0x57u}, - {0xCCu, 0xF7u}, - {0xCEu, 0x7Fu}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE0u, 0xA1u}, - {0xE2u, 0x50u}, - {0xE4u, 0x34u}, - {0xE6u, 0xC0u}, - {0xA9u, 0x80u}, - {0xE4u, 0x80u}, - {0xE6u, 0x02u}, - {0xEAu, 0x04u}, - {0xEEu, 0x20u}, + {0x80u, 0x08u}, + {0x81u, 0x40u}, + {0x83u, 0x40u}, + {0x84u, 0x40u}, + {0x86u, 0x40u}, + {0x8Bu, 0x22u}, + {0x8Eu, 0x03u}, + {0x8Fu, 0x40u}, + {0x91u, 0x11u}, + {0x92u, 0x10u}, + {0x94u, 0x18u}, + {0x96u, 0x40u}, + {0x98u, 0x10u}, + {0xA2u, 0x04u}, + {0xA6u, 0x31u}, + {0xAAu, 0x51u}, + {0xADu, 0x01u}, + {0xAEu, 0x20u}, + {0xC0u, 0xA6u}, + {0xC2u, 0xECu}, + {0xC4u, 0xFFu}, + {0xCAu, 0xB5u}, + {0xCCu, 0xFEu}, + {0xCEu, 0xDFu}, + {0xD6u, 0x38u}, + {0xD8u, 0x38u}, + {0xE0u, 0x40u}, + {0xE2u, 0x20u}, + {0xE4u, 0x40u}, + {0xE6u, 0x32u}, {0x80u, 0x04u}, - {0x84u, 0x08u}, - {0x88u, 0x02u}, + {0x86u, 0x10u}, + {0x88u, 0x10u}, {0x89u, 0x10u}, - {0x90u, 0x04u}, - {0x91u, 0x20u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x80u}, - {0xA0u, 0x02u}, - {0xA8u, 0x80u}, - {0xA9u, 0x40u}, - {0xE0u, 0x04u}, - {0xE2u, 0x08u}, - {0xE6u, 0x08u}, - {0xE8u, 0x04u}, - {0xEAu, 0x01u}, - {0xEEu, 0x08u}, - {0x05u, 0x05u}, - {0x07u, 0x0Au}, - {0x09u, 0x50u}, - {0x0Bu, 0xA0u}, - {0x0Du, 0x06u}, - {0x0Fu, 0x09u}, - {0x13u, 0xFFu}, - {0x14u, 0x01u}, - {0x15u, 0x03u}, - {0x17u, 0x0Cu}, - {0x1Bu, 0xFFu}, - {0x1Du, 0xFFu}, - {0x25u, 0x30u}, - {0x27u, 0xC0u}, - {0x29u, 0x0Fu}, - {0x2Bu, 0xF0u}, - {0x2Du, 0x60u}, - {0x2Fu, 0x90u}, - {0x33u, 0xFFu}, - {0x34u, 0x01u}, - {0x3Fu, 0x04u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x09u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x00u, 0x64u}, - {0x01u, 0x02u}, - {0x09u, 0x40u}, - {0x0Au, 0x21u}, - {0x0Bu, 0x84u}, - {0x0Fu, 0x20u}, - {0x10u, 0x18u}, - {0x11u, 0x45u}, - {0x18u, 0x10u}, - {0x19u, 0x20u}, - {0x1Au, 0x02u}, - {0x1Bu, 0x80u}, - {0x1Eu, 0x04u}, - {0x21u, 0x80u}, - {0x22u, 0x20u}, - {0x23u, 0x20u}, - {0x27u, 0x10u}, - {0x2Cu, 0x26u}, - {0x32u, 0x28u}, - {0x36u, 0x11u}, - {0x37u, 0x88u}, - {0x38u, 0x44u}, - {0x39u, 0x20u}, - {0x3Du, 0x28u}, - {0x3Fu, 0x80u}, - {0x40u, 0x04u}, - {0x42u, 0x20u}, - {0x43u, 0x80u}, - {0x48u, 0x40u}, - {0x49u, 0x06u}, - {0x4Au, 0x8Au}, - {0x51u, 0x20u}, - {0x52u, 0x44u}, - {0x53u, 0x40u}, - {0x5Fu, 0x40u}, - {0x63u, 0x02u}, - {0x65u, 0x40u}, - {0x68u, 0x0Cu}, - {0x69u, 0x55u}, - {0x72u, 0x01u}, - {0x83u, 0x08u}, - {0x85u, 0x44u}, - {0x88u, 0x04u}, - {0x8Bu, 0x82u}, - {0x90u, 0x06u}, - {0x91u, 0x28u}, - {0x92u, 0x20u}, - {0x94u, 0x50u}, - {0x95u, 0x41u}, - {0x96u, 0x04u}, - {0x9Au, 0x90u}, - {0x9Bu, 0x41u}, - {0x9Cu, 0x14u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x44u}, - {0xA0u, 0x22u}, - {0xA1u, 0x10u}, - {0xA2u, 0x15u}, - {0xA3u, 0x59u}, - {0xA4u, 0x04u}, - {0xA5u, 0x6Cu}, - {0xA6u, 0x88u}, - {0xA7u, 0x20u}, - {0xA8u, 0x40u}, - {0xABu, 0x40u}, - {0xB0u, 0x01u}, - {0xB1u, 0x08u}, - {0xB3u, 0x10u}, - {0xC0u, 0x0Fu}, - {0xC2u, 0x2Fu}, - {0xC4u, 0x0Fu}, - {0xCAu, 0x70u}, - {0xCCu, 0xF6u}, - {0xCEu, 0x7Eu}, - {0xD0u, 0x0Eu}, - {0xD2u, 0x0Cu}, - {0xD6u, 0x10u}, - {0xD8u, 0x18u}, - {0xE4u, 0xA0u}, - {0xEEu, 0x08u}, - {0x00u, 0xC0u}, - {0x01u, 0x77u}, - {0x02u, 0x02u}, - {0x03u, 0x80u}, - {0x04u, 0x1Fu}, - {0x05u, 0x24u}, - {0x06u, 0x20u}, - {0x07u, 0x40u}, - {0x08u, 0x7Fu}, - {0x0Au, 0x80u}, - {0x0Bu, 0x64u}, - {0x0Du, 0x64u}, - {0x0Eu, 0x9Fu}, - {0x11u, 0x93u}, - {0x12u, 0xFFu}, - {0x13u, 0x60u}, - {0x14u, 0x80u}, - {0x15u, 0x10u}, - {0x17u, 0xE5u}, - {0x19u, 0x24u}, - {0x1Au, 0x60u}, - {0x1Cu, 0xC0u}, - {0x1Du, 0x64u}, - {0x1Eu, 0x01u}, - {0x21u, 0x08u}, - {0x24u, 0xC0u}, - {0x25u, 0x40u}, - {0x26u, 0x04u}, - {0x27u, 0x02u}, - {0x28u, 0xC0u}, - {0x29u, 0x08u}, - {0x2Au, 0x08u}, - {0x2Cu, 0x90u}, - {0x2Du, 0x64u}, - {0x2Eu, 0x40u}, - {0x30u, 0xFFu}, - {0x31u, 0xF0u}, - {0x33u, 0x07u}, - {0x35u, 0x08u}, - {0x37u, 0x80u}, - {0x39u, 0x22u}, - {0x3Bu, 0x0Cu}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x40u}, - {0x54u, 0x09u}, - {0x56u, 0x04u}, + {0x8Cu, 0x10u}, + {0x8Eu, 0x04u}, + {0xE0u, 0xE0u}, + {0xE2u, 0x12u}, + {0x80u, 0x01u}, + {0x84u, 0x08u}, + {0x86u, 0x21u}, + {0x8Cu, 0x01u}, + {0x90u, 0x01u}, + {0x94u, 0x10u}, + {0x98u, 0x01u}, + {0x99u, 0x01u}, + {0x9Cu, 0x04u}, + {0xA0u, 0x01u}, + {0xA4u, 0x07u}, + {0xA5u, 0x01u}, + {0xA6u, 0x18u}, + {0xA8u, 0x22u}, + {0xAAu, 0x08u}, + {0xB1u, 0x01u}, + {0xB4u, 0x3Fu}, + {0xB8u, 0x20u}, + {0xB9u, 0x02u}, + {0xBEu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x01u, 0x04u}, + {0x02u, 0x08u}, + {0x03u, 0x41u}, + {0x05u, 0x08u}, + {0x07u, 0x41u}, + {0x09u, 0x91u}, + {0x0Au, 0x10u}, + {0x0Cu, 0x0Au}, + {0x0Eu, 0x06u}, + {0x10u, 0x82u}, + {0x13u, 0x08u}, + {0x15u, 0x01u}, + {0x17u, 0x18u}, + {0x19u, 0x08u}, + {0x1Au, 0x11u}, + {0x1Bu, 0x10u}, + {0x1Fu, 0x20u}, + {0x20u, 0x04u}, + {0x21u, 0x18u}, + {0x26u, 0x03u}, + {0x29u, 0x02u}, + {0x2Fu, 0x20u}, + {0x31u, 0x08u}, + {0x32u, 0x20u}, + {0x33u, 0x80u}, + {0x37u, 0x20u}, + {0x38u, 0x80u}, + {0x39u, 0x28u}, + {0x42u, 0x91u}, + {0x43u, 0x10u}, + {0x48u, 0x80u}, + {0x49u, 0x04u}, + {0x4Au, 0x04u}, + {0x4Bu, 0x01u}, + {0x50u, 0x08u}, + {0x51u, 0x80u}, + {0x52u, 0x14u}, + {0x53u, 0x44u}, + {0x62u, 0x11u}, + {0x63u, 0x21u}, + {0x81u, 0x08u}, + {0x82u, 0x80u}, + {0x88u, 0x10u}, + {0x89u, 0x80u}, + {0x8Cu, 0x04u}, + {0x8Du, 0x08u}, + {0x90u, 0x80u}, + {0x91u, 0x0Du}, + {0x92u, 0x04u}, + {0x96u, 0x01u}, + {0x97u, 0x88u}, + {0x99u, 0x02u}, + {0x9Bu, 0x79u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x0Cu}, + {0x9Eu, 0x05u}, + {0xA0u, 0x02u}, + {0xA1u, 0x11u}, + {0xA2u, 0x2Cu}, + {0xA3u, 0x80u}, + {0xA6u, 0x02u}, + {0xAAu, 0x11u}, + {0xACu, 0x42u}, + {0xB1u, 0x01u}, + {0xB2u, 0x04u}, + {0xB7u, 0x28u}, + {0xC0u, 0xBFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x7Du}, + {0xCAu, 0x41u}, + {0xCCu, 0x2Eu}, + {0xCEu, 0x0Eu}, + {0xD0u, 0x0Fu}, + {0xD2u, 0x04u}, + {0xD8u, 0x0Fu}, + {0xE4u, 0x04u}, + {0xE8u, 0x0Au}, + {0xEEu, 0x04u}, + {0x01u, 0xC0u}, + {0x03u, 0x02u}, + {0x04u, 0x07u}, + {0x05u, 0xC0u}, + {0x06u, 0x08u}, + {0x07u, 0x04u}, + {0x09u, 0xC0u}, + {0x0Bu, 0x08u}, + {0x0Du, 0xC0u}, + {0x0Fu, 0x01u}, + {0x10u, 0x08u}, + {0x12u, 0x06u}, + {0x13u, 0x60u}, + {0x15u, 0x1Fu}, + {0x17u, 0x20u}, + {0x19u, 0x7Fu}, + {0x1Bu, 0x80u}, + {0x1Du, 0x80u}, + {0x24u, 0x03u}, + {0x26u, 0x0Cu}, + {0x27u, 0xFFu}, + {0x28u, 0x0Bu}, + {0x2Au, 0x04u}, + {0x2Bu, 0x9Fu}, + {0x2Du, 0x90u}, + {0x2Fu, 0x40u}, + {0x30u, 0x0Eu}, + {0x33u, 0xFFu}, + {0x34u, 0x0Eu}, + {0x36u, 0x01u}, + {0x3Au, 0x22u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x04u}, + {0x56u, 0x02u}, + {0x57u, 0x28u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, - {0x82u, 0x80u}, - {0x8Au, 0x70u}, - {0x8Bu, 0x20u}, - {0x8Cu, 0xAAu}, - {0x8Eu, 0x55u}, - {0x91u, 0x0Au}, - {0x93u, 0x05u}, - {0x95u, 0x04u}, - {0x96u, 0x07u}, - {0x97u, 0x08u}, - {0x98u, 0x44u}, - {0x9Au, 0x88u}, - {0x9Bu, 0x17u}, - {0x9Du, 0x09u}, - {0x9Fu, 0x02u}, - {0xA6u, 0x08u}, - {0xABu, 0x08u}, - {0xACu, 0x99u}, - {0xADu, 0x10u}, - {0xAEu, 0x22u}, - {0xAFu, 0x20u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x0Fu}, - {0xB4u, 0xF0u}, - {0xB5u, 0x30u}, - {0xBFu, 0x10u}, + {0x80u, 0x19u}, + {0x82u, 0x22u}, + {0x87u, 0x10u}, + {0x89u, 0x20u}, + {0x8Bu, 0x40u}, + {0x8Fu, 0x2Eu}, + {0x90u, 0x04u}, + {0x91u, 0x09u}, + {0x92u, 0x48u}, + {0x93u, 0x10u}, + {0x94u, 0x10u}, + {0x97u, 0x01u}, + {0x99u, 0x15u}, + {0x9Au, 0x07u}, + {0x9Bu, 0x0Au}, + {0x9Fu, 0x01u}, + {0xA1u, 0x13u}, + {0xA2u, 0x08u}, + {0xA3u, 0x04u}, + {0xA4u, 0x0Au}, + {0xA6u, 0x55u}, + {0xA8u, 0x20u}, + {0xAAu, 0x50u}, + {0xAFu, 0x40u}, + {0xB0u, 0x70u}, + {0xB1u, 0x1Eu}, + {0xB4u, 0x0Fu}, + {0xB5u, 0x60u}, + {0xB7u, 0x01u}, + {0xBAu, 0x02u}, + {0xBFu, 0x50u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x00u, 0xA4u}, - {0x01u, 0x01u}, - {0x02u, 0x40u}, - {0x05u, 0x10u}, - {0x06u, 0x80u}, - {0x07u, 0x01u}, - {0x08u, 0x40u}, - {0x09u, 0x02u}, - {0x0Au, 0x21u}, - {0x0Bu, 0x04u}, - {0x0Eu, 0x28u}, - {0x10u, 0x08u}, - {0x11u, 0x44u}, - {0x16u, 0x10u}, - {0x17u, 0x40u}, + {0x01u, 0x02u}, + {0x05u, 0x08u}, + {0x08u, 0x03u}, + {0x09u, 0x04u}, + {0x0Au, 0x08u}, + {0x0Eu, 0x80u}, + {0x10u, 0x84u}, + {0x12u, 0x20u}, + {0x17u, 0x18u}, {0x19u, 0x02u}, - {0x1Du, 0x18u}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x20u}, - {0x20u, 0x60u}, - {0x21u, 0x02u}, - {0x22u, 0x4Au}, - {0x23u, 0x04u}, - {0x25u, 0x04u}, - {0x27u, 0x18u}, - {0x28u, 0x10u}, - {0x29u, 0x22u}, - {0x2Au, 0x44u}, - {0x2Fu, 0x0Au}, - {0x30u, 0x40u}, - {0x31u, 0x02u}, - {0x32u, 0x18u}, - {0x36u, 0x04u}, - {0x37u, 0x51u}, - {0x38u, 0x02u}, - {0x39u, 0x54u}, - {0x3Du, 0x20u}, + {0x1Au, 0x48u}, + {0x1Du, 0x80u}, + {0x1Eu, 0x80u}, + {0x1Fu, 0x10u}, + {0x20u, 0x48u}, + {0x22u, 0x80u}, + {0x27u, 0x20u}, + {0x29u, 0x02u}, + {0x2Au, 0xC0u}, + {0x2Cu, 0x02u}, + {0x2Du, 0x08u}, + {0x2Fu, 0x04u}, + {0x30u, 0x41u}, + {0x32u, 0x20u}, + {0x33u, 0x04u}, + {0x36u, 0x06u}, + {0x37u, 0x58u}, + {0x38u, 0x40u}, + {0x3Bu, 0x14u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x22u}, + {0x3Eu, 0x04u}, + {0x40u, 0x02u}, + {0x43u, 0x80u}, {0x58u, 0x10u}, {0x59u, 0x04u}, - {0x5Au, 0x82u}, + {0x5Au, 0x81u}, {0x61u, 0x80u}, {0x63u, 0x40u}, + {0x67u, 0x20u}, + {0x6Cu, 0x02u}, + {0x6Du, 0x27u}, + {0x6Eu, 0x04u}, + {0x6Fu, 0x28u}, + {0x74u, 0x40u}, + {0x77u, 0x01u}, + {0x86u, 0x40u}, {0x87u, 0x40u}, - {0x8Au, 0x20u}, - {0x8Fu, 0x08u}, - {0x90u, 0x06u}, - {0x91u, 0x55u}, - {0x92u, 0x23u}, + {0x88u, 0x04u}, + {0x8Fu, 0x40u}, + {0x90u, 0x80u}, + {0x91u, 0x08u}, + {0x92u, 0x80u}, + {0x93u, 0x14u}, {0x94u, 0x40u}, - {0x97u, 0x04u}, - {0x99u, 0x24u}, - {0x9Au, 0x94u}, - {0x9Bu, 0x41u}, - {0x9Eu, 0x20u}, - {0xA0u, 0x48u}, - {0xA1u, 0x90u}, - {0xA2u, 0x04u}, - {0xA3u, 0x0Au}, - {0xA4u, 0x10u}, - {0xA5u, 0x0Cu}, - {0xA6u, 0x0Au}, - {0xA7u, 0x20u}, - {0xABu, 0x10u}, - {0xAFu, 0x40u}, - {0xB3u, 0x20u}, - {0xC0u, 0xDFu}, - {0xC2u, 0x6Fu}, - {0xC4u, 0xA7u}, - {0xCAu, 0x3Fu}, + {0x96u, 0x64u}, + {0x97u, 0x80u}, + {0x98u, 0x44u}, + {0x9Bu, 0x5Cu}, + {0x9Du, 0x08u}, + {0x9Eu, 0x84u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x80u}, + {0xA1u, 0x04u}, + {0xA2u, 0x28u}, + {0xA3u, 0xC0u}, + {0xA4u, 0x02u}, + {0xA5u, 0x01u}, + {0xA6u, 0x80u}, + {0xA7u, 0x08u}, + {0xA8u, 0x20u}, + {0xA9u, 0x04u}, + {0xABu, 0x04u}, + {0xADu, 0x01u}, + {0xB0u, 0x01u}, + {0xB2u, 0x01u}, + {0xB3u, 0x08u}, + {0xB5u, 0x04u}, + {0xB6u, 0x01u}, + {0xC0u, 0x28u}, + {0xC2u, 0x1Eu}, + {0xC4u, 0x6Eu}, + {0xCAu, 0x79u}, {0xCCu, 0xFFu}, - {0xCEu, 0x2Fu}, + {0xCEu, 0xFEu}, {0xD6u, 0x0Fu}, - {0xD8u, 0x09u}, - {0xE4u, 0x80u}, - {0xEEu, 0x22u}, - {0x05u, 0x20u}, - {0x0Du, 0x20u}, + {0xD8u, 0x49u}, + {0xE2u, 0x08u}, + {0xE6u, 0x01u}, + {0xEAu, 0x08u}, + {0xEEu, 0x21u}, + {0x80u, 0x04u}, + {0x84u, 0x10u}, + {0x91u, 0x20u}, + {0x94u, 0x80u}, + {0x95u, 0x01u}, + {0x96u, 0x01u}, + {0x97u, 0x08u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x48u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x08u}, + {0xA0u, 0x10u}, + {0xA6u, 0x04u}, + {0xA8u, 0x48u}, + {0xAAu, 0x40u}, + {0xAFu, 0x08u}, + {0xB0u, 0x02u}, + {0xB2u, 0x20u}, + {0xB5u, 0x01u}, + {0xE0u, 0x20u}, + {0xE4u, 0x40u}, + {0xE8u, 0x80u}, + {0xECu, 0x40u}, + {0xEEu, 0x20u}, + {0x38u, 0x20u}, + {0x3Eu, 0x10u}, + {0x58u, 0x04u}, + {0x5Fu, 0x01u}, + {0x18u, 0x08u}, + {0x82u, 0x04u}, + {0x8Cu, 0x40u}, + {0x8Fu, 0x08u}, + {0x94u, 0x88u}, + {0x9Fu, 0x08u}, + {0xA6u, 0x04u}, + {0xACu, 0x01u}, + {0xADu, 0x01u}, + {0xB1u, 0x50u}, + {0xB2u, 0x01u}, + {0xB3u, 0x04u}, + {0xB5u, 0x08u}, + {0xB6u, 0x08u}, + {0xE4u, 0x50u}, + {0xE8u, 0xD0u}, + {0xECu, 0x80u}, + {0xEEu, 0x04u}, + {0x07u, 0x04u}, + {0x0Eu, 0x02u}, {0x12u, 0x08u}, {0x16u, 0x80u}, - {0x17u, 0x80u}, - {0x31u, 0x02u}, - {0x35u, 0x08u}, + {0x17u, 0x20u}, + {0x30u, 0x02u}, + {0x35u, 0x02u}, {0x36u, 0x80u}, - {0x38u, 0x08u}, {0x3Au, 0x80u}, - {0x3Du, 0x28u}, - {0x40u, 0x02u}, - {0x67u, 0x80u}, - {0x84u, 0x80u}, - {0x87u, 0x40u}, + {0x3Bu, 0x01u}, + {0x3Cu, 0x44u}, + {0x42u, 0x08u}, + {0x62u, 0x02u}, + {0x8Cu, 0x40u}, {0xC0u, 0x80u}, {0xC2u, 0x80u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD8u, 0x80u}, - {0xE2u, 0x10u}, - {0xE6u, 0x40u}, - {0x30u, 0x08u}, + {0xD8u, 0x40u}, + {0x32u, 0x01u}, {0x33u, 0x10u}, - {0x37u, 0x84u}, + {0x34u, 0x04u}, + {0x37u, 0x20u}, {0x39u, 0x40u}, - {0x51u, 0x01u}, - {0x56u, 0x08u}, - {0x60u, 0x80u}, - {0x89u, 0x01u}, - {0x94u, 0x08u}, - {0x98u, 0x80u}, - {0x99u, 0x20u}, - {0x9Bu, 0x90u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x08u}, - {0xA1u, 0x20u}, - {0xA5u, 0x16u}, + {0x53u, 0x10u}, + {0x57u, 0x80u}, + {0x5Cu, 0x01u}, + {0x82u, 0x01u}, + {0x8Bu, 0x10u}, + {0x8Fu, 0x80u}, + {0x94u, 0x04u}, + {0x9Bu, 0x30u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x08u}, + {0xA2u, 0x01u}, + {0xA4u, 0x02u}, {0xA6u, 0x80u}, {0xAAu, 0x08u}, - {0xABu, 0x10u}, + {0xABu, 0x14u}, + {0xAEu, 0x02u}, + {0xB7u, 0x01u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, - {0xD4u, 0xC0u}, - {0xD8u, 0x40u}, + {0xD4u, 0x60u}, + {0xD6u, 0x80u}, + {0xE4u, 0x80u}, + {0xE8u, 0x80u}, + {0xEAu, 0x40u}, {0x12u, 0x80u}, - {0x33u, 0x80u}, - {0x5Au, 0x01u}, - {0x80u, 0x04u}, - {0x85u, 0x08u}, - {0x92u, 0x01u}, - {0x94u, 0x08u}, - {0x95u, 0x40u}, - {0x99u, 0x20u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x08u}, - {0x9Fu, 0x04u}, - {0xA4u, 0x08u}, - {0xA5u, 0x06u}, + {0x30u, 0x20u}, + {0x84u, 0x02u}, + {0x94u, 0x04u}, + {0x96u, 0x02u}, + {0x9Cu, 0x04u}, + {0x9Eu, 0x08u}, + {0xA3u, 0x40u}, + {0xA4u, 0x02u}, {0xA6u, 0x80u}, - {0xA9u, 0x10u}, - {0xAEu, 0x09u}, - {0xB5u, 0x20u}, + {0xA9u, 0x40u}, + {0xABu, 0x40u}, + {0xB1u, 0x02u}, + {0xB4u, 0x01u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0xD6u, 0x40u}, - {0xE6u, 0x90u}, - {0xEAu, 0x90u}, - {0xEEu, 0x40u}, - {0x83u, 0x04u}, - {0x89u, 0x02u}, - {0x8Du, 0x04u}, - {0x9Cu, 0x02u}, - {0x9Fu, 0x04u}, - {0xA5u, 0x06u}, - {0xA7u, 0x80u}, - {0xB0u, 0x08u}, - {0xB1u, 0x20u}, - {0xB5u, 0x40u}, - {0xE2u, 0x80u}, - {0x00u, 0x80u}, - {0x05u, 0x20u}, - {0x09u, 0x20u}, - {0x0Eu, 0x01u}, - {0x13u, 0x02u}, - {0x14u, 0x40u}, - {0x62u, 0x02u}, - {0x65u, 0x02u}, - {0x81u, 0x02u}, - {0x82u, 0x02u}, - {0x8Du, 0x20u}, + {0xE2u, 0x10u}, + {0xEAu, 0x20u}, + {0xEEu, 0x20u}, + {0x84u, 0x04u}, + {0x86u, 0x01u}, + {0x8Du, 0x02u}, + {0x94u, 0x04u}, + {0x96u, 0x02u}, + {0x9Cu, 0x04u}, + {0x9Eu, 0x08u}, + {0xA3u, 0x40u}, + {0xA4u, 0x20u}, + {0xE2u, 0x10u}, + {0xE6u, 0x40u}, + {0x01u, 0x20u}, + {0x06u, 0x01u}, + {0x0Bu, 0x04u}, + {0x0Du, 0x80u}, + {0x13u, 0x08u}, + {0x14u, 0x80u}, + {0x58u, 0x02u}, + {0x62u, 0x08u}, + {0x87u, 0x04u}, {0xC0u, 0x03u}, {0xC2u, 0x03u}, {0xC4u, 0x0Cu}, - {0xD8u, 0x03u}, - {0xE2u, 0x08u}, - {0x00u, 0x01u}, - {0x07u, 0x40u}, - {0x08u, 0x01u}, - {0x0Eu, 0x80u}, - {0x51u, 0x02u}, - {0x56u, 0x20u}, - {0x58u, 0x04u}, - {0x65u, 0x01u}, - {0x84u, 0x10u}, - {0x85u, 0x02u}, - {0x88u, 0x44u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x20u}, - {0x92u, 0x01u}, - {0x98u, 0x40u}, - {0x9Bu, 0x02u}, - {0xA1u, 0x20u}, - {0xACu, 0x40u}, + {0xD6u, 0x02u}, + {0xD8u, 0x02u}, + {0x00u, 0x08u}, + {0x05u, 0x02u}, + {0x09u, 0x08u}, + {0x0Cu, 0x02u}, + {0x57u, 0x01u}, + {0x59u, 0x40u}, + {0x5Au, 0x04u}, + {0x5Fu, 0x02u}, + {0x84u, 0x80u}, + {0x8Du, 0x08u}, + {0x98u, 0x80u}, + {0x99u, 0x20u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x02u}, + {0xA1u, 0x80u}, + {0xA6u, 0x08u}, {0xC0u, 0x0Cu}, {0xC2u, 0x0Cu}, - {0xD4u, 0x03u}, - {0xD6u, 0x02u}, - {0xD8u, 0x01u}, - {0xE2u, 0x01u}, - {0xE4u, 0x01u}, - {0xE6u, 0x0Au}, - {0x57u, 0x80u}, - {0x89u, 0x40u}, - {0x8Eu, 0x20u}, - {0x92u, 0x01u}, - {0x9Bu, 0x02u}, - {0x9Eu, 0x20u}, - {0xA2u, 0x40u}, - {0xA4u, 0x10u}, - {0xA9u, 0x01u}, - {0xABu, 0x40u}, - {0xACu, 0x01u}, - {0xD4u, 0x02u}, - {0xE2u, 0x01u}, - {0xE4u, 0x02u}, - {0x08u, 0x01u}, - {0x0Bu, 0x02u}, - {0x0Cu, 0x08u}, - {0x0Fu, 0x02u}, - {0x80u, 0x08u}, - {0x87u, 0x02u}, - {0x90u, 0x08u}, - {0x92u, 0x01u}, + {0xD4u, 0x01u}, + {0xD6u, 0x07u}, + {0xE6u, 0x08u}, + {0x80u, 0x10u}, + {0x85u, 0x80u}, + {0x87u, 0x01u}, + {0x8Au, 0x04u}, + {0x8Du, 0x20u}, + {0x96u, 0x04u}, {0x97u, 0x02u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x40u}, - {0xA2u, 0x40u}, - {0xA4u, 0x10u}, + {0x99u, 0x22u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x08u}, + {0x9Fu, 0x02u}, + {0xA1u, 0x80u}, + {0xA7u, 0x01u}, + {0xA8u, 0x02u}, + {0xAAu, 0x08u}, + {0xABu, 0x01u}, + {0xB0u, 0x06u}, + {0xB1u, 0x40u}, + {0xE2u, 0x08u}, + {0xE4u, 0x04u}, + {0xE8u, 0x01u}, + {0xEAu, 0x04u}, + {0xEEu, 0x01u}, + {0x0Bu, 0x22u}, + {0x0Cu, 0x02u}, + {0x0Eu, 0x04u}, + {0x82u, 0x01u}, + {0x84u, 0x02u}, + {0x87u, 0x10u}, + {0x94u, 0x10u}, + {0x97u, 0x02u}, + {0x9Au, 0x01u}, + {0x9Fu, 0x02u}, + {0xAFu, 0x08u}, + {0xB1u, 0x02u}, + {0xC2u, 0x0Fu}, + {0xEAu, 0x01u}, + {0x64u, 0x80u}, + {0x80u, 0x80u}, + {0x86u, 0x08u}, + {0x94u, 0x04u}, + {0x9Eu, 0x08u}, + {0xA1u, 0x02u}, + {0xA3u, 0x40u}, + {0xB0u, 0x20u}, + {0xD8u, 0x80u}, + {0xE6u, 0xC0u}, + {0x07u, 0x80u}, + {0x51u, 0x02u}, + {0x57u, 0x40u}, + {0x83u, 0x80u}, + {0xA1u, 0x02u}, + {0xA3u, 0x40u}, {0xA8u, 0x04u}, - {0xABu, 0x80u}, + {0xC0u, 0x20u}, + {0xD4u, 0xC0u}, + {0xE0u, 0x80u}, + {0xEAu, 0x20u}, + {0x74u, 0x01u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x02u}, + {0x94u, 0x10u}, + {0x9Fu, 0x02u}, + {0xA0u, 0x01u}, {0xB0u, 0x01u}, - {0xB7u, 0x01u}, - {0xC2u, 0x0Fu}, - {0xEAu, 0x02u}, + {0xB2u, 0x04u}, + {0xDEu, 0x04u}, + {0xE0u, 0x04u}, + {0xE4u, 0x02u}, + {0xE8u, 0x01u}, {0xEEu, 0x04u}, - {0x84u, 0x02u}, - {0x9Cu, 0x02u}, - {0xAFu, 0x80u}, - {0xE2u, 0x10u}, - {0xEEu, 0x10u}, - {0x06u, 0x20u}, - {0x50u, 0x02u}, - {0x56u, 0x80u}, - {0x84u, 0x02u}, - {0x8Au, 0x20u}, - {0x9Au, 0x80u}, - {0x9Cu, 0x02u}, + {0x00u, 0x10u}, + {0x06u, 0x02u}, + {0x52u, 0x10u}, + {0x54u, 0x02u}, + {0x94u, 0x10u}, + {0x9Au, 0x10u}, + {0x9Eu, 0x02u}, {0xA0u, 0x02u}, - {0xB2u, 0x80u}, - {0xC0u, 0x20u}, - {0xD4u, 0xC0u}, - {0xE6u, 0x40u}, - {0x90u, 0x08u}, - {0x9Du, 0x40u}, - {0xA2u, 0x40u}, - {0xA4u, 0x10u}, - {0xAFu, 0x01u}, - {0xB2u, 0x01u}, - {0xEEu, 0x01u}, - {0x00u, 0x20u}, - {0x05u, 0x40u}, - {0x50u, 0x04u}, - {0x5Au, 0x40u}, - {0x8Eu, 0x40u}, - {0x90u, 0x08u}, - {0x9Du, 0x40u}, - {0xA4u, 0x10u}, - {0xAEu, 0x40u}, + {0xAAu, 0x02u}, + {0xB2u, 0x10u}, {0xC0u, 0x03u}, - {0xD4u, 0x05u}, - {0xE4u, 0x02u}, + {0xD4u, 0x04u}, + {0xD6u, 0x04u}, + {0xECu, 0x04u}, {0x10u, 0x03u}, - {0x11u, 0x01u}, - {0x1Cu, 0x03u}, - {0x1Du, 0x01u}, + {0x1Au, 0x03u}, {0x00u, 0xFDu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, - {0x10u, 0x55u}, + {0x10u, 0x95u}, }; @@ -2036,31 +2109,30 @@ void cyfitter_cfg(void) {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 1152u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P4_ROUTE_BASE), 768u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_0_1_0_CONFIG Address: CYDEV_UCFG_B1_P4_U1_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_0_1_0_CONFIG_VAL[] = { - 0x10u, 0x00u, 0x00u, 0x00u, 0x07u, 0x13u, 0x18u, 0x20u, 0x22u, 0x00u, 0x08u, 0x0Eu, 0x08u, 0x11u, 0x21u, 0x44u, - 0x00u, 0x00u, 0x80u, 0x00u, 0x01u, 0x29u, 0x00u, 0x10u, 0x04u, 0x6Eu, 0x00u, 0x00u, 0xC1u, 0x00u, 0x00u, 0x00u, - 0xC1u, 0x00u, 0x00u, 0x00u, 0xC1u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0xC0u, 0x00u, - 0x00u, 0x00u, 0x80u, 0x0Eu, 0x3Fu, 0x70u, 0x40u, 0x01u, 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x54u, 0x44u, - 0x56u, 0x02u, 0x10u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { + 0x02u, 0x00u, 0x00u, 0x00u, 0x32u, 0x00u, 0x04u, 0x08u, 0x01u, 0x00u, 0x0Eu, 0x07u, 0x36u, 0x00u, 0x00u, 0x80u, + 0x36u, 0x00u, 0x00u, 0x00u, 0x09u, 0x00u, 0x06u, 0x70u, 0x30u, 0xAAu, 0x06u, 0x55u, 0x04u, 0x44u, 0x00u, 0x88u, + 0x00u, 0x99u, 0x10u, 0x22u, 0x07u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x06u, 0x00u, 0x30u, 0x00u, + 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x10u, 0x0Fu, 0x20u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x00u, + 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xDEu, 0xFCu, 0x0Bu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x04u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B1_P4_U1_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index ced25f2..0462c6f 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -414,34 +414,34 @@ .set EXTLED__SLW, CYREG_PRT0_SLW /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB09_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB09_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB09_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB09_10_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB09_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB09_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB09_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -449,34 +449,32 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB09_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB09_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB09_10_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB09_10_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB09_10_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB09_10_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB09_10_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB09_10_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB09_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB09_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB09_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB09_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB09_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB09_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB09_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB09_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB09_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB09_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -484,9 +482,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB10_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB10_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST /* SD_SCK */ .set SD_SCK__0__MASK, 0x04 @@ -1844,15 +1842,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1865,37 +1863,37 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG @@ -2648,55 +2646,57 @@ .set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW /* scsiTarget */ -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB00_01_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB00_01_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB00_01_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB00_01_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB00_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB00_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB00_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB00_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB00_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB00_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB00_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB00_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB00_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB00_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB00_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB00_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB00_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB00_MSK .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2704,9 +2704,9 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST /* Debug_Timer_Interrupt */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2827,8 +2827,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2836,49 +2836,71 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK -.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB01_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB01_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK +.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK + +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 999ed3b..d8e24dc 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -414,34 +414,34 @@ EXTLED__SHIFT EQU 0 EXTLED__SLW EQU CYREG_PRT0_SLW /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -449,34 +449,32 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -484,9 +482,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST /* SD_SCK */ SD_SCK__0__MASK EQU 0x04 @@ -1844,15 +1842,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1865,37 +1863,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG @@ -2648,55 +2646,57 @@ SCSI_Noise__SEL__SHIFT EQU 3 SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW /* scsiTarget */ -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2704,9 +2704,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST /* Debug_Timer_Interrupt */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2827,8 +2827,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2836,49 +2836,71 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK + +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index bd7edfe..d08ae27 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -414,34 +414,34 @@ EXTLED__SHIFT EQU 0 EXTLED__SLW EQU CYREG_PRT0_SLW ; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -449,34 +449,32 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -484,9 +482,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST ; SD_SCK SD_SCK__0__MASK EQU 0x04 @@ -1844,15 +1842,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1865,37 +1863,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG @@ -2648,55 +2646,57 @@ SCSI_Noise__SEL__SHIFT EQU 3 SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW ; scsiTarget -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2704,9 +2704,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST ; Debug_Timer_Interrupt Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2827,8 +2827,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2836,49 +2836,71 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK + +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 5cd6dff..927ba95 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -68,6 +68,7 @@ #include #include #include +#include #include #include #include diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx index 143801f..abc4319 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,77 +1,12 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + @@ -98,18 +33,10 @@ - - - - - - - - - - - - + + + + @@ -136,24 +63,45 @@ + + + + + + + + + + + + + + + + + + + + + - + - + - + - + - + @@ -251,14 +199,70 @@ - + + + + + + + + + + + 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z=B`fnE%U_?cb=@*`wTtZdZ{$4>j%Wi@zBrp*{5jiZ{O3|wQJ5|XXd^HBsFq>*;Mx# zQgfcXAK3_h!kF?#s~SVPnc~JNmAc|8<4e5Bi~HSiWRKmidCh+I$V#;`Lny6vBh3X& zQ66oJyRI!4n!Ky4TML5-LqOkpC^a$e(;?FKkC`dM?Qp@#b^1tZ5x0GgY2($4$3jd) zr8rvL|wJk{XWihJd)P zn%MT$oOmosJ@zX!2NBtBimEo#Rfa&r9B0GK=WtzD`I9uagc`=G8q#HKWWJPsPvFwJ z5oiDmZ)iHqipx?oB7~*~HZ2L5VvicsTzfxjLUIz%&X16m6a&x6dhWh)%yZfF!C{^D zaouy5${x6+Ag@Pk&QfgD#~d5)rhZT(L+^0z6@3wbqLMzXvAvHlk1X(i1=fVVg(W_E zLVP3w^K>Y|E*@!qcehAk`}B#1n1sbpHG4nu8?RmKe@E2Gg757-HlvN37v>wr&v&hzhj=~c@Uix9`BIPt+ejpM$opF3qL=ngwGPwYG*NV<_VuXd5zv*zH^Tt zX2L^Lnc3hvC}Wl(9ygp2Y(YixP6V3x&CWos_r0a5NG^CE`*95Zib$Csd@q%yE*0(` zWJ!@}v#E9e{;Z-R5PG0tkTrrWNYJW&0~>O3xP6rvp!WbLW_=hydA)QxS`@4>VRMu5 z{%di&FVn6`iPiGQxH2Sdtm^oQ_=)UHc4N8zJuluN;k+~yGOBZ%)^j>; zcTyrctgW>#gFb#3dPY%|UohV9rNEfaD(0uOwHX&g75J~s(P55}QM^E*elZyU9$g0A z6ku|gow+@ig6ofp0l;S`0NBGZMEd_|=Vao1UENOkdj((({-_1ED8M8js9WH;0!$ie zUfcuz+?nW40won;k~>yPAVv`;LGjK2fK&bteO)G2oABfvi&1&)K6~8-p5%@ zhI9NbYeOvn*b#k+?g9R`p5#Bd&(VfIA~~1VEDZphhJP6=9M0Yjhjp>V*;(1!8sc2Q zQ6-qrf297x=>}5R01BXC;zxFry;(KJtmlUUxvhvllpSv1NMV5eV_guB=2Upl1%{zv zlJYwhu7+LbhQk1$RR{q1erW>$ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd index 69839ec..eaefeac 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd @@ -7,301 +7,9 @@ 32 - Debug_Timer - No description available - 0x0 - - 0 - 0x0 - registers - - - - Debug_Timer_GLOBAL_ENABLE - PM.ACT.CFG - 0x400043A3 - 8 - read-write - 0 - 0 - - - en_timer - Enable timer/counters. - 0 - 3 - read-write - - - - - Debug_Timer_CONTROL - TMRx.CFG0 - 0x40004F00 - 8 - read-write - 0 - 0 - - - EN - Enables timer/comparator. - 0 - 0 - read-write - - - MODE - Mode. (0 = Timer; 1 = Comparator) - 1 - 1 - read-write - - - Timer - Timer mode. CNT/CMP register holds timer count value. - 0 - - - Comparator - Comparator mode. CNT/CMP register holds comparator threshold value. - 1 - - - - - ONESHOT - Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. - 2 - 2 - read-write - - - CMP_BUFF - Buffer compare register. Compare register updates only on timer terminal count. - 3 - 3 - read-write - - - INV - Invert sense of TIMEREN signal - 4 - 4 - read-write - - - DB - Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. - 5 - 5 - read-write - - - Timer - CMP and TC are output. - 0 - - - Deadband - PHI1 (instead of CMP) and PHI2 (instead of TC) are output. - 1 - - - - - DEADBAND_PERIOD - Deadband Period - 6 - 7 - read-write - - - - - Debug_Timer_CONTROL2 - TMRx.CFG1 - 0x40004F01 - 8 - read-write - 0 - 0 - - - IRQ_SEL - Irq selection. (0 = raw interrupts; 1 = status register interrupts) - 0 - 0 - read-write - - - FTC - First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. - 1 - 1 - read-write - - - Disable_FTC - Disable the single cycle pulse, which signifies the timer is starting. - 0 - - - Enable_FTC - Enable the single cycle pulse, which signifies the timer is starting. - 1 - - - - - DCOR - Disable Clear on Read (DCOR) of Status Register SR0. - 2 - 2 - read-write - - - DBMODE - Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). - 3 - 3 - read-write - - - CLK_BUS_EN_SEL - Digital Global Clock selection. - 4 - 6 - read-write - - - BUS_CLK_SEL - Bus Clock selection. - 7 - 7 - read-write - - - - - Debug_Timer_CONTROL3_ - TMRx.CFG2 - 0x40004F02 - 8 - read-write - 0 - 0 - - - TMR_CFG - Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ - 0 - 1 - read-write - - - Continuous - Timer runs while EN bit of CFG0 register is set to '1'. - 0 - - - Pulsewidth - Timer runs from positive to negative edge of TIMEREN. - 1 - - - Period - Timer runs from positive to positive edge of TIMEREN. - 2 - - - Irq - Timer runs until IRQ. - 3 - - - - - COD - Clear On Disable (COD). Clears or gates outputs to zero. - 2 - 2 - read-write - - - ROD - Reset On Disable (ROD). Resets internal state of output logic - 3 - 3 - read-write - - - CMP_CFG - Comparator configurations - 4 - 6 - read-write - - - Equal - Compare Equal - 0 - - - Less_than - Compare Less Than - 1 - - - Less_than_or_equal - Compare Less Than or Equal . - 2 - - - Greater - Compare Greater Than . - 3 - - - Greater_than_or_equal - Compare Greater Than or Equal - 4 - - - - - HW_EN - When set Timer Enable controls counting. - 7 - 7 - read-write - - - - - Debug_Timer_PERIOD - TMRx.PER0 - Assigned Period - 0x40004F04 - 16 - read-write - 0 - 0 - - - Debug_Timer_COUNTER - TMRx.CNT_CMP0 - Current Down Counter Value - 0x40004F06 - 16 - read-write - 0 - 0 - - - - - SCSI_Parity_Error + SCSI_Filtered No description available - 0x40006464 + 0x40006468 0 0x0 @@ -309,7 +17,7 @@ - SCSI_Parity_Error_STATUS_REG + SCSI_Filtered_STATUS_REG No description available 0x0 8 @@ -318,7 +26,7 @@ 0 - SCSI_Parity_Error_MASK_REG + SCSI_Filtered_MASK_REG No description available 0x20 8 @@ -327,7 +35,7 @@ 0 - SCSI_Parity_Error_STATUS_AUX_CTL_REG + SCSI_Filtered_STATUS_AUX_CTL_REG No description available 0x30 8 @@ -454,9 +162,9 @@ - SCSI_Filtered + SCSI_Parity_Error No description available - 0x40006461 + 0x40006469 0 0x0 @@ -464,7 +172,7 @@ - SCSI_Filtered_STATUS_REG + SCSI_Parity_Error_STATUS_REG No description available 0x0 8 @@ -473,7 +181,7 @@ 0 - SCSI_Filtered_MASK_REG + SCSI_Parity_Error_MASK_REG No description available 0x20 8 @@ -482,7 +190,7 @@ 0 - SCSI_Filtered_STATUS_AUX_CTL_REG + SCSI_Parity_Error_STATUS_AUX_CTL_REG No description available 0x30 8 @@ -608,10 +316,31 @@ + + SCSI_Glitch_Ctl + No description available + 0x4000647A + + 0 + 0x0 + registers + + + + SCSI_Glitch_Ctl_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_CTL_PHASE No description available - 0x40006471 + 0x40006472 0 0x0 @@ -699,39 +428,273 @@ 0 - PinState_DP + PinState_DP + No description available + 6 + 6 + read-only + + + PinState_DM + No description available + 7 + 7 + read-only + + + + + USBFS_PRT_DM0 + Port Drive Mode Register + 0x400051F2 + 8 + read-write + 0 + 0 + + + DriveMode_DP + No description available + 6 + 6 + read-write + + + DriveMode_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_DM1 + Port Drive Mode Register + 0x400051F3 + 8 + read-write + 0 + 0 + + + PullUp_en_DP + No description available + 6 + 6 + read-write + + + PullUp_en_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_INP_DIS + Input buffer disable override + 0x400051F8 + 8 + read-write + 0 + 0 + + + seinput_dis_dp + No description available + 6 + 6 + read-write + + + seinput_dis_dm + No description available + 7 + 7 + read-write + + + + + USBFS_EP0_DR0 + bmRequestType + 0x40006000 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR1 + bRequest + 0x40006001 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR2 + wValueLo + 0x40006002 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR3 + wValueHi + 0x40006003 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR4 + wIndexLo + 0x40006004 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR5 + wIndexHi + 0x40006005 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR6 + lengthLo + 0x40006006 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR7 + lengthHi + 0x40006007 + 8 + read-write + 0 + 0 + + + USBFS_CR0 + USB Control Register 0 + 0x40006008 + 8 + read-write + 0 + 0 + + + device_address + No description available + 0 + 6 + read-only + + + usb_enable + No description available + 7 + 7 + read-write + + + + + USBFS_CR1 + USB Control Register 1 + 0x40006009 + 8 + read-write + 0 + 0 + + + reg_enable + No description available + 0 + 0 + read-write + + + enable_lock + No description available + 1 + 1 + read-write + + + bus_activity + No description available + 2 + 2 + read-write + + + trim_offset_msb + No description available + 3 + 3 + read-write + + + + + USBFS_SIE_EP1_CR0 + The Endpoint1 Control Register + 0x4000600E + 8 + read-write + 0 + 0 + + + USBFS_USBIO_CR0 + USBIO Control Register 0 + 0x40006010 + 8 + read-write + 0 + 0 + + + rd No description available - 6 - 6 + 0 + 0 read-only - PinState_DM + td No description available - 7 - 7 - read-only + 5 + 5 + read-write - - - - USBFS_PRT_DM0 - Port Drive Mode Register - 0x400051F2 - 8 - read-write - 0 - 0 - - DriveMode_DP + tse0 No description available 6 6 read-write - DriveMode_DM + ten No description available 7 7 @@ -740,233 +703,316 @@ - USBFS_PRT_DM1 - Port Drive Mode Register - 0x400051F3 + USBFS_USBIO_CR1 + USBIO Control Register 1 + 0x40006012 8 read-write 0 0 - PullUp_en_DP + dmo No description available - 6 - 6 - read-write + 0 + 0 + read-only - PullUp_en_DM + dpo No description available - 7 - 7 - read-write + 1 + 1 + read-only - - - - USBFS_PRT_INP_DIS - Input buffer disable override - 0x400051F8 - 8 - read-write - 0 - 0 - - seinput_dis_dp + usbpuen No description available - 6 - 6 + 2 + 2 read-write - seinput_dis_dm + iomode No description available - 7 - 7 + 5 + 5 read-write - USBFS_EP0_DR0 - bmRequestType - 0x40006000 + USBFS_SIE_EP2_CR0 + The Endpoint2 Control Register + 0x4000601E 8 read-write 0 0 - USBFS_EP0_DR1 - bRequest - 0x40006001 + USBFS_SIE_EP3_CR0 + The Endpoint3 Control Register + 0x4000602E 8 read-write 0 0 - USBFS_EP0_DR2 - wValueLo - 0x40006002 + USBFS_SIE_EP4_CR0 + The Endpoint4 Control Register + 0x4000603E 8 read-write 0 0 - USBFS_EP0_DR3 - wValueHi - 0x40006003 + USBFS_SIE_EP5_CR0 + The Endpoint5 Control Register + 0x4000604E 8 read-write 0 0 - USBFS_EP0_DR4 - wIndexLo - 0x40006004 + USBFS_SIE_EP6_CR0 + The Endpoint6 Control Register + 0x4000605E 8 read-write 0 0 - USBFS_EP0_DR5 - wIndexHi - 0x40006005 + USBFS_SIE_EP7_CR0 + The Endpoint7 Control Register + 0x4000606E 8 read-write 0 0 - USBFS_EP0_DR6 - lengthLo - 0x40006006 + USBFS_SIE_EP8_CR0 + The Endpoint8 Control Register + 0x4000607E 8 read-write 0 0 - USBFS_EP0_DR7 - lengthHi - 0x40006007 + USBFS_BUF_SIZE + Dedicated Endpoint Buffer Size Register + 0x4000608C 8 read-write 0 0 - USBFS_CR0 - USB Control Register 0 - 0x40006008 + USBFS_EP_ACTIVE + Endpoint Active Indication Register + 0x4000608E + 8 + read-write + 0 + 0 + + + USBFS_EP_TYPE + Endpoint Type (IN/OUT) Indication + 0x4000608F + 8 + read-write + 0 + 0 + + + USBFS_USB_CLK_EN + USB Block Clock Enable Register + 0x4000609D + 8 + read-write + 0 + 0 + + + + + Debug_Timer + No description available + 0x0 + + 0 + 0x0 + registers + + + + Debug_Timer_GLOBAL_ENABLE + PM.ACT.CFG + 0x400043A3 8 read-write 0 0 - device_address - No description available + en_timer + Enable timer/counters. 0 - 6 - read-only - - - usb_enable - No description available - 7 - 7 + 3 read-write - USBFS_CR1 - USB Control Register 1 - 0x40006009 + Debug_Timer_CONTROL + TMRx.CFG0 + 0x40004F00 8 read-write 0 0 - reg_enable - No description available + EN + Enables timer/comparator. 0 0 read-write - enable_lock - No description available + MODE + Mode. (0 = Timer; 1 = Comparator) 1 1 read-write + + + Timer + Timer mode. CNT/CMP register holds timer count value. + 0 + + + Comparator + Comparator mode. CNT/CMP register holds comparator threshold value. + 1 + + - bus_activity - No description available + ONESHOT + Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. 2 2 read-write - trim_offset_msb - No description available + CMP_BUFF + Buffer compare register. Compare register updates only on timer terminal count. 3 3 read-write - - - - USBFS_SIE_EP1_CR0 - The Endpoint1 Control Register - 0x4000600E - 8 - read-write - 0 - 0 + + INV + Invert sense of TIMEREN signal + 4 + 4 + read-write + + + DB + Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. + 5 + 5 + read-write + + + Timer + CMP and TC are output. + 0 + + + Deadband + PHI1 (instead of CMP) and PHI2 (instead of TC) are output. + 1 + + + + + DEADBAND_PERIOD + Deadband Period + 6 + 7 + read-write + + - USBFS_USBIO_CR0 - USBIO Control Register 0 - 0x40006010 + Debug_Timer_CONTROL2 + TMRx.CFG1 + 0x40004F01 8 read-write 0 0 - rd - No description available + IRQ_SEL + Irq selection. (0 = raw interrupts; 1 = status register interrupts) 0 0 - read-only + read-write - td - No description available - 5 - 5 + FTC + First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. + 1 + 1 + read-write + + + Disable_FTC + Disable the single cycle pulse, which signifies the timer is starting. + 0 + + + Enable_FTC + Enable the single cycle pulse, which signifies the timer is starting. + 1 + + + + + DCOR + Disable Clear on Read (DCOR) of Status Register SR0. + 2 + 2 read-write - tse0 - No description available - 6 + DBMODE + Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). + 3 + 3 + read-write + + + CLK_BUS_EN_SEL + Digital Global Clock selection. + 4 6 read-write - ten - No description available + BUS_CLK_SEL + Bus Clock selection. 7 7 read-write @@ -974,139 +1020,114 @@ - USBFS_USBIO_CR1 - USBIO Control Register 1 - 0x40006012 + Debug_Timer_CONTROL3_ + TMRx.CFG2 + 0x40004F02 8 read-write 0 0 - dmo - No description available + TMR_CFG + Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ 0 - 0 - read-only - - - dpo - No description available - 1 1 - read-only + read-write + + + Continuous + Timer runs while EN bit of CFG0 register is set to '1'. + 0 + + + Pulsewidth + Timer runs from positive to negative edge of TIMEREN. + 1 + + + Period + Timer runs from positive to positive edge of TIMEREN. + 2 + + + Irq + Timer runs until IRQ. + 3 + + - usbpuen - No description available + COD + Clear On Disable (COD). Clears or gates outputs to zero. 2 2 read-write - iomode - No description available - 5 - 5 + ROD + Reset On Disable (ROD). Resets internal state of output logic + 3 + 3 + read-write + + + CMP_CFG + Comparator configurations + 4 + 6 + read-write + + + Equal + Compare Equal + 0 + + + Less_than + Compare Less Than + 1 + + + Less_than_or_equal + Compare Less Than or Equal . + 2 + + + Greater + Compare Greater Than . + 3 + + + Greater_than_or_equal + Compare Greater Than or Equal + 4 + + + + + HW_EN + When set Timer Enable controls counting. + 7 + 7 read-write - USBFS_SIE_EP2_CR0 - The Endpoint2 Control Register - 0x4000601E - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP3_CR0 - The Endpoint3 Control Register - 0x4000602E - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP4_CR0 - The Endpoint4 Control Register - 0x4000603E - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP5_CR0 - The Endpoint5 Control Register - 0x4000604E - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP6_CR0 - The Endpoint6 Control Register - 0x4000605E - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP7_CR0 - The Endpoint7 Control Register - 0x4000606E - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP8_CR0 - The Endpoint8 Control Register - 0x4000607E - 8 - read-write - 0 - 0 - - - USBFS_BUF_SIZE - Dedicated Endpoint Buffer Size Register - 0x4000608C - 8 - read-write - 0 - 0 - - - USBFS_EP_ACTIVE - Endpoint Active Indication Register - 0x4000608E - 8 - read-write - 0 - 0 - - - USBFS_EP_TYPE - Endpoint Type (IN/OUT) Indication - 0x4000608F - 8 + Debug_Timer_PERIOD + TMRx.PER0 - Assigned Period + 0x40004F04 + 16 read-write 0 0 - USBFS_USB_CLK_EN - USB Block Clock Enable Register - 0x4000609D - 8 + Debug_Timer_COUNTER + TMRx.CNT_CMP0 - Current Down Counter Value + 0x40004F06 + 16 read-write 0 0 @@ -1116,7 +1137,7 @@ SCSI_Out_Ctl No description available - 0x40006470 + 0x40006478 0 0x0 @@ -1137,7 +1158,7 @@ SCSI_Out_Bits No description available - 0x40006478 + 0x4000647B 0 0x0 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 1f62920b294957ce5e27997e418622d29893dcc6..9b51094089f7001b2e9f22e8e74236667e595046 100755 GIT binary patch literal 248124 zcmeFa37j2Ab?<-2Sj53LF@Zq94h)*cHrSG-(eBv7TD*b0V9AC6wvaRnd1DC! zfk4QEK!7A9{KJyX31lOLBoM$Bkc1b9H6ex`Fy#49Hj+mO*%V{H-?vWJ?dt8`?w%{n zNV+qh+qZ9Z)u~gbPMtdE)T!!MpLKF4{CjA`|9a|I=N;z9$^XN3-eJ;%>(uGr9=Tdc z>pFLK)^{d52Rb`DJ34!Gx4*Mcse3!S^}kms3p;B&Tl9R=rQg|Eqa52hH!J^bO1r_8 zpfq{MraL1Kb)tBlAgh8a^tH4z-dWOF)LASb+jO^}vs`yumAXLBmg&hV-ECFsGM6@~ zJWD#;-F1t;CzLv=>#5%n`ZPswzh7UwJDVK>`yJ|3KJw7Kd5498{>aBCPlOyPAi@pG zR)+}dg(HNyv$IjSg})ATu2SPCgypWz6}oP5_xroV0NaEZD+FYvGK{NX5MhBDKPfV- zbi`P$??sLns{~@3OIxaZD|Nq81e#O{NVCm|@d$(aIDJ8kZLZJub*@&4-O4-i(CMdt zTlM~6_xXN3IjAS}?yVx&K_i*+oSWpCP(L2%>{COwsG(Qr7yPiL+vD(wgF7}Ibj2pY z+n3=Y`hWEPGG;tUPXacyd-~y7dQhhyvdnnBnlYj3uh8d!8g!+a4*DgG2pev3%tr?; zb<|xYiY|9|+mte?yH)yMp?_o3<)ZdVG3ItX-KtXK`gV+%(EiB@-Jsf)LdB!AMo56h zoubyMr+z2s1#%j@>=ab!JJHSa_yiiG@D4TR8rAt?!6k=SJ7wlaIwBe~gNYHe0TDy? zt!8FV#2-)<0&b&ut48vqBO_#4AcloNurh4C%CRjZgqas8$1?q|(ywt5f6|TirAl=~ zJk8+xW^Wb2_Nx3X1r|O-8I8p~3&VzEhMzEdoJi4}cMx6MMCQF>?-!|6FVKG-C{@H; z=Y|Rc?EKECAm6F3UZT$1>V9Vh<;8lkP<1X8MfhGOiY;>a)@f+&5>~eg+GOWqG1a8* z4?5VpT#jq?8(QsD9naR&J39=(TXeU_<){3v&W-v{I&GUeV3EkbRM+LI3@%5oB5O

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pufA8*j>($G!X z2S6P9B!hk|9%u9^Hfqv70OHVd4f-RgSvQxu0f\n" << + " \n" << + " " << + (config.flags & CONFIG_ENABLE_SCSI2 ? "true" : "false") << + "\n" << + "\n" << "